From 173dd90528029d709737e64084dd989f52d0e45e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Hru=C5=A1ka?= Date: Sat, 18 Nov 2017 20:45:30 +0100 Subject: [PATCH] got the voc sensor to do something --- CMakeLists.txt | 228 +- Drivers/BME680/bme680.c | 1138 + Drivers/BME680/bme680.h | 225 + Drivers/BME680/bme680_defs.h | 512 + .../Src/stm32l0xx_hal_i2c.c | 13 + Inc/debug.h | 6 +- Inc/hw_i2c.h | 80 + Inc/main.h | 2 - Makefile | 292 + Middlewares/Third_Party/Lora/Core/lora.c | 26 +- Src/debug.c | 10 + Src/hw_i2c.c | 162 + Src/main.c | 203 +- Src/stm32l0xx_it.c | 1 + Src/voc_sensor.c | 197 + Src/voc_sensor.h | 15 + build/LoRaMac.d | 43 + build/LoRaMac.lst | 13841 ++++++++++++ build/LoRaMacCrypto.d | 31 + build/LoRaMacCrypto.lst | 1053 + build/Region.d | 34 + build/Region.lst | 2208 ++ build/RegionCommon.d | 35 + build/RegionCommon.lst | 1997 ++ build/RegionEU868.d | 51 + build/RegionEU868.lst | 4727 ++++ build/aes.d | 4 + build/aes.lst | 2834 +++ build/bees.bin | Bin 0 -> 56464 bytes build/bees.hex | 3535 +++ build/bees.map | 6414 ++++++ build/bme680.d | 6 + build/bme680.lst | 5480 +++++ build/cmac.d | 25 + build/cmac.lst | 844 + build/debug.d | 135 + build/debug.lst | 326 + build/delay.d | 141 + build/delay.lst | 199 + build/hw_gpio.d | 135 + build/hw_gpio.lst | 672 + build/hw_i2c.d | 141 + build/hw_i2c.lst | 486 + build/hw_rtc.d | 138 + build/hw_rtc.lst | 2705 +++ build/hw_spi.d | 135 + build/hw_spi.lst | 824 + build/lora.d | 155 + build/lora.lst | 2559 +++ build/low_power.d | 138 + build/low_power.lst | 657 + build/main.d | 171 + build/main.lst | 571 + build/startup_stm32l073xx.d | 1 + build/stm32l0xx_hal.d | 102 + build/stm32l0xx_hal.lst | 1522 ++ build/stm32l0xx_hal_adc.d | 103 + build/stm32l0xx_hal_adc.lst | 5657 +++++ build/stm32l0xx_hal_adc_ex.d | 103 + build/stm32l0xx_hal_adc_ex.lst | 924 + build/stm32l0xx_hal_comp.d | 103 + build/stm32l0xx_hal_comp.lst | 32 + build/stm32l0xx_hal_comp_ex.d | 103 + build/stm32l0xx_hal_comp_ex.lst | 32 + build/stm32l0xx_hal_cortex.d | 103 + build/stm32l0xx_hal_cortex.lst | 2621 +++ build/stm32l0xx_hal_crc.d | 103 + build/stm32l0xx_hal_crc.lst | 32 + build/stm32l0xx_hal_crc_ex.d | 103 + build/stm32l0xx_hal_crc_ex.lst | 32 + build/stm32l0xx_hal_cryp.d | 2 + build/stm32l0xx_hal_cryp.lst | 25 + build/stm32l0xx_hal_cryp_ex.d | 2 + build/stm32l0xx_hal_cryp_ex.lst | 25 + build/stm32l0xx_hal_dac.d | 103 + build/stm32l0xx_hal_dac.lst | 32 + build/stm32l0xx_hal_dac_ex.d | 103 + build/stm32l0xx_hal_dac_ex.lst | 32 + build/stm32l0xx_hal_dma.d | 103 + build/stm32l0xx_hal_dma.lst | 3299 +++ build/stm32l0xx_hal_firewall.d | 103 + build/stm32l0xx_hal_firewall.lst | 32 + build/stm32l0xx_hal_flash.d | 103 + build/stm32l0xx_hal_flash.lst | 1990 ++ build/stm32l0xx_hal_flash_ex.d | 103 + build/stm32l0xx_hal_flash_ex.lst | 3227 +++ build/stm32l0xx_hal_flash_ramfunc.d | 103 + build/stm32l0xx_hal_flash_ramfunc.lst | 1527 ++ build/stm32l0xx_hal_gpio.d | 103 + build/stm32l0xx_hal_gpio.lst | 1503 ++ build/stm32l0xx_hal_i2c.d | 105 + build/stm32l0xx_hal_i2c.lst | 17938 ++++++++++++++++ build/stm32l0xx_hal_i2c_ex.d | 103 + build/stm32l0xx_hal_i2c_ex.lst | 868 + build/stm32l0xx_hal_i2s.d | 103 + build/stm32l0xx_hal_i2s.lst | 32 + build/stm32l0xx_hal_irda.d | 103 + build/stm32l0xx_hal_irda.lst | 32 + build/stm32l0xx_hal_iwdg.d | 103 + build/stm32l0xx_hal_iwdg.lst | 457 + build/stm32l0xx_hal_lcd.d | 103 + build/stm32l0xx_hal_lcd.lst | 32 + build/stm32l0xx_hal_lptim.d | 103 + build/stm32l0xx_hal_lptim.lst | 32 + build/stm32l0xx_hal_msp.d | 147 + build/stm32l0xx_hal_msp.lst | 676 + build/stm32l0xx_hal_pcd.d | 103 + build/stm32l0xx_hal_pcd.lst | 32 + build/stm32l0xx_hal_pcd_ex.d | 103 + build/stm32l0xx_hal_pcd_ex.lst | 32 + build/stm32l0xx_hal_pwr.d | 103 + build/stm32l0xx_hal_pwr.lst | 2041 ++ build/stm32l0xx_hal_pwr_ex.d | 103 + build/stm32l0xx_hal_pwr_ex.lst | 539 + build/stm32l0xx_hal_rcc.d | 103 + build/stm32l0xx_hal_rcc.lst | 4313 ++++ build/stm32l0xx_hal_rcc_ex.d | 103 + build/stm32l0xx_hal_rcc_ex.lst | 3456 +++ build/stm32l0xx_hal_rng.d | 103 + build/stm32l0xx_hal_rng.lst | 32 + build/stm32l0xx_hal_rtc.d | 103 + build/stm32l0xx_hal_rtc.lst | 5279 +++++ build/stm32l0xx_hal_rtc_ex.d | 103 + build/stm32l0xx_hal_rtc_ex.lst | 5596 +++++ build/stm32l0xx_hal_smartcard.d | 103 + build/stm32l0xx_hal_smartcard.lst | 32 + build/stm32l0xx_hal_smartcard_ex.d | 103 + build/stm32l0xx_hal_smartcard_ex.lst | 32 + build/stm32l0xx_hal_smbus.d | 103 + build/stm32l0xx_hal_smbus.lst | 32 + build/stm32l0xx_hal_spi.d | 103 + build/stm32l0xx_hal_spi.lst | 8540 ++++++++ build/stm32l0xx_hal_tim.d | 103 + build/stm32l0xx_hal_tim.lst | 16567 ++++++++++++++ build/stm32l0xx_hal_tim_ex.d | 103 + build/stm32l0xx_hal_tim_ex.lst | 648 + build/stm32l0xx_hal_tsc.d | 103 + build/stm32l0xx_hal_tsc.lst | 32 + build/stm32l0xx_hal_uart.d | 103 + build/stm32l0xx_hal_uart.lst | 9536 ++++++++ build/stm32l0xx_hal_uart_ex.d | 103 + build/stm32l0xx_hal_uart_ex.lst | 1291 ++ build/stm32l0xx_hal_usart.d | 103 + build/stm32l0xx_hal_usart.lst | 32 + build/stm32l0xx_hal_wwdg.d | 103 + build/stm32l0xx_hal_wwdg.lst | 32 + build/stm32l0xx_hw.d | 142 + build/stm32l0xx_hw.lst | 1305 ++ build/stm32l0xx_it.d | 140 + build/stm32l0xx_it.lst | 1162 + build/stm32l0xx_ll_adc.d | 109 + build/stm32l0xx_ll_adc.lst | 5993 ++++++ build/stm32l0xx_ll_comp.d | 106 + build/stm32l0xx_ll_comp.lst | 1249 ++ build/stm32l0xx_ll_crc.d | 109 + build/stm32l0xx_ll_crc.lst | 574 + build/stm32l0xx_ll_crs.d | 109 + build/stm32l0xx_ll_crs.lst | 873 + build/stm32l0xx_ll_dac.d | 109 + build/stm32l0xx_ll_dac.lst | 2263 ++ build/stm32l0xx_ll_dma.d | 109 + build/stm32l0xx_ll_dma.lst | 3142 +++ build/stm32l0xx_ll_exti.d | 106 + build/stm32l0xx_ll_exti.lst | 1445 ++ build/stm32l0xx_ll_gpio.d | 109 + build/stm32l0xx_ll_gpio.lst | 2610 +++ build/stm32l0xx_ll_i2c.d | 109 + build/stm32l0xx_ll_i2c.lst | 3383 +++ build/stm32l0xx_ll_lptim.d | 109 + build/stm32l0xx_ll_lptim.lst | 1486 ++ build/stm32l0xx_ll_lpuart.d | 112 + build/stm32l0xx_ll_lpuart.lst | 2394 +++ build/stm32l0xx_ll_pwr.d | 109 + build/stm32l0xx_ll_pwr.lst | 876 + build/stm32l0xx_ll_rcc.d | 106 + build/stm32l0xx_ll_rcc.lst | 4950 +++++ build/stm32l0xx_ll_rng.d | 109 + build/stm32l0xx_ll_rng.lst | 549 + build/stm32l0xx_ll_rtc.d | 109 + build/stm32l0xx_ll_rtc.lst | 6985 ++++++ build/stm32l0xx_ll_spi.d | 112 + build/stm32l0xx_ll_spi.lst | 3709 ++++ build/stm32l0xx_ll_tim.d | 109 + build/stm32l0xx_ll_tim.lst | 6609 ++++++ build/stm32l0xx_ll_usart.d | 112 + build/stm32l0xx_ll_usart.lst | 3748 ++++ build/stm32l0xx_ll_utils.d | 115 + build/stm32l0xx_ll_utils.lst | 5059 +++++ build/sx1272.d | 156 + build/sx1272.lst | 9945 +++++++++ build/sx1272mb2das.d | 150 + build/sx1272mb2das.lst | 925 + build/system_stm32l0xx.d | 102 + build/system_stm32l0xx.lst | 674 + build/timeServer.d | 141 + build/timeServer.lst | 1694 ++ build/utilities.d | 19 + build/utilities.lst | 479 + build/vcom.d | 137 + build/vcom.lst | 1441 ++ build/voc_sensor.d | 147 + build/voc_sensor.lst | 741 + 202 files changed, 241301 insertions(+), 20 deletions(-) create mode 100644 Drivers/BME680/bme680.c create mode 100644 Drivers/BME680/bme680.h create mode 100644 Drivers/BME680/bme680_defs.h create mode 100644 Inc/hw_i2c.h create mode 100644 Makefile create mode 100644 Src/hw_i2c.c create mode 100644 Src/voc_sensor.c create mode 100644 Src/voc_sensor.h create mode 100644 build/LoRaMac.d create mode 100644 build/LoRaMac.lst create mode 100644 build/LoRaMacCrypto.d create mode 100644 build/LoRaMacCrypto.lst create mode 100644 build/Region.d create mode 100644 build/Region.lst create mode 100644 build/RegionCommon.d create mode 100644 build/RegionCommon.lst create mode 100644 build/RegionEU868.d create mode 100644 build/RegionEU868.lst create mode 100644 build/aes.d create mode 100644 build/aes.lst create mode 100755 build/bees.bin create mode 100644 build/bees.hex create mode 100644 build/bees.map create mode 100644 build/bme680.d create mode 100644 build/bme680.lst create mode 100644 build/cmac.d create mode 100644 build/cmac.lst create mode 100644 build/debug.d create mode 100644 build/debug.lst create mode 100644 build/delay.d create mode 100644 build/delay.lst create mode 100644 build/hw_gpio.d create mode 100644 build/hw_gpio.lst create mode 100644 build/hw_i2c.d create mode 100644 build/hw_i2c.lst create mode 100644 build/hw_rtc.d create mode 100644 build/hw_rtc.lst create mode 100644 build/hw_spi.d create mode 100644 build/hw_spi.lst create mode 100644 build/lora.d create mode 100644 build/lora.lst create mode 100644 build/low_power.d create mode 100644 build/low_power.lst create mode 100644 build/main.d create mode 100644 build/main.lst create mode 100644 build/startup_stm32l073xx.d create mode 100644 build/stm32l0xx_hal.d create mode 100644 build/stm32l0xx_hal.lst create mode 100644 build/stm32l0xx_hal_adc.d create mode 100644 build/stm32l0xx_hal_adc.lst create mode 100644 build/stm32l0xx_hal_adc_ex.d create mode 100644 build/stm32l0xx_hal_adc_ex.lst create mode 100644 build/stm32l0xx_hal_comp.d create mode 100644 build/stm32l0xx_hal_comp.lst create mode 100644 build/stm32l0xx_hal_comp_ex.d create mode 100644 build/stm32l0xx_hal_comp_ex.lst create mode 100644 build/stm32l0xx_hal_cortex.d create mode 100644 build/stm32l0xx_hal_cortex.lst create mode 100644 build/stm32l0xx_hal_crc.d create mode 100644 build/stm32l0xx_hal_crc.lst create mode 100644 build/stm32l0xx_hal_crc_ex.d create mode 100644 build/stm32l0xx_hal_crc_ex.lst create mode 100644 build/stm32l0xx_hal_cryp.d create mode 100644 build/stm32l0xx_hal_cryp.lst create mode 100644 build/stm32l0xx_hal_cryp_ex.d create mode 100644 build/stm32l0xx_hal_cryp_ex.lst create mode 100644 build/stm32l0xx_hal_dac.d create mode 100644 build/stm32l0xx_hal_dac.lst create mode 100644 build/stm32l0xx_hal_dac_ex.d create mode 100644 build/stm32l0xx_hal_dac_ex.lst create mode 100644 build/stm32l0xx_hal_dma.d create mode 100644 build/stm32l0xx_hal_dma.lst create mode 100644 build/stm32l0xx_hal_firewall.d create mode 100644 build/stm32l0xx_hal_firewall.lst create mode 100644 build/stm32l0xx_hal_flash.d create mode 100644 build/stm32l0xx_hal_flash.lst create mode 100644 build/stm32l0xx_hal_flash_ex.d create mode 100644 build/stm32l0xx_hal_flash_ex.lst create mode 100644 build/stm32l0xx_hal_flash_ramfunc.d create mode 100644 build/stm32l0xx_hal_flash_ramfunc.lst create mode 100644 build/stm32l0xx_hal_gpio.d create mode 100644 build/stm32l0xx_hal_gpio.lst create mode 100644 build/stm32l0xx_hal_i2c.d create mode 100644 build/stm32l0xx_hal_i2c.lst create mode 100644 build/stm32l0xx_hal_i2c_ex.d create mode 100644 build/stm32l0xx_hal_i2c_ex.lst create mode 100644 build/stm32l0xx_hal_i2s.d create mode 100644 build/stm32l0xx_hal_i2s.lst create mode 100644 build/stm32l0xx_hal_irda.d create mode 100644 build/stm32l0xx_hal_irda.lst create mode 100644 build/stm32l0xx_hal_iwdg.d create mode 100644 build/stm32l0xx_hal_iwdg.lst create mode 100644 build/stm32l0xx_hal_lcd.d create mode 100644 build/stm32l0xx_hal_lcd.lst create mode 100644 build/stm32l0xx_hal_lptim.d create mode 100644 build/stm32l0xx_hal_lptim.lst create mode 100644 build/stm32l0xx_hal_msp.d create mode 100644 build/stm32l0xx_hal_msp.lst create mode 100644 build/stm32l0xx_hal_pcd.d create mode 100644 build/stm32l0xx_hal_pcd.lst create mode 100644 build/stm32l0xx_hal_pcd_ex.d create mode 100644 build/stm32l0xx_hal_pcd_ex.lst create mode 100644 build/stm32l0xx_hal_pwr.d create mode 100644 build/stm32l0xx_hal_pwr.lst create mode 100644 build/stm32l0xx_hal_pwr_ex.d create mode 100644 build/stm32l0xx_hal_pwr_ex.lst create mode 100644 build/stm32l0xx_hal_rcc.d create mode 100644 build/stm32l0xx_hal_rcc.lst create mode 100644 build/stm32l0xx_hal_rcc_ex.d create mode 100644 build/stm32l0xx_hal_rcc_ex.lst create mode 100644 build/stm32l0xx_hal_rng.d create mode 100644 build/stm32l0xx_hal_rng.lst create mode 100644 build/stm32l0xx_hal_rtc.d create mode 100644 build/stm32l0xx_hal_rtc.lst create mode 100644 build/stm32l0xx_hal_rtc_ex.d create mode 100644 build/stm32l0xx_hal_rtc_ex.lst create mode 100644 build/stm32l0xx_hal_smartcard.d create mode 100644 build/stm32l0xx_hal_smartcard.lst create mode 100644 build/stm32l0xx_hal_smartcard_ex.d create mode 100644 build/stm32l0xx_hal_smartcard_ex.lst create mode 100644 build/stm32l0xx_hal_smbus.d create mode 100644 build/stm32l0xx_hal_smbus.lst create mode 100644 build/stm32l0xx_hal_spi.d create mode 100644 build/stm32l0xx_hal_spi.lst create mode 100644 build/stm32l0xx_hal_tim.d create mode 100644 build/stm32l0xx_hal_tim.lst create mode 100644 build/stm32l0xx_hal_tim_ex.d create mode 100644 build/stm32l0xx_hal_tim_ex.lst create mode 100644 build/stm32l0xx_hal_tsc.d create mode 100644 build/stm32l0xx_hal_tsc.lst create mode 100644 build/stm32l0xx_hal_uart.d create mode 100644 build/stm32l0xx_hal_uart.lst create mode 100644 build/stm32l0xx_hal_uart_ex.d create mode 100644 build/stm32l0xx_hal_uart_ex.lst create mode 100644 build/stm32l0xx_hal_usart.d create mode 100644 build/stm32l0xx_hal_usart.lst create mode 100644 build/stm32l0xx_hal_wwdg.d create mode 100644 build/stm32l0xx_hal_wwdg.lst create mode 100644 build/stm32l0xx_hw.d create mode 100644 build/stm32l0xx_hw.lst create mode 100644 build/stm32l0xx_it.d create mode 100644 build/stm32l0xx_it.lst create mode 100644 build/stm32l0xx_ll_adc.d create mode 100644 build/stm32l0xx_ll_adc.lst create mode 100644 build/stm32l0xx_ll_comp.d create mode 100644 build/stm32l0xx_ll_comp.lst create mode 100644 build/stm32l0xx_ll_crc.d create mode 100644 build/stm32l0xx_ll_crc.lst create mode 100644 build/stm32l0xx_ll_crs.d create mode 100644 build/stm32l0xx_ll_crs.lst create mode 100644 build/stm32l0xx_ll_dac.d create mode 100644 build/stm32l0xx_ll_dac.lst create mode 100644 build/stm32l0xx_ll_dma.d create mode 100644 build/stm32l0xx_ll_dma.lst create mode 100644 build/stm32l0xx_ll_exti.d create mode 100644 build/stm32l0xx_ll_exti.lst create mode 100644 build/stm32l0xx_ll_gpio.d create mode 100644 build/stm32l0xx_ll_gpio.lst create mode 100644 build/stm32l0xx_ll_i2c.d create mode 100644 build/stm32l0xx_ll_i2c.lst create mode 100644 build/stm32l0xx_ll_lptim.d create mode 100644 build/stm32l0xx_ll_lptim.lst create mode 100644 build/stm32l0xx_ll_lpuart.d create mode 100644 build/stm32l0xx_ll_lpuart.lst create mode 100644 build/stm32l0xx_ll_pwr.d create mode 100644 build/stm32l0xx_ll_pwr.lst create mode 100644 build/stm32l0xx_ll_rcc.d create mode 100644 build/stm32l0xx_ll_rcc.lst create mode 100644 build/stm32l0xx_ll_rng.d create mode 100644 build/stm32l0xx_ll_rng.lst create mode 100644 build/stm32l0xx_ll_rtc.d create mode 100644 build/stm32l0xx_ll_rtc.lst create mode 100644 build/stm32l0xx_ll_spi.d create mode 100644 build/stm32l0xx_ll_spi.lst create mode 100644 build/stm32l0xx_ll_tim.d create mode 100644 build/stm32l0xx_ll_tim.lst create mode 100644 build/stm32l0xx_ll_usart.d create mode 100644 build/stm32l0xx_ll_usart.lst create mode 100644 build/stm32l0xx_ll_utils.d create mode 100644 build/stm32l0xx_ll_utils.lst create mode 100644 build/sx1272.d create mode 100644 build/sx1272.lst create mode 100644 build/sx1272mb2das.d create mode 100644 build/sx1272mb2das.lst create mode 100644 build/system_stm32l0xx.d create mode 100644 build/system_stm32l0xx.lst create mode 100644 build/timeServer.d create mode 100644 build/timeServer.lst create mode 100644 build/utilities.d create mode 100644 build/utilities.lst create mode 100644 build/vcom.d create mode 100644 build/vcom.lst create mode 100644 build/voc_sensor.d create mode 100644 build/voc_sensor.lst diff --git a/CMakeLists.txt b/CMakeLists.txt index c380a0a..61dea8b 100755 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,7 +3,7 @@ project(proj) set(CMAKE_CXX_STANDARD 11) -add_definitions(-DSTM32L073xx) +add_definitions(-DSTM32L073xx -DUSE_FULL_LL_DRIVER) set(SOURCE_FILES Src/system_stm32l0xx.c @@ -79,6 +79,7 @@ set(SOURCE_FILES Inc/hw_gpio.h Inc/hw_msp.h Inc/hw_rtc.h + Inc/hw_i2c.h Inc/hw_spi.h Inc/stm32l0xx_hw_conf.h Inc/vcom.h @@ -87,6 +88,7 @@ set(SOURCE_FILES Src/hw_gpio.c Src/hw_rtc.c Src/hw_spi.c + Src/hw_i2c.c Src/stm32l0xx_hw.c Src/vcom.c Src/stm32l0xx_hal_msp.c @@ -143,13 +145,233 @@ set(SOURCE_FILES Middlewares/Third_Party/Lora/Utilities/timeServer.h Middlewares/Third_Party/Lora/Utilities/low_power.c Middlewares/Third_Party/Lora/Utilities/delay.c - ) + ./Drivers/CMSIS/Include/cmsis_gcc.h + ./Drivers/CMSIS/Include/core_sc000.h + ./Drivers/CMSIS/Include/core_cm7.h + ./Drivers/CMSIS/Include/core_cm0.h + ./Drivers/CMSIS/Include/cmsis_armcc_V6.h + ./Drivers/CMSIS/Include/arm_math.h + ./Drivers/CMSIS/Include/core_sc300.h + ./Drivers/CMSIS/Include/core_cmInstr.h + ./Drivers/CMSIS/Include/cmsis_armcc.h + ./Drivers/CMSIS/Include/core_cmSimd.h + ./Drivers/CMSIS/Include/core_cm0plus.h + ./Drivers/CMSIS/Include/core_cm4.h + ./Drivers/CMSIS/Include/arm_common_tables.h + ./Drivers/CMSIS/Include/core_cm3.h + ./Drivers/CMSIS/Include/core_cmFunc.h + ./Drivers/CMSIS/Include/arm_const_structs.h + ./Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h + ./Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h + ./Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h + ./Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h + ./Drivers/BSP/sx1272mb2das/sx1272mb2das.h + ./Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h + ./Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h + ./Drivers/BSP/Components/sx1272/sx1272.h + ./junk/stm32l0xx_hal_conf.h + ./junk/usart.h + ./junk/rtc.h + ./junk/stm32l0xx_it.h + ./junk/i2c.h + ./junk/spi.h + ./junk/gpio.h + ./Inc/hw_gpio.h + ./Inc/stm32l0xx_hal_conf.h + ./Inc/Commissioning.h + ./Inc/hw.h + ./Inc/stm32l0xx_hw_conf.h + ./Inc/stm32l0xx_it.h + ./Inc/hw_spi.h + ./Inc/debug.h + ./Inc/hw_conf.h + ./Inc/vcom.h + ./Inc/main.h + ./Inc/hw_rtc.h + ./Inc/hw_i2c.h + ./Inc/hw_msp.h + ./Middlewares/Third_Party/Lora/Core/lora_mac_version.h + ./Middlewares/Third_Party/Lora/Core/lora.h + ./Middlewares/Third_Party/Lora/Crypto/cmac.h + ./Middlewares/Third_Party/Lora/Crypto/aes.h + ./Middlewares/Third_Party/Lora/Phy/radio.h + ./Middlewares/Third_Party/Lora/Conf/Commissioning_template.h + ./Middlewares/Third_Party/Lora/Conf/Inc/hw_gpio_template.h + ./Middlewares/Third_Party/Lora/Conf/Inc/hw_template.h + ./Middlewares/Third_Party/Lora/Conf/Inc/hw_rtc_template.h + ./Middlewares/Third_Party/Lora/Conf/Inc/hw_spi_template.h + ./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h + ./Middlewares/Third_Party/Lora/Mac/timer.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionUS915-Hybrid.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionUS915.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionCN470.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionKR920.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionAU915.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionCN779.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionIN865.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionAS923.h + ./Middlewares/Third_Party/Lora/Mac/region/Region.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionEU433.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h + ./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h + ./Middlewares/Third_Party/Lora/Mac/LoRaMac.h + ./Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h + ./Middlewares/Third_Party/Lora/Utilities/utilities.h + ./Middlewares/Third_Party/Lora/Utilities/delay.h + ./Middlewares/Third_Party/Lora/Utilities/timeServer.h + ./Middlewares/Third_Party/Lora/Utilities/low_power.h + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template-c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c + Drivers/BME680/bme680.c + Drivers/BME680/bme680.h + Drivers/BME680/bme680_defs.h + Src/voc_sensor.c + Src/voc_sensor.h) include_directories(Drivers/CMSIS/Device/ST/STM32L0xx/Include) include_directories(Drivers/CMSIS/Include) include_directories(Drivers/STM32L0xx_HAL_Driver/Inc) include_directories(Drivers/STM32L0xx_HAL_Driver/Inc/Legacy) -include_directories(Inc +include_directories( + Inc Middlewares/Third_Party/Lora/Core Middlewares/Third_Party/Lora/Crypto Middlewares/Third_Party/Lora/Mac diff --git a/Drivers/BME680/bme680.c b/Drivers/BME680/bme680.c new file mode 100644 index 0000000..b457dac --- /dev/null +++ b/Drivers/BME680/bme680.c @@ -0,0 +1,1138 @@ +/**\mainpage + * Copyright (C) 2017 - 2018 Bosch Sensortec GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holder nor the names of the + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + * The information provided is believed to be accurate and reliable. + * The copyright holder assumes no responsibility + * for the consequences of use + * of such information nor for any infringement of patents or + * other rights of third parties which may result from its use. + * No license is granted by implication or otherwise under any patent or + * patent rights of the copyright holder. + * + * File bme680.c + * @date 30 Oct 2017 + * @version 3.5.3 + * + */ + +/*! @file bme680.c + @brief Sensor driver for BME680 sensor */ +#include "bme680.h" + +/**static variables */ +/**Look up table for the possible gas range values */ +uint32_t lookupTable1[16] = { UINT32_C(2147483647), UINT32_C(2147483647), UINT32_C(2147483647), UINT32_C(2147483647), + UINT32_C(2147483647), UINT32_C(2126008810), UINT32_C(2147483647), UINT32_C(2130303777), UINT32_C(2147483647), + UINT32_C(2147483647), UINT32_C(2143188679), UINT32_C(2136746228), UINT32_C(2147483647), UINT32_C(2126008810), + UINT32_C(2147483647), UINT32_C(2147483647) }; +/**Look up table for the possible gas range values */ +uint32_t lookupTable2[16] = { UINT32_C(4096000000), UINT32_C(2048000000), UINT32_C(1024000000), UINT32_C(512000000), + UINT32_C(255744255), UINT32_C(127110228), UINT32_C(64000000), UINT32_C(32258064), UINT32_C(16016016), UINT32_C( + 8000000), UINT32_C(4000000), UINT32_C(2000000), UINT32_C(1000000), UINT32_C(500000), UINT32_C(250000), + UINT32_C(125000) }; + +/*! + * @brief This internal API is used to read the calibrated data from the sensor. + * + * This function is used to retrieve the calibration + * data from the image registers of the sensor. + * + * @note Registers 89h to A1h for calibration data 1 to 24 + * from bit 0 to 7 + * @note Registers E1h to F0h for calibration data 25 to 40 + * from bit 0 to 7 + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status. + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t get_calib_data(struct bme680_dev *dev); + +/*! + * @brief This internal API is used to set the gas configuration of the sensor. + * + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status. + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t set_gas_config(struct bme680_dev *dev); + +/*! + * @brief This internal API is used to get the gas configuration of the sensor. + * + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status. + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t get_gas_config(struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the Heat duration value. + * + * @param[in] dur :Value of the duration to be shared. + * + * @return uint8_t threshold duration after calculation. + */ +static uint8_t calc_heater_dur(uint16_t dur); + +/*! + * @brief This internal API is used to calculate the temperature value. + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] temp_adc :Contains the temperature ADC value . + * + * @return uint32_t calculated temperature. + */ +static int16_t calc_temperature(uint32_t temp_adc, struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the pressure value. + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] pres_adc :Contains the pressure ADC value . + * + * @return uint32_t calculated pressure. + */ +static uint32_t calc_pressure(uint32_t pres_adc, const struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the humidity value. + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] hum_adc :Contains the humidity ADC value. + * + * @return uint32_t calculated humidity. + */ +static uint32_t calc_humidity(uint16_t hum_adc, const struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the Gas Resistance value. + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] gas_res_adc :Contains the Gas Resistance ADC value. + * @param[in] gas_range :Contains the range of gas values. + * + * @return uint32_t calculated gas resistance. + */ +static uint32_t calc_gas_resistance(uint16_t gas_res_adc, uint8_t gas_range, const struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the Heat Resistance value. + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] temp :Contains the temporary value. + * + * @return uint8_t calculated heater resistance. + */ +static uint8_t calc_heater_res(uint16_t temp, const struct bme680_dev *dev); + +/*! + * @brief This internal API is used to calculate the field data of sensor. + * + * @param[out] data :Structure instance to hold the data + * @param[in] dev :Structure instance of bme680_dev. + * + * @return int8_t result of the field data from sensor. + */ +static int8_t read_field_data(struct bme680_field_data *data, struct bme680_dev *dev); + +/*! + * @brief This internal API is used to set the memory page + * based on register address. + * + * The value of memory page + * value | Description + * --------|-------------- + * 0 | BME680_PAGE0_SPI + * 1 | BME680_PAGE1_SPI + * + * @param[in] dev :Structure instance of bme680_dev. + * @param[in] reg_addr :Contains the register address array. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t set_mem_page(uint8_t reg_addr, struct bme680_dev *dev); + +/*! + * @brief This internal API is used to get the memory page based + * on register address. + * + * The value of memory page + * value | Description + * --------|-------------- + * 0 | BME680_PAGE0_SPI + * 1 | BME680_PAGE1_SPI + * + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t get_mem_page(struct bme680_dev *dev); + +/*! + * @brief This internal API is used to validate the device pointer for + * null conditions. + * + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t null_ptr_check(const struct bme680_dev *dev); + +/*! + * @brief This internal API is used to check the boundary + * conditions. + * + * @param[in] value :pointer to the value. + * @param[in] min :minimum value. + * @param[in] max :maximum value. + * @param[in] dev :Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +static int8_t boundary_check(uint8_t *value, uint8_t min, uint8_t max, struct bme680_dev *dev); + +/****************** Global Function Definitions *******************************/ +/*! + *@brief This API is the entry point. + *It reads the chip-id and calibration data from the sensor. + */ +int8_t bme680_init(struct bme680_dev *dev) +{ + int8_t rslt; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + /* Soft reset to restore it to default values*/ + rslt = bme680_soft_reset(dev); + if (rslt == BME680_OK) { + rslt = bme680_get_regs(BME680_CHIP_ID_ADDR, &dev->chip_id, 1, dev); + if (rslt == BME680_OK) { + if (dev->chip_id == BME680_CHIP_ID) { + /* Get the Calibration data */ + rslt = get_calib_data(dev); + } else { + rslt = BME680_E_DEV_NOT_FOUND; + } + } + } + } + + return rslt; +} + +/*! + * @brief This API reads the data from the given register address of the sensor. + */ +int8_t bme680_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bme680_dev *dev) +{ + int8_t rslt; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if (dev->intf == BME680_SPI_INTF) { + /* Set the memory page */ + rslt = set_mem_page(reg_addr, dev); + if (rslt == BME680_OK) + reg_addr = reg_addr | BME680_SPI_RD_MSK; + } + dev->com_rslt = dev->read(dev->dev_id, reg_addr, reg_data, len); + if (dev->com_rslt != 0) + rslt = BME680_E_COM_FAIL; + } + + return rslt; +} + +/*! + * @brief This API writes the given data to the register address + * of the sensor. + */ +int8_t bme680_set_regs(const uint8_t *reg_addr, const uint8_t *reg_data, uint8_t len, struct bme680_dev *dev) +{ + int8_t rslt; + /* Length of the temporary buffer is 2*(length of register)*/ + uint8_t tmp_buff[BME680_TMP_BUFFER_LENGTH] = { 0 }; + uint16_t index; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if ((len > 0) && (len < BME680_TMP_BUFFER_LENGTH / 2)) { + /* Interleave the 2 arrays */ + for (index = 0; index < len; index++) { + if (dev->intf == BME680_SPI_INTF) { + /* Set the memory page */ + rslt = set_mem_page(reg_addr[index], dev); + tmp_buff[(2 * index)] = reg_addr[index] & BME680_SPI_WR_MSK; + } else { + tmp_buff[(2 * index)] = reg_addr[index]; + } + tmp_buff[(2 * index) + 1] = reg_data[index]; + } + /* Write the interleaved array */ + if (rslt == BME680_OK) { + dev->com_rslt = dev->write(dev->dev_id, tmp_buff[0], &tmp_buff[1], (2 * len) - 1); + if (dev->com_rslt != 0) + rslt = BME680_E_COM_FAIL; + } + } else { + rslt = BME680_E_INVALID_LENGTH; + } + } + + return rslt; +} + +/*! + * @brief This API performs the soft reset of the sensor. + */ +int8_t bme680_soft_reset(struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t reg_addr = BME680_SOFT_RESET_ADDR; + /* 0xb6 is the soft reset command */ + uint8_t soft_rst_cmd = BME680_SOFT_RESET_CMD; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if (dev->intf == BME680_SPI_INTF) + rslt = get_mem_page(dev); + + /* Reset the device */ + if (rslt == BME680_OK) { + rslt = bme680_set_regs(®_addr, &soft_rst_cmd, 1, dev); + /* Wait for 5ms */ + dev->delay_ms(BME680_RESET_PERIOD); + + if (rslt == BME680_OK) { + /* After reset get the memory page */ + if (dev->intf == BME680_SPI_INTF) + rslt = get_mem_page(dev); + } + } + } + + return rslt; +} + +/*! + * @brief This API is used to set the oversampling, filter and T,P,H, gas selection + * settings in the sensor. + */ +int8_t bme680_set_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t reg_addr; + uint8_t data = 0; + uint8_t count = 0; + uint8_t reg_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + uint8_t intended_power_mode = dev->power_mode; /* Save intended power mode */ + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if (desired_settings & BME680_GAS_MEAS_SEL) + rslt = set_gas_config(dev); + + dev->power_mode = BME680_SLEEP_MODE; + if (rslt == BME680_OK) + rslt = bme680_set_sensor_mode(dev); + + /* Selecting the filter */ + if (desired_settings & BME680_FILTER_SEL) { + rslt = boundary_check(&dev->tph_sett.filter, BME680_FILTER_SIZE_0, BME680_FILTER_SIZE_127, dev); + reg_addr = BME680_CONF_ODR_FILT_ADDR; + + if (rslt == BME680_OK) + rslt = bme680_get_regs(reg_addr, &data, 1, dev); + + if (desired_settings & BME680_FILTER_SEL) + data = BME680_SET_BITS(data, BME680_FILTER, dev->tph_sett.filter); + + reg_array[count] = reg_addr; /* Append configuration */ + data_array[count] = data; + count++; + } + + /* Selecting heater control for the sensor */ + if (desired_settings & BME680_HCNTRL_SEL) { + rslt = boundary_check(&dev->gas_sett.heatr_ctrl, BME680_ENABLE_HEATER, + BME680_DISABLE_HEATER, dev); + reg_addr = BME680_CONF_HEAT_CTRL_ADDR; + + if (rslt == BME680_OK) + rslt = bme680_get_regs(reg_addr, &data, 1, dev); + data = BME680_SET_BITS_POS_0(data, BME680_HCTRL, dev->gas_sett.heatr_ctrl); + + reg_array[count] = reg_addr; /* Append configuration */ + data_array[count] = data; + count++; + } + + /* Selecting heater T,P oversampling for the sensor */ + if (desired_settings & (BME680_OST_SEL | BME680_OSP_SEL)) { + rslt = boundary_check(&dev->tph_sett.os_temp, BME680_OS_NONE, BME680_OS_16X, dev); + reg_addr = BME680_CONF_T_P_MODE_ADDR; + + if (rslt == BME680_OK) + rslt = bme680_get_regs(reg_addr, &data, 1, dev); + + if (desired_settings & BME680_OST_SEL) + data = BME680_SET_BITS(data, BME680_OST, dev->tph_sett.os_temp); + + if (desired_settings & BME680_OSP_SEL) + data = BME680_SET_BITS(data, BME680_OSP, dev->tph_sett.os_pres); + + reg_array[count] = reg_addr; + data_array[count] = data; + count++; + } + + /* Selecting humidity oversampling for the sensor */ + if (desired_settings & BME680_OSH_SEL) { + rslt = boundary_check(&dev->tph_sett.os_hum, BME680_OS_NONE, BME680_OS_16X, dev); + reg_addr = BME680_CONF_OS_H_ADDR; + + if (rslt == BME680_OK) + rslt = bme680_get_regs(reg_addr, &data, 1, dev); + data = BME680_SET_BITS_POS_0(data, BME680_OSH, dev->tph_sett.os_hum); + + reg_array[count] = reg_addr; /* Append configuration */ + data_array[count] = data; + count++; + } + + /* Selecting the runGas and NB conversion settings for the sensor */ + if (desired_settings & (BME680_RUN_GAS_SEL | BME680_NBCONV_SEL)) { + rslt = boundary_check(&dev->gas_sett.run_gas, BME680_RUN_GAS_DISABLE, + BME680_RUN_GAS_ENABLE, dev); + if (rslt == BME680_OK) { + /* Validate boundary conditions */ + rslt = boundary_check(&dev->gas_sett.nb_conv, BME680_NBCONV_MIN, + BME680_NBCONV_MAX, dev); + } + + reg_addr = BME680_CONF_ODR_RUN_GAS_NBC_ADDR; + + if (rslt == BME680_OK) + rslt = bme680_get_regs(reg_addr, &data, 1, dev); + + if (desired_settings & BME680_RUN_GAS_SEL) + data = BME680_SET_BITS(data, BME680_RUN_GAS, dev->gas_sett.run_gas); + + if (desired_settings & BME680_NBCONV_SEL) + data = BME680_SET_BITS_POS_0(data, BME680_NBCONV, dev->gas_sett.nb_conv); + + reg_array[count] = reg_addr; /* Append configuration */ + data_array[count] = data; + count++; + } + + if (rslt == BME680_OK) + rslt = bme680_set_regs(reg_array, data_array, count, dev); + + /* Restore previous intended power mode */ + dev->power_mode = intended_power_mode; + } + + return rslt; +} + +/*! + * @brief This API is used to get the oversampling, filter and T,P,H, gas selection + * settings in the sensor. + */ +int8_t bme680_get_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev) +{ + int8_t rslt; + /* starting address of the register array for burst read*/ + uint8_t reg_addr = BME680_CONF_HEAT_CTRL_ADDR; + uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + rslt = bme680_get_regs(reg_addr, data_array, BME680_REG_BUFFER_LENGTH, dev); + + if (rslt == BME680_OK) { + if (desired_settings & BME680_GAS_MEAS_SEL) + rslt = get_gas_config(dev); + + /* get the T,P,H ,Filter,ODR settings here */ + if (desired_settings & BME680_FILTER_SEL) + dev->tph_sett.filter = BME680_GET_BITS(data_array[BME680_REG_FILTER_INDEX], + BME680_FILTER); + + if (desired_settings & (BME680_OST_SEL | BME680_OSP_SEL)) { + dev->tph_sett.os_temp = BME680_GET_BITS(data_array[BME680_REG_TEMP_INDEX], BME680_OST); + dev->tph_sett.os_pres = BME680_GET_BITS(data_array[BME680_REG_PRES_INDEX], BME680_OSP); + } + + if (desired_settings & BME680_OSH_SEL) + dev->tph_sett.os_hum = BME680_GET_BITS_POS_0(data_array[BME680_REG_HUM_INDEX], + BME680_OSH); + + /* get the gas related settings */ + if (desired_settings & BME680_HCNTRL_SEL) + dev->gas_sett.heatr_ctrl = BME680_GET_BITS_POS_0(data_array[BME680_REG_HCTRL_INDEX], + BME680_HCTRL); + + if (desired_settings & (BME680_RUN_GAS_SEL | BME680_NBCONV_SEL)) { + dev->gas_sett.nb_conv = BME680_GET_BITS_POS_0(data_array[BME680_REG_NBCONV_INDEX], + BME680_NBCONV); + dev->gas_sett.run_gas = BME680_GET_BITS(data_array[BME680_REG_RUN_GAS_INDEX], + BME680_RUN_GAS); + } + } + } else { + rslt = BME680_E_NULL_PTR; + } + + return rslt; +} + +/*! + * @brief This API is used to set the power mode of the sensor. + */ +int8_t bme680_set_sensor_mode(struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t tmp_pow_mode; + uint8_t pow_mode = 0; + uint8_t reg_addr = BME680_CONF_T_P_MODE_ADDR; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + /* Call recursively until in sleep */ + do { + rslt = bme680_get_regs(BME680_CONF_T_P_MODE_ADDR, &tmp_pow_mode, 1, dev); + if (rslt == BME680_OK) { + /* Put to sleep before changing mode */ + pow_mode = (tmp_pow_mode & BME680_MODE_MSK); + + if (pow_mode != BME680_SLEEP_MODE) { + tmp_pow_mode = tmp_pow_mode & (~BME680_MODE_MSK); /* Set to sleep */ + rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + dev->delay_ms(BME680_POLL_PERIOD_MS); + } + } + } while (pow_mode != BME680_SLEEP_MODE); + + /* Already in sleep */ + if (dev->power_mode != BME680_SLEEP_MODE) { + tmp_pow_mode = (tmp_pow_mode & ~BME680_MODE_MSK) | (dev->power_mode & BME680_MODE_MSK); + if (rslt == BME680_OK) + rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + } + } + + return rslt; +} + +/*! + * @brief This API is used to get the power mode of the sensor. + */ +int8_t bme680_get_sensor_mode(struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t mode; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + rslt = bme680_get_regs(BME680_CONF_T_P_MODE_ADDR, &mode, 1, dev); + /* Masking the other register bit info*/ + dev->power_mode = mode & BME680_MODE_MSK; + } + + return rslt; +} + +/*! + * @brief This API is used to set the profile duration of the sensor. + */ +void bme680_set_profile_dur(uint16_t duration, struct bme680_dev *dev) +{ + uint32_t tph_dur; /* Calculate in us */ + + /* TPH measurement duration */ + tph_dur = ((uint32_t) (dev->tph_sett.os_temp + dev->tph_sett.os_pres + dev->tph_sett.os_hum) * UINT32_C(1963)); + tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + tph_dur += UINT32_C(477 * 5); /* Gas measurement duration */ + tph_dur += UINT32_C(500); /* Get it to the closest whole number.*/ + tph_dur /= UINT32_C(1000); /* Convert to ms */ + + tph_dur += UINT32_C(1); /* Wake up duration of 1ms */ + /* The remaining time should be used for heating */ + dev->gas_sett.heatr_dur = duration - (uint16_t) tph_dur; +} + +/*! + * @brief This API is used to get the profile duration of the sensor. + */ +void bme680_get_profile_dur(uint16_t *duration, const struct bme680_dev *dev) +{ + uint32_t tph_dur; /* Calculate in us */ + + /* TPH measurement duration */ + tph_dur = ((uint32_t) (dev->tph_sett.os_temp + dev->tph_sett.os_pres + dev->tph_sett.os_hum) * UINT32_C(1963)); + tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + tph_dur += UINT32_C(477 * 5); /* Gas measurement duration */ + tph_dur += UINT32_C(500); /* Get it to the closest whole number.*/ + tph_dur /= UINT32_C(1000); /* Convert to ms */ + + tph_dur += UINT32_C(1); /* Wake up duration of 1ms */ + + *duration = (uint16_t) tph_dur; + + /* Get the gas duration only when the run gas is enabled */ + if (dev->gas_sett.run_gas) { + /* The remaining time should be used for heating */ + *duration += dev->gas_sett.heatr_dur; + } +} + +/*! + * @brief This API reads the pressure, temperature and humidity and gas data + * from the sensor, compensates the data and store it in the bme680_data + * structure instance passed by the user. + */ +int8_t bme680_get_sensor_data(struct bme680_field_data *data, struct bme680_dev *dev) +{ + int8_t rslt; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + /* Reading the sensor data in forced mode only */ + rslt = read_field_data(data, dev); + if (rslt == BME680_OK) { + if (data->status & BME680_NEW_DATA_MSK) + dev->new_fields = 1; + else + dev->new_fields = 0; + } + } + + return rslt; +} + +/*! + * @brief This internal API is used to read the calibrated data from the sensor. + */ +static int8_t get_calib_data(struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t coeff_array[BME680_COEFF_SIZE] = { 0 }; + uint8_t temp_var = 0; /* Temporary variable */ + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + rslt = bme680_get_regs(BME680_COEFF_ADDR1, coeff_array, BME680_COEFF_ADDR1_LEN, dev); + /* Append the second half in the same array */ + if (rslt == BME680_OK) + rslt = bme680_get_regs(BME680_COEFF_ADDR2, &coeff_array[BME680_COEFF_ADDR1_LEN] + , BME680_COEFF_ADDR2_LEN, dev); + + /* Temperature related coefficients */ + dev->calib.par_t1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T1_MSB_REG], + coeff_array[BME680_T1_LSB_REG])); + dev->calib.par_t2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T2_MSB_REG], + coeff_array[BME680_T2_LSB_REG])); + dev->calib.par_t3 = (int8_t) (coeff_array[BME680_T3_REG]); + + /* Pressure related coefficients */ + dev->calib.par_p1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P1_MSB_REG], + coeff_array[BME680_P1_LSB_REG])); + dev->calib.par_p2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P2_MSB_REG], + coeff_array[BME680_P2_LSB_REG])); + dev->calib.par_p3 = (int8_t) coeff_array[BME680_P3_REG]; + dev->calib.par_p4 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P4_MSB_REG], + coeff_array[BME680_P4_LSB_REG])); + dev->calib.par_p5 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P5_MSB_REG], + coeff_array[BME680_P5_LSB_REG])); + dev->calib.par_p6 = (int8_t) (coeff_array[BME680_P6_REG]); + dev->calib.par_p7 = (int8_t) (coeff_array[BME680_P7_REG]); + dev->calib.par_p8 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P8_MSB_REG], + coeff_array[BME680_P8_LSB_REG])); + dev->calib.par_p9 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P9_MSB_REG], + coeff_array[BME680_P9_LSB_REG])); + dev->calib.par_p10 = (uint8_t) (coeff_array[BME680_P10_REG]); + + /* Humidity related coefficients */ + dev->calib.par_h1 = (uint16_t) (((uint16_t) coeff_array[BME680_H1_MSB_REG] << BME680_HUM_REG_SHIFT_VAL) + | (coeff_array[BME680_H1_LSB_REG] & BME680_BIT_H1_DATA_MSK)); + dev->calib.par_h2 = (uint16_t) (((uint16_t) coeff_array[BME680_H2_MSB_REG] << BME680_HUM_REG_SHIFT_VAL) + | ((coeff_array[BME680_H2_LSB_REG]) >> BME680_HUM_REG_SHIFT_VAL)); + dev->calib.par_h3 = (int8_t) coeff_array[BME680_H3_REG]; + dev->calib.par_h4 = (int8_t) coeff_array[BME680_H4_REG]; + dev->calib.par_h5 = (int8_t) coeff_array[BME680_H5_REG]; + dev->calib.par_h6 = (uint8_t) coeff_array[BME680_H6_REG]; + dev->calib.par_h7 = (int8_t) coeff_array[BME680_H7_REG]; + + /* Gas heater related coefficients */ + dev->calib.par_gh1 = (int8_t) coeff_array[BME680_GH1_REG]; + dev->calib.par_gh2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_GH2_MSB_REG], + coeff_array[BME680_GH2_LSB_REG])); + dev->calib.par_gh3 = (int8_t) coeff_array[BME680_GH3_REG]; + + /* Other coefficients */ + if (rslt == BME680_OK) { + rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_RANGE_ADDR, &temp_var, 1, dev); + + dev->calib.res_heat_range = ((temp_var & BME680_RHRANGE_MSK) / 16); + if (rslt == BME680_OK) { + rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_VAL_ADDR, &temp_var, 1, dev); + + dev->calib.res_heat_val = (int8_t) temp_var; + if (rslt == BME680_OK) + rslt = bme680_get_regs(BME680_ADDR_RANGE_SW_ERR_ADDR, &temp_var, 1, dev); + } + } + dev->calib.range_sw_err = ((int8_t) temp_var & (int8_t) BME680_RSERROR_MSK) / 16; + } + + return rslt; +} + +/*! + * @brief This internal API is used to set the gas configuration of the sensor. + */ +static int8_t set_gas_config(struct bme680_dev *dev) +{ + int8_t rslt; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + + uint8_t reg_addr[2] = {0}; + uint8_t reg_data[2] = {0}; + + if (dev->power_mode == BME680_FORCED_MODE) { + reg_addr[0] = BME680_RES_HEAT0_ADDR; + reg_data[0] = calc_heater_res(dev->gas_sett.heatr_temp, dev); + reg_addr[1] = BME680_GAS_WAIT0_ADDR; + reg_data[1] = calc_heater_dur(dev->gas_sett.heatr_dur); + dev->gas_sett.nb_conv = 0; + } else { + rslt = BME680_W_DEFINE_PWR_MODE; + } + if (rslt == BME680_OK) + rslt = bme680_set_regs(reg_addr, reg_data, 2, dev); + } + + return rslt; +} + +/*! + * @brief This internal API is used to get the gas configuration of the sensor. + */ +static int8_t get_gas_config(struct bme680_dev *dev) +{ + int8_t rslt; + /* starting address of the register array for burst read*/ + uint8_t reg_addr1 = BME680_ADDR_SENS_CONF_START; + uint8_t reg_addr2 = BME680_ADDR_GAS_CONF_START; + uint8_t data_array[BME680_GAS_HEATER_PROF_LEN_MAX] = { 0 }; + uint8_t index; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if (BME680_SPI_INTF == dev->intf) { + /* Memory page switch the SPI address*/ + rslt = set_mem_page(reg_addr1, dev); + } + + if (rslt == BME680_OK) { + rslt = bme680_get_regs(reg_addr1, data_array, BME680_GAS_HEATER_PROF_LEN_MAX, dev); + if (rslt == BME680_OK) { + for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + dev->gas_sett.heatr_temp = data_array[index]; + } + + rslt = bme680_get_regs(reg_addr2, data_array, BME680_GAS_HEATER_PROF_LEN_MAX, dev); + if (rslt == BME680_OK) { + for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + dev->gas_sett.heatr_dur = data_array[index]; + } + } + } + + return rslt; +} + +/*! + * @brief This internal API is used to calculate the temperature value. + */ +static int16_t calc_temperature(uint32_t temp_adc, struct bme680_dev *dev) +{ + int64_t var1; + int64_t var2; + int64_t var3; + int16_t calc_temp; + + var1 = ((int32_t) temp_adc >> 3) - ((int32_t) dev->calib.par_t1 << 1); + var2 = (var1 * (int32_t) dev->calib.par_t2) >> 11; + var3 = ((var1 >> 1) * (var1 >> 1)) >> 12; + var3 = ((var3) * ((int32_t) dev->calib.par_t3 << 4)) >> 14; + dev->calib.t_fine = (int32_t) (var2 + var3); + calc_temp = (int16_t) (((dev->calib.t_fine * 5) + 128) >> 8); + + return calc_temp; +} + +/*! + * @brief This internal API is used to calculate the pressure value. + */ +static uint32_t calc_pressure(uint32_t pres_adc, const struct bme680_dev *dev) +{ + int32_t var1 = 0; + int32_t var2 = 0; + int32_t var3 = 0; + int32_t var4 = 0; + int32_t pressure_comp = 0; + + var1 = (((int32_t)dev->calib.t_fine) >> 1) - 64000; + var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) * + (int32_t)dev->calib.par_p6) >> 2; + var2 = var2 + ((var1 * (int32_t)dev->calib.par_p5) << 1); + var2 = (var2 >> 2) + ((int32_t)dev->calib.par_p4 << 16); + var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) * + ((int32_t)dev->calib.par_p3 << 5)) >> 3) + + (((int32_t)dev->calib.par_p2 * var1) >> 1); + var1 = var1 >> 18; + var1 = ((32768 + var1) * (int32_t)dev->calib.par_p1) >> 15; + pressure_comp = 1048576 - pres_adc; + pressure_comp = (int32_t)((pressure_comp - (var2 >> 12)) * ((uint32_t)3125)); + var4 = (1 << 31); + if (pressure_comp >= var4) + pressure_comp = ((pressure_comp / (uint32_t)var1) << 1); + else + pressure_comp = ((pressure_comp << 1) / (uint32_t)var1); + var1 = ((int32_t)dev->calib.par_p9 * (int32_t)(((pressure_comp >> 3) * + (pressure_comp >> 3)) >> 13)) >> 12; + var2 = ((int32_t)(pressure_comp >> 2) * + (int32_t)dev->calib.par_p8) >> 13; + var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) * + (int32_t)(pressure_comp >> 8) * + (int32_t)dev->calib.par_p10) >> 17; + + pressure_comp = (int32_t)(pressure_comp) + ((var1 + var2 + var3 + + ((int32_t)dev->calib.par_p7 << 7)) >> 4); + + return (uint32_t)pressure_comp; + +} + +/*! + * @brief This internal API is used to calculate the humidity value. + */ +static uint32_t calc_humidity(uint16_t hum_adc, const struct bme680_dev *dev) +{ + int32_t var1; + int32_t var2; + int32_t var3; + int32_t var4; + int32_t var5; + int32_t var6; + int32_t temp_scaled; + int32_t calc_hum; + + temp_scaled = (((int32_t) dev->calib.t_fine * 5) + 128) >> 8; + var1 = (int32_t) (hum_adc - ((int32_t) ((int32_t) dev->calib.par_h1 * 16))) + - (((temp_scaled * (int32_t) dev->calib.par_h3) / ((int32_t) 100)) >> 1); + var2 = ((int32_t) dev->calib.par_h2 + * (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100)) + + (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6) + / ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10; + var3 = var1 * var2; + var4 = (int32_t) dev->calib.par_h6 << 7; + var4 = ((var4) + ((temp_scaled * (int32_t) dev->calib.par_h7) / ((int32_t) 100))) >> 4; + var5 = ((var3 >> 14) * (var3 >> 14)) >> 10; + var6 = (var4 * var5) >> 1; + calc_hum = (((var3 + var6) >> 10) * ((int32_t) 1000)) >> 12; + + if (calc_hum > 100000) /* Cap at 100%rH */ + calc_hum = 100000; + else if (calc_hum < 0) + calc_hum = 0; + + return (uint32_t) calc_hum; +} + +/*! + * @brief This internal API is used to calculate the Gas Resistance value. + */ +static uint32_t calc_gas_resistance(uint16_t gas_res_adc, uint8_t gas_range, const struct bme680_dev *dev) +{ + int64_t var1; + uint64_t var2; + int64_t var3; + uint32_t calc_gas_res; + + var1 = (int64_t) ((1340 + (5 * (int64_t) dev->calib.range_sw_err)) * + ((int64_t) lookupTable1[gas_range])) >> 16; + var2 = (((int64_t) ((int64_t) gas_res_adc << 15) - (int64_t) (16777216)) + var1); + var3 = (((int64_t) lookupTable2[gas_range] * (int64_t) var1) >> 9); + calc_gas_res = (uint32_t) ((var3 + ((int64_t) var2 >> 1)) / (int64_t) var2); + + return calc_gas_res; +} + +/*! + * @brief This internal API is used to calculate the Heat Resistance value. + */ +static uint8_t calc_heater_res(uint16_t temp, const struct bme680_dev *dev) +{ + uint8_t heatr_res; + int32_t var1; + int32_t var2; + int32_t var3; + int32_t var4; + int32_t var5; + int32_t heatr_res_x100; + + if (temp < 200) /* Cap temperature */ + temp = 200; + else if (temp > 400) + temp = 400; + + var1 = (((int32_t) dev->amb_temp * dev->calib.par_gh3) / 1000) * 256; + var2 = (dev->calib.par_gh1 + 784) * (((((dev->calib.par_gh2 + 154009) * temp * 5) / 100) + 3276800) / 10); + var3 = var1 + (var2 / 2); + var4 = (var3 / (dev->calib.res_heat_range + 4)); + var5 = (131 * dev->calib.res_heat_val) + 65536; + heatr_res_x100 = (int32_t) (((var4 / var5) - 250) * 34); + heatr_res = (uint8_t) ((heatr_res_x100 + 50) / 100); + + return heatr_res; +} + +/*! + * @brief This internal API is used to calculate the Heat duration value. + */ +static uint8_t calc_heater_dur(uint16_t dur) +{ + uint8_t factor = 0; + uint8_t durval; + + if (dur >= 0xfc0) { + durval = 0xff; /* Max duration*/ + } else { + while (dur > 0x3F) { + dur = dur / 4; + factor += 1; + } + durval = (uint8_t) (dur + (factor * 64)); + } + + return durval; +} + +/*! + * @brief This internal API is used to calculate the field data of sensor. + */ +static int8_t read_field_data(struct bme680_field_data *data, struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t buff[BME680_FIELD_LENGTH] = { 0 }; + uint8_t gas_range; + uint32_t adc_temp; + uint32_t adc_pres; + uint16_t adc_hum; + uint16_t adc_gas_res; + uint8_t tries = 10; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + do { + if (rslt == BME680_OK) { + rslt = bme680_get_regs(((uint8_t) (BME680_FIELD0_ADDR)), buff, (uint16_t) BME680_FIELD_LENGTH, + dev); + + data->status = buff[0] & BME680_NEW_DATA_MSK; + data->gas_index = buff[0] & BME680_GAS_INDEX_MSK; + data->meas_index = buff[1]; + + /* read the raw data from the sensor */ + adc_pres = (uint32_t) (((uint32_t) buff[2] * 4096) | ((uint32_t) buff[3] * 16) + | ((uint32_t) buff[4] / 16)); + adc_temp = (uint32_t) (((uint32_t) buff[5] * 4096) | ((uint32_t) buff[6] * 16) + | ((uint32_t) buff[7] / 16)); + adc_hum = (uint16_t) (((uint32_t) buff[8] * 256) | (uint32_t) buff[9]); + adc_gas_res = (uint16_t) ((uint32_t) buff[13] * 4 | (((uint32_t) buff[14]) / 64)); + gas_range = buff[14] & BME680_GAS_RANGE_MSK; + + data->status |= buff[14] & BME680_GASM_VALID_MSK; + data->status |= buff[14] & BME680_HEAT_STAB_MSK; + + if (data->status & BME680_NEW_DATA_MSK) { + data->temperature = calc_temperature(adc_temp, dev); + data->pressure = calc_pressure(adc_pres, dev); + data->humidity = calc_humidity(adc_hum, dev); + data->gas_resistance = calc_gas_resistance(adc_gas_res, gas_range, dev); + break; + } + /* Delay to poll the data */ + dev->delay_ms(BME680_POLL_PERIOD_MS); + } + tries--; + } while (tries); + + if (!tries) + rslt = BME680_W_NO_NEW_DATA; + + return rslt; +} + +/*! + * @brief This internal API is used to set the memory page based on register address. + */ +static int8_t set_mem_page(uint8_t reg_addr, struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t reg; + uint8_t mem_page; + + /* Check for null pointers in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + if (reg_addr > 0x7f) + mem_page = BME680_MEM_PAGE1; + else + mem_page = BME680_MEM_PAGE0; + + if (mem_page != dev->mem_page) { + dev->mem_page = mem_page; + + dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1); + if (dev->com_rslt != 0) + rslt = BME680_E_COM_FAIL; + + if (rslt == BME680_OK) { + reg = reg & (~BME680_MEM_PAGE_MSK); + reg = reg | (dev->mem_page & BME680_MEM_PAGE_MSK); + + dev->com_rslt = dev->write(dev->dev_id, BME680_MEM_PAGE_ADDR & BME680_SPI_WR_MSK, + ®, 1); + if (dev->com_rslt != 0) + rslt = BME680_E_COM_FAIL; + } + } + } + + return rslt; +} + +/*! + * @brief This internal API is used to get the memory page based on register address. + */ +static int8_t get_mem_page(struct bme680_dev *dev) +{ + int8_t rslt; + uint8_t reg; + + /* Check for null pointer in the device structure*/ + rslt = null_ptr_check(dev); + if (rslt == BME680_OK) { + dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1); + if (dev->com_rslt != 0) + rslt = BME680_E_COM_FAIL; + else + dev->mem_page = reg & BME680_MEM_PAGE_MSK; + } + + return rslt; +} + +/*! + * @brief This internal API is used to validate the boundary + * conditions. + */ +static int8_t boundary_check(uint8_t *value, uint8_t min, uint8_t max, struct bme680_dev *dev) +{ + int8_t rslt = BME680_OK; + + if (value != NULL) { + /* Check if value is below minimum value */ + if (*value < min) { + /* Auto correct the invalid value to minimum value */ + *value = min; + dev->info_msg |= BME680_I_MIN_CORRECTION; + } + /* Check if value is above maximum value */ + if (*value > max) { + /* Auto correct the invalid value to maximum value */ + *value = max; + dev->info_msg |= BME680_I_MAX_CORRECTION; + } + } else { + rslt = BME680_E_NULL_PTR; + } + + return rslt; +} + +/*! + * @brief This internal API is used to validate the device structure pointer for + * null conditions. + */ +static int8_t null_ptr_check(const struct bme680_dev *dev) +{ + int8_t rslt; + + if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_ms == NULL)) { + /* Device structure pointer is not valid */ + rslt = BME680_E_NULL_PTR; + } else { + /* Device structure is fine */ + rslt = BME680_OK; + } + + return rslt; +} diff --git a/Drivers/BME680/bme680.h b/Drivers/BME680/bme680.h new file mode 100644 index 0000000..56eb7a8 --- /dev/null +++ b/Drivers/BME680/bme680.h @@ -0,0 +1,225 @@ +/** + * Copyright (C) 2017 - 2018 Bosch Sensortec GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holder nor the names of the + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + * The information provided is believed to be accurate and reliable. + * The copyright holder assumes no responsibility + * for the consequences of use + * of such information nor for any infringement of patents or + * other rights of third parties which may result from its use. + * No license is granted by implication or otherwise under any patent or + * patent rights of the copyright holder. + * + * @file bme680.h + * @date 30 Oct 2017 + * @version 3.5.3 + * @brief + * + */ +/*! @file bme680.h + @brief Sensor driver for BME680 sensor */ +/*! + * @defgroup BME680 SENSOR API + * @{*/ +#ifndef BME680_H_ +#define BME680_H_ + +/*! CPP guard */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Header includes */ +#include "bme680_defs.h" + +/* function prototype declarations */ +/*! + * @brief This API is the entry point. + * It reads the chip-id and calibration data from the sensor. + * + * @param[in,out] dev : Structure instance of bme680_dev + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_init(struct bme680_dev *dev); + +/*! + * @brief This API writes the given data to the register address + * of the sensor. + * + * @param[in] reg_addr : Register address from where the data to be written. + * @param[in] reg_data : Pointer to data buffer which is to be written + * in the sensor. + * @param[in] len : No of bytes of data to write.. + * @param[in] dev : Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_set_regs(const uint8_t *reg_addr, const uint8_t *reg_data, uint8_t len, struct bme680_dev *dev); + +/*! + * @brief This API reads the data from the given register address of the sensor. + * + * @param[in] reg_addr : Register address from where the data to be read + * @param[out] reg_data : Pointer to data buffer to store the read data. + * @param[in] len : No of bytes of data to be read. + * @param[in] dev : Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bme680_dev *dev); + +/*! + * @brief This API performs the soft reset of the sensor. + * + * @param[in] dev : Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error. + */ +int8_t bme680_soft_reset(struct bme680_dev *dev); + +/*! + * @brief This API is used to set the power mode of the sensor. + * + * @param[in] dev : Structure instance of bme680_dev + * @note : Pass the value to bme680_dev.power_mode structure variable. + * + * value | mode + * -------------|------------------ + * 0x00 | BME680_SLEEP_MODE + * 0x01 | BME680_FORCED_MODE + * + * * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_set_sensor_mode(struct bme680_dev *dev); + +/*! + * @brief This API is used to get the power mode of the sensor. + * + * @param[in] dev : Structure instance of bme680_dev + * @note : bme680_dev.power_mode structure variable hold the power mode. + * + * value | mode + * ---------|------------------ + * 0x00 | BME680_SLEEP_MODE + * 0x01 | BME680_FORCED_MODE + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_get_sensor_mode(struct bme680_dev *dev); + +/*! + * @brief This API is used to set the profile duration of the sensor. + * + * @param[in] dev : Structure instance of bme680_dev. + * @param[in] duration : Duration of the measurement in ms. + * + * @return Nothing + */ +void bme680_set_profile_dur(uint16_t duration, struct bme680_dev *dev); + +/*! + * @brief This API is used to get the profile duration of the sensor. + * + * @param[in] dev : Structure instance of bme680_dev. + * @param[in] duration : Duration of the measurement in ms. + * + * @return Nothing + */ +void bme680_get_profile_dur(uint16_t *duration, const struct bme680_dev *dev); + +/*! + * @brief This API reads the pressure, temperature and humidity and gas data + * from the sensor, compensates the data and store it in the bme680_data + * structure instance passed by the user. + * + * @param[out] data: Structure instance to hold the data. + * @param[in] dev : Structure instance of bme680_dev. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + */ +int8_t bme680_get_sensor_data(struct bme680_field_data *data, struct bme680_dev *dev); + +/*! + * @brief This API is used to set the oversampling, filter and T,P,H, gas selection + * settings in the sensor. + * + * @param[in] dev : Structure instance of bme680_dev. + * @param[in] desired_settings : Variable used to select the settings which + * are to be set in the sensor. + * + * Macros | Functionality + *---------------------------------|---------------------------------------------- + * BME680_OST_SEL | To set temperature oversampling. + * BME680_OSP_SEL | To set pressure oversampling. + * BME680_OSH_SEL | To set humidity oversampling. + * BME680_GAS_MEAS_SEL | To set gas measurement setting. + * BME680_FILTER_SEL | To set filter setting. + * BME680_HCNTRL_SEL | To set humidity control setting. + * BME680_RUN_GAS_SEL | To set run gas setting. + * BME680_NBCONV_SEL | To set NB conversion setting. + * BME680_GAS_SENSOR_SEL | To set all gas sensor related settings + * + * @note : Below are the macros to be used by the user for selecting the + * desired settings. User can do OR operation of these macros for configuring + * multiple settings. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error. + */ +int8_t bme680_set_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev); + +/*! + * @brief This API is used to get the oversampling, filter and T,P,H, gas selection + * settings in the sensor. + * + * @param[in] dev : Structure instance of bme680_dev. + * @param[in] desired_settings : Variable used to select the settings which + * are to be get from the sensor. + * + * @return Result of API execution status + * @retval zero -> Success / +ve value -> Warning / -ve value -> Error. + */ +int8_t bme680_get_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev); +#ifdef __cplusplus +} +#endif /* End of CPP guard */ +#endif /* BME680_H_ */ +/** @}*/ diff --git a/Drivers/BME680/bme680_defs.h b/Drivers/BME680/bme680_defs.h new file mode 100644 index 0000000..3afb94c --- /dev/null +++ b/Drivers/BME680/bme680_defs.h @@ -0,0 +1,512 @@ +/** + * Copyright (C) 2017 - 2018 Bosch Sensortec GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holder nor the names of the + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + * The information provided is believed to be accurate and reliable. + * The copyright holder assumes no responsibility + * for the consequences of use + * of such information nor for any infringement of patents or + * other rights of third parties which may result from its use. + * No license is granted by implication or otherwise under any patent or + * patent rights of the copyright holder. + * + * @file bme680_defs.h + * @date 30 Oct 2017 + * @version 3.5.3 + * @brief + * + */ + +/*! @file bme680_defs.h + @brief Sensor driver for BME680 sensor */ +/*! + * @defgroup BME680 SENSOR API + * @brief + * @{*/ +#ifndef BME680_DEFS_H_ +#define BME680_DEFS_H_ + +/********************************************************/ +/* header includes */ +#ifdef __KERNEL__ +#include +#include +#else +#include +#include +#endif + +/******************************************************************************/ +/*! @name Common macros */ +/******************************************************************************/ + +#if !defined(UINT8_C) && !defined(INT8_C) +#define INT8_C(x) S8_C(x) +#define UINT8_C(x) U8_C(x) +#endif + +#if !defined(UINT16_C) && !defined(INT16_C) +#define INT16_C(x) S16_C(x) +#define UINT16_C(x) U16_C(x) +#endif + +#if !defined(INT32_C) && !defined(UINT32_C) +#define INT32_C(x) S32_C(x) +#define UINT32_C(x) U32_C(x) +#endif + +#if !defined(INT64_C) && !defined(UINT64_C) +#define INT64_C(x) S64_C(x) +#define UINT64_C(x) U64_C(x) +#endif + +/**@}*/ + +/**\name C standard macros */ +#ifndef NULL +#ifdef __cplusplus +#define NULL 0 +#else +#define NULL ((void *) 0) +#endif +#endif + +/** BME680 General config */ +#define BME680_POLL_PERIOD_MS UINT8_C(10) + +/** BME680 I2C addresses */ +#define BME680_I2C_ADDR_PRIMARY UINT8_C(0x76) +#define BME680_I2C_ADDR_SECONDARY UINT8_C(0x77) + +/** BME680 unique chip identifier */ +#define BME680_CHIP_ID UINT8_C(0x61) + +/** BME680 coefficients related defines */ +#define BME680_COEFF_SIZE UINT8_C(0x41) +#define BME680_COEFF_ADDR1_LEN UINT8_C(25) +#define BME680_COEFF_ADDR2_LEN UINT8_C(16) + +/** BME680 field_x related defines */ +#define BME680_FIELD_LENGTH UINT8_C(15) +#define BME680_FIELD_ADDR_OFFSET UINT8_C(17) + +/** Soft reset command */ +#define BME680_SOFT_RESET_CMD UINT8_C(0xb6) + +/** Error code definitions */ +#define BME680_OK INT8_C(0) +/* Errors */ +#define BME680_E_NULL_PTR INT8_C(-1) +#define BME680_E_COM_FAIL INT8_C(-2) +#define BME680_E_DEV_NOT_FOUND INT8_C(-3) +#define BME680_E_INVALID_LENGTH INT8_C(-4) + +/* Warnings */ +#define BME680_W_DEFINE_PWR_MODE INT8_C(1) +#define BME680_W_NO_NEW_DATA INT8_C(2) + +/* Info's */ +#define BME680_I_MIN_CORRECTION UINT8_C(1) +#define BME680_I_MAX_CORRECTION UINT8_C(2) + +/** Register map */ +/** Other coefficient's address */ +#define BME680_ADDR_RES_HEAT_VAL_ADDR UINT8_C(0x00) +#define BME680_ADDR_RES_HEAT_RANGE_ADDR UINT8_C(0x02) +#define BME680_ADDR_RANGE_SW_ERR_ADDR UINT8_C(0x04) +#define BME680_ADDR_SENS_CONF_START UINT8_C(0x5A) +#define BME680_ADDR_GAS_CONF_START UINT8_C(0x64) + +/** Field settings */ +#define BME680_FIELD0_ADDR UINT8_C(0x1d) + +/** Heater settings */ +#define BME680_RES_HEAT0_ADDR UINT8_C(0x5a) +#define BME680_GAS_WAIT0_ADDR UINT8_C(0x64) + +/** Sensor configuration registers */ +#define BME680_CONF_HEAT_CTRL_ADDR UINT8_C(0x70) +#define BME680_CONF_ODR_RUN_GAS_NBC_ADDR UINT8_C(0x71) +#define BME680_CONF_OS_H_ADDR UINT8_C(0x72) +#define BME680_MEM_PAGE_ADDR UINT8_C(0xf3) +#define BME680_CONF_T_P_MODE_ADDR UINT8_C(0x74) +#define BME680_CONF_ODR_FILT_ADDR UINT8_C(0x75) + +/** Coefficient's address */ +#define BME680_COEFF_ADDR1 UINT8_C(0x89) +#define BME680_COEFF_ADDR2 UINT8_C(0xe1) + +/** Chip identifier */ +#define BME680_CHIP_ID_ADDR UINT8_C(0xd0) + +/** Soft reset register */ +#define BME680_SOFT_RESET_ADDR UINT8_C(0xe0) + +/** Heater control settings */ +#define BME680_ENABLE_HEATER UINT8_C(0x00) +#define BME680_DISABLE_HEATER UINT8_C(0x08) + +/** Gas measurement settings */ +#define BME680_DISABLE_GAS_MEAS UINT8_C(0x00) +#define BME680_ENABLE_GAS_MEAS UINT8_C(0x01) + +/** Over-sampling settings */ +#define BME680_OS_NONE UINT8_C(0) +#define BME680_OS_1X UINT8_C(1) +#define BME680_OS_2X UINT8_C(2) +#define BME680_OS_4X UINT8_C(3) +#define BME680_OS_8X UINT8_C(4) +#define BME680_OS_16X UINT8_C(5) + +/** IIR filter settings */ +#define BME680_FILTER_SIZE_0 UINT8_C(0) +#define BME680_FILTER_SIZE_1 UINT8_C(1) +#define BME680_FILTER_SIZE_3 UINT8_C(2) +#define BME680_FILTER_SIZE_7 UINT8_C(3) +#define BME680_FILTER_SIZE_15 UINT8_C(4) +#define BME680_FILTER_SIZE_31 UINT8_C(5) +#define BME680_FILTER_SIZE_63 UINT8_C(6) +#define BME680_FILTER_SIZE_127 UINT8_C(7) + +/** Power mode settings */ +#define BME680_SLEEP_MODE UINT8_C(0) +#define BME680_FORCED_MODE UINT8_C(1) + +/** Delay related macro declaration */ +#define BME680_RESET_PERIOD UINT32_C(10) + +/** SPI memory page settings */ +#define BME680_MEM_PAGE0 UINT8_C(0x10) +#define BME680_MEM_PAGE1 UINT8_C(0x00) + +/** Ambient humidity shift value for compensation */ +#define BME680_HUM_REG_SHIFT_VAL UINT8_C(4) + +/** Run gas enable and disable settings */ +#define BME680_RUN_GAS_DISABLE UINT8_C(0) +#define BME680_RUN_GAS_ENABLE UINT8_C(1) + +/** Buffer length macro declaration */ +#define BME680_TMP_BUFFER_LENGTH UINT8_C(40) +#define BME680_REG_BUFFER_LENGTH UINT8_C(6) +#define BME680_FIELD_DATA_LENGTH UINT8_C(3) +#define BME680_GAS_REG_BUF_LENGTH UINT8_C(20) +#define BME680_GAS_HEATER_PROF_LEN_MAX UINT8_C(10) + +/** Settings selector */ +#define BME680_OST_SEL UINT16_C(1) +#define BME680_OSP_SEL UINT16_C(2) +#define BME680_OSH_SEL UINT16_C(4) +#define BME680_GAS_MEAS_SEL UINT16_C(8) +#define BME680_FILTER_SEL UINT16_C(16) +#define BME680_HCNTRL_SEL UINT16_C(32) +#define BME680_RUN_GAS_SEL UINT16_C(64) +#define BME680_NBCONV_SEL UINT16_C(128) +#define BME680_GAS_SENSOR_SEL (BME680_GAS_MEAS_SEL | BME680_RUN_GAS_SEL | BME680_NBCONV_SEL) + +/** Number of conversion settings*/ +#define BME680_NBCONV_MIN UINT8_C(0) +#define BME680_NBCONV_MAX UINT8_C(10) + +/** Mask definitions */ +#define BME680_GAS_MEAS_MSK UINT8_C(0x30) +#define BME680_NBCONV_MSK UINT8_C(0X0F) +#define BME680_FILTER_MSK UINT8_C(0X1C) +#define BME680_OST_MSK UINT8_C(0XE0) +#define BME680_OSP_MSK UINT8_C(0X1C) +#define BME680_OSH_MSK UINT8_C(0X07) +#define BME680_HCTRL_MSK UINT8_C(0x08) +#define BME680_RUN_GAS_MSK UINT8_C(0x10) +#define BME680_MODE_MSK UINT8_C(0x03) +#define BME680_RHRANGE_MSK UINT8_C(0x30) +#define BME680_RSERROR_MSK UINT8_C(0xf0) +#define BME680_NEW_DATA_MSK UINT8_C(0x80) +#define BME680_GAS_INDEX_MSK UINT8_C(0x0f) +#define BME680_GAS_RANGE_MSK UINT8_C(0x0f) +#define BME680_GASM_VALID_MSK UINT8_C(0x20) +#define BME680_HEAT_STAB_MSK UINT8_C(0x10) +#define BME680_MEM_PAGE_MSK UINT8_C(0x10) +#define BME680_SPI_RD_MSK UINT8_C(0x80) +#define BME680_SPI_WR_MSK UINT8_C(0x7f) +#define BME680_BIT_H1_DATA_MSK UINT8_C(0x0F) + +/** Bit position definitions for sensor settings */ +#define BME680_GAS_MEAS_POS UINT8_C(4) +#define BME680_FILTER_POS UINT8_C(2) +#define BME680_OST_POS UINT8_C(5) +#define BME680_OSP_POS UINT8_C(2) +#define BME680_RUN_GAS_POS UINT8_C(4) + +/** Array Index to Field data mapping for Calibration Data*/ +#define BME680_T2_LSB_REG (1) +#define BME680_T2_MSB_REG (2) +#define BME680_T3_REG (3) +#define BME680_P1_LSB_REG (5) +#define BME680_P1_MSB_REG (6) +#define BME680_P2_LSB_REG (7) +#define BME680_P2_MSB_REG (8) +#define BME680_P3_REG (9) +#define BME680_P4_LSB_REG (11) +#define BME680_P4_MSB_REG (12) +#define BME680_P5_LSB_REG (13) +#define BME680_P5_MSB_REG (14) +#define BME680_P7_REG (15) +#define BME680_P6_REG (16) +#define BME680_P8_LSB_REG (19) +#define BME680_P8_MSB_REG (20) +#define BME680_P9_LSB_REG (21) +#define BME680_P9_MSB_REG (22) +#define BME680_P10_REG (23) +#define BME680_H2_MSB_REG (25) +#define BME680_H2_LSB_REG (26) +#define BME680_H1_LSB_REG (26) +#define BME680_H1_MSB_REG (27) +#define BME680_H3_REG (28) +#define BME680_H4_REG (29) +#define BME680_H5_REG (30) +#define BME680_H6_REG (31) +#define BME680_H7_REG (32) +#define BME680_T1_LSB_REG (33) +#define BME680_T1_MSB_REG (34) +#define BME680_GH2_LSB_REG (35) +#define BME680_GH2_MSB_REG (36) +#define BME680_GH1_REG (37) +#define BME680_GH3_REG (38) + +/** BME680 register buffer index settings*/ +#define BME680_REG_FILTER_INDEX UINT8_C(5) +#define BME680_REG_TEMP_INDEX UINT8_C(4) +#define BME680_REG_PRES_INDEX UINT8_C(4) +#define BME680_REG_HUM_INDEX UINT8_C(2) +#define BME680_REG_NBCONV_INDEX UINT8_C(1) +#define BME680_REG_RUN_GAS_INDEX UINT8_C(1) +#define BME680_REG_HCTRL_INDEX UINT8_C(0) + +/** Macro to combine two 8 bit data's to form a 16 bit data */ +#define BME680_CONCAT_BYTES(msb, lsb) (((uint16_t)msb << 8) | (uint16_t)lsb) + +/** Macro to SET and GET BITS of a register */ +#define BME680_SET_BITS(reg_data, bitname, data) \ + ((reg_data & ~(bitname##_MSK)) | \ + ((data << bitname##_POS) & bitname##_MSK)) +#define BME680_GET_BITS(reg_data, bitname) ((reg_data & (bitname##_MSK)) >> \ + (bitname##_POS)) + +/** Macro variant to handle the bitname position if it is zero */ +#define BME680_SET_BITS_POS_0(reg_data, bitname, data) \ + ((reg_data & ~(bitname##_MSK)) | \ + (data & bitname##_MSK)) +#define BME680_GET_BITS_POS_0(reg_data, bitname) (reg_data & (bitname##_MSK)) + +/** Type definitions */ +/* + * Generic communication function pointer + * @param[in] dev_id: Place holder to store the id of the device structure + * Can be used to store the index of the Chip select or + * I2C address of the device. + * @param[in] reg_addr: Used to select the register the where data needs to + * be read from or written to. + * @param[in/out] reg_data: Data array to read/write + * @param[in] len: Length of the data array + */ +typedef int8_t (*bme680_com_fptr_t)(uint8_t dev_id, uint8_t reg_addr, uint8_t *data, uint16_t len); + +/* + * Delay function pointer + * @param[in] period: Time period in milliseconds + */ +typedef void (*bme680_delay_fptr_t)(uint32_t period); + +/*! + * @brief Interface selection Enumerations + */ +enum bme680_intf { + /*! SPI interface */ + BME680_SPI_INTF, + /*! I2C interface */ + BME680_I2C_INTF +}; + +/* structure definitions */ +/*! + * @brief Sensor field data structure + */ +struct bme680_field_data { + /*! Contains new_data, gasm_valid & heat_stab */ + uint8_t status; + /*! The index of the heater profile used */ + uint8_t gas_index; + /*! Measurement index to track order */ + uint8_t meas_index; + /*! Temperature in degree celsius x100 */ + int16_t temperature; + /*! Pressure in Pascal */ + uint32_t pressure; + /*! Humidity in % relative humidity x1000 */ + uint32_t humidity; + /*! Gas resistance in Ohms */ + uint32_t gas_resistance; +}; + +/*! + * @brief Structure to hold the Calibration data + */ +struct bme680_calib_data { + /*! Variable to store calibrated humidity data */ + uint16_t par_h1; + /*! Variable to store calibrated humidity data */ + uint16_t par_h2; + /*! Variable to store calibrated humidity data */ + int8_t par_h3; + /*! Variable to store calibrated humidity data */ + int8_t par_h4; + /*! Variable to store calibrated humidity data */ + int8_t par_h5; + /*! Variable to store calibrated humidity data */ + uint8_t par_h6; + /*! Variable to store calibrated humidity data */ + int8_t par_h7; + /*! Variable to store calibrated gas data */ + int8_t par_gh1; + /*! Variable to store calibrated gas data */ + int16_t par_gh2; + /*! Variable to store calibrated gas data */ + int8_t par_gh3; + /*! Variable to store calibrated temperature data */ + uint16_t par_t1; + /*! Variable to store calibrated temperature data */ + int16_t par_t2; + /*! Variable to store calibrated temperature data */ + int8_t par_t3; + /*! Variable to store calibrated pressure data */ + uint16_t par_p1; + /*! Variable to store calibrated pressure data */ + int16_t par_p2; + /*! Variable to store calibrated pressure data */ + int8_t par_p3; + /*! Variable to store calibrated pressure data */ + int16_t par_p4; + /*! Variable to store calibrated pressure data */ + int16_t par_p5; + /*! Variable to store calibrated pressure data */ + int8_t par_p6; + /*! Variable to store calibrated pressure data */ + int8_t par_p7; + /*! Variable to store calibrated pressure data */ + int16_t par_p8; + /*! Variable to store calibrated pressure data */ + int16_t par_p9; + /*! Variable to store calibrated pressure data */ + uint8_t par_p10; + /*! Variable to store t_fine size */ + int32_t t_fine; + /*! Variable to store heater resistance range */ + uint8_t res_heat_range; + /*! Variable to store heater resistance value */ + int8_t res_heat_val; + /*! Variable to store error range */ + int8_t range_sw_err; +}; + +/*! + * @brief BME680 sensor settings structure which comprises of ODR, + * over-sampling and filter settings. + */ +struct bme680_tph_sett { + /*! Humidity oversampling */ + uint8_t os_hum; + /*! Temperature oversampling */ + uint8_t os_temp; + /*! Pressure oversampling */ + uint8_t os_pres; + /*! Filter coefficient */ + uint8_t filter; +}; + +/*! + * @brief BME680 gas sensor which comprises of gas settings + * and status parameters + */ +struct bme680_gas_sett { + /*! Variable to store nb conversion */ + uint8_t nb_conv; + /*! Variable to store heater control */ + uint8_t heatr_ctrl; + /*! Run gas enable value */ + uint8_t run_gas; + /*! Pointer to store heater temperature */ + uint16_t heatr_temp; + /*! Pointer to store duration profile */ + uint16_t heatr_dur; +}; + +/*! + * @brief BME680 device structure + */ +struct bme680_dev { + /*! Chip Id */ + uint8_t chip_id; + /*! Device Id */ + uint8_t dev_id; + /*! SPI/I2C interface */ + enum bme680_intf intf; + /*! Memory page used */ + uint8_t mem_page; + /*! Ambient temperature in Degree C*/ + int8_t amb_temp; + /*! Sensor calibration data */ + struct bme680_calib_data calib; + /*! Sensor settings */ + struct bme680_tph_sett tph_sett; + /*! Gas Sensor settings */ + struct bme680_gas_sett gas_sett; + /*! Sensor power modes */ + uint8_t power_mode; + /*! New sensor fields */ + uint8_t new_fields; + /*! Store the info messages */ + uint8_t info_msg; + /*! Burst read structure */ + bme680_com_fptr_t read; + /*! Burst write structure */ + bme680_com_fptr_t write; + /*! Delay in ms */ + bme680_delay_fptr_t delay_ms; + /*! Communication function result */ + int8_t com_rslt; +}; + + + +#endif /* BME680_DEFS_H_ */ +/** @}*/ +/** @}*/ diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c index 2d1ccc8..9d59fd3 100755 --- a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c +++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c @@ -239,6 +239,7 @@ */ /* Includes ------------------------------------------------------------------*/ +#include #include "stm32l0xx_hal.h" /** @addtogroup STM32L0xx_HAL_Driver @@ -1892,6 +1893,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, { if ((pData == NULL) || (Size == 0U)) { + PRINTF("Bad pData or Size=0\r\n"); return HAL_ERROR; } @@ -1903,6 +1905,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { + PRINTF("Timeout\r\n"); return HAL_TIMEOUT; } @@ -1918,6 +1921,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { + PRINTF("Error in memory read - %d\r\n", hi2c->ErrorCode); if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ @@ -1950,6 +1954,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until RXNE flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { + PRINTF("waiting for flag timeout1\r\n"); return HAL_TIMEOUT; } @@ -1963,6 +1968,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { + PRINTF("waiting for flag timeout2\r\n"); return HAL_TIMEOUT; } @@ -1986,6 +1992,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + PRINTF("waiting for stop error %d\r\n", hi2c->ErrorCode); return HAL_ERROR; } else @@ -2010,6 +2017,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } else { + PRINTF("busy!!\r\n"); return HAL_BUSY; } } @@ -3713,6 +3721,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { + PRINTF("I2C_RequestMemoryRead error %d\r\n", hi2c->ErrorCode); if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; @@ -3738,6 +3747,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { + PRINTF("I2C_RequestMemoryRead error2 %d\r\n", hi2c->ErrorCode); if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; @@ -3755,6 +3765,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TC flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { + PRINTF("I2C_RequestMemoryRead TIMEOUT\r\n"); return HAL_TIMEOUT; } @@ -4507,6 +4518,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { + PRINTF("I2C_WaitOnTXISFlagUntilTimeout ->I2C_IsAcknowledgeFailed error\r\n"); return HAL_ERROR; } @@ -4522,6 +4534,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); + PRINTF("I2C_WaitOnTXISFlagUntilTimeout timeout\r\n"); return HAL_TIMEOUT; } } diff --git a/Inc/debug.h b/Inc/debug.h index 5889438..584492f 100755 --- a/Inc/debug.h +++ b/Inc/debug.h @@ -69,7 +69,7 @@ void DBG_Init( void ); -void Error_Handler( void ); +//void Error_Handler( void ); #ifdef DEBUG @@ -116,6 +116,10 @@ void Error_Handler( void ); #endif /* DEBUG */ + void _Error_Handler(char *, int); + +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) + #ifdef __cplusplus } #endif diff --git a/Inc/hw_i2c.h b/Inc/hw_i2c.h new file mode 100644 index 0000000..5eff566 --- /dev/null +++ b/Inc/hw_i2c.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * File Name : I2C.h + * Description : This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2017 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __i2c_H +#define __i2c_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal.h" +#include "main.h" +#include "debug.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ i2c_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/main.h b/Inc/main.h index 15c9019..c6414dc 100755 --- a/Inc/main.h +++ b/Inc/main.h @@ -75,9 +75,7 @@ #ifdef __cplusplus extern "C" { #endif -void _Error_Handler(char *, int); -#define Error_Handler() _Error_Handler(__FILE__, __LINE__) #ifdef __cplusplus } #endif diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..1bdfab4 --- /dev/null +++ b/Makefile @@ -0,0 +1,292 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [2.26.0] date: [Thu Nov 16 09:19:43 CET 2017] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = bees + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### + +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \ +./Drivers/BSP/sx1272mb2das/sx1272mb2das.c \ +./Drivers/BSP/Components/sx1272/sx1272.c \ +./Middlewares/Third_Party/Lora/Core/lora.c \ +./Middlewares/Third_Party/Lora/Crypto/aes.c \ +./Middlewares/Third_Party/Lora/Crypto/cmac.c \ +./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c \ +./Middlewares/Third_Party/Lora/Mac/region/Region.c \ +./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c \ +./Middlewares/Third_Party/Lora/Mac/LoRaMac.c \ +./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c \ +./Middlewares/Third_Party/Lora/Utilities/delay.c \ +./Middlewares/Third_Party/Lora/Utilities/timeServer.c \ +./Middlewares/Third_Party/Lora/Utilities/utilities.c \ +./Middlewares/Third_Party/Lora/Utilities/low_power.c \ +./Src/vcom.c \ +./Src/stm32l0xx_hw.c \ +./Src/hw_rtc.c \ +./Src/stm32l0xx_hal_msp.c \ +./Src/debug.c \ +./Src/hw_i2c.c \ +./Src/hw_gpio.c \ +./Src/hw_spi.c \ +./Src/main.c \ +./Src/system_stm32l0xx.c \ +./Src/stm32l0xx_it.c \ +Src/voc_sensor.c \ +Drivers/BME680/bme680.c + + +# ASM sources +ASM_SOURCES = \ +startup/startup_stm32l073xx.s + + +###################################### +# firmware library +###################################### +PERIFLIB_SOURCES = + + +####################################### +# binaries +####################################### +BINPATH = /bin +PREFIX = arm-none-eabi- +CC = $(BINPATH)/$(PREFIX)gcc +AS = $(BINPATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(BINPATH)/$(PREFIX)objcopy +AR = $(BINPATH)/$(PREFIX)ar +SZ = $(BINPATH)/$(PREFIX)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m0plus + +# fpu +# NONE for Cortex-M0/M0+/M3 + +# float-abi + + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_HAL_DRIVER \ +-DSTM32L073xx \ +-DREGION_EU868 \ +-DUSE_FULL_LL_DRIVER + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ + -IInc \ + -IDrivers/STM32L0xx_HAL_Driver/Inc \ + -IDrivers/STM32L0xx_HAL_Driver/Inc/Legacy \ + -IDrivers/CMSIS/Device/ST/STM32L0xx/Include \ + -IDrivers/CMSIS/Include \ + -IMiddlewares/Third_Party/Lora/Core \ + -IMiddlewares/Third_Party/Lora/Crypto \ + -IMiddlewares/Third_Party/Lora/Mac \ + -IMiddlewares/Third_Party/Lora/Phy \ + -IMiddlewares/Third_Party/Lora/Utilities \ + -IMiddlewares/Third_Party/Lora/Mac/region \ + -IDrivers/BSP/Components/sx1272 + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -ggdb -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" + +CFLAGS += -D__weak="__attribute__((weak))" -D__packed="__attribute__((__packed__))" +CFLAGS += -std=gnu99 -Wfatal-errors +CFLAGS += -Wall -Wextra -Wshadow +CFLAGS += -Wwrite-strings -Wold-style-definition -Winline -Wno-missing-noreturn -Wstrict-prototypes +CFLAGS += -Wredundant-decls -Wfloat-equal -Wsign-compare +CFLAGS += -fno-common -ffunction-sections -fdata-sections -Wno-unused-function +CFLAGS += -MD -Wno-format-zero-length -Wno-redundant-decls -Wno-unused-parameter +CFLAGS += -Wno-discarded-qualifiers -Wno-unused-variable +CFLAGS += -Wno-float-equal -Wno-implicit-fallthrough +CFLAGS += -fmerge-constants -fmerge-all-constants -finline-small-functions -findirect-inlining + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32L073RZTx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections +# -specs=nano.specs + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +.PHONY: flash dis + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + @$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + @$(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + @$(CC) $(OBJECTS) $(LDFLAGS) -o $@ + @$(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + @$(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + @$(BIN) $< $@ + +$(BUILD_DIR): + @mkdir -p $@ + +flash: $(BUILD_DIR)/$(TARGET).bin + @printf " FLASH $<\n" + @st-flash write $< 0x8000000 + +dis: $(BUILD_DIR)/$(TARGET).elf + @arm-none-eabi-objdump -Sslrtd build/mf103.elf > disassembly.lst + +####################################### +# clean up +####################################### +clean: + -rm -fR .dep $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/Middlewares/Third_Party/Lora/Core/lora.c b/Middlewares/Third_Party/Lora/Core/lora.c index 2a0ce6f..0cd34cb 100755 --- a/Middlewares/Third_Party/Lora/Core/lora.c +++ b/Middlewares/Third_Party/Lora/Core/lora.c @@ -179,7 +179,7 @@ struct ComplianceTest_s /*! * \brief Prepares the payload of the frame */ -static void PrepareTxFrame( ) +static void PrepareTxFrame( void) { if( ComplianceTest.Running == true ) { @@ -260,15 +260,15 @@ static bool SendFrame( void ) void OnSendEvent( void ) { - MibRequestConfirm_t mibReq; + MibRequestConfirm_t _mibReq; LoRaMacStatus_t status; - mibReq.Type = MIB_NETWORK_JOINED; - status = LoRaMacMibGetRequestConfirm( &mibReq ); + _mibReq.Type = MIB_NETWORK_JOINED; + status = LoRaMacMibGetRequestConfirm( &_mibReq ); if( status == LORAMAC_STATUS_OK ) { - if( mibReq.Param.IsNetworkJoined == true ) + if( _mibReq.Param.IsNetworkJoined == true ) { DeviceState = DEVICE_STATE_SEND; NextTx = true; @@ -399,10 +399,10 @@ static void McpsIndication( McpsIndication_t *mcpsIndication ) ComplianceTest.Running = true; ComplianceTest.State = 1; - MibRequestConfirm_t mibReq; - mibReq.Type = MIB_ADR; - mibReq.Param.AdrEnable = true; - LoRaMacMibSetRequestConfirm( &mibReq ); + MibRequestConfirm_t _mibReq; + _mibReq.Type = MIB_ADR; + _mibReq.Param.AdrEnable = true; + LoRaMacMibSetRequestConfirm( &_mibReq ); #if defined( REGION_EU868 ) LoRaMacTestSetDutyCycleOn( false ); @@ -418,10 +418,10 @@ static void McpsIndication( McpsIndication_t *mcpsIndication ) ComplianceTest.DownLinkCounter = 0; ComplianceTest.Running = false; - MibRequestConfirm_t mibReq; - mibReq.Type = MIB_ADR; - mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; - LoRaMacMibSetRequestConfirm( &mibReq ); + MibRequestConfirm_t _mibReq; + _mibReq.Type = MIB_ADR; + _mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + LoRaMacMibSetRequestConfirm( &_mibReq ); #if defined( REGION_EU868 ) LoRaMacTestSetDutyCycleOn( LORAWAN_DUTYCYCLE_ON ); #endif diff --git a/Src/debug.c b/Src/debug.c index e12ea95..b5f0cd9 100755 --- a/Src/debug.c +++ b/Src/debug.c @@ -103,6 +103,7 @@ void DBG_Init( void ) #endif } +#if 0 /** * @brief Error_Handler * @param None @@ -113,6 +114,15 @@ void Error_Handler(void) DBG_PRINTF("Error_Handler\n\r"); while(1); } +#endif + +void _Error_Handler(char * file, int line) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + PRINTF("INIT ERROR, %s:%d", file, (uint16_t) line); + /* USER CODE END Error_Handler_Debug */ +} + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Src/hw_i2c.c b/Src/hw_i2c.c new file mode 100644 index 0000000..834e4cd --- /dev/null +++ b/Src/hw_i2c.c @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * File Name : I2C.c + * Description : This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2017 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hw.h" +#include "hw_i2c.h" +#include "debug.h" + +static inline uint32_t setupTiming(void) +{ + const uint32_t presc = 15; + + // delays + const uint32_t sdadel = 2; + const uint32_t scldel = 2; + + const uint32_t scll = 6; + const uint32_t sclh = 7; + + return presc << I2C_TIMINGR_PRESC_Pos | + scldel << I2C_TIMINGR_SCLDEL_Pos | + sdadel << I2C_TIMINGR_SDADEL_Pos | + sclh << I2C_TIMINGR_SCLH_Pos | + scll << I2C_TIMINGR_SCLL_Pos; +} + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = setupTiming(); //0x00000708; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Src/main.c b/Src/main.c index 8a3e5c3..4f07c41 100755 --- a/Src/main.c +++ b/Src/main.c @@ -59,12 +59,16 @@ Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene */ /* Includes ------------------------------------------------------------------*/ +#include +#include +#include "stm32l0xx_ll_i2c.h" #include "hw.h" #include "low_power.h" #include "lora.h" //#include "bsp.h" #include "timeServer.h" #include "vcom.h" +#include "voc_sensor.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -137,6 +141,185 @@ static LoRaParam_t LoRaParamInit = {TX_ON_TIMER, /* Private functions ---------------------------------------------------------*/ +#if 0 +typedef enum { + i2cSpeed_std, + i2cSpeed_fast, + i2cSpeed_fastPlus, + i2cSpeed_count, +} i2cSpeed_t; + +void i2cInit(I2C_TypeDef *i2c, i2cSpeed_t spd); + +#define I2C_7BIT_ADDR (0 << 31) +#define I2C_10BIT_ADDR (1 << 31) + +// Returns number of bytes written +uint32_t i2cWrite(I2C_TypeDef *i2c, uint32_t addr, uint8_t *txBuffer, + uint32_t len); + +// Returns number of bytes read +uint32_t i2cRead(I2C_TypeDef *i2c, uint8_t addr, uint8_t *rxBuffer, + uint32_t numBytes); + +#define I2C_READ 0 +#define I2C_WRITE 1 + +static uint32_t setupTiming(i2cSpeed_t spd, uint32_t clockFreq) { + (void) spd; + (void) clockFreq; + uint32_t presc = 0; + uint32_t sdadel = 2; + uint32_t scldel = 2; + uint32_t scll = 6; + uint32_t sclh = 7; + + return presc << 28 | + scldel << 20 | + sdadel << 16 | + sclh << 8 | + scll; +} + +void i2cInit(I2C_TypeDef *i2c, i2cSpeed_t spd) { + // Setup timing register + i2c->TIMINGR = setupTiming(spd, SystemCoreClock); + + // Reset state + i2c->CR1 &= ~I2C_CR1_PE; +} + +static uint32_t i2cSetup(uint32_t addr, uint8_t direction) { + uint32_t ret = 0; + if (addr & I2C_10BIT_ADDR) { + ret = (addr & 0x000003FF) | I2C_CR2_ADD10; + } else { + // 7 Bit Address + ret = (addr & 0x0000007F) << 1; + } + + if (direction == I2C_READ) { + ret |= I2C_CR2_RD_WRN; + if (addr & I2C_10BIT_ADDR) { + ret |= I2C_CR2_HEAD10R; + } + } + + return ret; +} + +// Will return the number of data bytes written to the device +uint32_t i2cWrite(I2C_TypeDef *i2c, uint32_t addr, uint8_t *txBuffer, + uint32_t len) { + + uint32_t numTxBytes = 0; + + i2c->CR1 &= ~I2C_CR1_PE; + i2c->CR2 = 0; + + i2c->CR2 = i2cSetup(addr, I2C_WRITE); + + if (len > 0xFF) { + i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + } else { + i2c->CR2 |= ((len & 0xFF) << 16) | I2C_CR2_AUTOEND; + } + i2c->CR1 |= I2C_CR1_PE; + i2c->CR2 |= I2C_CR2_START; + while(i2c->CR2 & I2C_CR2_START); + uint8_t done = 0; + uint32_t i = 0; + while (!done && i < 0x0000001F) { + i++; + if (i2c->ISR & I2C_ISR_NACKF) { + // Was not acknowledged, disable device and exit + done = 1; + } + + if (i2c->ISR & I2C_ISR_TXIS) { + // Device acknowledged and we must send the next byte + if (numTxBytes < len){ + i2c->TXDR = txBuffer[numTxBytes++]; + } + + i = 0; + + } + + if (i2c->ISR & I2C_ISR_TC) { + done = 1; + } + + if (i2c->ISR & I2C_ISR_TCR) { + i = 0; + if ((len - numTxBytes) > 0xFF) { + i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + } else { + i2c->CR2 &= ~(0x00FF0000 | I2C_CR2_RELOAD); + i2c->CR2 |= ((len - numTxBytes) & 0xFF) << 16 | + I2C_CR2_AUTOEND; + } + } + + } + i2c->CR1 &= ~I2C_CR1_PE; + return numTxBytes; +} + +uint32_t i2cRead(I2C_TypeDef *i2c, uint8_t addr, uint8_t *rxBuffer, + uint32_t numBytes) { + + uint32_t numRxBytes = 0; + + i2c->CR1 &= ~I2C_CR1_PE; + i2c->CR2 = 0; + + i2c->CR2 = i2cSetup(addr, I2C_READ); + + if (numBytes > 0xFF) { + i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + } else { + i2c->CR2 |= ((numBytes & 0xFF) << 16) | I2C_CR2_AUTOEND; + } + i2c->CR1 |= I2C_CR1_PE; + i2c->CR2 |= I2C_CR2_START; + + while(i2c->CR2 & I2C_CR2_START); + uint8_t done = 0; + uint32_t i = 0; + while (!done && i < 0x0000001F) { + i++; + + if (i2c->ISR & I2C_ISR_RXNE) { + // Device acknowledged and we must send the next byte + if (numRxBytes < numBytes){ + rxBuffer[numRxBytes++] = i2c->RXDR; + } + + i = 0; + } + + if (i2c->ISR & I2C_ISR_TC) { + done = 1; + } + + if (i2c->ISR & I2C_ISR_TCR) { + i = 0; + if ((numBytes - numRxBytes) > 0xFF) { + i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + } else { + i2c->CR2 &= ~(0x00FF0000 | I2C_CR2_RELOAD); + i2c->CR2 |= ((numBytes - numRxBytes) & 0xFF) << 16 | + I2C_CR2_AUTOEND; + } + } + + } + i2c->CR1 &= ~I2C_CR1_PE; + return numRxBytes; +} +#endif + /** * @brief Main program @@ -154,11 +337,29 @@ int main(void) /* Configure the debug mode*/ DBG_Init(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + /* Configure the hardware*/ HW_Init(); + MX_I2C1_Init(); + + // BLINKY + GPIO_InitTypeDef initStruct = { 0 }; + initStruct.Mode =GPIO_MODE_OUTPUT_PP; + initStruct.Pull = GPIO_NOPULL; + initStruct.Speed = GPIO_SPEED_HIGH; + HW_GPIO_Init(GPIOC, GPIO_PIN_7, &initStruct); /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + voc_init(); + + while(1) { + GPIOC->ODR ^= 1<<7; + voc_measure(); + } +#if 0 /* Configure the Lora Stack*/ lora_Init(&LoRaMainCallbacks, &LoRaParamInit); @@ -184,6 +385,7 @@ int main(void) /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ } +#endif } static void LoraTxData(lora_AppData_t *AppData, FunctionalState *IsTxConfirmed) @@ -219,5 +421,4 @@ static void LoraRxData(lora_AppData_t *AppData) } /* USER CODE END 4 */ } - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Src/stm32l0xx_it.c b/Src/stm32l0xx_it.c index ff0e2d9..5a8899b 100755 --- a/Src/stm32l0xx_it.c +++ b/Src/stm32l0xx_it.c @@ -102,6 +102,7 @@ void NMI_Handler(void) void HardFault_Handler(void) { + PRINTF("\r\nHARDFAULT!\r\n"); while(1) { __NOP(); diff --git a/Src/voc_sensor.c b/Src/voc_sensor.c new file mode 100644 index 0000000..bd647cf --- /dev/null +++ b/Src/voc_sensor.c @@ -0,0 +1,197 @@ +// +// Created by MightyPork on 2017/11/17. +// + +#include +#include +#include "voc_sensor.h" + +struct bme680_dev gas_sensor; + +static void user_delay_ms(uint32_t period) +{ + /* + * Return control or wait, + * for a period amount of milliseconds + */ + HAL_Delay(period); +} + +#if 0 +static int8_t user_spi_read(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) +{ + int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + + /* + * The parameter dev_id can be used as a variable to select which Chip Select pin has + * to be set low to activate the relevant device on the SPI bus + */ + + /* + * Data on the bus should be like + * |----------------+---------------------+-------------| + * | MOSI | MISO | Chip Select | + * |----------------+---------------------|-------------| + * | (don't care) | (don't care) | HIGH | + * | (reg_addr) | (don't care) | LOW | + * | (don't care) | (reg_data[0]) | LOW | + * | (....) | (....) | LOW | + * | (don't care) | (reg_data[len - 1]) | LOW | + * | (don't care) | (don't care) | HIGH | + * |----------------+---------------------|-------------| + */ + + return rslt; +} + +static int8_t user_spi_write(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) +{ + int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + + /* + * The parameter dev_id can be used as a variable to select which Chip Select pin has + * to be set low to activate the relevant device on the SPI bus + */ + + /* + * Data on the bus should be like + * |---------------------+--------------+-------------| + * | MOSI | MISO | Chip Select | + * |---------------------+--------------|-------------| + * | (don't care) | (don't care) | HIGH | + * | (reg_addr) | (don't care) | LOW | + * | (reg_data[0]) | (don't care) | LOW | + * | (....) | (....) | LOW | + * | (reg_data[len - 1]) | (don't care) | LOW | + * | (don't care) | (don't care) | HIGH | + * |---------------------+--------------|-------------| + */ + + return rslt; +} +#endif + +static int8_t user_i2c_read(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) +{ + int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + + /* + * The parameter dev_id can be used as a variable to store the I2C address of the device + */ + + /* + * Data on the bus should be like + * |------------+---------------------| + * | I2C action | Data | + * |------------+---------------------| + * | Start | - | + * | Write | (reg_addr) | + * | Stop | - | + * | Start | - | + * | Read | (reg_data[0]) | + * | Read | (....) | + * | Read | (reg_data[len - 1]) | + * | Stop | - | + * |------------+---------------------| + */ + HAL_I2C_Master_Transmit(&hi2c1, dev_id<<1, ®_addr, 1, 100); + HAL_I2C_Master_Receive(&hi2c1, dev_id<<1, reg_data, len, 100); + + return rslt; +} + +static int8_t user_i2c_write(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) +{ + /* + * The parameter dev_id can be used as a variable to store the I2C address of the device + */ + + /* + * Data on the bus should be like + * |------------+---------------------| + * | I2C action | Data | + * |------------+---------------------| + * | Start | - | + * | Write | (reg_addr) | + * | Write | (reg_data[0]) | + * | Write | (....) | + * | Write | (reg_data[len - 1]) | + * | Stop | - | + * |------------+---------------------| + */ + uint8_t data[64]; + data[0] = reg_addr; + for (int i = 0; i < len; i++) { + data[i+1] = reg_data[i]; + } + HAL_I2C_Master_Transmit(&hi2c1, dev_id<<1, &data[0], (uint16_t) (len + 1), 100); + + return BME680_OK; +} + + +void voc_init(void) +{ + int8_t rslt; + gas_sensor.dev_id = BME680_I2C_ADDR_PRIMARY; + gas_sensor.intf = BME680_I2C_INTF; + gas_sensor.read = user_i2c_read; + gas_sensor.write = user_i2c_write; + gas_sensor.delay_ms = user_delay_ms; + + PRINTF("BME680 initializing...\r\n"); + rslt = bme680_init(&gas_sensor); + assert_param(rslt == BME680_OK); + + + PRINTF("BME680 configuring...\r\n"); + /* Set the temperature, pressure and humidity settings */ + gas_sensor.tph_sett.os_hum = BME680_OS_2X; + gas_sensor.tph_sett.os_pres = BME680_OS_4X; + gas_sensor.tph_sett.os_temp = BME680_OS_8X; + gas_sensor.tph_sett.filter = BME680_FILTER_SIZE_3; + + /* Set the remaining gas sensor settings and link the heating profile */ + gas_sensor.gas_sett.run_gas = BME680_ENABLE_GAS_MEAS; + /* Create a ramp heat waveform in 3 steps */ + gas_sensor.gas_sett.heatr_temp = 320; /* degree Celsius */ + gas_sensor.gas_sett.heatr_dur = 150; /* milliseconds */ + + /* Select the power mode */ + /* Must be set before writing the sensor configuration */ + gas_sensor.power_mode = BME680_FORCED_MODE; + + /* Set the required sensor settings needed */ + uint8_t set_required_settings = BME680_OST_SEL | BME680_OSP_SEL | BME680_OSH_SEL | BME680_FILTER_SEL | BME680_GAS_SENSOR_SEL; + + /* Set the desired sensor configuration */ + rslt = bme680_set_sensor_settings(set_required_settings,&gas_sensor); + assert_param(rslt == BME680_OK); +} + +void voc_measure(void) +{ + /* Set the power mode */ + int8_t rslt; + + rslt = bme680_set_sensor_mode(&gas_sensor); + assert_param(rslt == BME680_OK); + + /* Get the total measurement duration so as to sleep or wait till the + * measurement is complete */ + uint16_t meas_period; + bme680_get_profile_dur(&meas_period, &gas_sensor); + HAL_Delay(meas_period); /* Delay till the measurement is ready */ + struct bme680_field_data data; + + rslt = bme680_get_sensor_data(&data, &gas_sensor); + assert_param(rslt == BME680_OK); + + PRINTF("T: %.2f degC, P: %.2f hPa, H %.2f %%rH ", data.temperature / 100.0f, + data.pressure / 100.0f, data.humidity / 1000.0f ); + /* Avoid using measurements from an unstable heating setup */ + if(data.status & BME680_GASM_VALID_MSK) + PRINTF(", G: %d ohms", data.gas_resistance); + + PRINTF("\r\n"); +} diff --git a/Src/voc_sensor.h b/Src/voc_sensor.h new file mode 100644 index 0000000..247d00a --- /dev/null +++ b/Src/voc_sensor.h @@ -0,0 +1,15 @@ +// +// Created by MightyPork on 2017/11/17. +// + +#ifndef PROJ_VOC_SENSOR_H +#define PROJ_VOC_SENSOR_H + +#include "../Drivers/BME680/bme680.h" + +extern struct bme680_dev gas_sensor; + +void voc_init(void); +void voc_measure(void); + +#endif //PROJ_VOC_SENSOR_H diff --git a/build/LoRaMac.d b/build/LoRaMac.d new file mode 100644 index 0000000..d370249 --- /dev/null +++ b/build/LoRaMac.d @@ -0,0 +1,43 @@ +build/LoRaMac.d: Middlewares/Third_Party/Lora/Mac/LoRaMac.c \ + Middlewares/Third_Party/Lora/Phy/radio.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Mac/region/Region.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h Inc/debug.h \ + Inc/hw_conf.h Inc/vcom.h Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h + +Middlewares/Third_Party/Lora/Phy/radio.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Mac/region/Region.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h: + +Inc/debug.h: + +Inc/hw_conf.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h: diff --git a/build/LoRaMac.lst b/build/LoRaMac.lst new file mode 100644 index 0000000..8980de7 --- /dev/null +++ b/build/LoRaMac.lst @@ -0,0 +1,13841 @@ +ARM GAS /tmp/ccrFaSdZ.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "LoRaMac.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.ResetMacParameters,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 ResetMacParameters: + 23 .LFB104: + 24 .file 1 "./Middlewares/Third_Party/Lora/Mac/LoRaMac.c" + 1:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /* + 2:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ___ _____ _ ___ _ _____ ___ ___ ___ ___ + 9:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + 10:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + 11:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + 12:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** embedded.connectivity.solutions=============== + 13:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 14:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Description: LoRa MAC layer implementation + 15:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 16:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 17:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 18:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) + 19:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 20:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 21:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 22:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include + 23:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include + 24:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include + 25:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "radio.h" + 26:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "timeServer.h" + 27:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "LoRaMac.h" + 28:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "region/Region.h" + 29:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "LoRaMacCrypto.h" + 30:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 31:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "debug.h" + 32:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #include "LoRaMacTest.h" + 33:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 34:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 2 + + + 35:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 36:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 37:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Maximum PHY layer payload size + 38:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 39:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define LORAMAC_PHY_MAXPAYLOAD 255 + 40:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 41:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 42:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Maximum MAC commands buffer size + 43:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 44:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define LORA_MAC_COMMAND_MAX_LENGTH 128 + 45:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 46:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 47:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Maximum length of the fOpts field + 48:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 49:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define LORA_MAC_COMMAND_MAX_FOPTS_LENGTH 15 + 50:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 51:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 52:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac region. + 53:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 54:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacRegion_t LoRaMacRegion; + 55:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 56:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 57:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac duty cycle for the back-off procedure during the first hour. + 58:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 59:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define BACKOFF_DC_1_HOUR 100 + 60:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 61:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 62:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac duty cycle for the back-off procedure during the next 10 hours. + 63:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 64:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define BACKOFF_DC_10_HOURS 1000 + 65:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 66:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 67:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac duty cycle for the back-off procedure during the next 24 hours. + 68:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 69:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** #define BACKOFF_DC_24_HOURS 10000 + 70:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 71:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 72:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Device IEEE EUI + 73:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 74:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t *LoRaMacDevEui; + 75:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 76:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 77:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Application IEEE EUI + 78:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 79:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t *LoRaMacAppEui; + 80:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 81:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 82:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * AES encryption/decryption cipher application key + 83:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 84:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t *LoRaMacAppKey; + 85:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 86:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 87:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * AES encryption/decryption cipher network session key + 88:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 89:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LoRaMacNwkSKey[] = + 90:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 91:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ARM GAS /tmp/ccrFaSdZ.s page 3 + + + 92:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 93:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** }; + 94:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 95:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 96:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * AES encryption/decryption cipher application session key + 97:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 98:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LoRaMacAppSKey[] = + 99:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 101:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 102:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** }; + 103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 104:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Device nonce is a random value extracted by issuing a sequence of RSSI + 106:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * measurements + 107:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 108:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint16_t LoRaMacDevNonce; + 109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Network ID ( 3 bytes ) + 112:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t LoRaMacNetID; + 114:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 115:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Mote Address + 117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 118:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t LoRaMacDevAddr; + 119:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 120:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Multicast channels linked list + 122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 123:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static MulticastParams_t *MulticastChannels = NULL; + 124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 125:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Actual device class + 127:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static DeviceClass_t LoRaMacDeviceClass; + 129:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 130:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 131:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Indicates if the node is connected to a private or public network + 132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool PublicNetwork; + 134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 135:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 136:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Indicates if the node supports repeaters + 137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool RepeaterSupport; + 139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 141:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Buffer containing the data to be sent or received. + 142:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 143:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LoRaMacBuffer[LORAMAC_PHY_MAXPAYLOAD]; + 144:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 145:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 146:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Length of packet in LoRaMacBuffer + 147:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint16_t LoRaMacBufferPktLen = 0; + ARM GAS /tmp/ccrFaSdZ.s page 4 + + + 149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 150:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Length of the payload in LoRaMacBuffer + 152:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LoRaMacTxPayloadLen = 0; + 154:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 155:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Buffer containing the upper layer data. + 157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 158:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LoRaMacRxPayload[LORAMAC_PHY_MAXPAYLOAD]; + 159:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 160:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 161:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMAC frame counter. Each time a packet is sent the counter is incremented. + 162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Only the 16 LSB bits are sent + 163:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t UpLinkCounter = 0; + 165:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMAC frame counter. Each time a packet is received the counter is incremented. + 168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Only the 16 LSB bits are received + 169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 170:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t DownLinkCounter = 0; + 171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 172:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * IsPacketCounterFixed enables the MIC field tests by fixing the + 174:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * UpLinkCounter value + 175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 176:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool IsUpLinkCounterFixed = false; + 177:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 178:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Used for test purposes. Disables the opening of the reception windows. + 180:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool IsRxWindowsEnabled = true; + 182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 183:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Indicates if the MAC layer has already joined a network. + 185:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool IsLoRaMacNetworkJoined = false; + 187:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 188:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 189:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac ADR control status + 190:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool AdrCtrlOn = false; + 192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 193:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 194:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Counts the number of missed ADR acknowledgements + 195:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 196:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t AdrAckCounter = 0; + 197:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * If the node has sent a FRAME_TYPE_DATA_CONFIRMED_UP this variable indicates + 200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * if the nodes needs to manage the server acknowledgement. + 201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 202:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool NodeAckRequested = false; + 203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 204:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 205:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * If the server has sent a FRAME_TYPE_DATA_CONFIRMED_DOWN this variable indicates + ARM GAS /tmp/ccrFaSdZ.s page 5 + + + 206:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * if the ACK bit must be set for the next transmission + 207:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 208:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool SrvAckRequested = false; + 209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 211:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Indicates if the MAC layer wants to send MAC commands + 212:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 213:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool MacCommandsInNextTx = false; + 214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 215:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 216:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Contains the current MacCommandsBuffer index + 217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 218:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MacCommandsBufferIndex = 0; + 219:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 221:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Contains the current MacCommandsBuffer index for MAC commands to repeat + 222:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MacCommandsBufferToRepeatIndex = 0; + 224:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 225:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 226:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Buffer containing the MAC layer commands + 227:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MacCommandsBuffer[LORA_MAC_COMMAND_MAX_LENGTH]; + 229:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 230:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 231:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Buffer containing the MAC layer commands which must be repeated + 232:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 233:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MacCommandsBufferToRepeat[LORA_MAC_COMMAND_MAX_LENGTH]; + 234:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 235:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 236:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac parameters + 237:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 238:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams_t LoRaMacParams; + 239:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 240:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac default parameters + 242:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 243:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams_t LoRaMacParamsDefaults; + 244:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 246:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Uplink messages repetitions counter + 247:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 248:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t ChannelsNbRepCounter = 0; + 249:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 250:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Maximum duty cycle + 252:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark Possibility to shutdown the device. + 253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 254:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MaxDCycle = 0; + 255:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 256:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Aggregated duty cycle management + 258:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 259:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint16_t AggregatedDCycle; + 260:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerTime_t AggregatedLastTxDoneTime; + 261:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerTime_t AggregatedTimeOff; + 262:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 6 + + + 263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 264:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Enables/Disables duty cycle management (Test only) + 265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 266:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool DutyCycleOn; + 267:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 268:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 269:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Current channel index + 270:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t Channel; + 272:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 273:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 274:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Current channel index + 275:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 276:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t LastTxChannel; + 277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 278:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 279:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Set to true, if the last uplink was a join request + 280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 281:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool LastTxIsJoinRequest; + 282:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 283:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 284:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Stores the time at LoRaMac initialization. + 285:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 286:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark Used for the BACKOFF_DC computation. + 287:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 288:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerTime_t LoRaMacInitializationTime = 0; + 289:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 290:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 291:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac internal states + 292:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** enum eLoRaMacState + 294:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 295:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_IDLE = 0x00000000, + 296:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_TX_RUNNING = 0x00000001, + 297:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_RX = 0x00000002, + 298:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_ACK_REQ = 0x00000004, + 299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_ACK_RETRY = 0x00000008, + 300:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_TX_DELAYED = 0x00000010, + 301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_TX_CONFIG = 0x00000020, + 302:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LORAMAC_RX_ABORT = 0x00000040, + 303:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** }; + 304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 305:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 306:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac internal state + 307:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 308:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t LoRaMacState = LORAMAC_IDLE; + 309:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 310:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac timer used to check the LoRaMacState (runs every second) + 312:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 313:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerEvent_t MacStateCheckTimer; + 314:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac upper layer event functions + 317:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacPrimitives_t *LoRaMacPrimitives; + 319:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 7 + + + 320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 321:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac upper layer callback functions + 322:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 323:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacCallback_t *LoRaMacCallbacks; + 324:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 325:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 326:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Radio events function pointer + 327:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 328:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static RadioEvents_t RadioEvents; + 329:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 330:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 331:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac duty cycle delayed Tx timer + 332:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 333:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerEvent_t TxDelayedTimer; + 334:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 335:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 336:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac reception windows timers + 337:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 338:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerEvent_t RxWindowTimer1; + 339:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerEvent_t RxWindowTimer2; + 340:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 341:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 342:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac reception windows delay + 343:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark normal frame: RxWindowXDelay = ReceiveDelayX - RADIO_WAKEUP_TIME + 344:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * join frame : RxWindowXDelay = JoinAcceptDelayX - RADIO_WAKEUP_TIME + 345:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 346:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t RxWindow1Delay; + 347:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint32_t RxWindow2Delay; + 348:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 349:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 350:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac Rx windows configuration + 351:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 352:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static RxConfigParams_t RxWindow1Config; + 353:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static RxConfigParams_t RxWindow2Config; + 354:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 355:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 356:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Acknowledge timeout timer. Used for packet retransmissions. + 357:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 358:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static TimerEvent_t AckTimeoutTimer; + 359:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 360:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 361:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Number of trials to get a frame acknowledged + 362:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 363:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t AckTimeoutRetries = 1; + 364:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 365:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 366:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Number of trials to get a frame acknowledged + 367:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 368:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t AckTimeoutRetriesCounter = 1; + 369:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 370:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 371:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Indicates if the AckTimeout timer has expired or not + 372:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 373:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool AckTimeoutRetry = false; + 374:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 375:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 376:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Last transmission time on air + ARM GAS /tmp/ccrFaSdZ.s page 8 + + + 377:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 378:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerTime_t TxTimeOnAir = 0; + 379:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 380:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 381:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Number of trials for the Join Request + 382:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 383:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t JoinRequestTrials; + 384:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 385:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 386:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Maximum number of trials for the Join Request + 387:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 388:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t MaxJoinRequestTrials; + 389:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 390:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 391:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Structure to hold an MCPS indication data. + 392:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 393:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static McpsIndication_t McpsIndication; + 394:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 395:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 396:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Structure to hold MCPS confirm data. + 397:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 398:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static McpsConfirm_t McpsConfirm; + 399:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 400:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 401:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Structure to hold MLME confirm data. + 402:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 403:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static MlmeConfirm_t MlmeConfirm; + 404:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 405:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 406:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * Holds the current rx window slot + 407:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 408:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t RxSlot = 0; + 409:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 410:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 411:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMac tx/rx operation state + 412:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 413:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags_t LoRaMacFlags; + 414:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 415:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 416:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function to be executed on Radio Tx Done event + 417:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 418:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioTxDone( void ); + 419:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 420:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 421:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief This function prepares the MAC to abort the execution of function + 422:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * OnRadioRxDone in case of a reception error. + 423:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 424:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void PrepareRxDoneAbort( void ); + 425:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 426:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 427:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function to be executed on Radio Rx Done event + 428:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 429:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); + 430:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 431:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 432:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on Radio Tx Timeout event + 433:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + ARM GAS /tmp/ccrFaSdZ.s page 9 + + + 434:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioTxTimeout( void ); + 435:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 436:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 437:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on Radio Rx error event + 438:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 439:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxError( void ); + 440:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 441:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 442:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on Radio Rx Timeout event + 443:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 444:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxTimeout( void ); + 445:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 446:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 447:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on Resend Frame timer event. + 448:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 449:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnMacStateCheckTimerEvent( void ); + 450:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 451:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 452:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on duty cycle delayed Tx timer event + 453:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 454:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnTxDelayedTimerEvent( void ); + 455:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 456:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 457:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on first Rx window timer event + 458:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 459:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRxWindow1TimerEvent( void ); + 460:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 461:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 462:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on second Rx window timer event + 463:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 464:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRxWindow2TimerEvent( void ); + 465:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 466:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 467:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Function executed on AckTimeout timer event + 468:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 469:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnAckTimeoutTimerEvent( void ); + 470:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 471:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 472:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Initializes and opens the reception window + 473:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 474:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] rxContinuous Set to true, if the RX is in continuous mode + 475:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] maxRxWindow Maximum RX window timeout + 476:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 477:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void RxWindowSetup( bool rxContinuous, uint32_t maxRxWindow ); + 478:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 479:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 480:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Adds a new MAC command to be sent. + 481:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 482:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \Remark MAC layer internal function + 483:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 484:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [in] cmd MAC command to be added + 485:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * [MOTE_MAC_LINK_CHECK_REQ, + 486:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * MOTE_MAC_LINK_ADR_ANS, + 487:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * MOTE_MAC_DUTY_CYCLE_ANS, + 488:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * MOTE_MAC_RX2_PARAM_SET_ANS, + 489:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * MOTE_MAC_DEV_STATUS_ANS + 490:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * MOTE_MAC_NEW_CHANNEL_ANS] + ARM GAS /tmp/ccrFaSdZ.s page 10 + + + 491:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [in] p1 1st parameter ( optional depends on the command ) + 492:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [in] p2 2nd parameter ( optional depends on the command ) + 493:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 494:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Function status [0: OK, 1: Unknown command, 2: Buffer full] + 495:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 496:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacStatus_t AddMacCommand( uint8_t cmd, uint8_t p1, uint8_t p2 ); + 497:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 498:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 499:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Parses the MAC commands which must be repeated. + 500:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 501:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \Remark MAC layer internal function + 502:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 503:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] cmdBufIn Buffer which stores the MAC commands to send + 504:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] length Length of the input buffer to parse + 505:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [OUT] cmdBufOut Buffer which stores the MAC commands which must be + 506:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * repeated. + 507:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval Size of the MAC commands to repeat. + 509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t ParseMacCommandsToRepeat( uint8_t* cmdBufIn, uint8_t length, uint8_t* cmdBufOut ); + 511:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 512:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 513:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Validates if the payload fits into the frame, taking the datarate + 514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * into account. + 515:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 516:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \details Refer to chapter 4.3.2 of the LoRaWAN specification, v1.0 + 517:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 518:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param lenN Length of the application payload. The length depends on the + 519:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * datarate and is region specific + 520:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 521:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param datarate Current datarate + 522:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 523:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param fOptsLen Length of the fOpts field + 524:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 525:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval [false: payload does not fit into the frame, true: payload fits into + 526:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * the frame] + 527:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 528:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool ValidatePayloadLength( uint8_t lenN, int8_t datarate, uint8_t fOptsLen ); + 529:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 530:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 531:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Decodes MAC commands in the fOpts field and in the payload + 532:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 533:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void ProcessMacCommands( uint8_t *payload, uint8_t macIndex, uint8_t commandsSize, uint8_t s + 534:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 535:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 536:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief LoRaMAC layer generic send frame + 537:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 538:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] macHdr MAC header field + 539:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fPort MAC payload port + 540:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fBuffer MAC data buffer to be sent + 541:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fBufferSize MAC data buffer size + 542:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Status of the operation. + 543:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 544:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t Send( LoRaMacHeader_t *macHdr, uint8_t fPort, void *fBuffer, uint16_t fBufferSize ) + 545:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 546:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 547:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief LoRaMAC layer frame buffer initialization + ARM GAS /tmp/ccrFaSdZ.s page 11 + + + 548:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 549:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] macHdr MAC header field + 550:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fCtrl MAC frame control field + 551:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fOpts MAC commands buffer + 552:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fPort MAC payload port + 553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fBuffer MAC data buffer to be sent + 554:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] fBufferSize MAC data buffer size + 555:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Status of the operation. + 556:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 557:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t PrepareFrame( LoRaMacHeader_t *macHdr, LoRaMacFrameCtrl_t *fCtrl, uint8_t fPort, vo + 558:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 559:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /* + 560:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Schedules the frame according to the duty cycle + 561:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 562:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval Status of the operation + 563:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 564:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacStatus_t ScheduleTx( void ); + 565:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 566:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /* + 567:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Calculates the back-off time for the band of a channel. + 568:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 569:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] channel The last Tx channel index + 570:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 571:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void CalculateBackOff( uint8_t channel ); + 572:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 573:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 574:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief LoRaMAC layer prepared frame buffer transmission with channel specification + 575:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 576:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark PrepareFrame must be called at least once before calling this + 577:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * function. + 578:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 579:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] channel Channel to transmit on + 580:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Status of the operation. + 581:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 582:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SendFrameOnChannel( uint8_t channel ); + 583:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 584:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 585:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Sets the radio in continuous transmission mode + 586:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 587:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark Uses the radio parameters set on the previous transmission. + 588:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 589:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] timeout Time in seconds while the radio is kept in continuous wave mode + 590:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Status of the operation. + 591:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 592:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SetTxContinuousWave( uint16_t timeout ); + 593:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 594:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 595:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Sets the radio in continuous transmission mode + 596:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 597:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \remark Uses the radio parameters set on the previous transmission. + 598:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * + 599:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] timeout Time in seconds while the radio is kept in continuous wave mode + 600:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] frequency RF frequency to be set. + 601:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \param [IN] power RF output power to be set. + 602:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \retval status Status of the operation. + 603:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 604:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SetTxContinuousWave1( uint16_t timeout, uint32_t frequency, uint8_t power ); + ARM GAS /tmp/ccrFaSdZ.s page 12 + + + 605:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 606:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /*! + 607:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * \brief Resets MAC specific parameters to default + 608:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** */ + 609:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void ResetMacParameters( void ); + 610:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 611:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioTxDone( void ) + 612:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 613:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 614:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; + 615:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** SetBandTxDoneParams_t txDone; + 616:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerTime_t curTime = TimerGetCurrentTime( ); + 617:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 618:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + 619:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 620:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); + 621:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 622:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 623:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 624:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); + 625:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 626:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 627:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Setup timers + 628:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsRxWindowsEnabled == true ) + 629:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 630:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &RxWindowTimer1, RxWindow1Delay ); + 631:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &RxWindowTimer1 ); + 632:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + 633:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 634:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &RxWindowTimer2, RxWindow2Delay ); + 635:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &RxWindowTimer2 ); + 636:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 637:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacDeviceClass == CLASS_C ) || ( NodeAckRequested == true ) ) + 638:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 639:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_ACK_TIMEOUT; + 640:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &AckTimeoutTimer, RxWindow2Delay + phyParam.Value ); + 642:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &AckTimeoutTimer ); + 643:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 644:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 645:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 646:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 647:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 648:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT; + 649:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 650:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Value == 0 ) + 651:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 652:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsReq = 1; + 653:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 654:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; + 655:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 656:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 657:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Verify if the last uplink was a join request + 658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN ) ) + 659:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 660:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LastTxIsJoinRequest = true; + 661:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 13 + + + 662:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 663:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 664:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LastTxIsJoinRequest = false; + 665:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 666:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 667:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Store last Tx channel + 668:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LastTxChannel = Channel; + 669:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update last tx done time for the current channel + 670:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txDone.Channel = Channel; + 671:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txDone.Joined = IsLoRaMacNetworkJoined; + 672:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txDone.LastTxDoneTime = curTime; + 673:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionSetBandTxDone( LoRaMacRegion, &txDone ); + 674:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update Aggregated last tx done time + 675:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedLastTxDoneTime = curTime; + 676:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 677:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == false ) + 678:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 679:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 680:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter++; + 681:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 682:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 683:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 684:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void PrepareRxDoneAbort( void ) + 685:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 686:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_RX_ABORT; + 687:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 688:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested ) + 689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 690:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnAckTimeoutTimerEvent( ); + 691:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 692:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 693:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsInd = 1; + 694:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; + 695:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 696:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Trig OnMacCheckTimerEvent call as soon as possible + 697:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, 1 ); + 698:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 699:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 700:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 701:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ) + 702:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 703:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + 704:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFrameCtrl_t fCtrl; + 705:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ApplyCFListParams_t applyCFList; + 706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 707:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** bool skipIndication = false; + 709:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 710:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t pktHeaderLen = 0; + 711:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t address = 0; + 712:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t appPayloadStartIndex = 0; + 713:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t port = 0xFF; + 714:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t frameLen = 0; + 715:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t mic = 0; + 716:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t micRx = 0; + 717:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 718:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t sequenceCounter = 0; + ARM GAS /tmp/ccrFaSdZ.s page 14 + + + 719:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t sequenceCounterPrev = 0; + 720:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t sequenceCounterDiff = 0; + 721:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t downLinkCounter = 0; + 722:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 723:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastParams_t *curMulticastParams = NULL; + 724:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t *nwkSKey = LoRaMacNwkSKey; + 725:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t *appSKey = LoRaMacAppSKey; + 726:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 727:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t multicast = 0; + 728:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 729:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** bool isMicOk = false; + 730:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 731:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; + 732:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Rssi = rssi; + 733:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Snr = snr; + 734:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxSlot = RxSlot; + 735:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Port = 0; + 736:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Multicast = 0; + 737:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.FramePending = 0; + 738:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = NULL; + 739:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = 0; + 740:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxData = false; + 741:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.AckReceived = false; + 742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = 0; + 743:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + 744:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 745:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); + 746:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer2 ); + 747:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 748:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Value = payload[pktHeaderLen++]; + 749:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 750:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( macHdr.Bits.MType ) + 751:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 752:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_JOIN_ACCEPT: + 753:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsLoRaMacNetworkJoined == true ) + 754:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 755:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + 756:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 757:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 758:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 759:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacJoinDecrypt( payload + 1, size - 1, LoRaMacAppKey, LoRaMacRxPayload + 1 ); + 760:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 761:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacRxPayload[0] = macHdr.Value; + 762:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 763:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacJoinComputeMic( LoRaMacRxPayload, size - LORAMAC_MFR_LEN, LoRaMacAppKey, &mic ); + 764:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 765:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN]; + 766:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 1] << 8 ); + 767:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 2] << 16 ); + 768:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 3] << 24 ); + 769:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 770:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( micRx == mic ) + 771:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 772:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacJoinComputeSKeys( LoRaMacAppKey, LoRaMacRxPayload + 1, LoRaMacDevNonce, LoRa + 773:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 774:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID = ( uint32_t )LoRaMacRxPayload[4]; + 775:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[5] << 8 ); + ARM GAS /tmp/ccrFaSdZ.s page 15 + + + 776:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[6] << 16 ); + 777:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 778:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr = ( uint32_t )LoRaMacRxPayload[7]; + 779:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[8] << 8 ); + 780:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[9] << 16 ); + 781:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[10] << 24 ); + 782:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 783:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // DLSettings + 784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx1DrOffset = ( LoRaMacRxPayload[11] >> 4 ) & 0x07; + 785:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate = LoRaMacRxPayload[11] & 0x0F; + 786:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 787:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // RxDelay + 788:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 = ( LoRaMacRxPayload[12] & 0x0F ); + 789:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacParams.ReceiveDelay1 == 0 ) + 790:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 791:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 = 1; + 792:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 793:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 *= 1000; + 794:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; + 795:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 796:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Apply CF list + 797:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** applyCFList.Payload = &LoRaMacRxPayload[13]; + 798:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Size of the regular payload is 12. Plus 1 byte MHDR and 4 bytes MIC + 799:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** applyCFList.Size = size - 17; + 800:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 801:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionApplyCFList( LoRaMacRegion, &applyCFList ); + 802:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 803:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 804:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsLoRaMacNetworkJoined = true; + 805:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + 806:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 807:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 808:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 809:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_JOIN_FAIL; + 810:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 811:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 812:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_DATA_CONFIRMED_DOWN: + 813:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_DATA_UNCONFIRMED_DOWN: + 814:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 815:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Check if the received payload size is valid + 816:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 817:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = McpsIndication.RxDatarate; + 818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD; + 819:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 820:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Get the maximum payload length + 821:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RepeaterSupport == true ) + 822:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 823:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; + 824:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 825:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 826:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MAX( 0, ( int16_t )( ( int16_t )size - ( int16_t )LORA_MAC_FRMPAYLOAD_OVERHEAD + 827:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 828:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + 829:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 830:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 831:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 832:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 16 + + + 833:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address = payload[pktHeaderLen++]; + 834:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 8 ); + 835:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 16 ); + 836:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 24 ); + 837:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 838:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( address != LoRaMacDevAddr ) + 839:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 840:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** curMulticastParams = MulticastChannels; + 841:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( curMulticastParams != NULL ) + 842:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 843:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( address == curMulticastParams->Address ) + 844:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 845:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** multicast = 1; + 846:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nwkSKey = curMulticastParams->NwkSKey; + 847:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appSKey = curMulticastParams->AppSKey; + 848:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = curMulticastParams->DownLinkCounter; + 849:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 850:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 851:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** curMulticastParams = curMulticastParams->Next; + 852:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 853:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( multicast == 0 ) + 854:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 855:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // We are not the destination of this frame. + 856:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ADDRESS_FAIL; + 857:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 858:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 859:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 860:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 861:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 862:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 863:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** multicast = 0; + 864:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nwkSKey = LoRaMacNwkSKey; + 865:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appSKey = LoRaMacAppSKey; + 866:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = DownLinkCounter; + 867:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 868:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 869:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Value = payload[pktHeaderLen++]; + 870:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 871:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounter = ( uint16_t )payload[pktHeaderLen++]; + 872:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounter |= ( uint16_t )payload[pktHeaderLen++] << 8; + 873:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 874:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appPayloadStartIndex = 8 + fCtrl.Bits.FOptsLen; + 875:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 876:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( uint32_t )payload[size - LORAMAC_MFR_LEN]; + 877:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 1] << 8 ); + 878:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 2] << 16 ); + 879:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 3] << 24 ); + 880:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 881:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounterPrev = ( uint16_t )downLinkCounter; + 882:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounterDiff = ( sequenceCounter - sequenceCounterPrev ); + 883:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 884:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( sequenceCounterDiff < ( 1 << 15 ) ) + 885:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 886:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter += sequenceCounterDiff; + 887:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK + 888:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( micRx == mic ) + 889:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 17 + + + 890:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** isMicOk = true; + 891:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 892:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 893:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 894:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 895:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // check for sequence roll-over + 896:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t downLinkCounterTmp = downLinkCounter + 0x10000 + ( int16_t )sequenceC + 897:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK + 898:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( micRx == mic ) + 899:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 900:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** isMicOk = true; + 901:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = downLinkCounterTmp; + 902:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 903:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 904:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 905:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Check for a the maximum allowed counter difference + 906:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_FCNT_GAP; + 907:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 908:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( sequenceCounterDiff >= phyParam.Value ) + 909:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 910:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_TOO_MANY_FRAMES_LOSS + 911:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 912:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 913:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 914:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 915:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 916:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( isMicOk == true ) + 917:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 918:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 919:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Multicast = multicast; + 920:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.FramePending = fCtrl.Bits.FPending; + 921:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = NULL; + 922:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = 0; + 923:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 924:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 925:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 926:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrAckCounter = 0; + 928:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = 0; + 929:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 930:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update 32 bits downlink counter + 931:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( multicast == 1 ) + 932:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 933:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_MULTICAST; + 934:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 935:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( curMulticastParams->DownLinkCounter == downLinkCounter ) && + 936:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( curMulticastParams->DownLinkCounter != 0 ) ) + 937:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 938:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_REPEATED; + 939:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 940:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 941:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 942:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** curMulticastParams->DownLinkCounter = downLinkCounter; + 944:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 945:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 946:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 18 + + + 947:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( macHdr.Bits.MType == FRAME_TYPE_DATA_CONFIRMED_DOWN ) + 948:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 949:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** SrvAckRequested = true; + 950:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_CONFIRMED; + 951:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 952:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( DownLinkCounter == downLinkCounter ) && + 953:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 954:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 955:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Duplicated confirmed downlink. Skip indication. + 956:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // In this case, the MAC layer shall accept the MAC commands + 957:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // which are included in the downlink retransmission. + 958:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // It should not provide the same frame to the application + 959:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // layer again. + 960:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** skipIndication = true; + 961:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 962:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 963:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 964:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 965:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** SrvAckRequested = false; + 966:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + 967:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 968:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( DownLinkCounter == downLinkCounter ) && + 969:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 970:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 971:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_REPEATED + 972:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 973:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 974:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 975:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 976:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 977:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DownLinkCounter = downLinkCounter; + 978:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 979:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 980:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // This must be done before parsing the payload and the MAC commands. + 981:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // We need to reset the MacCommandsBufferIndex here, since we need + 982:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // to take retransmissions and repetitions into account. Error cases + 983:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // will be handled in function OnMacStateCheckTimerEvent. + 984:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( McpsConfirm.McpsRequest == MCPS_CONFIRMED ) + 985:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 986:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fCtrl.Bits.Ack == 1 ) + 987:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Reset MacCommandsBufferIndex when we have received an ACK. + 988:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; + 989:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 990:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 991:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else + 992:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Reset the variable if we have received any valid frame. + 993:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; + 994:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 995:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 996:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Process payload and MAC commands + 997:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( ( size - 4 ) - appPayloadStartIndex ) > 0 ) + 998:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 999:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** port = payload[appPayloadStartIndex++]; +1000:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen = ( size - 4 ) - appPayloadStartIndex; +1001:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1002:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Port = port; +1003:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 19 + + +1004:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( port == 0 ) +1005:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1006:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Only allow frames which do not have fOpts +1007:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fCtrl.Bits.FOptsLen == 0 ) +1008:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1009:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPayloadDecrypt( payload + appPayloadStartIndex, +1010:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen, +1011:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nwkSKey, +1012:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address, +1013:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DOWN_LINK, +1014:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter, +1015:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacRxPayload ); +1016:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1017:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Decode frame payload MAC commands +1018:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ProcessMacCommands( LoRaMacRxPayload, 0, frameLen, snr ); +1019:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1020:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1021:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1022:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** skipIndication = true; +1023:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1024:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1025:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1026:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1027:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fCtrl.Bits.FOptsLen > 0 ) +1028:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1029:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Decode Options field MAC commands. Omit the fPort. +1030:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ProcessMacCommands( payload, 8, appPayloadStartIndex - 1, snr ); +1031:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1032:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1033:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPayloadDecrypt( payload + appPayloadStartIndex, +1034:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen, +1035:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appSKey, +1036:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address, +1037:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DOWN_LINK, +1038:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter, +1039:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacRxPayload ); +1040:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1041:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( skipIndication == false ) +1042:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1043:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = LoRaMacRxPayload; +1044:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = frameLen; +1045:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxData = true; +1046:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1047:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1048:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1049:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1050:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1051:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fCtrl.Bits.FOptsLen > 0 ) +1052:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1053:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Decode Options field MAC commands +1054:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ProcessMacCommands( payload, 8, appPayloadStartIndex, snr ); +1055:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1056:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1057:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1058:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( skipIndication == false ) +1059:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1060:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Check if the frame is an acknowledgement + ARM GAS /tmp/ccrFaSdZ.s page 20 + + +1061:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fCtrl.Bits.Ack == 1 ) +1062:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1063:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = true; +1064:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.AckReceived = true; +1065:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1066:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Stop the AckTimeout timer as no more retransmissions +1067:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // are needed. +1068:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &AckTimeoutTimer ); +1069:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1070:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1071:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1072:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; +1073:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1074:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( AckTimeoutRetriesCounter > AckTimeoutRetries ) +1075:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1076:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Stop the AckTimeout timer as no more retransmissions +1077:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // are needed. +1078:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &AckTimeoutTimer ); +1079:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1080:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1081:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1082:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Provide always an indication, skip the callback to the user application, +1083:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // in case of a confirmed downlink retransmission. +1084:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsInd = 1; +1085:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsIndSkip = skipIndication; +1086:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1087:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1088:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1089:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_MIC_FAIL; +1090:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1091:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); +1092:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; +1093:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1094:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1095:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1096:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_PROPRIETARY: +1097:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1098:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpy1( LoRaMacRxPayload, &payload[pktHeaderLen], size ); +1099:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_PROPRIETARY; +1101:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_OK; +1102:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = LoRaMacRxPayload; +1103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = size - pktHeaderLen; +1104:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsInd = 1; +1106:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1107:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1108:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +1109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; +1110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); +1111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1112:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1114:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1115:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Trig OnMacCheckTimerEvent call as soon as possible +1116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, 1 ); +1117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + ARM GAS /tmp/ccrFaSdZ.s page 21 + + +1118:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1119:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1120:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioTxTimeout( void ) +1121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) +1123:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); +1125:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1127:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); +1129:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1130:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1131:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT; +1132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT; +1133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1135:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1136:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxError( void ) +1137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) +1139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); +1141:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1142:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1143:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1144:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); +1145:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1146:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1147:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RxSlot == 0 ) +1148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == true ) +1150:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_ERROR; +1152:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_ERROR; +1154:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1155:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( TimerGetElapsedTime( AggregatedLastTxDoneTime ) >= RxWindow2Delay ) +1156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1158:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1159:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1160:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1161:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == true ) +1163:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_ERROR; +1165:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_ERROR; +1167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1170:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRadioRxTimeout( void ) +1172:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) +1174:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 22 + + +1175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); +1176:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1177:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1178:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); +1180:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RxSlot == 0 ) +1183:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == true ) +1185:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_TIMEOUT; +1187:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1188:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_TIMEOUT; +1189:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1190:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( TimerGetElapsedTime( AggregatedLastTxDoneTime ) >= RxWindow2Delay ) +1191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1193:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1194:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1195:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1196:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1197:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == true ) +1198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT; +1200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT; +1202:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) +1204:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1205:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1206:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1207:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1208:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnMacStateCheckTimerEvent( void ) +1211:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1212:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +1213:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +1214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** bool txTimeout = false; +1215:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1216:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &MacStateCheckTimer ); +1217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1218:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.MacDone == 1 ) +1219:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_RX_ABORT ) == LORAMAC_RX_ABORT ) +1221:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1222:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_RX_ABORT; +1223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1224:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1225:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1226:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacFlags.Bits.MlmeReq == 1 ) || ( ( LoRaMacFlags.Bits.McpsReq == 1 ) ) ) +1227:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( McpsConfirm.Status == LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT ) || +1229:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( MlmeConfirm.Status == LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT ) ) +1230:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1231:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Stop transmit cycle due to tx timeout. + ARM GAS /tmp/ccrFaSdZ.s page 23 + + +1232:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1233:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +1234:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; +1235:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; +1236:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.TxTimeOnAir = 0; +1237:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txTimeout = true; +1238:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1239:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1240:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( NodeAckRequested == false ) && ( txTimeout == false ) ) +1242:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1243:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacFlags.Bits.MlmeReq == 1 ) || ( ( LoRaMacFlags.Bits.McpsReq == 1 ) ) ) +1244:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN ) +1246:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure for the join request +1247:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.NbRetries = JoinRequestTrials; +1248:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1249:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MlmeConfirm.Status == LORAMAC_EVENT_INFO_STATUS_OK ) +1250:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Node joined successfully +1251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter = 0; +1252:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter = 0; +1253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1254:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1255:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1256:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( JoinRequestTrials >= MaxJoinRequestTrials ) +1258:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1259:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1260:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1261:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1262:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 0; +1264:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Sends the same frame again +1265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnTxDelayedTimerEvent( ); +1266:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1267:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1268:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1269:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1270:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure for all other frames +1271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( ChannelsNbRepCounter >= LoRaMacParams.ChannelsNbRep ) || ( LoRaMacFlags.B +1272:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1273:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.McpsInd == 0 ) +1274:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // Maximum repetitions without downlink. Reset MacCommandsBufferIndex. +1275:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Only process the case when the MAC did not receive a downlink. +1276:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +1277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrAckCounter++; +1278:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1279:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter = 0; +1281:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1282:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) +1283:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1284:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter++; +1285:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1286:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1287:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1288:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 24 + + +1289:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1290:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1291:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 0; +1292:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Sends the same frame again +1293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnTxDelayedTimerEvent( ); +1294:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1295:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1296:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1297:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1298:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.McpsInd == 1 ) +1300:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure if we received a frame +1301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( McpsConfirm.AckReceived == true ) || ( AckTimeoutRetriesCounter > AckTimeoutRetri +1302:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1303:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetry = false; +1304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; +1305:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) +1306:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1307:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter++; +1308:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1309:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; +1310:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1312:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1313:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1314:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( AckTimeoutRetry == true ) && ( ( LoRaMacState & LORAMAC_TX_DELAYED ) == 0 ) ) +1316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Retransmissions procedure for confirmed uplinks +1317:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetry = false; +1318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( AckTimeoutRetriesCounter < AckTimeoutRetries ) && ( AckTimeoutRetriesCounter <= M +1319:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetriesCounter++; +1321:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1322:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( AckTimeoutRetriesCounter % 2 ) == 1 ) +1323:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1324:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; +1325:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +1326:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = LoRaMacParams.ChannelsDatarate; +1327:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); +1328:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = phyParam.Value; +1329:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1330:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Try to send the frame again +1331:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ScheduleTx( ) == LORAMAC_STATUS_OK ) +1332:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1333:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 0; +1334:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1335:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1336:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1337:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // The DR is not applicable for the payload size +1338:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_DR_PAYLOAD_SIZE_ERROR; +1339:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1340:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +1341:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1342:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; +1343:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; +1344:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; +1345:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Datarate = LoRaMacParams.ChannelsDatarate; + ARM GAS /tmp/ccrFaSdZ.s page 25 + + +1346:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) +1347:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1348:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter++; +1349:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1350:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1351:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1352:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1353:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1354:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionInitDefaults( LoRaMacRegion, INIT_TYPE_RESTORE ); +1355:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1356:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; +1357:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1358:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +1359:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; +1360:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; +1361:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; +1362:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) +1363:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1364:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter++; +1365:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1366:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1367:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1368:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1369:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Handle reception for Class B and Class C +1370:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_RX ) == LORAMAC_RX ) +1371:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1372:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_RX; +1373:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1374:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacState == LORAMAC_IDLE ) +1375:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1376:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.McpsReq == 1 ) +1377:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1378:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPrimitives->MacMcpsConfirm( &McpsConfirm ); +1379:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsReq = 0; +1380:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1381:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1382:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.MlmeReq == 1 ) +1383:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1384:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPrimitives->MacMlmeConfirm( &MlmeConfirm ); +1385:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 0; +1386:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1387:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1388:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Procedure done. Reset variables. +1389:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 0; +1390:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1391:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1392:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1393:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Operation not finished restart timer +1394:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); +1395:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); +1396:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1397:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1398:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.McpsInd == 1 ) +1399:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1400:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass == CLASS_C ) +1401:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Activate RX2 window for Class C +1402:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); + ARM GAS /tmp/ccrFaSdZ.s page 26 + + +1403:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1404:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacFlags.Bits.McpsIndSkip == 0 ) +1405:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1406:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPrimitives->MacMcpsIndication( &McpsIndication ); +1407:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1408:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsIndSkip = 0; +1409:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsInd = 0; +1410:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1411:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1412:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1413:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnTxDelayedTimerEvent( void ) +1414:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1415:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; +1416:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFrameCtrl_t fCtrl; +1417:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AlternateDrParams_t altDr; +1418:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1419:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &TxDelayedTimer ); +1420:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_DELAYED; +1421:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1422:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN ) ) +1423:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1424:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ResetMacParameters( ); +1425:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1426:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** altDr.NbTrials = JoinRequestTrials + 1; +1427:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = RegionAlternateDr( LoRaMacRegion, &altDr ); +1428:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1429:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Value = 0; +1430:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; +1431:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1432:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Value = 0; +1433:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.Adr = AdrCtrlOn; +1434:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1435:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** /* In case of join request retransmissions, the stack must prepare +1436:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * the frame again, because the network server keeps track of the random +1437:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** * LoRaMacDevNonce values to prevent reply attacks. */ +1438:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareFrame( &macHdr, &fCtrl, 0, NULL, 0 ); +1439:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1440:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1441:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ScheduleTx( ); +1442:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1443:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1444:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRxWindow1TimerEvent( void ) +1445:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1446:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer1 ); +1447:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxSlot = 0; +1448:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1449:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.Channel = Channel; +1450:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.DrOffset = LoRaMacParams.Rx1DrOffset; +1451:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; +1452:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.RepeaterSupport = RepeaterSupport; +1453:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.RxContinuous = false; +1454:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.Window = RxSlot; +1455:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1456:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass == CLASS_C ) +1457:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1458:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Standby( ); +1459:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 27 + + +1460:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1461:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionRxConfig( LoRaMacRegion, &RxWindow1Config, ( int8_t* )&McpsIndication.RxDatarate ); +1462:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindowSetup( RxWindow1Config.RxContinuous, LoRaMacParams.MaxRxWindow ); +1463:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1464:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1465:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnRxWindow2TimerEvent( void ) +1466:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1467:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer2 ); +1468:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1469:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Channel = Channel; +1470:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Frequency = LoRaMacParams.Rx2Channel.Frequency; +1471:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; +1472:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RepeaterSupport = RepeaterSupport; +1473:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Window = 1; +1474:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1475:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) +1476:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1477:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RxContinuous = false; +1478:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1479:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1480:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1481:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RxContinuous = true; +1482:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1483:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1484:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionRxConfig( LoRaMacRegion, &RxWindow2Config, ( int8_t* )&McpsIndication.RxDatarate ) == +1485:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1486:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindowSetup( RxWindow2Config.RxContinuous, LoRaMacParams.MaxRxWindow ); +1487:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxSlot = RxWindow2Config.Window; +1488:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1489:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1490:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1491:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void OnAckTimeoutTimerEvent( void ) +1492:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1493:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &AckTimeoutTimer ); +1494:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1495:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( NodeAckRequested == true ) +1496:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1497:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetry = true; +1498:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_ACK_REQ; +1499:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1500:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass == CLASS_C ) +1501:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1502:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; +1503:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1504:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1505:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1506:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void RxWindowSetup( bool rxContinuous, uint32_t maxRxWindow ) +1507:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( rxContinuous == false ) +1509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Rx( maxRxWindow ); +1511:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1512:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1513:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Rx( 0 ); // Continuous mode +1515:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1516:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 28 + + +1517:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1518:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static bool ValidatePayloadLength( uint8_t lenN, int8_t datarate, uint8_t fOptsLen ) +1519:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1520:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +1521:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +1522:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t maxN = 0; +1523:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t payloadSize = 0; +1524:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1525:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Setup PHY request +1526:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +1527:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = datarate; +1528:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD; +1529:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1530:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Get the maximum payload length +1531:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RepeaterSupport == true ) +1532:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1533:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; +1534:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1535:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); +1536:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** maxN = phyParam.Value; +1537:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1538:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Calculate the resulting payload size +1539:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** payloadSize = ( lenN + fOptsLen ); +1540:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1541:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Validation of the application payload size +1542:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( payloadSize <= maxN ) && ( payloadSize <= LORAMAC_PHY_MAXPAYLOAD ) ) +1543:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1544:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return true; +1545:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1546:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return false; +1547:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1548:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1549:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacStatus_t AddMacCommand( uint8_t cmd, uint8_t p1, uint8_t p2 ) +1550:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1551:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_BUSY; +1552:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // The maximum buffer length must take MAC commands to re-send into account. +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t bufLen = LORA_MAC_COMMAND_MAX_LENGTH - MacCommandsBufferToRepeatIndex; +1554:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1555:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( cmd ) +1556:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1557:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_LINK_CHECK_REQ: +1558:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < bufLen ) +1559:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1560:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1561:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this command +1562:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1563:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1564:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1565:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_LINK_ADR_ANS: +1566:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < ( bufLen - 1 ) ) +1567:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1568:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1569:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Margin +1570:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p1; +1571:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1572:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1573:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + ARM GAS /tmp/ccrFaSdZ.s page 29 + + +1574:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DUTY_CYCLE_ANS: +1575:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < bufLen ) +1576:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1577:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1578:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer +1579:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1580:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1581:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1582:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_RX_PARAM_SETUP_ANS: +1583:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < ( bufLen - 1 ) ) +1584:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1585:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1586:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Datarate ACK, Channel ACK +1587:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p1; +1588:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1589:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1590:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1591:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DEV_STATUS_ANS: +1592:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < ( bufLen - 2 ) ) +1593:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1594:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1595:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // 1st byte Battery +1596:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // 2nd byte Margin +1597:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p1; +1598:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p2; +1599:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1600:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1601:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1602:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_NEW_CHANNEL_ANS: +1603:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < ( bufLen - 1 ) ) +1604:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1605:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1606:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Datarate range OK, Channel frequency OK +1607:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p1; +1608:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1609:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1610:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1611:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_RX_TIMING_SETUP_ANS: +1612:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < bufLen ) +1613:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1614:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1615:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer +1616:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1617:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1618:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1619:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_TX_PARAM_SETUP_ANS: +1620:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < bufLen ) +1621:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1622:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; +1623:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer +1624:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1625:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1626:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1627:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DL_CHANNEL_ANS: +1628:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex < bufLen ) +1629:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1630:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + ARM GAS /tmp/ccrFaSdZ.s page 30 + + +1631:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Uplink frequency exists, Channel frequency OK +1632:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p1; +1633:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; +1634:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1635:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1636:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +1637:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_SERVICE_UNKNOWN; +1638:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1639:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( status == LORAMAC_STATUS_OK ) +1640:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsInNextTx = true; +1642:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1643:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +1644:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1645:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1646:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static uint8_t ParseMacCommandsToRepeat( uint8_t* cmdBufIn, uint8_t length, uint8_t* cmdBufOut ) +1647:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1648:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t i = 0; +1649:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t cmdCount = 0; +1650:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1651:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( cmdBufIn == NULL ) || ( cmdBufOut == NULL ) ) +1652:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1653:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return 0; +1654:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1655:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1656:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** for( i = 0; i < length; i++ ) +1657:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( cmdBufIn[i] ) +1659:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1660:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // STICKY +1661:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DL_CHANNEL_ANS: +1662:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_RX_PARAM_SETUP_ANS: +1663:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // 1 byte payload +1664:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cmdBufOut[cmdCount++] = cmdBufIn[i++]; +1665:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cmdBufOut[cmdCount++] = cmdBufIn[i]; +1666:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1667:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1668:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_RX_TIMING_SETUP_ANS: +1669:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // 0 byte payload +1670:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cmdBufOut[cmdCount++] = cmdBufIn[i]; +1671:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1672:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1673:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // NON-STICKY +1674:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DEV_STATUS_ANS: +1675:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // 2 bytes payload +1676:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** i += 2; +1677:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1678:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1679:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_LINK_ADR_ANS: +1680:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_NEW_CHANNEL_ANS: +1681:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // 1 byte payload +1682:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** i++; +1683:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1684:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1685:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_TX_PARAM_SETUP_ANS: +1686:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_DUTY_CYCLE_ANS: +1687:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MOTE_MAC_LINK_CHECK_REQ: + ARM GAS /tmp/ccrFaSdZ.s page 31 + + +1688:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // 0 byte payload +1689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1690:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1691:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +1692:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1693:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1694:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1695:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1696:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return cmdCount; +1697:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1698:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1699:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void ProcessMacCommands( uint8_t *payload, uint8_t macIndex, uint8_t commandsSize, uint8_t s +1700:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1701:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t status = 0; +1702:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1703:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( macIndex < commandsSize ) +1704:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1705:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Decode Frame MAC commands +1706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( payload[macIndex++] ) +1707:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_LINK_CHECK_ANS: +1709:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; +1710:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.DemodMargin = payload[macIndex++]; +1711:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.NbGateways = payload[macIndex++]; +1712:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1713:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_LINK_ADR_REQ: +1714:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1715:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LinkAdrReqParams_t linkAdrReq; +1716:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t linkAdrDatarate = DR_0; +1717:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t linkAdrTxPower = TX_POWER_0; +1718:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t linkAdrNbRep = 0; +1719:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t linkAdrNbBytesParsed = 0; +1720:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1721:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Fill parameter structure +1722:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.Payload = &payload[macIndex - 1]; +1723:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.PayloadSize = commandsSize - ( macIndex - 1 ); +1724:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.AdrEnabled = AdrCtrlOn; +1725:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +1726:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentDatarate = LoRaMacParams.ChannelsDatarate; +1727:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentTxPower = LoRaMacParams.ChannelsTxPower; +1728:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentNbRep = LoRaMacParams.ChannelsNbRep; +1729:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1730:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Process the ADR requests +1731:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = RegionLinkAdrReq( LoRaMacRegion, &linkAdrReq, &linkAdrDatarate, +1732:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &linkAdrTxPower, &linkAdrNbRep, &linkAdrNbBytesParse +1733:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1734:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( status & 0x07 ) == 0x07 ) +1735:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1736:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = linkAdrDatarate; +1737:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsTxPower = linkAdrTxPower; +1738:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsNbRep = linkAdrNbRep; +1739:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1740:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1741:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Add the answers to the buffer +1742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** for( uint8_t i = 0; i < ( linkAdrNbBytesParsed / 5 ); i++ ) +1743:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1744:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_LINK_ADR_ANS, status, 0 ); + ARM GAS /tmp/ccrFaSdZ.s page 32 + + +1745:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1746:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update MAC index +1747:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macIndex += linkAdrNbBytesParsed - 1; +1748:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1749:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1750:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DUTY_CYCLE_REQ: +1751:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MaxDCycle = payload[macIndex++]; +1752:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedDCycle = 1 << MaxDCycle; +1753:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_DUTY_CYCLE_ANS, 0, 0 ); +1754:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1755:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_RX_PARAM_SETUP_REQ: +1756:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1757:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxParamSetupReqParams_t rxParamSetupReq; +1758:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = 0x07; +1759:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1760:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.DrOffset = ( payload[macIndex] >> 4 ) & 0x07; +1761:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Datarate = payload[macIndex] & 0x0F; +1762:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macIndex++; +1763:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1764:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency = ( uint32_t )payload[macIndex++]; +1765:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 8; +1766:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 16; +1767:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency *= 100; +1768:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1769:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Perform request on region +1770:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = RegionRxParamSetupReq( LoRaMacRegion, &rxParamSetupReq ); +1771:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1772:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( status & 0x07 ) == 0x07 ) +1773:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1774:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate = rxParamSetupReq.Datarate; +1775:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Frequency = rxParamSetupReq.Frequency; +1776:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx1DrOffset = rxParamSetupReq.DrOffset; +1777:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1778:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_RX_PARAM_SETUP_ANS, status, 0 ); +1779:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1780:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1781:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DEV_STATUS_REQ: +1782:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1783:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t batteryLevel = BAT_LEVEL_NO_MEASURE; +1784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacCallbacks != NULL ) && ( LoRaMacCallbacks->GetBatteryLevel != NULL +1785:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1786:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** batteryLevel = LoRaMacCallbacks->GetBatteryLevel( ); +1787:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1788:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_DEV_STATUS_ANS, batteryLevel, snr ); +1789:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1790:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1791:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_NEW_CHANNEL_REQ: +1792:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1793:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NewChannelReqParams_t newChannelReq; +1794:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelParams_t chParam; +1795:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = 0x03; +1796:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1797:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** newChannelReq.ChannelId = payload[macIndex++]; +1798:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** newChannelReq.NewChannel = &chParam; +1799:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1800:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency = ( uint32_t )payload[macIndex++]; +1801:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency |= ( uint32_t )payload[macIndex++] << 8; + ARM GAS /tmp/ccrFaSdZ.s page 33 + + +1802:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency |= ( uint32_t )payload[macIndex++] << 16; +1803:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency *= 100; +1804:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Rx1Frequency = 0; +1805:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.DrRange.Value = payload[macIndex++]; +1806:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1807:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = RegionNewChannelReq( LoRaMacRegion, &newChannelReq ); +1808:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1809:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_NEW_CHANNEL_ANS, status, 0 ); +1810:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1811:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1812:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_RX_TIMING_SETUP_REQ: +1813:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1814:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t delay = payload[macIndex++] & 0x0F; +1815:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1816:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( delay == 0 ) +1817:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** delay++; +1819:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1820:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 = delay * 1000; +1821:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; +1822:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_RX_TIMING_SETUP_ANS, 0, 0 ); +1823:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1824:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1825:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_TX_PARAM_SETUP_REQ: +1826:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1827:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TxParamSetupReqParams_t txParamSetupReq; +1828:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t eirpDwellTime = payload[macIndex++]; +1829:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1830:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.UplinkDwellTime = 0; +1831:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.DownlinkDwellTime = 0; +1832:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1833:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( eirpDwellTime & 0x20 ) == 0x20 ) +1834:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1835:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.DownlinkDwellTime = 1; +1836:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1837:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( eirpDwellTime & 0x10 ) == 0x10 ) +1838:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1839:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.UplinkDwellTime = 1; +1840:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1841:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.MaxEirp = eirpDwellTime & 0x0F; +1842:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1843:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Check the status for correctness +1844:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionTxParamSetupReq( LoRaMacRegion, &txParamSetupReq ) != -1 ) +1845:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1846:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Accept command +1847:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.UplinkDwellTime = txParamSetupReq.UplinkDwellTime; +1848:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.DownlinkDwellTime = txParamSetupReq.DownlinkDwellTime; +1849:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MaxEirp = LoRaMacMaxEirpTable[txParamSetupReq.MaxEirp]; +1850:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Add command response +1851:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_TX_PARAM_SETUP_ANS, 0, 0 ); +1852:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1853:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1854:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1855:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DL_CHANNEL_REQ: +1856:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1857:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DlChannelReqParams_t dlChannelReq; +1858:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = 0x03; + ARM GAS /tmp/ccrFaSdZ.s page 34 + + +1859:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1860:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.ChannelId = payload[macIndex++]; +1861:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency = ( uint32_t )payload[macIndex++]; +1862:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 8; +1863:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 16; +1864:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency *= 100; +1865:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1866:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = RegionDlChannelReq( LoRaMacRegion, &dlChannelReq ); +1867:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1868:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_DL_CHANNEL_ANS, status, 0 ); +1869:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1870:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +1871:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +1872:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Unknown command. ABORT MAC commands processing +1873:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; +1874:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1875:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1876:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1877:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1878:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t Send( LoRaMacHeader_t *macHdr, uint8_t fPort, void *fBuffer, uint16_t fBufferSize ) +1879:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1880:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFrameCtrl_t fCtrl; +1881:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_PARAMETER_INVALID; +1882:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1883:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Value = 0; +1884:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.FOptsLen = 0; +1885:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.FPending = 0; +1886:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.Ack = false; +1887:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.AdrAckReq = false; +1888:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.Adr = AdrCtrlOn; +1889:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1890:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Prepare the frame +1891:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = PrepareFrame( macHdr, &fCtrl, fPort, fBuffer, fBufferSize ); +1892:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1893:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Validate status +1894:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( status != LORAMAC_STATUS_OK ) +1895:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1896:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +1897:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1898:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1899:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset confirm parameters +1900:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = 0; +1901:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; +1902:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.UpLinkCounter = UpLinkCounter; +1903:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1904:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = ScheduleTx( ); +1905:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1906:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +1907:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1908:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1909:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static LoRaMacStatus_t ScheduleTx( void ) +1910:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1911:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerTime_t dutyCycleTimeOff = 0; +1912:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NextChanParams_t nextChan; +1913:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1914:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Check if the device is off +1915:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MaxDCycle == 255 ) + ARM GAS /tmp/ccrFaSdZ.s page 35 + + +1916:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1917:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_DEVICE_OFF; +1918:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1919:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MaxDCycle == 0 ) +1920:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1921:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedTimeOff = 0; +1922:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1923:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1924:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update Backoff +1925:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** CalculateBackOff( LastTxChannel ); +1926:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.AggrTimeOff = AggregatedTimeOff; +1928:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.Datarate = LoRaMacParams.ChannelsDatarate; +1929:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.DutyCycleEnabled = DutyCycleOn; +1930:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.Joined = IsLoRaMacNetworkJoined; +1931:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.LastAggrTx = AggregatedLastTxDoneTime; +1932:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1933:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Select channel +1934:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( RegionNextChannel( LoRaMacRegion, &nextChan, &Channel, &dutyCycleTimeOff, &AggregatedTim +1935:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1936:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Set the default datarate +1937:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; +1938:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update datarate in the function parameters +1939:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.Datarate = LoRaMacParams.ChannelsDatarate; +1940:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1941:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1942:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Compute Rx1 windows parameters +1943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionComputeRxWindowParameters( LoRaMacRegion, +1944:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionApplyDrOffset( LoRaMacRegion, LoRaMacParams.DownlinkDwel +1945:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols, +1946:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.SystemMaxRxError, +1947:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &RxWindow1Config ); +1948:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Compute Rx2 windows parameters +1949:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionComputeRxWindowParameters( LoRaMacRegion, +1950:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate, +1951:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols, +1952:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.SystemMaxRxError, +1953:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &RxWindow2Config ); +1954:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1955:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsLoRaMacNetworkJoined == false ) +1956:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1957:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Delay = LoRaMacParams.JoinAcceptDelay1 + RxWindow1Config.WindowOffset; +1958:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Delay = LoRaMacParams.JoinAcceptDelay2 + RxWindow2Config.WindowOffset; +1959:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1960:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1961:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1962:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ValidatePayloadLength( LoRaMacTxPayloadLen, LoRaMacParams.ChannelsDatarate, MacCommands +1963:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1964:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_LENGTH_ERROR; +1965:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1966:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Delay = LoRaMacParams.ReceiveDelay1 + RxWindow1Config.WindowOffset; +1967:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Delay = LoRaMacParams.ReceiveDelay2 + RxWindow2Config.WindowOffset; +1968:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1969:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1970:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Schedule transmission of frame +1971:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( dutyCycleTimeOff == 0 ) +1972:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 36 + + +1973:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Try to send now +1974:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return SendFrameOnChannel( Channel ); +1975:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1976:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +1977:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1978:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Send later - prepare timer +1979:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_TX_DELAYED; +1980:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &TxDelayedTimer, dutyCycleTimeOff ); +1981:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &TxDelayedTimer ); +1982:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1983:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; +1984:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1985:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +1986:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1987:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void CalculateBackOff( uint8_t channel ) +1988:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +1989:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** CalcBackOffParams_t calcBackOff; +1990:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1991:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.Joined = IsLoRaMacNetworkJoined; +1992:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.DutyCycleEnabled = DutyCycleOn; +1993:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.Channel = channel; +1994:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.ElapsedTime = TimerGetElapsedTime( LoRaMacInitializationTime ); +1995:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.TxTimeOnAir = TxTimeOnAir; +1996:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.LastTxIsJoinRequest = LastTxIsJoinRequest; +1997:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +1998:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update regional back-off +1999:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionCalcBackOff( LoRaMacRegion, &calcBackOff ); +2000:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2001:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update aggregated time-off +2002:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedTimeOff = AggregatedTimeOff + ( TxTimeOnAir * AggregatedDCycle - TxTimeOnAir ); +2003:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2004:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2005:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** static void ResetMacParameters( void ) +2006:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 25 .loc 1 2006 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 0000 70B5 push {r4, r5, r6, lr} + 30 .LCFI0: + 31 .cfi_def_cfa_offset 16 + 32 .cfi_offset 4, -16 + 33 .cfi_offset 5, -12 + 34 .cfi_offset 6, -8 + 35 .cfi_offset 14, -4 +2007:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsLoRaMacNetworkJoined = false; + 36 .loc 1 2007 0 + 37 0002 0023 movs r3, #0 + 38 0004 244A ldr r2, .L4 + 39 0006 1370 strb r3, [r2] +2008:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2009:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Counters +2010:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter = 0; + 40 .loc 1 2010 0 + 41 0008 244A ldr r2, .L4+4 + 42 000a 1360 str r3, [r2] +2011:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DownLinkCounter = 0; + ARM GAS /tmp/ccrFaSdZ.s page 37 + + + 43 .loc 1 2011 0 + 44 000c 244A ldr r2, .L4+8 + 45 000e 1360 str r3, [r2] +2012:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrAckCounter = 0; + 46 .loc 1 2012 0 + 47 0010 244A ldr r2, .L4+12 + 48 0012 1360 str r3, [r2] +2013:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2014:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter = 0; + 49 .loc 1 2014 0 + 50 0014 244A ldr r2, .L4+16 + 51 0016 1370 strb r3, [r2] +2015:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2016:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = 1; + 52 .loc 1 2016 0 + 53 0018 0122 movs r2, #1 + 54 001a 2449 ldr r1, .L4+20 + 55 001c 0A70 strb r2, [r1] +2017:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetriesCounter = 1; + 56 .loc 1 2017 0 + 57 001e 2449 ldr r1, .L4+24 + 58 0020 0A70 strb r2, [r1] +2018:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetry = false; + 59 .loc 1 2018 0 + 60 0022 2449 ldr r1, .L4+28 + 61 0024 0B70 strb r3, [r1] +2019:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2020:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MaxDCycle = 0; + 62 .loc 1 2020 0 + 63 0026 2449 ldr r1, .L4+32 + 64 0028 0B70 strb r3, [r1] +2021:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedDCycle = 1; + 65 .loc 1 2021 0 + 66 002a 2449 ldr r1, .L4+36 + 67 002c 0A80 strh r2, [r1] +2022:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2023:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; + 68 .loc 1 2023 0 + 69 002e 244A ldr r2, .L4+40 + 70 0030 1370 strb r3, [r2] +2024:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = 0; + 71 .loc 1 2024 0 + 72 0032 244A ldr r2, .L4+44 + 73 0034 1370 strb r3, [r2] +2025:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2026:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsRxWindowsEnabled = true; + 74 .loc 1 2026 0 + 75 0036 0121 movs r1, #1 + 76 0038 234A ldr r2, .L4+48 + 77 003a 1170 strb r1, [r2] +2027:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2028:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsTxPower = LoRaMacParamsDefaults.ChannelsTxPower; + 78 .loc 1 2028 0 + 79 003c 2349 ldr r1, .L4+52 + 80 003e 0020 movs r0, #0 + 81 0040 0856 ldrsb r0, [r1, r0] + 82 0042 234A ldr r2, .L4+56 + ARM GAS /tmp/ccrFaSdZ.s page 38 + + + 83 0044 1070 strb r0, [r2] +2029:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + 84 .loc 1 2029 0 + 85 0046 0120 movs r0, #1 + 86 0048 0856 ldrsb r0, [r1, r0] + 87 004a 5070 strb r0, [r2, #1] +2030:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx1DrOffset = LoRaMacParamsDefaults.Rx1DrOffset; + 88 .loc 1 2030 0 + 89 004c 2120 movs r0, #33 + 90 004e 0C5C ldrb r4, [r1, r0] + 91 0050 1454 strb r4, [r2, r0] +2031:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel = LoRaMacParamsDefaults.Rx2Channel; + 92 .loc 1 2031 0 + 93 0052 1000 movs r0, r2 + 94 0054 2430 adds r0, r0, #36 + 95 0056 0C00 movs r4, r1 + 96 0058 2434 adds r4, r4, #36 + 97 005a 60CC ldmia r4!, {r5, r6} + 98 005c 60C0 stmia r0!, {r5, r6} +2032:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.UplinkDwellTime = LoRaMacParamsDefaults.UplinkDwellTime; + 99 .loc 1 2032 0 + 100 005e 2C20 movs r0, #44 + 101 0060 0C5C ldrb r4, [r1, r0] + 102 0062 1454 strb r4, [r2, r0] +2033:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.DownlinkDwellTime = LoRaMacParamsDefaults.DownlinkDwellTime; + 103 .loc 1 2033 0 + 104 0064 0130 adds r0, r0, #1 + 105 0066 0C5C ldrb r4, [r1, r0] + 106 0068 1454 strb r4, [r2, r0] +2034:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MaxEirp = LoRaMacParamsDefaults.MaxEirp; + 107 .loc 1 2034 0 + 108 006a 086B ldr r0, [r1, #48] + 109 006c 1063 str r0, [r2, #48] +2035:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.AntennaGain = LoRaMacParamsDefaults.AntennaGain; + 110 .loc 1 2035 0 + 111 006e 496B ldr r1, [r1, #52] + 112 0070 5163 str r1, [r2, #52] +2036:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2037:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 113 .loc 1 2037 0 + 114 0072 184A ldr r2, .L4+60 + 115 0074 1370 strb r3, [r2] +2038:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** SrvAckRequested = false; + 116 .loc 1 2038 0 + 117 0076 184A ldr r2, .L4+64 + 118 0078 1370 strb r3, [r2] +2039:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsInNextTx = false; + 119 .loc 1 2039 0 + 120 007a 184A ldr r2, .L4+68 + 121 007c 1370 strb r3, [r2] +2040:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2041:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset Multicast downlink counters +2042:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastParams_t *cur = MulticastChannels; + 122 .loc 1 2042 0 + 123 007e 184B ldr r3, .L4+72 + 124 0080 1B68 ldr r3, [r3] + 125 .LVL0: + ARM GAS /tmp/ccrFaSdZ.s page 39 + + +2043:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( cur != NULL ) + 126 .loc 1 2043 0 + 127 0082 02E0 b .L2 + 128 .L3: +2044:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2045:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur->DownLinkCounter = 0; + 129 .loc 1 2045 0 + 130 0084 0022 movs r2, #0 + 131 0086 5A62 str r2, [r3, #36] +2046:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur = cur->Next; + 132 .loc 1 2046 0 + 133 0088 9B6A ldr r3, [r3, #40] + 134 .LVL1: + 135 .L2: +2043:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( cur != NULL ) + 136 .loc 1 2043 0 + 137 008a 002B cmp r3, #0 + 138 008c FAD1 bne .L3 +2047:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2048:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2049:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Initialize channel index. +2050:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Channel = 0; + 139 .loc 1 2050 0 + 140 008e 154A ldr r2, .L4+76 + 141 0090 1370 strb r3, [r2] +2051:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LastTxChannel = Channel; + 142 .loc 1 2051 0 + 143 0092 154A ldr r2, .L4+80 + 144 0094 1370 strb r3, [r2] +2052:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 145 .loc 1 2052 0 + 146 @ sp needed + 147 0096 70BD pop {r4, r5, r6, pc} + 148 .L5: + 149 .align 2 + 150 .L4: + 151 0098 00000000 .word .LANCHOR0 + 152 009c 00000000 .word .LANCHOR1 + 153 00a0 00000000 .word .LANCHOR2 + 154 00a4 00000000 .word .LANCHOR3 + 155 00a8 00000000 .word .LANCHOR4 + 156 00ac 00000000 .word .LANCHOR5 + 157 00b0 00000000 .word .LANCHOR6 + 158 00b4 00000000 .word .LANCHOR7 + 159 00b8 00000000 .word .LANCHOR8 + 160 00bc 00000000 .word .LANCHOR9 + 161 00c0 00000000 .word .LANCHOR10 + 162 00c4 00000000 .word .LANCHOR11 + 163 00c8 00000000 .word .LANCHOR12 + 164 00cc 00000000 .word .LANCHOR13 + 165 00d0 00000000 .word .LANCHOR14 + 166 00d4 00000000 .word .LANCHOR15 + 167 00d8 00000000 .word .LANCHOR16 + 168 00dc 00000000 .word .LANCHOR17 + 169 00e0 00000000 .word .LANCHOR18 + 170 00e4 00000000 .word .LANCHOR19 + 171 00e8 00000000 .word .LANCHOR20 + ARM GAS /tmp/ccrFaSdZ.s page 40 + + + 172 .cfi_endproc + 173 .LFE104: + 175 .section .text.ValidatePayloadLength,"ax",%progbits + 176 .align 1 + 177 .syntax unified + 178 .code 16 + 179 .thumb_func + 180 .fpu softvfp + 182 ValidatePayloadLength: + 183 .LFB97: +1519:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 184 .loc 1 1519 0 + 185 .cfi_startproc + 186 @ args = 0, pretend = 0, frame = 8 + 187 @ frame_needed = 0, uses_anonymous_args = 0 + 188 .LVL2: + 189 0000 30B5 push {r4, r5, lr} + 190 .LCFI1: + 191 .cfi_def_cfa_offset 12 + 192 .cfi_offset 4, -12 + 193 .cfi_offset 5, -8 + 194 .cfi_offset 14, -4 + 195 0002 83B0 sub sp, sp, #12 + 196 .LCFI2: + 197 .cfi_def_cfa_offset 24 + 198 0004 0500 movs r5, r0 + 199 0006 1400 movs r4, r2 + 200 .LVL3: +1526:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = datarate; + 201 .loc 1 1526 0 + 202 0008 104A ldr r2, .L11 + 203 .LVL4: + 204 000a 2C23 movs r3, #44 + 205 000c D25C ldrb r2, [r2, r3] + 206 000e 01AB add r3, sp, #4 + 207 0010 9A70 strb r2, [r3, #2] +1527:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD; + 208 .loc 1 1527 0 + 209 0012 5970 strb r1, [r3, #1] +1528:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 210 .loc 1 1528 0 + 211 0014 0922 movs r2, #9 + 212 0016 1A70 strb r2, [r3] +1531:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 213 .loc 1 1531 0 + 214 0018 0D4B ldr r3, .L11+4 + 215 001a 1B78 ldrb r3, [r3] + 216 001c 002B cmp r3, #0 + 217 001e 02D0 beq .L7 +1533:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 218 .loc 1 1533 0 + 219 0020 01AB add r3, sp, #4 + 220 0022 0132 adds r2, r2, #1 + 221 0024 1A70 strb r2, [r3] + 222 .L7: +1535:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** maxN = phyParam.Value; + 223 .loc 1 1535 0 + ARM GAS /tmp/ccrFaSdZ.s page 41 + + + 224 0026 0B4B ldr r3, .L11+8 + 225 0028 1878 ldrb r0, [r3] + 226 .LVL5: + 227 002a 01A9 add r1, sp, #4 + 228 .LVL6: + 229 002c FFF7FEFF bl RegionGetPhyParam + 230 .LVL7: +1536:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 231 .loc 1 1536 0 + 232 0030 80B2 uxth r0, r0 + 233 .LVL8: +1539:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 234 .loc 1 1539 0 + 235 0032 6419 adds r4, r4, r5 + 236 .LVL9: +1542:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 237 .loc 1 1542 0 + 238 0034 A042 cmp r0, r4 + 239 0036 03D3 bcc .L9 +1542:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 240 .loc 1 1542 0 is_stmt 0 discriminator 1 + 241 0038 FF2C cmp r4, #255 + 242 003a 04D9 bls .L10 +1546:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 243 .loc 1 1546 0 is_stmt 1 + 244 003c 0020 movs r0, #0 + 245 .LVL10: + 246 003e 00E0 b .L8 + 247 .LVL11: + 248 .L9: + 249 0040 0020 movs r0, #0 + 250 .LVL12: + 251 .L8: +1547:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 252 .loc 1 1547 0 + 253 0042 03B0 add sp, sp, #12 + 254 @ sp needed + 255 .LVL13: + 256 0044 30BD pop {r4, r5, pc} + 257 .LVL14: + 258 .L10: +1544:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 259 .loc 1 1544 0 + 260 0046 0120 movs r0, #1 + 261 .LVL15: + 262 0048 FBE7 b .L8 + 263 .L12: + 264 004a C046 .align 2 + 265 .L11: + 266 004c 00000000 .word .LANCHOR14 + 267 0050 00000000 .word .LANCHOR21 + 268 0054 00000000 .word .LANCHOR22 + 269 .cfi_endproc + 270 .LFE97: + 272 .section .text.OnAckTimeoutTimerEvent,"ax",%progbits + 273 .align 1 + 274 .syntax unified + ARM GAS /tmp/ccrFaSdZ.s page 42 + + + 275 .code 16 + 276 .thumb_func + 277 .fpu softvfp + 279 OnAckTimeoutTimerEvent: + 280 .LFB95: +1492:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &AckTimeoutTimer ); + 281 .loc 1 1492 0 + 282 .cfi_startproc + 283 @ args = 0, pretend = 0, frame = 0 + 284 @ frame_needed = 0, uses_anonymous_args = 0 + 285 0000 10B5 push {r4, lr} + 286 .LCFI3: + 287 .cfi_def_cfa_offset 8 + 288 .cfi_offset 4, -8 + 289 .cfi_offset 14, -4 +1493:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 290 .loc 1 1493 0 + 291 0002 0D48 ldr r0, .L17 + 292 0004 FFF7FEFF bl TimerStop + 293 .LVL16: +1495:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 294 .loc 1 1495 0 + 295 0008 0C4B ldr r3, .L17+4 + 296 000a 1B78 ldrb r3, [r3] + 297 000c 002B cmp r3, #0 + 298 000e 07D0 beq .L14 +1497:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_ACK_REQ; + 299 .loc 1 1497 0 + 300 0010 0B4B ldr r3, .L17+8 + 301 0012 0122 movs r2, #1 + 302 0014 1A70 strb r2, [r3] +1498:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 303 .loc 1 1498 0 + 304 0016 0B4A ldr r2, .L17+12 + 305 0018 0423 movs r3, #4 + 306 001a 1168 ldr r1, [r2] + 307 001c 9943 bics r1, r3 + 308 001e 1160 str r1, [r2] + 309 .L14: +1500:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 310 .loc 1 1500 0 + 311 0020 094B ldr r3, .L17+16 + 312 0022 1B78 ldrb r3, [r3] + 313 0024 022B cmp r3, #2 + 314 0026 00D0 beq .L16 + 315 .L13: +1504:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 316 .loc 1 1504 0 + 317 @ sp needed + 318 0028 10BD pop {r4, pc} + 319 .L16: +1502:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 320 .loc 1 1502 0 + 321 002a 084A ldr r2, .L17+20 + 322 002c 1378 ldrb r3, [r2] + 323 002e 1021 movs r1, #16 + 324 0030 0B43 orrs r3, r1 + ARM GAS /tmp/ccrFaSdZ.s page 43 + + + 325 0032 1370 strb r3, [r2] +1504:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 326 .loc 1 1504 0 + 327 0034 F8E7 b .L13 + 328 .L18: + 329 0036 C046 .align 2 + 330 .L17: + 331 0038 00000000 .word .LANCHOR23 + 332 003c 00000000 .word .LANCHOR15 + 333 0040 00000000 .word .LANCHOR7 + 334 0044 00000000 .word .LANCHOR24 + 335 0048 00000000 .word .LANCHOR25 + 336 004c 00000000 .word .LANCHOR26 + 337 .cfi_endproc + 338 .LFE95: + 340 .section .text.PrepareRxDoneAbort,"ax",%progbits + 341 .align 1 + 342 .syntax unified + 343 .code 16 + 344 .thumb_func + 345 .fpu softvfp + 347 PrepareRxDoneAbort: + 348 .LFB86: + 685:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_RX_ABORT; + 349 .loc 1 685 0 + 350 .cfi_startproc + 351 @ args = 0, pretend = 0, frame = 0 + 352 @ frame_needed = 0, uses_anonymous_args = 0 + 353 0000 10B5 push {r4, lr} + 354 .LCFI4: + 355 .cfi_def_cfa_offset 8 + 356 .cfi_offset 4, -8 + 357 .cfi_offset 14, -4 + 686:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 358 .loc 1 686 0 + 359 0002 0E4A ldr r2, .L22 + 360 0004 4023 movs r3, #64 + 361 0006 1168 ldr r1, [r2] + 362 0008 0B43 orrs r3, r1 + 363 000a 1360 str r3, [r2] + 688:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 364 .loc 1 688 0 + 365 000c 0C4B ldr r3, .L22+4 + 366 000e 1B78 ldrb r3, [r3] + 367 0010 002B cmp r3, #0 + 368 0012 0FD1 bne .L21 + 369 .L20: + 693:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; + 370 .loc 1 693 0 + 371 0014 0B4A ldr r2, .L22+8 + 372 0016 1378 ldrb r3, [r2] + 694:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 373 .loc 1 694 0 + 374 0018 0221 movs r1, #2 + 375 001a 0B43 orrs r3, r1 + 376 001c 1021 movs r1, #16 + 377 001e 0B43 orrs r3, r1 + ARM GAS /tmp/ccrFaSdZ.s page 44 + + + 378 0020 1370 strb r3, [r2] + 697:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 379 .loc 1 697 0 + 380 0022 094C ldr r4, .L22+12 + 381 0024 0121 movs r1, #1 + 382 0026 2000 movs r0, r4 + 383 0028 FFF7FEFF bl TimerSetValue + 384 .LVL17: + 698:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 385 .loc 1 698 0 + 386 002c 2000 movs r0, r4 + 387 002e FFF7FEFF bl TimerStart + 388 .LVL18: + 699:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 389 .loc 1 699 0 + 390 @ sp needed + 391 0032 10BD pop {r4, pc} + 392 .L21: + 690:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 393 .loc 1 690 0 + 394 0034 FFF7FEFF bl OnAckTimeoutTimerEvent + 395 .LVL19: + 396 0038 ECE7 b .L20 + 397 .L23: + 398 003a C046 .align 2 + 399 .L22: + 400 003c 00000000 .word .LANCHOR24 + 401 0040 00000000 .word .LANCHOR15 + 402 0044 00000000 .word .LANCHOR26 + 403 0048 00000000 .word .LANCHOR27 + 404 .cfi_endproc + 405 .LFE86: + 407 .global __aeabi_uidiv + 408 .global __aeabi_ui2f + 409 .section .text.ProcessMacCommands,"ax",%progbits + 410 .align 1 + 411 .syntax unified + 412 .code 16 + 413 .thumb_func + 414 .fpu softvfp + 416 ProcessMacCommands: + 417 .LFB100: +1700:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t status = 0; + 418 .loc 1 1700 0 + 419 .cfi_startproc + 420 @ args = 0, pretend = 0, frame = 32 + 421 @ frame_needed = 0, uses_anonymous_args = 0 + 422 .LVL20: + 423 0000 F0B5 push {r4, r5, r6, r7, lr} + 424 .LCFI5: + 425 .cfi_def_cfa_offset 20 + 426 .cfi_offset 4, -20 + 427 .cfi_offset 5, -16 + 428 .cfi_offset 6, -12 + 429 .cfi_offset 7, -8 + 430 .cfi_offset 14, -4 + 431 0002 D646 mov lr, r10 + ARM GAS /tmp/ccrFaSdZ.s page 45 + + + 432 0004 4F46 mov r7, r9 + 433 0006 4646 mov r6, r8 + 434 0008 C0B5 push {r6, r7, lr} + 435 .LCFI6: + 436 .cfi_def_cfa_offset 32 + 437 .cfi_offset 8, -32 + 438 .cfi_offset 9, -28 + 439 .cfi_offset 10, -24 + 440 000a 8AB0 sub sp, sp, #40 + 441 .LCFI7: + 442 .cfi_def_cfa_offset 72 + 443 000c 0700 movs r7, r0 + 444 000e 0C00 movs r4, r1 + 445 0010 1500 movs r5, r2 + 446 0012 0393 str r3, [sp, #12] + 447 .LVL21: + 448 .L25: +1703:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 449 .loc 1 1703 0 + 450 0014 AC42 cmp r4, r5 + 451 0016 00D3 bcc .LCB387 + 452 0018 09E2 b .L24 @long jump + 453 .LCB387: +1706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 454 .loc 1 1706 0 + 455 001a 661C adds r6, r4, #1 + 456 001c F6B2 uxtb r6, r6 + 457 .LVL22: + 458 001e 3B5D ldrb r3, [r7, r4] + 459 0020 0A2B cmp r3, #10 + 460 0022 00D9 bls .LCB393 + 461 0024 03E2 b .L24 @long jump + 462 .LCB393: + 463 0026 9B00 lsls r3, r3, #2 + 464 0028 DA4A ldr r2, .L58 + 465 002a D358 ldr r3, [r2, r3] + 466 002c 9F46 mov pc, r3 + 467 .section .rodata.ProcessMacCommands,"a",%progbits + 468 .align 2 + 469 .L28: + 470 0000 2E040000 .word .L24 + 471 0004 2E040000 .word .L24 + 472 0008 2E000000 .word .L27 + 473 000c 46000000 .word .L29 + 474 0010 2C010000 .word .L30 + 475 0014 68010000 .word .L31 + 476 0018 FA010000 .word .L32 + 477 001c 50020000 .word .L33 + 478 0020 C4020000 .word .L34 + 479 0024 14030000 .word .L35 + 480 0028 C8030000 .word .L36 + 481 .section .text.ProcessMacCommands + 482 .L27: +1709:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.DemodMargin = payload[macIndex++]; + 483 .loc 1 1709 0 + 484 002e DA4B ldr r3, .L58+4 + 485 0030 0022 movs r2, #0 + ARM GAS /tmp/ccrFaSdZ.s page 46 + + + 486 0032 5A70 strb r2, [r3, #1] +1710:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.NbGateways = payload[macIndex++]; + 487 .loc 1 1710 0 + 488 0034 A21C adds r2, r4, #2 + 489 0036 D2B2 uxtb r2, r2 + 490 .LVL23: + 491 0038 B95D ldrb r1, [r7, r6] + 492 003a 1972 strb r1, [r3, #8] +1711:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 493 .loc 1 1711 0 + 494 003c 0334 adds r4, r4, #3 + 495 003e E4B2 uxtb r4, r4 + 496 .LVL24: + 497 0040 BA5C ldrb r2, [r7, r2] + 498 0042 5A72 strb r2, [r3, #9] +1712:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_LINK_ADR_REQ: + 499 .loc 1 1712 0 + 500 0044 E6E7 b .L25 + 501 .LVL25: + 502 .L29: + 503 .LBB34: +1716:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t linkAdrTxPower = TX_POWER_0; + 504 .loc 1 1716 0 + 505 0046 0922 movs r2, #9 + 506 0048 02AB add r3, sp, #8 + 507 004a 9C46 mov ip, r3 + 508 004c 6244 add r2, r2, ip + 509 004e 0021 movs r1, #0 + 510 0050 1170 strb r1, [r2] +1717:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t linkAdrNbRep = 0; + 511 .loc 1 1717 0 + 512 0052 0A23 movs r3, #10 + 513 0054 6046 mov r0, ip + 514 0056 6344 add r3, r3, ip + 515 0058 9C46 mov ip, r3 + 516 005a 1970 strb r1, [r3] +1718:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t linkAdrNbBytesParsed = 0; + 517 .loc 1 1718 0 + 518 005c 0B24 movs r4, #11 + 519 005e 8046 mov r8, r0 + 520 0060 4444 add r4, r4, r8 + 521 0062 2170 strb r1, [r4] +1719:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 522 .loc 1 1719 0 + 523 0064 0173 strb r1, [r0, #12] +1722:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.PayloadSize = commandsSize - ( macIndex - 1 ); + 524 .loc 1 1722 0 + 525 0066 701E subs r0, r6, #1 + 526 0068 3818 adds r0, r7, r0 + 527 006a 07A9 add r1, sp, #28 + 528 006c 0790 str r0, [sp, #28] +1723:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.AdrEnabled = AdrCtrlOn; + 529 .loc 1 1723 0 + 530 006e A81B subs r0, r5, r6 + 531 0070 0130 adds r0, r0, #1 + 532 0072 0871 strb r0, [r1, #4] +1724:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + ARM GAS /tmp/ccrFaSdZ.s page 47 + + + 533 .loc 1 1724 0 + 534 0074 C948 ldr r0, .L58+8 + 535 0076 0078 ldrb r0, [r0] + 536 0078 8871 strb r0, [r1, #6] +1725:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentDatarate = LoRaMacParams.ChannelsDatarate; + 537 .loc 1 1725 0 + 538 007a C948 ldr r0, .L58+12 + 539 007c 2C23 movs r3, #44 + 540 007e C35C ldrb r3, [r0, r3] + 541 0080 4B71 strb r3, [r1, #5] +1726:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentTxPower = LoRaMacParams.ChannelsTxPower; + 542 .loc 1 1726 0 + 543 0082 0123 movs r3, #1 + 544 0084 C356 ldrsb r3, [r0, r3] + 545 0086 CB71 strb r3, [r1, #7] +1727:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** linkAdrReq.CurrentNbRep = LoRaMacParams.ChannelsNbRep; + 546 .loc 1 1727 0 + 547 0088 0023 movs r3, #0 + 548 008a C356 ldrsb r3, [r0, r3] + 549 008c 0B72 strb r3, [r1, #8] +1728:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 550 .loc 1 1728 0 + 551 008e 2023 movs r3, #32 + 552 0090 C05C ldrb r0, [r0, r3] + 553 0092 4872 strb r0, [r1, #9] +1731:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &linkAdrTxPower, &linkAdrNbRep, &linkAdrNbBytesParse + 554 .loc 1 1731 0 + 555 0094 C348 ldr r0, .L58+16 + 556 0096 0078 ldrb r0, [r0] + 557 0098 05AB add r3, sp, #20 + 558 009a 0193 str r3, [sp, #4] + 559 009c 0094 str r4, [sp] + 560 009e 6346 mov r3, ip + 561 00a0 FFF7FEFF bl RegionLinkAdrReq + 562 .LVL26: + 563 00a4 0300 movs r3, r0 + 564 00a6 8246 mov r10, r0 + 565 .LVL27: +1734:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 566 .loc 1 1734 0 + 567 00a8 0720 movs r0, #7 + 568 00aa 1840 ands r0, r3 + 569 00ac 0728 cmp r0, #7 + 570 00ae 01D0 beq .L55 + 571 .LVL28: + 572 .L38: + 573 .LBE34: +1700:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t status = 0; + 574 .loc 1 1700 0 discriminator 1 + 575 00b0 0024 movs r4, #0 + 576 00b2 12E0 b .L40 + 577 .LVL29: + 578 .L55: + 579 .LBB38: +1736:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsTxPower = linkAdrTxPower; + 580 .loc 1 1736 0 + 581 00b4 BA4B ldr r3, .L58+12 + ARM GAS /tmp/ccrFaSdZ.s page 48 + + + 582 .LVL30: + 583 00b6 0922 movs r2, #9 + 584 00b8 02A9 add r1, sp, #8 + 585 00ba 8C46 mov ip, r1 + 586 00bc 6244 add r2, r2, ip + 587 00be 1278 ldrb r2, [r2] + 588 00c0 5A70 strb r2, [r3, #1] +1737:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsNbRep = linkAdrNbRep; + 589 .loc 1 1737 0 + 590 00c2 0A22 movs r2, #10 + 591 00c4 6244 add r2, r2, ip + 592 00c6 1278 ldrb r2, [r2] + 593 00c8 1A70 strb r2, [r3] +1738:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 594 .loc 1 1738 0 + 595 00ca 0B22 movs r2, #11 + 596 00cc 6244 add r2, r2, ip + 597 00ce 1178 ldrb r1, [r2] + 598 00d0 2022 movs r2, #32 + 599 00d2 9954 strb r1, [r3, r2] + 600 00d4 ECE7 b .L38 + 601 .LVL31: + 602 .L39: + 603 .LBB35: +1742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 604 .loc 1 1742 0 + 605 00d6 0134 adds r4, r4, #1 + 606 .LVL32: + 607 00d8 E4B2 uxtb r4, r4 + 608 .LVL33: + 609 .L40: +1742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 610 .loc 1 1742 0 is_stmt 0 discriminator 1 + 611 00da 05AB add r3, sp, #20 + 612 00dc 1B78 ldrb r3, [r3] + 613 00de 9846 mov r8, r3 + 614 00e0 0521 movs r1, #5 + 615 00e2 1800 movs r0, r3 + 616 00e4 FFF7FEFF bl __aeabi_uidiv + 617 .LVL34: + 618 00e8 C0B2 uxtb r0, r0 + 619 00ea A042 cmp r0, r4 + 620 00ec 18D9 bls .L56 + 621 .LVL35: + 622 .LBB36: + 623 .LBB37: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 624 .loc 1 1553 0 is_stmt 1 + 625 00ee AE4B ldr r3, .L58+20 + 626 00f0 1A78 ldrb r2, [r3] + 627 00f2 8023 movs r3, #128 + 628 00f4 5B42 rsbs r3, r3, #0 + 629 00f6 9B1A subs r3, r3, r2 + 630 00f8 DBB2 uxtb r3, r3 + 631 .LVL36: +1566:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 632 .loc 1 1566 0 + ARM GAS /tmp/ccrFaSdZ.s page 49 + + + 633 00fa AC4A ldr r2, .L58+24 + 634 00fc 1278 ldrb r2, [r2] + 635 00fe 013B subs r3, r3, #1 + 636 .LVL37: + 637 0100 9A42 cmp r2, r3 + 638 0102 E8DA bge .L39 +1568:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Margin + 639 .loc 1 1568 0 + 640 0104 531C adds r3, r2, #1 + 641 .LVL38: + 642 0106 DBB2 uxtb r3, r3 + 643 0108 A949 ldr r1, .L58+28 + 644 010a 0320 movs r0, #3 + 645 010c 8854 strb r0, [r1, r2] +1570:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; + 646 .loc 1 1570 0 + 647 010e 0232 adds r2, r2, #2 + 648 0110 A648 ldr r0, .L58+24 + 649 0112 0270 strb r2, [r0] + 650 0114 5246 mov r2, r10 + 651 0116 CA54 strb r2, [r1, r3] + 652 .LVL39: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 653 .loc 1 1641 0 + 654 0118 A64B ldr r3, .L58+32 + 655 011a 0122 movs r2, #1 + 656 011c 1A70 strb r2, [r3] + 657 011e DAE7 b .L39 + 658 .LVL40: + 659 .L56: + 660 .LBE37: + 661 .LBE36: + 662 .LBE35: +1747:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 663 .loc 1 1747 0 + 664 0120 3400 movs r4, r6 + 665 .LVL41: + 666 0122 4444 add r4, r4, r8 + 667 0124 E4B2 uxtb r4, r4 + 668 0126 013C subs r4, r4, #1 + 669 0128 E4B2 uxtb r4, r4 + 670 .LVL42: + 671 .LBE38: +1749:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DUTY_CYCLE_REQ: + 672 .loc 1 1749 0 + 673 012a 73E7 b .L25 + 674 .LVL43: + 675 .L30: +1751:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedDCycle = 1 << MaxDCycle; + 676 .loc 1 1751 0 + 677 012c 0234 adds r4, r4, #2 + 678 012e E4B2 uxtb r4, r4 + 679 .LVL44: + 680 0130 BA5D ldrb r2, [r7, r6] + 681 0132 A14B ldr r3, .L58+36 + 682 0134 1A70 strb r2, [r3] +1752:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_DUTY_CYCLE_ANS, 0, 0 ); + ARM GAS /tmp/ccrFaSdZ.s page 50 + + + 683 .loc 1 1752 0 + 684 0136 0123 movs r3, #1 + 685 0138 9340 lsls r3, r3, r2 + 686 013a A04A ldr r2, .L58+40 + 687 013c 1380 strh r3, [r2] + 688 .LVL45: + 689 .LBB39: + 690 .LBB40: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 691 .loc 1 1553 0 + 692 013e 9A4B ldr r3, .L58+20 + 693 0140 1A78 ldrb r2, [r3] + 694 0142 8023 movs r3, #128 + 695 0144 5B42 rsbs r3, r3, #0 + 696 0146 9B1A subs r3, r3, r2 + 697 0148 DBB2 uxtb r3, r3 + 698 .LVL46: +1575:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 699 .loc 1 1575 0 + 700 014a 984A ldr r2, .L58+24 + 701 014c 1278 ldrb r2, [r2] + 702 014e 9342 cmp r3, r2 + 703 0150 00D8 bhi .LCB629 + 704 0152 5FE7 b .L25 @long jump + 705 .LCB629: +1577:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer + 706 .loc 1 1577 0 + 707 0154 511C adds r1, r2, #1 + 708 0156 954B ldr r3, .L58+24 + 709 .LVL47: + 710 0158 1970 strb r1, [r3] + 711 015a 954B ldr r3, .L58+28 + 712 015c 0421 movs r1, #4 + 713 015e 9954 strb r1, [r3, r2] + 714 .LVL48: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 715 .loc 1 1641 0 + 716 0160 944B ldr r3, .L58+32 + 717 0162 0122 movs r2, #1 + 718 0164 1A70 strb r2, [r3] + 719 0166 55E7 b .L25 + 720 .LVL49: + 721 .L31: + 722 .LBE40: + 723 .LBE39: + 724 .LBB41: +1760:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Datarate = payload[macIndex] & 0x0F; + 725 .loc 1 1760 0 + 726 0168 BA19 adds r2, r7, r6 + 727 016a 1378 ldrb r3, [r2] + 728 016c 1B09 lsrs r3, r3, #4 + 729 016e 0726 movs r6, #7 + 730 .LVL50: + 731 0170 3340 ands r3, r6 + 732 0172 07A9 add r1, sp, #28 + 733 0174 4B70 strb r3, [r1, #1] +1761:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macIndex++; + ARM GAS /tmp/ccrFaSdZ.s page 51 + + + 734 .loc 1 1761 0 + 735 0176 1278 ldrb r2, [r2] + 736 0178 52B2 sxtb r2, r2 + 737 017a 0F23 movs r3, #15 + 738 017c 1340 ands r3, r2 + 739 017e 0B70 strb r3, [r1] +1762:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 740 .loc 1 1762 0 + 741 0180 A31C adds r3, r4, #2 + 742 0182 DBB2 uxtb r3, r3 + 743 .LVL51: +1764:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 8; + 744 .loc 1 1764 0 + 745 0184 E01C adds r0, r4, #3 + 746 0186 C0B2 uxtb r0, r0 + 747 .LVL52: + 748 0188 FB5C ldrb r3, [r7, r3] +1765:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 16; + 749 .loc 1 1765 0 + 750 018a 221D adds r2, r4, #4 + 751 018c D2B2 uxtb r2, r2 + 752 .LVL53: + 753 018e 385C ldrb r0, [r7, r0] + 754 0190 0002 lsls r0, r0, #8 + 755 0192 0343 orrs r3, r0 +1766:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** rxParamSetupReq.Frequency *= 100; + 756 .loc 1 1766 0 + 757 0194 0534 adds r4, r4, #5 + 758 0196 E4B2 uxtb r4, r4 + 759 .LVL54: + 760 0198 BA5C ldrb r2, [r7, r2] + 761 019a 1204 lsls r2, r2, #16 + 762 019c 1343 orrs r3, r2 +1767:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 763 .loc 1 1767 0 + 764 019e 6422 movs r2, #100 + 765 01a0 5343 muls r3, r2 + 766 01a2 4B60 str r3, [r1, #4] +1770:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 767 .loc 1 1770 0 + 768 01a4 7F4B ldr r3, .L58+16 + 769 01a6 1878 ldrb r0, [r3] + 770 01a8 FFF7FEFF bl RegionRxParamSetupReq + 771 .LVL55: +1772:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 772 .loc 1 1772 0 + 773 01ac 0640 ands r6, r0 + 774 01ae 072E cmp r6, #7 + 775 01b0 18D0 beq .L57 + 776 .L42: + 777 .LVL56: + 778 .LBB42: + 779 .LBB43: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 780 .loc 1 1553 0 + 781 01b2 7D4B ldr r3, .L58+20 + 782 01b4 1A78 ldrb r2, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 52 + + + 783 01b6 8023 movs r3, #128 + 784 01b8 5B42 rsbs r3, r3, #0 + 785 01ba 9B1A subs r3, r3, r2 + 786 01bc DBB2 uxtb r3, r3 + 787 .LVL57: +1583:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 788 .loc 1 1583 0 + 789 01be 7B4A ldr r2, .L58+24 + 790 01c0 1278 ldrb r2, [r2] + 791 01c2 013B subs r3, r3, #1 + 792 .LVL58: + 793 01c4 9A42 cmp r2, r3 + 794 01c6 00DB blt .LCB721 + 795 01c8 24E7 b .L25 @long jump + 796 .LCB721: +1585:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Datarate ACK, Channel ACK + 797 .loc 1 1585 0 + 798 01ca 531C adds r3, r2, #1 + 799 .LVL59: + 800 01cc DBB2 uxtb r3, r3 + 801 01ce 7849 ldr r1, .L58+28 + 802 01d0 0526 movs r6, #5 + 803 01d2 8E54 strb r6, [r1, r2] +1587:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; + 804 .loc 1 1587 0 + 805 01d4 0232 adds r2, r2, #2 + 806 01d6 754E ldr r6, .L58+24 + 807 01d8 3270 strb r2, [r6] + 808 01da C854 strb r0, [r1, r3] + 809 .LVL60: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 810 .loc 1 1641 0 + 811 01dc 754B ldr r3, .L58+32 + 812 01de 0122 movs r2, #1 + 813 01e0 1A70 strb r2, [r3] + 814 .LVL61: + 815 .LBE43: + 816 .LBE42: + 817 .LBE41: +1780:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DEV_STATUS_REQ: + 818 .loc 1 1780 0 + 819 01e2 17E7 b .L25 + 820 .LVL62: + 821 .L57: + 822 .LBB44: +1774:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Frequency = rxParamSetupReq.Frequency; + 823 .loc 1 1774 0 + 824 01e4 07AA add r2, sp, #28 + 825 01e6 1678 ldrb r6, [r2] + 826 01e8 6D4B ldr r3, .L58+12 + 827 01ea 2821 movs r1, #40 + 828 01ec 5E54 strb r6, [r3, r1] +1775:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx1DrOffset = rxParamSetupReq.DrOffset; + 829 .loc 1 1775 0 + 830 01ee 0899 ldr r1, [sp, #32] + 831 01f0 5962 str r1, [r3, #36] +1776:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 53 + + + 832 .loc 1 1776 0 + 833 01f2 5178 ldrb r1, [r2, #1] + 834 01f4 2122 movs r2, #33 + 835 01f6 9954 strb r1, [r3, r2] + 836 01f8 DBE7 b .L42 + 837 .LVL63: + 838 .L32: + 839 .LBE44: + 840 .LBB45: +1784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 841 .loc 1 1784 0 + 842 01fa 714B ldr r3, .L58+44 + 843 01fc 1B68 ldr r3, [r3] + 844 01fe 002B cmp r3, #0 + 845 0200 22D0 beq .L52 +1784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 846 .loc 1 1784 0 is_stmt 0 discriminator 1 + 847 0202 1B68 ldr r3, [r3] + 848 0204 002B cmp r3, #0 + 849 0206 21D0 beq .L53 +1786:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 850 .loc 1 1786 0 is_stmt 1 + 851 0208 9847 blx r3 + 852 .LVL64: + 853 .L44: + 854 .LBB46: + 855 .LBB47: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 856 .loc 1 1553 0 + 857 020a 674B ldr r3, .L58+20 + 858 020c 1A78 ldrb r2, [r3] + 859 020e 8023 movs r3, #128 + 860 0210 5B42 rsbs r3, r3, #0 + 861 0212 9B1A subs r3, r3, r2 + 862 0214 DBB2 uxtb r3, r3 + 863 .LVL65: +1592:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 864 .loc 1 1592 0 + 865 0216 654A ldr r2, .L58+24 + 866 0218 1278 ldrb r2, [r2] + 867 021a 023B subs r3, r3, #2 + 868 .LVL66: + 869 021c 9A42 cmp r2, r3 + 870 021e 00DB blt .LCB803 + 871 0220 03E1 b .L54 @long jump + 872 .LCB803: +1594:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // 1st byte Battery + 873 .loc 1 1594 0 + 874 0222 541C adds r4, r2, #1 + 875 0224 E4B2 uxtb r4, r4 + 876 0226 6249 ldr r1, .L58+28 + 877 0228 0623 movs r3, #6 + 878 .LVL67: + 879 022a 8B54 strb r3, [r1, r2] +1597:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBuffer[MacCommandsBufferIndex++] = p2; + 880 .loc 1 1597 0 + 881 022c 931C adds r3, r2, #2 + ARM GAS /tmp/ccrFaSdZ.s page 54 + + + 882 022e DBB2 uxtb r3, r3 + 883 0230 0855 strb r0, [r1, r4] +1598:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; + 884 .loc 1 1598 0 + 885 0232 0332 adds r2, r2, #3 + 886 0234 5D48 ldr r0, .L58+24 + 887 .LVL68: + 888 0236 0270 strb r2, [r0] + 889 0238 6A46 mov r2, sp + 890 023a 127B ldrb r2, [r2, #12] + 891 023c CA54 strb r2, [r1, r3] + 892 .LVL69: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 893 .loc 1 1641 0 + 894 023e 5D4B ldr r3, .L58+32 + 895 0240 0122 movs r2, #1 + 896 0242 1A70 strb r2, [r3] + 897 .LBE47: + 898 .LBE46: + 899 .LBE45: +1706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 900 .loc 1 1706 0 + 901 0244 3400 movs r4, r6 + 902 0246 E5E6 b .L25 + 903 .LVL70: + 904 .L52: + 905 .LBB48: +1783:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacCallbacks != NULL ) && ( LoRaMacCallbacks->GetBatteryLevel != NULL + 906 .loc 1 1783 0 + 907 0248 FF20 movs r0, #255 + 908 024a DEE7 b .L44 + 909 .L53: + 910 024c FF20 movs r0, #255 + 911 024e DCE7 b .L44 + 912 .LVL71: + 913 .L33: + 914 .LBE48: + 915 .LBB49: +1797:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** newChannelReq.NewChannel = &chParam; + 916 .loc 1 1797 0 + 917 0250 A31C adds r3, r4, #2 + 918 0252 DBB2 uxtb r3, r3 + 919 .LVL72: + 920 0254 BA57 ldrsb r2, [r7, r6] + 921 0256 05A9 add r1, sp, #20 + 922 0258 0A71 strb r2, [r1, #4] +1798:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 923 .loc 1 1798 0 + 924 025a 07AA add r2, sp, #28 + 925 025c 0592 str r2, [sp, #20] +1800:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency |= ( uint32_t )payload[macIndex++] << 8; + 926 .loc 1 1800 0 + 927 025e E01C adds r0, r4, #3 + 928 0260 C0B2 uxtb r0, r0 + 929 .LVL73: + 930 0262 FB5C ldrb r3, [r7, r3] +1801:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency |= ( uint32_t )payload[macIndex++] << 16; + ARM GAS /tmp/ccrFaSdZ.s page 55 + + + 931 .loc 1 1801 0 + 932 0264 261D adds r6, r4, #4 + 933 0266 F6B2 uxtb r6, r6 + 934 .LVL74: + 935 0268 385C ldrb r0, [r7, r0] + 936 026a 0002 lsls r0, r0, #8 + 937 026c 0343 orrs r3, r0 +1802:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Frequency *= 100; + 938 .loc 1 1802 0 + 939 026e 601D adds r0, r4, #5 + 940 0270 C0B2 uxtb r0, r0 + 941 .LVL75: + 942 0272 BE5D ldrb r6, [r7, r6] + 943 0274 3604 lsls r6, r6, #16 + 944 0276 3343 orrs r3, r6 +1803:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.Rx1Frequency = 0; + 945 .loc 1 1803 0 + 946 0278 6426 movs r6, #100 + 947 027a 7343 muls r3, r6 + 948 027c 0793 str r3, [sp, #28] +1804:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chParam.DrRange.Value = payload[macIndex++]; + 949 .loc 1 1804 0 + 950 027e 0023 movs r3, #0 + 951 0280 0893 str r3, [sp, #32] +1805:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 952 .loc 1 1805 0 + 953 0282 0634 adds r4, r4, #6 + 954 0284 E4B2 uxtb r4, r4 + 955 .LVL76: + 956 0286 3B56 ldrsb r3, [r7, r0] + 957 0288 1372 strb r3, [r2, #8] +1807:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 958 .loc 1 1807 0 + 959 028a 464B ldr r3, .L58+16 + 960 028c 1878 ldrb r0, [r3] + 961 028e FFF7FEFF bl RegionNewChannelReq + 962 .LVL77: + 963 .LBB50: + 964 .LBB51: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 965 .loc 1 1553 0 + 966 0292 454B ldr r3, .L58+20 + 967 0294 1A78 ldrb r2, [r3] + 968 0296 8023 movs r3, #128 + 969 0298 5B42 rsbs r3, r3, #0 + 970 029a 9B1A subs r3, r3, r2 + 971 029c DBB2 uxtb r3, r3 + 972 .LVL78: +1603:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 973 .loc 1 1603 0 + 974 029e 434A ldr r2, .L58+24 + 975 02a0 1278 ldrb r2, [r2] + 976 02a2 013B subs r3, r3, #1 + 977 .LVL79: + 978 02a4 9A42 cmp r2, r3 + 979 02a6 00DB blt .LCB913 + 980 02a8 B4E6 b .L25 @long jump + ARM GAS /tmp/ccrFaSdZ.s page 56 + + + 981 .LCB913: +1605:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Datarate range OK, Channel frequency OK + 982 .loc 1 1605 0 + 983 02aa 531C adds r3, r2, #1 + 984 .LVL80: + 985 02ac DBB2 uxtb r3, r3 + 986 02ae 4049 ldr r1, .L58+28 + 987 02b0 5D3E subs r6, r6, #93 + 988 02b2 8E54 strb r6, [r1, r2] +1607:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; + 989 .loc 1 1607 0 + 990 02b4 0232 adds r2, r2, #2 + 991 02b6 3D4E ldr r6, .L58+24 + 992 02b8 3270 strb r2, [r6] + 993 02ba C854 strb r0, [r1, r3] + 994 .LVL81: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 995 .loc 1 1641 0 + 996 02bc 3D4B ldr r3, .L58+32 + 997 02be 0122 movs r2, #1 + 998 02c0 1A70 strb r2, [r3] + 999 .LVL82: + 1000 .LBE51: + 1001 .LBE50: + 1002 .LBE49: +1811:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_RX_TIMING_SETUP_REQ: + 1003 .loc 1 1811 0 + 1004 02c2 A7E6 b .L25 + 1005 .LVL83: + 1006 .L34: + 1007 .LBB52: +1814:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1008 .loc 1 1814 0 + 1009 02c4 0234 adds r4, r4, #2 + 1010 02c6 E4B2 uxtb r4, r4 + 1011 .LVL84: + 1012 02c8 BA5D ldrb r2, [r7, r6] + 1013 02ca 0F23 movs r3, #15 + 1014 02cc 1A40 ands r2, r3 + 1015 .LVL85: +1816:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1016 .loc 1 1816 0 + 1017 02ce 00D1 bne .L46 +1818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1018 .loc 1 1818 0 + 1019 02d0 0132 adds r2, r2, #1 + 1020 .LVL86: + 1021 .L46: +1820:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; + 1022 .loc 1 1820 0 + 1023 02d2 5301 lsls r3, r2, #5 + 1024 02d4 9B1A subs r3, r3, r2 + 1025 02d6 9B00 lsls r3, r3, #2 + 1026 02d8 9B18 adds r3, r3, r2 + 1027 02da DA00 lsls r2, r3, #3 + 1028 .LVL87: + 1029 02dc 304B ldr r3, .L58+12 + ARM GAS /tmp/ccrFaSdZ.s page 57 + + + 1030 02de 1A61 str r2, [r3, #16] +1821:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AddMacCommand( MOTE_MAC_RX_TIMING_SETUP_ANS, 0, 0 ); + 1031 .loc 1 1821 0 + 1032 02e0 FA21 movs r1, #250 + 1033 02e2 8900 lsls r1, r1, #2 + 1034 02e4 8C46 mov ip, r1 + 1035 02e6 6244 add r2, r2, ip + 1036 02e8 5A61 str r2, [r3, #20] + 1037 .LVL88: + 1038 .LBB53: + 1039 .LBB54: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1040 .loc 1 1553 0 + 1041 02ea 2F4B ldr r3, .L58+20 + 1042 02ec 1A78 ldrb r2, [r3] + 1043 02ee 8023 movs r3, #128 + 1044 02f0 5B42 rsbs r3, r3, #0 + 1045 02f2 9B1A subs r3, r3, r2 + 1046 02f4 DBB2 uxtb r3, r3 + 1047 .LVL89: +1612:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1048 .loc 1 1612 0 + 1049 02f6 2D4A ldr r2, .L58+24 + 1050 02f8 1278 ldrb r2, [r2] + 1051 02fa 9342 cmp r3, r2 + 1052 02fc 00D8 bhi .LCB991 + 1053 02fe 89E6 b .L25 @long jump + 1054 .LCB991: +1614:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer + 1055 .loc 1 1614 0 + 1056 0300 511C adds r1, r2, #1 + 1057 0302 2A4B ldr r3, .L58+24 + 1058 .LVL90: + 1059 0304 1970 strb r1, [r3] + 1060 0306 2A4B ldr r3, .L58+28 + 1061 0308 0821 movs r1, #8 + 1062 030a 9954 strb r1, [r3, r2] + 1063 .LVL91: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1064 .loc 1 1641 0 + 1065 030c 294B ldr r3, .L58+32 + 1066 030e 0122 movs r2, #1 + 1067 0310 1A70 strb r2, [r3] + 1068 0312 7FE6 b .L25 + 1069 .LVL92: + 1070 .L35: + 1071 .LBE54: + 1072 .LBE53: + 1073 .LBE52: + 1074 .LBB55: +1828:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1075 .loc 1 1828 0 + 1076 0314 0234 adds r4, r4, #2 + 1077 0316 E4B2 uxtb r4, r4 + 1078 .LVL93: + 1079 0318 BA5D ldrb r2, [r7, r6] + 1080 .LVL94: + ARM GAS /tmp/ccrFaSdZ.s page 58 + + +1830:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txParamSetupReq.DownlinkDwellTime = 0; + 1081 .loc 1 1830 0 + 1082 031a 07AB add r3, sp, #28 + 1083 031c 0021 movs r1, #0 + 1084 031e 1970 strb r1, [r3] +1831:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1085 .loc 1 1831 0 + 1086 0320 5970 strb r1, [r3, #1] +1833:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1087 .loc 1 1833 0 + 1088 0322 9306 lsls r3, r2, #26 + 1089 0324 02D5 bpl .L47 +1835:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1090 .loc 1 1835 0 + 1091 0326 07AB add r3, sp, #28 + 1092 0328 0131 adds r1, r1, #1 + 1093 032a 5970 strb r1, [r3, #1] + 1094 .L47: +1837:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1095 .loc 1 1837 0 + 1096 032c D306 lsls r3, r2, #27 + 1097 032e 02D5 bpl .L48 +1839:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1098 .loc 1 1839 0 + 1099 0330 07AB add r3, sp, #28 + 1100 0332 0121 movs r1, #1 + 1101 0334 1970 strb r1, [r3] + 1102 .L48: +1841:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1103 .loc 1 1841 0 + 1104 0336 0F23 movs r3, #15 + 1105 0338 1340 ands r3, r2 + 1106 033a 07A9 add r1, sp, #28 + 1107 033c 8B70 strb r3, [r1, #2] +1844:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1108 .loc 1 1844 0 + 1109 033e 194B ldr r3, .L58+16 + 1110 0340 1878 ldrb r0, [r3] + 1111 0342 FFF7FEFF bl RegionTxParamSetupReq + 1112 .LVL95: + 1113 0346 431C adds r3, r0, #1 + 1114 0348 00D1 bne .LCB1060 + 1115 034a 63E6 b .L25 @long jump + 1116 .LCB1060: +1847:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.DownlinkDwellTime = txParamSetupReq.DownlinkDwellTime; + 1117 .loc 1 1847 0 + 1118 034c 07AB add r3, sp, #28 + 1119 034e 1978 ldrb r1, [r3] + 1120 0350 134E ldr r6, .L58+12 + 1121 0352 2C22 movs r2, #44 + 1122 0354 B154 strb r1, [r6, r2] +1848:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MaxEirp = LoRaMacMaxEirpTable[txParamSetupReq.MaxEirp]; + 1123 .loc 1 1848 0 + 1124 0356 5978 ldrb r1, [r3, #1] + 1125 0358 0132 adds r2, r2, #1 + 1126 035a B154 strb r1, [r6, r2] +1849:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Add command response + ARM GAS /tmp/ccrFaSdZ.s page 59 + + + 1127 .loc 1 1849 0 + 1128 035c 9B78 ldrb r3, [r3, #2] + 1129 035e 194A ldr r2, .L58+48 + 1130 0360 D05C ldrb r0, [r2, r3] + 1131 0362 FFF7FEFF bl __aeabi_ui2f + 1132 .LVL96: + 1133 0366 3063 str r0, [r6, #48] + 1134 .LVL97: + 1135 .LBB56: + 1136 .LBB57: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1137 .loc 1 1553 0 + 1138 0368 0F4B ldr r3, .L58+20 + 1139 036a 1A78 ldrb r2, [r3] + 1140 036c 8023 movs r3, #128 + 1141 036e 5B42 rsbs r3, r3, #0 + 1142 0370 9B1A subs r3, r3, r2 + 1143 0372 DBB2 uxtb r3, r3 + 1144 .LVL98: +1620:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1145 .loc 1 1620 0 + 1146 0374 0D4A ldr r2, .L58+24 + 1147 0376 1278 ldrb r2, [r2] + 1148 0378 9342 cmp r3, r2 + 1149 037a 00D8 bhi .LCB1091 + 1150 037c 4AE6 b .L25 @long jump + 1151 .LCB1091: +1622:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this answer + 1152 .loc 1 1622 0 + 1153 037e 511C adds r1, r2, #1 + 1154 0380 0A4B ldr r3, .L58+24 + 1155 .LVL99: + 1156 0382 1970 strb r1, [r3] + 1157 0384 0A4B ldr r3, .L58+28 + 1158 0386 0921 movs r1, #9 + 1159 0388 9954 strb r1, [r3, r2] + 1160 .LVL100: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1161 .loc 1 1641 0 + 1162 038a 0A4B ldr r3, .L58+32 + 1163 038c 0122 movs r2, #1 + 1164 038e 1A70 strb r2, [r3] + 1165 .LBE57: + 1166 .LBE56: + 1167 .LBE55: +1854:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case SRV_MAC_DL_CHANNEL_REQ: + 1168 .loc 1 1854 0 + 1169 0390 40E6 b .L25 + 1170 .L59: + 1171 0392 C046 .align 2 + 1172 .L58: + 1173 0394 00000000 .word .L28 + 1174 0398 00000000 .word .LANCHOR28 + 1175 039c 00000000 .word .LANCHOR29 + 1176 03a0 00000000 .word .LANCHOR14 + 1177 03a4 00000000 .word .LANCHOR22 + 1178 03a8 00000000 .word .LANCHOR11 + ARM GAS /tmp/ccrFaSdZ.s page 60 + + + 1179 03ac 00000000 .word .LANCHOR10 + 1180 03b0 00000000 .word MacCommandsBuffer + 1181 03b4 00000000 .word .LANCHOR17 + 1182 03b8 00000000 .word .LANCHOR8 + 1183 03bc 00000000 .word .LANCHOR9 + 1184 03c0 00000000 .word .LANCHOR30 + 1185 03c4 00000000 .word .LANCHOR31 + 1186 .LVL101: + 1187 .L36: + 1188 .LBB58: +1860:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency = ( uint32_t )payload[macIndex++]; + 1189 .loc 1 1860 0 + 1190 03c8 A31C adds r3, r4, #2 + 1191 03ca DBB2 uxtb r3, r3 + 1192 .LVL102: + 1193 03cc BA5D ldrb r2, [r7, r6] + 1194 03ce 07A9 add r1, sp, #28 + 1195 03d0 0A70 strb r2, [r1] +1861:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 8; + 1196 .loc 1 1861 0 + 1197 03d2 E01C adds r0, r4, #3 + 1198 03d4 C0B2 uxtb r0, r0 + 1199 .LVL103: + 1200 03d6 FB5C ldrb r3, [r7, r3] +1862:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 16; + 1201 .loc 1 1862 0 + 1202 03d8 221D adds r2, r4, #4 + 1203 03da D2B2 uxtb r2, r2 + 1204 .LVL104: + 1205 03dc 385C ldrb r0, [r7, r0] + 1206 03de 0002 lsls r0, r0, #8 + 1207 03e0 0343 orrs r3, r0 +1863:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** dlChannelReq.Rx1Frequency *= 100; + 1208 .loc 1 1863 0 + 1209 03e2 0534 adds r4, r4, #5 + 1210 03e4 E4B2 uxtb r4, r4 + 1211 .LVL105: + 1212 03e6 BA5C ldrb r2, [r7, r2] + 1213 03e8 1204 lsls r2, r2, #16 + 1214 03ea 1343 orrs r3, r2 +1864:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1215 .loc 1 1864 0 + 1216 03ec 6422 movs r2, #100 + 1217 03ee 5343 muls r3, r2 + 1218 03f0 4B60 str r3, [r1, #4] +1866:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1219 .loc 1 1866 0 + 1220 03f2 124B ldr r3, .L60 + 1221 03f4 1878 ldrb r0, [r3] + 1222 03f6 FFF7FEFF bl RegionDlChannelReq + 1223 .LVL106: + 1224 .LBB59: + 1225 .LBB60: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1226 .loc 1 1553 0 + 1227 03fa 114B ldr r3, .L60+4 + 1228 03fc 1A78 ldrb r2, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 61 + + + 1229 03fe 8023 movs r3, #128 + 1230 0400 5B42 rsbs r3, r3, #0 + 1231 0402 9B1A subs r3, r3, r2 + 1232 0404 DBB2 uxtb r3, r3 + 1233 .LVL107: +1628:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1234 .loc 1 1628 0 + 1235 0406 0F4A ldr r2, .L60+8 + 1236 0408 1278 ldrb r2, [r2] + 1237 040a 9342 cmp r3, r2 + 1238 040c 00D8 bhi .LCB1184 + 1239 040e 01E6 b .L25 @long jump + 1240 .LCB1184: +1630:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Status: Uplink frequency exists, Channel frequency OK + 1241 .loc 1 1630 0 + 1242 0410 531C adds r3, r2, #1 + 1243 .LVL108: + 1244 0412 DBB2 uxtb r3, r3 + 1245 0414 0C49 ldr r1, .L60+12 + 1246 0416 0A26 movs r6, #10 + 1247 0418 8E54 strb r6, [r1, r2] +1632:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_OK; + 1248 .loc 1 1632 0 + 1249 041a 0232 adds r2, r2, #2 + 1250 041c 094E ldr r6, .L60+8 + 1251 041e 3270 strb r2, [r6] + 1252 0420 C854 strb r0, [r1, r3] + 1253 .LVL109: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1254 .loc 1 1641 0 + 1255 0422 0A4B ldr r3, .L60+16 + 1256 0424 0122 movs r2, #1 + 1257 0426 1A70 strb r2, [r3] + 1258 .LVL110: + 1259 .LBE60: + 1260 .LBE59: + 1261 .LBE58: +1870:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: + 1262 .loc 1 1870 0 + 1263 0428 F4E5 b .L25 + 1264 .LVL111: + 1265 .L54: +1706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1266 .loc 1 1706 0 + 1267 042a 3400 movs r4, r6 + 1268 042c F2E5 b .L25 + 1269 .LVL112: + 1270 .L24: +1876:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1271 .loc 1 1876 0 + 1272 042e 0AB0 add sp, sp, #40 + 1273 @ sp needed + 1274 .LVL113: + 1275 0430 1CBC pop {r2, r3, r4} + 1276 0432 9046 mov r8, r2 + 1277 0434 9946 mov r9, r3 + 1278 0436 A246 mov r10, r4 + ARM GAS /tmp/ccrFaSdZ.s page 62 + + + 1279 0438 F0BD pop {r4, r5, r6, r7, pc} + 1280 .L61: + 1281 043a C046 .align 2 + 1282 .L60: + 1283 043c 00000000 .word .LANCHOR22 + 1284 0440 00000000 .word .LANCHOR11 + 1285 0444 00000000 .word .LANCHOR10 + 1286 0448 00000000 .word MacCommandsBuffer + 1287 044c 00000000 .word .LANCHOR17 + 1288 .cfi_endproc + 1289 .LFE100: + 1291 .section .text.OnRadioRxDone,"ax",%progbits + 1292 .align 1 + 1293 .syntax unified + 1294 .code 16 + 1295 .thumb_func + 1296 .fpu softvfp + 1298 OnRadioRxDone: + 1299 .LFB87: + 702:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + 1300 .loc 1 702 0 + 1301 .cfi_startproc + 1302 @ args = 0, pretend = 0, frame = 48 + 1303 @ frame_needed = 0, uses_anonymous_args = 0 + 1304 .LVL114: + 1305 0000 F0B5 push {r4, r5, r6, r7, lr} + 1306 .LCFI8: + 1307 .cfi_def_cfa_offset 20 + 1308 .cfi_offset 4, -20 + 1309 .cfi_offset 5, -16 + 1310 .cfi_offset 6, -12 + 1311 .cfi_offset 7, -8 + 1312 .cfi_offset 14, -4 + 1313 0002 DE46 mov lr, fp + 1314 0004 5746 mov r7, r10 + 1315 0006 4E46 mov r6, r9 + 1316 0008 4546 mov r5, r8 + 1317 000a E0B5 push {r5, r6, r7, lr} + 1318 .LCFI9: + 1319 .cfi_def_cfa_offset 36 + 1320 .cfi_offset 8, -36 + 1321 .cfi_offset 9, -32 + 1322 .cfi_offset 10, -28 + 1323 .cfi_offset 11, -24 + 1324 000c 91B0 sub sp, sp, #68 + 1325 .LCFI10: + 1326 .cfi_def_cfa_offset 104 + 1327 000e 0400 movs r4, r0 + 1328 0010 0E00 movs r6, r1 + 1329 .LVL115: + 715:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t micRx = 0; + 1330 .loc 1 715 0 + 1331 0012 0020 movs r0, #0 + 1332 .LVL116: + 1333 0014 0C90 str r0, [sp, #48] + 1334 .LVL117: + 731:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Rssi = rssi; + ARM GAS /tmp/ccrFaSdZ.s page 63 + + + 1335 .loc 1 731 0 + 1336 0016 9049 ldr r1, .L126 + 1337 .LVL118: + 1338 0018 0871 strb r0, [r1, #4] + 732:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Snr = snr; + 1339 .loc 1 732 0 + 1340 001a 9049 ldr r1, .L126+4 + 1341 001c CA81 strh r2, [r1, #14] + 733:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxSlot = RxSlot; + 1342 .loc 1 733 0 + 1343 001e DDB2 uxtb r5, r3 + 1344 0020 0D74 strb r5, [r1, #16] + 734:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Port = 0; + 1345 .loc 1 734 0 + 1346 0022 8F4B ldr r3, .L126+8 + 1347 .LVL119: + 1348 0024 1B78 ldrb r3, [r3] + 1349 0026 4B74 strb r3, [r1, #17] + 735:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Multicast = 0; + 1350 .loc 1 735 0 + 1351 0028 C870 strb r0, [r1, #3] + 736:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.FramePending = 0; + 1352 .loc 1 736 0 + 1353 002a 8870 strb r0, [r1, #2] + 737:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = NULL; + 1354 .loc 1 737 0 + 1355 002c 4871 strb r0, [r1, #5] + 738:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = 0; + 1356 .loc 1 738 0 + 1357 002e 8860 str r0, [r1, #8] + 739:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxData = false; + 1358 .loc 1 739 0 + 1359 0030 0873 strb r0, [r1, #12] + 740:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.AckReceived = false; + 1360 .loc 1 740 0 + 1361 0032 4873 strb r0, [r1, #13] + 741:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = 0; + 1362 .loc 1 741 0 + 1363 0034 8874 strb r0, [r1, #18] + 742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + 1364 .loc 1 742 0 + 1365 0036 4861 str r0, [r1, #20] + 743:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1366 .loc 1 743 0 + 1367 0038 0870 strb r0, [r1] + 745:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer2 ); + 1368 .loc 1 745 0 + 1369 003a 8A4B ldr r3, .L126+12 + 1370 003c 5B6B ldr r3, [r3, #52] + 1371 003e 9847 blx r3 + 1372 .LVL120: + 746:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1373 .loc 1 746 0 + 1374 0040 8948 ldr r0, .L126+16 + 1375 0042 FFF7FEFF bl TimerStop + 1376 .LVL121: + 748:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 64 + + + 1377 .loc 1 748 0 + 1378 0046 2378 ldrb r3, [r4] + 1379 0048 9846 mov r8, r3 + 750:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1380 .loc 1 750 0 + 1381 004a 5B09 lsrs r3, r3, #5 + 1382 004c 032B cmp r3, #3 + 1383 004e 00D1 bne .LCB1344 + 1384 0050 B3E0 b .L64 @long jump + 1385 .LCB1344: + 1386 0052 2CD9 bls .L107 + 1387 0054 052B cmp r3, #5 + 1388 0056 00D1 bne .LCB1348 + 1389 0058 AFE0 b .L64 @long jump + 1390 .LCB1348: + 1391 005a 072B cmp r3, #7 + 1392 005c 00D0 beq .LCB1350 + 1393 005e ABE2 b .L63 @long jump + 1394 .LCB1350: +1098:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1395 .loc 1 1098 0 + 1396 0060 611C adds r1, r4, #1 + 1397 0062 824C ldr r4, .L126+20 + 1398 .LVL122: + 1399 0064 3200 movs r2, r6 + 1400 0066 2000 movs r0, r4 + 1401 0068 FFF7FEFF bl memcpy1 + 1402 .LVL123: +1100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_OK; + 1403 .loc 1 1100 0 + 1404 006c 7B4B ldr r3, .L126+4 + 1405 006e 0322 movs r2, #3 + 1406 0070 1A70 strb r2, [r3] +1101:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = LoRaMacRxPayload; + 1407 .loc 1 1101 0 + 1408 0072 0022 movs r2, #0 + 1409 0074 5A70 strb r2, [r3, #1] +1102:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = size - pktHeaderLen; + 1410 .loc 1 1102 0 + 1411 0076 9C60 str r4, [r3, #8] +1103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1412 .loc 1 1103 0 + 1413 0078 013E subs r6, r6, #1 + 1414 007a 1E73 strb r6, [r3, #12] +1105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 1415 .loc 1 1105 0 + 1416 007c 7C4A ldr r2, .L126+24 + 1417 007e 1378 ldrb r3, [r2] + 1418 0080 0221 movs r1, #2 + 1419 0082 0B43 orrs r3, r1 + 1420 0084 1370 strb r3, [r2] + 1421 .LVL124: + 1422 .L72: +1113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1423 .loc 1 1113 0 discriminator 1 + 1424 0086 7A4A ldr r2, .L126+24 + 1425 0088 1378 ldrb r3, [r2] + ARM GAS /tmp/ccrFaSdZ.s page 65 + + + 1426 008a 1021 movs r1, #16 + 1427 008c 0B43 orrs r3, r1 + 1428 008e 1370 strb r3, [r2] +1116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 1429 .loc 1 1116 0 discriminator 1 + 1430 0090 784C ldr r4, .L126+28 + 1431 0092 0121 movs r1, #1 + 1432 0094 2000 movs r0, r4 + 1433 0096 FFF7FEFF bl TimerSetValue + 1434 .LVL125: +1117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1435 .loc 1 1117 0 discriminator 1 + 1436 009a 2000 movs r0, r4 + 1437 009c FFF7FEFF bl TimerStart + 1438 .LVL126: + 1439 .L62: +1118:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1440 .loc 1 1118 0 + 1441 00a0 11B0 add sp, sp, #68 + 1442 @ sp needed + 1443 00a2 3CBC pop {r2, r3, r4, r5} + 1444 00a4 9046 mov r8, r2 + 1445 00a6 9946 mov r9, r3 + 1446 00a8 A246 mov r10, r4 + 1447 00aa AB46 mov fp, r5 + 1448 00ac F0BD pop {r4, r5, r6, r7, pc} + 1449 .LVL127: + 1450 .L107: + 750:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1451 .loc 1 750 0 + 1452 00ae 012B cmp r3, #1 + 1453 00b0 00D0 beq .LCB1441 + 1454 00b2 81E2 b .L63 @long jump + 1455 .LCB1441: + 753:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1456 .loc 1 753 0 + 1457 00b4 704B ldr r3, .L126+32 + 1458 00b6 1B78 ldrb r3, [r3] + 1459 00b8 002B cmp r3, #0 + 1460 00ba 05D0 beq .L68 + 755:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 1461 .loc 1 755 0 + 1462 00bc 674B ldr r3, .L126+4 + 1463 00be 0122 movs r2, #1 + 1464 00c0 5A70 strb r2, [r3, #1] + 756:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 1465 .loc 1 756 0 + 1466 00c2 FFF7FEFF bl PrepareRxDoneAbort + 1467 .LVL128: + 757:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1468 .loc 1 757 0 + 1469 00c6 EBE7 b .L62 + 1470 .L68: + 759:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1471 .loc 1 759 0 + 1472 00c8 601C adds r0, r4, #1 + 1473 00ca 6C4C ldr r4, .L126+36 + ARM GAS /tmp/ccrFaSdZ.s page 66 + + + 1474 .LVL129: + 1475 00cc 6C4F ldr r7, .L126+40 + 1476 00ce 751E subs r5, r6, #1 + 1477 00d0 A9B2 uxth r1, r5 + 1478 00d2 2300 movs r3, r4 + 1479 00d4 3A68 ldr r2, [r7] + 1480 00d6 FFF7FEFF bl LoRaMacJoinDecrypt + 1481 .LVL130: + 761:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1482 .loc 1 761 0 + 1483 00da 013C subs r4, r4, #1 + 1484 00dc 4346 mov r3, r8 + 1485 00de 2370 strb r3, [r4] + 763:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1486 .loc 1 763 0 + 1487 00e0 3A68 ldr r2, [r7] + 1488 00e2 371F subs r7, r6, #4 + 1489 00e4 B9B2 uxth r1, r7 + 1490 00e6 0CAB add r3, sp, #48 + 1491 00e8 2000 movs r0, r4 + 1492 00ea FFF7FEFF bl LoRaMacJoinComputeMic + 1493 .LVL131: + 765:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 1] << 8 ); + 1494 .loc 1 765 0 + 1495 00ee E25D ldrb r2, [r4, r7] + 1496 .LVL132: + 766:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 2] << 16 ); + 1497 .loc 1 766 0 + 1498 00f0 F31E subs r3, r6, #3 + 1499 00f2 E35C ldrb r3, [r4, r3] + 1500 00f4 1B02 lsls r3, r3, #8 + 1501 00f6 1A43 orrs r2, r3 + 1502 .LVL133: + 767:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 3] << 24 ); + 1503 .loc 1 767 0 + 1504 00f8 B31E subs r3, r6, #2 + 1505 00fa E35C ldrb r3, [r4, r3] + 1506 00fc 1B04 lsls r3, r3, #16 + 1507 00fe 1A43 orrs r2, r3 + 1508 .LVL134: + 768:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1509 .loc 1 768 0 + 1510 0100 635D ldrb r3, [r4, r5] + 1511 0102 1B06 lsls r3, r3, #24 + 1512 0104 1343 orrs r3, r2 + 1513 .LVL135: + 770:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1514 .loc 1 770 0 + 1515 0106 0C9A ldr r2, [sp, #48] + 1516 0108 9A42 cmp r2, r3 + 1517 010a 03D0 beq .L108 + 809:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1518 .loc 1 809 0 + 1519 010c 5D4B ldr r3, .L126+44 + 1520 .LVL136: + 1521 010e 0722 movs r2, #7 + 1522 0110 5A70 strb r2, [r3, #1] + ARM GAS /tmp/ccrFaSdZ.s page 67 + + + 1523 0112 B8E7 b .L72 + 1524 .LVL137: + 1525 .L108: + 772:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1526 .loc 1 772 0 + 1527 0114 5C4B ldr r3, .L126+48 + 1528 .LVL138: + 1529 0116 1A88 ldrh r2, [r3] + 1530 0118 584C ldr r4, .L126+36 + 1531 .LVL139: + 1532 011a 594B ldr r3, .L126+40 + 1533 011c 1868 ldr r0, [r3] + 1534 011e 5B4B ldr r3, .L126+52 + 1535 0120 0093 str r3, [sp] + 1536 0122 5B4B ldr r3, .L126+56 + 1537 0124 2100 movs r1, r4 + 1538 0126 FFF7FEFF bl LoRaMacJoinComputeSKeys + 1539 .LVL140: + 774:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[5] << 8 ); + 1540 .loc 1 774 0 + 1541 012a 611E subs r1, r4, #1 + 1542 012c E378 ldrb r3, [r4, #3] + 775:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[6] << 16 ); + 1543 .loc 1 775 0 + 1544 012e 2279 ldrb r2, [r4, #4] + 1545 0130 1202 lsls r2, r2, #8 + 1546 0132 1343 orrs r3, r2 + 776:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1547 .loc 1 776 0 + 1548 0134 6279 ldrb r2, [r4, #5] + 1549 0136 1204 lsls r2, r2, #16 + 1550 0138 1343 orrs r3, r2 + 1551 013a 564A ldr r2, .L126+60 + 1552 013c 1360 str r3, [r2] + 778:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[8] << 8 ); + 1553 .loc 1 778 0 + 1554 013e A379 ldrb r3, [r4, #6] + 779:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[9] << 16 ); + 1555 .loc 1 779 0 + 1556 0140 E279 ldrb r2, [r4, #7] + 1557 0142 1202 lsls r2, r2, #8 + 1558 0144 1343 orrs r3, r2 + 780:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[10] << 24 ); + 1559 .loc 1 780 0 + 1560 0146 227A ldrb r2, [r4, #8] + 1561 0148 1204 lsls r2, r2, #16 + 1562 014a 1343 orrs r3, r2 + 781:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1563 .loc 1 781 0 + 1564 014c 627A ldrb r2, [r4, #9] + 1565 014e 1206 lsls r2, r2, #24 + 1566 0150 1343 orrs r3, r2 + 1567 0152 514A ldr r2, .L126+64 + 1568 0154 1360 str r3, [r2] + 784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate = LoRaMacRxPayload[11] & 0x0F; + 1569 .loc 1 784 0 + 1570 0156 A27A ldrb r2, [r4, #10] + ARM GAS /tmp/ccrFaSdZ.s page 68 + + + 1571 0158 1009 lsrs r0, r2, #4 + 1572 015a 0723 movs r3, #7 + 1573 015c 0340 ands r3, r0 + 1574 015e 4F48 ldr r0, .L126+68 + 1575 0160 2124 movs r4, #33 + 1576 0162 0355 strb r3, [r0, r4] + 785:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1577 .loc 1 785 0 + 1578 0164 0F23 movs r3, #15 + 1579 0166 1A40 ands r2, r3 + 1580 0168 0734 adds r4, r4, #7 + 1581 016a 0255 strb r2, [r0, r4] + 788:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacParams.ReceiveDelay1 == 0 ) + 1582 .loc 1 788 0 + 1583 016c 0A7B ldrb r2, [r1, #12] + 1584 016e 1340 ands r3, r2 + 1585 0170 0361 str r3, [r0, #16] + 789:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1586 .loc 1 789 0 + 1587 0172 01D1 bne .L71 + 791:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1588 .loc 1 791 0 + 1589 0174 0122 movs r2, #1 + 1590 0176 0261 str r2, [r0, #16] + 1591 .L71: + 793:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; + 1592 .loc 1 793 0 + 1593 0178 484C ldr r4, .L126+68 + 1594 017a 2269 ldr r2, [r4, #16] + 1595 017c 5301 lsls r3, r2, #5 + 1596 017e 9B1A subs r3, r3, r2 + 1597 0180 9B00 lsls r3, r3, #2 + 1598 0182 9B18 adds r3, r3, r2 + 1599 0184 DB00 lsls r3, r3, #3 + 1600 0186 2361 str r3, [r4, #16] + 794:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1601 .loc 1 794 0 + 1602 0188 FA22 movs r2, #250 + 1603 018a 9200 lsls r2, r2, #2 + 1604 018c 9446 mov ip, r2 + 1605 018e 6344 add r3, r3, ip + 1606 0190 6361 str r3, [r4, #20] + 797:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Size of the regular payload is 12. Plus 1 byte MHDR and 4 bytes MIC + 1607 .loc 1 797 0 + 1608 0192 0EA9 add r1, sp, #56 + 1609 0194 424B ldr r3, .L126+72 + 1610 0196 0E93 str r3, [sp, #56] + 799:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1611 .loc 1 799 0 + 1612 0198 113E subs r6, r6, #17 + 1613 019a 0E71 strb r6, [r1, #4] + 801:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1614 .loc 1 801 0 + 1615 019c 414B ldr r3, .L126+76 + 1616 019e 1878 ldrb r0, [r3] + 1617 01a0 FFF7FEFF bl RegionApplyCFList + 1618 .LVL141: + ARM GAS /tmp/ccrFaSdZ.s page 69 + + + 803:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsLoRaMacNetworkJoined = true; + 1619 .loc 1 803 0 + 1620 01a4 374B ldr r3, .L126+44 + 1621 01a6 0022 movs r2, #0 + 1622 01a8 5A70 strb r2, [r3, #1] + 804:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + 1623 .loc 1 804 0 + 1624 01aa 334B ldr r3, .L126+32 + 1625 01ac 0132 adds r2, r2, #1 + 1626 01ae 1A70 strb r2, [r3] + 805:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1627 .loc 1 805 0 + 1628 01b0 3D4B ldr r3, .L126+80 + 1629 01b2 5B78 ldrb r3, [r3, #1] + 1630 01b4 5BB2 sxtb r3, r3 + 1631 01b6 6370 strb r3, [r4, #1] + 1632 01b8 65E7 b .L72 + 1633 .LVL142: + 1634 .L64: + 816:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = McpsIndication.RxDatarate; + 1635 .loc 1 816 0 + 1636 01ba 384A ldr r2, .L126+68 + 1637 01bc 2D23 movs r3, #45 + 1638 01be D25C ldrb r2, [r2, r3] + 1639 01c0 0DAB add r3, sp, #52 + 1640 01c2 9A70 strb r2, [r3, #2] + 817:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD; + 1641 .loc 1 817 0 + 1642 01c4 254A ldr r2, .L126+4 + 1643 01c6 1279 ldrb r2, [r2, #4] + 1644 01c8 52B2 sxtb r2, r2 + 1645 01ca 5A70 strb r2, [r3, #1] + 818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1646 .loc 1 818 0 + 1647 01cc 0922 movs r2, #9 + 1648 01ce 1A70 strb r2, [r3] + 821:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1649 .loc 1 821 0 + 1650 01d0 364B ldr r3, .L126+84 + 1651 01d2 1B78 ldrb r3, [r3] + 1652 01d4 002B cmp r3, #0 + 1653 01d6 02D0 beq .L73 + 823:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1654 .loc 1 823 0 + 1655 01d8 0DAB add r3, sp, #52 + 1656 01da 0132 adds r2, r2, #1 + 1657 01dc 1A70 strb r2, [r3] + 1658 .L73: + 825:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MAX( 0, ( int16_t )( ( int16_t )size - ( int16_t )LORA_MAC_FRMPAYLOAD_OVERHEAD + 1659 .loc 1 825 0 + 1660 01de 314B ldr r3, .L126+76 + 1661 01e0 1878 ldrb r0, [r3] + 1662 01e2 0DA9 add r1, sp, #52 + 1663 01e4 FFF7FEFF bl RegionGetPhyParam + 1664 .LVL143: + 826:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1665 .loc 1 826 0 + ARM GAS /tmp/ccrFaSdZ.s page 70 + + + 1666 01e8 3300 movs r3, r6 + 1667 01ea 0D3B subs r3, r3, #13 + 1668 01ec 1BB2 sxth r3, r3 + 1669 01ee 1A1C adds r2, r3, #0 + 1670 01f0 002B cmp r3, #0 + 1671 01f2 1CDB blt .L109 + 1672 .L74: + 1673 01f4 12B2 sxth r2, r2 + 1674 .LVL144: + 1675 01f6 8242 cmp r2, r0 + 1676 01f8 1BD8 bhi .L110 + 1677 .LVL145: + 833:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 8 ); + 1678 .loc 1 833 0 + 1679 01fa 6378 ldrb r3, [r4, #1] + 1680 .LVL146: + 834:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 16 ); + 1681 .loc 1 834 0 + 1682 01fc A278 ldrb r2, [r4, #2] + 1683 01fe 1202 lsls r2, r2, #8 + 1684 0200 1343 orrs r3, r2 + 1685 .LVL147: + 835:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** address |= ( (uint32_t)payload[pktHeaderLen++] << 24 ); + 1686 .loc 1 835 0 + 1687 0202 E278 ldrb r2, [r4, #3] + 1688 0204 1204 lsls r2, r2, #16 + 1689 0206 1343 orrs r3, r2 + 1690 .LVL148: + 836:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1691 .loc 1 836 0 + 1692 0208 2279 ldrb r2, [r4, #4] + 1693 020a 1206 lsls r2, r2, #24 + 1694 020c 1343 orrs r3, r2 + 1695 .LVL149: + 1696 020e 9946 mov r9, r3 + 1697 .LVL150: + 838:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1698 .loc 1 838 0 + 1699 0210 214B ldr r3, .L126+64 + 1700 .LVL151: + 1701 0212 1B68 ldr r3, [r3] + 1702 0214 4B45 cmp r3, r9 + 1703 0216 00D1 bne .LCB1669 + 1704 0218 02E1 b .L76 @long jump + 1705 .LCB1669: + 840:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( curMulticastParams != NULL ) + 1706 .loc 1 840 0 + 1707 021a 254B ldr r3, .L126+88 + 1708 021c 1F68 ldr r7, [r3] + 1709 .LVL152: + 1710 021e 4B46 mov r3, r9 + 1711 .L77: + 841:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1712 .loc 1 841 0 + 1713 0220 002F cmp r7, #0 + 1714 0222 47D0 beq .L111 + 843:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 71 + + + 1715 .loc 1 843 0 + 1716 0224 3A68 ldr r2, [r7] + 1717 0226 9A42 cmp r2, r3 + 1718 0228 09D0 beq .L112 + 851:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1719 .loc 1 851 0 + 1720 022a BF6A ldr r7, [r7, #40] + 1721 .LVL153: + 1722 022c F8E7 b .L77 + 1723 .LVL154: + 1724 .L109: + 826:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1725 .loc 1 826 0 + 1726 022e 0022 movs r2, #0 + 1727 0230 E0E7 b .L74 + 1728 .LVL155: + 1729 .L110: + 828:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 1730 .loc 1 828 0 + 1731 0232 0A4B ldr r3, .L126+4 + 1732 0234 0122 movs r2, #1 + 1733 0236 5A70 strb r2, [r3, #1] + 829:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 1734 .loc 1 829 0 + 1735 0238 FFF7FEFF bl PrepareRxDoneAbort + 1736 .LVL156: + 830:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1737 .loc 1 830 0 + 1738 023c 30E7 b .L62 + 1739 .LVL157: + 1740 .L112: + 1741 023e 9946 mov r9, r3 + 1742 .LVL158: + 846:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appSKey = curMulticastParams->AppSKey; + 1743 .loc 1 846 0 + 1744 0240 3B1D adds r3, r7, #4 + 1745 .LVL159: + 1746 0242 0693 str r3, [sp, #24] + 1747 .LVL160: + 847:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = curMulticastParams->DownLinkCounter; + 1748 .loc 1 847 0 + 1749 0244 1423 movs r3, #20 + 1750 .LVL161: + 1751 0246 9C46 mov ip, r3 + 1752 0248 BC44 add ip, ip, r7 + 1753 024a 6346 mov r3, ip + 1754 024c 0A93 str r3, [sp, #40] + 1755 .LVL162: + 848:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 1756 .loc 1 848 0 + 1757 024e 7B6A ldr r3, [r7, #36] + 1758 .LVL163: + 1759 0250 0493 str r3, [sp, #16] + 1760 .LVL164: + 845:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nwkSKey = curMulticastParams->NwkSKey; + 1761 .loc 1 845 0 + 1762 0252 0123 movs r3, #1 + ARM GAS /tmp/ccrFaSdZ.s page 72 + + + 1763 .LVL165: + 1764 0254 0593 str r3, [sp, #20] + 849:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1765 .loc 1 849 0 + 1766 0256 36E0 b .L79 + 1767 .L127: + 1768 .align 2 + 1769 .L126: + 1770 0258 00000000 .word .LANCHOR34 + 1771 025c 00000000 .word .LANCHOR35 + 1772 0260 00000000 .word .LANCHOR36 + 1773 0264 00000000 .word Radio + 1774 0268 00000000 .word .LANCHOR37 + 1775 026c 00000000 .word LoRaMacRxPayload + 1776 0270 00000000 .word .LANCHOR26 + 1777 0274 00000000 .word .LANCHOR27 + 1778 0278 00000000 .word .LANCHOR0 + 1779 027c 01000000 .word LoRaMacRxPayload+1 + 1780 0280 00000000 .word .LANCHOR38 + 1781 0284 00000000 .word .LANCHOR28 + 1782 0288 00000000 .word .LANCHOR39 + 1783 028c 00000000 .word .LANCHOR32 + 1784 0290 00000000 .word .LANCHOR33 + 1785 0294 00000000 .word .LANCHOR40 + 1786 0298 00000000 .word .LANCHOR41 + 1787 029c 00000000 .word .LANCHOR14 + 1788 02a0 0D000000 .word LoRaMacRxPayload+13 + 1789 02a4 00000000 .word .LANCHOR22 + 1790 02a8 00000000 .word .LANCHOR13 + 1791 02ac 00000000 .word .LANCHOR21 + 1792 02b0 00000000 .word .LANCHOR18 + 1793 .LVL166: + 1794 .L111: + 1795 02b4 9946 mov r9, r3 + 727:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1796 .loc 1 727 0 + 1797 02b6 0023 movs r3, #0 + 1798 .LVL167: + 1799 02b8 0593 str r3, [sp, #20] + 725:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1800 .loc 1 725 0 + 1801 02ba C24B ldr r3, .L128 + 1802 02bc 0A93 str r3, [sp, #40] + 724:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t *appSKey = LoRaMacAppSKey; + 1803 .loc 1 724 0 + 1804 02be C24B ldr r3, .L128+4 + 1805 02c0 0693 str r3, [sp, #24] + 721:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1806 .loc 1 721 0 + 1807 02c2 0023 movs r3, #0 + 1808 02c4 0493 str r3, [sp, #16] + 1809 .LVL168: + 1810 .L79: + 853:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1811 .loc 1 853 0 + 1812 02c6 059B ldr r3, [sp, #20] + 1813 02c8 002B cmp r3, #0 + ARM GAS /tmp/ccrFaSdZ.s page 73 + + + 1814 02ca 00D1 bne .LCB1799 + 1815 02cc A2E0 b .L113 @long jump + 1816 .LCB1799: + 1817 .LVL169: + 1818 .L81: + 869:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1819 .loc 1 869 0 + 1820 02ce 6379 ldrb r3, [r4, #5] + 1821 02d0 9B46 mov fp, r3 + 1822 .LVL170: + 871:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounter |= ( uint16_t )payload[pktHeaderLen++] << 8; + 1823 .loc 1 871 0 + 1824 02d2 A279 ldrb r2, [r4, #6] + 1825 .LVL171: + 872:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1826 .loc 1 872 0 + 1827 02d4 E379 ldrb r3, [r4, #7] + 1828 02d6 1B02 lsls r3, r3, #8 + 1829 02d8 1A43 orrs r2, r3 + 1830 .LVL172: + 874:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1831 .loc 1 874 0 + 1832 02da 5B46 mov r3, fp + 1833 02dc 1807 lsls r0, r3, #28 + 1834 .LVL173: + 1835 02de 030F lsrs r3, r0, #28 + 1836 02e0 0B93 str r3, [sp, #44] + 1837 02e2 0833 adds r3, r3, #8 + 1838 02e4 0993 str r3, [sp, #36] + 1839 .LVL174: + 876:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 1] << 8 ); + 1840 .loc 1 876 0 + 1841 02e6 A319 adds r3, r4, r6 + 1842 02e8 191F subs r1, r3, #4 + 1843 02ea 0878 ldrb r0, [r1] + 1844 .LVL175: + 877:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 2] << 16 ); + 1845 .loc 1 877 0 + 1846 02ec D91E subs r1, r3, #3 + 1847 02ee 0978 ldrb r1, [r1] + 1848 02f0 0902 lsls r1, r1, #8 + 1849 02f2 0843 orrs r0, r1 + 1850 .LVL176: + 878:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 3] << 24 ); + 1851 .loc 1 878 0 + 1852 02f4 991E subs r1, r3, #2 + 1853 02f6 0978 ldrb r1, [r1] + 1854 02f8 0904 lsls r1, r1, #16 + 1855 02fa 0143 orrs r1, r0 + 1856 .LVL177: + 879:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1857 .loc 1 879 0 + 1858 02fc 013B subs r3, r3, #1 + 1859 02fe 1B78 ldrb r3, [r3] + 1860 0300 1B06 lsls r3, r3, #24 + 1861 0302 0B43 orrs r3, r1 + 1862 0304 0893 str r3, [sp, #32] + ARM GAS /tmp/ccrFaSdZ.s page 74 + + + 1863 .LVL178: + 881:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sequenceCounterDiff = ( sequenceCounter - sequenceCounterPrev ); + 1864 .loc 1 881 0 + 1865 0306 0499 ldr r1, [sp, #16] + 1866 0308 8BB2 uxth r3, r1 + 1867 .LVL179: + 882:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1868 .loc 1 882 0 + 1869 030a D31A subs r3, r2, r3 + 1870 .LVL180: + 1871 030c 9AB2 uxth r2, r3 + 1872 .LVL181: + 1873 030e 0792 str r2, [sp, #28] + 1874 .LVL182: + 884:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1875 .loc 1 884 0 + 1876 0310 13B2 sxth r3, r2 + 1877 0312 002B cmp r3, #0 + 1878 0314 00DA bge .LCB1868 + 1879 0316 8EE0 b .L82 @long jump + 1880 .LCB1868: + 886:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK + 1881 .loc 1 886 0 + 1882 0318 9446 mov ip, r2 + 1883 031a 6144 add r1, r1, ip + 1884 .LVL183: + 1885 031c 8A46 mov r10, r1 + 1886 .LVL184: + 887:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( micRx == mic ) + 1887 .loc 1 887 0 + 1888 031e 311F subs r1, r6, #4 + 1889 .LVL185: + 1890 0320 89B2 uxth r1, r1 + 1891 0322 0CAB add r3, sp, #48 + 1892 0324 0293 str r3, [sp, #8] + 1893 .LVL186: + 1894 0326 5246 mov r2, r10 + 1895 .LVL187: + 1896 0328 0192 str r2, [sp, #4] + 1897 032a 0123 movs r3, #1 + 1898 032c 0093 str r3, [sp] + 1899 032e 4B46 mov r3, r9 + 1900 0330 069A ldr r2, [sp, #24] + 1901 0332 2000 movs r0, r4 + 1902 0334 FFF7FEFF bl LoRaMacComputeMic + 1903 .LVL188: + 888:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1904 .loc 1 888 0 + 1905 0338 0C9A ldr r2, [sp, #48] + 1906 033a 089B ldr r3, [sp, #32] + 1907 033c 9A42 cmp r2, r3 + 1908 033e 00D1 bne .LCB1895 + 1909 0340 96E0 b .L100 @long jump + 1910 .LCB1895: + 729:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1911 .loc 1 729 0 + 1912 0342 0023 movs r3, #0 + ARM GAS /tmp/ccrFaSdZ.s page 75 + + + 1913 0344 0493 str r3, [sp, #16] + 1914 .LVL189: + 1915 .L83: + 906:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 1916 .loc 1 906 0 + 1917 0346 0DA9 add r1, sp, #52 + 1918 0348 1123 movs r3, #17 + 1919 034a 0B70 strb r3, [r1] + 907:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( sequenceCounterDiff >= phyParam.Value ) + 1920 .loc 1 907 0 + 1921 034c 9F4B ldr r3, .L128+8 + 1922 034e 1878 ldrb r0, [r3] + 1923 0350 FFF7FEFF bl RegionGetPhyParam + 1924 .LVL190: + 908:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1925 .loc 1 908 0 + 1926 0354 079B ldr r3, [sp, #28] + 1927 .LVL191: + 1928 0356 8342 cmp r3, r0 + 1929 0358 00D3 bcc .LCB1915 + 1930 035a 8FE0 b .L114 @long jump + 1931 .LCB1915: + 916:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1932 .loc 1 916 0 + 1933 035c 049B ldr r3, [sp, #16] + 1934 035e 002B cmp r3, #0 + 1935 0360 00D1 bne .LCB1918 + 1936 0362 23E1 b .L85 @long jump + 1937 .LCB1918: + 918:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Multicast = multicast; + 1938 .loc 1 918 0 + 1939 0364 9A4A ldr r2, .L128+12 + 1940 0366 0023 movs r3, #0 + 1941 0368 5370 strb r3, [r2, #1] + 919:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.FramePending = fCtrl.Bits.FPending; + 1942 .loc 1 919 0 + 1943 036a 0598 ldr r0, [sp, #20] + 1944 .LVL192: + 1945 036c 9070 strb r0, [r2, #2] + 920:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.Buffer = NULL; + 1946 .loc 1 920 0 + 1947 036e 5946 mov r1, fp + 1948 0370 C906 lsls r1, r1, #27 + 1949 0372 C90F lsrs r1, r1, #31 + 1950 0374 5171 strb r1, [r2, #5] + 921:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = 0; + 1951 .loc 1 921 0 + 1952 0376 9360 str r3, [r2, #8] + 922:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 1953 .loc 1 922 0 + 1954 0378 1373 strb r3, [r2, #12] + 923:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1955 .loc 1 923 0 + 1956 037a 5146 mov r1, r10 + 1957 037c 5161 str r1, [r2, #20] + 925:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1958 .loc 1 925 0 + ARM GAS /tmp/ccrFaSdZ.s page 76 + + + 1959 037e 954A ldr r2, .L128+16 + 1960 0380 5370 strb r3, [r2, #1] + 927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = 0; + 1961 .loc 1 927 0 + 1962 0382 954A ldr r2, .L128+20 + 1963 0384 1360 str r3, [r2] + 928:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1964 .loc 1 928 0 + 1965 0386 954A ldr r2, .L128+24 + 1966 0388 1370 strb r3, [r2] + 931:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1967 .loc 1 931 0 + 1968 038a 0128 cmp r0, #1 + 1969 038c 7ED0 beq .L115 + 947:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 1970 .loc 1 947 0 + 1971 038e 1F23 movs r3, #31 + 1972 0390 4246 mov r2, r8 + 1973 0392 9A43 bics r2, r3 + 1974 0394 1300 movs r3, r2 + 1975 0396 A02A cmp r2, #160 + 1976 0398 00D1 bne .LCB1947 + 1977 039a 89E0 b .L116 @long jump + 1978 .LCB1947: + 965:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + 1979 .loc 1 965 0 + 1980 039c 0023 movs r3, #0 + 1981 039e 904A ldr r2, .L128+28 + 1982 03a0 1370 strb r3, [r2] + 966:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1983 .loc 1 966 0 + 1984 03a2 8B4A ldr r2, .L128+12 + 1985 03a4 1370 strb r3, [r2] + 968:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 1986 .loc 1 968 0 + 1987 03a6 8F4B ldr r3, .L128+32 + 1988 03a8 1B68 ldr r3, [r3] + 1989 03aa 5345 cmp r3, r10 + 1990 03ac 00D1 bne .LCB1956 + 1991 03ae 8EE0 b .L117 @long jump + 1992 .LCB1956: + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 1993 .loc 1 708 0 + 1994 03b0 0027 movs r7, #0 + 1995 .LVL193: + 1996 .L90: + 977:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 1997 .loc 1 977 0 + 1998 03b2 8C4B ldr r3, .L128+32 + 1999 03b4 5246 mov r2, r10 + 2000 03b6 1A60 str r2, [r3] + 2001 .LVL194: + 2002 .L88: + 984:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2003 .loc 1 984 0 + 2004 03b8 864B ldr r3, .L128+16 + 2005 03ba 1B78 ldrb r3, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 77 + + + 2006 03bc 012B cmp r3, #1 + 2007 03be 00D1 bne .LCB1973 + 2008 03c0 91E0 b .L118 @long jump + 2009 .LCB1973: + 993:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2010 .loc 1 993 0 + 2011 03c2 894B ldr r3, .L128+36 + 2012 03c4 0022 movs r2, #0 + 2013 03c6 1A70 strb r2, [r3] + 2014 .L92: + 997:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2015 .loc 1 997 0 + 2016 03c8 331F subs r3, r6, #4 + 2017 03ca 099A ldr r2, [sp, #36] + 2018 03cc 9B1A subs r3, r3, r2 + 2019 03ce 002B cmp r3, #0 + 2020 03d0 00DC bgt .LCB1983 + 2021 03d2 C4E0 b .L93 @long jump + 2022 .LCB1983: + 999:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen = ( size - 4 ) - appPayloadStartIndex; + 2023 .loc 1 999 0 + 2024 03d4 0B9B ldr r3, [sp, #44] + 2025 03d6 0921 movs r1, #9 + 2026 .LVL195: + 2027 03d8 8C46 mov ip, r1 + 2028 03da 6344 add r3, r3, ip + 2029 03dc 9846 mov r8, r3 + 2030 .LVL196: + 2031 03de A35C ldrb r3, [r4, r2] + 2032 .LVL197: +1000:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2033 .loc 1 1000 0 + 2034 03e0 4246 mov r2, r8 + 2035 03e2 B61A subs r6, r6, r2 + 2036 03e4 F6B2 uxtb r6, r6 + 2037 03e6 043E subs r6, r6, #4 + 2038 03e8 F6B2 uxtb r6, r6 + 2039 .LVL198: +1002:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2040 .loc 1 1002 0 + 2041 03ea 794A ldr r2, .L128+12 + 2042 03ec D370 strb r3, [r2, #3] +1004:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2043 .loc 1 1004 0 + 2044 03ee 002B cmp r3, #0 + 2045 03f0 00D0 beq .LCB2004 + 2046 03f2 94E0 b .L94 @long jump + 2047 .LCB2004: +1007:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2048 .loc 1 1007 0 + 2049 03f4 5B46 mov r3, fp + 2050 .LVL199: + 2051 03f6 1B07 lsls r3, r3, #28 + 2052 03f8 7DD0 beq .L119 +1022:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2053 .loc 1 1022 0 + 2054 03fa 049F ldr r7, [sp, #16] + ARM GAS /tmp/ccrFaSdZ.s page 78 + + + 2055 .LVL200: + 2056 .L95: +1084:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsIndSkip = skipIndication; + 2057 .loc 1 1084 0 + 2058 03fc 7B49 ldr r1, .L128+40 + 2059 03fe 0B78 ldrb r3, [r1] +1085:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2060 .loc 1 1085 0 + 2061 0400 0122 movs r2, #1 + 2062 0402 3A40 ands r2, r7 + 2063 0404 9200 lsls r2, r2, #2 + 2064 0406 0227 movs r7, #2 + 2065 0408 1F43 orrs r7, r3 + 2066 040a 0423 movs r3, #4 + 2067 040c 9F43 bics r7, r3 + 2068 040e 1743 orrs r7, r2 + 2069 0410 0F70 strb r7, [r1] +1095:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_PROPRIETARY: + 2070 .loc 1 1095 0 + 2071 0412 38E6 b .L72 + 2072 .LVL201: + 2073 .L113: + 856:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 2074 .loc 1 856 0 + 2075 0414 6E4B ldr r3, .L128+12 + 2076 0416 0B22 movs r2, #11 + 2077 0418 5A70 strb r2, [r3, #1] + 857:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 2078 .loc 1 857 0 + 2079 041a FFF7FEFF bl PrepareRxDoneAbort + 2080 .LVL202: + 858:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2081 .loc 1 858 0 + 2082 041e 3FE6 b .L62 + 2083 .LVL203: + 2084 .L76: + 866:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2085 .loc 1 866 0 + 2086 0420 704B ldr r3, .L128+32 + 2087 0422 1B68 ldr r3, [r3] + 2088 0424 0493 str r3, [sp, #16] + 2089 .LVL204: + 863:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nwkSKey = LoRaMacNwkSKey; + 2090 .loc 1 863 0 + 2091 0426 0023 movs r3, #0 + 2092 .LVL205: + 2093 0428 0593 str r3, [sp, #20] + 865:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = DownLinkCounter; + 2094 .loc 1 865 0 + 2095 042a 664B ldr r3, .L128 + 2096 042c 0A93 str r3, [sp, #40] + 864:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** appSKey = LoRaMacAppSKey; + 2097 .loc 1 864 0 + 2098 042e 664B ldr r3, .L128+4 + 2099 0430 0693 str r3, [sp, #24] + 723:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t *nwkSKey = LoRaMacNwkSKey; + 2100 .loc 1 723 0 + ARM GAS /tmp/ccrFaSdZ.s page 79 + + + 2101 0432 0027 movs r7, #0 + 2102 0434 4BE7 b .L81 + 2103 .LVL206: + 2104 .L82: + 2105 .LBB61: + 896:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK + 2106 .loc 1 896 0 + 2107 0436 049A ldr r2, [sp, #16] + 2108 .LVL207: + 2109 0438 9446 mov ip, r2 + 2110 043a 6344 add r3, r3, ip + 2111 .LVL208: + 2112 043c 8021 movs r1, #128 + 2113 .LVL209: + 2114 043e 4902 lsls r1, r1, #9 + 2115 0440 8A46 mov r10, r1 + 2116 0442 9A44 add r10, r10, r3 + 2117 .LVL210: + 897:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( micRx == mic ) + 2118 .loc 1 897 0 + 2119 0444 311F subs r1, r6, #4 + 2120 0446 89B2 uxth r1, r1 + 2121 0448 0CAB add r3, sp, #48 + 2122 044a 0293 str r3, [sp, #8] + 2123 .LVL211: + 2124 044c 5346 mov r3, r10 + 2125 044e 0193 str r3, [sp, #4] + 2126 0450 0123 movs r3, #1 + 2127 0452 0093 str r3, [sp] + 2128 0454 4B46 mov r3, r9 + 2129 0456 069A ldr r2, [sp, #24] + 2130 0458 2000 movs r0, r4 + 2131 045a FFF7FEFF bl LoRaMacComputeMic + 2132 .LVL212: + 898:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2133 .loc 1 898 0 + 2134 045e 0C9B ldr r3, [sp, #48] + 2135 0460 0899 ldr r1, [sp, #32] + 2136 0462 8B42 cmp r3, r1 + 2137 0464 07D0 beq .L101 + 2138 0466 049A ldr r2, [sp, #16] + 2139 0468 9246 mov r10, r2 + 2140 .LVL213: + 2141 .LBE61: + 729:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2142 .loc 1 729 0 + 2143 046a 0023 movs r3, #0 + 2144 046c 0493 str r3, [sp, #16] + 2145 .LVL214: + 2146 046e 6AE7 b .L83 + 2147 .LVL215: + 2148 .L100: + 890:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2149 .loc 1 890 0 + 2150 0470 0123 movs r3, #1 + 2151 0472 0493 str r3, [sp, #16] + 2152 .LVL216: + ARM GAS /tmp/ccrFaSdZ.s page 80 + + + 2153 0474 67E7 b .L83 + 2154 .LVL217: + 2155 .L101: + 2156 .LBB62: + 900:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** downLinkCounter = downLinkCounterTmp; + 2157 .loc 1 900 0 + 2158 0476 0123 movs r3, #1 + 2159 0478 0493 str r3, [sp, #16] + 2160 .LVL218: + 2161 047a 64E7 b .L83 + 2162 .LVL219: + 2163 .L114: + 2164 .LBE62: + 910:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 2165 .loc 1 910 0 + 2166 047c 544B ldr r3, .L128+12 + 2167 047e 0A22 movs r2, #10 + 2168 0480 5A70 strb r2, [r3, #1] + 911:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 2169 .loc 1 911 0 + 2170 0482 5246 mov r2, r10 + 2171 0484 5A61 str r2, [r3, #20] + 912:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 2172 .loc 1 912 0 + 2173 0486 FFF7FEFF bl PrepareRxDoneAbort + 2174 .LVL220: + 913:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2175 .loc 1 913 0 + 2176 048a 09E6 b .L62 + 2177 .LVL221: + 2178 .L115: + 933:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2179 .loc 1 933 0 + 2180 048c 504B ldr r3, .L128+12 + 2181 048e 0222 movs r2, #2 + 2182 0490 1A70 strb r2, [r3] + 935:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( curMulticastParams->DownLinkCounter != 0 ) ) + 2183 .loc 1 935 0 + 2184 0492 7B6A ldr r3, [r7, #36] + 2185 0494 5345 cmp r3, r10 + 2186 0496 03D0 beq .L120 + 2187 .L87: + 943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2188 .loc 1 943 0 + 2189 0498 5346 mov r3, r10 + 2190 049a 7B62 str r3, [r7, #36] + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2191 .loc 1 708 0 + 2192 049c 0027 movs r7, #0 + 2193 .LVL222: + 2194 049e 8BE7 b .L88 + 2195 .LVL223: + 2196 .L120: + 935:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( curMulticastParams->DownLinkCounter != 0 ) ) + 2197 .loc 1 935 0 discriminator 1 + 2198 04a0 002B cmp r3, #0 + 2199 04a2 F9D0 beq .L87 + ARM GAS /tmp/ccrFaSdZ.s page 81 + + + 938:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 2200 .loc 1 938 0 + 2201 04a4 4A4B ldr r3, .L128+12 + 2202 04a6 0632 adds r2, r2, #6 + 2203 04a8 5A70 strb r2, [r3, #1] + 940:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 2204 .loc 1 940 0 + 2205 04aa FFF7FEFF bl PrepareRxDoneAbort + 2206 .LVL224: + 941:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2207 .loc 1 941 0 + 2208 04ae F7E5 b .L62 + 2209 .LVL225: + 2210 .L116: + 949:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.McpsIndication = MCPS_CONFIRMED; + 2211 .loc 1 949 0 + 2212 04b0 9F3B subs r3, r3, #159 + 2213 04b2 4B4A ldr r2, .L128+28 + 2214 04b4 1370 strb r3, [r2] + 950:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2215 .loc 1 950 0 + 2216 04b6 464A ldr r2, .L128+12 + 2217 04b8 1370 strb r3, [r2] + 952:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 2218 .loc 1 952 0 + 2219 04ba 4A4B ldr r3, .L128+32 + 2220 04bc 1B68 ldr r3, [r3] + 2221 04be 5345 cmp r3, r10 + 2222 04c0 01D0 beq .L121 + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2223 .loc 1 708 0 + 2224 04c2 0027 movs r7, #0 + 2225 .LVL226: + 2226 04c4 75E7 b .L90 + 2227 .LVL227: + 2228 .L121: + 952:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 2229 .loc 1 952 0 discriminator 1 + 2230 04c6 002B cmp r3, #0 + 2231 04c8 0BD1 bne .L103 + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2232 .loc 1 708 0 + 2233 04ca 0027 movs r7, #0 + 2234 .LVL228: + 2235 04cc 71E7 b .L90 + 2236 .LVL229: + 2237 .L117: + 968:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( DownLinkCounter != 0 ) ) + 2238 .loc 1 968 0 discriminator 1 + 2239 04ce 002B cmp r3, #0 + 2240 04d0 01D1 bne .L122 + 708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2241 .loc 1 708 0 + 2242 04d2 0027 movs r7, #0 + 2243 .LVL230: + 2244 04d4 6DE7 b .L90 + 2245 .LVL231: + ARM GAS /tmp/ccrFaSdZ.s page 82 + + + 2246 .L122: + 971:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.DownLinkCounter = downLinkCounter; + 2247 .loc 1 971 0 + 2248 04d6 1300 movs r3, r2 + 2249 04d8 0822 movs r2, #8 + 2250 04da 5A70 strb r2, [r3, #1] + 973:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 2251 .loc 1 973 0 + 2252 04dc FFF7FEFF bl PrepareRxDoneAbort + 2253 .LVL232: + 974:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2254 .loc 1 974 0 + 2255 04e0 DEE5 b .L62 + 2256 .LVL233: + 2257 .L103: + 960:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2258 .loc 1 960 0 + 2259 04e2 049F ldr r7, [sp, #16] + 2260 .LVL234: + 2261 04e4 65E7 b .L90 + 2262 .LVL235: + 2263 .L118: + 986:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Reset MacCommandsBufferIndex when we have received an ACK. + 2264 .loc 1 986 0 + 2265 04e6 5B46 mov r3, fp + 2266 04e8 9B06 lsls r3, r3, #26 + 2267 04ea 00D4 bmi .LCB2283 + 2268 04ec 6CE7 b .L92 @long jump + 2269 .LCB2283: + 988:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2270 .loc 1 988 0 + 2271 04ee 3E4B ldr r3, .L128+36 + 2272 04f0 0022 movs r2, #0 + 2273 04f2 1A70 strb r2, [r3] + 2274 04f4 68E7 b .L92 + 2275 .LVL236: + 2276 .L119: +1009:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen, + 2277 .loc 1 1009 0 + 2278 04f6 2000 movs r0, r4 + 2279 04f8 4044 add r0, r0, r8 + 2280 04fa B1B2 uxth r1, r6 + 2281 04fc 3C4C ldr r4, .L128+44 + 2282 .LVL237: + 2283 04fe 0294 str r4, [sp, #8] + 2284 0500 5346 mov r3, r10 + 2285 0502 0193 str r3, [sp, #4] + 2286 0504 0123 movs r3, #1 + 2287 0506 0093 str r3, [sp] + 2288 0508 4B46 mov r3, r9 + 2289 050a 069A ldr r2, [sp, #24] + 2290 050c FFF7FEFF bl LoRaMacPayloadDecrypt + 2291 .LVL238: +1018:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2292 .loc 1 1018 0 + 2293 0510 2B00 movs r3, r5 + 2294 0512 3200 movs r2, r6 + ARM GAS /tmp/ccrFaSdZ.s page 83 + + + 2295 0514 0021 movs r1, #0 + 2296 0516 2000 movs r0, r4 + 2297 0518 FFF7FEFF bl ProcessMacCommands + 2298 .LVL239: + 2299 051c 22E0 b .L96 + 2300 .LVL240: + 2301 .L94: +1027:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2302 .loc 1 1027 0 + 2303 051e 5B46 mov r3, fp + 2304 .LVL241: + 2305 0520 1B07 lsls r3, r3, #28 + 2306 0522 15D1 bne .L123 + 2307 .LVL242: + 2308 .L97: +1033:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** frameLen, + 2309 .loc 1 1033 0 + 2310 0524 2000 movs r0, r4 + 2311 0526 4044 add r0, r0, r8 + 2312 0528 B1B2 uxth r1, r6 + 2313 052a 314B ldr r3, .L128+44 + 2314 052c 0293 str r3, [sp, #8] + 2315 052e 5346 mov r3, r10 + 2316 0530 0193 str r3, [sp, #4] + 2317 0532 0123 movs r3, #1 + 2318 0534 0093 str r3, [sp] + 2319 0536 4B46 mov r3, r9 + 2320 0538 0A9A ldr r2, [sp, #40] + 2321 053a FFF7FEFF bl LoRaMacPayloadDecrypt + 2322 .LVL243: +1041:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2323 .loc 1 1041 0 + 2324 053e 002F cmp r7, #0 + 2325 0540 10D1 bne .L96 +1043:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.BufferSize = frameLen; + 2326 .loc 1 1043 0 + 2327 0542 234B ldr r3, .L128+12 + 2328 0544 2A4A ldr r2, .L128+44 + 2329 0546 9A60 str r2, [r3, #8] +1044:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.RxData = true; + 2330 .loc 1 1044 0 + 2331 0548 1E73 strb r6, [r3, #12] +1045:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2332 .loc 1 1045 0 + 2333 054a 0122 movs r2, #1 + 2334 054c 5A73 strb r2, [r3, #13] + 2335 054e 09E0 b .L96 + 2336 .LVL244: + 2337 .L123: +1030:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2338 .loc 1 1030 0 + 2339 0550 2B00 movs r3, r5 + 2340 0552 099A ldr r2, [sp, #36] + 2341 0554 0821 movs r1, #8 + 2342 0556 2000 movs r0, r4 + 2343 0558 FFF7FEFF bl ProcessMacCommands + 2344 .LVL245: + ARM GAS /tmp/ccrFaSdZ.s page 84 + + + 2345 055c E2E7 b .L97 + 2346 .LVL246: + 2347 .L93: +1051:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2348 .loc 1 1051 0 + 2349 055e 5B46 mov r3, fp + 2350 0560 1B07 lsls r3, r3, #28 + 2351 0562 13D1 bne .L124 + 2352 .LVL247: + 2353 .L96: +1058:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2354 .loc 1 1058 0 + 2355 0564 002F cmp r7, #0 + 2356 0566 00D0 beq .LCB2397 + 2357 0568 48E7 b .L95 @long jump + 2358 .LCB2397: +1061:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2359 .loc 1 1061 0 + 2360 056a 5B46 mov r3, fp + 2361 056c 9B06 lsls r3, r3, #26 + 2362 056e 14D4 bmi .L125 +1072:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2363 .loc 1 1072 0 + 2364 0570 184B ldr r3, .L128+16 + 2365 0572 0022 movs r2, #0 + 2366 0574 1A71 strb r2, [r3, #4] +1074:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2367 .loc 1 1074 0 + 2368 0576 1F4B ldr r3, .L128+48 + 2369 0578 1A78 ldrb r2, [r3] + 2370 057a 1F4B ldr r3, .L128+52 + 2371 057c 1B78 ldrb r3, [r3] + 2372 057e 9A42 cmp r2, r3 + 2373 0580 00D8 bhi .LCB2412 + 2374 0582 3BE7 b .L95 @long jump + 2375 .LCB2412: +1078:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2376 .loc 1 1078 0 + 2377 0584 1D48 ldr r0, .L128+56 + 2378 0586 FFF7FEFF bl TimerStop + 2379 .LVL248: + 2380 058a 37E7 b .L95 + 2381 .LVL249: + 2382 .L124: +1054:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2383 .loc 1 1054 0 + 2384 058c 2B00 movs r3, r5 + 2385 058e 099A ldr r2, [sp, #36] + 2386 0590 0821 movs r1, #8 + 2387 .LVL250: + 2388 0592 2000 movs r0, r4 + 2389 0594 FFF7FEFF bl ProcessMacCommands + 2390 .LVL251: + 2391 0598 E4E7 b .L96 + 2392 .LVL252: + 2393 .L125: +1063:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsIndication.AckReceived = true; + ARM GAS /tmp/ccrFaSdZ.s page 85 + + + 2394 .loc 1 1063 0 + 2395 059a 0123 movs r3, #1 + 2396 059c 0D4A ldr r2, .L128+16 + 2397 059e 1371 strb r3, [r2, #4] +1064:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2398 .loc 1 1064 0 + 2399 05a0 0B4A ldr r2, .L128+12 + 2400 05a2 9374 strb r3, [r2, #18] +1068:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2401 .loc 1 1068 0 + 2402 05a4 1548 ldr r0, .L128+56 + 2403 05a6 FFF7FEFF bl TimerStop + 2404 .LVL253: + 2405 05aa 27E7 b .L95 + 2406 .LVL254: + 2407 .L85: +1089:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2408 .loc 1 1089 0 + 2409 05ac 084B ldr r3, .L128+12 + 2410 05ae 0C22 movs r2, #12 + 2411 05b0 5A70 strb r2, [r3, #1] +1091:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return; + 2412 .loc 1 1091 0 + 2413 05b2 FFF7FEFF bl PrepareRxDoneAbort + 2414 .LVL255: +1092:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2415 .loc 1 1092 0 + 2416 05b6 73E5 b .L62 + 2417 .LVL256: + 2418 .L63: +1109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PrepareRxDoneAbort( ); + 2419 .loc 1 1109 0 + 2420 05b8 054B ldr r3, .L128+12 + 2421 05ba 0122 movs r2, #1 + 2422 05bc 5A70 strb r2, [r3, #1] +1110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 2423 .loc 1 1110 0 + 2424 05be FFF7FEFF bl PrepareRxDoneAbort + 2425 .LVL257: +1111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2426 .loc 1 1111 0 + 2427 05c2 60E5 b .L72 + 2428 .L129: + 2429 .align 2 + 2430 .L128: + 2431 05c4 00000000 .word .LANCHOR32 + 2432 05c8 00000000 .word .LANCHOR33 + 2433 05cc 00000000 .word .LANCHOR22 + 2434 05d0 00000000 .word .LANCHOR35 + 2435 05d4 00000000 .word .LANCHOR34 + 2436 05d8 00000000 .word .LANCHOR3 + 2437 05dc 00000000 .word .LANCHOR11 + 2438 05e0 00000000 .word .LANCHOR16 + 2439 05e4 00000000 .word .LANCHOR2 + 2440 05e8 00000000 .word .LANCHOR10 + 2441 05ec 00000000 .word .LANCHOR26 + 2442 05f0 00000000 .word LoRaMacRxPayload + ARM GAS /tmp/ccrFaSdZ.s page 86 + + + 2443 05f4 00000000 .word .LANCHOR6 + 2444 05f8 00000000 .word .LANCHOR5 + 2445 05fc 00000000 .word .LANCHOR23 + 2446 .cfi_endproc + 2447 .LFE87: + 2449 .section .text.OnRxWindow2TimerEvent,"ax",%progbits + 2450 .align 1 + 2451 .syntax unified + 2452 .code 16 + 2453 .thumb_func + 2454 .fpu softvfp + 2456 OnRxWindow2TimerEvent: + 2457 .LFB94: +1466:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer2 ); + 2458 .loc 1 1466 0 + 2459 .cfi_startproc + 2460 @ args = 0, pretend = 0, frame = 0 + 2461 @ frame_needed = 0, uses_anonymous_args = 0 + 2462 0000 10B5 push {r4, lr} + 2463 .LCFI11: + 2464 .cfi_def_cfa_offset 8 + 2465 .cfi_offset 4, -8 + 2466 .cfi_offset 14, -4 +1467:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2467 .loc 1 1467 0 + 2468 0002 1C48 ldr r0, .L136 + 2469 0004 FFF7FEFF bl TimerStop + 2470 .LVL258: +1469:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Frequency = LoRaMacParams.Rx2Channel.Frequency; + 2471 .loc 1 1469 0 + 2472 0008 1B4B ldr r3, .L136+4 + 2473 000a 1C4A ldr r2, .L136+8 + 2474 000c 1278 ldrb r2, [r2] + 2475 000e 1A70 strb r2, [r3] +1470:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 2476 .loc 1 1470 0 + 2477 0010 1B4A ldr r2, .L136+12 + 2478 0012 516A ldr r1, [r2, #36] + 2479 0014 5960 str r1, [r3, #4] +1471:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RepeaterSupport = RepeaterSupport; + 2480 .loc 1 1471 0 + 2481 0016 2D21 movs r1, #45 + 2482 0018 525C ldrb r2, [r2, r1] + 2483 001a 1A74 strb r2, [r3, #16] +1472:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Window = 1; + 2484 .loc 1 1472 0 + 2485 001c 194A ldr r2, .L136+16 + 2486 001e 1278 ldrb r2, [r2] + 2487 0020 5A74 strb r2, [r3, #17] +1473:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2488 .loc 1 1473 0 + 2489 0022 0122 movs r2, #1 + 2490 0024 DA74 strb r2, [r3, #19] +1475:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2491 .loc 1 1475 0 + 2492 0026 184B ldr r3, .L136+20 + 2493 0028 1B78 ldrb r3, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 87 + + + 2494 002a 022B cmp r3, #2 + 2495 002c 19D0 beq .L131 +1477:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2496 .loc 1 1477 0 + 2497 002e 124B ldr r3, .L136+4 + 2498 0030 0022 movs r2, #0 + 2499 0032 9A74 strb r2, [r3, #18] + 2500 .L132: +1484:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2501 .loc 1 1484 0 + 2502 0034 154A ldr r2, .L136+24 + 2503 0036 164B ldr r3, .L136+28 + 2504 0038 1878 ldrb r0, [r3] + 2505 003a 0432 adds r2, r2, #4 + 2506 003c 0E49 ldr r1, .L136+4 + 2507 003e FFF7FEFF bl RegionRxConfig + 2508 .LVL259: + 2509 0042 0028 cmp r0, #0 + 2510 0044 0CD0 beq .L130 +1486:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxSlot = RxWindow2Config.Window; + 2511 .loc 1 1486 0 + 2512 0046 0C4B ldr r3, .L136+4 + 2513 0048 9B7C ldrb r3, [r3, #18] + 2514 004a 0D4A ldr r2, .L136+12 + 2515 004c D068 ldr r0, [r2, #12] + 2516 .LVL260: + 2517 .LBB63: + 2518 .LBB64: +1508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2519 .loc 1 1508 0 + 2520 004e 002B cmp r3, #0 + 2521 0050 0BD1 bne .L134 +1510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2522 .loc 1 1510 0 + 2523 0052 104B ldr r3, .L136+32 + 2524 .LVL261: + 2525 0054 DB6B ldr r3, [r3, #60] + 2526 0056 9847 blx r3 + 2527 .LVL262: + 2528 .L135: + 2529 .LBE64: + 2530 .LBE63: +1487:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2531 .loc 1 1487 0 + 2532 0058 074B ldr r3, .L136+4 + 2533 005a DA7C ldrb r2, [r3, #19] + 2534 005c 0E4B ldr r3, .L136+36 + 2535 005e 1A70 strb r2, [r3] + 2536 .L130: +1489:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2537 .loc 1 1489 0 + 2538 @ sp needed + 2539 0060 10BD pop {r4, pc} + 2540 .L131: +1481:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2541 .loc 1 1481 0 + 2542 0062 054B ldr r3, .L136+4 + ARM GAS /tmp/ccrFaSdZ.s page 88 + + + 2543 0064 0122 movs r2, #1 + 2544 0066 9A74 strb r2, [r3, #18] + 2545 0068 E4E7 b .L132 + 2546 .LVL263: + 2547 .L134: + 2548 .LBB66: + 2549 .LBB65: +1514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2550 .loc 1 1514 0 + 2551 006a 0A4B ldr r3, .L136+32 + 2552 .LVL264: + 2553 006c DB6B ldr r3, [r3, #60] + 2554 006e 0020 movs r0, #0 + 2555 .LVL265: + 2556 0070 9847 blx r3 + 2557 .LVL266: + 2558 0072 F1E7 b .L135 + 2559 .L137: + 2560 .align 2 + 2561 .L136: + 2562 0074 00000000 .word .LANCHOR37 + 2563 0078 00000000 .word .LANCHOR42 + 2564 007c 00000000 .word .LANCHOR19 + 2565 0080 00000000 .word .LANCHOR14 + 2566 0084 00000000 .word .LANCHOR21 + 2567 0088 00000000 .word .LANCHOR25 + 2568 008c 00000000 .word .LANCHOR35 + 2569 0090 00000000 .word .LANCHOR22 + 2570 0094 00000000 .word Radio + 2571 0098 00000000 .word .LANCHOR36 + 2572 .LBE65: + 2573 .LBE66: + 2574 .cfi_endproc + 2575 .LFE94: + 2577 .section .text.OnRadioRxTimeout,"ax",%progbits + 2578 .align 1 + 2579 .syntax unified + 2580 .code 16 + 2581 .thumb_func + 2582 .fpu softvfp + 2584 OnRadioRxTimeout: + 2585 .LFB90: +1172:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + 2586 .loc 1 1172 0 + 2587 .cfi_startproc + 2588 @ args = 0, pretend = 0, frame = 0 + 2589 @ frame_needed = 0, uses_anonymous_args = 0 + 2590 0000 10B5 push {r4, lr} + 2591 .LCFI12: + 2592 .cfi_def_cfa_offset 8 + 2593 .cfi_offset 4, -8 + 2594 .cfi_offset 14, -4 +1173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2595 .loc 1 1173 0 + 2596 0002 1D4B ldr r3, .L145 + 2597 0004 1B78 ldrb r3, [r3] + 2598 0006 022B cmp r3, #2 + ARM GAS /tmp/ccrFaSdZ.s page 89 + + + 2599 0008 1ED0 beq .L139 +1175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2600 .loc 1 1175 0 + 2601 000a 1C4B ldr r3, .L145+4 + 2602 000c 5B6B ldr r3, [r3, #52] + 2603 000e 9847 blx r3 + 2604 .LVL267: + 2605 .L140: +1182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2606 .loc 1 1182 0 + 2607 0010 1B4B ldr r3, .L145+8 + 2608 0012 1B78 ldrb r3, [r3] + 2609 0014 002B cmp r3, #0 + 2610 0016 1AD1 bne .L141 +1184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2611 .loc 1 1184 0 + 2612 0018 1A4B ldr r3, .L145+12 + 2613 001a 1B78 ldrb r3, [r3] + 2614 001c 002B cmp r3, #0 + 2615 001e 02D0 beq .L142 +1186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2616 .loc 1 1186 0 + 2617 0020 194B ldr r3, .L145+16 + 2618 0022 0322 movs r2, #3 + 2619 0024 5A70 strb r2, [r3, #1] + 2620 .L142: +1188:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2621 .loc 1 1188 0 + 2622 0026 194B ldr r3, .L145+20 + 2623 0028 0322 movs r2, #3 + 2624 002a 5A70 strb r2, [r3, #1] +1190:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2625 .loc 1 1190 0 + 2626 002c 184B ldr r3, .L145+24 + 2627 002e 1868 ldr r0, [r3] + 2628 0030 FFF7FEFF bl TimerGetElapsedTime + 2629 .LVL268: + 2630 0034 174B ldr r3, .L145+28 + 2631 0036 1B68 ldr r3, [r3] + 2632 0038 9842 cmp r0, r3 + 2633 003a 1BD3 bcc .L138 +1192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2634 .loc 1 1192 0 + 2635 003c 164A ldr r2, .L145+32 + 2636 003e 1378 ldrb r3, [r2] + 2637 0040 1021 movs r1, #16 + 2638 0042 0B43 orrs r3, r1 + 2639 0044 1370 strb r3, [r2] + 2640 0046 15E0 b .L138 + 2641 .L139: +1179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2642 .loc 1 1179 0 + 2643 0048 FFF7FEFF bl OnRxWindow2TimerEvent + 2644 .LVL269: + 2645 004c E0E7 b .L140 + 2646 .L141: +1197:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 90 + + + 2647 .loc 1 1197 0 + 2648 004e 0D4B ldr r3, .L145+12 + 2649 0050 1B78 ldrb r3, [r3] + 2650 0052 002B cmp r3, #0 + 2651 0054 02D0 beq .L144 +1199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2652 .loc 1 1199 0 + 2653 0056 0C4B ldr r3, .L145+16 + 2654 0058 0422 movs r2, #4 + 2655 005a 5A70 strb r2, [r3, #1] + 2656 .L144: +1201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2657 .loc 1 1201 0 + 2658 005c 0B4B ldr r3, .L145+20 + 2659 005e 0422 movs r2, #4 + 2660 0060 5A70 strb r2, [r3, #1] +1203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2661 .loc 1 1203 0 + 2662 0062 054B ldr r3, .L145 + 2663 0064 1B78 ldrb r3, [r3] + 2664 0066 022B cmp r3, #2 + 2665 0068 04D0 beq .L138 +1205:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2666 .loc 1 1205 0 + 2667 006a 0B4A ldr r2, .L145+32 + 2668 006c 1378 ldrb r3, [r2] + 2669 006e 1021 movs r1, #16 + 2670 0070 0B43 orrs r3, r1 + 2671 0072 1370 strb r3, [r2] + 2672 .L138: +1208:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2673 .loc 1 1208 0 + 2674 @ sp needed + 2675 0074 10BD pop {r4, pc} + 2676 .L146: + 2677 0076 C046 .align 2 + 2678 .L145: + 2679 0078 00000000 .word .LANCHOR25 + 2680 007c 00000000 .word Radio + 2681 0080 00000000 .word .LANCHOR36 + 2682 0084 00000000 .word .LANCHOR15 + 2683 0088 00000000 .word .LANCHOR34 + 2684 008c 00000000 .word .LANCHOR28 + 2685 0090 00000000 .word .LANCHOR43 + 2686 0094 00000000 .word .LANCHOR44 + 2687 0098 00000000 .word .LANCHOR26 + 2688 .cfi_endproc + 2689 .LFE90: + 2691 .section .text.OnRadioTxTimeout,"ax",%progbits + 2692 .align 1 + 2693 .syntax unified + 2694 .code 16 + 2695 .thumb_func + 2696 .fpu softvfp + 2698 OnRadioTxTimeout: + 2699 .LFB88: +1121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + ARM GAS /tmp/ccrFaSdZ.s page 91 + + + 2700 .loc 1 1121 0 + 2701 .cfi_startproc + 2702 @ args = 0, pretend = 0, frame = 0 + 2703 @ frame_needed = 0, uses_anonymous_args = 0 + 2704 0000 10B5 push {r4, lr} + 2705 .LCFI13: + 2706 .cfi_def_cfa_offset 8 + 2707 .cfi_offset 4, -8 + 2708 .cfi_offset 14, -4 +1122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2709 .loc 1 1122 0 + 2710 0002 0A4B ldr r3, .L150 + 2711 0004 1B78 ldrb r3, [r3] + 2712 0006 022B cmp r3, #2 + 2713 0008 0DD0 beq .L148 +1124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2714 .loc 1 1124 0 + 2715 000a 094B ldr r3, .L150+4 + 2716 000c 5B6B ldr r3, [r3, #52] + 2717 000e 9847 blx r3 + 2718 .LVL270: + 2719 .L149: +1131:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT; + 2720 .loc 1 1131 0 + 2721 0010 0223 movs r3, #2 + 2722 0012 084A ldr r2, .L150+8 + 2723 0014 5370 strb r3, [r2, #1] +1132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; + 2724 .loc 1 1132 0 + 2725 0016 084A ldr r2, .L150+12 + 2726 0018 5370 strb r3, [r2, #1] +1133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2727 .loc 1 1133 0 + 2728 001a 084A ldr r2, .L150+16 + 2729 001c 1378 ldrb r3, [r2] + 2730 001e 1021 movs r1, #16 + 2731 0020 0B43 orrs r3, r1 + 2732 0022 1370 strb r3, [r2] +1134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2733 .loc 1 1134 0 + 2734 @ sp needed + 2735 0024 10BD pop {r4, pc} + 2736 .L148: +1128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2737 .loc 1 1128 0 + 2738 0026 FFF7FEFF bl OnRxWindow2TimerEvent + 2739 .LVL271: + 2740 002a F1E7 b .L149 + 2741 .L151: + 2742 .align 2 + 2743 .L150: + 2744 002c 00000000 .word .LANCHOR25 + 2745 0030 00000000 .word Radio + 2746 0034 00000000 .word .LANCHOR34 + 2747 0038 00000000 .word .LANCHOR28 + 2748 003c 00000000 .word .LANCHOR26 + 2749 .cfi_endproc + ARM GAS /tmp/ccrFaSdZ.s page 92 + + + 2750 .LFE88: + 2752 .section .text.OnRadioRxError,"ax",%progbits + 2753 .align 1 + 2754 .syntax unified + 2755 .code 16 + 2756 .thumb_func + 2757 .fpu softvfp + 2759 OnRadioRxError: + 2760 .LFB89: +1137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + 2761 .loc 1 1137 0 + 2762 .cfi_startproc + 2763 @ args = 0, pretend = 0, frame = 0 + 2764 @ frame_needed = 0, uses_anonymous_args = 0 + 2765 0000 10B5 push {r4, lr} + 2766 .LCFI14: + 2767 .cfi_def_cfa_offset 8 + 2768 .cfi_offset 4, -8 + 2769 .cfi_offset 14, -4 +1138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2770 .loc 1 1138 0 + 2771 0002 1B4B ldr r3, .L159 + 2772 0004 1B78 ldrb r3, [r3] + 2773 0006 022B cmp r3, #2 + 2774 0008 1ED0 beq .L153 +1140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2775 .loc 1 1140 0 + 2776 000a 1A4B ldr r3, .L159+4 + 2777 000c 5B6B ldr r3, [r3, #52] + 2778 000e 9847 blx r3 + 2779 .LVL272: + 2780 .L154: +1147:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2781 .loc 1 1147 0 + 2782 0010 194B ldr r3, .L159+8 + 2783 0012 1B78 ldrb r3, [r3] + 2784 0014 002B cmp r3, #0 + 2785 0016 1AD1 bne .L155 +1149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2786 .loc 1 1149 0 + 2787 0018 184B ldr r3, .L159+12 + 2788 001a 1B78 ldrb r3, [r3] + 2789 001c 002B cmp r3, #0 + 2790 001e 02D0 beq .L156 +1151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2791 .loc 1 1151 0 + 2792 0020 174B ldr r3, .L159+16 + 2793 0022 0522 movs r2, #5 + 2794 0024 5A70 strb r2, [r3, #1] + 2795 .L156: +1153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2796 .loc 1 1153 0 + 2797 0026 174B ldr r3, .L159+20 + 2798 0028 0522 movs r2, #5 + 2799 002a 5A70 strb r2, [r3, #1] +1155:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2800 .loc 1 1155 0 + ARM GAS /tmp/ccrFaSdZ.s page 93 + + + 2801 002c 164B ldr r3, .L159+24 + 2802 002e 1868 ldr r0, [r3] + 2803 0030 FFF7FEFF bl TimerGetElapsedTime + 2804 .LVL273: + 2805 0034 154B ldr r3, .L159+28 + 2806 0036 1B68 ldr r3, [r3] + 2807 0038 9842 cmp r0, r3 + 2808 003a 17D3 bcc .L152 +1157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2809 .loc 1 1157 0 + 2810 003c 144A ldr r2, .L159+32 + 2811 003e 1378 ldrb r3, [r2] + 2812 0040 1021 movs r1, #16 + 2813 0042 0B43 orrs r3, r1 + 2814 0044 1370 strb r3, [r2] + 2815 0046 11E0 b .L152 + 2816 .L153: +1144:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2817 .loc 1 1144 0 + 2818 0048 FFF7FEFF bl OnRxWindow2TimerEvent + 2819 .LVL274: + 2820 004c E0E7 b .L154 + 2821 .L155: +1162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2822 .loc 1 1162 0 + 2823 004e 0B4B ldr r3, .L159+12 + 2824 0050 1B78 ldrb r3, [r3] + 2825 0052 002B cmp r3, #0 + 2826 0054 02D0 beq .L158 +1164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2827 .loc 1 1164 0 + 2828 0056 0A4B ldr r3, .L159+16 + 2829 0058 0622 movs r2, #6 + 2830 005a 5A70 strb r2, [r3, #1] + 2831 .L158: +1166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MacDone = 1; + 2832 .loc 1 1166 0 + 2833 005c 094B ldr r3, .L159+20 + 2834 005e 0622 movs r2, #6 + 2835 0060 5A70 strb r2, [r3, #1] +1167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2836 .loc 1 1167 0 + 2837 0062 0B4A ldr r2, .L159+32 + 2838 0064 1378 ldrb r3, [r2] + 2839 0066 1021 movs r1, #16 + 2840 0068 0B43 orrs r3, r1 + 2841 006a 1370 strb r3, [r2] + 2842 .L152: +1169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2843 .loc 1 1169 0 + 2844 @ sp needed + 2845 006c 10BD pop {r4, pc} + 2846 .L160: + 2847 006e C046 .align 2 + 2848 .L159: + 2849 0070 00000000 .word .LANCHOR25 + 2850 0074 00000000 .word Radio + ARM GAS /tmp/ccrFaSdZ.s page 94 + + + 2851 0078 00000000 .word .LANCHOR36 + 2852 007c 00000000 .word .LANCHOR15 + 2853 0080 00000000 .word .LANCHOR34 + 2854 0084 00000000 .word .LANCHOR28 + 2855 0088 00000000 .word .LANCHOR43 + 2856 008c 00000000 .word .LANCHOR44 + 2857 0090 00000000 .word .LANCHOR26 + 2858 .cfi_endproc + 2859 .LFE89: + 2861 .section .text.OnRadioTxDone,"ax",%progbits + 2862 .align 1 + 2863 .syntax unified + 2864 .code 16 + 2865 .thumb_func + 2866 .fpu softvfp + 2868 OnRadioTxDone: + 2869 .LFB85: + 612:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 2870 .loc 1 612 0 + 2871 .cfi_startproc + 2872 @ args = 0, pretend = 0, frame = 16 + 2873 @ frame_needed = 0, uses_anonymous_args = 0 + 2874 0000 30B5 push {r4, r5, lr} + 2875 .LCFI15: + 2876 .cfi_def_cfa_offset 12 + 2877 .cfi_offset 4, -12 + 2878 .cfi_offset 5, -8 + 2879 .cfi_offset 14, -4 + 2880 0002 85B0 sub sp, sp, #20 + 2881 .LCFI16: + 2882 .cfi_def_cfa_offset 32 + 616:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2883 .loc 1 616 0 + 2884 0004 FFF7FEFF bl TimerGetCurrentTime + 2885 .LVL275: + 2886 0008 0400 movs r4, r0 + 2887 .LVL276: + 618:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2888 .loc 1 618 0 + 2889 000a 3F4B ldr r3, .L174 + 2890 000c 1B78 ldrb r3, [r3] + 2891 000e 022B cmp r3, #2 + 2892 0010 25D0 beq .L162 + 620:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2893 .loc 1 620 0 + 2894 0012 3E4B ldr r3, .L174+4 + 2895 0014 5B6B ldr r3, [r3, #52] + 2896 0016 9847 blx r3 + 2897 .LVL277: + 2898 .L163: + 628:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2899 .loc 1 628 0 + 2900 0018 3D4B ldr r3, .L174+8 + 2901 001a 1B78 ldrb r3, [r3] + 2902 001c 002B cmp r3, #0 + 2903 001e 21D1 bne .L172 + 647:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT; + ARM GAS /tmp/ccrFaSdZ.s page 95 + + + 2904 .loc 1 647 0 + 2905 0020 3C4B ldr r3, .L174+12 + 2906 0022 0022 movs r2, #0 + 2907 0024 5A70 strb r2, [r3, #1] + 648:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 2908 .loc 1 648 0 + 2909 0026 3C4B ldr r3, .L174+16 + 2910 0028 0432 adds r2, r2, #4 + 2911 002a 5A70 strb r2, [r3, #1] + 650:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2912 .loc 1 650 0 + 2913 002c 3B4B ldr r3, .L174+20 + 2914 002e 1B78 ldrb r3, [r3] + 2915 0030 002B cmp r3, #0 + 2916 0032 03D1 bne .L168 + 652:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2917 .loc 1 652 0 + 2918 0034 394A ldr r2, .L174+20 + 2919 0036 0121 movs r1, #1 + 2920 0038 0B43 orrs r3, r1 + 2921 003a 1370 strb r3, [r2] + 2922 .L168: + 654:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2923 .loc 1 654 0 + 2924 003c 374A ldr r2, .L174+20 + 2925 003e 1378 ldrb r3, [r2] + 2926 0040 1021 movs r1, #16 + 2927 0042 0B43 orrs r3, r1 + 2928 0044 1370 strb r3, [r2] + 2929 .L167: + 658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2930 .loc 1 658 0 + 2931 0046 354B ldr r3, .L174+20 + 2932 0048 1B78 ldrb r3, [r3] + 2933 004a 1B07 lsls r3, r3, #28 + 2934 004c 3BD5 bpl .L169 + 658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2935 .loc 1 658 0 is_stmt 0 discriminator 1 + 2936 004e 324B ldr r3, .L174+16 + 2937 0050 1B78 ldrb r3, [r3] + 2938 0052 002B cmp r3, #0 + 2939 0054 37D1 bne .L169 + 660:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2940 .loc 1 660 0 is_stmt 1 + 2941 0056 324B ldr r3, .L174+24 + 2942 0058 0122 movs r2, #1 + 2943 005a 1A70 strb r2, [r3] + 2944 005c 36E0 b .L170 + 2945 .LVL278: + 2946 .L162: + 624:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2947 .loc 1 624 0 + 2948 005e FFF7FEFF bl OnRxWindow2TimerEvent + 2949 .LVL279: + 2950 0062 D9E7 b .L163 + 2951 .L172: + 630:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &RxWindowTimer1 ); + ARM GAS /tmp/ccrFaSdZ.s page 96 + + + 2952 .loc 1 630 0 + 2953 0064 2F4B ldr r3, .L174+28 + 2954 0066 1968 ldr r1, [r3] + 2955 0068 2F4D ldr r5, .L174+32 + 2956 006a 2800 movs r0, r5 + 2957 006c FFF7FEFF bl TimerSetValue + 2958 .LVL280: + 631:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( LoRaMacDeviceClass != CLASS_C ) + 2959 .loc 1 631 0 + 2960 0070 2800 movs r0, r5 + 2961 0072 FFF7FEFF bl TimerStart + 2962 .LVL281: + 632:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2963 .loc 1 632 0 + 2964 0076 244B ldr r3, .L174 + 2965 0078 1B78 ldrb r3, [r3] + 2966 007a 022B cmp r3, #2 + 2967 007c 19D1 bne .L173 + 2968 .L165: + 637:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2969 .loc 1 637 0 + 2970 007e 224B ldr r3, .L174 + 2971 0080 1B78 ldrb r3, [r3] + 2972 0082 022B cmp r3, #2 + 2973 0084 03D0 beq .L166 + 637:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 2974 .loc 1 637 0 is_stmt 0 discriminator 1 + 2975 0086 294B ldr r3, .L174+36 + 2976 0088 1B78 ldrb r3, [r3] + 2977 008a 002B cmp r3, #0 + 2978 008c DBD0 beq .L167 + 2979 .L166: + 639:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 2980 .loc 1 639 0 is_stmt 1 + 2981 008e 03A9 add r1, sp, #12 + 2982 0090 1223 movs r3, #18 + 2983 0092 0B70 strb r3, [r1] + 640:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &AckTimeoutTimer, RxWindow2Delay + phyParam.Value ); + 2984 .loc 1 640 0 + 2985 0094 264B ldr r3, .L174+40 + 2986 0096 1878 ldrb r0, [r3] + 2987 0098 FFF7FEFF bl RegionGetPhyParam + 2988 .LVL282: + 641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &AckTimeoutTimer ); + 2989 .loc 1 641 0 + 2990 009c 254B ldr r3, .L174+44 + 2991 009e 1968 ldr r1, [r3] + 2992 .LVL283: + 2993 00a0 4118 adds r1, r0, r1 + 2994 00a2 254D ldr r5, .L174+48 + 2995 00a4 2800 movs r0, r5 + 2996 .LVL284: + 2997 00a6 FFF7FEFF bl TimerSetValue + 2998 .LVL285: + 642:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 2999 .loc 1 642 0 + 3000 00aa 2800 movs r0, r5 + ARM GAS /tmp/ccrFaSdZ.s page 97 + + + 3001 00ac FFF7FEFF bl TimerStart + 3002 .LVL286: + 3003 00b0 C9E7 b .L167 + 3004 .L173: + 634:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &RxWindowTimer2 ); + 3005 .loc 1 634 0 + 3006 00b2 204B ldr r3, .L174+44 + 3007 00b4 1968 ldr r1, [r3] + 3008 00b6 214D ldr r5, .L174+52 + 3009 00b8 2800 movs r0, r5 + 3010 00ba FFF7FEFF bl TimerSetValue + 3011 .LVL287: + 635:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3012 .loc 1 635 0 + 3013 00be 2800 movs r0, r5 + 3014 00c0 FFF7FEFF bl TimerStart + 3015 .LVL288: + 3016 00c4 DBE7 b .L165 + 3017 .L169: + 664:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3018 .loc 1 664 0 + 3019 00c6 164B ldr r3, .L174+24 + 3020 00c8 0022 movs r2, #0 + 3021 00ca 1A70 strb r2, [r3] + 3022 .L170: + 668:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update last tx done time for the current channel + 3023 .loc 1 668 0 + 3024 00cc 1C4B ldr r3, .L174+56 + 3025 00ce 1B78 ldrb r3, [r3] + 3026 00d0 1C4A ldr r2, .L174+60 + 3027 00d2 1370 strb r3, [r2] + 670:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txDone.Joined = IsLoRaMacNetworkJoined; + 3028 .loc 1 670 0 + 3029 00d4 01A9 add r1, sp, #4 + 3030 00d6 0B70 strb r3, [r1] + 671:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txDone.LastTxDoneTime = curTime; + 3031 .loc 1 671 0 + 3032 00d8 1B4B ldr r3, .L174+64 + 3033 00da 1B78 ldrb r3, [r3] + 3034 00dc 4B70 strb r3, [r1, #1] + 672:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionSetBandTxDone( LoRaMacRegion, &txDone ); + 3035 .loc 1 672 0 + 3036 00de 4C60 str r4, [r1, #4] + 673:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update Aggregated last tx done time + 3037 .loc 1 673 0 + 3038 00e0 134B ldr r3, .L174+40 + 3039 00e2 1878 ldrb r0, [r3] + 3040 00e4 FFF7FEFF bl RegionSetBandTxDone + 3041 .LVL289: + 675:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3042 .loc 1 675 0 + 3043 00e8 184B ldr r3, .L174+68 + 3044 00ea 1C60 str r4, [r3] + 677:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3045 .loc 1 677 0 + 3046 00ec 0F4B ldr r3, .L174+36 + 3047 00ee 1B78 ldrb r3, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 98 + + + 3048 00f0 002B cmp r3, #0 + 3049 00f2 06D1 bne .L161 + 679:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter++; + 3050 .loc 1 679 0 + 3051 00f4 074B ldr r3, .L174+12 + 3052 00f6 0022 movs r2, #0 + 3053 00f8 5A70 strb r2, [r3, #1] + 680:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3054 .loc 1 680 0 + 3055 00fa 154A ldr r2, .L174+72 + 3056 00fc 1378 ldrb r3, [r2] + 3057 00fe 0133 adds r3, r3, #1 + 3058 0100 1370 strb r3, [r2] + 3059 .L161: + 682:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3060 .loc 1 682 0 + 3061 0102 05B0 add sp, sp, #20 + 3062 @ sp needed + 3063 .LVL290: + 3064 0104 30BD pop {r4, r5, pc} + 3065 .L175: + 3066 0106 C046 .align 2 + 3067 .L174: + 3068 0108 00000000 .word .LANCHOR25 + 3069 010c 00000000 .word Radio + 3070 0110 00000000 .word .LANCHOR12 + 3071 0114 00000000 .word .LANCHOR34 + 3072 0118 00000000 .word .LANCHOR28 + 3073 011c 00000000 .word .LANCHOR26 + 3074 0120 00000000 .word .LANCHOR47 + 3075 0124 00000000 .word .LANCHOR45 + 3076 0128 00000000 .word .LANCHOR46 + 3077 012c 00000000 .word .LANCHOR15 + 3078 0130 00000000 .word .LANCHOR22 + 3079 0134 00000000 .word .LANCHOR44 + 3080 0138 00000000 .word .LANCHOR23 + 3081 013c 00000000 .word .LANCHOR37 + 3082 0140 00000000 .word .LANCHOR19 + 3083 0144 00000000 .word .LANCHOR20 + 3084 0148 00000000 .word .LANCHOR0 + 3085 014c 00000000 .word .LANCHOR43 + 3086 0150 00000000 .word .LANCHOR4 + 3087 .cfi_endproc + 3088 .LFE85: + 3090 .section .text.OnRxWindow1TimerEvent,"ax",%progbits + 3091 .align 1 + 3092 .syntax unified + 3093 .code 16 + 3094 .thumb_func + 3095 .fpu softvfp + 3097 OnRxWindow1TimerEvent: + 3098 .LFB93: +1445:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStop( &RxWindowTimer1 ); + 3099 .loc 1 1445 0 + 3100 .cfi_startproc + 3101 @ args = 0, pretend = 0, frame = 0 + 3102 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccrFaSdZ.s page 99 + + + 3103 0000 10B5 push {r4, lr} + 3104 .LCFI17: + 3105 .cfi_def_cfa_offset 8 + 3106 .cfi_offset 4, -8 + 3107 .cfi_offset 14, -4 +1446:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxSlot = 0; + 3108 .loc 1 1446 0 + 3109 0002 1948 ldr r0, .L181 + 3110 0004 FFF7FEFF bl TimerStop + 3111 .LVL291: +1447:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3112 .loc 1 1447 0 + 3113 0008 0022 movs r2, #0 + 3114 000a 184B ldr r3, .L181+4 + 3115 000c 1A70 strb r2, [r3] +1449:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.DrOffset = LoRaMacParams.Rx1DrOffset; + 3116 .loc 1 1449 0 + 3117 000e 184B ldr r3, .L181+8 + 3118 0010 1849 ldr r1, .L181+12 + 3119 0012 0978 ldrb r1, [r1] + 3120 0014 1970 strb r1, [r3] +1450:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 3121 .loc 1 1450 0 + 3122 0016 1849 ldr r1, .L181+16 + 3123 0018 2120 movs r0, #33 + 3124 001a 0856 ldrsb r0, [r1, r0] + 3125 001c D870 strb r0, [r3, #3] +1451:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.RepeaterSupport = RepeaterSupport; + 3126 .loc 1 1451 0 + 3127 001e 2D20 movs r0, #45 + 3128 0020 095C ldrb r1, [r1, r0] + 3129 0022 1974 strb r1, [r3, #16] +1452:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.RxContinuous = false; + 3130 .loc 1 1452 0 + 3131 0024 1549 ldr r1, .L181+20 + 3132 0026 0978 ldrb r1, [r1] + 3133 0028 5974 strb r1, [r3, #17] +1453:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow1Config.Window = RxSlot; + 3134 .loc 1 1453 0 + 3135 002a 9A74 strb r2, [r3, #18] +1454:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3136 .loc 1 1454 0 + 3137 002c DA74 strb r2, [r3, #19] +1456:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3138 .loc 1 1456 0 + 3139 002e 144B ldr r3, .L181+24 + 3140 0030 1B78 ldrb r3, [r3] + 3141 0032 022B cmp r3, #2 + 3142 0034 02D1 bne .L177 +1458:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3143 .loc 1 1458 0 + 3144 0036 134B ldr r3, .L181+28 + 3145 0038 9B6B ldr r3, [r3, #56] + 3146 003a 9847 blx r3 + 3147 .LVL292: + 3148 .L177: +1461:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindowSetup( RxWindow1Config.RxContinuous, LoRaMacParams.MaxRxWindow ); + ARM GAS /tmp/ccrFaSdZ.s page 100 + + + 3149 .loc 1 1461 0 + 3150 003c 124A ldr r2, .L181+32 + 3151 003e 0C4C ldr r4, .L181+8 + 3152 0040 124B ldr r3, .L181+36 + 3153 0042 1878 ldrb r0, [r3] + 3154 0044 0432 adds r2, r2, #4 + 3155 0046 2100 movs r1, r4 + 3156 0048 FFF7FEFF bl RegionRxConfig + 3157 .LVL293: +1462:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3158 .loc 1 1462 0 + 3159 004c A37C ldrb r3, [r4, #18] + 3160 004e 0A4A ldr r2, .L181+16 + 3161 0050 D068 ldr r0, [r2, #12] + 3162 .LVL294: + 3163 .LBB67: + 3164 .LBB68: +1508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3165 .loc 1 1508 0 + 3166 0052 002B cmp r3, #0 + 3167 0054 04D0 beq .L180 +1514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3168 .loc 1 1514 0 + 3169 0056 0B4B ldr r3, .L181+28 + 3170 .LVL295: + 3171 0058 DB6B ldr r3, [r3, #60] + 3172 005a 0020 movs r0, #0 + 3173 .LVL296: + 3174 005c 9847 blx r3 + 3175 .LVL297: + 3176 .L176: + 3177 .LBE68: + 3178 .LBE67: +1463:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3179 .loc 1 1463 0 + 3180 @ sp needed + 3181 005e 10BD pop {r4, pc} + 3182 .LVL298: + 3183 .L180: + 3184 .LBB70: + 3185 .LBB69: +1510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3186 .loc 1 1510 0 + 3187 0060 084B ldr r3, .L181+28 + 3188 .LVL299: + 3189 0062 DB6B ldr r3, [r3, #60] + 3190 0064 9847 blx r3 + 3191 .LVL300: + 3192 0066 FAE7 b .L176 + 3193 .L182: + 3194 .align 2 + 3195 .L181: + 3196 0068 00000000 .word .LANCHOR46 + 3197 006c 00000000 .word .LANCHOR36 + 3198 0070 00000000 .word .LANCHOR48 + 3199 0074 00000000 .word .LANCHOR19 + 3200 0078 00000000 .word .LANCHOR14 + ARM GAS /tmp/ccrFaSdZ.s page 101 + + + 3201 007c 00000000 .word .LANCHOR21 + 3202 0080 00000000 .word .LANCHOR25 + 3203 0084 00000000 .word Radio + 3204 0088 00000000 .word .LANCHOR35 + 3205 008c 00000000 .word .LANCHOR22 + 3206 .LBE69: + 3207 .LBE70: + 3208 .cfi_endproc + 3209 .LFE93: + 3211 .section .text.PrepareFrame,"ax",%progbits + 3212 .align 1 + 3213 .global PrepareFrame + 3214 .syntax unified + 3215 .code 16 + 3216 .thumb_func + 3217 .fpu softvfp + 3219 PrepareFrame: + 3220 .LFB105: +2053:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2054:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t PrepareFrame( LoRaMacHeader_t *macHdr, LoRaMacFrameCtrl_t *fCtrl, uint8_t fPort, vo +2055:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3221 .loc 1 2055 0 + 3222 .cfi_startproc + 3223 @ args = 4, pretend = 0, frame = 24 + 3224 @ frame_needed = 0, uses_anonymous_args = 0 + 3225 .LVL301: + 3226 0000 F0B5 push {r4, r5, r6, r7, lr} + 3227 .LCFI18: + 3228 .cfi_def_cfa_offset 20 + 3229 .cfi_offset 4, -20 + 3230 .cfi_offset 5, -16 + 3231 .cfi_offset 6, -12 + 3232 .cfi_offset 7, -8 + 3233 .cfi_offset 14, -4 + 3234 0002 CE46 mov lr, r9 + 3235 0004 00B5 push {lr} + 3236 .LCFI19: + 3237 .cfi_def_cfa_offset 24 + 3238 .cfi_offset 9, -24 + 3239 0006 8AB0 sub sp, sp, #40 + 3240 .LCFI20: + 3241 .cfi_def_cfa_offset 64 + 3242 0008 0E00 movs r6, r1 + 3243 000a 0592 str r2, [sp, #20] + 3244 000c 1D00 movs r5, r3 + 3245 000e 10AB add r3, sp, #64 + 3246 .LVL302: + 3247 0010 1A88 ldrh r2, [r3] + 3248 .LVL303: +2056:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrNextParams_t adrNext; +2057:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t i; +2058:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t pktHeaderLen = 0; +2059:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint32_t mic = 0; + 3249 .loc 1 2059 0 + 3250 0012 0023 movs r3, #0 + 3251 .LVL304: + 3252 0014 0693 str r3, [sp, #24] + ARM GAS /tmp/ccrFaSdZ.s page 102 + + + 3253 .LVL305: +2060:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** const void* payload = fBuffer; +2061:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t framePort = fPort; +2062:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2063:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen = 0; + 3254 .loc 1 2063 0 + 3255 0016 C949 ldr r1, .L220 + 3256 .LVL306: + 3257 0018 0B80 strh r3, [r1] +2064:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2065:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 3258 .loc 1 2065 0 + 3259 001a 0021 movs r1, #0 + 3260 001c C84B ldr r3, .L220+4 + 3261 001e 1970 strb r1, [r3] +2066:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2067:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( fBuffer == NULL ) + 3262 .loc 1 2067 0 + 3263 0020 002D cmp r5, #0 + 3264 0022 17D0 beq .L216 + 3265 .L184: + 3266 .LVL307: +2068:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2069:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = 0; +2070:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2071:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2072:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacTxPayloadLen = fBufferSize; + 3267 .loc 1 2072 0 + 3268 0024 D2B2 uxtb r2, r2 + 3269 .LVL308: + 3270 0026 C74B ldr r3, .L220+8 + 3271 0028 1A70 strb r2, [r3] + 3272 .LVL309: +2073:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2074:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = macHdr->Value; + 3273 .loc 1 2074 0 + 3274 002a 0178 ldrb r1, [r0] + 3275 002c C64B ldr r3, .L220+12 + 3276 002e 1970 strb r1, [r3] +2075:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2076:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( macHdr->Bits.MType ) + 3277 .loc 1 2076 0 + 3278 0030 0378 ldrb r3, [r0] + 3279 0032 5B09 lsrs r3, r3, #5 + 3280 0034 022B cmp r3, #2 + 3281 0036 57D0 beq .L186 + 3282 0038 0ED9 bls .L217 + 3283 003a 042B cmp r3, #4 + 3284 003c 51D0 beq .L189 + 3285 003e 072B cmp r3, #7 + 3286 0040 00D0 beq .LCB3268 + 3287 0042 75E1 b .L209 @long jump + 3288 .LCB3268: +2077:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2078:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_JOIN_REQ: +2079:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen = pktHeaderLen; +2080:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 103 + + +2081:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpyr( LoRaMacBuffer + LoRaMacBufferPktLen, LoRaMacAppEui, 8 ); +2082:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen += 8; +2083:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpyr( LoRaMacBuffer + LoRaMacBufferPktLen, LoRaMacDevEui, 8 ); +2084:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen += 8; +2085:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2086:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevNonce = Radio.Random( ); +2087:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2088:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = LoRaMacDevNonce & 0xFF; +2089:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( LoRaMacDevNonce >> 8 ) & 0xFF; +2090:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2091:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacJoinComputeMic( LoRaMacBuffer, LoRaMacBufferPktLen & 0xFF, LoRaMacAppKey, &mic ) +2092:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2093:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = mic & 0xFF; +2094:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 8 ) & 0xFF; +2095:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 16 ) & 0xFF; +2096:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 24 ) & 0xFF; +2097:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2098:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2099:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_DATA_CONFIRMED_UP: +2100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = true; +2101:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** //Intentional fallthrough +2102:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_DATA_UNCONFIRMED_UP: +2103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsLoRaMacNetworkJoined == false ) +2104:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_NO_NETWORK_JOINED; // No network has been joined yet +2106:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2107:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2108:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Adr next request +2109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.UpdateChanMask = true; +2110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrEnabled = fCtrl->Bits.Adr; +2111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrAckCounter = AdrAckCounter; +2112:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.Datarate = LoRaMacParams.ChannelsDatarate; +2113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.TxPower = LoRaMacParams.ChannelsTxPower; +2114:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +2115:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl->Bits.AdrAckReq = RegionAdrNext( LoRaMacRegion, &adrNext, +2117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &LoRaMacParams.ChannelsDatarate, &LoRaMacParams. +2118:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2119:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( SrvAckRequested == true ) +2120:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** SrvAckRequested = false; +2122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl->Bits.Ack = 1; +2123:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2125:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr ) & 0xFF; +2126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 8 ) & 0xFF; +2127:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 16 ) & 0xFF; +2128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 24 ) & 0xFF; +2129:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2130:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = fCtrl->Value; +2131:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = UpLinkCounter & 0xFF; +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( UpLinkCounter >> 8 ) & 0xFF; +2134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2135:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Copy the MAC commands which must be re-send into the MAC command buffer +2136:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpy1( &MacCommandsBuffer[MacCommandsBufferIndex], MacCommandsBufferToRepeat, MacComm +2137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex += MacCommandsBufferToRepeatIndex; + ARM GAS /tmp/ccrFaSdZ.s page 104 + + +2138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( payload != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) +2140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2141:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsInNextTx == true ) +2142:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2143:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferIndex <= LORA_MAC_COMMAND_MAX_FOPTS_LENGTH ) +2144:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2145:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl->Bits.FOptsLen += MacCommandsBufferIndex; +2146:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2147:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update FCtrl field with new value of OptionsLength +2148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[0x05] = fCtrl->Value; +2149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** for( i = 0; i < MacCommandsBufferIndex; i++ ) +2150:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = MacCommandsBuffer[i]; +2152:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2154:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2155:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacTxPayloadLen = MacCommandsBufferIndex; +2157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** payload = MacCommandsBuffer; +2158:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** framePort = 0; +2159:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2160:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2161:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2163:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( MacCommandsBufferIndex > 0 ) && ( MacCommandsInNextTx == true ) ) +2165:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacTxPayloadLen = MacCommandsBufferIndex; +2167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** payload = MacCommandsBuffer; +2168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** framePort = 0; +2169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2170:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsInNextTx = false; +2172:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Store MAC commands which must be re-send in case the device does not receive a downl +2173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = ParseMacCommandsToRepeat( MacCommandsBuffer, MacComman +2174:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferToRepeatIndex > 0 ) +2175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2176:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsInNextTx = true; +2177:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2178:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( payload != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) +2180:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = framePort; +2182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2183:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( framePort == 0 ) +2184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2185:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset buffer index as the mac commands are being sent on port 0 +2186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +2187:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPayloadEncrypt( (uint8_t* ) payload, LoRaMacTxPayloadLen, LoRaMacNwkSKey +2188:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2189:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2190:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPayloadEncrypt( (uint8_t* ) payload, LoRaMacTxPayloadLen, LoRaMacAppSKey +2192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2193:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2194:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen = pktHeaderLen + LoRaMacTxPayloadLen; + ARM GAS /tmp/ccrFaSdZ.s page 105 + + +2195:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2196:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacComputeMic( LoRaMacBuffer, LoRaMacBufferPktLen, LoRaMacNwkSKey, LoRaMacDevAddr, +2197:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 0] = mic & 0xFF; +2199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 1] = ( mic >> 8 ) & 0xFF; +2200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 2] = ( mic >> 16 ) & 0xFF; +2201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 3] = ( mic >> 24 ) & 0xFF; +2202:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen += LORAMAC_MFR_LEN; +2204:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2205:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2206:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_PROPRIETARY: +2207:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( fBuffer != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) + 3289 .loc 1 2207 0 + 3290 0044 002D cmp r5, #0 + 3291 0046 00D1 bne .LCB3270 + 3292 0048 76E1 b .L214 @long jump + 3293 .LCB3270: + 3294 .loc 1 2207 0 is_stmt 0 discriminator 1 + 3295 004a 002A cmp r2, #0 + 3296 004c 00D0 beq .LCB3272 + 3297 004e 63E1 b .L218 @long jump + 3298 .LCB3272: +2208:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpy1( LoRaMacBuffer + pktHeaderLen, ( uint8_t* ) fBuffer, LoRaMacTxPayloadLen ); +2210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen = pktHeaderLen + LoRaMacTxPayloadLen; +2211:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2212:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2213:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +2214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_SERVICE_UNKNOWN; +2215:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2216:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 3299 .loc 1 2217 0 is_stmt 1 + 3300 0050 0020 movs r0, #0 + 3301 .LVL310: + 3302 0052 4CE1 b .L185 + 3303 .LVL311: + 3304 .L216: +2069:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3305 .loc 1 2069 0 + 3306 0054 0022 movs r2, #0 + 3307 0056 E5E7 b .L184 + 3308 .LVL312: + 3309 .L217: +2076:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3310 .loc 1 2076 0 + 3311 0058 002B cmp r3, #0 + 3312 005a 00D0 beq .LCB3291 + 3313 005c 68E1 b .L209 @long jump + 3314 .LCB3291: +2079:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3315 .loc 1 2079 0 + 3316 005e B74D ldr r5, .L220 + 3317 .LVL313: + 3318 0060 0123 movs r3, #1 + 3319 0062 2B80 strh r3, [r5] + ARM GAS /tmp/ccrFaSdZ.s page 106 + + +2081:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen += 8; + 3320 .loc 1 2081 0 + 3321 0064 B94B ldr r3, .L220+16 + 3322 0066 1968 ldr r1, [r3] + 3323 0068 B94C ldr r4, .L220+20 + 3324 006a 0822 movs r2, #8 + 3325 006c 2000 movs r0, r4 + 3326 .LVL314: + 3327 006e FFF7FEFF bl memcpyr + 3328 .LVL315: +2082:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpyr( LoRaMacBuffer + LoRaMacBufferPktLen, LoRaMacDevEui, 8 ); + 3329 .loc 1 2082 0 + 3330 0072 2888 ldrh r0, [r5] + 3331 0074 0830 adds r0, r0, #8 + 3332 0076 80B2 uxth r0, r0 + 3333 0078 2880 strh r0, [r5] +2083:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen += 8; + 3334 .loc 1 2083 0 + 3335 007a B64B ldr r3, .L220+24 + 3336 007c 1968 ldr r1, [r3] + 3337 007e 013C subs r4, r4, #1 + 3338 0080 0019 adds r0, r0, r4 + 3339 0082 0822 movs r2, #8 + 3340 0084 FFF7FEFF bl memcpyr + 3341 .LVL316: +2084:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3342 .loc 1 2084 0 + 3343 0088 2B88 ldrh r3, [r5] + 3344 008a 0833 adds r3, r3, #8 + 3345 008c 2B80 strh r3, [r5] +2086:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3346 .loc 1 2086 0 + 3347 008e B24B ldr r3, .L220+28 + 3348 0090 DB69 ldr r3, [r3, #28] + 3349 0092 9847 blx r3 + 3350 .LVL317: + 3351 0094 80B2 uxth r0, r0 + 3352 0096 B14B ldr r3, .L220+32 + 3353 0098 1880 strh r0, [r3] +2088:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( LoRaMacDevNonce >> 8 ) & 0xFF; + 3354 .loc 1 2088 0 + 3355 009a 2A88 ldrh r2, [r5] + 3356 009c 531C adds r3, r2, #1 + 3357 009e 9BB2 uxth r3, r3 + 3358 00a0 A054 strb r0, [r4, r2] +2089:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3359 .loc 1 2089 0 + 3360 00a2 591C adds r1, r3, #1 + 3361 00a4 89B2 uxth r1, r1 + 3362 00a6 2980 strh r1, [r5] + 3363 00a8 000A lsrs r0, r0, #8 + 3364 00aa E054 strb r0, [r4, r3] +2091:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3365 .loc 1 2091 0 + 3366 00ac AC4B ldr r3, .L220+36 + 3367 00ae 1A68 ldr r2, [r3] + 3368 00b0 FF23 movs r3, #255 + ARM GAS /tmp/ccrFaSdZ.s page 107 + + + 3369 00b2 1940 ands r1, r3 + 3370 00b4 06AB add r3, sp, #24 + 3371 00b6 2000 movs r0, r4 + 3372 00b8 FFF7FEFF bl LoRaMacJoinComputeMic + 3373 .LVL318: +2093:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 8 ) & 0xFF; + 3374 .loc 1 2093 0 + 3375 00bc 069B ldr r3, [sp, #24] + 3376 00be 2988 ldrh r1, [r5] + 3377 00c0 4A1C adds r2, r1, #1 + 3378 00c2 92B2 uxth r2, r2 + 3379 00c4 6354 strb r3, [r4, r1] +2094:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 16 ) & 0xFF; + 3380 .loc 1 2094 0 + 3381 00c6 180A lsrs r0, r3, #8 + 3382 00c8 511C adds r1, r2, #1 + 3383 00ca 89B2 uxth r1, r1 + 3384 00cc A054 strb r0, [r4, r2] +2095:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 24 ) & 0xFF; + 3385 .loc 1 2095 0 + 3386 00ce 180C lsrs r0, r3, #16 + 3387 00d0 4A1C adds r2, r1, #1 + 3388 00d2 92B2 uxth r2, r2 + 3389 00d4 6054 strb r0, [r4, r1] +2096:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3390 .loc 1 2096 0 + 3391 00d6 1B0E lsrs r3, r3, #24 + 3392 00d8 511C adds r1, r2, #1 + 3393 00da 2980 strh r1, [r5] + 3394 00dc A354 strb r3, [r4, r2] + 3395 .loc 1 2217 0 + 3396 00de 0020 movs r0, #0 +2098:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case FRAME_TYPE_DATA_CONFIRMED_UP: + 3397 .loc 1 2098 0 + 3398 00e0 05E1 b .L185 + 3399 .LVL319: + 3400 .L189: +2100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** //Intentional fallthrough + 3401 .loc 1 2100 0 + 3402 00e2 974B ldr r3, .L220+4 + 3403 00e4 0122 movs r2, #1 + 3404 00e6 1A70 strb r2, [r3] + 3405 .L186: +2103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3406 .loc 1 2103 0 + 3407 00e8 9E4B ldr r3, .L220+40 + 3408 00ea 1B78 ldrb r3, [r3] + 3409 00ec 002B cmp r3, #0 + 3410 00ee 00D1 bne .LCB3377 + 3411 00f0 20E1 b .L210 @long jump + 3412 .LCB3377: +2109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrEnabled = fCtrl->Bits.Adr; + 3413 .loc 1 2109 0 + 3414 00f2 07A9 add r1, sp, #28 + 3415 00f4 0123 movs r3, #1 + 3416 00f6 0B70 strb r3, [r1] +2110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrAckCounter = AdrAckCounter; + ARM GAS /tmp/ccrFaSdZ.s page 108 + + + 3417 .loc 1 2110 0 + 3418 00f8 3378 ldrb r3, [r6] + 3419 00fa DB09 lsrs r3, r3, #7 + 3420 00fc 4B70 strb r3, [r1, #1] +2111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.Datarate = LoRaMacParams.ChannelsDatarate; + 3421 .loc 1 2111 0 + 3422 00fe 9A4F ldr r7, .L220+44 + 3423 0100 3B68 ldr r3, [r7] + 3424 0102 4B60 str r3, [r1, #4] +2112:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.TxPower = LoRaMacParams.ChannelsTxPower; + 3425 .loc 1 2112 0 + 3426 0104 994B ldr r3, .L220+48 + 3427 0106 0122 movs r2, #1 + 3428 0108 9A56 ldrsb r2, [r3, r2] + 3429 010a 0A72 strb r2, [r1, #8] +2113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 3430 .loc 1 2113 0 + 3431 010c 0022 movs r2, #0 + 3432 010e 9A56 ldrsb r2, [r3, r2] + 3433 0110 4A72 strb r2, [r1, #9] +2114:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3434 .loc 1 2114 0 + 3435 0112 2C22 movs r2, #44 + 3436 0114 9A5C ldrb r2, [r3, r2] + 3437 0116 8A72 strb r2, [r1, #10] +2116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &LoRaMacParams.ChannelsDatarate, &LoRaMacParams. + 3438 .loc 1 2116 0 + 3439 0118 5A1C adds r2, r3, #1 + 3440 011a 9548 ldr r0, .L220+52 + 3441 .LVL320: + 3442 011c 0078 ldrb r0, [r0] + 3443 011e 0097 str r7, [sp] + 3444 0120 FFF7FEFF bl RegionAdrNext + 3445 .LVL321: + 3446 0124 0123 movs r3, #1 + 3447 0126 0340 ands r3, r0 + 3448 0128 9B01 lsls r3, r3, #6 + 3449 012a 3078 ldrb r0, [r6] + 3450 012c 4022 movs r2, #64 + 3451 012e 9043 bics r0, r2 + 3452 0130 1843 orrs r0, r3 + 3453 0132 3070 strb r0, [r6] +2119:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3454 .loc 1 2119 0 + 3455 0134 8F4B ldr r3, .L220+56 + 3456 0136 1B78 ldrb r3, [r3] + 3457 0138 002B cmp r3, #0 + 3458 013a 06D0 beq .L191 +2121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl->Bits.Ack = 1; + 3459 .loc 1 2121 0 + 3460 013c 8D4B ldr r3, .L220+56 + 3461 013e 0022 movs r2, #0 + 3462 0140 1A70 strb r2, [r3] +2122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3463 .loc 1 2122 0 + 3464 0142 C3B2 uxtb r3, r0 + 3465 0144 2022 movs r2, #32 + ARM GAS /tmp/ccrFaSdZ.s page 109 + + + 3466 0146 1343 orrs r3, r2 + 3467 0148 3370 strb r3, [r6] + 3468 .L191: +2125:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 8 ) & 0xFF; + 3469 .loc 1 2125 0 + 3470 014a 8B4B ldr r3, .L220+60 + 3471 014c 1A68 ldr r2, [r3] + 3472 .LVL322: + 3473 014e 7E4B ldr r3, .L220+12 + 3474 0150 5A70 strb r2, [r3, #1] +2126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 16 ) & 0xFF; + 3475 .loc 1 2126 0 + 3476 0152 110A lsrs r1, r2, #8 + 3477 .LVL323: + 3478 0154 9970 strb r1, [r3, #2] +2127:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 24 ) & 0xFF; + 3479 .loc 1 2127 0 + 3480 0156 110C lsrs r1, r2, #16 + 3481 .LVL324: + 3482 0158 D970 strb r1, [r3, #3] +2128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3483 .loc 1 2128 0 + 3484 015a 120E lsrs r2, r2, #24 + 3485 .LVL325: + 3486 015c 1A71 strb r2, [r3, #4] + 3487 .LVL326: +2130:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3488 .loc 1 2130 0 + 3489 015e 3278 ldrb r2, [r6] + 3490 0160 5A71 strb r2, [r3, #5] +2132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[pktHeaderLen++] = ( UpLinkCounter >> 8 ) & 0xFF; + 3491 .loc 1 2132 0 + 3492 0162 864A ldr r2, .L220+64 + 3493 0164 1268 ldr r2, [r2] + 3494 .LVL327: + 3495 0166 9A71 strb r2, [r3, #6] +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3496 .loc 1 2133 0 + 3497 0168 120A lsrs r2, r2, #8 + 3498 .LVL328: + 3499 016a DA71 strb r2, [r3, #7] +2136:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex += MacCommandsBufferToRepeatIndex; + 3500 .loc 1 2136 0 + 3501 016c 844C ldr r4, .L220+68 + 3502 016e 2078 ldrb r0, [r4] + 3503 0170 844B ldr r3, .L220+72 + 3504 0172 9946 mov r9, r3 + 3505 0174 1A78 ldrb r2, [r3] + 3506 0176 844B ldr r3, .L220+76 + 3507 0178 C018 adds r0, r0, r3 + 3508 017a 8449 ldr r1, .L220+80 + 3509 017c FFF7FEFF bl memcpy1 + 3510 .LVL329: +2137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3511 .loc 1 2137 0 + 3512 0180 2778 ldrb r7, [r4] + 3513 0182 4B46 mov r3, r9 + ARM GAS /tmp/ccrFaSdZ.s page 110 + + + 3514 0184 1B78 ldrb r3, [r3] + 3515 0186 FF18 adds r7, r7, r3 + 3516 0188 FFB2 uxtb r7, r7 + 3517 018a 2770 strb r7, [r4] +2139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3518 .loc 1 2139 0 + 3519 018c 002D cmp r5, #0 + 3520 018e 2AD0 beq .L192 +2139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3521 .loc 1 2139 0 is_stmt 0 discriminator 1 + 3522 0190 6C4B ldr r3, .L220+8 + 3523 0192 1B78 ldrb r3, [r3] + 3524 0194 002B cmp r3, #0 + 3525 0196 26D0 beq .L192 +2141:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3526 .loc 1 2141 0 is_stmt 1 + 3527 0198 7D4B ldr r3, .L220+84 + 3528 019a 1B78 ldrb r3, [r3] + 3529 019c 002B cmp r3, #0 + 3530 019e 2FD0 beq .L211 +2143:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3531 .loc 1 2143 0 + 3532 01a0 0F2F cmp r7, #15 + 3533 01a2 19D8 bhi .L194 +2145:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3534 .loc 1 2145 0 + 3535 01a4 3278 ldrb r2, [r6] + 3536 01a6 1307 lsls r3, r2, #28 + 3537 01a8 1B0F lsrs r3, r3, #28 + 3538 01aa FB18 adds r3, r7, r3 + 3539 01ac 0F21 movs r1, #15 + 3540 01ae 0B40 ands r3, r1 + 3541 01b0 8A43 bics r2, r1 + 3542 01b2 1343 orrs r3, r2 + 3543 01b4 3370 strb r3, [r6] +2148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** for( i = 0; i < MacCommandsBufferIndex; i++ ) + 3544 .loc 1 2148 0 + 3545 01b6 644A ldr r2, .L220+12 + 3546 01b8 5371 strb r3, [r2, #5] + 3547 .LVL330: +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3548 .loc 1 2133 0 + 3549 01ba 0824 movs r4, #8 +2149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3550 .loc 1 2149 0 + 3551 01bc 0023 movs r3, #0 + 3552 01be 07E0 b .L195 + 3553 .LVL331: + 3554 .L196: +2151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3555 .loc 1 2151 0 discriminator 3 + 3556 01c0 621C adds r2, r4, #1 + 3557 .LVL332: + 3558 01c2 7149 ldr r1, .L220+76 + 3559 01c4 C85C ldrb r0, [r1, r3] + 3560 01c6 6049 ldr r1, .L220+12 + 3561 01c8 0855 strb r0, [r1, r4] + ARM GAS /tmp/ccrFaSdZ.s page 111 + + +2149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3562 .loc 1 2149 0 discriminator 3 + 3563 01ca 0133 adds r3, r3, #1 + 3564 .LVL333: + 3565 01cc 9BB2 uxth r3, r3 + 3566 .LVL334: +2151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3567 .loc 1 2151 0 discriminator 3 + 3568 01ce D4B2 uxtb r4, r2 + 3569 .LVL335: + 3570 .L195: +2149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3571 .loc 1 2149 0 discriminator 1 + 3572 01d0 BAB2 uxth r2, r7 + 3573 01d2 9A42 cmp r2, r3 + 3574 01d4 F4D8 bhi .L196 + 3575 01d6 16E0 b .L193 + 3576 .LVL336: + 3577 .L194: +2156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** payload = MacCommandsBuffer; + 3578 .loc 1 2156 0 + 3579 01d8 5A4B ldr r3, .L220+8 + 3580 01da 1F70 strb r7, [r3] + 3581 .LVL337: +2158:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3582 .loc 1 2158 0 + 3583 01dc 0023 movs r3, #0 + 3584 01de 0593 str r3, [sp, #20] +2157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** framePort = 0; + 3585 .loc 1 2157 0 + 3586 01e0 694D ldr r5, .L220+76 + 3587 .LVL338: +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3588 .loc 1 2133 0 + 3589 01e2 0824 movs r4, #8 + 3590 01e4 0FE0 b .L193 + 3591 .LVL339: + 3592 .L192: +2164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3593 .loc 1 2164 0 + 3594 01e6 002F cmp r7, #0 + 3595 01e8 0CD0 beq .L212 +2164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3596 .loc 1 2164 0 is_stmt 0 discriminator 1 + 3597 01ea 694B ldr r3, .L220+84 + 3598 01ec 1B78 ldrb r3, [r3] + 3599 01ee 002B cmp r3, #0 + 3600 01f0 0FD0 beq .L213 +2166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** payload = MacCommandsBuffer; + 3601 .loc 1 2166 0 is_stmt 1 + 3602 01f2 544B ldr r3, .L220+8 + 3603 01f4 1F70 strb r7, [r3] + 3604 .LVL340: +2168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3605 .loc 1 2168 0 + 3606 01f6 0023 movs r3, #0 + 3607 01f8 0593 str r3, [sp, #20] + ARM GAS /tmp/ccrFaSdZ.s page 112 + + +2167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** framePort = 0; + 3608 .loc 1 2167 0 + 3609 01fa 634D ldr r5, .L220+76 + 3610 .LVL341: +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3611 .loc 1 2133 0 + 3612 01fc 0824 movs r4, #8 + 3613 01fe 02E0 b .L193 + 3614 .LVL342: + 3615 .L211: + 3616 0200 0824 movs r4, #8 + 3617 0202 00E0 b .L193 + 3618 .L212: + 3619 0204 0824 movs r4, #8 + 3620 .LVL343: + 3621 .L193: +2171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Store MAC commands which must be re-send in case the device does not receive a downl + 3622 .loc 1 2171 0 + 3623 0206 624B ldr r3, .L220+84 + 3624 0208 0022 movs r2, #0 + 3625 020a 1A70 strb r2, [r3] + 3626 .LVL344: + 3627 .LBB73: + 3628 .LBB74: +1649:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3629 .loc 1 1649 0 + 3630 020c 0026 movs r6, #0 + 3631 .LVL345: +1656:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3632 .loc 1 1656 0 + 3633 020e 0023 movs r3, #0 + 3634 0210 0EE0 b .L197 + 3635 .LVL346: + 3636 .L213: + 3637 .LBE74: + 3638 .LBE73: +2133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3639 .loc 1 2133 0 + 3640 0212 0824 movs r4, #8 + 3641 0214 F7E7 b .L193 + 3642 .LVL347: + 3643 .L201: + 3644 .LBB76: + 3645 .LBB75: +1664:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cmdBufOut[cmdCount++] = cmdBufIn[i]; + 3646 .loc 1 1664 0 + 3647 0216 0133 adds r3, r3, #1 + 3648 .LVL348: + 3649 0218 DBB2 uxtb r3, r3 + 3650 .LVL349: + 3651 021a 721C adds r2, r6, #1 + 3652 021c D2B2 uxtb r2, r2 + 3653 .LVL350: + 3654 021e 5B49 ldr r1, .L220+80 + 3655 0220 8855 strb r0, [r1, r6] +1665:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 3656 .loc 1 1665 0 + ARM GAS /tmp/ccrFaSdZ.s page 113 + + + 3657 0222 0236 adds r6, r6, #2 + 3658 0224 F6B2 uxtb r6, r6 + 3659 .LVL351: + 3660 0226 5848 ldr r0, .L220+76 + 3661 0228 C05C ldrb r0, [r0, r3] + 3662 022a 8854 strb r0, [r1, r2] + 3663 .LVL352: + 3664 .L198: +1656:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3665 .loc 1 1656 0 + 3666 022c 0133 adds r3, r3, #1 + 3667 .LVL353: + 3668 022e DBB2 uxtb r3, r3 + 3669 .LVL354: + 3670 .L197: + 3671 0230 9F42 cmp r7, r3 + 3672 0232 14D9 bls .L219 +1658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3673 .loc 1 1658 0 + 3674 0234 544A ldr r2, .L220+76 + 3675 0236 D05C ldrb r0, [r2, r3] + 3676 0238 C21E subs r2, r0, #3 + 3677 023a D1B2 uxtb r1, r2 + 3678 023c 0729 cmp r1, #7 + 3679 023e F5D8 bhi .L198 + 3680 0240 8A00 lsls r2, r1, #2 + 3681 0242 5449 ldr r1, .L220+88 + 3682 0244 8A58 ldr r2, [r1, r2] + 3683 0246 9746 mov pc, r2 + 3684 .section .rodata.PrepareFrame,"a",%progbits + 3685 .align 2 + 3686 .L200: + 3687 0000 58020000 .word .L199 + 3688 0004 2C020000 .word .L198 + 3689 0008 16020000 .word .L201 + 3690 000c 52020000 .word .L202 + 3691 0010 58020000 .word .L199 + 3692 0014 48020000 .word .L203 + 3693 0018 2C020000 .word .L198 + 3694 001c 16020000 .word .L201 + 3695 .section .text.PrepareFrame + 3696 .L203: +1670:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 3697 .loc 1 1670 0 + 3698 0248 721C adds r2, r6, #1 + 3699 .LVL355: + 3700 024a 5049 ldr r1, .L220+80 + 3701 024c 8855 strb r0, [r1, r6] + 3702 024e D6B2 uxtb r6, r2 + 3703 0250 ECE7 b .L198 + 3704 .LVL356: + 3705 .L202: +1676:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 3706 .loc 1 1676 0 + 3707 0252 0233 adds r3, r3, #2 + 3708 .LVL357: + 3709 0254 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccrFaSdZ.s page 114 + + + 3710 .LVL358: + 3711 0256 E9E7 b .L198 + 3712 .L199: +1682:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 3713 .loc 1 1682 0 + 3714 0258 0133 adds r3, r3, #1 + 3715 .LVL359: + 3716 025a DBB2 uxtb r3, r3 + 3717 .LVL360: + 3718 025c E6E7 b .L198 + 3719 .L219: + 3720 .LVL361: + 3721 .LBE75: + 3722 .LBE76: +2173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MacCommandsBufferToRepeatIndex > 0 ) + 3723 .loc 1 2173 0 + 3724 025e 494B ldr r3, .L220+72 + 3725 0260 1E70 strb r6, [r3] +2174:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3726 .loc 1 2174 0 + 3727 0262 002E cmp r6, #0 + 3728 0264 02D0 beq .L205 +2176:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3729 .loc 1 2176 0 + 3730 0266 4A4B ldr r3, .L220+84 + 3731 0268 0122 movs r2, #1 + 3732 026a 1A70 strb r2, [r3] + 3733 .L205: +2179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3734 .loc 1 2179 0 + 3735 026c 002D cmp r5, #0 + 3736 026e 1CD0 beq .L206 +2179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3737 .loc 1 2179 0 is_stmt 0 discriminator 1 + 3738 0270 344B ldr r3, .L220+8 + 3739 0272 1978 ldrb r1, [r3] + 3740 0274 0029 cmp r1, #0 + 3741 0276 18D0 beq .L206 +2181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3742 .loc 1 2181 0 is_stmt 1 + 3743 0278 661C adds r6, r4, #1 + 3744 027a F6B2 uxtb r6, r6 + 3745 .LVL362: + 3746 027c 324B ldr r3, .L220+12 + 3747 027e 059A ldr r2, [sp, #20] + 3748 0280 1A55 strb r2, [r3, r4] +2183:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3749 .loc 1 2183 0 + 3750 0282 002A cmp r2, #0 + 3751 0284 37D1 bne .L207 +2186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPayloadEncrypt( (uint8_t* ) payload, LoRaMacTxPayloadLen, LoRaMacNwkSKey + 3752 .loc 1 2186 0 + 3753 0286 0020 movs r0, #0 + 3754 0288 3D4B ldr r3, .L220+68 + 3755 028a 1870 strb r0, [r3] +2187:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3756 .loc 1 2187 0 + ARM GAS /tmp/ccrFaSdZ.s page 115 + + + 3757 028c 3A4B ldr r3, .L220+60 + 3758 028e 1B68 ldr r3, [r3] + 3759 0290 89B2 uxth r1, r1 + 3760 0292 2D4A ldr r2, .L220+12 + 3761 0294 B218 adds r2, r6, r2 + 3762 0296 0292 str r2, [sp, #8] + 3763 0298 384A ldr r2, .L220+64 + 3764 029a 1268 ldr r2, [r2] + 3765 029c 0192 str r2, [sp, #4] + 3766 029e 0090 str r0, [sp] + 3767 02a0 3D4A ldr r2, .L220+92 + 3768 02a2 2800 movs r0, r5 + 3769 02a4 FFF7FEFF bl LoRaMacPayloadEncrypt + 3770 .LVL363: +2181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3771 .loc 1 2181 0 + 3772 02a8 3400 movs r4, r6 + 3773 .LVL364: + 3774 .L206: +2194:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3775 .loc 1 2194 0 + 3776 02aa 264B ldr r3, .L220+8 + 3777 02ac 1978 ldrb r1, [r3] + 3778 02ae 0919 adds r1, r1, r4 + 3779 02b0 224D ldr r5, .L220 + 3780 .LVL365: + 3781 02b2 2980 strh r1, [r5] +2196:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3782 .loc 1 2196 0 + 3783 02b4 304B ldr r3, .L220+60 + 3784 02b6 1B68 ldr r3, [r3] + 3785 02b8 234C ldr r4, .L220+12 + 3786 .LVL366: + 3787 02ba 06AA add r2, sp, #24 + 3788 02bc 0292 str r2, [sp, #8] + 3789 02be 2F4A ldr r2, .L220+64 + 3790 02c0 1268 ldr r2, [r2] + 3791 02c2 0192 str r2, [sp, #4] + 3792 02c4 0022 movs r2, #0 + 3793 02c6 0092 str r2, [sp] + 3794 02c8 334A ldr r2, .L220+92 + 3795 02ca 2000 movs r0, r4 + 3796 02cc FFF7FEFF bl LoRaMacComputeMic + 3797 .LVL367: +2198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 1] = ( mic >> 8 ) & 0xFF; + 3798 .loc 1 2198 0 + 3799 02d0 069A ldr r2, [sp, #24] + 3800 02d2 2B88 ldrh r3, [r5] + 3801 02d4 E254 strb r2, [r4, r3] +2199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 2] = ( mic >> 16 ) & 0xFF; + 3802 .loc 1 2199 0 + 3803 02d6 100A lsrs r0, r2, #8 + 3804 02d8 591C adds r1, r3, #1 + 3805 02da 6054 strb r0, [r4, r1] +2200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBuffer[LoRaMacBufferPktLen + 3] = ( mic >> 24 ) & 0xFF; + 3806 .loc 1 2200 0 + 3807 02dc 100C lsrs r0, r2, #16 + ARM GAS /tmp/ccrFaSdZ.s page 116 + + + 3808 02de 991C adds r1, r3, #2 + 3809 02e0 6054 strb r0, [r4, r1] +2201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3810 .loc 1 2201 0 + 3811 02e2 120E lsrs r2, r2, #24 + 3812 02e4 D91C adds r1, r3, #3 + 3813 02e6 6254 strb r2, [r4, r1] +2203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3814 .loc 1 2203 0 + 3815 02e8 0433 adds r3, r3, #4 + 3816 02ea 2B80 strh r3, [r5] + 3817 .loc 1 2217 0 + 3818 02ec 0020 movs r0, #0 + 3819 .L185: +2218:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3820 .loc 1 2218 0 + 3821 02ee 0AB0 add sp, sp, #40 + 3822 @ sp needed + 3823 02f0 04BC pop {r2} + 3824 02f2 9146 mov r9, r2 + 3825 02f4 F0BD pop {r4, r5, r6, r7, pc} + 3826 .LVL368: + 3827 .L207: +2191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3828 .loc 1 2191 0 + 3829 02f6 204B ldr r3, .L220+60 + 3830 02f8 1B68 ldr r3, [r3] + 3831 02fa 89B2 uxth r1, r1 + 3832 02fc 124A ldr r2, .L220+12 + 3833 02fe B218 adds r2, r6, r2 + 3834 0300 0292 str r2, [sp, #8] + 3835 0302 1E4A ldr r2, .L220+64 + 3836 0304 1268 ldr r2, [r2] + 3837 0306 0192 str r2, [sp, #4] + 3838 0308 0022 movs r2, #0 + 3839 030a 0092 str r2, [sp] + 3840 030c 234A ldr r2, .L220+96 + 3841 030e 2800 movs r0, r5 + 3842 0310 FFF7FEFF bl LoRaMacPayloadEncrypt + 3843 .LVL369: +2181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 3844 .loc 1 2181 0 + 3845 0314 3400 movs r4, r6 + 3846 0316 C8E7 b .L206 + 3847 .LVL370: + 3848 .L218: +2209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacBufferPktLen = pktHeaderLen + LoRaMacTxPayloadLen; + 3849 .loc 1 2209 0 + 3850 0318 92B2 uxth r2, r2 + 3851 031a 2900 movs r1, r5 + 3852 031c 0C48 ldr r0, .L220+20 + 3853 .LVL371: + 3854 031e FFF7FEFF bl memcpy1 + 3855 .LVL372: +2210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3856 .loc 1 2210 0 + 3857 0322 084B ldr r3, .L220+8 + ARM GAS /tmp/ccrFaSdZ.s page 117 + + + 3858 0324 1B78 ldrb r3, [r3] + 3859 0326 0133 adds r3, r3, #1 + 3860 0328 044A ldr r2, .L220 + 3861 032a 1380 strh r3, [r2] +2217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3862 .loc 1 2217 0 + 3863 032c 0020 movs r0, #0 + 3864 032e DEE7 b .L185 + 3865 .LVL373: + 3866 .L209: +2214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3867 .loc 1 2214 0 + 3868 0330 0220 movs r0, #2 + 3869 .LVL374: + 3870 0332 DCE7 b .L185 + 3871 .LVL375: + 3872 .L210: +2105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3873 .loc 1 2105 0 + 3874 0334 0720 movs r0, #7 + 3875 .LVL376: + 3876 0336 DAE7 b .L185 + 3877 .LVL377: + 3878 .L214: +2217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 3879 .loc 1 2217 0 + 3880 0338 0020 movs r0, #0 + 3881 .LVL378: + 3882 033a D8E7 b .L185 + 3883 .L221: + 3884 .align 2 + 3885 .L220: + 3886 033c 00000000 .word .LANCHOR49 + 3887 0340 00000000 .word .LANCHOR15 + 3888 0344 00000000 .word .LANCHOR50 + 3889 0348 00000000 .word LoRaMacBuffer + 3890 034c 00000000 .word .LANCHOR51 + 3891 0350 01000000 .word LoRaMacBuffer+1 + 3892 0354 00000000 .word .LANCHOR52 + 3893 0358 00000000 .word Radio + 3894 035c 00000000 .word .LANCHOR39 + 3895 0360 00000000 .word .LANCHOR38 + 3896 0364 00000000 .word .LANCHOR0 + 3897 0368 00000000 .word .LANCHOR3 + 3898 036c 00000000 .word .LANCHOR14 + 3899 0370 00000000 .word .LANCHOR22 + 3900 0374 00000000 .word .LANCHOR16 + 3901 0378 00000000 .word .LANCHOR41 + 3902 037c 00000000 .word .LANCHOR1 + 3903 0380 00000000 .word .LANCHOR10 + 3904 0384 00000000 .word .LANCHOR11 + 3905 0388 00000000 .word MacCommandsBuffer + 3906 038c 00000000 .word MacCommandsBufferToRepeat + 3907 0390 00000000 .word .LANCHOR17 + 3908 0394 00000000 .word .L200 + 3909 0398 00000000 .word .LANCHOR33 + 3910 039c 00000000 .word .LANCHOR32 + ARM GAS /tmp/ccrFaSdZ.s page 118 + + + 3911 .cfi_endproc + 3912 .LFE105: + 3914 .section .text.SendFrameOnChannel,"ax",%progbits + 3915 .align 1 + 3916 .global SendFrameOnChannel + 3917 .syntax unified + 3918 .code 16 + 3919 .thumb_func + 3920 .fpu softvfp + 3922 SendFrameOnChannel: + 3923 .LFB106: +2219:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SendFrameOnChannel( uint8_t channel ) +2221:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 3924 .loc 1 2221 0 + 3925 .cfi_startproc + 3926 @ args = 0, pretend = 0, frame = 24 + 3927 @ frame_needed = 0, uses_anonymous_args = 0 + 3928 .LVL379: + 3929 0000 70B5 push {r4, r5, r6, lr} + 3930 .LCFI21: + 3931 .cfi_def_cfa_offset 16 + 3932 .cfi_offset 4, -16 + 3933 .cfi_offset 5, -12 + 3934 .cfi_offset 6, -8 + 3935 .cfi_offset 14, -4 + 3936 0002 86B0 sub sp, sp, #24 + 3937 .LCFI22: + 3938 .cfi_def_cfa_offset 40 +2222:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TxConfigParams_t txConfig; +2223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t txPower = 0; + 3939 .loc 1 2223 0 + 3940 0004 6B46 mov r3, sp + 3941 0006 DD1D adds r5, r3, #7 + 3942 0008 0023 movs r3, #0 + 3943 000a 2B70 strb r3, [r5] +2224:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2225:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.Channel = channel; + 3944 .loc 1 2225 0 + 3945 000c 02A9 add r1, sp, #8 + 3946 000e 0870 strb r0, [r1] +2226:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.Datarate = LoRaMacParams.ChannelsDatarate; + 3947 .loc 1 2226 0 + 3948 0010 1F4C ldr r4, .L224 + 3949 0012 0123 movs r3, #1 + 3950 0014 E356 ldrsb r3, [r4, r3] + 3951 0016 4B70 strb r3, [r1, #1] +2227:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.TxPower = LoRaMacParams.ChannelsTxPower; + 3952 .loc 1 2227 0 + 3953 0018 0023 movs r3, #0 + 3954 001a E356 ldrsb r3, [r4, r3] + 3955 001c 8B70 strb r3, [r1, #2] +2228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.MaxEirp = LoRaMacParams.MaxEirp; + 3956 .loc 1 2228 0 + 3957 001e 236B ldr r3, [r4, #48] + 3958 0020 4B60 str r3, [r1, #4] +2229:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.AntennaGain = LoRaMacParams.AntennaGain; + ARM GAS /tmp/ccrFaSdZ.s page 119 + + + 3959 .loc 1 2229 0 + 3960 0022 636B ldr r3, [r4, #52] + 3961 0024 8B60 str r3, [r1, #8] +2230:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txConfig.PktLen = LoRaMacBufferPktLen; + 3962 .loc 1 2230 0 + 3963 0026 1B4B ldr r3, .L224+4 + 3964 0028 1B88 ldrh r3, [r3] + 3965 002a 8B81 strh r3, [r1, #12] +2231:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2232:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DBG_PRINTF( "\n\r*** seqTx= %d *****\n\r", UpLinkCounter ); +2233:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2234:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionTxConfig( LoRaMacRegion, &txConfig, &txPower, &TxTimeOnAir ); + 3966 .loc 1 2234 0 + 3967 002c 1A4E ldr r6, .L224+8 + 3968 002e 1B4B ldr r3, .L224+12 + 3969 0030 1878 ldrb r0, [r3] + 3970 .LVL380: + 3971 0032 3300 movs r3, r6 + 3972 0034 2A00 movs r2, r5 + 3973 0036 FFF7FEFF bl RegionTxConfig + 3974 .LVL381: +2235:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2236:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + 3975 .loc 1 2236 0 + 3976 003a 194A ldr r2, .L224+16 + 3977 003c 0121 movs r1, #1 + 3978 003e 5170 strb r1, [r2, #1] +2237:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + 3979 .loc 1 2237 0 + 3980 0040 184B ldr r3, .L224+20 + 3981 0042 5970 strb r1, [r3, #1] +2238:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Datarate = LoRaMacParams.ChannelsDatarate; + 3982 .loc 1 2238 0 + 3983 0044 6178 ldrb r1, [r4, #1] + 3984 0046 9970 strb r1, [r3, #2] +2239:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.TxPower = txPower; + 3985 .loc 1 2239 0 + 3986 0048 2978 ldrb r1, [r5] + 3987 004a D970 strb r1, [r3, #3] +2240:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Store the time on air +2242:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.TxTimeOnAir = TxTimeOnAir; + 3988 .loc 1 2242 0 + 3989 004c 3168 ldr r1, [r6] + 3990 004e 9960 str r1, [r3, #8] +2243:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.TxTimeOnAir = TxTimeOnAir; + 3991 .loc 1 2243 0 + 3992 0050 5160 str r1, [r2, #4] +2244:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Starts the MAC layer status check timer +2246:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + 3993 .loc 1 2246 0 + 3994 0052 FA21 movs r1, #250 + 3995 0054 144C ldr r4, .L224+24 + 3996 0056 8900 lsls r1, r1, #2 + 3997 0058 2000 movs r0, r4 + 3998 005a FFF7FEFF bl TimerSetValue + ARM GAS /tmp/ccrFaSdZ.s page 120 + + + 3999 .LVL382: +2247:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 4000 .loc 1 2247 0 + 4001 005e 2000 movs r0, r4 + 4002 0060 FFF7FEFF bl TimerStart + 4003 .LVL383: +2248:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2249:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsLoRaMacNetworkJoined == false ) + 4004 .loc 1 2249 0 + 4005 0064 114B ldr r3, .L224+28 + 4006 0066 1B78 ldrb r3, [r3] + 4007 0068 002B cmp r3, #0 + 4008 006a 03D1 bne .L223 +2250:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** JoinRequestTrials++; + 4009 .loc 1 2251 0 + 4010 006c 104A ldr r2, .L224+32 + 4011 006e 1378 ldrb r3, [r2] + 4012 0070 0133 adds r3, r3, #1 + 4013 0072 1370 strb r3, [r2] + 4014 .L223: +2252:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2254:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Send now +2255:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Send( LoRaMacBuffer, LoRaMacBufferPktLen ); + 4015 .loc 1 2255 0 + 4016 0074 0F4B ldr r3, .L224+36 + 4017 0076 1B6B ldr r3, [r3, #48] + 4018 0078 064A ldr r2, .L224+4 + 4019 007a 1178 ldrb r1, [r2] + 4020 007c 0E48 ldr r0, .L224+40 + 4021 007e 9847 blx r3 + 4022 .LVL384: +2256:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_TX_RUNNING; + 4023 .loc 1 2257 0 + 4024 0080 0E4A ldr r2, .L224+44 + 4025 0082 0123 movs r3, #1 + 4026 0084 1168 ldr r1, [r2] + 4027 0086 0B43 orrs r3, r1 + 4028 0088 1360 str r3, [r2] +2258:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2259:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; +2260:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4029 .loc 1 2260 0 + 4030 008a 0020 movs r0, #0 + 4031 008c 06B0 add sp, sp, #24 + 4032 @ sp needed + 4033 008e 70BD pop {r4, r5, r6, pc} + 4034 .L225: + 4035 .align 2 + 4036 .L224: + 4037 0090 00000000 .word .LANCHOR14 + 4038 0094 00000000 .word .LANCHOR49 + 4039 0098 00000000 .word .LANCHOR53 + 4040 009c 00000000 .word .LANCHOR22 + 4041 00a0 00000000 .word .LANCHOR28 + ARM GAS /tmp/ccrFaSdZ.s page 121 + + + 4042 00a4 00000000 .word .LANCHOR34 + 4043 00a8 00000000 .word .LANCHOR27 + 4044 00ac 00000000 .word .LANCHOR0 + 4045 00b0 00000000 .word .LANCHOR54 + 4046 00b4 00000000 .word Radio + 4047 00b8 00000000 .word LoRaMacBuffer + 4048 00bc 00000000 .word .LANCHOR24 + 4049 .cfi_endproc + 4050 .LFE106: + 4052 .section .text.ScheduleTx,"ax",%progbits + 4053 .align 1 + 4054 .syntax unified + 4055 .code 16 + 4056 .thumb_func + 4057 .fpu softvfp + 4059 ScheduleTx: + 4060 .LFB102: +1910:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerTime_t dutyCycleTimeOff = 0; + 4061 .loc 1 1910 0 + 4062 .cfi_startproc + 4063 @ args = 0, pretend = 0, frame = 32 + 4064 @ frame_needed = 0, uses_anonymous_args = 0 + 4065 0000 F0B5 push {r4, r5, r6, r7, lr} + 4066 .LCFI23: + 4067 .cfi_def_cfa_offset 20 + 4068 .cfi_offset 4, -20 + 4069 .cfi_offset 5, -16 + 4070 .cfi_offset 6, -12 + 4071 .cfi_offset 7, -8 + 4072 .cfi_offset 14, -4 + 4073 0002 8BB0 sub sp, sp, #44 + 4074 .LCFI24: + 4075 .cfi_def_cfa_offset 64 +1911:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NextChanParams_t nextChan; + 4076 .loc 1 1911 0 + 4077 0004 0023 movs r3, #0 + 4078 0006 0993 str r3, [sp, #36] +1915:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4079 .loc 1 1915 0 + 4080 0008 584B ldr r3, .L237 + 4081 000a 1B78 ldrb r3, [r3] + 4082 000c FF2B cmp r3, #255 + 4083 000e 00D1 bne .LCB4064 + 4084 0010 A8E0 b .L234 @long jump + 4085 .LCB4064: +1919:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4086 .loc 1 1919 0 + 4087 0012 002B cmp r3, #0 + 4088 0014 02D1 bne .L228 +1921:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4089 .loc 1 1921 0 + 4090 0016 564B ldr r3, .L237+4 + 4091 0018 0022 movs r2, #0 + 4092 001a 1A60 str r2, [r3] + 4093 .L228: +1925:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4094 .loc 1 1925 0 + ARM GAS /tmp/ccrFaSdZ.s page 122 + + + 4095 001c 554B ldr r3, .L237+8 + 4096 001e 1B78 ldrb r3, [r3] + 4097 .LVL385: + 4098 .LBB79: + 4099 .LBB80: +1991:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.DutyCycleEnabled = DutyCycleOn; + 4100 .loc 1 1991 0 + 4101 0020 03AC add r4, sp, #12 + 4102 0022 554D ldr r5, .L237+12 + 4103 0024 2A78 ldrb r2, [r5] + 4104 0026 2270 strb r2, [r4] +1992:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.Channel = channel; + 4105 .loc 1 1992 0 + 4106 0028 544E ldr r6, .L237+16 + 4107 002a 3278 ldrb r2, [r6] + 4108 002c A270 strb r2, [r4, #2] +1993:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.ElapsedTime = TimerGetElapsedTime( LoRaMacInitializationTime ); + 4109 .loc 1 1993 0 + 4110 002e E370 strb r3, [r4, #3] +1994:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.TxTimeOnAir = TxTimeOnAir; + 4111 .loc 1 1994 0 + 4112 0030 534B ldr r3, .L237+20 + 4113 .LVL386: + 4114 0032 1868 ldr r0, [r3] + 4115 0034 FFF7FEFF bl TimerGetElapsedTime + 4116 .LVL387: + 4117 0038 6060 str r0, [r4, #4] +1995:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** calcBackOff.LastTxIsJoinRequest = LastTxIsJoinRequest; + 4118 .loc 1 1995 0 + 4119 003a 524F ldr r7, .L237+24 + 4120 003c 3B68 ldr r3, [r7] + 4121 003e A360 str r3, [r4, #8] +1996:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4122 .loc 1 1996 0 + 4123 0040 514B ldr r3, .L237+28 + 4124 0042 1B78 ldrb r3, [r3] + 4125 0044 6370 strb r3, [r4, #1] +1999:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4126 .loc 1 1999 0 + 4127 0046 514B ldr r3, .L237+32 + 4128 0048 1878 ldrb r0, [r3] + 4129 004a 2100 movs r1, r4 + 4130 004c FFF7FEFF bl RegionCalcBackOff + 4131 .LVL388: +2002:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4132 .loc 1 2002 0 + 4133 0050 4F4B ldr r3, .L237+36 + 4134 0052 1A88 ldrh r2, [r3] + 4135 0054 013A subs r2, r2, #1 + 4136 0056 3B68 ldr r3, [r7] + 4137 0058 5343 muls r3, r2 + 4138 005a 454A ldr r2, .L237+4 + 4139 005c 1168 ldr r1, [r2] + 4140 005e 8C46 mov ip, r1 + 4141 0060 6344 add r3, r3, ip + 4142 0062 1360 str r3, [r2] + 4143 .LBE80: + ARM GAS /tmp/ccrFaSdZ.s page 123 + + + 4144 .LBE79: +1927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.Datarate = LoRaMacParams.ChannelsDatarate; + 4145 .loc 1 1927 0 + 4146 0064 06AA add r2, sp, #24 + 4147 0066 0693 str r3, [sp, #24] +1928:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.DutyCycleEnabled = DutyCycleOn; + 4148 .loc 1 1928 0 + 4149 0068 4A4B ldr r3, .L237+40 + 4150 006a 5B78 ldrb r3, [r3, #1] + 4151 006c 5BB2 sxtb r3, r3 + 4152 006e 1372 strb r3, [r2, #8] +1929:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.Joined = IsLoRaMacNetworkJoined; + 4153 .loc 1 1929 0 + 4154 0070 3378 ldrb r3, [r6] + 4155 0072 9372 strb r3, [r2, #10] +1930:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** nextChan.LastAggrTx = AggregatedLastTxDoneTime; + 4156 .loc 1 1930 0 + 4157 0074 2B78 ldrb r3, [r5] + 4158 0076 5372 strb r3, [r2, #9] +1931:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4159 .loc 1 1931 0 + 4160 0078 474B ldr r3, .L237+44 + 4161 007a 1B68 ldr r3, [r3] + 4162 007c 0793 str r3, [sp, #28] +1934:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4163 .loc 1 1934 0 + 4164 007e 06E0 b .L229 + 4165 .L230: +1937:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Update datarate in the function parameters + 4166 .loc 1 1937 0 + 4167 0080 464B ldr r3, .L237+48 + 4168 0082 5B78 ldrb r3, [r3, #1] + 4169 0084 5BB2 sxtb r3, r3 + 4170 0086 434A ldr r2, .L237+40 + 4171 0088 5370 strb r3, [r2, #1] +1939:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4172 .loc 1 1939 0 + 4173 008a 06AA add r2, sp, #24 + 4174 008c 1372 strb r3, [r2, #8] + 4175 .L229: +1934:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4176 .loc 1 1934 0 + 4177 008e 3F4B ldr r3, .L237+32 + 4178 0090 1878 ldrb r0, [r3] + 4179 0092 374B ldr r3, .L237+4 + 4180 0094 0093 str r3, [sp] + 4181 0096 09AB add r3, sp, #36 + 4182 0098 414A ldr r2, .L237+52 + 4183 009a 06A9 add r1, sp, #24 + 4184 009c FFF7FEFF bl RegionNextChannel + 4185 .LVL389: + 4186 00a0 0028 cmp r0, #0 + 4187 00a2 EDD0 beq .L230 +1943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionApplyDrOffset( LoRaMacRegion, LoRaMacParams.DownlinkDwel + 4188 .loc 1 1943 0 + 4189 00a4 394E ldr r6, .L237+32 + 4190 00a6 3578 ldrb r5, [r6] + ARM GAS /tmp/ccrFaSdZ.s page 124 + + +1944:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols, + 4191 .loc 1 1944 0 + 4192 00a8 3A4C ldr r4, .L237+40 + 4193 00aa 2123 movs r3, #33 + 4194 00ac E356 ldrsb r3, [r4, r3] + 4195 00ae 0122 movs r2, #1 + 4196 00b0 A256 ldrsb r2, [r4, r2] + 4197 00b2 2D21 movs r1, #45 + 4198 00b4 615C ldrb r1, [r4, r1] + 4199 00b6 2800 movs r0, r5 + 4200 00b8 FFF7FEFF bl RegionApplyDrOffset + 4201 .LVL390: +1943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionApplyDrOffset( LoRaMacRegion, LoRaMacParams.DownlinkDwel + 4202 .loc 1 1943 0 + 4203 00bc 6368 ldr r3, [r4, #4] + 4204 00be 227A ldrb r2, [r4, #8] + 4205 00c0 41B2 sxtb r1, r0 + 4206 00c2 3848 ldr r0, .L237+56 + 4207 00c4 0090 str r0, [sp] + 4208 00c6 2800 movs r0, r5 + 4209 00c8 FFF7FEFF bl RegionComputeRxWindowParameters + 4210 .LVL391: +1949:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate, + 4211 .loc 1 1949 0 + 4212 00cc 6368 ldr r3, [r4, #4] + 4213 00ce 227A ldrb r2, [r4, #8] + 4214 00d0 2821 movs r1, #40 + 4215 00d2 6156 ldrsb r1, [r4, r1] + 4216 00d4 3078 ldrb r0, [r6] + 4217 00d6 344C ldr r4, .L237+60 + 4218 00d8 0094 str r4, [sp] + 4219 00da FFF7FEFF bl RegionComputeRxWindowParameters + 4220 .LVL392: +1955:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4221 .loc 1 1955 0 + 4222 00de 264B ldr r3, .L237+12 + 4223 00e0 1B78 ldrb r3, [r3] + 4224 00e2 002B cmp r3, #0 + 4225 00e4 1FD1 bne .L231 +1957:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Delay = LoRaMacParams.JoinAcceptDelay2 + RxWindow2Config.WindowOffset; + 4226 .loc 1 1957 0 + 4227 00e6 2B4A ldr r2, .L237+40 + 4228 00e8 2E4B ldr r3, .L237+56 + 4229 00ea DB68 ldr r3, [r3, #12] + 4230 00ec 9169 ldr r1, [r2, #24] + 4231 00ee 8C46 mov ip, r1 + 4232 00f0 6344 add r3, r3, ip + 4233 00f2 2E49 ldr r1, .L237+64 + 4234 00f4 0B60 str r3, [r1] +1958:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4235 .loc 1 1958 0 + 4236 00f6 D369 ldr r3, [r2, #28] + 4237 00f8 2B4A ldr r2, .L237+60 + 4238 00fa D268 ldr r2, [r2, #12] + 4239 00fc 9B18 adds r3, r3, r2 + 4240 00fe 2C4A ldr r2, .L237+68 + 4241 0100 1360 str r3, [r2] + ARM GAS /tmp/ccrFaSdZ.s page 125 + + + 4242 .L232: +1971:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4243 .loc 1 1971 0 + 4244 0102 0999 ldr r1, [sp, #36] + 4245 0104 0029 cmp r1, #0 + 4246 0106 28D0 beq .L236 +1979:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &TxDelayedTimer, dutyCycleTimeOff ); + 4247 .loc 1 1979 0 + 4248 0108 2A4A ldr r2, .L237+72 + 4249 010a 1023 movs r3, #16 + 4250 010c 1068 ldr r0, [r2] + 4251 010e 0343 orrs r3, r0 + 4252 0110 1360 str r3, [r2] +1980:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &TxDelayedTimer ); + 4253 .loc 1 1980 0 + 4254 0112 294C ldr r4, .L237+76 + 4255 0114 2000 movs r0, r4 + 4256 0116 FFF7FEFF bl TimerSetValue + 4257 .LVL393: +1981:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4258 .loc 1 1981 0 + 4259 011a 2000 movs r0, r4 + 4260 011c FFF7FEFF bl TimerStart + 4261 .LVL394: +1983:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4262 .loc 1 1983 0 + 4263 0120 0020 movs r0, #0 + 4264 .L227: +1985:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4265 .loc 1 1985 0 + 4266 0122 0BB0 add sp, sp, #44 + 4267 @ sp needed + 4268 0124 F0BD pop {r4, r5, r6, r7, pc} + 4269 .L231: +1962:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4270 .loc 1 1962 0 + 4271 0126 254B ldr r3, .L237+80 + 4272 0128 1A78 ldrb r2, [r3] + 4273 012a 1A4B ldr r3, .L237+40 + 4274 012c 0121 movs r1, #1 + 4275 012e 5956 ldrsb r1, [r3, r1] + 4276 0130 234B ldr r3, .L237+84 + 4277 0132 1878 ldrb r0, [r3] + 4278 0134 FFF7FEFF bl ValidatePayloadLength + 4279 .LVL395: + 4280 0138 0028 cmp r0, #0 + 4281 013a 15D0 beq .L235 +1966:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Delay = LoRaMacParams.ReceiveDelay2 + RxWindow2Config.WindowOffset; + 4282 .loc 1 1966 0 + 4283 013c 154A ldr r2, .L237+40 + 4284 013e 194B ldr r3, .L237+56 + 4285 0140 DB68 ldr r3, [r3, #12] + 4286 0142 1169 ldr r1, [r2, #16] + 4287 0144 8C46 mov ip, r1 + 4288 0146 6344 add r3, r3, ip + 4289 0148 1849 ldr r1, .L237+64 + 4290 014a 0B60 str r3, [r1] + ARM GAS /tmp/ccrFaSdZ.s page 126 + + +1967:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4291 .loc 1 1967 0 + 4292 014c 5369 ldr r3, [r2, #20] + 4293 014e 164A ldr r2, .L237+60 + 4294 0150 D268 ldr r2, [r2, #12] + 4295 0152 9B18 adds r3, r3, r2 + 4296 0154 164A ldr r2, .L237+68 + 4297 0156 1360 str r3, [r2] + 4298 0158 D3E7 b .L232 + 4299 .L236: +1974:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4300 .loc 1 1974 0 + 4301 015a 114B ldr r3, .L237+52 + 4302 015c 1878 ldrb r0, [r3] + 4303 015e FFF7FEFF bl SendFrameOnChannel + 4304 .LVL396: + 4305 0162 DEE7 b .L227 + 4306 .L234: +1917:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4307 .loc 1 1917 0 + 4308 0164 0920 movs r0, #9 + 4309 0166 DCE7 b .L227 + 4310 .L235: +1964:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4311 .loc 1 1964 0 + 4312 0168 0820 movs r0, #8 + 4313 016a DAE7 b .L227 + 4314 .L238: + 4315 .align 2 + 4316 .L237: + 4317 016c 00000000 .word .LANCHOR8 + 4318 0170 00000000 .word .LANCHOR55 + 4319 0174 00000000 .word .LANCHOR20 + 4320 0178 00000000 .word .LANCHOR0 + 4321 017c 00000000 .word .LANCHOR56 + 4322 0180 00000000 .word .LANCHOR57 + 4323 0184 00000000 .word .LANCHOR53 + 4324 0188 00000000 .word .LANCHOR47 + 4325 018c 00000000 .word .LANCHOR22 + 4326 0190 00000000 .word .LANCHOR9 + 4327 0194 00000000 .word .LANCHOR14 + 4328 0198 00000000 .word .LANCHOR43 + 4329 019c 00000000 .word .LANCHOR13 + 4330 01a0 00000000 .word .LANCHOR19 + 4331 01a4 00000000 .word .LANCHOR48 + 4332 01a8 00000000 .word .LANCHOR42 + 4333 01ac 00000000 .word .LANCHOR45 + 4334 01b0 00000000 .word .LANCHOR44 + 4335 01b4 00000000 .word .LANCHOR24 + 4336 01b8 00000000 .word .LANCHOR58 + 4337 01bc 00000000 .word .LANCHOR10 + 4338 01c0 00000000 .word .LANCHOR50 + 4339 .cfi_endproc + 4340 .LFE102: + 4342 .section .text.Send,"ax",%progbits + 4343 .align 1 + 4344 .global Send + ARM GAS /tmp/ccrFaSdZ.s page 127 + + + 4345 .syntax unified + 4346 .code 16 + 4347 .thumb_func + 4348 .fpu softvfp + 4350 Send: + 4351 .LFB101: +1879:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFrameCtrl_t fCtrl; + 4352 .loc 1 1879 0 + 4353 .cfi_startproc + 4354 @ args = 0, pretend = 0, frame = 8 + 4355 @ frame_needed = 0, uses_anonymous_args = 0 + 4356 .LVL397: + 4357 0000 30B5 push {r4, r5, lr} + 4358 .LCFI25: + 4359 .cfi_def_cfa_offset 12 + 4360 .cfi_offset 4, -12 + 4361 .cfi_offset 5, -8 + 4362 .cfi_offset 14, -4 + 4363 0002 85B0 sub sp, sp, #20 + 4364 .LCFI26: + 4365 .cfi_def_cfa_offset 32 + 4366 0004 0D00 movs r5, r1 + 4367 .LVL398: +1883:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.FOptsLen = 0; + 4368 .loc 1 1883 0 + 4369 0006 03A9 add r1, sp, #12 + 4370 .LVL399: +1888:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4371 .loc 1 1888 0 + 4372 0008 0B4C ldr r4, .L242 + 4373 000a 2478 ldrb r4, [r4] + 4374 000c E401 lsls r4, r4, #7 + 4375 000e 0C70 strb r4, [r1] +1891:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4376 .loc 1 1891 0 + 4377 0010 0093 str r3, [sp] + 4378 0012 1300 movs r3, r2 + 4379 .LVL400: + 4380 0014 2A00 movs r2, r5 + 4381 .LVL401: + 4382 0016 FFF7FEFF bl PrepareFrame + 4383 .LVL402: +1894:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4384 .loc 1 1894 0 + 4385 001a 0028 cmp r0, #0 + 4386 001c 01D0 beq .L241 + 4387 .LVL403: + 4388 .L240: +1907:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4389 .loc 1 1907 0 + 4390 001e 05B0 add sp, sp, #20 + 4391 @ sp needed + 4392 0020 30BD pop {r4, r5, pc} + 4393 .LVL404: + 4394 .L241: +1900:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; + 4395 .loc 1 1900 0 + ARM GAS /tmp/ccrFaSdZ.s page 128 + + + 4396 0022 064B ldr r3, .L242+4 + 4397 0024 0022 movs r2, #0 + 4398 0026 5A71 strb r2, [r3, #5] +1901:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.UpLinkCounter = UpLinkCounter; + 4399 .loc 1 1901 0 + 4400 0028 1A71 strb r2, [r3, #4] +1902:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4401 .loc 1 1902 0 + 4402 002a 054A ldr r2, .L242+8 + 4403 002c 1268 ldr r2, [r2] + 4404 002e DA60 str r2, [r3, #12] +1904:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4405 .loc 1 1904 0 + 4406 0030 FFF7FEFF bl ScheduleTx + 4407 .LVL405: +1906:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4408 .loc 1 1906 0 + 4409 0034 F3E7 b .L240 + 4410 .L243: + 4411 0036 C046 .align 2 + 4412 .L242: + 4413 0038 00000000 .word .LANCHOR29 + 4414 003c 00000000 .word .LANCHOR34 + 4415 0040 00000000 .word .LANCHOR1 + 4416 .cfi_endproc + 4417 .LFE101: + 4419 .section .text.OnTxDelayedTimerEvent,"ax",%progbits + 4420 .align 1 + 4421 .syntax unified + 4422 .code 16 + 4423 .thumb_func + 4424 .fpu softvfp + 4426 OnTxDelayedTimerEvent: + 4427 .LFB92: +1414:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + 4428 .loc 1 1414 0 + 4429 .cfi_startproc + 4430 @ args = 0, pretend = 0, frame = 16 + 4431 @ frame_needed = 0, uses_anonymous_args = 0 + 4432 0000 00B5 push {lr} + 4433 .LCFI27: + 4434 .cfi_def_cfa_offset 4 + 4435 .cfi_offset 14, -4 + 4436 0002 87B0 sub sp, sp, #28 + 4437 .LCFI28: + 4438 .cfi_def_cfa_offset 32 +1419:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_DELAYED; + 4439 .loc 1 1419 0 + 4440 0004 1748 ldr r0, .L247 + 4441 0006 FFF7FEFF bl TimerStop + 4442 .LVL406: +1420:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4443 .loc 1 1420 0 + 4444 000a 174A ldr r2, .L247+4 + 4445 000c 1023 movs r3, #16 + 4446 000e 1168 ldr r1, [r2] + 4447 0010 9943 bics r1, r3 + ARM GAS /tmp/ccrFaSdZ.s page 129 + + + 4448 0012 1160 str r1, [r2] +1422:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4449 .loc 1 1422 0 + 4450 0014 154B ldr r3, .L247+8 + 4451 0016 1B78 ldrb r3, [r3] + 4452 0018 1B07 lsls r3, r3, #28 + 4453 001a 03D5 bpl .L245 +1422:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4454 .loc 1 1422 0 is_stmt 0 discriminator 1 + 4455 001c 144B ldr r3, .L247+12 + 4456 001e 1B78 ldrb r3, [r3] + 4457 0020 002B cmp r3, #0 + 4458 0022 03D0 beq .L246 + 4459 .L245: +1441:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4460 .loc 1 1441 0 is_stmt 1 + 4461 0024 FFF7FEFF bl ScheduleTx + 4462 .LVL407: +1442:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4463 .loc 1 1442 0 + 4464 0028 07B0 add sp, sp, #28 + 4465 @ sp needed + 4466 002a 00BD pop {pc} + 4467 .L246: +1424:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4468 .loc 1 1424 0 + 4469 002c FFF7FEFF bl ResetMacParameters + 4470 .LVL408: +1426:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = RegionAlternateDr( LoRaMacRegion, &altDr ); + 4471 .loc 1 1426 0 + 4472 0030 104B ldr r3, .L247+16 + 4473 0032 1B78 ldrb r3, [r3] + 4474 0034 0133 adds r3, r3, #1 + 4475 0036 03A9 add r1, sp, #12 + 4476 0038 0B80 strh r3, [r1] +1427:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4477 .loc 1 1427 0 + 4478 003a 0F4B ldr r3, .L247+20 + 4479 003c 1878 ldrb r0, [r3] + 4480 003e FFF7FEFF bl RegionAlternateDr + 4481 .LVL409: + 4482 0042 0E4B ldr r3, .L247+24 + 4483 0044 5870 strb r0, [r3, #1] +1429:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; + 4484 .loc 1 1429 0 + 4485 0046 05A8 add r0, sp, #20 +1430:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4486 .loc 1 1430 0 + 4487 0048 0023 movs r3, #0 + 4488 004a 0370 strb r3, [r0] +1432:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fCtrl.Bits.Adr = AdrCtrlOn; + 4489 .loc 1 1432 0 + 4490 004c 04A9 add r1, sp, #16 +1433:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4491 .loc 1 1433 0 + 4492 004e 0C4B ldr r3, .L247+28 + 4493 0050 1B78 ldrb r3, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 130 + + + 4494 0052 DB01 lsls r3, r3, #7 + 4495 0054 0B70 strb r3, [r1] +1438:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4496 .loc 1 1438 0 + 4497 0056 0023 movs r3, #0 + 4498 0058 0093 str r3, [sp] + 4499 005a 0022 movs r2, #0 + 4500 005c FFF7FEFF bl PrepareFrame + 4501 .LVL410: + 4502 0060 E0E7 b .L245 + 4503 .L248: + 4504 0062 C046 .align 2 + 4505 .L247: + 4506 0064 00000000 .word .LANCHOR58 + 4507 0068 00000000 .word .LANCHOR24 + 4508 006c 00000000 .word .LANCHOR26 + 4509 0070 00000000 .word .LANCHOR28 + 4510 0074 00000000 .word .LANCHOR54 + 4511 0078 00000000 .word .LANCHOR22 + 4512 007c 00000000 .word .LANCHOR14 + 4513 0080 00000000 .word .LANCHOR29 + 4514 .cfi_endproc + 4515 .LFE92: + 4517 .section .text.OnMacStateCheckTimerEvent,"ax",%progbits + 4518 .align 1 + 4519 .syntax unified + 4520 .code 16 + 4521 .thumb_func + 4522 .fpu softvfp + 4524 OnMacStateCheckTimerEvent: + 4525 .LFB91: +1211:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 4526 .loc 1 1211 0 + 4527 .cfi_startproc + 4528 @ args = 0, pretend = 0, frame = 8 + 4529 @ frame_needed = 0, uses_anonymous_args = 0 + 4530 0000 10B5 push {r4, lr} + 4531 .LCFI29: + 4532 .cfi_def_cfa_offset 8 + 4533 .cfi_offset 4, -8 + 4534 .cfi_offset 14, -4 + 4535 0002 82B0 sub sp, sp, #8 + 4536 .LCFI30: + 4537 .cfi_def_cfa_offset 16 + 4538 .LVL411: +1216:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4539 .loc 1 1216 0 + 4540 0004 B748 ldr r0, .L280 + 4541 0006 FFF7FEFF bl TimerStop + 4542 .LVL412: +1218:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4543 .loc 1 1218 0 + 4544 000a B74B ldr r3, .L280+4 + 4545 000c 1B78 ldrb r3, [r3] + 4546 000e DA06 lsls r2, r3, #27 + 4547 0010 00D4 bmi .LCB4513 + 4548 0012 12E1 b .L250 @long jump + ARM GAS /tmp/ccrFaSdZ.s page 131 + + + 4549 .LCB4513: +1220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4550 .loc 1 1220 0 + 4551 0014 B54A ldr r2, .L280+8 + 4552 0016 1268 ldr r2, [r2] + 4553 0018 5106 lsls r1, r2, #25 + 4554 001a 05D5 bpl .L251 +1222:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; + 4555 .loc 1 1222 0 + 4556 001c 4021 movs r1, #64 + 4557 001e 8A43 bics r2, r1 +1223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4558 .loc 1 1223 0 + 4559 0020 3F39 subs r1, r1, #63 + 4560 0022 8A43 bics r2, r1 + 4561 0024 B149 ldr r1, .L280+8 + 4562 0026 0A60 str r2, [r1] + 4563 .L251: +1226:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4564 .loc 1 1226 0 + 4565 0028 0922 movs r2, #9 + 4566 002a 1A40 ands r2, r3 + 4567 002c 19D0 beq .L276 +1228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( MlmeConfirm.Status == LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT ) ) + 4568 .loc 1 1228 0 + 4569 002e B049 ldr r1, .L280+12 + 4570 0030 4978 ldrb r1, [r1, #1] + 4571 0032 0229 cmp r1, #2 + 4572 0034 05D0 beq .L253 +1229:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4573 .loc 1 1229 0 discriminator 1 + 4574 0036 AF49 ldr r1, .L280+16 + 4575 0038 4978 ldrb r1, [r1, #1] +1228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( MlmeConfirm.Status == LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT ) ) + 4576 .loc 1 1228 0 discriminator 1 + 4577 003a 0229 cmp r1, #2 + 4578 003c 01D0 beq .L253 +1214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4579 .loc 1 1214 0 + 4580 003e 0020 movs r0, #0 + 4581 0040 10E0 b .L252 + 4582 .L253: +1232:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; + 4583 .loc 1 1232 0 + 4584 0042 AA48 ldr r0, .L280+8 + 4585 0044 0121 movs r1, #1 + 4586 0046 0468 ldr r4, [r0] + 4587 0048 8C43 bics r4, r1 + 4588 004a 0460 str r4, [r0] +1233:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + 4589 .loc 1 1233 0 + 4590 004c 0020 movs r0, #0 + 4591 004e AA49 ldr r1, .L280+20 + 4592 0050 0870 strb r0, [r1] +1234:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; + 4593 .loc 1 1234 0 + 4594 0052 A749 ldr r1, .L280+12 + ARM GAS /tmp/ccrFaSdZ.s page 132 + + + 4595 0054 A94C ldr r4, .L280+24 + 4596 0056 2478 ldrb r4, [r4] + 4597 0058 4C71 strb r4, [r1, #5] +1235:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.TxTimeOnAir = 0; + 4598 .loc 1 1235 0 + 4599 005a 0871 strb r0, [r1, #4] +1236:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txTimeout = true; + 4600 .loc 1 1236 0 + 4601 005c 8860 str r0, [r1, #8] + 4602 .LVL413: +1237:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4603 .loc 1 1237 0 + 4604 005e 0130 adds r0, r0, #1 + 4605 0060 00E0 b .L252 + 4606 .LVL414: + 4607 .L276: +1214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4608 .loc 1 1214 0 + 4609 0062 0020 movs r0, #0 + 4610 .LVL415: + 4611 .L252: +1241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4612 .loc 1 1241 0 + 4613 0064 A649 ldr r1, .L280+28 + 4614 0066 0978 ldrb r1, [r1] + 4615 0068 0029 cmp r1, #0 + 4616 006a 4ED1 bne .L254 +1241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4617 .loc 1 1241 0 is_stmt 0 discriminator 1 + 4618 006c 0028 cmp r0, #0 + 4619 006e 4CD1 bne .L254 +1243:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4620 .loc 1 1243 0 is_stmt 1 + 4621 0070 002A cmp r2, #0 + 4622 0072 4AD0 beq .L254 +1245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure for the join request + 4623 .loc 1 1245 0 + 4624 0074 1A07 lsls r2, r3, #28 + 4625 0076 26D5 bpl .L255 +1245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure for the join request + 4626 .loc 1 1245 0 is_stmt 0 discriminator 1 + 4627 0078 9E4A ldr r2, .L280+16 + 4628 007a 1278 ldrb r2, [r2] + 4629 007c 002A cmp r2, #0 + 4630 007e 22D1 bne .L255 +1247:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4631 .loc 1 1247 0 is_stmt 1 + 4632 0080 A04B ldr r3, .L280+32 + 4633 0082 1A78 ldrb r2, [r3] + 4634 0084 9B4B ldr r3, .L280+16 + 4635 0086 9A72 strb r2, [r3, #10] +1249:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Node joined successfully + 4636 .loc 1 1249 0 + 4637 0088 5B78 ldrb r3, [r3, #1] + 4638 008a 002B cmp r3, #0 + 4639 008c 09D1 bne .L256 +1251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelsNbRepCounter = 0; + ARM GAS /tmp/ccrFaSdZ.s page 133 + + + 4640 .loc 1 1251 0 + 4641 008e 9E4A ldr r2, .L280+36 + 4642 0090 1360 str r3, [r2] +1252:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; + 4643 .loc 1 1252 0 + 4644 0092 9E4A ldr r2, .L280+40 + 4645 0094 1370 strb r3, [r2] +1253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4646 .loc 1 1253 0 + 4647 0096 954A ldr r2, .L280+8 + 4648 0098 0133 adds r3, r3, #1 + 4649 009a 1168 ldr r1, [r2] + 4650 009c 9943 bics r1, r3 + 4651 009e 1160 str r1, [r2] + 4652 00a0 33E0 b .L254 + 4653 .L256: +1257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4654 .loc 1 1257 0 + 4655 00a2 9B4B ldr r3, .L280+44 + 4656 00a4 1B78 ldrb r3, [r3] + 4657 00a6 9A42 cmp r2, r3 + 4658 00a8 05D3 bcc .L257 +1259:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4659 .loc 1 1259 0 + 4660 00aa 904A ldr r2, .L280+8 + 4661 00ac 0123 movs r3, #1 + 4662 00ae 1168 ldr r1, [r2] + 4663 00b0 9943 bics r1, r3 + 4664 00b2 1160 str r1, [r2] + 4665 00b4 29E0 b .L254 + 4666 .L257: +1263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Sends the same frame again + 4667 .loc 1 1263 0 + 4668 00b6 8C4A ldr r2, .L280+4 + 4669 00b8 1378 ldrb r3, [r2] + 4670 00ba 1021 movs r1, #16 + 4671 00bc 8B43 bics r3, r1 + 4672 00be 1370 strb r3, [r2] +1265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4673 .loc 1 1265 0 + 4674 00c0 FFF7FEFF bl OnTxDelayedTimerEvent + 4675 .LVL416: + 4676 00c4 21E0 b .L254 + 4677 .LVL417: + 4678 .L255: +1271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4679 .loc 1 1271 0 + 4680 00c6 9349 ldr r1, .L280+48 + 4681 00c8 2022 movs r2, #32 + 4682 00ca 895C ldrb r1, [r1, r2] + 4683 00cc 8F4A ldr r2, .L280+40 + 4684 00ce 1278 ldrb r2, [r2] + 4685 00d0 9142 cmp r1, r2 + 4686 00d2 01D9 bls .L258 +1271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4687 .loc 1 1271 0 is_stmt 0 discriminator 1 + 4688 00d4 9A07 lsls r2, r3, #30 + ARM GAS /tmp/ccrFaSdZ.s page 134 + + + 4689 00d6 5FD5 bpl .L259 + 4690 .L258: +1273:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { // Maximum repetitions without downlink. Reset MacCommandsBufferIndex. + 4691 .loc 1 1273 0 is_stmt 1 + 4692 00d8 9B07 lsls r3, r3, #30 + 4693 00da 06D4 bmi .L260 +1276:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrAckCounter++; + 4694 .loc 1 1276 0 + 4695 00dc 864B ldr r3, .L280+20 + 4696 00de 0022 movs r2, #0 + 4697 00e0 1A70 strb r2, [r3] +1277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4698 .loc 1 1277 0 + 4699 00e2 8D4A ldr r2, .L280+52 + 4700 00e4 1368 ldr r3, [r2] + 4701 00e6 0133 adds r3, r3, #1 + 4702 00e8 1360 str r3, [r2] + 4703 .L260: +1280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4704 .loc 1 1280 0 + 4705 00ea 884B ldr r3, .L280+40 + 4706 00ec 0022 movs r2, #0 + 4707 00ee 1A70 strb r2, [r3] +1282:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4708 .loc 1 1282 0 + 4709 00f0 8A4B ldr r3, .L280+56 + 4710 00f2 1B78 ldrb r3, [r3] + 4711 00f4 002B cmp r3, #0 + 4712 00f6 03D1 bne .L261 +1284:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4713 .loc 1 1284 0 + 4714 00f8 834A ldr r2, .L280+36 + 4715 00fa 1368 ldr r3, [r2] + 4716 00fc 0133 adds r3, r3, #1 + 4717 00fe 1360 str r3, [r2] + 4718 .L261: +1287:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4719 .loc 1 1287 0 + 4720 0100 7A4A ldr r2, .L280+8 + 4721 0102 0123 movs r3, #1 + 4722 0104 1168 ldr r1, [r2] + 4723 0106 9943 bics r1, r3 + 4724 0108 1160 str r1, [r2] + 4725 .LVL418: + 4726 .L254: +1299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Procedure if we received a frame + 4727 .loc 1 1299 0 + 4728 010a 774B ldr r3, .L280+4 + 4729 010c 1B78 ldrb r3, [r3] + 4730 010e 9B07 lsls r3, r3, #30 + 4731 0110 1FD5 bpl .L262 +1301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4732 .loc 1 1301 0 + 4733 0112 774B ldr r3, .L280+12 + 4734 0114 1B79 ldrb r3, [r3, #4] + 4735 0116 002B cmp r3, #0 + 4736 0118 05D1 bne .L263 + ARM GAS /tmp/ccrFaSdZ.s page 135 + + +1301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4737 .loc 1 1301 0 is_stmt 0 discriminator 1 + 4738 011a 784B ldr r3, .L280+24 + 4739 011c 1A78 ldrb r2, [r3] + 4740 011e 804B ldr r3, .L280+60 + 4741 0120 1B78 ldrb r3, [r3] + 4742 0122 9A42 cmp r2, r3 + 4743 0124 15D9 bls .L262 + 4744 .L263: +1303:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 4745 .loc 1 1303 0 is_stmt 1 + 4746 0126 0023 movs r3, #0 + 4747 0128 7E4A ldr r2, .L280+64 + 4748 012a 1370 strb r3, [r2] +1304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) + 4749 .loc 1 1304 0 + 4750 012c 744A ldr r2, .L280+28 + 4751 012e 1370 strb r3, [r2] +1305:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4752 .loc 1 1305 0 + 4753 0130 7A4B ldr r3, .L280+56 + 4754 0132 1B78 ldrb r3, [r3] + 4755 0134 002B cmp r3, #0 + 4756 0136 03D1 bne .L264 +1307:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4757 .loc 1 1307 0 + 4758 0138 734A ldr r2, .L280+36 + 4759 013a 1368 ldr r3, [r2] + 4760 013c 0133 adds r3, r3, #1 + 4761 013e 1360 str r3, [r2] + 4762 .L264: +1309:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4763 .loc 1 1309 0 + 4764 0140 6E4B ldr r3, .L280+24 + 4765 0142 1A78 ldrb r2, [r3] + 4766 0144 6A4B ldr r3, .L280+12 + 4767 0146 5A71 strb r2, [r3, #5] +1311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4768 .loc 1 1311 0 + 4769 0148 684A ldr r2, .L280+8 + 4770 014a 0123 movs r3, #1 + 4771 014c 1168 ldr r1, [r2] + 4772 014e 9943 bics r1, r3 + 4773 0150 1160 str r1, [r2] + 4774 .L262: +1315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Retransmissions procedure for confirmed uplinks + 4775 .loc 1 1315 0 + 4776 0152 744B ldr r3, .L280+64 + 4777 0154 1B78 ldrb r3, [r3] + 4778 0156 002B cmp r3, #0 + 4779 0158 6FD0 beq .L250 +1315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Retransmissions procedure for confirmed uplinks + 4780 .loc 1 1315 0 is_stmt 0 discriminator 1 + 4781 015a 644B ldr r3, .L280+8 + 4782 015c 1B68 ldr r3, [r3] + 4783 015e DB06 lsls r3, r3, #27 + 4784 0160 6BD4 bmi .L250 + ARM GAS /tmp/ccrFaSdZ.s page 136 + + +1317:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( AckTimeoutRetriesCounter < AckTimeoutRetries ) && ( AckTimeoutRetriesCounter <= M + 4785 .loc 1 1317 0 is_stmt 1 + 4786 0162 704B ldr r3, .L280+64 + 4787 0164 0022 movs r2, #0 + 4788 0166 1A70 strb r2, [r3] +1318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4789 .loc 1 1318 0 + 4790 0168 644B ldr r3, .L280+24 + 4791 016a 1B78 ldrb r3, [r3] + 4792 016c 6C4A ldr r2, .L280+60 + 4793 016e 1278 ldrb r2, [r2] + 4794 0170 9342 cmp r3, r2 + 4795 0172 46D2 bcs .L265 +1318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4796 .loc 1 1318 0 is_stmt 0 discriminator 1 + 4797 0174 082B cmp r3, #8 + 4798 0176 44D8 bhi .L265 +1320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4799 .loc 1 1320 0 is_stmt 1 + 4800 0178 0133 adds r3, r3, #1 + 4801 017a DBB2 uxtb r3, r3 + 4802 017c 5F4A ldr r2, .L280+24 + 4803 017e 1370 strb r3, [r2] +1322:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4804 .loc 1 1322 0 + 4805 0180 DB07 lsls r3, r3, #31 + 4806 0182 11D4 bmi .L278 + 4807 .LVL419: + 4808 .L266: +1331:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4809 .loc 1 1331 0 + 4810 0184 FFF7FEFF bl ScheduleTx + 4811 .LVL420: + 4812 0188 0028 cmp r0, #0 + 4813 018a 1DD1 bne .L267 +1333:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4814 .loc 1 1333 0 + 4815 018c 564A ldr r2, .L280+4 + 4816 018e 1378 ldrb r3, [r2] + 4817 0190 1021 movs r1, #16 + 4818 0192 8B43 bics r3, r1 + 4819 0194 1370 strb r3, [r2] + 4820 0196 50E0 b .L250 + 4821 .LVL421: + 4822 .L259: +1291:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Sends the same frame again + 4823 .loc 1 1291 0 + 4824 0198 534A ldr r2, .L280+4 + 4825 019a 1378 ldrb r3, [r2] + 4826 019c 1021 movs r1, #16 + 4827 019e 8B43 bics r3, r1 + 4828 01a0 1370 strb r3, [r2] +1293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4829 .loc 1 1293 0 + 4830 01a2 FFF7FEFF bl OnTxDelayedTimerEvent + 4831 .LVL422: + 4832 01a6 B0E7 b .L254 + ARM GAS /tmp/ccrFaSdZ.s page 137 + + + 4833 .L278: +1324:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 4834 .loc 1 1324 0 + 4835 01a8 01A9 add r1, sp, #4 + 4836 01aa 2023 movs r3, #32 + 4837 01ac 0B70 strb r3, [r1] +1325:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = LoRaMacParams.ChannelsDatarate; + 4838 .loc 1 1325 0 + 4839 01ae 594C ldr r4, .L280+48 + 4840 01b0 0C33 adds r3, r3, #12 + 4841 01b2 E35C ldrb r3, [r4, r3] + 4842 01b4 8B70 strb r3, [r1, #2] +1326:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 4843 .loc 1 1326 0 + 4844 01b6 0123 movs r3, #1 + 4845 01b8 E356 ldrsb r3, [r4, r3] + 4846 01ba 4B70 strb r3, [r1, #1] +1327:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = phyParam.Value; + 4847 .loc 1 1327 0 + 4848 01bc 5A4B ldr r3, .L280+68 + 4849 01be 1878 ldrb r0, [r3] + 4850 01c0 FFF7FEFF bl RegionGetPhyParam + 4851 .LVL423: +1328:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4852 .loc 1 1328 0 + 4853 01c4 6070 strb r0, [r4, #1] + 4854 01c6 DDE7 b .L266 + 4855 .L267: +1338:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4856 .loc 1 1338 0 + 4857 01c8 494B ldr r3, .L280+12 + 4858 01ca 0922 movs r2, #9 + 4859 01cc 5A70 strb r2, [r3, #1] +1340:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState &= ~LORAMAC_TX_RUNNING; + 4860 .loc 1 1340 0 + 4861 01ce 0022 movs r2, #0 + 4862 01d0 4949 ldr r1, .L280+20 + 4863 01d2 0A70 strb r2, [r1] +1341:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 4864 .loc 1 1341 0 + 4865 01d4 4548 ldr r0, .L280+8 + 4866 01d6 0121 movs r1, #1 + 4867 01d8 0468 ldr r4, [r0] + 4868 01da 8C43 bics r4, r1 + 4869 01dc 0460 str r4, [r0] +1342:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; + 4870 .loc 1 1342 0 + 4871 01de 4849 ldr r1, .L280+28 + 4872 01e0 0A70 strb r2, [r1] +1343:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + 4873 .loc 1 1343 0 + 4874 01e2 1A71 strb r2, [r3, #4] +1344:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Datarate = LoRaMacParams.ChannelsDatarate; + 4875 .loc 1 1344 0 + 4876 01e4 454A ldr r2, .L280+24 + 4877 01e6 1278 ldrb r2, [r2] + 4878 01e8 5A71 strb r2, [r3, #5] + ARM GAS /tmp/ccrFaSdZ.s page 138 + + +1345:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) + 4879 .loc 1 1345 0 + 4880 01ea 4A4A ldr r2, .L280+48 + 4881 01ec 5278 ldrb r2, [r2, #1] + 4882 01ee 9A70 strb r2, [r3, #2] +1346:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4883 .loc 1 1346 0 + 4884 01f0 4A4B ldr r3, .L280+56 + 4885 01f2 1B78 ldrb r3, [r3] + 4886 01f4 002B cmp r3, #0 + 4887 01f6 20D1 bne .L250 +1348:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4888 .loc 1 1348 0 + 4889 01f8 434A ldr r2, .L280+36 + 4890 01fa 1368 ldr r3, [r2] + 4891 01fc 0133 adds r3, r3, #1 + 4892 01fe 1360 str r3, [r2] + 4893 0200 1BE0 b .L250 + 4894 .L265: +1354:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4895 .loc 1 1354 0 + 4896 0202 494B ldr r3, .L280+68 + 4897 0204 1878 ldrb r0, [r3] + 4898 0206 0121 movs r1, #1 + 4899 0208 FFF7FEFF bl RegionInitDefaults + 4900 .LVL424: +1356:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 4901 .loc 1 1356 0 + 4902 020c 374A ldr r2, .L280+8 + 4903 020e 0123 movs r3, #1 + 4904 0210 1168 ldr r1, [r2] + 4905 0212 9943 bics r1, r3 + 4906 0214 1160 str r1, [r2] +1358:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 4907 .loc 1 1358 0 + 4908 0216 0023 movs r3, #0 + 4909 0218 374A ldr r2, .L280+20 + 4910 021a 1370 strb r3, [r2] +1359:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.AckReceived = false; + 4911 .loc 1 1359 0 + 4912 021c 384A ldr r2, .L280+28 + 4913 021e 1370 strb r3, [r2] +1360:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + 4914 .loc 1 1360 0 + 4915 0220 334A ldr r2, .L280+12 + 4916 0222 1371 strb r3, [r2, #4] +1361:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( IsUpLinkCounterFixed == false ) + 4917 .loc 1 1361 0 + 4918 0224 354B ldr r3, .L280+24 + 4919 0226 1B78 ldrb r3, [r3] + 4920 0228 5371 strb r3, [r2, #5] +1362:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4921 .loc 1 1362 0 + 4922 022a 3C4B ldr r3, .L280+56 + 4923 022c 1B78 ldrb r3, [r3] + 4924 022e 002B cmp r3, #0 + 4925 0230 03D1 bne .L250 + ARM GAS /tmp/ccrFaSdZ.s page 139 + + +1364:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4926 .loc 1 1364 0 + 4927 0232 354A ldr r2, .L280+36 + 4928 0234 1368 ldr r3, [r2] + 4929 0236 0133 adds r3, r3, #1 + 4930 0238 1360 str r3, [r2] + 4931 .L250: +1370:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4932 .loc 1 1370 0 + 4933 023a 2C4B ldr r3, .L280+8 + 4934 023c 1B68 ldr r3, [r3] + 4935 023e 9A07 lsls r2, r3, #30 + 4936 0240 03D5 bpl .L268 +1372:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4937 .loc 1 1372 0 + 4938 0242 0222 movs r2, #2 + 4939 0244 9343 bics r3, r2 + 4940 0246 294A ldr r2, .L280+8 + 4941 0248 1360 str r3, [r2] + 4942 .L268: +1374:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4943 .loc 1 1374 0 + 4944 024a 284B ldr r3, .L280+8 + 4945 024c 1B68 ldr r3, [r3] + 4946 024e 002B cmp r3, #0 + 4947 0250 3AD1 bne .L269 +1376:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4948 .loc 1 1376 0 + 4949 0252 254B ldr r3, .L280+4 + 4950 0254 1B78 ldrb r3, [r3] + 4951 0256 DB07 lsls r3, r3, #31 + 4952 0258 09D5 bpl .L270 +1378:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsReq = 0; + 4953 .loc 1 1378 0 + 4954 025a 344B ldr r3, .L280+72 + 4955 025c 1B68 ldr r3, [r3] + 4956 025e 1B68 ldr r3, [r3] + 4957 0260 2348 ldr r0, .L280+12 + 4958 0262 9847 blx r3 + 4959 .LVL425: +1379:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4960 .loc 1 1379 0 + 4961 0264 204A ldr r2, .L280+4 + 4962 0266 1378 ldrb r3, [r2] + 4963 0268 0121 movs r1, #1 + 4964 026a 8B43 bics r3, r1 + 4965 026c 1370 strb r3, [r2] + 4966 .L270: +1382:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4967 .loc 1 1382 0 + 4968 026e 1E4B ldr r3, .L280+4 + 4969 0270 1B78 ldrb r3, [r3] + 4970 0272 1B07 lsls r3, r3, #28 + 4971 0274 09D5 bpl .L271 +1384:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 0; + 4972 .loc 1 1384 0 + 4973 0276 2D4B ldr r3, .L280+72 + ARM GAS /tmp/ccrFaSdZ.s page 140 + + + 4974 0278 1B68 ldr r3, [r3] + 4975 027a 9B68 ldr r3, [r3, #8] + 4976 027c 1D48 ldr r0, .L280+16 + 4977 027e 9847 blx r3 + 4978 .LVL426: +1385:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4979 .loc 1 1385 0 + 4980 0280 194A ldr r2, .L280+4 + 4981 0282 1378 ldrb r3, [r2] + 4982 0284 0821 movs r1, #8 + 4983 0286 8B43 bics r3, r1 + 4984 0288 1370 strb r3, [r2] + 4985 .L271: +1389:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 4986 .loc 1 1389 0 + 4987 028a 174A ldr r2, .L280+4 + 4988 028c 1378 ldrb r3, [r2] + 4989 028e 1021 movs r1, #16 + 4990 0290 8B43 bics r3, r1 + 4991 0292 1370 strb r3, [r2] + 4992 .L272: +1398:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 4993 .loc 1 1398 0 + 4994 0294 144B ldr r3, .L280+4 + 4995 0296 1B78 ldrb r3, [r3] + 4996 0298 9B07 lsls r3, r3, #30 + 4997 029a 13D5 bpl .L249 +1400:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** {// Activate RX2 window for Class C + 4998 .loc 1 1400 0 + 4999 029c 244B ldr r3, .L280+76 + 5000 029e 1B78 ldrb r3, [r3] + 5001 02a0 022B cmp r3, #2 + 5002 02a2 1BD0 beq .L279 + 5003 .L274: +1404:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5004 .loc 1 1404 0 + 5005 02a4 104B ldr r3, .L280+4 + 5006 02a6 1B78 ldrb r3, [r3] + 5007 02a8 5B07 lsls r3, r3, #29 + 5008 02aa 04D4 bmi .L275 +1406:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5009 .loc 1 1406 0 + 5010 02ac 1F4B ldr r3, .L280+72 + 5011 02ae 1B68 ldr r3, [r3] + 5012 02b0 5B68 ldr r3, [r3, #4] + 5013 02b2 2048 ldr r0, .L280+80 + 5014 02b4 9847 blx r3 + 5015 .LVL427: + 5016 .L275: +1408:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsInd = 0; + 5017 .loc 1 1408 0 + 5018 02b6 0C4A ldr r2, .L280+4 + 5019 02b8 1378 ldrb r3, [r2] +1409:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5020 .loc 1 1409 0 + 5021 02ba 0421 movs r1, #4 + 5022 02bc 8B43 bics r3, r1 + ARM GAS /tmp/ccrFaSdZ.s page 141 + + + 5023 02be 0239 subs r1, r1, #2 + 5024 02c0 8B43 bics r3, r1 + 5025 02c2 1370 strb r3, [r2] + 5026 .L249: +1411:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 5027 .loc 1 1411 0 + 5028 02c4 02B0 add sp, sp, #8 + 5029 @ sp needed + 5030 02c6 10BD pop {r4, pc} + 5031 .L269: +1394:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 5032 .loc 1 1394 0 + 5033 02c8 FA21 movs r1, #250 + 5034 02ca 064C ldr r4, .L280 + 5035 02cc 8900 lsls r1, r1, #2 + 5036 02ce 2000 movs r0, r4 + 5037 02d0 FFF7FEFF bl TimerSetValue + 5038 .LVL428: +1395:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5039 .loc 1 1395 0 + 5040 02d4 2000 movs r0, r4 + 5041 02d6 FFF7FEFF bl TimerStart + 5042 .LVL429: + 5043 02da DBE7 b .L272 + 5044 .L279: +1402:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5045 .loc 1 1402 0 + 5046 02dc FFF7FEFF bl OnRxWindow2TimerEvent + 5047 .LVL430: + 5048 02e0 E0E7 b .L274 + 5049 .L281: + 5050 02e2 C046 .align 2 + 5051 .L280: + 5052 02e4 00000000 .word .LANCHOR27 + 5053 02e8 00000000 .word .LANCHOR26 + 5054 02ec 00000000 .word .LANCHOR24 + 5055 02f0 00000000 .word .LANCHOR34 + 5056 02f4 00000000 .word .LANCHOR28 + 5057 02f8 00000000 .word .LANCHOR10 + 5058 02fc 00000000 .word .LANCHOR6 + 5059 0300 00000000 .word .LANCHOR15 + 5060 0304 00000000 .word .LANCHOR54 + 5061 0308 00000000 .word .LANCHOR1 + 5062 030c 00000000 .word .LANCHOR4 + 5063 0310 00000000 .word .LANCHOR59 + 5064 0314 00000000 .word .LANCHOR14 + 5065 0318 00000000 .word .LANCHOR3 + 5066 031c 00000000 .word .LANCHOR60 + 5067 0320 00000000 .word .LANCHOR5 + 5068 0324 00000000 .word .LANCHOR7 + 5069 0328 00000000 .word .LANCHOR22 + 5070 032c 00000000 .word .LANCHOR61 + 5071 0330 00000000 .word .LANCHOR25 + 5072 0334 00000000 .word .LANCHOR35 + 5073 .cfi_endproc + 5074 .LFE91: + 5076 .section .text.SetTxContinuousWave,"ax",%progbits + ARM GAS /tmp/ccrFaSdZ.s page 142 + + + 5077 .align 1 + 5078 .global SetTxContinuousWave + 5079 .syntax unified + 5080 .code 16 + 5081 .thumb_func + 5082 .fpu softvfp + 5084 SetTxContinuousWave: + 5085 .LFB107: +2261:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2262:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SetTxContinuousWave( uint16_t timeout ) +2263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5086 .loc 1 2263 0 + 5087 .cfi_startproc + 5088 @ args = 0, pretend = 0, frame = 24 + 5089 @ frame_needed = 0, uses_anonymous_args = 0 + 5090 .LVL431: + 5091 0000 10B5 push {r4, lr} + 5092 .LCFI31: + 5093 .cfi_def_cfa_offset 8 + 5094 .cfi_offset 4, -8 + 5095 .cfi_offset 14, -4 + 5096 0002 86B0 sub sp, sp, #24 + 5097 .LCFI32: + 5098 .cfi_def_cfa_offset 32 +2264:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ContinuousWaveParams_t continuousWave; +2265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2266:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.Channel = Channel; + 5099 .loc 1 2266 0 + 5100 0004 134B ldr r3, .L283 + 5101 0006 1B78 ldrb r3, [r3] + 5102 0008 02AA add r2, sp, #8 + 5103 000a 1370 strb r3, [r2] +2267:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.Datarate = LoRaMacParams.ChannelsDatarate; + 5104 .loc 1 2267 0 + 5105 000c 124B ldr r3, .L283+4 + 5106 000e 0122 movs r2, #1 + 5107 0010 9A56 ldrsb r2, [r3, r2] + 5108 0012 02A9 add r1, sp, #8 + 5109 0014 4A70 strb r2, [r1, #1] +2268:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.TxPower = LoRaMacParams.ChannelsTxPower; + 5110 .loc 1 2268 0 + 5111 0016 0022 movs r2, #0 + 5112 0018 9A56 ldrsb r2, [r3, r2] + 5113 001a 8A70 strb r2, [r1, #2] +2269:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.MaxEirp = LoRaMacParams.MaxEirp; + 5114 .loc 1 2269 0 + 5115 001c 1A6B ldr r2, [r3, #48] + 5116 001e 0392 str r2, [sp, #12] +2270:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.AntennaGain = LoRaMacParams.AntennaGain; + 5117 .loc 1 2270 0 + 5118 0020 5B6B ldr r3, [r3, #52] + 5119 0022 0193 str r3, [sp, #4] + 5120 0024 0493 str r3, [sp, #16] +2271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** continuousWave.Timeout = timeout; + 5121 .loc 1 2271 0 + 5122 0026 8881 strh r0, [r1, #12] +2272:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 143 + + +2273:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionSetContinuousWave( LoRaMacRegion, &continuousWave ); + 5123 .loc 1 2273 0 + 5124 0028 0C4B ldr r3, .L283+8 + 5125 002a 1878 ldrb r0, [r3] + 5126 .LVL432: + 5127 002c FFF7FEFF bl RegionSetContinuousWave + 5128 .LVL433: +2274:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2275:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Starts the MAC layer status check timer +2276:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + 5129 .loc 1 2276 0 + 5130 0030 FA21 movs r1, #250 + 5131 0032 0B4C ldr r4, .L283+12 + 5132 0034 8900 lsls r1, r1, #2 + 5133 0036 2000 movs r0, r4 + 5134 0038 FFF7FEFF bl TimerSetValue + 5135 .LVL434: +2277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 5136 .loc 1 2277 0 + 5137 003c 2000 movs r0, r4 + 5138 003e FFF7FEFF bl TimerStart + 5139 .LVL435: +2278:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2279:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_TX_RUNNING; + 5140 .loc 1 2279 0 + 5141 0042 084A ldr r2, .L283+16 + 5142 0044 0123 movs r3, #1 + 5143 0046 1168 ldr r1, [r2] + 5144 0048 0B43 orrs r3, r1 + 5145 004a 1360 str r3, [r2] +2280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2281:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; +2282:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5146 .loc 1 2282 0 + 5147 004c 0020 movs r0, #0 + 5148 004e 06B0 add sp, sp, #24 + 5149 @ sp needed + 5150 0050 10BD pop {r4, pc} + 5151 .L284: + 5152 0052 C046 .align 2 + 5153 .L283: + 5154 0054 00000000 .word .LANCHOR19 + 5155 0058 00000000 .word .LANCHOR14 + 5156 005c 00000000 .word .LANCHOR22 + 5157 0060 00000000 .word .LANCHOR27 + 5158 0064 00000000 .word .LANCHOR24 + 5159 .cfi_endproc + 5160 .LFE107: + 5162 .section .text.SetTxContinuousWave1,"ax",%progbits + 5163 .align 1 + 5164 .global SetTxContinuousWave1 + 5165 .syntax unified + 5166 .code 16 + 5167 .thumb_func + 5168 .fpu softvfp + 5170 SetTxContinuousWave1: + 5171 .LFB108: + ARM GAS /tmp/ccrFaSdZ.s page 144 + + +2283:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2284:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t SetTxContinuousWave1( uint16_t timeout, uint32_t frequency, uint8_t power ) +2285:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5172 .loc 1 2285 0 + 5173 .cfi_startproc + 5174 @ args = 0, pretend = 0, frame = 0 + 5175 @ frame_needed = 0, uses_anonymous_args = 0 + 5176 .LVL436: + 5177 0000 10B5 push {r4, lr} + 5178 .LCFI33: + 5179 .cfi_def_cfa_offset 8 + 5180 .cfi_offset 4, -8 + 5181 .cfi_offset 14, -4 + 5182 0002 0400 movs r4, r0 + 5183 0004 0800 movs r0, r1 + 5184 .LVL437: +2286:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.SetTxContinuousWave( frequency, power, timeout ); + 5185 .loc 1 2286 0 + 5186 0006 0A4B ldr r3, .L286 + 5187 0008 5B6C ldr r3, [r3, #68] + 5188 000a 51B2 sxtb r1, r2 + 5189 .LVL438: + 5190 000c 2200 movs r2, r4 + 5191 .LVL439: + 5192 000e 9847 blx r3 + 5193 .LVL440: +2287:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2288:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Starts the MAC layer status check timer +2289:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + 5194 .loc 1 2289 0 + 5195 0010 FA21 movs r1, #250 + 5196 0012 084C ldr r4, .L286+4 + 5197 0014 8900 lsls r1, r1, #2 + 5198 0016 2000 movs r0, r4 + 5199 0018 FFF7FEFF bl TimerSetValue + 5200 .LVL441: +2290:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerStart( &MacStateCheckTimer ); + 5201 .loc 1 2290 0 + 5202 001c 2000 movs r0, r4 + 5203 001e FFF7FEFF bl TimerStart + 5204 .LVL442: +2291:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2292:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState |= LORAMAC_TX_RUNNING; + 5205 .loc 1 2292 0 + 5206 0022 054A ldr r2, .L286+8 + 5207 0024 0123 movs r3, #1 + 5208 0026 1168 ldr r1, [r2] + 5209 0028 0B43 orrs r3, r1 + 5210 002a 1360 str r3, [r2] +2293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2294:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; +2295:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5211 .loc 1 2295 0 + 5212 002c 0020 movs r0, #0 + 5213 @ sp needed + 5214 002e 10BD pop {r4, pc} + 5215 .L287: + ARM GAS /tmp/ccrFaSdZ.s page 145 + + + 5216 .align 2 + 5217 .L286: + 5218 0030 00000000 .word Radio + 5219 0034 00000000 .word .LANCHOR27 + 5220 0038 00000000 .word .LANCHOR24 + 5221 .cfi_endproc + 5222 .LFE108: + 5224 .section .text.LoRaMacInitialization,"ax",%progbits + 5225 .align 1 + 5226 .global LoRaMacInitialization + 5227 .syntax unified + 5228 .code 16 + 5229 .thumb_func + 5230 .fpu softvfp + 5232 LoRaMacInitialization: + 5233 .LFB109: +2296:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2297:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacInitialization( LoRaMacPrimitives_t *primitives, LoRaMacCallback_t *callback +2298:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5234 .loc 1 2298 0 + 5235 .cfi_startproc + 5236 @ args = 0, pretend = 0, frame = 8 + 5237 @ frame_needed = 0, uses_anonymous_args = 0 + 5238 .LVL443: + 5239 0000 F0B5 push {r4, r5, r6, r7, lr} + 5240 .LCFI34: + 5241 .cfi_def_cfa_offset 20 + 5242 .cfi_offset 4, -20 + 5243 .cfi_offset 5, -16 + 5244 .cfi_offset 6, -12 + 5245 .cfi_offset 7, -8 + 5246 .cfi_offset 14, -4 + 5247 0002 83B0 sub sp, sp, #12 + 5248 .LCFI35: + 5249 .cfi_def_cfa_offset 32 + 5250 0004 0400 movs r4, r0 + 5251 0006 0E00 movs r6, r1 + 5252 0008 1500 movs r5, r2 +2299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +2300:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +2301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2302:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( primitives == NULL ) + 5253 .loc 1 2302 0 + 5254 000a 0028 cmp r0, #0 + 5255 000c 00D1 bne .LCB5188 + 5256 000e EFE0 b .L290 @long jump + 5257 .LCB5188: +2303:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +2305:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2306:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2307:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( primitives->MacMcpsConfirm == NULL ) || + 5258 .loc 1 2307 0 + 5259 0010 0368 ldr r3, [r0] + 5260 0012 002B cmp r3, #0 + 5261 0014 00D1 bne .LCB5192 + 5262 0016 EDE0 b .L291 @long jump + ARM GAS /tmp/ccrFaSdZ.s page 146 + + + 5263 .LCB5192: + 5264 .loc 1 2307 0 is_stmt 0 discriminator 1 + 5265 0018 4368 ldr r3, [r0, #4] + 5266 001a 002B cmp r3, #0 + 5267 001c 00D1 bne .LCB5196 + 5268 001e EBE0 b .L292 @long jump + 5269 .LCB5196: +2308:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( primitives->MacMcpsIndication == NULL ) || + 5270 .loc 1 2308 0 is_stmt 1 + 5271 0020 8368 ldr r3, [r0, #8] + 5272 0022 002B cmp r3, #0 + 5273 0024 00D1 bne .LCB5200 + 5274 0026 E9E0 b .L293 @long jump + 5275 .LCB5200: +2309:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( primitives->MacMlmeConfirm == NULL ) ) +2310:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +2312:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2313:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Verify if the region is supported +2314:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionIsActive( region ) == false ) + 5276 .loc 1 2314 0 + 5277 0028 1000 movs r0, r2 + 5278 .LVL444: + 5279 002a FFF7FEFF bl RegionIsActive + 5280 .LVL445: + 5281 002e 0028 cmp r0, #0 + 5282 0030 00D1 bne .LCB5208 + 5283 0032 E5E0 b .L294 @long jump + 5284 .LCB5208: +2315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_REGION_NOT_SUPPORTED; +2317:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2319:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacPrimitives = primitives; + 5285 .loc 1 2319 0 + 5286 0034 734B ldr r3, .L295 + 5287 0036 1C60 str r4, [r3] +2320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacCallbacks = callbacks; + 5288 .loc 1 2320 0 + 5289 0038 734B ldr r3, .L295+4 + 5290 003a 1E60 str r6, [r3] +2321:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacRegion = region; + 5291 .loc 1 2321 0 + 5292 003c 734E ldr r6, .L295+8 + 5293 .LVL446: + 5294 003e 3570 strb r5, [r6] +2322:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2323:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Value = 0; + 5295 .loc 1 2323 0 + 5296 0040 0023 movs r3, #0 + 5297 0042 734A ldr r2, .L295+12 + 5298 0044 1370 strb r3, [r2] +2324:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2325:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDeviceClass = CLASS_A; + 5299 .loc 1 2325 0 + 5300 0046 734A ldr r2, .L295+16 + 5301 0048 1370 strb r3, [r2] + ARM GAS /tmp/ccrFaSdZ.s page 147 + + +2326:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacState = LORAMAC_IDLE; + 5302 .loc 1 2326 0 + 5303 004a 734A ldr r2, .L295+20 + 5304 004c 1360 str r3, [r2] +2327:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2328:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** JoinRequestTrials = 0; + 5305 .loc 1 2328 0 + 5306 004e 734A ldr r2, .L295+24 + 5307 0050 1370 strb r3, [r2] +2329:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MaxJoinRequestTrials = 1; + 5308 .loc 1 2329 0 + 5309 0052 0127 movs r7, #1 + 5310 0054 724A ldr r2, .L295+28 + 5311 0056 1770 strb r7, [r2] +2330:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RepeaterSupport = false; + 5312 .loc 1 2330 0 + 5313 0058 724A ldr r2, .L295+32 + 5314 005a 1370 strb r3, [r2] +2331:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2332:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset duty cycle times +2333:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedLastTxDoneTime = 0; + 5315 .loc 1 2333 0 + 5316 005c 724A ldr r2, .L295+36 + 5317 005e 1360 str r3, [r2] +2334:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AggregatedTimeOff = 0; + 5318 .loc 1 2334 0 + 5319 0060 724A ldr r2, .L295+40 + 5320 0062 1360 str r3, [r2] +2335:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2336:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset to defaults +2337:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DUTY_CYCLE; + 5321 .loc 1 2337 0 + 5322 0064 01AC add r4, sp, #4 + 5323 .LVL447: + 5324 0066 0B33 adds r3, r3, #11 + 5325 0068 2370 strb r3, [r4] +2338:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5326 .loc 1 2338 0 + 5327 006a 2100 movs r1, r4 + 5328 006c 2800 movs r0, r5 + 5329 006e FFF7FEFF bl RegionGetPhyParam + 5330 .LVL448: +2339:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DutyCycleOn = ( bool ) phyParam.Value; + 5331 .loc 1 2339 0 + 5332 0072 431E subs r3, r0, #1 + 5333 0074 9841 sbcs r0, r0, r3 + 5334 .LVL449: + 5335 0076 6E4B ldr r3, .L295+44 + 5336 0078 1870 strb r0, [r3] +2340:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2341:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_TX_POWER; + 5337 .loc 1 2341 0 + 5338 007a 0823 movs r3, #8 + 5339 007c 2370 strb r3, [r4] +2342:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5340 .loc 1 2342 0 + 5341 007e 3078 ldrb r0, [r6] + ARM GAS /tmp/ccrFaSdZ.s page 148 + + + 5342 0080 2100 movs r1, r4 + 5343 0082 FFF7FEFF bl RegionGetPhyParam + 5344 .LVL450: +2343:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ChannelsTxPower = phyParam.Value; + 5345 .loc 1 2343 0 + 5346 0086 6B4D ldr r5, .L295+48 + 5347 0088 2870 strb r0, [r5] +2344:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2345:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_TX_DR; + 5348 .loc 1 2345 0 + 5349 008a 0523 movs r3, #5 + 5350 008c 2370 strb r3, [r4] +2346:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5351 .loc 1 2346 0 + 5352 008e 3078 ldrb r0, [r6] + 5353 0090 2100 movs r1, r4 + 5354 0092 FFF7FEFF bl RegionGetPhyParam + 5355 .LVL451: +2347:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ChannelsDatarate = phyParam.Value; + 5356 .loc 1 2347 0 + 5357 0096 6870 strb r0, [r5, #1] +2348:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2349:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_RX_WINDOW; + 5358 .loc 1 2349 0 + 5359 0098 0C23 movs r3, #12 + 5360 009a 2370 strb r3, [r4] +2350:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5361 .loc 1 2350 0 + 5362 009c 3078 ldrb r0, [r6] + 5363 009e 2100 movs r1, r4 + 5364 00a0 FFF7FEFF bl RegionGetPhyParam + 5365 .LVL452: +2351:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.MaxRxWindow = phyParam.Value; + 5366 .loc 1 2351 0 + 5367 00a4 E860 str r0, [r5, #12] +2352:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2353:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_RECEIVE_DELAY1; + 5368 .loc 1 2353 0 + 5369 00a6 0D23 movs r3, #13 + 5370 00a8 2370 strb r3, [r4] +2354:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5371 .loc 1 2354 0 + 5372 00aa 3078 ldrb r0, [r6] + 5373 .LVL453: + 5374 00ac 2100 movs r1, r4 + 5375 00ae FFF7FEFF bl RegionGetPhyParam + 5376 .LVL454: +2355:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ReceiveDelay1 = phyParam.Value; + 5377 .loc 1 2355 0 + 5378 00b2 2861 str r0, [r5, #16] +2356:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2357:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_RECEIVE_DELAY2; + 5379 .loc 1 2357 0 + 5380 00b4 0E23 movs r3, #14 + 5381 00b6 2370 strb r3, [r4] +2358:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5382 .loc 1 2358 0 + ARM GAS /tmp/ccrFaSdZ.s page 149 + + + 5383 00b8 3078 ldrb r0, [r6] + 5384 .LVL455: + 5385 00ba 2100 movs r1, r4 + 5386 00bc FFF7FEFF bl RegionGetPhyParam + 5387 .LVL456: +2359:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ReceiveDelay2 = phyParam.Value; + 5388 .loc 1 2359 0 + 5389 00c0 6861 str r0, [r5, #20] +2360:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2361:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_JOIN_ACCEPT_DELAY1; + 5390 .loc 1 2361 0 + 5391 00c2 0F23 movs r3, #15 + 5392 00c4 2370 strb r3, [r4] +2362:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5393 .loc 1 2362 0 + 5394 00c6 3078 ldrb r0, [r6] + 5395 .LVL457: + 5396 00c8 2100 movs r1, r4 + 5397 00ca FFF7FEFF bl RegionGetPhyParam + 5398 .LVL458: +2363:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.JoinAcceptDelay1 = phyParam.Value; + 5399 .loc 1 2363 0 + 5400 00ce A861 str r0, [r5, #24] +2364:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2365:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_JOIN_ACCEPT_DELAY2; + 5401 .loc 1 2365 0 + 5402 00d0 1023 movs r3, #16 + 5403 00d2 2370 strb r3, [r4] +2366:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5404 .loc 1 2366 0 + 5405 00d4 3078 ldrb r0, [r6] + 5406 .LVL459: + 5407 00d6 2100 movs r1, r4 + 5408 00d8 FFF7FEFF bl RegionGetPhyParam + 5409 .LVL460: +2367:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.JoinAcceptDelay2 = phyParam.Value; + 5410 .loc 1 2367 0 + 5411 00dc E861 str r0, [r5, #28] +2368:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2369:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_DR1_OFFSET; + 5412 .loc 1 2369 0 + 5413 00de 1323 movs r3, #19 + 5414 00e0 2370 strb r3, [r4] +2370:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5415 .loc 1 2370 0 + 5416 00e2 3078 ldrb r0, [r6] + 5417 .LVL461: + 5418 00e4 2100 movs r1, r4 + 5419 00e6 FFF7FEFF bl RegionGetPhyParam + 5420 .LVL462: +2371:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.Rx1DrOffset = phyParam.Value; + 5421 .loc 1 2371 0 + 5422 00ea 2123 movs r3, #33 + 5423 00ec E854 strb r0, [r5, r3] +2372:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2373:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_RX2_FREQUENCY; + 5424 .loc 1 2373 0 + ARM GAS /tmp/ccrFaSdZ.s page 150 + + + 5425 00ee 0D3B subs r3, r3, #13 + 5426 00f0 2370 strb r3, [r4] +2374:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5427 .loc 1 2374 0 + 5428 00f2 3078 ldrb r0, [r6] + 5429 00f4 2100 movs r1, r4 + 5430 00f6 FFF7FEFF bl RegionGetPhyParam + 5431 .LVL463: +2375:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.Rx2Channel.Frequency = phyParam.Value; + 5432 .loc 1 2375 0 + 5433 00fa 6862 str r0, [r5, #36] +2376:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2377:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_RX2_DR; + 5434 .loc 1 2377 0 + 5435 00fc 1523 movs r3, #21 + 5436 00fe 2370 strb r3, [r4] +2378:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5437 .loc 1 2378 0 + 5438 0100 3078 ldrb r0, [r6] + 5439 .LVL464: + 5440 0102 2100 movs r1, r4 + 5441 0104 FFF7FEFF bl RegionGetPhyParam + 5442 .LVL465: +2379:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.Rx2Channel.Datarate = phyParam.Value; + 5443 .loc 1 2379 0 + 5444 0108 2823 movs r3, #40 + 5445 010a E854 strb r0, [r5, r3] +2380:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2381:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_UPLINK_DWELL_TIME; + 5446 .loc 1 2381 0 + 5447 010c 0E3B subs r3, r3, #14 + 5448 010e 2370 strb r3, [r4] +2382:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5449 .loc 1 2382 0 + 5450 0110 3078 ldrb r0, [r6] + 5451 0112 2100 movs r1, r4 + 5452 0114 FFF7FEFF bl RegionGetPhyParam + 5453 .LVL466: +2383:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.UplinkDwellTime = phyParam.Value; + 5454 .loc 1 2383 0 + 5455 0118 2C23 movs r3, #44 + 5456 011a E854 strb r0, [r5, r3] +2384:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2385:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_DOWNLINK_DWELL_TIME; + 5457 .loc 1 2385 0 + 5458 011c 113B subs r3, r3, #17 + 5459 011e 2370 strb r3, [r4] +2386:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5460 .loc 1 2386 0 + 5461 0120 3078 ldrb r0, [r6] + 5462 0122 2100 movs r1, r4 + 5463 0124 FFF7FEFF bl RegionGetPhyParam + 5464 .LVL467: +2387:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.DownlinkDwellTime = phyParam.Value; + 5465 .loc 1 2387 0 + 5466 0128 2D23 movs r3, #45 + 5467 012a E854 strb r0, [r5, r3] + ARM GAS /tmp/ccrFaSdZ.s page 151 + + +2388:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2389:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_MAX_EIRP; + 5468 .loc 1 2389 0 + 5469 012c 113B subs r3, r3, #17 + 5470 012e 2370 strb r3, [r4] +2390:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5471 .loc 1 2390 0 + 5472 0130 3078 ldrb r0, [r6] + 5473 0132 2100 movs r1, r4 + 5474 0134 FFF7FEFF bl RegionGetPhyParam + 5475 .LVL468: +2391:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.MaxEirp = phyParam.fValue; + 5476 .loc 1 2391 0 + 5477 0138 2863 str r0, [r5, #48] +2392:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2393:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_ANTENNA_GAIN; + 5478 .loc 1 2393 0 + 5479 013a 1D23 movs r3, #29 + 5480 013c 2370 strb r3, [r4] +2394:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5481 .loc 1 2394 0 + 5482 013e 3078 ldrb r0, [r6] + 5483 0140 2100 movs r1, r4 + 5484 0142 FFF7FEFF bl RegionGetPhyParam + 5485 .LVL469: +2395:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.AntennaGain = phyParam.fValue; + 5486 .loc 1 2395 0 + 5487 0146 6863 str r0, [r5, #52] +2396:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2397:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionInitDefaults( LoRaMacRegion, INIT_TYPE_INIT ); + 5488 .loc 1 2397 0 + 5489 0148 3078 ldrb r0, [r6] + 5490 014a 0021 movs r1, #0 + 5491 014c FFF7FEFF bl RegionInitDefaults + 5492 .LVL470: +2398:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2399:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Init parameters which are not set in function ResetMacParameters +2400:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ChannelsNbRep = 1; + 5493 .loc 1 2400 0 + 5494 0150 2022 movs r2, #32 + 5495 0152 AF54 strb r7, [r5, r2] +2401:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.SystemMaxRxError = 10; + 5496 .loc 1 2401 0 + 5497 0154 0A20 movs r0, #10 + 5498 0156 6860 str r0, [r5, #4] +2402:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.MinRxSymbols = 6; + 5499 .loc 1 2402 0 + 5500 0158 0621 movs r1, #6 + 5501 015a 2972 strb r1, [r5, #8] +2403:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2404:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.SystemMaxRxError = LoRaMacParamsDefaults.SystemMaxRxError; + 5502 .loc 1 2404 0 + 5503 015c 364B ldr r3, .L295+52 + 5504 015e 5860 str r0, [r3, #4] +2405:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols = LoRaMacParamsDefaults.MinRxSymbols; + 5505 .loc 1 2405 0 + 5506 0160 1972 strb r1, [r3, #8] + ARM GAS /tmp/ccrFaSdZ.s page 152 + + +2406:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MaxRxWindow = LoRaMacParamsDefaults.MaxRxWindow; + 5507 .loc 1 2406 0 + 5508 0162 E968 ldr r1, [r5, #12] + 5509 0164 D960 str r1, [r3, #12] +2407:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 = LoRaMacParamsDefaults.ReceiveDelay1; + 5510 .loc 1 2407 0 + 5511 0166 2969 ldr r1, [r5, #16] + 5512 0168 1961 str r1, [r3, #16] +2408:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = LoRaMacParamsDefaults.ReceiveDelay2; + 5513 .loc 1 2408 0 + 5514 016a 6969 ldr r1, [r5, #20] + 5515 016c 5961 str r1, [r3, #20] +2409:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.JoinAcceptDelay1 = LoRaMacParamsDefaults.JoinAcceptDelay1; + 5516 .loc 1 2409 0 + 5517 016e A969 ldr r1, [r5, #24] + 5518 0170 9961 str r1, [r3, #24] +2410:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.JoinAcceptDelay2 = LoRaMacParamsDefaults.JoinAcceptDelay2; + 5519 .loc 1 2410 0 + 5520 0172 E969 ldr r1, [r5, #28] + 5521 0174 D961 str r1, [r3, #28] +2411:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsNbRep = LoRaMacParamsDefaults.ChannelsNbRep; + 5522 .loc 1 2411 0 + 5523 0176 9F54 strb r7, [r3, r2] +2412:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2413:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ResetMacParameters( ); + 5524 .loc 1 2413 0 + 5525 0178 FFF7FEFF bl ResetMacParameters + 5526 .LVL471: +2414:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2415:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Initialize timers +2416:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerInit( &MacStateCheckTimer, OnMacStateCheckTimerEvent ); + 5527 .loc 1 2416 0 + 5528 017c 2F4C ldr r4, .L295+56 + 5529 017e 3049 ldr r1, .L295+60 + 5530 0180 2000 movs r0, r4 + 5531 0182 FFF7FEFF bl TimerInit + 5532 .LVL472: +2417:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + 5533 .loc 1 2417 0 + 5534 0186 FA21 movs r1, #250 + 5535 0188 8900 lsls r1, r1, #2 + 5536 018a 2000 movs r0, r4 + 5537 018c FFF7FEFF bl TimerSetValue + 5538 .LVL473: +2418:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2419:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerInit( &TxDelayedTimer, OnTxDelayedTimerEvent ); + 5539 .loc 1 2419 0 + 5540 0190 2C49 ldr r1, .L295+64 + 5541 0192 2D48 ldr r0, .L295+68 + 5542 0194 FFF7FEFF bl TimerInit + 5543 .LVL474: +2420:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerInit( &RxWindowTimer1, OnRxWindow1TimerEvent ); + 5544 .loc 1 2420 0 + 5545 0198 2C49 ldr r1, .L295+72 + 5546 019a 2D48 ldr r0, .L295+76 + 5547 019c FFF7FEFF bl TimerInit + 5548 .LVL475: + ARM GAS /tmp/ccrFaSdZ.s page 153 + + +2421:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerInit( &RxWindowTimer2, OnRxWindow2TimerEvent ); + 5549 .loc 1 2421 0 + 5550 01a0 2C49 ldr r1, .L295+80 + 5551 01a2 2D48 ldr r0, .L295+84 + 5552 01a4 FFF7FEFF bl TimerInit + 5553 .LVL476: +2422:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** TimerInit( &AckTimeoutTimer, OnAckTimeoutTimerEvent ); + 5554 .loc 1 2422 0 + 5555 01a8 2C49 ldr r1, .L295+88 + 5556 01aa 2D48 ldr r0, .L295+92 + 5557 01ac FFF7FEFF bl TimerInit + 5558 .LVL477: +2423:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2424:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Store the current initialization time +2425:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacInitializationTime = TimerGetCurrentTime( ); + 5559 .loc 1 2425 0 + 5560 01b0 FFF7FEFF bl TimerGetCurrentTime + 5561 .LVL478: + 5562 01b4 2B4B ldr r3, .L295+96 + 5563 01b6 1860 str r0, [r3] +2426:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2427:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Initialize Radio driver +2428:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RadioEvents.TxDone = OnRadioTxDone; + 5564 .loc 1 2428 0 + 5565 01b8 2B48 ldr r0, .L295+100 + 5566 01ba 2C4B ldr r3, .L295+104 + 5567 01bc 0360 str r3, [r0] +2429:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RadioEvents.RxDone = OnRadioRxDone; + 5568 .loc 1 2429 0 + 5569 01be 2C4B ldr r3, .L295+108 + 5570 01c0 8360 str r3, [r0, #8] +2430:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RadioEvents.RxError = OnRadioRxError; + 5571 .loc 1 2430 0 + 5572 01c2 2C4B ldr r3, .L295+112 + 5573 01c4 0361 str r3, [r0, #16] +2431:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RadioEvents.TxTimeout = OnRadioTxTimeout; + 5574 .loc 1 2431 0 + 5575 01c6 2C4B ldr r3, .L295+116 + 5576 01c8 4360 str r3, [r0, #4] +2432:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RadioEvents.RxTimeout = OnRadioRxTimeout; + 5577 .loc 1 2432 0 + 5578 01ca 2C4B ldr r3, .L295+120 + 5579 01cc C360 str r3, [r0, #12] +2433:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Init( &RadioEvents ); + 5580 .loc 1 2433 0 + 5581 01ce 2C4C ldr r4, .L295+124 + 5582 01d0 A368 ldr r3, [r4, #8] + 5583 01d2 9847 blx r3 + 5584 .LVL479: +2434:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2435:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Random seed initialization +2436:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** srand1( Radio.Random( ) ); + 5585 .loc 1 2436 0 + 5586 01d4 E369 ldr r3, [r4, #28] + 5587 01d6 9847 blx r3 + 5588 .LVL480: + 5589 01d8 FFF7FEFF bl srand1 + ARM GAS /tmp/ccrFaSdZ.s page 154 + + + 5590 .LVL481: +2437:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2438:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PublicNetwork = true; + 5591 .loc 1 2438 0 + 5592 01dc 294B ldr r3, .L295+128 + 5593 01de 1F70 strb r7, [r3] +2439:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.SetPublicNetwork( PublicNetwork ); + 5594 .loc 1 2439 0 + 5595 01e0 0120 movs r0, #1 + 5596 01e2 236E ldr r3, [r4, #96] + 5597 01e4 9847 blx r3 + 5598 .LVL482: +2440:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); + 5599 .loc 1 2440 0 + 5600 01e6 636B ldr r3, [r4, #52] + 5601 01e8 9847 blx r3 + 5602 .LVL483: +2441:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2442:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 5603 .loc 1 2442 0 + 5604 01ea 0020 movs r0, #0 + 5605 .L289: +2443:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5606 .loc 1 2443 0 + 5607 01ec 03B0 add sp, sp, #12 + 5608 @ sp needed + 5609 01ee F0BD pop {r4, r5, r6, r7, pc} + 5610 .LVL484: + 5611 .L290: +2304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5612 .loc 1 2304 0 + 5613 01f0 0320 movs r0, #3 + 5614 .LVL485: + 5615 01f2 FBE7 b .L289 + 5616 .LVL486: + 5617 .L291: +2311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5618 .loc 1 2311 0 + 5619 01f4 0320 movs r0, #3 + 5620 .LVL487: + 5621 01f6 F9E7 b .L289 + 5622 .LVL488: + 5623 .L292: + 5624 01f8 0320 movs r0, #3 + 5625 .LVL489: + 5626 01fa F7E7 b .L289 + 5627 .LVL490: + 5628 .L293: + 5629 01fc 0320 movs r0, #3 + 5630 .LVL491: + 5631 01fe F5E7 b .L289 + 5632 .LVL492: + 5633 .L294: +2316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5634 .loc 1 2316 0 + 5635 0200 0A20 movs r0, #10 + 5636 0202 F3E7 b .L289 + ARM GAS /tmp/ccrFaSdZ.s page 155 + + + 5637 .L296: + 5638 .align 2 + 5639 .L295: + 5640 0204 00000000 .word .LANCHOR61 + 5641 0208 00000000 .word .LANCHOR30 + 5642 020c 00000000 .word .LANCHOR22 + 5643 0210 00000000 .word .LANCHOR26 + 5644 0214 00000000 .word .LANCHOR25 + 5645 0218 00000000 .word .LANCHOR24 + 5646 021c 00000000 .word .LANCHOR54 + 5647 0220 00000000 .word .LANCHOR59 + 5648 0224 00000000 .word .LANCHOR21 + 5649 0228 00000000 .word .LANCHOR43 + 5650 022c 00000000 .word .LANCHOR55 + 5651 0230 00000000 .word .LANCHOR56 + 5652 0234 00000000 .word .LANCHOR13 + 5653 0238 00000000 .word .LANCHOR14 + 5654 023c 00000000 .word .LANCHOR27 + 5655 0240 00000000 .word OnMacStateCheckTimerEvent + 5656 0244 00000000 .word OnTxDelayedTimerEvent + 5657 0248 00000000 .word .LANCHOR58 + 5658 024c 00000000 .word OnRxWindow1TimerEvent + 5659 0250 00000000 .word .LANCHOR46 + 5660 0254 00000000 .word OnRxWindow2TimerEvent + 5661 0258 00000000 .word .LANCHOR37 + 5662 025c 00000000 .word OnAckTimeoutTimerEvent + 5663 0260 00000000 .word .LANCHOR23 + 5664 0264 00000000 .word .LANCHOR57 + 5665 0268 00000000 .word .LANCHOR62 + 5666 026c 00000000 .word OnRadioTxDone + 5667 0270 00000000 .word OnRadioRxDone + 5668 0274 00000000 .word OnRadioRxError + 5669 0278 00000000 .word OnRadioTxTimeout + 5670 027c 00000000 .word OnRadioRxTimeout + 5671 0280 00000000 .word Radio + 5672 0284 00000000 .word .LANCHOR63 + 5673 .cfi_endproc + 5674 .LFE109: + 5676 .section .text.LoRaMacQueryTxPossible,"ax",%progbits + 5677 .align 1 + 5678 .global LoRaMacQueryTxPossible + 5679 .syntax unified + 5680 .code 16 + 5681 .thumb_func + 5682 .fpu softvfp + 5684 LoRaMacQueryTxPossible: + 5685 .LFB110: +2444:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2445:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacQueryTxPossible( uint8_t size, LoRaMacTxInfo_t* txInfo ) +2446:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5686 .loc 1 2446 0 + 5687 .cfi_startproc + 5688 @ args = 0, pretend = 0, frame = 32 + 5689 @ frame_needed = 0, uses_anonymous_args = 0 + 5690 .LVL493: + 5691 0000 F0B5 push {r4, r5, r6, r7, lr} + 5692 .LCFI36: + ARM GAS /tmp/ccrFaSdZ.s page 156 + + + 5693 .cfi_def_cfa_offset 20 + 5694 .cfi_offset 4, -20 + 5695 .cfi_offset 5, -16 + 5696 .cfi_offset 6, -12 + 5697 .cfi_offset 7, -8 + 5698 .cfi_offset 14, -4 + 5699 0002 CE46 mov lr, r9 + 5700 0004 00B5 push {lr} + 5701 .LCFI37: + 5702 .cfi_def_cfa_offset 24 + 5703 .cfi_offset 9, -24 + 5704 0006 8AB0 sub sp, sp, #40 + 5705 .LCFI38: + 5706 .cfi_def_cfa_offset 64 + 5707 0008 0390 str r0, [sp, #12] + 5708 000a 0E00 movs r6, r1 +2447:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrNextParams_t adrNext; +2448:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +2449:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +2450:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t datarate = LoRaMacParamsDefaults.ChannelsDatarate; + 5709 .loc 1 2450 0 + 5710 000c 344B ldr r3, .L305 + 5711 000e 0121 movs r1, #1 + 5712 .LVL494: + 5713 0010 5956 ldrsb r1, [r3, r1] + 5714 0012 0F22 movs r2, #15 + 5715 0014 02A8 add r0, sp, #8 + 5716 .LVL495: + 5717 0016 8446 mov ip, r0 + 5718 0018 6244 add r2, r2, ip + 5719 001a 1170 strb r1, [r2] +2451:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t txPower = LoRaMacParamsDefaults.ChannelsTxPower; + 5720 .loc 1 2451 0 + 5721 001c 0022 movs r2, #0 + 5722 001e 9A56 ldrsb r2, [r3, r2] + 5723 0020 0E23 movs r3, #14 + 5724 0022 6344 add r3, r3, ip + 5725 0024 1A70 strb r2, [r3] +2452:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t fOptLen = MacCommandsBufferIndex + MacCommandsBufferToRepeatIndex; + 5726 .loc 1 2452 0 + 5727 0026 2F4B ldr r3, .L305+4 + 5728 0028 1C78 ldrb r4, [r3] + 5729 002a 2F4B ldr r3, .L305+8 + 5730 002c 1B78 ldrb r3, [r3] + 5731 002e E418 adds r4, r4, r3 + 5732 0030 E4B2 uxtb r4, r4 + 5733 .LVL496: +2453:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2454:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( txInfo == NULL ) + 5734 .loc 1 2454 0 + 5735 0032 002E cmp r6, #0 + 5736 0034 52D0 beq .L302 +2455:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2456:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +2457:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2458:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2459:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Setup ADR request + ARM GAS /tmp/ccrFaSdZ.s page 157 + + +2460:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.UpdateChanMask = false; + 5737 .loc 1 2460 0 + 5738 0036 07A9 add r1, sp, #28 + 5739 0038 0023 movs r3, #0 + 5740 003a 0B70 strb r3, [r1] +2461:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrEnabled = AdrCtrlOn; + 5741 .loc 1 2461 0 + 5742 003c 2B4B ldr r3, .L305+12 + 5743 003e 1B78 ldrb r3, [r3] + 5744 0040 4B70 strb r3, [r1, #1] +2462:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.AdrAckCounter = AdrAckCounter; + 5745 .loc 1 2462 0 + 5746 0042 2B4B ldr r3, .L305+16 + 5747 0044 1A68 ldr r2, [r3] + 5748 0046 4A60 str r2, [r1, #4] +2463:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.Datarate = LoRaMacParams.ChannelsDatarate; + 5749 .loc 1 2463 0 + 5750 0048 2A4F ldr r7, .L305+20 + 5751 004a 0122 movs r2, #1 + 5752 004c BA56 ldrsb r2, [r7, r2] + 5753 004e 0A72 strb r2, [r1, #8] +2464:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.TxPower = LoRaMacParams.ChannelsTxPower; + 5754 .loc 1 2464 0 + 5755 0050 0022 movs r2, #0 + 5756 0052 BA56 ldrsb r2, [r7, r2] + 5757 0054 4A72 strb r2, [r1, #9] +2465:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** adrNext.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 5758 .loc 1 2465 0 + 5759 0056 2C22 movs r2, #44 + 5760 0058 9146 mov r9, r2 + 5761 005a BA5C ldrb r2, [r7, r2] + 5762 005c 8A72 strb r2, [r1, #10] +2466:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2467:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // We call the function for information purposes only. We don't want to +2468:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // apply the datarate, the tx power and the ADR ack counter. +2469:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionAdrNext( LoRaMacRegion, &adrNext, &datarate, &txPower, &AdrAckCounter ); + 5763 .loc 1 2469 0 + 5764 005e 0F25 movs r5, #15 + 5765 0060 6544 add r5, r5, ip + 5766 0062 254A ldr r2, .L305+24 + 5767 0064 1078 ldrb r0, [r2] + 5768 0066 0093 str r3, [sp] + 5769 0068 0E23 movs r3, #14 + 5770 006a 6344 add r3, r3, ip + 5771 006c 2A00 movs r2, r5 + 5772 006e FFF7FEFF bl RegionAdrNext + 5773 .LVL497: +2470:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2471:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Setup PHY request +2472:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 5774 .loc 1 2472 0 + 5775 0072 4B46 mov r3, r9 + 5776 0074 FA5C ldrb r2, [r7, r3] + 5777 0076 06AB add r3, sp, #24 + 5778 0078 9A70 strb r2, [r3, #2] +2473:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Datarate = datarate; + 5779 .loc 1 2473 0 + ARM GAS /tmp/ccrFaSdZ.s page 158 + + + 5780 007a 2A78 ldrb r2, [r5] + 5781 007c 5A70 strb r2, [r3, #1] +2474:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD; + 5782 .loc 1 2474 0 + 5783 007e 0922 movs r2, #9 + 5784 0080 1A70 strb r2, [r3] +2475:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2476:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Change request in case repeater is supported +2477:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RepeaterSupport == true ) + 5785 .loc 1 2477 0 + 5786 0082 1E4B ldr r3, .L305+28 + 5787 0084 1B78 ldrb r3, [r3] + 5788 0086 002B cmp r3, #0 + 5789 0088 02D0 beq .L299 +2478:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2479:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; + 5790 .loc 1 2479 0 + 5791 008a 06AB add r3, sp, #24 + 5792 008c 0132 adds r2, r2, #1 + 5793 008e 1A70 strb r2, [r3] + 5794 .L299: +2480:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2481:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 5795 .loc 1 2481 0 + 5796 0090 194B ldr r3, .L305+24 + 5797 0092 1878 ldrb r0, [r3] + 5798 0094 06A9 add r1, sp, #24 + 5799 0096 FFF7FEFF bl RegionGetPhyParam + 5800 .LVL498: +2482:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txInfo->CurrentPayloadSize = phyParam.Value; + 5801 .loc 1 2482 0 + 5802 009a C0B2 uxtb r0, r0 + 5803 009c 7070 strb r0, [r6, #1] +2483:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2484:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Verify if the fOpts fit into the maximum payload +2485:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( txInfo->CurrentPayloadSize >= fOptLen ) + 5804 .loc 1 2485 0 + 5805 009e A042 cmp r0, r4 + 5806 00a0 12D3 bcc .L300 +2486:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2487:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txInfo->MaxPossiblePayload = txInfo->CurrentPayloadSize - fOptLen; + 5807 .loc 1 2487 0 + 5808 00a2 001B subs r0, r0, r4 + 5809 00a4 3070 strb r0, [r6] + 5810 .LVL499: + 5811 .L301: +2488:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2489:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2490:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2491:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** txInfo->MaxPossiblePayload = txInfo->CurrentPayloadSize; +2492:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // The fOpts don't fit into the maximum payload. Omit the MAC commands to +2493:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // ensure that another uplink is possible. +2494:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fOptLen = 0; +2495:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; +2496:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = 0; +2497:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2498:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 159 + + +2499:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Verify if the fOpts and the payload fit into the maximum payload +2500:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ValidatePayloadLength( size, datarate, fOptLen ) == false ) + 5812 .loc 1 2500 0 + 5813 00a6 0F23 movs r3, #15 + 5814 00a8 02AA add r2, sp, #8 + 5815 00aa 9446 mov ip, r2 + 5816 00ac 6344 add r3, r3, ip + 5817 00ae 0021 movs r1, #0 + 5818 00b0 5956 ldrsb r1, [r3, r1] + 5819 00b2 2200 movs r2, r4 + 5820 00b4 0398 ldr r0, [sp, #12] + 5821 00b6 FFF7FEFF bl ValidatePayloadLength + 5822 .LVL500: + 5823 00ba 0028 cmp r0, #0 + 5824 00bc 0CD0 beq .L304 +2501:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2502:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_LENGTH_ERROR; +2503:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2504:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 5825 .loc 1 2504 0 + 5826 00be 0020 movs r0, #0 + 5827 .L298: +2505:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5828 .loc 1 2505 0 + 5829 00c0 0AB0 add sp, sp, #40 + 5830 @ sp needed + 5831 .LVL501: + 5832 .LVL502: + 5833 00c2 04BC pop {r2} + 5834 00c4 9146 mov r9, r2 + 5835 00c6 F0BD pop {r4, r5, r6, r7, pc} + 5836 .LVL503: + 5837 .L300: +2491:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // The fOpts don't fit into the maximum payload. Omit the MAC commands to + 5838 .loc 1 2491 0 + 5839 00c8 3070 strb r0, [r6] + 5840 .LVL504: +2495:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferToRepeatIndex = 0; + 5841 .loc 1 2495 0 + 5842 00ca 0023 movs r3, #0 + 5843 00cc 054A ldr r2, .L305+4 + 5844 00ce 1370 strb r3, [r2] +2496:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5845 .loc 1 2496 0 + 5846 00d0 054A ldr r2, .L305+8 + 5847 00d2 1370 strb r3, [r2] +2494:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MacCommandsBufferIndex = 0; + 5848 .loc 1 2494 0 + 5849 00d4 0024 movs r4, #0 + 5850 00d6 E6E7 b .L301 + 5851 .LVL505: + 5852 .L304: +2502:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5853 .loc 1 2502 0 + 5854 00d8 0830 adds r0, r0, #8 + 5855 00da F1E7 b .L298 + 5856 .L302: + ARM GAS /tmp/ccrFaSdZ.s page 160 + + +2456:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 5857 .loc 1 2456 0 + 5858 00dc 0320 movs r0, #3 + 5859 00de EFE7 b .L298 + 5860 .L306: + 5861 .align 2 + 5862 .L305: + 5863 00e0 00000000 .word .LANCHOR13 + 5864 00e4 00000000 .word .LANCHOR10 + 5865 00e8 00000000 .word .LANCHOR11 + 5866 00ec 00000000 .word .LANCHOR29 + 5867 00f0 00000000 .word .LANCHOR3 + 5868 00f4 00000000 .word .LANCHOR14 + 5869 00f8 00000000 .word .LANCHOR22 + 5870 00fc 00000000 .word .LANCHOR21 + 5871 .cfi_endproc + 5872 .LFE110: + 5874 .section .text.LoRaMacMibGetRequestConfirm,"ax",%progbits + 5875 .align 1 + 5876 .global LoRaMacMibGetRequestConfirm + 5877 .syntax unified + 5878 .code 16 + 5879 .thumb_func + 5880 .fpu softvfp + 5882 LoRaMacMibGetRequestConfirm: + 5883 .LFB111: +2506:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2507:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMibGetRequestConfirm( MibRequestConfirm_t *mibGet ) +2508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 5884 .loc 1 2508 0 + 5885 .cfi_startproc + 5886 @ args = 0, pretend = 0, frame = 8 + 5887 @ frame_needed = 0, uses_anonymous_args = 0 + 5888 .LVL506: + 5889 0000 10B5 push {r4, lr} + 5890 .LCFI39: + 5891 .cfi_def_cfa_offset 8 + 5892 .cfi_offset 4, -8 + 5893 .cfi_offset 14, -4 + 5894 0002 82B0 sub sp, sp, #8 + 5895 .LCFI40: + 5896 .cfi_def_cfa_offset 16 + 5897 0004 041E subs r4, r0, #0 + 5898 .LVL507: +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_OK; +2510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +2511:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +2512:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2513:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mibGet == NULL ) + 5899 .loc 1 2513 0 + 5900 0006 00D1 bne .LCB5764 + 5901 0008 B3E0 b .L340 @long jump + 5902 .LCB5764: +2514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2515:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +2516:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2517:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 161 + + +2518:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( mibGet->Type ) + 5903 .loc 1 2518 0 + 5904 000a 0378 ldrb r3, [r0] + 5905 000c 1D2B cmp r3, #29 + 5906 000e 00D9 bls .LCB5767 + 5907 0010 B2E0 b .L341 @long jump + 5908 .LCB5767: + 5909 0012 9B00 lsls r3, r3, #2 + 5910 0014 594A ldr r2, .L342 + 5911 0016 D358 ldr r3, [r2, r3] + 5912 0018 9F46 mov pc, r3 + 5913 .section .rodata.LoRaMacMibGetRequestConfirm,"a",%progbits + 5914 .align 2 + 5915 .L310: + 5916 0000 1A000000 .word .L309 + 5917 0004 24000000 .word .L311 + 5918 0008 2E000000 .word .L312 + 5919 000c 38000000 .word .L313 + 5920 0010 42000000 .word .L314 + 5921 0014 4C000000 .word .L315 + 5922 0018 54000000 .word .L316 + 5923 001c 5C000000 .word .L317 + 5924 0020 66000000 .word .L318 + 5925 0024 70000000 .word .L319 + 5926 0028 84000000 .word .L320 + 5927 002c 92000000 .word .L321 + 5928 0030 B4000000 .word .L322 + 5929 0034 A0000000 .word .L323 + 5930 0038 C8000000 .word .L324 + 5931 003c D4000000 .word .L325 + 5932 0040 DE000000 .word .L326 + 5933 0044 E8000000 .word .L327 + 5934 0048 F2000000 .word .L328 + 5935 004c FC000000 .word .L329 + 5936 0050 06010000 .word .L330 + 5937 0054 12010000 .word .L331 + 5938 0058 2A010000 .word .L332 + 5939 005c 1E010000 .word .L333 + 5940 0060 36010000 .word .L334 + 5941 0064 40010000 .word .L335 + 5942 0068 4A010000 .word .L336 + 5943 006c 54010000 .word .L337 + 5944 0070 5E010000 .word .L338 + 5945 0074 68010000 .word .L339 + 5946 .section .text.LoRaMacMibGetRequestConfirm + 5947 .L309: +2519:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2520:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DEVICE_CLASS: +2521:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2522:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.Class = LoRaMacDeviceClass; + 5948 .loc 1 2522 0 + 5949 001a 594B ldr r3, .L342+4 + 5950 001c 1B78 ldrb r3, [r3] + 5951 001e 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 5952 .loc 1 2509 0 + 5953 0020 0020 movs r0, #0 + ARM GAS /tmp/ccrFaSdZ.s page 162 + + + 5954 .LVL508: +2523:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 5955 .loc 1 2523 0 + 5956 0022 A7E0 b .L308 + 5957 .LVL509: + 5958 .L311: +2524:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2525:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NETWORK_JOINED: +2526:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2527:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.IsNetworkJoined = IsLoRaMacNetworkJoined; + 5959 .loc 1 2527 0 + 5960 0024 574B ldr r3, .L342+8 + 5961 0026 1B78 ldrb r3, [r3] + 5962 0028 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 5963 .loc 1 2509 0 + 5964 002a 0020 movs r0, #0 + 5965 .LVL510: +2528:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 5966 .loc 1 2528 0 + 5967 002c A2E0 b .L308 + 5968 .LVL511: + 5969 .L312: +2529:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2530:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_ADR: +2531:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2532:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.AdrEnable = AdrCtrlOn; + 5970 .loc 1 2532 0 + 5971 002e 564B ldr r3, .L342+12 + 5972 0030 1B78 ldrb r3, [r3] + 5973 0032 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 5974 .loc 1 2509 0 + 5975 0034 0020 movs r0, #0 + 5976 .LVL512: +2533:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 5977 .loc 1 2533 0 + 5978 0036 9DE0 b .L308 + 5979 .LVL513: + 5980 .L313: +2534:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2535:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NET_ID: +2536:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2537:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.NetID = LoRaMacNetID; + 5981 .loc 1 2537 0 + 5982 0038 544B ldr r3, .L342+16 + 5983 003a 1B68 ldr r3, [r3] + 5984 003c 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 5985 .loc 1 2509 0 + 5986 003e 0020 movs r0, #0 + 5987 .LVL514: +2538:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 5988 .loc 1 2538 0 + 5989 0040 98E0 b .L308 + 5990 .LVL515: + 5991 .L314: + ARM GAS /tmp/ccrFaSdZ.s page 163 + + +2539:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2540:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DEV_ADDR: +2541:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2542:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.DevAddr = LoRaMacDevAddr; + 5992 .loc 1 2542 0 + 5993 0042 534B ldr r3, .L342+20 + 5994 0044 1B68 ldr r3, [r3] + 5995 0046 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 5996 .loc 1 2509 0 + 5997 0048 0020 movs r0, #0 + 5998 .LVL516: +2543:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 5999 .loc 1 2543 0 + 6000 004a 93E0 b .L308 + 6001 .LVL517: + 6002 .L315: +2544:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2545:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NWK_SKEY: +2546:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2547:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.NwkSKey = LoRaMacNwkSKey; + 6003 .loc 1 2547 0 + 6004 004c 514B ldr r3, .L342+24 + 6005 004e 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6006 .loc 1 2509 0 + 6007 0050 0020 movs r0, #0 + 6008 .LVL518: +2548:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6009 .loc 1 2548 0 + 6010 0052 8FE0 b .L308 + 6011 .LVL519: + 6012 .L316: +2549:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2550:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_APP_SKEY: +2551:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2552:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.AppSKey = LoRaMacAppSKey; + 6013 .loc 1 2552 0 + 6014 0054 504B ldr r3, .L342+28 + 6015 0056 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6016 .loc 1 2509 0 + 6017 0058 0020 movs r0, #0 + 6018 .LVL520: +2553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6019 .loc 1 2553 0 + 6020 005a 8BE0 b .L308 + 6021 .LVL521: + 6022 .L317: +2554:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2555:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_PUBLIC_NETWORK: +2556:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2557:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.EnablePublicNetwork = PublicNetwork; + 6023 .loc 1 2557 0 + 6024 005c 4F4B ldr r3, .L342+32 + 6025 005e 1B78 ldrb r3, [r3] + 6026 0060 0371 strb r3, [r0, #4] + ARM GAS /tmp/ccrFaSdZ.s page 164 + + +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6027 .loc 1 2509 0 + 6028 0062 0020 movs r0, #0 + 6029 .LVL522: +2558:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6030 .loc 1 2558 0 + 6031 0064 86E0 b .L308 + 6032 .LVL523: + 6033 .L318: +2559:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2560:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_REPEATER_SUPPORT: +2561:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2562:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.EnableRepeaterSupport = RepeaterSupport; + 6034 .loc 1 2562 0 + 6035 0066 4E4B ldr r3, .L342+36 + 6036 0068 1B78 ldrb r3, [r3] + 6037 006a 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6038 .loc 1 2509 0 + 6039 006c 0020 movs r0, #0 + 6040 .LVL524: +2563:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6041 .loc 1 2563 0 + 6042 006e 81E0 b .L308 + 6043 .LVL525: + 6044 .L319: +2564:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2565:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS: +2566:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2567:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_CHANNELS; + 6045 .loc 1 2567 0 + 6046 0070 01A9 add r1, sp, #4 + 6047 0072 1923 movs r3, #25 + 6048 0074 0B70 strb r3, [r1] +2568:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 6049 .loc 1 2568 0 + 6050 0076 4B4B ldr r3, .L342+40 + 6051 0078 1878 ldrb r0, [r3] + 6052 .LVL526: + 6053 007a FFF7FEFF bl RegionGetPhyParam + 6054 .LVL527: +2569:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2570:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelList = phyParam.Channels; + 6055 .loc 1 2570 0 + 6056 007e 6060 str r0, [r4, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6057 .loc 1 2509 0 + 6058 0080 0020 movs r0, #0 + 6059 .LVL528: +2571:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6060 .loc 1 2571 0 + 6061 0082 77E0 b .L308 + 6062 .LVL529: + 6063 .L320: +2572:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2573:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RX2_CHANNEL: +2574:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 165 + + +2575:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.Rx2Channel = LoRaMacParams.Rx2Channel; + 6064 .loc 1 2575 0 + 6065 0084 0434 adds r4, r4, #4 + 6066 0086 484B ldr r3, .L342+44 + 6067 0088 2433 adds r3, r3, #36 + 6068 008a 06CB ldmia r3!, {r1, r2} + 6069 008c 06C4 stmia r4!, {r1, r2} +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6070 .loc 1 2509 0 + 6071 008e 0020 movs r0, #0 + 6072 .LVL530: +2576:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6073 .loc 1 2576 0 + 6074 0090 70E0 b .L308 + 6075 .LVL531: + 6076 .L321: +2577:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2578:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RX2_DEFAULT_CHANNEL: +2579:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2580:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.Rx2Channel = LoRaMacParamsDefaults.Rx2Channel; + 6077 .loc 1 2580 0 + 6078 0092 0434 adds r4, r4, #4 + 6079 0094 454B ldr r3, .L342+48 + 6080 0096 2433 adds r3, r3, #36 + 6081 0098 06CB ldmia r3!, {r1, r2} + 6082 009a 06C4 stmia r4!, {r1, r2} +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6083 .loc 1 2509 0 + 6084 009c 0020 movs r0, #0 + 6085 .LVL532: +2581:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6086 .loc 1 2581 0 + 6087 009e 69E0 b .L308 + 6088 .LVL533: + 6089 .L323: +2582:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2583:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_MASK: +2584:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2585:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_CHANNELS_DEFAULT_MASK; + 6090 .loc 1 2585 0 + 6091 00a0 01A9 add r1, sp, #4 + 6092 00a2 1723 movs r3, #23 + 6093 00a4 0B70 strb r3, [r1] +2586:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 6094 .loc 1 2586 0 + 6095 00a6 3F4B ldr r3, .L342+40 + 6096 00a8 1878 ldrb r0, [r3] + 6097 .LVL534: + 6098 00aa FFF7FEFF bl RegionGetPhyParam + 6099 .LVL535: +2587:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2588:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsDefaultMask = phyParam.ChannelsMask; + 6100 .loc 1 2588 0 + 6101 00ae 6060 str r0, [r4, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6102 .loc 1 2509 0 + 6103 00b0 0020 movs r0, #0 + ARM GAS /tmp/ccrFaSdZ.s page 166 + + + 6104 .LVL536: +2589:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6105 .loc 1 2589 0 + 6106 00b2 5FE0 b .L308 + 6107 .LVL537: + 6108 .L322: +2590:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2591:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_MASK: +2592:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2593:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_CHANNELS_MASK; + 6109 .loc 1 2593 0 + 6110 00b4 01A9 add r1, sp, #4 + 6111 00b6 1623 movs r3, #22 + 6112 00b8 0B70 strb r3, [r1] +2594:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 6113 .loc 1 2594 0 + 6114 00ba 3A4B ldr r3, .L342+40 + 6115 00bc 1878 ldrb r0, [r3] + 6116 .LVL538: + 6117 00be FFF7FEFF bl RegionGetPhyParam + 6118 .LVL539: +2595:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2596:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsMask = phyParam.ChannelsMask; + 6119 .loc 1 2596 0 + 6120 00c2 6060 str r0, [r4, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6121 .loc 1 2509 0 + 6122 00c4 0020 movs r0, #0 + 6123 .LVL540: +2597:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6124 .loc 1 2597 0 + 6125 00c6 55E0 b .L308 + 6126 .LVL541: + 6127 .L324: +2598:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2599:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_NB_REP: +2600:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2601:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelNbRep = LoRaMacParams.ChannelsNbRep; + 6128 .loc 1 2601 0 + 6129 00c8 374A ldr r2, .L342+44 + 6130 00ca 2023 movs r3, #32 + 6131 00cc D35C ldrb r3, [r2, r3] + 6132 00ce 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6133 .loc 1 2509 0 + 6134 00d0 0020 movs r0, #0 + 6135 .LVL542: +2602:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6136 .loc 1 2602 0 + 6137 00d2 4FE0 b .L308 + 6138 .LVL543: + 6139 .L325: +2603:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2604:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_MAX_RX_WINDOW_DURATION: +2605:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2606:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.MaxRxWindow = LoRaMacParams.MaxRxWindow; + 6140 .loc 1 2606 0 + ARM GAS /tmp/ccrFaSdZ.s page 167 + + + 6141 00d4 344B ldr r3, .L342+44 + 6142 00d6 DB68 ldr r3, [r3, #12] + 6143 00d8 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6144 .loc 1 2509 0 + 6145 00da 0020 movs r0, #0 + 6146 .LVL544: +2607:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6147 .loc 1 2607 0 + 6148 00dc 4AE0 b .L308 + 6149 .LVL545: + 6150 .L326: +2608:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2609:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RECEIVE_DELAY_1: +2610:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2611:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ReceiveDelay1 = LoRaMacParams.ReceiveDelay1; + 6151 .loc 1 2611 0 + 6152 00de 324B ldr r3, .L342+44 + 6153 00e0 1B69 ldr r3, [r3, #16] + 6154 00e2 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6155 .loc 1 2509 0 + 6156 00e4 0020 movs r0, #0 + 6157 .LVL546: +2612:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6158 .loc 1 2612 0 + 6159 00e6 45E0 b .L308 + 6160 .LVL547: + 6161 .L327: +2613:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2614:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RECEIVE_DELAY_2: +2615:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2616:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ReceiveDelay2 = LoRaMacParams.ReceiveDelay2; + 6162 .loc 1 2616 0 + 6163 00e8 2F4B ldr r3, .L342+44 + 6164 00ea 5B69 ldr r3, [r3, #20] + 6165 00ec 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6166 .loc 1 2509 0 + 6167 00ee 0020 movs r0, #0 + 6168 .LVL548: +2617:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6169 .loc 1 2617 0 + 6170 00f0 40E0 b .L308 + 6171 .LVL549: + 6172 .L328: +2618:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2619:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_JOIN_ACCEPT_DELAY_1: +2620:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2621:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.JoinAcceptDelay1 = LoRaMacParams.JoinAcceptDelay1; + 6173 .loc 1 2621 0 + 6174 00f2 2D4B ldr r3, .L342+44 + 6175 00f4 9B69 ldr r3, [r3, #24] + 6176 00f6 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6177 .loc 1 2509 0 + 6178 00f8 0020 movs r0, #0 + ARM GAS /tmp/ccrFaSdZ.s page 168 + + + 6179 .LVL550: +2622:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6180 .loc 1 2622 0 + 6181 00fa 3BE0 b .L308 + 6182 .LVL551: + 6183 .L329: +2623:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2624:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_JOIN_ACCEPT_DELAY_2: +2625:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2626:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.JoinAcceptDelay2 = LoRaMacParams.JoinAcceptDelay2; + 6184 .loc 1 2626 0 + 6185 00fc 2A4B ldr r3, .L342+44 + 6186 00fe DB69 ldr r3, [r3, #28] + 6187 0100 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6188 .loc 1 2509 0 + 6189 0102 0020 movs r0, #0 + 6190 .LVL552: +2627:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6191 .loc 1 2627 0 + 6192 0104 36E0 b .L308 + 6193 .LVL553: + 6194 .L330: +2628:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2629:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_DATARATE: +2630:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2631:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsDefaultDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + 6195 .loc 1 2631 0 + 6196 0106 294B ldr r3, .L342+48 + 6197 0108 5B78 ldrb r3, [r3, #1] + 6198 010a 5BB2 sxtb r3, r3 + 6199 010c 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6200 .loc 1 2509 0 + 6201 010e 0020 movs r0, #0 + 6202 .LVL554: +2632:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6203 .loc 1 2632 0 + 6204 0110 30E0 b .L308 + 6205 .LVL555: + 6206 .L331: +2633:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2634:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DATARATE: +2635:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2636:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsDatarate = LoRaMacParams.ChannelsDatarate; + 6207 .loc 1 2636 0 + 6208 0112 254B ldr r3, .L342+44 + 6209 0114 5B78 ldrb r3, [r3, #1] + 6210 0116 5BB2 sxtb r3, r3 + 6211 0118 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6212 .loc 1 2509 0 + 6213 011a 0020 movs r0, #0 + 6214 .LVL556: +2637:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6215 .loc 1 2637 0 + 6216 011c 2AE0 b .L308 + ARM GAS /tmp/ccrFaSdZ.s page 169 + + + 6217 .LVL557: + 6218 .L333: +2638:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2639:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_TX_POWER: +2640:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsDefaultTxPower = LoRaMacParamsDefaults.ChannelsTxPower; + 6219 .loc 1 2641 0 + 6220 011e 234B ldr r3, .L342+48 + 6221 0120 1B78 ldrb r3, [r3] + 6222 0122 5BB2 sxtb r3, r3 + 6223 0124 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6224 .loc 1 2509 0 + 6225 0126 0020 movs r0, #0 + 6226 .LVL558: +2642:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6227 .loc 1 2642 0 + 6228 0128 24E0 b .L308 + 6229 .LVL559: + 6230 .L332: +2643:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2644:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_TX_POWER: +2645:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2646:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.ChannelsTxPower = LoRaMacParams.ChannelsTxPower; + 6231 .loc 1 2646 0 + 6232 012a 1F4B ldr r3, .L342+44 + 6233 012c 1B78 ldrb r3, [r3] + 6234 012e 5BB2 sxtb r3, r3 + 6235 0130 0371 strb r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6236 .loc 1 2509 0 + 6237 0132 0020 movs r0, #0 + 6238 .LVL560: +2647:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6239 .loc 1 2647 0 + 6240 0134 1EE0 b .L308 + 6241 .LVL561: + 6242 .L334: +2648:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2649:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_UPLINK_COUNTER: +2650:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2651:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.UpLinkCounter = UpLinkCounter; + 6243 .loc 1 2651 0 + 6244 0136 1E4B ldr r3, .L342+52 + 6245 0138 1B68 ldr r3, [r3] + 6246 013a 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6247 .loc 1 2509 0 + 6248 013c 0020 movs r0, #0 + 6249 .LVL562: +2652:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6250 .loc 1 2652 0 + 6251 013e 19E0 b .L308 + 6252 .LVL563: + 6253 .L335: +2653:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2654:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DOWNLINK_COUNTER: + ARM GAS /tmp/ccrFaSdZ.s page 170 + + +2655:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2656:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.DownLinkCounter = DownLinkCounter; + 6254 .loc 1 2656 0 + 6255 0140 1C4B ldr r3, .L342+56 + 6256 0142 1B68 ldr r3, [r3] + 6257 0144 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6258 .loc 1 2509 0 + 6259 0146 0020 movs r0, #0 + 6260 .LVL564: +2657:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6261 .loc 1 2657 0 + 6262 0148 14E0 b .L308 + 6263 .LVL565: + 6264 .L336: +2658:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2659:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_MULTICAST_CHANNEL: +2660:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2661:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.MulticastList = MulticastChannels; + 6265 .loc 1 2661 0 + 6266 014a 1B4B ldr r3, .L342+60 + 6267 014c 1B68 ldr r3, [r3] + 6268 014e 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6269 .loc 1 2509 0 + 6270 0150 0020 movs r0, #0 + 6271 .LVL566: +2662:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6272 .loc 1 2662 0 + 6273 0152 0FE0 b .L308 + 6274 .LVL567: + 6275 .L337: +2663:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2664:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_SYSTEM_MAX_RX_ERROR: +2665:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2666:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.SystemMaxRxError = LoRaMacParams.SystemMaxRxError; + 6276 .loc 1 2666 0 + 6277 0154 144B ldr r3, .L342+44 + 6278 0156 5B68 ldr r3, [r3, #4] + 6279 0158 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6280 .loc 1 2509 0 + 6281 015a 0020 movs r0, #0 + 6282 .LVL568: +2667:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6283 .loc 1 2667 0 + 6284 015c 0AE0 b .L308 + 6285 .LVL569: + 6286 .L338: +2668:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2669:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_MIN_RX_SYMBOLS: +2670:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2671:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.MinRxSymbols = LoRaMacParams.MinRxSymbols; + 6287 .loc 1 2671 0 + 6288 015e 124B ldr r3, .L342+44 + 6289 0160 1B7A ldrb r3, [r3, #8] + 6290 0162 0371 strb r3, [r0, #4] + ARM GAS /tmp/ccrFaSdZ.s page 171 + + +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6291 .loc 1 2509 0 + 6292 0164 0020 movs r0, #0 + 6293 .LVL570: +2672:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6294 .loc 1 2672 0 + 6295 0166 05E0 b .L308 + 6296 .LVL571: + 6297 .L339: +2673:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2674:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_ANTENNA_GAIN: +2675:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2676:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mibGet->Param.AntennaGain = LoRaMacParams.AntennaGain; + 6298 .loc 1 2676 0 + 6299 0168 0F4B ldr r3, .L342+44 + 6300 016a 5B6B ldr r3, [r3, #52] + 6301 016c 4360 str r3, [r0, #4] +2509:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; + 6302 .loc 1 2509 0 + 6303 016e 0020 movs r0, #0 + 6304 .LVL572: +2677:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6305 .loc 1 2677 0 + 6306 0170 00E0 b .L308 + 6307 .LVL573: + 6308 .L340: +2515:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 6309 .loc 1 2515 0 + 6310 0172 0320 movs r0, #3 + 6311 .LVL574: + 6312 .L308: +2678:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2679:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +2680:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_SERVICE_UNKNOWN; +2681:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2682:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2683:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2684:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +2685:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 6313 .loc 1 2685 0 + 6314 0174 02B0 add sp, sp, #8 + 6315 @ sp needed + 6316 0176 10BD pop {r4, pc} + 6317 .LVL575: + 6318 .L341: +2680:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6319 .loc 1 2680 0 + 6320 0178 0220 movs r0, #2 + 6321 .LVL576: + 6322 017a FBE7 b .L308 + 6323 .L343: + 6324 .align 2 + 6325 .L342: + 6326 017c 00000000 .word .L310 + 6327 0180 00000000 .word .LANCHOR25 + 6328 0184 00000000 .word .LANCHOR0 + 6329 0188 00000000 .word .LANCHOR29 + ARM GAS /tmp/ccrFaSdZ.s page 172 + + + 6330 018c 00000000 .word .LANCHOR40 + 6331 0190 00000000 .word .LANCHOR41 + 6332 0194 00000000 .word .LANCHOR33 + 6333 0198 00000000 .word .LANCHOR32 + 6334 019c 00000000 .word .LANCHOR63 + 6335 01a0 00000000 .word .LANCHOR21 + 6336 01a4 00000000 .word .LANCHOR22 + 6337 01a8 00000000 .word .LANCHOR14 + 6338 01ac 00000000 .word .LANCHOR13 + 6339 01b0 00000000 .word .LANCHOR1 + 6340 01b4 00000000 .word .LANCHOR2 + 6341 01b8 00000000 .word .LANCHOR18 + 6342 .cfi_endproc + 6343 .LFE111: + 6345 .section .text.LoRaMacMibSetRequestConfirm,"ax",%progbits + 6346 .align 1 + 6347 .global LoRaMacMibSetRequestConfirm + 6348 .syntax unified + 6349 .code 16 + 6350 .thumb_func + 6351 .fpu softvfp + 6353 LoRaMacMibSetRequestConfirm: + 6354 .LFB112: +2686:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2687:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMibSetRequestConfirm( MibRequestConfirm_t *mibSet ) +2688:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 6355 .loc 1 2688 0 + 6356 .cfi_startproc + 6357 @ args = 0, pretend = 0, frame = 16 + 6358 @ frame_needed = 0, uses_anonymous_args = 0 + 6359 .LVL577: + 6360 0000 70B5 push {r4, r5, r6, lr} + 6361 .LCFI41: + 6362 .cfi_def_cfa_offset 16 + 6363 .cfi_offset 4, -16 + 6364 .cfi_offset 5, -12 + 6365 .cfi_offset 6, -8 + 6366 .cfi_offset 14, -4 + 6367 0002 86B0 sub sp, sp, #24 + 6368 .LCFI42: + 6369 .cfi_def_cfa_offset 40 + 6370 0004 041E subs r4, r0, #0 + 6371 .LVL578: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_OK; +2690:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; +2691:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** VerifyParams_t verify; +2692:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2693:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mibSet == NULL ) + 6372 .loc 1 2693 0 + 6373 0006 00D1 bne .LCB6177 + 6374 0008 6AE1 b .L379 @long jump + 6375 .LCB6177: +2694:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2695:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +2696:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2697:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 6376 .loc 1 2697 0 + ARM GAS /tmp/ccrFaSdZ.s page 173 + + + 6377 000a C54B ldr r3, .L400 + 6378 000c 1B68 ldr r3, [r3] + 6379 000e DB07 lsls r3, r3, #31 + 6380 0010 00D5 bpl .LCB6183 + 6381 0012 67E1 b .L380 @long jump + 6382 .LCB6183: +2698:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2699:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +2700:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2701:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2702:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( mibSet->Type ) + 6383 .loc 1 2702 0 + 6384 0014 0378 ldrb r3, [r0] + 6385 0016 1D2B cmp r3, #29 + 6386 0018 00D9 bls .LCB6186 + 6387 001a 66E1 b .L381 @long jump + 6388 .LCB6186: + 6389 001c 9B00 lsls r3, r3, #2 + 6390 001e C14A ldr r2, .L400+4 + 6391 0020 D358 ldr r3, [r2, r3] + 6392 0022 9F46 mov pc, r3 + 6393 .section .rodata.LoRaMacMibSetRequestConfirm,"a",%progbits + 6394 .align 2 + 6395 .L347: + 6396 0000 24000000 .word .L346 + 6397 0004 4E000000 .word .L348 + 6398 0008 58000000 .word .L349 + 6399 000c 62000000 .word .L350 + 6400 0010 6C000000 .word .L351 + 6401 0014 76000000 .word .L352 + 6402 0018 8A000000 .word .L353 + 6403 001c 9E000000 .word .L354 + 6404 0020 AE000000 .word .L355 + 6405 0024 EA020000 .word .L381 + 6406 0028 B8000000 .word .L356 + 6407 002c 66010000 .word .L357 + 6408 0030 B0010000 .word .L358 + 6409 0034 94010000 .word .L359 + 6410 0038 CC010000 .word .L360 + 6411 003c E2010000 .word .L361 + 6412 0040 EC010000 .word .L362 + 6413 0044 F6010000 .word .L363 + 6414 0048 00020000 .word .L364 + 6415 004c 0A020000 .word .L365 + 6416 0050 14020000 .word .L366 + 6417 0054 3A020000 .word .L367 + 6418 0058 82020000 .word .L368 + 6419 005c 5E020000 .word .L369 + 6420 0060 A6020000 .word .L370 + 6421 0064 B0020000 .word .L371 + 6422 0068 EA020000 .word .L381 + 6423 006c BA020000 .word .L372 + 6424 0070 C8020000 .word .L373 + 6425 0074 D6020000 .word .L374 + 6426 .section .text.LoRaMacMibSetRequestConfirm + 6427 .L346: +2703:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + ARM GAS /tmp/ccrFaSdZ.s page 174 + + +2704:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DEVICE_CLASS: +2705:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2706:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDeviceClass = mibSet->Param.Class; + 6428 .loc 1 2706 0 + 6429 0024 0379 ldrb r3, [r0, #4] + 6430 0026 C04A ldr r2, .L400+8 + 6431 0028 1370 strb r3, [r2] +2707:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( LoRaMacDeviceClass ) + 6432 .loc 1 2707 0 + 6433 002a 002B cmp r3, #0 + 6434 002c 03D0 beq .L375 + 6435 002e 022B cmp r3, #2 + 6436 0030 06D0 beq .L376 +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6437 .loc 1 2689 0 + 6438 0032 0020 movs r0, #0 + 6439 .LVL579: + 6440 0034 57E1 b .L345 + 6441 .LVL580: + 6442 .L375: +2708:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2709:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case CLASS_A: +2710:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2711:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Set the radio into sleep to setup a defined state +2712:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.Sleep( ); + 6443 .loc 1 2712 0 + 6444 0036 BD4B ldr r3, .L400+12 + 6445 0038 5B6B ldr r3, [r3, #52] + 6446 003a 9847 blx r3 + 6447 .LVL581: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6448 .loc 1 2689 0 + 6449 003c 0020 movs r0, #0 +2713:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6450 .loc 1 2713 0 + 6451 003e 52E1 b .L345 + 6452 .LVL582: + 6453 .L376: +2714:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2715:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case CLASS_B: +2716:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2717:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2718:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2719:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case CLASS_C: +2720:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2721:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Set the NodeAckRequested indicator to default +2722:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; + 6454 .loc 1 2722 0 + 6455 0040 BB4B ldr r3, .L400+16 + 6456 0042 0022 movs r2, #0 + 6457 0044 1A70 strb r2, [r3] +2723:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** OnRxWindow2TimerEvent( ); + 6458 .loc 1 2723 0 + 6459 0046 FFF7FEFF bl OnRxWindow2TimerEvent + 6460 .LVL583: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6461 .loc 1 2689 0 + ARM GAS /tmp/ccrFaSdZ.s page 175 + + + 6462 004a 0020 movs r0, #0 +2724:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6463 .loc 1 2724 0 + 6464 004c 4BE1 b .L345 + 6465 .LVL584: + 6466 .L348: +2725:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2726:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2727:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2728:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2729:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NETWORK_JOINED: +2730:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2731:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsLoRaMacNetworkJoined = mibSet->Param.IsNetworkJoined; + 6467 .loc 1 2731 0 + 6468 004e 0279 ldrb r2, [r0, #4] + 6469 0050 B84B ldr r3, .L400+20 + 6470 0052 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6471 .loc 1 2689 0 + 6472 0054 0020 movs r0, #0 + 6473 .LVL585: +2732:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6474 .loc 1 2732 0 + 6475 0056 46E1 b .L345 + 6476 .LVL586: + 6477 .L349: +2733:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2734:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_ADR: +2735:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2736:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AdrCtrlOn = mibSet->Param.AdrEnable; + 6478 .loc 1 2736 0 + 6479 0058 0279 ldrb r2, [r0, #4] + 6480 005a B74B ldr r3, .L400+24 + 6481 005c 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6482 .loc 1 2689 0 + 6483 005e 0020 movs r0, #0 + 6484 .LVL587: +2737:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6485 .loc 1 2737 0 + 6486 0060 41E1 b .L345 + 6487 .LVL588: + 6488 .L350: +2738:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2739:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NET_ID: +2740:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2741:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacNetID = mibSet->Param.NetID; + 6489 .loc 1 2741 0 + 6490 0062 4268 ldr r2, [r0, #4] + 6491 0064 B54B ldr r3, .L400+28 + 6492 0066 1A60 str r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6493 .loc 1 2689 0 + 6494 0068 0020 movs r0, #0 + 6495 .LVL589: +2742:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6496 .loc 1 2742 0 + ARM GAS /tmp/ccrFaSdZ.s page 176 + + + 6497 006a 3CE1 b .L345 + 6498 .LVL590: + 6499 .L351: +2743:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2744:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DEV_ADDR: +2745:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2746:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevAddr = mibSet->Param.DevAddr; + 6500 .loc 1 2746 0 + 6501 006c 4268 ldr r2, [r0, #4] + 6502 006e B44B ldr r3, .L400+32 + 6503 0070 1A60 str r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6504 .loc 1 2689 0 + 6505 0072 0020 movs r0, #0 + 6506 .LVL591: +2747:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6507 .loc 1 2747 0 + 6508 0074 37E1 b .L345 + 6509 .LVL592: + 6510 .L352: +2748:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2749:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_NWK_SKEY: +2750:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2751:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mibSet->Param.NwkSKey != NULL ) + 6511 .loc 1 2751 0 + 6512 0076 4168 ldr r1, [r0, #4] + 6513 0078 0029 cmp r1, #0 + 6514 007a 00D1 bne .LCB6277 + 6515 007c 37E1 b .L383 @long jump + 6516 .LCB6277: +2752:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2753:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpy1( LoRaMacNwkSKey, mibSet->Param.NwkSKey, + 6517 .loc 1 2753 0 + 6518 007e 1022 movs r2, #16 + 6519 0080 B048 ldr r0, .L400+36 + 6520 .LVL593: + 6521 0082 FFF7FEFF bl memcpy1 + 6522 .LVL594: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6523 .loc 1 2689 0 + 6524 0086 0020 movs r0, #0 + 6525 0088 2DE1 b .L345 + 6526 .LVL595: + 6527 .L353: +2754:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sizeof( LoRaMacNwkSKey ) ); +2755:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2756:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2757:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2758:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2759:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2760:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2761:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2762:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_APP_SKEY: +2763:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2764:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mibSet->Param.AppSKey != NULL ) + 6528 .loc 1 2764 0 + 6529 008a 4168 ldr r1, [r0, #4] + ARM GAS /tmp/ccrFaSdZ.s page 177 + + + 6530 008c 0029 cmp r1, #0 + 6531 008e 00D1 bne .LCB6291 + 6532 0090 2FE1 b .L384 @long jump + 6533 .LCB6291: +2765:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2766:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memcpy1( LoRaMacAppSKey, mibSet->Param.AppSKey, + 6534 .loc 1 2766 0 + 6535 0092 1022 movs r2, #16 + 6536 0094 AC48 ldr r0, .L400+40 + 6537 .LVL596: + 6538 0096 FFF7FEFF bl memcpy1 + 6539 .LVL597: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6540 .loc 1 2689 0 + 6541 009a 0020 movs r0, #0 + 6542 009c 23E1 b .L345 + 6543 .LVL598: + 6544 .L354: +2767:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** sizeof( LoRaMacAppSKey ) ); +2768:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2769:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2770:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2771:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2772:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2773:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2774:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2775:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_PUBLIC_NETWORK: +2776:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2777:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PublicNetwork = mibSet->Param.EnablePublicNetwork; + 6545 .loc 1 2777 0 + 6546 009e 0079 ldrb r0, [r0, #4] + 6547 .LVL599: + 6548 00a0 AA4B ldr r3, .L400+44 + 6549 00a2 1870 strb r0, [r3] +2778:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Radio.SetPublicNetwork( PublicNetwork ); + 6550 .loc 1 2778 0 + 6551 00a4 A14B ldr r3, .L400+12 + 6552 00a6 1B6E ldr r3, [r3, #96] + 6553 00a8 9847 blx r3 + 6554 .LVL600: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6555 .loc 1 2689 0 + 6556 00aa 0020 movs r0, #0 +2779:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6557 .loc 1 2779 0 + 6558 00ac 1BE1 b .L345 + 6559 .LVL601: + 6560 .L355: +2780:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2781:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_REPEATER_SUPPORT: +2782:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2783:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RepeaterSupport = mibSet->Param.EnableRepeaterSupport; + 6561 .loc 1 2783 0 + 6562 00ae 0279 ldrb r2, [r0, #4] + 6563 00b0 A74B ldr r3, .L400+48 + 6564 00b2 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + ARM GAS /tmp/ccrFaSdZ.s page 178 + + + 6565 .loc 1 2689 0 + 6566 00b4 0020 movs r0, #0 + 6567 .LVL602: +2784:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6568 .loc 1 2784 0 + 6569 00b6 16E1 b .L345 + 6570 .LVL603: + 6571 .L356: +2785:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2786:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RX2_CHANNEL: +2787:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2788:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.Datarate = mibSet->Param.Rx2Channel.Datarate; + 6572 .loc 1 2788 0 + 6573 00b8 0823 movs r3, #8 + 6574 00ba C356 ldrsb r3, [r0, r3] + 6575 00bc 03A9 add r1, sp, #12 + 6576 00be 0B70 strb r3, [r1] +2789:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 6577 .loc 1 2789 0 + 6578 00c0 A44A ldr r2, .L400+52 + 6579 00c2 2D23 movs r3, #45 + 6580 00c4 D35C ldrb r3, [r2, r3] + 6581 00c6 4B70 strb r3, [r1, #1] +2790:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2791:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_RX_DR ) == true ) + 6582 .loc 1 2791 0 + 6583 00c8 A34B ldr r3, .L400+56 + 6584 00ca 1878 ldrb r0, [r3] + 6585 .LVL604: + 6586 00cc 0622 movs r2, #6 + 6587 00ce FFF7FEFF bl RegionVerify + 6588 .LVL605: + 6589 00d2 0028 cmp r0, #0 + 6590 00d4 00D1 bne .LCB6342 + 6591 00d6 0EE1 b .L385 @long jump + 6592 .LCB6342: +2792:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2793:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel = mibSet->Param.Rx2Channel; + 6593 .loc 1 2793 0 + 6594 00d8 9E4B ldr r3, .L400+52 + 6595 00da 2433 adds r3, r3, #36 + 6596 00dc 0434 adds r4, r4, #4 + 6597 .LVL606: + 6598 00de 06CC ldmia r4!, {r1, r2} + 6599 00e0 06C3 stmia r3!, {r1, r2} + 6600 .LVL607: +2794:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2795:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacDeviceClass == CLASS_C ) && ( IsLoRaMacNetworkJoined == true ) ) + 6601 .loc 1 2795 0 + 6602 00e2 914B ldr r3, .L400+8 + 6603 00e4 1B78 ldrb r3, [r3] + 6604 00e6 022B cmp r3, #2 + 6605 00e8 01D0 beq .L398 +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6606 .loc 1 2689 0 + 6607 00ea 0020 movs r0, #0 + 6608 00ec FBE0 b .L345 + ARM GAS /tmp/ccrFaSdZ.s page 179 + + + 6609 .L398: + 6610 .loc 1 2795 0 discriminator 1 + 6611 00ee 914B ldr r3, .L400+20 + 6612 00f0 1B78 ldrb r3, [r3] + 6613 00f2 002B cmp r3, #0 + 6614 00f4 01D1 bne .L399 +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6615 .loc 1 2689 0 + 6616 00f6 0020 movs r0, #0 + 6617 00f8 F5E0 b .L345 + 6618 .L399: +2796:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2797:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Compute Rx2 windows parameters +2798:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RegionComputeRxWindowParameters( LoRaMacRegion, +2799:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate, + 6619 .loc 1 2799 0 + 6620 00fa 964D ldr r5, .L400+52 +2798:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.Rx2Channel.Datarate, + 6621 .loc 1 2798 0 + 6622 00fc 6B68 ldr r3, [r5, #4] + 6623 00fe 2A7A ldrb r2, [r5, #8] + 6624 0100 2821 movs r1, #40 + 6625 0102 6956 ldrsb r1, [r5, r1] + 6626 0104 944E ldr r6, .L400+56 + 6627 0106 3078 ldrb r0, [r6] + 6628 0108 944C ldr r4, .L400+60 + 6629 .LVL608: + 6630 010a 0094 str r4, [sp] + 6631 010c FFF7FEFF bl RegionComputeRxWindowParameters + 6632 .LVL609: +2800:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols, +2801:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.SystemMaxRxError, +2802:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** &RxWindow2Config ); +2803:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2804:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Channel = Channel; + 6633 .loc 1 2804 0 + 6634 0110 934B ldr r3, .L400+64 + 6635 0112 1B78 ldrb r3, [r3] + 6636 0114 2370 strb r3, [r4] +2805:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Frequency = LoRaMacParams.Rx2Channel.Frequency; + 6637 .loc 1 2805 0 + 6638 0116 6B6A ldr r3, [r5, #36] + 6639 0118 6360 str r3, [r4, #4] +2806:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 6640 .loc 1 2806 0 + 6641 011a 2D23 movs r3, #45 + 6642 011c EB5C ldrb r3, [r5, r3] + 6643 011e 2374 strb r3, [r4, #16] +2807:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RepeaterSupport = RepeaterSupport; + 6644 .loc 1 2807 0 + 6645 0120 8B4B ldr r3, .L400+48 + 6646 0122 1B78 ldrb r3, [r3] + 6647 0124 6374 strb r3, [r4, #17] +2808:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.Window = 1; + 6648 .loc 1 2808 0 + 6649 0126 0123 movs r3, #1 + 6650 0128 E374 strb r3, [r4, #19] + ARM GAS /tmp/ccrFaSdZ.s page 180 + + +2809:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindow2Config.RxContinuous = true; + 6651 .loc 1 2809 0 + 6652 012a A374 strb r3, [r4, #18] +2810:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2811:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionRxConfig( LoRaMacRegion, &RxWindow2Config, ( int8_t* )&McpsIndication + 6653 .loc 1 2811 0 + 6654 012c 8D4A ldr r2, .L400+68 + 6655 012e 3078 ldrb r0, [r6] + 6656 0130 0432 adds r2, r2, #4 + 6657 0132 2100 movs r1, r4 + 6658 0134 FFF7FEFF bl RegionRxConfig + 6659 .LVL610: + 6660 0138 0028 cmp r0, #0 + 6661 013a 00D1 bne .LCB6402 + 6662 013c DDE0 b .L388 @long jump + 6663 .LCB6402: +2812:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2813:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxWindowSetup( RxWindow2Config.RxContinuous, LoRaMacParams.MaxRxWindow ); + 6664 .loc 1 2813 0 + 6665 013e 874B ldr r3, .L400+60 + 6666 0140 9B7C ldrb r3, [r3, #18] + 6667 0142 844A ldr r2, .L400+52 + 6668 0144 D068 ldr r0, [r2, #12] + 6669 .LVL611: + 6670 .LBB81: + 6671 .LBB82: +1508:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 6672 .loc 1 1508 0 + 6673 0146 002B cmp r3, #0 + 6674 0148 08D1 bne .L377 +1510:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 6675 .loc 1 1510 0 + 6676 014a 784B ldr r3, .L400+12 + 6677 .LVL612: + 6678 014c DB6B ldr r3, [r3, #60] + 6679 014e 9847 blx r3 + 6680 .LVL613: + 6681 .L378: + 6682 .LBE82: + 6683 .LBE81: +2814:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** RxSlot = RxWindow2Config.Window; + 6684 .loc 1 2814 0 + 6685 0150 824B ldr r3, .L400+60 + 6686 0152 DA7C ldrb r2, [r3, #19] + 6687 0154 844B ldr r3, .L400+72 + 6688 0156 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6689 .loc 1 2689 0 + 6690 0158 0020 movs r0, #0 + 6691 015a C4E0 b .L345 + 6692 .LVL614: + 6693 .L377: + 6694 .LBB84: + 6695 .LBB83: +1514:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 6696 .loc 1 1514 0 + 6697 015c 734B ldr r3, .L400+12 + ARM GAS /tmp/ccrFaSdZ.s page 181 + + + 6698 .LVL615: + 6699 015e DB6B ldr r3, [r3, #60] + 6700 0160 0020 movs r0, #0 + 6701 .LVL616: + 6702 0162 9847 blx r3 + 6703 .LVL617: + 6704 0164 F4E7 b .L378 + 6705 .LVL618: + 6706 .L357: + 6707 .LBE83: + 6708 .LBE84: +2815:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2816:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2817:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2819:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2820:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2821:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2822:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2823:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2824:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2825:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2826:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2827:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2828:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RX2_DEFAULT_CHANNEL: +2829:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2830:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.Datarate = mibSet->Param.Rx2Channel.Datarate; + 6709 .loc 1 2830 0 + 6710 0166 0823 movs r3, #8 + 6711 0168 C356 ldrsb r3, [r0, r3] + 6712 016a 03A9 add r1, sp, #12 + 6713 016c 0B70 strb r3, [r1] +2831:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + 6714 .loc 1 2831 0 + 6715 016e 794A ldr r2, .L400+52 + 6716 0170 2D23 movs r3, #45 + 6717 0172 D35C ldrb r3, [r2, r3] + 6718 0174 4B70 strb r3, [r1, #1] +2832:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2833:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_RX_DR ) == true ) + 6719 .loc 1 2833 0 + 6720 0176 784B ldr r3, .L400+56 + 6721 0178 1878 ldrb r0, [r3] + 6722 .LVL619: + 6723 017a 0622 movs r2, #6 + 6724 017c FFF7FEFF bl RegionVerify + 6725 .LVL620: + 6726 0180 0028 cmp r0, #0 + 6727 0182 00D1 bne .LCB6472 + 6728 0184 BBE0 b .L389 @long jump + 6729 .LCB6472: +2834:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2835:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.Rx2Channel = mibSet->Param.Rx2DefaultChannel; + 6730 .loc 1 2835 0 + 6731 0186 794B ldr r3, .L400+76 + 6732 0188 2433 adds r3, r3, #36 + 6733 018a 0434 adds r4, r4, #4 + ARM GAS /tmp/ccrFaSdZ.s page 182 + + + 6734 .LVL621: + 6735 018c 06CC ldmia r4!, {r1, r2} + 6736 018e 06C3 stmia r3!, {r1, r2} + 6737 .LVL622: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6738 .loc 1 2689 0 + 6739 0190 0020 movs r0, #0 + 6740 0192 A8E0 b .L345 + 6741 .LVL623: + 6742 .L359: +2836:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2837:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2838:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2839:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2840:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2841:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2842:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2843:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_MASK: +2844:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2845:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chanMaskSet.ChannelsMaskIn = mibSet->Param.ChannelsMask; + 6743 .loc 1 2845 0 + 6744 0194 4368 ldr r3, [r0, #4] + 6745 0196 0493 str r3, [sp, #16] + 6746 0198 04A9 add r1, sp, #16 +2846:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chanMaskSet.ChannelsMaskType = CHANNELS_DEFAULT_MASK; + 6747 .loc 1 2846 0 + 6748 019a 0123 movs r3, #1 + 6749 019c 0B71 strb r3, [r1, #4] +2847:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2848:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionChanMaskSet( LoRaMacRegion, &chanMaskSet ) == false ) + 6750 .loc 1 2848 0 + 6751 019e 6E4B ldr r3, .L400+56 + 6752 01a0 1878 ldrb r0, [r3] + 6753 .LVL624: + 6754 01a2 FFF7FEFF bl RegionChanMaskSet + 6755 .LVL625: + 6756 01a6 0028 cmp r0, #0 + 6757 01a8 00D1 bne .LCB6497 + 6758 01aa AAE0 b .L390 @long jump + 6759 .LCB6497: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6760 .loc 1 2689 0 + 6761 01ac 0020 movs r0, #0 + 6762 01ae 9AE0 b .L345 + 6763 .LVL626: + 6764 .L358: +2849:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2850:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2851:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2852:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2853:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2854:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_MASK: +2855:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2856:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chanMaskSet.ChannelsMaskIn = mibSet->Param.ChannelsMask; + 6765 .loc 1 2856 0 + 6766 01b0 4368 ldr r3, [r0, #4] + 6767 01b2 0493 str r3, [sp, #16] + ARM GAS /tmp/ccrFaSdZ.s page 183 + + + 6768 01b4 04A9 add r1, sp, #16 +2857:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** chanMaskSet.ChannelsMaskType = CHANNELS_MASK; + 6769 .loc 1 2857 0 + 6770 01b6 0023 movs r3, #0 + 6771 01b8 0B71 strb r3, [r1, #4] +2858:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2859:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionChanMaskSet( LoRaMacRegion, &chanMaskSet ) == false ) + 6772 .loc 1 2859 0 + 6773 01ba 674B ldr r3, .L400+56 + 6774 01bc 1878 ldrb r0, [r3] + 6775 .LVL627: + 6776 01be FFF7FEFF bl RegionChanMaskSet + 6777 .LVL628: + 6778 01c2 0028 cmp r0, #0 + 6779 01c4 00D1 bne .LCB6516 + 6780 01c6 9EE0 b .L391 @long jump + 6781 .LCB6516: +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6782 .loc 1 2689 0 + 6783 01c8 0020 movs r0, #0 + 6784 01ca 8CE0 b .L345 + 6785 .LVL629: + 6786 .L360: +2860:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2861:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2862:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2863:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2864:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2865:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_NB_REP: +2866:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2867:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( mibSet->Param.ChannelNbRep >= 1 ) && + 6787 .loc 1 2867 0 + 6788 01cc 0279 ldrb r2, [r0, #4] + 6789 01ce 531E subs r3, r2, #1 + 6790 01d0 DBB2 uxtb r3, r3 + 6791 01d2 0E2B cmp r3, #14 + 6792 01d4 00D9 bls .LCB6527 + 6793 01d6 98E0 b .L392 @long jump + 6794 .LCB6527: +2868:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mibSet->Param.ChannelNbRep <= 15 ) ) +2869:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2870:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsNbRep = mibSet->Param.ChannelNbRep; + 6795 .loc 1 2870 0 + 6796 01d8 5E49 ldr r1, .L400+52 + 6797 01da 2023 movs r3, #32 + 6798 01dc CA54 strb r2, [r1, r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6799 .loc 1 2689 0 + 6800 01de 0020 movs r0, #0 + 6801 .LVL630: + 6802 01e0 81E0 b .L345 + 6803 .LVL631: + 6804 .L361: +2871:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2872:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2873:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2874:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; + ARM GAS /tmp/ccrFaSdZ.s page 184 + + +2875:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2876:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2877:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2878:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_MAX_RX_WINDOW_DURATION: +2879:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2880:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MaxRxWindow = mibSet->Param.MaxRxWindow; + 6805 .loc 1 2880 0 + 6806 01e2 4268 ldr r2, [r0, #4] + 6807 01e4 5B4B ldr r3, .L400+52 + 6808 01e6 DA60 str r2, [r3, #12] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6809 .loc 1 2689 0 + 6810 01e8 0020 movs r0, #0 + 6811 .LVL632: +2881:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6812 .loc 1 2881 0 + 6813 01ea 7CE0 b .L345 + 6814 .LVL633: + 6815 .L362: +2882:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2883:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RECEIVE_DELAY_1: +2884:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2885:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay1 = mibSet->Param.ReceiveDelay1; + 6816 .loc 1 2885 0 + 6817 01ec 4268 ldr r2, [r0, #4] + 6818 01ee 594B ldr r3, .L400+52 + 6819 01f0 1A61 str r2, [r3, #16] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6820 .loc 1 2689 0 + 6821 01f2 0020 movs r0, #0 + 6822 .LVL634: +2886:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6823 .loc 1 2886 0 + 6824 01f4 77E0 b .L345 + 6825 .LVL635: + 6826 .L363: +2887:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2888:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_RECEIVE_DELAY_2: +2889:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2890:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ReceiveDelay2 = mibSet->Param.ReceiveDelay2; + 6827 .loc 1 2890 0 + 6828 01f6 4268 ldr r2, [r0, #4] + 6829 01f8 564B ldr r3, .L400+52 + 6830 01fa 5A61 str r2, [r3, #20] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6831 .loc 1 2689 0 + 6832 01fc 0020 movs r0, #0 + 6833 .LVL636: +2891:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6834 .loc 1 2891 0 + 6835 01fe 72E0 b .L345 + 6836 .LVL637: + 6837 .L364: +2892:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2893:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_JOIN_ACCEPT_DELAY_1: +2894:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2895:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.JoinAcceptDelay1 = mibSet->Param.JoinAcceptDelay1; + ARM GAS /tmp/ccrFaSdZ.s page 185 + + + 6838 .loc 1 2895 0 + 6839 0200 4268 ldr r2, [r0, #4] + 6840 0202 544B ldr r3, .L400+52 + 6841 0204 9A61 str r2, [r3, #24] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6842 .loc 1 2689 0 + 6843 0206 0020 movs r0, #0 + 6844 .LVL638: +2896:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6845 .loc 1 2896 0 + 6846 0208 6DE0 b .L345 + 6847 .LVL639: + 6848 .L365: +2897:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2898:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_JOIN_ACCEPT_DELAY_2: +2899:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2900:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.JoinAcceptDelay2 = mibSet->Param.JoinAcceptDelay2; + 6849 .loc 1 2900 0 + 6850 020a 4268 ldr r2, [r0, #4] + 6851 020c 514B ldr r3, .L400+52 + 6852 020e DA61 str r2, [r3, #28] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6853 .loc 1 2689 0 + 6854 0210 0020 movs r0, #0 + 6855 .LVL640: +2901:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6856 .loc 1 2901 0 + 6857 0212 68E0 b .L345 + 6858 .LVL641: + 6859 .L366: +2902:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2903:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_DATARATE: +2904:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2905:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.Datarate = mibSet->Param.ChannelsDefaultDatarate; + 6860 .loc 1 2905 0 + 6861 0214 0423 movs r3, #4 + 6862 0216 C356 ldrsb r3, [r0, r3] + 6863 0218 03A9 add r1, sp, #12 + 6864 021a 0B70 strb r3, [r1] +2906:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2907:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_DEF_TX_DR ) == true ) + 6865 .loc 1 2907 0 + 6866 021c 4E4B ldr r3, .L400+56 + 6867 021e 1878 ldrb r0, [r3] + 6868 .LVL642: + 6869 0220 0522 movs r2, #5 + 6870 0222 FFF7FEFF bl RegionVerify + 6871 .LVL643: + 6872 0226 0028 cmp r0, #0 + 6873 0228 00D1 bne .LCB6599 + 6874 022a 70E0 b .L393 @long jump + 6875 .LCB6599: +2908:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2909:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ChannelsDatarate = verify.DatarateParams.Datarate; + 6876 .loc 1 2909 0 + 6877 022c 03AB add r3, sp, #12 + 6878 022e 0022 movs r2, #0 + ARM GAS /tmp/ccrFaSdZ.s page 186 + + + 6879 0230 9A56 ldrsb r2, [r3, r2] + 6880 0232 4E4B ldr r3, .L400+76 + 6881 0234 5A70 strb r2, [r3, #1] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6882 .loc 1 2689 0 + 6883 0236 0020 movs r0, #0 + 6884 0238 55E0 b .L345 + 6885 .LVL644: + 6886 .L367: +2910:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2911:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2912:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2913:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2914:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2915:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2916:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2917:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DATARATE: +2918:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2919:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.Datarate = mibSet->Param.ChannelsDatarate; + 6887 .loc 1 2919 0 + 6888 023a 0423 movs r3, #4 + 6889 023c C356 ldrsb r3, [r0, r3] + 6890 023e 03A9 add r1, sp, #12 + 6891 0240 0B70 strb r3, [r1] +2920:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2921:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_TX_DR ) == true ) + 6892 .loc 1 2921 0 + 6893 0242 454B ldr r3, .L400+56 + 6894 0244 1878 ldrb r0, [r3] + 6895 .LVL645: + 6896 0246 0422 movs r2, #4 + 6897 0248 FFF7FEFF bl RegionVerify + 6898 .LVL646: + 6899 024c 0028 cmp r0, #0 + 6900 024e 60D0 beq .L394 +2922:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2923:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = verify.DatarateParams.Datarate; + 6901 .loc 1 2923 0 + 6902 0250 03AB add r3, sp, #12 + 6903 0252 0022 movs r2, #0 + 6904 0254 9A56 ldrsb r2, [r3, r2] + 6905 0256 3F4B ldr r3, .L400+52 + 6906 0258 5A70 strb r2, [r3, #1] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6907 .loc 1 2689 0 + 6908 025a 0020 movs r0, #0 + 6909 025c 43E0 b .L345 + 6910 .LVL647: + 6911 .L369: +2924:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2925:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2926:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2928:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2929:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2930:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2931:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_DEFAULT_TX_POWER: + ARM GAS /tmp/ccrFaSdZ.s page 187 + + +2932:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2933:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.TxPower = mibSet->Param.ChannelsDefaultTxPower; + 6912 .loc 1 2933 0 + 6913 025e 0423 movs r3, #4 + 6914 0260 C356 ldrsb r3, [r0, r3] + 6915 0262 03A9 add r1, sp, #12 + 6916 0264 0B70 strb r3, [r1] +2934:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2935:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_DEF_TX_POWER ) == true ) + 6917 .loc 1 2935 0 + 6918 0266 3C4B ldr r3, .L400+56 + 6919 0268 1878 ldrb r0, [r3] + 6920 .LVL648: + 6921 026a 0822 movs r2, #8 + 6922 026c FFF7FEFF bl RegionVerify + 6923 .LVL649: + 6924 0270 0028 cmp r0, #0 + 6925 0272 50D0 beq .L395 +2936:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2937:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParamsDefaults.ChannelsTxPower = verify.TxPower; + 6926 .loc 1 2937 0 + 6927 0274 03AB add r3, sp, #12 + 6928 0276 0022 movs r2, #0 + 6929 0278 9A56 ldrsb r2, [r3, r2] + 6930 027a 3C4B ldr r3, .L400+76 + 6931 027c 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6932 .loc 1 2689 0 + 6933 027e 0020 movs r0, #0 + 6934 0280 31E0 b .L345 + 6935 .LVL650: + 6936 .L368: +2938:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2939:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2940:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2941:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2942:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2943:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2944:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2945:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_CHANNELS_TX_POWER: +2946:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2947:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.TxPower = mibSet->Param.ChannelsTxPower; + 6937 .loc 1 2947 0 + 6938 0282 0423 movs r3, #4 + 6939 0284 C356 ldrsb r3, [r0, r3] + 6940 0286 03A9 add r1, sp, #12 + 6941 0288 0B70 strb r3, [r1] +2948:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2949:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_TX_POWER ) == true ) + 6942 .loc 1 2949 0 + 6943 028a 334B ldr r3, .L400+56 + 6944 028c 1878 ldrb r0, [r3] + 6945 .LVL651: + 6946 028e 0722 movs r2, #7 + 6947 0290 FFF7FEFF bl RegionVerify + 6948 .LVL652: + 6949 0294 0028 cmp r0, #0 + ARM GAS /tmp/ccrFaSdZ.s page 188 + + + 6950 0296 40D0 beq .L396 +2950:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2951:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsTxPower = verify.TxPower; + 6951 .loc 1 2951 0 + 6952 0298 03AB add r3, sp, #12 + 6953 029a 0022 movs r2, #0 + 6954 029c 9A56 ldrsb r2, [r3, r2] + 6955 029e 2D4B ldr r3, .L400+52 + 6956 02a0 1A70 strb r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6957 .loc 1 2689 0 + 6958 02a2 0020 movs r0, #0 + 6959 02a4 1FE0 b .L345 + 6960 .LVL653: + 6961 .L370: +2952:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2953:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +2954:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2955:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_PARAMETER_INVALID; +2956:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2957:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2958:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2959:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_UPLINK_COUNTER: +2960:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2961:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter = mibSet->Param.UpLinkCounter; + 6962 .loc 1 2961 0 + 6963 02a6 4268 ldr r2, [r0, #4] + 6964 02a8 314B ldr r3, .L400+80 + 6965 02aa 1A60 str r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6966 .loc 1 2689 0 + 6967 02ac 0020 movs r0, #0 + 6968 .LVL654: +2962:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6969 .loc 1 2962 0 + 6970 02ae 1AE0 b .L345 + 6971 .LVL655: + 6972 .L371: +2963:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2964:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_DOWNLINK_COUNTER: +2965:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2966:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DownLinkCounter = mibSet->Param.DownLinkCounter; + 6973 .loc 1 2966 0 + 6974 02b0 4268 ldr r2, [r0, #4] + 6975 02b2 304B ldr r3, .L400+84 + 6976 02b4 1A60 str r2, [r3] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6977 .loc 1 2689 0 + 6978 02b6 0020 movs r0, #0 + 6979 .LVL656: +2967:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6980 .loc 1 2967 0 + 6981 02b8 15E0 b .L345 + 6982 .LVL657: + 6983 .L372: +2968:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2969:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_SYSTEM_MAX_RX_ERROR: + ARM GAS /tmp/ccrFaSdZ.s page 189 + + +2970:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2971:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.SystemMaxRxError = LoRaMacParamsDefaults.SystemMaxRxError = mibSet->Param + 6984 .loc 1 2971 0 + 6985 02ba 4368 ldr r3, [r0, #4] + 6986 02bc 2B4A ldr r2, .L400+76 + 6987 02be 5360 str r3, [r2, #4] + 6988 02c0 244A ldr r2, .L400+52 + 6989 02c2 5360 str r3, [r2, #4] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 6990 .loc 1 2689 0 + 6991 02c4 0020 movs r0, #0 + 6992 .LVL658: +2972:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 6993 .loc 1 2972 0 + 6994 02c6 0EE0 b .L345 + 6995 .LVL659: + 6996 .L373: +2973:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2974:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_MIN_RX_SYMBOLS: +2975:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2976:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.MinRxSymbols = LoRaMacParamsDefaults.MinRxSymbols = mibSet->Param.MinRxSy + 6997 .loc 1 2976 0 + 6998 02c8 0379 ldrb r3, [r0, #4] + 6999 02ca 284A ldr r2, .L400+76 + 7000 02cc 1372 strb r3, [r2, #8] + 7001 02ce 214A ldr r2, .L400+52 + 7002 02d0 1372 strb r3, [r2, #8] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 7003 .loc 1 2689 0 + 7004 02d2 0020 movs r0, #0 + 7005 .LVL660: +2977:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7006 .loc 1 2977 0 + 7007 02d4 07E0 b .L345 + 7008 .LVL661: + 7009 .L374: +2978:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2979:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MIB_ANTENNA_GAIN: +2980:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2981:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.AntennaGain = mibSet->Param.AntennaGain; + 7010 .loc 1 2981 0 + 7011 02d6 4268 ldr r2, [r0, #4] + 7012 02d8 1E4B ldr r3, .L400+52 + 7013 02da 5A63 str r2, [r3, #52] +2689:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChanMaskSetParams_t chanMaskSet; + 7014 .loc 1 2689 0 + 7015 02dc 0020 movs r0, #0 + 7016 .LVL662: +2982:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7017 .loc 1 2982 0 + 7018 02de 02E0 b .L345 + 7019 .LVL663: + 7020 .L379: +2695:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7021 .loc 1 2695 0 + 7022 02e0 0320 movs r0, #3 + 7023 .LVL664: + ARM GAS /tmp/ccrFaSdZ.s page 190 + + + 7024 02e2 00E0 b .L345 + 7025 .LVL665: + 7026 .L380: +2699:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7027 .loc 1 2699 0 + 7028 02e4 0120 movs r0, #1 + 7029 .LVL666: + 7030 .L345: +2983:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2984:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +2985:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = LORAMAC_STATUS_SERVICE_UNKNOWN; +2986:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +2987:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +2988:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2989:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +2990:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7031 .loc 1 2990 0 + 7032 02e6 06B0 add sp, sp, #24 + 7033 @ sp needed + 7034 02e8 70BD pop {r4, r5, r6, pc} + 7035 .LVL667: + 7036 .L381: +2985:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7037 .loc 1 2985 0 + 7038 02ea 0220 movs r0, #2 + 7039 .LVL668: + 7040 02ec FBE7 b .L345 + 7041 .LVL669: + 7042 .L383: +2758:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7043 .loc 1 2758 0 + 7044 02ee 0320 movs r0, #3 + 7045 .LVL670: + 7046 02f0 F9E7 b .L345 + 7047 .LVL671: + 7048 .L384: +2771:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7049 .loc 1 2771 0 + 7050 02f2 0320 movs r0, #3 + 7051 .LVL672: + 7052 02f4 F7E7 b .L345 + 7053 .L385: +2824:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7054 .loc 1 2824 0 + 7055 02f6 0320 movs r0, #3 + 7056 02f8 F5E7 b .L345 + 7057 .LVL673: + 7058 .L388: +2818:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7059 .loc 1 2818 0 + 7060 02fa 0320 movs r0, #3 + 7061 02fc F3E7 b .L345 + 7062 .LVL674: + 7063 .L389: +2839:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7064 .loc 1 2839 0 + 7065 02fe 0320 movs r0, #3 + ARM GAS /tmp/ccrFaSdZ.s page 191 + + + 7066 0300 F1E7 b .L345 + 7067 .L390: +2850:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7068 .loc 1 2850 0 + 7069 0302 0320 movs r0, #3 + 7070 0304 EFE7 b .L345 + 7071 .L391: +2861:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7072 .loc 1 2861 0 + 7073 0306 0320 movs r0, #3 + 7074 0308 EDE7 b .L345 + 7075 .LVL675: + 7076 .L392: +2874:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7077 .loc 1 2874 0 + 7078 030a 0320 movs r0, #3 + 7079 .LVL676: + 7080 030c EBE7 b .L345 + 7081 .L393: +2913:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7082 .loc 1 2913 0 + 7083 030e 0320 movs r0, #3 + 7084 0310 E9E7 b .L345 + 7085 .L394: +2927:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7086 .loc 1 2927 0 + 7087 0312 0320 movs r0, #3 + 7088 0314 E7E7 b .L345 + 7089 .L395: +2941:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7090 .loc 1 2941 0 + 7091 0316 0320 movs r0, #3 + 7092 0318 E5E7 b .L345 + 7093 .L396: +2955:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7094 .loc 1 2955 0 + 7095 031a 0320 movs r0, #3 + 7096 031c E3E7 b .L345 + 7097 .L401: + 7098 031e C046 .align 2 + 7099 .L400: + 7100 0320 00000000 .word .LANCHOR24 + 7101 0324 00000000 .word .L347 + 7102 0328 00000000 .word .LANCHOR25 + 7103 032c 00000000 .word Radio + 7104 0330 00000000 .word .LANCHOR15 + 7105 0334 00000000 .word .LANCHOR0 + 7106 0338 00000000 .word .LANCHOR29 + 7107 033c 00000000 .word .LANCHOR40 + 7108 0340 00000000 .word .LANCHOR41 + 7109 0344 00000000 .word .LANCHOR33 + 7110 0348 00000000 .word .LANCHOR32 + 7111 034c 00000000 .word .LANCHOR63 + 7112 0350 00000000 .word .LANCHOR21 + 7113 0354 00000000 .word .LANCHOR14 + 7114 0358 00000000 .word .LANCHOR22 + 7115 035c 00000000 .word .LANCHOR42 + ARM GAS /tmp/ccrFaSdZ.s page 192 + + + 7116 0360 00000000 .word .LANCHOR19 + 7117 0364 00000000 .word .LANCHOR35 + 7118 0368 00000000 .word .LANCHOR36 + 7119 036c 00000000 .word .LANCHOR13 + 7120 0370 00000000 .word .LANCHOR1 + 7121 0374 00000000 .word .LANCHOR2 + 7122 .cfi_endproc + 7123 .LFE112: + 7125 .section .text.LoRaMacChannelAdd,"ax",%progbits + 7126 .align 1 + 7127 .global LoRaMacChannelAdd + 7128 .syntax unified + 7129 .code 16 + 7130 .thumb_func + 7131 .fpu softvfp + 7133 LoRaMacChannelAdd: + 7134 .LFB113: +2991:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2992:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacChannelAdd( uint8_t id, ChannelParams_t params ) +2993:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7135 .loc 1 2993 0 + 7136 .cfi_startproc + 7137 @ args = 0, pretend = 0, frame = 24 + 7138 @ frame_needed = 0, uses_anonymous_args = 0 + 7139 .LVL677: + 7140 0000 00B5 push {lr} + 7141 .LCFI43: + 7142 .cfi_def_cfa_offset 4 + 7143 .cfi_offset 14, -4 + 7144 0002 87B0 sub sp, sp, #28 + 7145 .LCFI44: + 7146 .cfi_def_cfa_offset 32 + 7147 0004 0191 str r1, [sp, #4] + 7148 0006 0292 str r2, [sp, #8] + 7149 0008 0393 str r3, [sp, #12] +2994:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelAddParams_t channelAdd; +2995:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +2996:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Validate if the MAC is in a correct state +2997:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 7150 .loc 1 2997 0 + 7151 000a 094B ldr r3, .L406 + 7152 000c 1B68 ldr r3, [r3] + 7153 000e DA07 lsls r2, r3, #31 + 7154 0010 01D5 bpl .L403 +2998:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +2999:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_CONFIG ) != LORAMAC_TX_CONFIG ) + 7155 .loc 1 2999 0 + 7156 0012 9B06 lsls r3, r3, #26 + 7157 0014 09D5 bpl .L405 + 7158 .L403: +3000:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3001:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +3002:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3003:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3004:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3005:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** channelAdd.NewChannel = ¶ms; + 7159 .loc 1 3005 0 + ARM GAS /tmp/ccrFaSdZ.s page 193 + + + 7160 0016 04A9 add r1, sp, #16 + 7161 0018 01AB add r3, sp, #4 + 7162 001a 0493 str r3, [sp, #16] +3006:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** channelAdd.ChannelId = id; + 7163 .loc 1 3006 0 + 7164 001c 0871 strb r0, [r1, #4] +3007:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3008:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return RegionChannelAdd( LoRaMacRegion, &channelAdd ); + 7165 .loc 1 3008 0 + 7166 001e 054B ldr r3, .L406+4 + 7167 0020 1878 ldrb r0, [r3] + 7168 .LVL678: + 7169 0022 FFF7FEFF bl RegionChannelAdd + 7170 .LVL679: + 7171 .L404: +3009:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7172 .loc 1 3009 0 + 7173 0026 07B0 add sp, sp, #28 + 7174 @ sp needed + 7175 0028 00BD pop {pc} + 7176 .LVL680: + 7177 .L405: +3001:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7178 .loc 1 3001 0 + 7179 002a 0120 movs r0, #1 + 7180 .LVL681: + 7181 002c FBE7 b .L404 + 7182 .L407: + 7183 002e C046 .align 2 + 7184 .L406: + 7185 0030 00000000 .word .LANCHOR24 + 7186 0034 00000000 .word .LANCHOR22 + 7187 .cfi_endproc + 7188 .LFE113: + 7190 .section .text.LoRaMacChannelRemove,"ax",%progbits + 7191 .align 1 + 7192 .global LoRaMacChannelRemove + 7193 .syntax unified + 7194 .code 16 + 7195 .thumb_func + 7196 .fpu softvfp + 7198 LoRaMacChannelRemove: + 7199 .LFB114: +3010:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3011:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacChannelRemove( uint8_t id ) +3012:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7200 .loc 1 3012 0 + 7201 .cfi_startproc + 7202 @ args = 0, pretend = 0, frame = 8 + 7203 @ frame_needed = 0, uses_anonymous_args = 0 + 7204 .LVL682: + 7205 0000 00B5 push {lr} + 7206 .LCFI45: + 7207 .cfi_def_cfa_offset 4 + 7208 .cfi_offset 14, -4 + 7209 0002 83B0 sub sp, sp, #12 + 7210 .LCFI46: + ARM GAS /tmp/ccrFaSdZ.s page 194 + + + 7211 .cfi_def_cfa_offset 16 +3013:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ChannelRemoveParams_t channelRemove; +3014:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3015:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 7212 .loc 1 3015 0 + 7213 0004 0A4B ldr r3, .L414 + 7214 0006 1B68 ldr r3, [r3] + 7215 0008 DA07 lsls r2, r3, #31 + 7216 000a 01D5 bpl .L409 +3016:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3017:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_CONFIG ) != LORAMAC_TX_CONFIG ) + 7217 .loc 1 3017 0 + 7218 000c 9B06 lsls r3, r3, #26 + 7219 000e 0CD5 bpl .L411 + 7220 .L409: +3018:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3019:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +3020:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3021:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3022:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3023:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** channelRemove.ChannelId = id; + 7221 .loc 1 3023 0 + 7222 0010 01A9 add r1, sp, #4 + 7223 0012 0870 strb r0, [r1] +3024:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3025:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionChannelsRemove( LoRaMacRegion, &channelRemove ) == false ) + 7224 .loc 1 3025 0 + 7225 0014 074B ldr r3, .L414+4 + 7226 0016 1878 ldrb r0, [r3] + 7227 .LVL683: + 7228 0018 FFF7FEFF bl RegionChannelsRemove + 7229 .LVL684: + 7230 001c 0028 cmp r0, #0 + 7231 001e 02D0 beq .L413 +3026:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3027:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3028:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3029:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 7232 .loc 1 3029 0 + 7233 0020 0020 movs r0, #0 + 7234 .L410: +3030:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7235 .loc 1 3030 0 + 7236 0022 03B0 add sp, sp, #12 + 7237 @ sp needed + 7238 0024 00BD pop {pc} + 7239 .L413: +3027:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7240 .loc 1 3027 0 + 7241 0026 0330 adds r0, r0, #3 + 7242 0028 FBE7 b .L410 + 7243 .LVL685: + 7244 .L411: +3019:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7245 .loc 1 3019 0 + 7246 002a 0120 movs r0, #1 + 7247 .LVL686: + ARM GAS /tmp/ccrFaSdZ.s page 195 + + + 7248 002c F9E7 b .L410 + 7249 .L415: + 7250 002e C046 .align 2 + 7251 .L414: + 7252 0030 00000000 .word .LANCHOR24 + 7253 0034 00000000 .word .LANCHOR22 + 7254 .cfi_endproc + 7255 .LFE114: + 7257 .section .text.LoRaMacMulticastChannelLink,"ax",%progbits + 7258 .align 1 + 7259 .global LoRaMacMulticastChannelLink + 7260 .syntax unified + 7261 .code 16 + 7262 .thumb_func + 7263 .fpu softvfp + 7265 LoRaMacMulticastChannelLink: + 7266 .LFB115: +3031:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3032:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMulticastChannelLink( MulticastParams_t *channelParam ) +3033:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7267 .loc 1 3033 0 + 7268 .cfi_startproc + 7269 @ args = 0, pretend = 0, frame = 0 + 7270 @ frame_needed = 0, uses_anonymous_args = 0 + 7271 @ link register save eliminated. + 7272 .LVL687: +3034:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( channelParam == NULL ) + 7273 .loc 1 3034 0 + 7274 0000 0028 cmp r0, #0 + 7275 0002 13D0 beq .L419 +3035:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3036:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3037:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3038:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 7276 .loc 1 3038 0 + 7277 0004 0B4B ldr r3, .L422 + 7278 0006 1B68 ldr r3, [r3] + 7279 0008 DB07 lsls r3, r3, #31 + 7280 000a 11D4 bmi .L420 +3039:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3040:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +3041:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3042:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3043:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset downlink counter +3044:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** channelParam->DownLinkCounter = 0; + 7281 .loc 1 3044 0 + 7282 000c 0023 movs r3, #0 + 7283 000e 4362 str r3, [r0, #36] +3045:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3046:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MulticastChannels == NULL ) + 7284 .loc 1 3046 0 + 7285 0010 094B ldr r3, .L422+4 + 7286 0012 1A68 ldr r2, [r3] + 7287 0014 002A cmp r2, #0 + 7288 0016 03D1 bne .L418 +3047:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3048:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // New node is the fist element + ARM GAS /tmp/ccrFaSdZ.s page 196 + + +3049:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastChannels = channelParam; + 7289 .loc 1 3049 0 + 7290 0018 1860 str r0, [r3] +3050:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3051:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +3052:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3053:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastParams_t *cur = MulticastChannels; +3054:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3055:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Search the last node in the list +3056:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( cur->Next != NULL ) +3057:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3058:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur = cur->Next; +3059:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3060:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // This function always finds the last node +3061:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur->Next = channelParam; +3062:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3063:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3064:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 7291 .loc 1 3064 0 + 7292 001a 0020 movs r0, #0 + 7293 .LVL688: + 7294 001c 09E0 b .L417 + 7295 .LVL689: + 7296 .L421: + 7297 .LBB85: +3058:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7298 .loc 1 3058 0 + 7299 001e 1A00 movs r2, r3 + 7300 .LVL690: + 7301 .L418: +3056:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7302 .loc 1 3056 0 + 7303 0020 936A ldr r3, [r2, #40] + 7304 0022 002B cmp r3, #0 + 7305 0024 FBD1 bne .L421 +3061:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7306 .loc 1 3061 0 + 7307 0026 9062 str r0, [r2, #40] + 7308 .LBE85: + 7309 .loc 1 3064 0 + 7310 0028 0020 movs r0, #0 + 7311 .LVL691: + 7312 002a 02E0 b .L417 + 7313 .LVL692: + 7314 .L419: +3036:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7315 .loc 1 3036 0 + 7316 002c 0320 movs r0, #3 + 7317 .LVL693: + 7318 002e 00E0 b .L417 + 7319 .LVL694: + 7320 .L420: +3040:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7321 .loc 1 3040 0 + 7322 0030 0120 movs r0, #1 + 7323 .LVL695: + 7324 .L417: + ARM GAS /tmp/ccrFaSdZ.s page 197 + + +3065:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7325 .loc 1 3065 0 + 7326 @ sp needed + 7327 0032 7047 bx lr + 7328 .L423: + 7329 .align 2 + 7330 .L422: + 7331 0034 00000000 .word .LANCHOR24 + 7332 0038 00000000 .word .LANCHOR18 + 7333 .cfi_endproc + 7334 .LFE115: + 7336 .section .text.LoRaMacMulticastChannelUnlink,"ax",%progbits + 7337 .align 1 + 7338 .global LoRaMacMulticastChannelUnlink + 7339 .syntax unified + 7340 .code 16 + 7341 .thumb_func + 7342 .fpu softvfp + 7344 LoRaMacMulticastChannelUnlink: + 7345 .LFB116: +3066:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3067:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMulticastChannelUnlink( MulticastParams_t *channelParam ) +3068:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7346 .loc 1 3068 0 + 7347 .cfi_startproc + 7348 @ args = 0, pretend = 0, frame = 0 + 7349 @ frame_needed = 0, uses_anonymous_args = 0 + 7350 @ link register save eliminated. + 7351 .LVL696: +3069:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( channelParam == NULL ) + 7352 .loc 1 3069 0 + 7353 0000 0028 cmp r0, #0 + 7354 0002 1AD0 beq .L429 +3070:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3071:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3072:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3073:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 7355 .loc 1 3073 0 + 7356 0004 104B ldr r3, .L433 + 7357 0006 1B68 ldr r3, [r3] + 7358 0008 DB07 lsls r3, r3, #31 + 7359 000a 18D4 bmi .L430 +3074:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3075:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +3076:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3077:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3078:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MulticastChannels != NULL ) + 7360 .loc 1 3078 0 + 7361 000c 0F4B ldr r3, .L433+4 + 7362 000e 1A68 ldr r2, [r3] + 7363 0010 002A cmp r2, #0 + 7364 0012 16D0 beq .L431 +3079:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3080:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( MulticastChannels == channelParam ) + 7365 .loc 1 3080 0 + 7366 0014 8242 cmp r2, r0 + 7367 0016 03D1 bne .L426 + ARM GAS /tmp/ccrFaSdZ.s page 198 + + +3081:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3082:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // First element +3083:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastChannels = channelParam->Next; + 7368 .loc 1 3083 0 + 7369 0018 826A ldr r2, [r0, #40] + 7370 001a 1A60 str r2, [r3] + 7371 001c 09E0 b .L427 + 7372 .LVL697: + 7373 .L432: + 7374 .LBB86: +3084:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3085:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +3086:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3087:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MulticastParams_t *cur = MulticastChannels; +3088:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3089:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Search the node in the list +3090:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** while( cur->Next && cur->Next != channelParam ) +3091:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3092:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur = cur->Next; + 7375 .loc 1 3092 0 + 7376 001e 1A00 movs r2, r3 + 7377 .LVL698: + 7378 .L426: +3090:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7379 .loc 1 3090 0 + 7380 0020 936A ldr r3, [r2, #40] + 7381 0022 002B cmp r3, #0 + 7382 0024 01D0 beq .L428 +3090:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7383 .loc 1 3090 0 is_stmt 0 discriminator 1 + 7384 0026 8342 cmp r3, r0 + 7385 0028 F9D1 bne .L432 + 7386 .L428: +3093:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3094:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // If we found the node, remove it +3095:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( cur->Next ) + 7387 .loc 1 3095 0 is_stmt 1 + 7388 002a 002B cmp r3, #0 + 7389 002c 01D0 beq .L427 +3096:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3097:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** cur->Next = channelParam->Next; + 7390 .loc 1 3097 0 + 7391 002e 836A ldr r3, [r0, #40] + 7392 0030 9362 str r3, [r2, #40] + 7393 .LVL699: + 7394 .L427: + 7395 .LBE86: +3098:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3099:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3100:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** channelParam->Next = NULL; + 7396 .loc 1 3100 0 + 7397 0032 0023 movs r3, #0 + 7398 0034 8362 str r3, [r0, #40] +3101:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3102:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_OK; + 7399 .loc 1 3103 0 + ARM GAS /tmp/ccrFaSdZ.s page 199 + + + 7400 0036 0020 movs r0, #0 + 7401 .LVL700: + 7402 0038 02E0 b .L425 + 7403 .LVL701: + 7404 .L429: +3071:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7405 .loc 1 3071 0 + 7406 003a 0320 movs r0, #3 + 7407 .LVL702: + 7408 003c 00E0 b .L425 + 7409 .LVL703: + 7410 .L430: +3075:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7411 .loc 1 3075 0 + 7412 003e 0120 movs r0, #1 + 7413 .LVL704: + 7414 .L425: +3104:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7415 .loc 1 3104 0 + 7416 @ sp needed + 7417 0040 7047 bx lr + 7418 .LVL705: + 7419 .L431: +3103:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7420 .loc 1 3103 0 + 7421 0042 0020 movs r0, #0 + 7422 .LVL706: + 7423 0044 FCE7 b .L425 + 7424 .L434: + 7425 0046 C046 .align 2 + 7426 .L433: + 7427 0048 00000000 .word .LANCHOR24 + 7428 004c 00000000 .word .LANCHOR18 + 7429 .cfi_endproc + 7430 .LFE116: + 7432 .section .text.LoRaMacMlmeRequest,"ax",%progbits + 7433 .align 1 + 7434 .global LoRaMacMlmeRequest + 7435 .syntax unified + 7436 .code 16 + 7437 .thumb_func + 7438 .fpu softvfp + 7440 LoRaMacMlmeRequest: + 7441 .LFB117: +3105:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3106:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMlmeRequest( MlmeReq_t *mlmeRequest ) +3107:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7442 .loc 1 3107 0 + 7443 .cfi_startproc + 7444 @ args = 0, pretend = 0, frame = 16 + 7445 @ frame_needed = 0, uses_anonymous_args = 0 + 7446 .LVL707: + 7447 0000 30B5 push {r4, r5, lr} + 7448 .LCFI47: + 7449 .cfi_def_cfa_offset 12 + 7450 .cfi_offset 4, -12 + 7451 .cfi_offset 5, -8 + ARM GAS /tmp/ccrFaSdZ.s page 200 + + + 7452 .cfi_offset 14, -4 + 7453 0002 85B0 sub sp, sp, #20 + 7454 .LCFI48: + 7455 .cfi_def_cfa_offset 32 + 7456 0004 041E subs r4, r0, #0 + 7457 .LVL708: +3108:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_SERVICE_UNKNOWN; +3109:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; +3110:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AlternateDrParams_t altDr; +3111:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** VerifyParams_t verify; +3112:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +3113:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +3114:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3115:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mlmeRequest == NULL ) + 7458 .loc 1 3115 0 + 7459 0006 00D1 bne .LCB7174 + 7460 0008 B0E0 b .L444 @long jump + 7461 .LCB7174: +3116:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3118:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3119:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) + 7462 .loc 1 3119 0 + 7463 000a 5E4B ldr r3, .L457 + 7464 000c 1B68 ldr r3, [r3] + 7465 000e DB07 lsls r3, r3, #31 + 7466 0010 02D5 bpl .L454 +3120:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3121:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; + 7467 .loc 1 3121 0 + 7468 0012 0120 movs r0, #1 + 7469 .LVL709: + 7470 .L436: +3122:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3123:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memset1( ( uint8_t* ) &MlmeConfirm, 0, sizeof( MlmeConfirm ) ); +3125:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; +3127:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( mlmeRequest->Type ) +3129:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3130:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MLME_JOIN: +3131:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( LoRaMacState & LORAMAC_TX_DELAYED ) == LORAMAC_TX_DELAYED ) +3133:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; +3135:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3136:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( mlmeRequest->Req.Join.DevEui == NULL ) || +3138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.AppEui == NULL ) || +3139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.AppKey == NULL ) || +3140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.NbTrials == 0 ) ) +3141:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3142:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3143:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3144:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3145:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Verify the parameter NbTrials for the join procedure + ARM GAS /tmp/ccrFaSdZ.s page 201 + + +3146:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.NbJoinTrials = mlmeRequest->Req.Join.NbTrials; +3147:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_NB_JOIN_TRIALS ) == false ) +3149:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3150:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Value not supported, get default +3151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_DEF_NB_JOIN_TRIALS; +3152:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); +3153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mlmeRequest->Req.Join.NbTrials = ( uint8_t ) phyParam.Value; +3154:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3155:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; +3157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.MlmeRequest = mlmeRequest->Type; +3158:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3159:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacDevEui = mlmeRequest->Req.Join.DevEui; +3160:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacAppEui = mlmeRequest->Req.Join.AppEui; +3161:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacAppKey = mlmeRequest->Req.Join.AppKey; +3162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MaxJoinRequestTrials = mlmeRequest->Req.Join.NbTrials; +3163:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3164:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Reset variable JoinRequestTrials +3165:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** JoinRequestTrials = 0; +3166:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3167:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Setup header information +3168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Value = 0; +3169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; +3170:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ResetMacParameters( ); +3172:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** altDr.NbTrials = JoinRequestTrials + 1; +3174:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = RegionAlternateDr( LoRaMacRegion, &altDr ); +3176:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3177:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = Send( &macHdr, 0, NULL, 0 ); +3178:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3179:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3180:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MLME_LINK_CHECK: +3181:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; +3183:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // LoRaMac will send this command piggy-pack +3184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.MlmeRequest = mlmeRequest->Type; +3185:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3186:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = AddMacCommand( MOTE_MAC_LINK_CHECK_REQ, 0, 0 ); +3187:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3188:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3189:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MLME_TXCW: +3190:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.MlmeRequest = mlmeRequest->Type; +3192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; +3193:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = SetTxContinuousWave( mlmeRequest->Req.TxCw.Timeout ); +3194:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3195:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3196:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MLME_TXCW_1: +3197:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.MlmeRequest = mlmeRequest->Type; +3199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; +3200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = SetTxContinuousWave1( mlmeRequest->Req.TxCw.Timeout, mlmeRequest->Req.TxCw.Fre +3201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3202:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 202 + + +3203:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +3204:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3205:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3206:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3207:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( status != LORAMAC_STATUS_OK ) +3208:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; +3210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 0; +3211:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3212:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3213:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +3214:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7471 .loc 1 3214 0 + 7472 0014 05B0 add sp, sp, #20 + 7473 @ sp needed + 7474 0016 30BD pop {r4, r5, pc} + 7475 .LVL710: + 7476 .L454: +3124:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7477 .loc 1 3124 0 + 7478 0018 5B4D ldr r5, .L457+4 + 7479 001a 0C22 movs r2, #12 + 7480 001c 0021 movs r1, #0 + 7481 001e 2800 movs r0, r5 + 7482 .LVL711: + 7483 0020 FFF7FEFF bl memset1 + 7484 .LVL712: +3126:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7485 .loc 1 3126 0 + 7486 0024 0123 movs r3, #1 + 7487 0026 6B70 strb r3, [r5, #1] +3128:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7488 .loc 1 3128 0 + 7489 0028 2378 ldrb r3, [r4] + 7490 002a 012B cmp r3, #1 + 7491 002c 5CD0 beq .L438 + 7492 002e 002B cmp r3, #0 + 7493 0030 06D0 beq .L439 + 7494 0032 022B cmp r3, #2 + 7495 0034 77D0 beq .L440 + 7496 0036 032B cmp r3, #3 + 7497 0038 00D1 bne .LCB7217 + 7498 003a 8AE0 b .L441 @long jump + 7499 .LCB7217: +3108:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + 7500 .loc 1 3108 0 + 7501 003c 0220 movs r0, #2 + 7502 003e 7FE0 b .L437 + 7503 .L439: +3132:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7504 .loc 1 3132 0 + 7505 0040 504B ldr r3, .L457 + 7506 0042 1B68 ldr r3, [r3] + 7507 0044 DB06 lsls r3, r3, #27 + 7508 0046 00D5 bpl .LCB7228 + 7509 0048 92E0 b .L447 @long jump + 7510 .LCB7228: + ARM GAS /tmp/ccrFaSdZ.s page 203 + + +3137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.AppEui == NULL ) || + 7511 .loc 1 3137 0 + 7512 004a 6368 ldr r3, [r4, #4] + 7513 004c 002B cmp r3, #0 + 7514 004e 00D1 bne .LCB7232 + 7515 0050 90E0 b .L448 @long jump + 7516 .LCB7232: +3137:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.AppEui == NULL ) || + 7517 .loc 1 3137 0 is_stmt 0 discriminator 1 + 7518 0052 A368 ldr r3, [r4, #8] + 7519 0054 002B cmp r3, #0 + 7520 0056 00D1 bne .LCB7236 + 7521 0058 8EE0 b .L449 @long jump + 7522 .LCB7236: +3138:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.AppKey == NULL ) || + 7523 .loc 1 3138 0 is_stmt 1 + 7524 005a E368 ldr r3, [r4, #12] + 7525 005c 002B cmp r3, #0 + 7526 005e 00D1 bne .LCB7240 + 7527 0060 8CE0 b .L450 @long jump + 7528 .LCB7240: +3140:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7529 .loc 1 3140 0 + 7530 0062 237C ldrb r3, [r4, #16] +3139:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( mlmeRequest->Req.Join.NbTrials == 0 ) ) + 7531 .loc 1 3139 0 + 7532 0064 002B cmp r3, #0 + 7533 0066 00D1 bne .LCB7243 + 7534 0068 8AE0 b .L451 @long jump + 7535 .LCB7243: +3146:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7536 .loc 1 3146 0 + 7537 006a 01A9 add r1, sp, #4 + 7538 006c 0B70 strb r3, [r1] +3148:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7539 .loc 1 3148 0 + 7540 006e 474B ldr r3, .L457+8 + 7541 0070 1878 ldrb r0, [r3] + 7542 0072 1E22 movs r2, #30 + 7543 0074 FFF7FEFF bl RegionVerify + 7544 .LVL713: + 7545 0078 0028 cmp r0, #0 + 7546 007a 2BD0 beq .L455 + 7547 .LVL714: + 7548 .L442: +3156:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MlmeConfirm.MlmeRequest = mlmeRequest->Type; + 7549 .loc 1 3156 0 + 7550 007c 444A ldr r2, .L457+12 + 7551 007e 1378 ldrb r3, [r2] + 7552 0080 0821 movs r1, #8 + 7553 0082 0B43 orrs r3, r1 + 7554 0084 1370 strb r3, [r2] +3157:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7555 .loc 1 3157 0 + 7556 0086 2278 ldrb r2, [r4] + 7557 0088 3F4B ldr r3, .L457+4 + 7558 008a 1A70 strb r2, [r3] + ARM GAS /tmp/ccrFaSdZ.s page 204 + + +3159:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacAppEui = mlmeRequest->Req.Join.AppEui; + 7559 .loc 1 3159 0 + 7560 008c 414B ldr r3, .L457+16 + 7561 008e 6268 ldr r2, [r4, #4] + 7562 0090 1A60 str r2, [r3] +3160:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacAppKey = mlmeRequest->Req.Join.AppKey; + 7563 .loc 1 3160 0 + 7564 0092 414B ldr r3, .L457+20 + 7565 0094 A268 ldr r2, [r4, #8] + 7566 0096 1A60 str r2, [r3] +3161:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** MaxJoinRequestTrials = mlmeRequest->Req.Join.NbTrials; + 7567 .loc 1 3161 0 + 7568 0098 404B ldr r3, .L457+24 + 7569 009a E268 ldr r2, [r4, #12] + 7570 009c 1A60 str r2, [r3] +3162:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7571 .loc 1 3162 0 + 7572 009e 227C ldrb r2, [r4, #16] + 7573 00a0 3F4B ldr r3, .L457+28 + 7574 00a2 1A70 strb r2, [r3] +3165:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7575 .loc 1 3165 0 + 7576 00a4 3F4D ldr r5, .L457+32 + 7577 00a6 0023 movs r3, #0 + 7578 00a8 2B70 strb r3, [r5] +3168:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; + 7579 .loc 1 3168 0 + 7580 00aa 03AC add r4, sp, #12 + 7581 .LVL715: +3169:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7582 .loc 1 3169 0 + 7583 00ac 2370 strb r3, [r4] +3171:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7584 .loc 1 3171 0 + 7585 00ae FFF7FEFF bl ResetMacParameters + 7586 .LVL716: +3173:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7587 .loc 1 3173 0 + 7588 00b2 2B78 ldrb r3, [r5] + 7589 00b4 0133 adds r3, r3, #1 + 7590 00b6 02A9 add r1, sp, #8 + 7591 00b8 0B80 strh r3, [r1] +3175:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7592 .loc 1 3175 0 + 7593 00ba 344B ldr r3, .L457+8 + 7594 00bc 1878 ldrb r0, [r3] + 7595 00be FFF7FEFF bl RegionAlternateDr + 7596 .LVL717: + 7597 00c2 394B ldr r3, .L457+36 + 7598 00c4 5870 strb r0, [r3, #1] +3177:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7599 .loc 1 3177 0 + 7600 00c6 0023 movs r3, #0 + 7601 00c8 0022 movs r2, #0 + 7602 00ca 0021 movs r1, #0 + 7603 00cc 2000 movs r0, r4 + 7604 00ce FFF7FEFF bl Send + ARM GAS /tmp/ccrFaSdZ.s page 205 + + + 7605 .LVL718: +3178:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7606 .loc 1 3178 0 + 7607 00d2 32E0 b .L443 + 7608 .LVL719: + 7609 .L455: +3151:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 7610 .loc 1 3151 0 + 7611 00d4 1F23 movs r3, #31 + 7612 00d6 6A46 mov r2, sp + 7613 00d8 1370 strb r3, [r2] +3152:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** mlmeRequest->Req.Join.NbTrials = ( uint8_t ) phyParam.Value; + 7614 .loc 1 3152 0 + 7615 00da 2C4B ldr r3, .L457+8 + 7616 00dc 1878 ldrb r0, [r3] + 7617 00de 6946 mov r1, sp + 7618 00e0 FFF7FEFF bl RegionGetPhyParam + 7619 .LVL720: +3153:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7620 .loc 1 3153 0 + 7621 00e4 2074 strb r0, [r4, #16] + 7622 00e6 C9E7 b .L442 + 7623 .L438: +3182:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // LoRaMac will send this command piggy-pack + 7624 .loc 1 3182 0 + 7625 00e8 294A ldr r2, .L457+12 + 7626 00ea 1378 ldrb r3, [r2] + 7627 00ec 0821 movs r1, #8 + 7628 00ee 0B43 orrs r3, r1 + 7629 00f0 1370 strb r3, [r2] +3184:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7630 .loc 1 3184 0 + 7631 00f2 2278 ldrb r2, [r4] + 7632 00f4 244B ldr r3, .L457+4 + 7633 00f6 1A70 strb r2, [r3] + 7634 .LVL721: + 7635 .LBB87: + 7636 .LBB88: +1553:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7637 .loc 1 1553 0 + 7638 00f8 2C4B ldr r3, .L457+40 + 7639 00fa 1A78 ldrb r2, [r3] + 7640 00fc 8023 movs r3, #128 + 7641 00fe 5B42 rsbs r3, r3, #0 + 7642 0100 9B1A subs r3, r3, r2 + 7643 0102 DBB2 uxtb r3, r3 + 7644 .LVL722: +1558:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7645 .loc 1 1558 0 + 7646 0104 2A4A ldr r2, .L457+44 + 7647 0106 1278 ldrb r2, [r2] + 7648 0108 9342 cmp r3, r2 + 7649 010a 01D8 bhi .L456 +1551:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // The maximum buffer length must take MAC commands to re-send into account. + 7650 .loc 1 1551 0 + 7651 010c 0120 movs r0, #1 + 7652 010e 17E0 b .L437 + ARM GAS /tmp/ccrFaSdZ.s page 206 + + + 7653 .L456: +1560:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // No payload for this command + 7654 .loc 1 1560 0 + 7655 0110 511C adds r1, r2, #1 + 7656 0112 274B ldr r3, .L457+44 + 7657 .LVL723: + 7658 0114 1970 strb r1, [r3] + 7659 0116 274B ldr r3, .L457+48 + 7660 0118 0221 movs r1, #2 + 7661 011a 9954 strb r1, [r3, r2] + 7662 .LVL724: +1641:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7663 .loc 1 1641 0 + 7664 011c 264B ldr r3, .L457+52 + 7665 011e 0122 movs r2, #1 + 7666 0120 1A70 strb r2, [r3] + 7667 .LVL725: + 7668 0122 0020 movs r0, #0 + 7669 0124 76E7 b .L436 + 7670 .LVL726: + 7671 .L440: + 7672 .LBE88: + 7673 .LBE87: +3191:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; + 7674 .loc 1 3191 0 + 7675 0126 184A ldr r2, .L457+4 + 7676 0128 1370 strb r3, [r2] +3192:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = SetTxContinuousWave( mlmeRequest->Req.TxCw.Timeout ); + 7677 .loc 1 3192 0 + 7678 012a 194A ldr r2, .L457+12 + 7679 012c 1378 ldrb r3, [r2] + 7680 012e 0821 movs r1, #8 + 7681 0130 0B43 orrs r3, r1 + 7682 0132 1370 strb r3, [r2] +3193:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7683 .loc 1 3193 0 + 7684 0134 A088 ldrh r0, [r4, #4] + 7685 0136 FFF7FEFF bl SetTxContinuousWave + 7686 .LVL727: + 7687 .L443: +3207:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7688 .loc 1 3207 0 + 7689 013a 0028 cmp r0, #0 + 7690 013c 00D1 bne .LCB7402 + 7691 013e 69E7 b .L436 @long jump + 7692 .LCB7402: + 7693 .LVL728: + 7694 .L437: +3209:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 0; + 7695 .loc 1 3209 0 + 7696 0140 1E4B ldr r3, .L457+56 + 7697 0142 0022 movs r2, #0 + 7698 0144 1A70 strb r2, [r3] +3210:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7699 .loc 1 3210 0 + 7700 0146 124A ldr r2, .L457+12 + 7701 0148 1378 ldrb r3, [r2] + ARM GAS /tmp/ccrFaSdZ.s page 207 + + + 7702 014a 0821 movs r1, #8 + 7703 014c 8B43 bics r3, r1 + 7704 014e 1370 strb r3, [r2] + 7705 0150 60E7 b .L436 + 7706 .LVL729: + 7707 .L441: +3198:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.MlmeReq = 1; + 7708 .loc 1 3198 0 + 7709 0152 0D4A ldr r2, .L457+4 + 7710 0154 1370 strb r3, [r2] +3199:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = SetTxContinuousWave1( mlmeRequest->Req.TxCw.Timeout, mlmeRequest->Req.TxCw.Fre + 7711 .loc 1 3199 0 + 7712 0156 0E4A ldr r2, .L457+12 + 7713 0158 1378 ldrb r3, [r2] + 7714 015a 0821 movs r1, #8 + 7715 015c 0B43 orrs r3, r1 + 7716 015e 1370 strb r3, [r2] +3200:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7717 .loc 1 3200 0 + 7718 0160 A088 ldrh r0, [r4, #4] + 7719 0162 A168 ldr r1, [r4, #8] + 7720 0164 227B ldrb r2, [r4, #12] + 7721 0166 FFF7FEFF bl SetTxContinuousWave1 + 7722 .LVL730: +3201:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7723 .loc 1 3201 0 + 7724 016a E6E7 b .L443 + 7725 .LVL731: + 7726 .L444: +3117:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7727 .loc 1 3117 0 + 7728 016c 0320 movs r0, #3 + 7729 .LVL732: + 7730 016e 51E7 b .L436 + 7731 .L447: +3134:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7732 .loc 1 3134 0 + 7733 0170 0120 movs r0, #1 + 7734 0172 4FE7 b .L436 + 7735 .L448: +3142:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7736 .loc 1 3142 0 + 7737 0174 0320 movs r0, #3 + 7738 0176 4DE7 b .L436 + 7739 .L449: + 7740 0178 0320 movs r0, #3 + 7741 017a 4BE7 b .L436 + 7742 .L450: + 7743 017c 0320 movs r0, #3 + 7744 017e 49E7 b .L436 + 7745 .L451: + 7746 0180 0320 movs r0, #3 + 7747 0182 47E7 b .L436 + 7748 .L458: + 7749 .align 2 + 7750 .L457: + 7751 0184 00000000 .word .LANCHOR24 + ARM GAS /tmp/ccrFaSdZ.s page 208 + + + 7752 0188 00000000 .word .LANCHOR28 + 7753 018c 00000000 .word .LANCHOR22 + 7754 0190 00000000 .word .LANCHOR26 + 7755 0194 00000000 .word .LANCHOR52 + 7756 0198 00000000 .word .LANCHOR51 + 7757 019c 00000000 .word .LANCHOR38 + 7758 01a0 00000000 .word .LANCHOR59 + 7759 01a4 00000000 .word .LANCHOR54 + 7760 01a8 00000000 .word .LANCHOR14 + 7761 01ac 00000000 .word .LANCHOR11 + 7762 01b0 00000000 .word .LANCHOR10 + 7763 01b4 00000000 .word MacCommandsBuffer + 7764 01b8 00000000 .word .LANCHOR17 + 7765 01bc 00000000 .word .LANCHOR15 + 7766 .cfi_endproc + 7767 .LFE117: + 7769 .section .text.LoRaMacMcpsRequest,"ax",%progbits + 7770 .align 1 + 7771 .global LoRaMacMcpsRequest + 7772 .syntax unified + 7773 .code 16 + 7774 .thumb_func + 7775 .fpu softvfp + 7777 LoRaMacMcpsRequest: + 7778 .LFB118: +3215:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3216:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t LoRaMacMcpsRequest( McpsReq_t *mcpsRequest ) +3217:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7779 .loc 1 3217 0 + 7780 .cfi_startproc + 7781 @ args = 0, pretend = 0, frame = 16 + 7782 @ frame_needed = 0, uses_anonymous_args = 0 + 7783 .LVL733: + 7784 0000 F0B5 push {r4, r5, r6, r7, lr} + 7785 .LCFI49: + 7786 .cfi_def_cfa_offset 20 + 7787 .cfi_offset 4, -20 + 7788 .cfi_offset 5, -16 + 7789 .cfi_offset 6, -12 + 7790 .cfi_offset 7, -8 + 7791 .cfi_offset 14, -4 + 7792 0002 CE46 mov lr, r9 + 7793 0004 4746 mov r7, r8 + 7794 0006 80B5 push {r7, lr} + 7795 .LCFI50: + 7796 .cfi_def_cfa_offset 28 + 7797 .cfi_offset 8, -28 + 7798 .cfi_offset 9, -24 + 7799 0008 85B0 sub sp, sp, #20 + 7800 .LCFI51: + 7801 .cfi_def_cfa_offset 48 + 7802 000a 041E subs r4, r0, #0 + 7803 .LVL734: +3218:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** GetPhyParams_t getPhy; +3219:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** PhyParam_t phyParam; +3220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacStatus_t status = LORAMAC_STATUS_SERVICE_UNKNOWN; +3221:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + ARM GAS /tmp/ccrFaSdZ.s page 209 + + +3222:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** VerifyParams_t verify; +3223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint8_t fPort = 0; +3224:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void *fBuffer; +3225:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** uint16_t fBufferSize; +3226:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** int8_t datarate; +3227:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** bool readyToSend = false; +3228:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3229:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( mcpsRequest == NULL ) + 7804 .loc 1 3229 0 + 7805 000c 00D1 bne .LCB7518 + 7806 000e 96E0 b .L468 @long jump + 7807 .LCB7518: +3230:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3231:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3232:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3233:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) || + 7808 .loc 1 3233 0 + 7809 0010 1123 movs r3, #17 + 7810 0012 4E4A ldr r2, .L476 + 7811 0014 1268 ldr r2, [r2] + 7812 0016 1A42 tst r2, r3 + 7813 0018 05D0 beq .L474 +3234:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** ( ( LoRaMacState & LORAMAC_TX_DELAYED ) == LORAMAC_TX_DELAYED ) ) +3235:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3236:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_BUSY; + 7814 .loc 1 3236 0 + 7815 001a 0120 movs r0, #1 + 7816 .LVL735: + 7817 .L460: +3237:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3238:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3239:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Value = 0; +3240:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memset1 ( ( uint8_t* ) &McpsConfirm, 0, sizeof( McpsConfirm ) ); +3241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; +3242:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3243:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // AckTimeoutRetriesCounter must be reset every time a new request (unconfirmed or confirmed) i +3244:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetriesCounter = 1; +3245:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3246:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** switch( mcpsRequest->Type ) +3247:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3248:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MCPS_UNCONFIRMED: +3249:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3250:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** readyToSend = true; +3251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = 1; +3252:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_DATA_UNCONFIRMED_UP; +3254:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fPort = mcpsRequest->Req.Unconfirmed.fPort; +3255:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Unconfirmed.fBuffer; +3256:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Unconfirmed.fBufferSize; +3257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Unconfirmed.Datarate; +3258:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3259:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3260:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MCPS_CONFIRMED: +3261:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3262:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** readyToSend = true; +3263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = mcpsRequest->Req.Confirmed.NbTrials; +3264:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + ARM GAS /tmp/ccrFaSdZ.s page 210 + + +3265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_DATA_CONFIRMED_UP; +3266:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fPort = mcpsRequest->Req.Confirmed.fPort; +3267:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Confirmed.fBuffer; +3268:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Confirmed.fBufferSize; +3269:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Confirmed.Datarate; +3270:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3271:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3272:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** case MCPS_PROPRIETARY: +3273:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3274:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** readyToSend = true; +3275:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = 1; +3276:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** macHdr.Bits.MType = FRAME_TYPE_PROPRIETARY; +3278:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Proprietary.fBuffer; +3279:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Proprietary.fBufferSize; +3280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Proprietary.Datarate; +3281:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3282:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3283:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** default: +3284:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; +3285:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3286:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3287:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Get the minimum possible datarate +3288:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.Attribute = PHY_MIN_TX_DR; +3289:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +3290:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); +3291:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Apply the minimum possible datarate. +3292:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Some regions have limitations for the minimum datarate. +3293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = MAX( datarate, phyParam.Value ); +3294:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3295:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( readyToSend == true ) +3296:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3297:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( AdrCtrlOn == false ) +3298:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.Datarate = datarate; +3300:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; +3301:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3302:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_TX_DR ) == true ) +3303:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacParams.ChannelsDatarate = verify.DatarateParams.Datarate; +3305:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3306:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +3307:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3308:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return LORAMAC_STATUS_PARAMETER_INVALID; +3309:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3310:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3311:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3312:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** status = Send( &macHdr, fPort, fBuffer, fBufferSize ); +3313:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( status == LORAMAC_STATUS_OK ) +3314:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.McpsRequest = mcpsRequest->Type; +3316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsReq = 1; +3317:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3318:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** else +3319:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** NodeAckRequested = false; +3321:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + ARM GAS /tmp/ccrFaSdZ.s page 211 + + +3322:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3323:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3324:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** return status; +3325:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7818 .loc 1 3325 0 + 7819 001c 05B0 add sp, sp, #20 + 7820 @ sp needed + 7821 .LVL736: + 7822 001e 0CBC pop {r2, r3} + 7823 0020 9046 mov r8, r2 + 7824 0022 9946 mov r9, r3 + 7825 0024 F0BD pop {r4, r5, r6, r7, pc} + 7826 .LVL737: + 7827 .L474: +3239:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** memset1 ( ( uint8_t* ) &McpsConfirm, 0, sizeof( McpsConfirm ) ); + 7828 .loc 1 3239 0 + 7829 0026 02AB add r3, sp, #8 + 7830 0028 0022 movs r2, #0 + 7831 002a 1A70 strb r2, [r3] +3240:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + 7832 .loc 1 3240 0 + 7833 002c 484E ldr r6, .L476+4 + 7834 002e 1432 adds r2, r2, #20 + 7835 0030 0021 movs r1, #0 + 7836 0032 3000 movs r0, r6 + 7837 .LVL738: + 7838 0034 FFF7FEFF bl memset1 + 7839 .LVL739: +3241:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7840 .loc 1 3241 0 + 7841 0038 0123 movs r3, #1 + 7842 003a 7370 strb r3, [r6, #1] +3244:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7843 .loc 1 3244 0 + 7844 003c 454A ldr r2, .L476+8 + 7845 003e 1370 strb r3, [r2] +3246:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7846 .loc 1 3246 0 + 7847 0040 2378 ldrb r3, [r4] + 7848 0042 012B cmp r3, #1 + 7849 0044 4DD0 beq .L462 + 7850 0046 002B cmp r3, #0 + 7851 0048 05D0 beq .L463 + 7852 004a 032B cmp r3, #3 + 7853 004c 5CD0 beq .L464 +3227:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7854 .loc 1 3227 0 + 7855 004e 0026 movs r6, #0 +3223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void *fBuffer; + 7856 .loc 1 3223 0 + 7857 0050 0023 movs r3, #0 + 7858 0052 9946 mov r9, r3 + 7859 0054 11E0 b .L461 + 7860 .L463: + 7861 .LVL740: +3251:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7862 .loc 1 3251 0 + ARM GAS /tmp/ccrFaSdZ.s page 212 + + + 7863 0056 404B ldr r3, .L476+12 + 7864 0058 0122 movs r2, #1 + 7865 005a 1A70 strb r2, [r3] +3253:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fPort = mcpsRequest->Req.Unconfirmed.fPort; + 7866 .loc 1 3253 0 + 7867 005c 02AA add r2, sp, #8 + 7868 005e 1178 ldrb r1, [r2] + 7869 0060 1F23 movs r3, #31 + 7870 0062 0B40 ands r3, r1 + 7871 0064 4021 movs r1, #64 + 7872 0066 0B43 orrs r3, r1 + 7873 0068 1370 strb r3, [r2] +3254:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Unconfirmed.fBuffer; + 7874 .loc 1 3254 0 + 7875 006a 2379 ldrb r3, [r4, #4] + 7876 006c 9946 mov r9, r3 + 7877 .LVL741: +3255:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Unconfirmed.fBufferSize; + 7878 .loc 1 3255 0 + 7879 006e A368 ldr r3, [r4, #8] + 7880 0070 9846 mov r8, r3 + 7881 .LVL742: +3256:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Unconfirmed.Datarate; + 7882 .loc 1 3256 0 + 7883 0072 A789 ldrh r7, [r4, #12] + 7884 .LVL743: +3257:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7885 .loc 1 3257 0 + 7886 0074 0E25 movs r5, #14 + 7887 0076 6557 ldrsb r5, [r4, r5] + 7888 .LVL744: +3250:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = 1; + 7889 .loc 1 3250 0 + 7890 0078 0126 movs r6, #1 + 7891 .LVL745: + 7892 .L461: +3288:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 7893 .loc 1 3288 0 + 7894 007a 03A9 add r1, sp, #12 + 7895 007c 0123 movs r3, #1 + 7896 007e 0B70 strb r3, [r1] +3289:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + 7897 .loc 1 3289 0 + 7898 0080 364A ldr r2, .L476+16 + 7899 0082 2B33 adds r3, r3, #43 + 7900 0084 D35C ldrb r3, [r2, r3] + 7901 0086 8B70 strb r3, [r1, #2] +3290:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** // Apply the minimum possible datarate. + 7902 .loc 1 3290 0 + 7903 0088 354B ldr r3, .L476+20 + 7904 008a 1878 ldrb r0, [r3] + 7905 008c FFF7FEFF bl RegionGetPhyParam + 7906 .LVL746: +3293:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7907 .loc 1 3293 0 + 7908 0090 2B00 movs r3, r5 + 7909 0092 8542 cmp r5, r0 + ARM GAS /tmp/ccrFaSdZ.s page 213 + + + 7910 0094 00D2 bcs .L465 + 7911 0096 0300 movs r3, r0 + 7912 .L465: + 7913 0098 5BB2 sxtb r3, r3 + 7914 .LVL747: +3295:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7915 .loc 1 3295 0 + 7916 009a 002E cmp r6, #0 + 7917 009c 51D0 beq .L471 +3297:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7918 .loc 1 3297 0 + 7919 009e 314A ldr r2, .L476+24 + 7920 00a0 1278 ldrb r2, [r2] + 7921 00a2 002A cmp r2, #0 + 7922 00a4 11D1 bne .L466 +3299:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DatarateParams.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + 7923 .loc 1 3299 0 + 7924 00a6 01A9 add r1, sp, #4 + 7925 00a8 0B70 strb r3, [r1] +3300:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7926 .loc 1 3300 0 + 7927 00aa 2C4A ldr r2, .L476+16 + 7928 00ac 2C23 movs r3, #44 + 7929 .LVL748: + 7930 00ae D35C ldrb r3, [r2, r3] + 7931 00b0 8B70 strb r3, [r1, #2] +3302:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7932 .loc 1 3302 0 + 7933 00b2 2B4B ldr r3, .L476+20 + 7934 00b4 1878 ldrb r0, [r3] + 7935 00b6 0422 movs r2, #4 + 7936 00b8 FFF7FEFF bl RegionVerify + 7937 .LVL749: + 7938 00bc 0028 cmp r0, #0 + 7939 00be 42D0 beq .L472 +3304:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7940 .loc 1 3304 0 + 7941 00c0 01AB add r3, sp, #4 + 7942 00c2 0022 movs r2, #0 + 7943 00c4 9A56 ldrsb r2, [r3, r2] + 7944 00c6 254B ldr r3, .L476+16 + 7945 00c8 5A70 strb r2, [r3, #1] + 7946 .L466: +3312:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( status == LORAMAC_STATUS_OK ) + 7947 .loc 1 3312 0 + 7948 00ca 3B00 movs r3, r7 + 7949 00cc 4246 mov r2, r8 + 7950 00ce 4946 mov r1, r9 + 7951 00d0 02A8 add r0, sp, #8 + 7952 00d2 FFF7FEFF bl Send + 7953 .LVL750: +3313:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 7954 .loc 1 3313 0 + 7955 00d6 0028 cmp r0, #0 + 7956 00d8 28D0 beq .L475 +3320:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7957 .loc 1 3320 0 + ARM GAS /tmp/ccrFaSdZ.s page 214 + + + 7958 00da 234B ldr r3, .L476+28 + 7959 00dc 0022 movs r2, #0 + 7960 00de 1A70 strb r2, [r3] + 7961 00e0 9CE7 b .L460 + 7962 .LVL751: + 7963 .L462: +3263:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7964 .loc 1 3263 0 + 7965 00e2 E27B ldrb r2, [r4, #15] + 7966 00e4 1C4B ldr r3, .L476+12 + 7967 00e6 1A70 strb r2, [r3] +3265:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fPort = mcpsRequest->Req.Confirmed.fPort; + 7968 .loc 1 3265 0 + 7969 00e8 02A9 add r1, sp, #8 + 7970 00ea 0A78 ldrb r2, [r1] + 7971 00ec 1F23 movs r3, #31 + 7972 00ee 1A40 ands r2, r3 + 7973 00f0 9F3B subs r3, r3, #159 + 7974 00f2 1343 orrs r3, r2 + 7975 00f4 0B70 strb r3, [r1] +3266:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Confirmed.fBuffer; + 7976 .loc 1 3266 0 + 7977 00f6 2379 ldrb r3, [r4, #4] + 7978 00f8 9946 mov r9, r3 + 7979 .LVL752: +3267:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Confirmed.fBufferSize; + 7980 .loc 1 3267 0 + 7981 00fa A368 ldr r3, [r4, #8] + 7982 00fc 9846 mov r8, r3 + 7983 .LVL753: +3268:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Confirmed.Datarate; + 7984 .loc 1 3268 0 + 7985 00fe A789 ldrh r7, [r4, #12] + 7986 .LVL754: +3269:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 7987 .loc 1 3269 0 + 7988 0100 0E25 movs r5, #14 + 7989 0102 6557 ldrsb r5, [r4, r5] + 7990 .LVL755: +3262:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = mcpsRequest->Req.Confirmed.NbTrials; + 7991 .loc 1 3262 0 + 7992 0104 0126 movs r6, #1 +3270:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 7993 .loc 1 3270 0 + 7994 0106 B8E7 b .L461 + 7995 .LVL756: + 7996 .L464: +3275:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** + 7997 .loc 1 3275 0 + 7998 0108 134B ldr r3, .L476+12 + 7999 010a 0122 movs r2, #1 + 8000 010c 1A70 strb r2, [r3] +3277:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBuffer = mcpsRequest->Req.Proprietary.fBuffer; + 8001 .loc 1 3277 0 + 8002 010e 02AA add r2, sp, #8 + 8003 0110 1178 ldrb r1, [r2] + 8004 0112 2023 movs r3, #32 + ARM GAS /tmp/ccrFaSdZ.s page 215 + + + 8005 0114 5B42 rsbs r3, r3, #0 + 8006 0116 0B43 orrs r3, r1 + 8007 0118 1370 strb r3, [r2] +3278:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** fBufferSize = mcpsRequest->Req.Proprietary.fBufferSize; + 8008 .loc 1 3278 0 + 8009 011a 6368 ldr r3, [r4, #4] + 8010 011c 9846 mov r8, r3 + 8011 .LVL757: +3279:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** datarate = mcpsRequest->Req.Proprietary.Datarate; + 8012 .loc 1 3279 0 + 8013 011e 2789 ldrh r7, [r4, #8] + 8014 .LVL758: +3280:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** break; + 8015 .loc 1 3280 0 + 8016 0120 0A25 movs r5, #10 + 8017 0122 6557 ldrsb r5, [r4, r5] + 8018 .LVL759: +3274:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** AckTimeoutRetries = 1; + 8019 .loc 1 3274 0 + 8020 0124 0126 movs r6, #1 +3223:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void *fBuffer; + 8021 .loc 1 3223 0 + 8022 0126 0023 movs r3, #0 + 8023 .LVL760: + 8024 0128 9946 mov r9, r3 +3281:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8025 .loc 1 3281 0 + 8026 012a A6E7 b .L461 + 8027 .LVL761: + 8028 .L475: +3315:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacFlags.Bits.McpsReq = 1; + 8029 .loc 1 3315 0 + 8030 012c 2278 ldrb r2, [r4] + 8031 012e 084B ldr r3, .L476+4 + 8032 0130 1A70 strb r2, [r3] +3316:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8033 .loc 1 3316 0 + 8034 0132 0E4A ldr r2, .L476+32 + 8035 0134 1378 ldrb r3, [r2] + 8036 0136 0121 movs r1, #1 + 8037 0138 0B43 orrs r3, r1 + 8038 013a 1370 strb r3, [r2] + 8039 013c 6EE7 b .L460 + 8040 .LVL762: + 8041 .L468: +3231:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8042 .loc 1 3231 0 + 8043 013e 0320 movs r0, #3 + 8044 .LVL763: + 8045 0140 6CE7 b .L460 + 8046 .LVL764: + 8047 .L471: +3220:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** LoRaMacHeader_t macHdr; + 8048 .loc 1 3220 0 + 8049 0142 0220 movs r0, #2 + 8050 0144 6AE7 b .L460 + 8051 .LVL765: + ARM GAS /tmp/ccrFaSdZ.s page 216 + + + 8052 .L472: +3308:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8053 .loc 1 3308 0 + 8054 0146 0320 movs r0, #3 + 8055 0148 68E7 b .L460 + 8056 .L477: + 8057 014a C046 .align 2 + 8058 .L476: + 8059 014c 00000000 .word .LANCHOR24 + 8060 0150 00000000 .word .LANCHOR34 + 8061 0154 00000000 .word .LANCHOR6 + 8062 0158 00000000 .word .LANCHOR5 + 8063 015c 00000000 .word .LANCHOR14 + 8064 0160 00000000 .word .LANCHOR22 + 8065 0164 00000000 .word .LANCHOR29 + 8066 0168 00000000 .word .LANCHOR15 + 8067 016c 00000000 .word .LANCHOR26 + 8068 .cfi_endproc + 8069 .LFE118: + 8071 .section .text.LoRaMacTestRxWindowsOn,"ax",%progbits + 8072 .align 1 + 8073 .global LoRaMacTestRxWindowsOn + 8074 .syntax unified + 8075 .code 16 + 8076 .thumb_func + 8077 .fpu softvfp + 8079 LoRaMacTestRxWindowsOn: + 8080 .LFB119: +3326:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3327:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void LoRaMacTestRxWindowsOn( bool enable ) +3328:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 8081 .loc 1 3328 0 + 8082 .cfi_startproc + 8083 @ args = 0, pretend = 0, frame = 0 + 8084 @ frame_needed = 0, uses_anonymous_args = 0 + 8085 @ link register save eliminated. + 8086 .LVL766: +3329:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsRxWindowsEnabled = enable; + 8087 .loc 1 3329 0 + 8088 0000 014B ldr r3, .L479 + 8089 0002 1870 strb r0, [r3] +3330:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8090 .loc 1 3330 0 + 8091 @ sp needed + 8092 0004 7047 bx lr + 8093 .L480: + 8094 0006 C046 .align 2 + 8095 .L479: + 8096 0008 00000000 .word .LANCHOR12 + 8097 .cfi_endproc + 8098 .LFE119: + 8100 .section .text.LoRaMacTestSetMic,"ax",%progbits + 8101 .align 1 + 8102 .global LoRaMacTestSetMic + 8103 .syntax unified + 8104 .code 16 + 8105 .thumb_func + ARM GAS /tmp/ccrFaSdZ.s page 217 + + + 8106 .fpu softvfp + 8108 LoRaMacTestSetMic: + 8109 .LFB120: +3331:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3332:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void LoRaMacTestSetMic( uint16_t txPacketCounter ) +3333:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 8110 .loc 1 3333 0 + 8111 .cfi_startproc + 8112 @ args = 0, pretend = 0, frame = 0 + 8113 @ frame_needed = 0, uses_anonymous_args = 0 + 8114 @ link register save eliminated. + 8115 .LVL767: +3334:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** UpLinkCounter = txPacketCounter; + 8116 .loc 1 3334 0 + 8117 0000 024B ldr r3, .L482 + 8118 0002 1860 str r0, [r3] +3335:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** IsUpLinkCounterFixed = true; + 8119 .loc 1 3335 0 + 8120 0004 024B ldr r3, .L482+4 + 8121 0006 0122 movs r2, #1 + 8122 0008 1A70 strb r2, [r3] +3336:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8123 .loc 1 3336 0 + 8124 @ sp needed + 8125 000a 7047 bx lr + 8126 .L483: + 8127 .align 2 + 8128 .L482: + 8129 000c 00000000 .word .LANCHOR1 + 8130 0010 00000000 .word .LANCHOR60 + 8131 .cfi_endproc + 8132 .LFE120: + 8134 .section .text.LoRaMacTestSetDutyCycleOn,"ax",%progbits + 8135 .align 1 + 8136 .global LoRaMacTestSetDutyCycleOn + 8137 .syntax unified + 8138 .code 16 + 8139 .thumb_func + 8140 .fpu softvfp + 8142 LoRaMacTestSetDutyCycleOn: + 8143 .LFB121: +3337:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3338:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void LoRaMacTestSetDutyCycleOn( bool enable ) +3339:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 8144 .loc 1 3339 0 + 8145 .cfi_startproc + 8146 @ args = 0, pretend = 0, frame = 8 + 8147 @ frame_needed = 0, uses_anonymous_args = 0 + 8148 .LVL768: + 8149 0000 10B5 push {r4, lr} + 8150 .LCFI52: + 8151 .cfi_def_cfa_offset 8 + 8152 .cfi_offset 4, -8 + 8153 .cfi_offset 14, -4 + 8154 0002 82B0 sub sp, sp, #8 + 8155 .LCFI53: + 8156 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccrFaSdZ.s page 218 + + + 8157 0004 0400 movs r4, r0 +3340:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** VerifyParams_t verify; +3341:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3342:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** verify.DutyCycle = enable; + 8158 .loc 1 3342 0 + 8159 0006 01A9 add r1, sp, #4 + 8160 0008 0870 strb r0, [r1] +3343:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3344:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** if( RegionVerify( LoRaMacRegion, &verify, PHY_DUTY_CYCLE ) == true ) + 8161 .loc 1 3344 0 + 8162 000a 054B ldr r3, .L486 + 8163 000c 1878 ldrb r0, [r3] + 8164 .LVL769: + 8165 000e 0B22 movs r2, #11 + 8166 0010 FFF7FEFF bl RegionVerify + 8167 .LVL770: + 8168 0014 0028 cmp r0, #0 + 8169 0016 01D0 beq .L484 +3345:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { +3346:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** DutyCycleOn = enable; + 8170 .loc 1 3346 0 + 8171 0018 024B ldr r3, .L486+4 + 8172 001a 1C70 strb r4, [r3] + 8173 .L484: +3347:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } +3348:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8174 .loc 1 3348 0 + 8175 001c 02B0 add sp, sp, #8 + 8176 @ sp needed + 8177 001e 10BD pop {r4, pc} + 8178 .L487: + 8179 .align 2 + 8180 .L486: + 8181 0020 00000000 .word .LANCHOR22 + 8182 0024 00000000 .word .LANCHOR56 + 8183 .cfi_endproc + 8184 .LFE121: + 8186 .section .text.LoRaMacTestSetChannel,"ax",%progbits + 8187 .align 1 + 8188 .global LoRaMacTestSetChannel + 8189 .syntax unified + 8190 .code 16 + 8191 .thumb_func + 8192 .fpu softvfp + 8194 LoRaMacTestSetChannel: + 8195 .LFB122: +3349:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** +3350:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** void LoRaMacTestSetChannel( uint8_t channel ) +3351:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** { + 8196 .loc 1 3351 0 + 8197 .cfi_startproc + 8198 @ args = 0, pretend = 0, frame = 0 + 8199 @ frame_needed = 0, uses_anonymous_args = 0 + 8200 @ link register save eliminated. + 8201 .LVL771: +3352:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** Channel = channel; + 8202 .loc 1 3352 0 + ARM GAS /tmp/ccrFaSdZ.s page 219 + + + 8203 0000 014B ldr r3, .L489 + 8204 0002 1870 strb r0, [r3] +3353:./Middlewares/Third_Party/Lora/Mac/LoRaMac.c **** } + 8205 .loc 1 3353 0 + 8206 @ sp needed + 8207 0004 7047 bx lr + 8208 .L490: + 8209 0006 C046 .align 2 + 8210 .L489: + 8211 0008 00000000 .word .LANCHOR19 + 8212 .cfi_endproc + 8213 .LFE122: + 8215 .global LoRaMacFlags + 8216 .global TxTimeOnAir + 8217 .global LoRaMacState + 8218 .global LoRaMacParamsDefaults + 8219 .global LoRaMacParams + 8220 .section .bss.AckTimeoutRetry,"aw",%nobits + 8221 .set .LANCHOR7,. + 0 + 8224 AckTimeoutRetry: + 8225 0000 00 .space 1 + 8226 .section .bss.AckTimeoutTimer,"aw",%nobits + 8227 .align 2 + 8228 .set .LANCHOR23,. + 0 + 8231 AckTimeoutTimer: + 8232 0000 00000000 .space 20 + 8232 00000000 + 8232 00000000 + 8232 00000000 + 8232 00000000 + 8233 .section .bss.AdrAckCounter,"aw",%nobits + 8234 .align 2 + 8235 .set .LANCHOR3,. + 0 + 8238 AdrAckCounter: + 8239 0000 00000000 .space 4 + 8240 .section .bss.AdrCtrlOn,"aw",%nobits + 8241 .set .LANCHOR29,. + 0 + 8244 AdrCtrlOn: + 8245 0000 00 .space 1 + 8246 .section .bss.AggregatedDCycle,"aw",%nobits + 8247 .align 1 + 8248 .set .LANCHOR9,. + 0 + 8251 AggregatedDCycle: + 8252 0000 0000 .space 2 + 8253 .section .bss.AggregatedLastTxDoneTime,"aw",%nobits + 8254 .align 2 + 8255 .set .LANCHOR43,. + 0 + 8258 AggregatedLastTxDoneTime: + 8259 0000 00000000 .space 4 + 8260 .section .bss.AggregatedTimeOff,"aw",%nobits + 8261 .align 2 + 8262 .set .LANCHOR55,. + 0 + 8265 AggregatedTimeOff: + 8266 0000 00000000 .space 4 + 8267 .section .bss.Channel,"aw",%nobits + 8268 .set .LANCHOR19,. + 0 + 8271 Channel: + ARM GAS /tmp/ccrFaSdZ.s page 220 + + + 8272 0000 00 .space 1 + 8273 .section .bss.ChannelsNbRepCounter,"aw",%nobits + 8274 .set .LANCHOR4,. + 0 + 8277 ChannelsNbRepCounter: + 8278 0000 00 .space 1 + 8279 .section .bss.DownLinkCounter,"aw",%nobits + 8280 .align 2 + 8281 .set .LANCHOR2,. + 0 + 8284 DownLinkCounter: + 8285 0000 00000000 .space 4 + 8286 .section .bss.DutyCycleOn,"aw",%nobits + 8287 .set .LANCHOR56,. + 0 + 8290 DutyCycleOn: + 8291 0000 00 .space 1 + 8292 .section .bss.IsLoRaMacNetworkJoined,"aw",%nobits + 8293 .set .LANCHOR0,. + 0 + 8296 IsLoRaMacNetworkJoined: + 8297 0000 00 .space 1 + 8298 .section .bss.IsUpLinkCounterFixed,"aw",%nobits + 8299 .set .LANCHOR60,. + 0 + 8302 IsUpLinkCounterFixed: + 8303 0000 00 .space 1 + 8304 .section .bss.JoinRequestTrials,"aw",%nobits + 8305 .set .LANCHOR54,. + 0 + 8308 JoinRequestTrials: + 8309 0000 00 .space 1 + 8310 .section .bss.LastTxChannel,"aw",%nobits + 8311 .set .LANCHOR20,. + 0 + 8314 LastTxChannel: + 8315 0000 00 .space 1 + 8316 .section .bss.LastTxIsJoinRequest,"aw",%nobits + 8317 .set .LANCHOR47,. + 0 + 8320 LastTxIsJoinRequest: + 8321 0000 00 .space 1 + 8322 .section .bss.LoRaMacAppEui,"aw",%nobits + 8323 .align 2 + 8324 .set .LANCHOR51,. + 0 + 8327 LoRaMacAppEui: + 8328 0000 00000000 .space 4 + 8329 .section .bss.LoRaMacAppKey,"aw",%nobits + 8330 .align 2 + 8331 .set .LANCHOR38,. + 0 + 8334 LoRaMacAppKey: + 8335 0000 00000000 .space 4 + 8336 .section .bss.LoRaMacAppSKey,"aw",%nobits + 8337 .align 2 + 8338 .set .LANCHOR32,. + 0 + 8341 LoRaMacAppSKey: + 8342 0000 00000000 .space 16 + 8342 00000000 + 8342 00000000 + 8342 00000000 + 8343 .section .bss.LoRaMacBuffer,"aw",%nobits + 8344 .align 2 + 8347 LoRaMacBuffer: + 8348 0000 00000000 .space 255 + 8348 00000000 + ARM GAS /tmp/ccrFaSdZ.s page 221 + + + 8348 00000000 + 8348 00000000 + 8348 00000000 + 8349 .section .bss.LoRaMacBufferPktLen,"aw",%nobits + 8350 .align 1 + 8351 .set .LANCHOR49,. + 0 + 8354 LoRaMacBufferPktLen: + 8355 0000 0000 .space 2 + 8356 .section .bss.LoRaMacCallbacks,"aw",%nobits + 8357 .align 2 + 8358 .set .LANCHOR30,. + 0 + 8361 LoRaMacCallbacks: + 8362 0000 00000000 .space 4 + 8363 .section .bss.LoRaMacDevAddr,"aw",%nobits + 8364 .align 2 + 8365 .set .LANCHOR41,. + 0 + 8368 LoRaMacDevAddr: + 8369 0000 00000000 .space 4 + 8370 .section .bss.LoRaMacDevEui,"aw",%nobits + 8371 .align 2 + 8372 .set .LANCHOR52,. + 0 + 8375 LoRaMacDevEui: + 8376 0000 00000000 .space 4 + 8377 .section .bss.LoRaMacDevNonce,"aw",%nobits + 8378 .align 1 + 8379 .set .LANCHOR39,. + 0 + 8382 LoRaMacDevNonce: + 8383 0000 0000 .space 2 + 8384 .section .bss.LoRaMacDeviceClass,"aw",%nobits + 8385 .set .LANCHOR25,. + 0 + 8388 LoRaMacDeviceClass: + 8389 0000 00 .space 1 + 8390 .section .bss.LoRaMacFlags,"aw",%nobits + 8391 .align 2 + 8392 .set .LANCHOR26,. + 0 + 8395 LoRaMacFlags: + 8396 0000 00 .space 1 + 8397 .section .bss.LoRaMacInitializationTime,"aw",%nobits + 8398 .align 2 + 8399 .set .LANCHOR57,. + 0 + 8402 LoRaMacInitializationTime: + 8403 0000 00000000 .space 4 + 8404 .section .bss.LoRaMacNetID,"aw",%nobits + 8405 .align 2 + 8406 .set .LANCHOR40,. + 0 + 8409 LoRaMacNetID: + 8410 0000 00000000 .space 4 + 8411 .section .bss.LoRaMacNwkSKey,"aw",%nobits + 8412 .align 2 + 8413 .set .LANCHOR33,. + 0 + 8416 LoRaMacNwkSKey: + 8417 0000 00000000 .space 16 + 8417 00000000 + 8417 00000000 + 8417 00000000 + 8418 .section .bss.LoRaMacParams,"aw",%nobits + 8419 .align 2 + ARM GAS /tmp/ccrFaSdZ.s page 222 + + + 8420 .set .LANCHOR14,. + 0 + 8423 LoRaMacParams: + 8424 0000 00000000 .space 56 + 8424 00000000 + 8424 00000000 + 8424 00000000 + 8424 00000000 + 8425 .section .bss.LoRaMacParamsDefaults,"aw",%nobits + 8426 .align 2 + 8427 .set .LANCHOR13,. + 0 + 8430 LoRaMacParamsDefaults: + 8431 0000 00000000 .space 56 + 8431 00000000 + 8431 00000000 + 8431 00000000 + 8431 00000000 + 8432 .section .bss.LoRaMacPrimitives,"aw",%nobits + 8433 .align 2 + 8434 .set .LANCHOR61,. + 0 + 8437 LoRaMacPrimitives: + 8438 0000 00000000 .space 4 + 8439 .section .bss.LoRaMacRegion,"aw",%nobits + 8440 .set .LANCHOR22,. + 0 + 8443 LoRaMacRegion: + 8444 0000 00 .space 1 + 8445 .section .bss.LoRaMacRxPayload,"aw",%nobits + 8446 .align 2 + 8449 LoRaMacRxPayload: + 8450 0000 00000000 .space 255 + 8450 00000000 + 8450 00000000 + 8450 00000000 + 8450 00000000 + 8451 .section .bss.LoRaMacState,"aw",%nobits + 8452 .align 2 + 8453 .set .LANCHOR24,. + 0 + 8456 LoRaMacState: + 8457 0000 00000000 .space 4 + 8458 .section .bss.LoRaMacTxPayloadLen,"aw",%nobits + 8459 .set .LANCHOR50,. + 0 + 8462 LoRaMacTxPayloadLen: + 8463 0000 00 .space 1 + 8464 .section .bss.MacCommandsBuffer,"aw",%nobits + 8465 .align 2 + 8468 MacCommandsBuffer: + 8469 0000 00000000 .space 128 + 8469 00000000 + 8469 00000000 + 8469 00000000 + 8469 00000000 + 8470 .section .bss.MacCommandsBufferIndex,"aw",%nobits + 8471 .set .LANCHOR10,. + 0 + 8474 MacCommandsBufferIndex: + 8475 0000 00 .space 1 + 8476 .section .bss.MacCommandsBufferToRepeat,"aw",%nobits + 8477 .align 2 + 8480 MacCommandsBufferToRepeat: + ARM GAS /tmp/ccrFaSdZ.s page 223 + + + 8481 0000 00000000 .space 128 + 8481 00000000 + 8481 00000000 + 8481 00000000 + 8481 00000000 + 8482 .section .bss.MacCommandsBufferToRepeatIndex,"aw",%nobits + 8483 .set .LANCHOR11,. + 0 + 8486 MacCommandsBufferToRepeatIndex: + 8487 0000 00 .space 1 + 8488 .section .bss.MacCommandsInNextTx,"aw",%nobits + 8489 .set .LANCHOR17,. + 0 + 8492 MacCommandsInNextTx: + 8493 0000 00 .space 1 + 8494 .section .bss.MacStateCheckTimer,"aw",%nobits + 8495 .align 2 + 8496 .set .LANCHOR27,. + 0 + 8499 MacStateCheckTimer: + 8500 0000 00000000 .space 20 + 8500 00000000 + 8500 00000000 + 8500 00000000 + 8500 00000000 + 8501 .section .bss.MaxDCycle,"aw",%nobits + 8502 .set .LANCHOR8,. + 0 + 8505 MaxDCycle: + 8506 0000 00 .space 1 + 8507 .section .bss.MaxJoinRequestTrials,"aw",%nobits + 8508 .set .LANCHOR59,. + 0 + 8511 MaxJoinRequestTrials: + 8512 0000 00 .space 1 + 8513 .section .bss.McpsConfirm,"aw",%nobits + 8514 .align 2 + 8515 .set .LANCHOR34,. + 0 + 8518 McpsConfirm: + 8519 0000 00000000 .space 20 + 8519 00000000 + 8519 00000000 + 8519 00000000 + 8519 00000000 + 8520 .section .bss.McpsIndication,"aw",%nobits + 8521 .align 2 + 8522 .set .LANCHOR35,. + 0 + 8525 McpsIndication: + 8526 0000 00000000 .space 24 + 8526 00000000 + 8526 00000000 + 8526 00000000 + 8526 00000000 + 8527 .section .bss.MlmeConfirm,"aw",%nobits + 8528 .align 2 + 8529 .set .LANCHOR28,. + 0 + 8532 MlmeConfirm: + 8533 0000 00000000 .space 12 + 8533 00000000 + 8533 00000000 + 8534 .section .bss.MulticastChannels,"aw",%nobits + 8535 .align 2 + ARM GAS /tmp/ccrFaSdZ.s page 224 + + + 8536 .set .LANCHOR18,. + 0 + 8539 MulticastChannels: + 8540 0000 00000000 .space 4 + 8541 .section .bss.NodeAckRequested,"aw",%nobits + 8542 .set .LANCHOR15,. + 0 + 8545 NodeAckRequested: + 8546 0000 00 .space 1 + 8547 .section .bss.PublicNetwork,"aw",%nobits + 8548 .set .LANCHOR63,. + 0 + 8551 PublicNetwork: + 8552 0000 00 .space 1 + 8553 .section .bss.RadioEvents,"aw",%nobits + 8554 .align 2 + 8555 .set .LANCHOR62,. + 0 + 8558 RadioEvents: + 8559 0000 00000000 .space 28 + 8559 00000000 + 8559 00000000 + 8559 00000000 + 8559 00000000 + 8560 .section .bss.RepeaterSupport,"aw",%nobits + 8561 .set .LANCHOR21,. + 0 + 8564 RepeaterSupport: + 8565 0000 00 .space 1 + 8566 .section .bss.RxSlot,"aw",%nobits + 8567 .set .LANCHOR36,. + 0 + 8570 RxSlot: + 8571 0000 00 .space 1 + 8572 .section .bss.RxWindow1Config,"aw",%nobits + 8573 .align 2 + 8574 .set .LANCHOR48,. + 0 + 8577 RxWindow1Config: + 8578 0000 00000000 .space 20 + 8578 00000000 + 8578 00000000 + 8578 00000000 + 8578 00000000 + 8579 .section .bss.RxWindow1Delay,"aw",%nobits + 8580 .align 2 + 8581 .set .LANCHOR45,. + 0 + 8584 RxWindow1Delay: + 8585 0000 00000000 .space 4 + 8586 .section .bss.RxWindow2Config,"aw",%nobits + 8587 .align 2 + 8588 .set .LANCHOR42,. + 0 + 8591 RxWindow2Config: + 8592 0000 00000000 .space 20 + 8592 00000000 + 8592 00000000 + 8592 00000000 + 8592 00000000 + 8593 .section .bss.RxWindow2Delay,"aw",%nobits + 8594 .align 2 + 8595 .set .LANCHOR44,. + 0 + 8598 RxWindow2Delay: + 8599 0000 00000000 .space 4 + 8600 .section .bss.RxWindowTimer1,"aw",%nobits + ARM GAS /tmp/ccrFaSdZ.s page 225 + + + 8601 .align 2 + 8602 .set .LANCHOR46,. + 0 + 8605 RxWindowTimer1: + 8606 0000 00000000 .space 20 + 8606 00000000 + 8606 00000000 + 8606 00000000 + 8606 00000000 + 8607 .section .bss.RxWindowTimer2,"aw",%nobits + 8608 .align 2 + 8609 .set .LANCHOR37,. + 0 + 8612 RxWindowTimer2: + 8613 0000 00000000 .space 20 + 8613 00000000 + 8613 00000000 + 8613 00000000 + 8613 00000000 + 8614 .section .bss.SrvAckRequested,"aw",%nobits + 8615 .set .LANCHOR16,. + 0 + 8618 SrvAckRequested: + 8619 0000 00 .space 1 + 8620 .section .bss.TxDelayedTimer,"aw",%nobits + 8621 .align 2 + 8622 .set .LANCHOR58,. + 0 + 8625 TxDelayedTimer: + 8626 0000 00000000 .space 20 + 8626 00000000 + 8626 00000000 + 8626 00000000 + 8626 00000000 + 8627 .section .bss.TxTimeOnAir,"aw",%nobits + 8628 .align 2 + 8629 .set .LANCHOR53,. + 0 + 8632 TxTimeOnAir: + 8633 0000 00000000 .space 4 + 8634 .section .bss.UpLinkCounter,"aw",%nobits + 8635 .align 2 + 8636 .set .LANCHOR1,. + 0 + 8639 UpLinkCounter: + 8640 0000 00000000 .space 4 + 8641 .section .data.AckTimeoutRetries,"aw",%progbits + 8642 .set .LANCHOR5,. + 0 + 8645 AckTimeoutRetries: + 8646 0000 01 .byte 1 + 8647 .section .data.AckTimeoutRetriesCounter,"aw",%progbits + 8648 .set .LANCHOR6,. + 0 + 8651 AckTimeoutRetriesCounter: + 8652 0000 01 .byte 1 + 8653 .section .data.IsRxWindowsEnabled,"aw",%progbits + 8654 .set .LANCHOR12,. + 0 + 8657 IsRxWindowsEnabled: + 8658 0000 01 .byte 1 + 8659 .section .rodata.LoRaMacMaxEirpTable,"a",%progbits + 8660 .align 2 + 8661 .set .LANCHOR31,. + 0 + 8664 LoRaMacMaxEirpTable: + 8665 0000 08 .byte 8 + ARM GAS /tmp/ccrFaSdZ.s page 226 + + + 8666 0001 0A .byte 10 + 8667 0002 0C .byte 12 + 8668 0003 0D .byte 13 + 8669 0004 0E .byte 14 + 8670 0005 10 .byte 16 + 8671 0006 12 .byte 18 + 8672 0007 14 .byte 20 + 8673 0008 15 .byte 21 + 8674 0009 18 .byte 24 + 8675 000a 1A .byte 26 + 8676 000b 1B .byte 27 + 8677 000c 1D .byte 29 + 8678 000d 1E .byte 30 + 8679 000e 21 .byte 33 + 8680 000f 24 .byte 36 + 8681 .text + 8682 .Letext0: + 8683 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 8684 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 8685 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 8686 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 8687 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 8688 .file 7 "/usr/arm-none-eabi/include/sys/_stdint.h" + 8689 .file 8 "Middlewares/Third_Party/Lora/Phy/radio.h" + 8690 .file 9 "/usr/arm-none-eabi/include/math.h" + 8691 .file 10 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 8692 .file 11 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + 8693 .file 12 "./Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 8694 .file 13 "./Middlewares/Third_Party/Lora/Mac/region/Region.h" + 8695 .file 14 "./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h" + ARM GAS /tmp/ccrFaSdZ.s page 227 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 LoRaMac.c + /tmp/ccrFaSdZ.s:16 .text.ResetMacParameters:0000000000000000 $t + /tmp/ccrFaSdZ.s:22 .text.ResetMacParameters:0000000000000000 ResetMacParameters + /tmp/ccrFaSdZ.s:151 .text.ResetMacParameters:0000000000000098 $d + /tmp/ccrFaSdZ.s:176 .text.ValidatePayloadLength:0000000000000000 $t + /tmp/ccrFaSdZ.s:182 .text.ValidatePayloadLength:0000000000000000 ValidatePayloadLength + /tmp/ccrFaSdZ.s:266 .text.ValidatePayloadLength:000000000000004c $d + /tmp/ccrFaSdZ.s:273 .text.OnAckTimeoutTimerEvent:0000000000000000 $t + /tmp/ccrFaSdZ.s:279 .text.OnAckTimeoutTimerEvent:0000000000000000 OnAckTimeoutTimerEvent + /tmp/ccrFaSdZ.s:331 .text.OnAckTimeoutTimerEvent:0000000000000038 $d + /tmp/ccrFaSdZ.s:341 .text.PrepareRxDoneAbort:0000000000000000 $t + /tmp/ccrFaSdZ.s:347 .text.PrepareRxDoneAbort:0000000000000000 PrepareRxDoneAbort + /tmp/ccrFaSdZ.s:400 .text.PrepareRxDoneAbort:000000000000003c $d + /tmp/ccrFaSdZ.s:410 .text.ProcessMacCommands:0000000000000000 $t + /tmp/ccrFaSdZ.s:416 .text.ProcessMacCommands:0000000000000000 ProcessMacCommands + /tmp/ccrFaSdZ.s:468 .rodata.ProcessMacCommands:0000000000000000 $d + /tmp/ccrFaSdZ.s:1173 .text.ProcessMacCommands:0000000000000394 $d + /tmp/ccrFaSdZ.s:8468 .bss.MacCommandsBuffer:0000000000000000 MacCommandsBuffer + /tmp/ccrFaSdZ.s:1190 .text.ProcessMacCommands:00000000000003c8 $t + /tmp/ccrFaSdZ.s:1283 .text.ProcessMacCommands:000000000000043c $d + /tmp/ccrFaSdZ.s:1292 .text.OnRadioRxDone:0000000000000000 $t + /tmp/ccrFaSdZ.s:1298 .text.OnRadioRxDone:0000000000000000 OnRadioRxDone + /tmp/ccrFaSdZ.s:1770 .text.OnRadioRxDone:0000000000000258 $d + /tmp/ccrFaSdZ.s:8449 .bss.LoRaMacRxPayload:0000000000000000 LoRaMacRxPayload + /tmp/ccrFaSdZ.s:1795 .text.OnRadioRxDone:00000000000002b4 $t + /tmp/ccrFaSdZ.s:2431 .text.OnRadioRxDone:00000000000005c4 $d + /tmp/ccrFaSdZ.s:2450 .text.OnRxWindow2TimerEvent:0000000000000000 $t + /tmp/ccrFaSdZ.s:2456 .text.OnRxWindow2TimerEvent:0000000000000000 OnRxWindow2TimerEvent + /tmp/ccrFaSdZ.s:2562 .text.OnRxWindow2TimerEvent:0000000000000074 $d + /tmp/ccrFaSdZ.s:2578 .text.OnRadioRxTimeout:0000000000000000 $t + /tmp/ccrFaSdZ.s:2584 .text.OnRadioRxTimeout:0000000000000000 OnRadioRxTimeout + /tmp/ccrFaSdZ.s:2679 .text.OnRadioRxTimeout:0000000000000078 $d + /tmp/ccrFaSdZ.s:2692 .text.OnRadioTxTimeout:0000000000000000 $t + /tmp/ccrFaSdZ.s:2698 .text.OnRadioTxTimeout:0000000000000000 OnRadioTxTimeout + /tmp/ccrFaSdZ.s:2744 .text.OnRadioTxTimeout:000000000000002c $d + /tmp/ccrFaSdZ.s:2753 .text.OnRadioRxError:0000000000000000 $t + /tmp/ccrFaSdZ.s:2759 .text.OnRadioRxError:0000000000000000 OnRadioRxError + /tmp/ccrFaSdZ.s:2849 .text.OnRadioRxError:0000000000000070 $d + /tmp/ccrFaSdZ.s:2862 .text.OnRadioTxDone:0000000000000000 $t + /tmp/ccrFaSdZ.s:2868 .text.OnRadioTxDone:0000000000000000 OnRadioTxDone + /tmp/ccrFaSdZ.s:3068 .text.OnRadioTxDone:0000000000000108 $d + /tmp/ccrFaSdZ.s:3091 .text.OnRxWindow1TimerEvent:0000000000000000 $t + /tmp/ccrFaSdZ.s:3097 .text.OnRxWindow1TimerEvent:0000000000000000 OnRxWindow1TimerEvent + /tmp/ccrFaSdZ.s:3196 .text.OnRxWindow1TimerEvent:0000000000000068 $d + /tmp/ccrFaSdZ.s:3212 .text.PrepareFrame:0000000000000000 $t + /tmp/ccrFaSdZ.s:3219 .text.PrepareFrame:0000000000000000 PrepareFrame + /tmp/ccrFaSdZ.s:3685 .rodata.PrepareFrame:0000000000000000 $d + /tmp/ccrFaSdZ.s:3886 .text.PrepareFrame:000000000000033c $d + /tmp/ccrFaSdZ.s:8347 .bss.LoRaMacBuffer:0000000000000000 LoRaMacBuffer + /tmp/ccrFaSdZ.s:8480 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Middlewares/Third_Party/Lora/Crypto/cmac.h \ + Middlewares/Third_Party/Lora/Crypto/aes.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Middlewares/Third_Party/Lora/Crypto/aes.h: + +Middlewares/Third_Party/Lora/Crypto/cmac.h: + +Middlewares/Third_Party/Lora/Crypto/aes.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h: diff --git a/build/LoRaMacCrypto.lst b/build/LoRaMacCrypto.lst new file mode 100644 index 0000000..bc5fd56 --- /dev/null +++ b/build/LoRaMacCrypto.lst @@ -0,0 +1,1053 @@ +ARM GAS /tmp/ccDkMnY2.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "LoRaMacCrypto.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LoRaMacComputeMic,"ax",%progbits + 16 .align 1 + 17 .global LoRaMacComputeMic + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LoRaMacComputeMic: + 24 .LFB82: + 25 .file 1 "./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c" + 1:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /* + 2:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** ___ _____ _ ___ _ _____ ___ ___ ___ ___ + 9:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + 10:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + 11:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + 12:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** embedded.connectivity.solutions=============== + 13:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 14:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** Description: LoRa MAC layer implementation + 15:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 16:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 17:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 18:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) + 19:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 20:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include + 21:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include + 22:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include "utilities.h" + 23:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 24:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include "aes.h" + 25:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include "cmac.h" + 26:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 27:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #include "LoRaMacCrypto.h" + 28:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 29:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 30:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * CMAC/AES Message Integrity Code (MIC) Block B0 size + 31:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 32:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** #define LORAMAC_MIC_BLOCK_B0_SIZE 16 + 33:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + ARM GAS /tmp/ccDkMnY2.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 35:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * MIC field computation initial data + 36:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 37:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static uint8_t MicBlockB0[] = { 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 38:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 39:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** }; + 40:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 41:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 42:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * Contains the computed MIC field. + 43:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * + 44:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \remark Only the 4 first bytes are used + 45:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 46:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static uint8_t Mic[16]; + 47:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 48:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 49:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * Encryption aBlock and sBlock + 50:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 51:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static uint8_t aBlock[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 52:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 53:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** }; + 54:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static uint8_t sBlock[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 55:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 56:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** }; + 57:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 58:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 59:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * AES computation context variable + 60:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 61:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static aes_context AesContext; + 62:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 63:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 64:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * CMAC computation context variable + 65:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 66:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** static AES_CMAC_CTX AesCmacCtx[1]; + 67:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 68:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** /*! + 69:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \brief Computes the LoRaMAC frame MIC field + 70:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * + 71:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] buffer Data buffer + 72:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] size Data buffer size + 73:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] key AES key to be used + 74:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] address Frame address + 75:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] dir Frame direction [0: uplink, 1: downlink] + 76:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [IN] sequenceCounter Frame sequence counter + 77:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** * \param [OUT] mic Computed MIC field + 78:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** */ + 79:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, + 80:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 26 .loc 1 80 0 + 27 .cfi_startproc + 28 @ args = 12, pretend = 0, frame = 8 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F0B5 push {r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 20 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + ARM GAS /tmp/ccDkMnY2.s page 3 + + + 36 .cfi_offset 6, -12 + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 39 0002 83B0 sub sp, sp, #12 + 40 .LCFI1: + 41 .cfi_def_cfa_offset 32 + 42 0004 0190 str r0, [sp, #4] + 43 0006 0D00 movs r5, r1 + 44 0008 1600 movs r6, r2 + 45 000a 08AA add r2, sp, #32 + 46 .LVL1: + 47 000c 1278 ldrb r2, [r2] + 48 .LVL2: + 49 000e 0999 ldr r1, [sp, #36] + 50 .LVL3: + 81:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[5] = dir; + 51 .loc 1 81 0 + 52 0010 1B4C ldr r4, .L2 + 53 0012 6271 strb r2, [r4, #5] + 82:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 83:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[6] = ( address ) & 0xFF; + 54 .loc 1 83 0 + 55 0014 A371 strb r3, [r4, #6] + 84:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[7] = ( address >> 8 ) & 0xFF; + 56 .loc 1 84 0 + 57 0016 1A0A lsrs r2, r3, #8 + 58 0018 E271 strb r2, [r4, #7] + 85:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[8] = ( address >> 16 ) & 0xFF; + 59 .loc 1 85 0 + 60 001a 1A0C lsrs r2, r3, #16 + 61 001c 2272 strb r2, [r4, #8] + 86:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[9] = ( address >> 24 ) & 0xFF; + 62 .loc 1 86 0 + 63 001e 1B0E lsrs r3, r3, #24 + 64 .LVL4: + 65 0020 6372 strb r3, [r4, #9] + 87:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 88:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[10] = ( sequenceCounter ) & 0xFF; + 66 .loc 1 88 0 + 67 0022 A172 strb r1, [r4, #10] + 89:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[11] = ( sequenceCounter >> 8 ) & 0xFF; + 68 .loc 1 89 0 + 69 0024 0B0A lsrs r3, r1, #8 + 70 0026 E372 strb r3, [r4, #11] + 90:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[12] = ( sequenceCounter >> 16 ) & 0xFF; + 71 .loc 1 90 0 + 72 0028 0B0C lsrs r3, r1, #16 + 73 002a 2373 strb r3, [r4, #12] + 91:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[13] = ( sequenceCounter >> 24 ) & 0xFF; + 74 .loc 1 91 0 + 75 002c 090E lsrs r1, r1, #24 + 76 002e 6173 strb r1, [r4, #13] + 92:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 93:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** MicBlockB0[15] = size & 0xFF; + 77 .loc 1 93 0 + 78 0030 E573 strb r5, [r4, #15] + 94:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + ARM GAS /tmp/ccDkMnY2.s page 4 + + + 95:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Init( AesCmacCtx ); + 79 .loc 1 95 0 + 80 0032 144F ldr r7, .L2+4 + 81 0034 3800 movs r0, r7 + 82 .LVL5: + 83 0036 FFF7FEFF bl AES_CMAC_Init + 84 .LVL6: + 96:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 97:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_SetKey( AesCmacCtx, key ); + 85 .loc 1 97 0 + 86 003a 3100 movs r1, r6 + 87 003c 3800 movs r0, r7 + 88 003e FFF7FEFF bl AES_CMAC_SetKey + 89 .LVL7: + 98:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 99:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Update( AesCmacCtx, MicBlockB0, LORAMAC_MIC_BLOCK_B0_SIZE ); + 90 .loc 1 99 0 + 91 0042 1022 movs r2, #16 + 92 0044 2100 movs r1, r4 + 93 0046 3800 movs r0, r7 + 94 0048 FFF7FEFF bl AES_CMAC_Update + 95 .LVL8: + 100:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 101:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Update( AesCmacCtx, buffer, size & 0xFF ); + 96 .loc 1 101 0 + 97 004c FF22 movs r2, #255 + 98 004e 2A40 ands r2, r5 + 99 0050 0199 ldr r1, [sp, #4] + 100 0052 3800 movs r0, r7 + 101 0054 FFF7FEFF bl AES_CMAC_Update + 102 .LVL9: + 102:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 103:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Final( Mic, AesCmacCtx ); + 103 .loc 1 103 0 + 104 0058 0B4C ldr r4, .L2+8 + 105 005a 3900 movs r1, r7 + 106 005c 2000 movs r0, r4 + 107 005e FFF7FEFF bl AES_CMAC_Final + 108 .LVL10: + 104:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 105:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** *mic = ( uint32_t )( ( uint32_t )Mic[3] << 24 | ( uint32_t )Mic[2] << 16 | ( uint32_t )Mic[1] < + 109 .loc 1 105 0 + 110 0062 E378 ldrb r3, [r4, #3] + 111 0064 1B06 lsls r3, r3, #24 + 112 0066 A278 ldrb r2, [r4, #2] + 113 0068 1204 lsls r2, r2, #16 + 114 006a 1343 orrs r3, r2 + 115 006c 6278 ldrb r2, [r4, #1] + 116 006e 1202 lsls r2, r2, #8 + 117 0070 1343 orrs r3, r2 + 118 0072 2278 ldrb r2, [r4] + 119 0074 1343 orrs r3, r2 + 120 0076 0A9A ldr r2, [sp, #40] + 121 0078 1360 str r3, [r2] + 106:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 122 .loc 1 106 0 + 123 007a 03B0 add sp, sp, #12 + ARM GAS /tmp/ccDkMnY2.s page 5 + + + 124 @ sp needed + 125 .LVL11: + 126 007c F0BD pop {r4, r5, r6, r7, pc} + 127 .L3: + 128 007e C046 .align 2 + 129 .L2: + 130 0080 00000000 .word .LANCHOR0 + 131 0084 00000000 .word AesCmacCtx + 132 0088 00000000 .word .LANCHOR1 + 133 .cfi_endproc + 134 .LFE82: + 136 .section .text.LoRaMacPayloadEncrypt,"ax",%progbits + 137 .align 1 + 138 .global LoRaMacPayloadEncrypt + 139 .syntax unified + 140 .code 16 + 141 .thumb_func + 142 .fpu softvfp + 144 LoRaMacPayloadEncrypt: + 145 .LFB83: + 107:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 108:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacPayloadEncrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t addr + 109:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 146 .loc 1 109 0 + 147 .cfi_startproc + 148 @ args = 12, pretend = 0, frame = 8 + 149 @ frame_needed = 0, uses_anonymous_args = 0 + 150 .LVL12: + 151 0000 F0B5 push {r4, r5, r6, r7, lr} + 152 .LCFI2: + 153 .cfi_def_cfa_offset 20 + 154 .cfi_offset 4, -20 + 155 .cfi_offset 5, -16 + 156 .cfi_offset 6, -12 + 157 .cfi_offset 7, -8 + 158 .cfi_offset 14, -4 + 159 0002 DE46 mov lr, fp + 160 0004 4746 mov r7, r8 + 161 0006 80B5 push {r7, lr} + 162 .LCFI3: + 163 .cfi_def_cfa_offset 28 + 164 .cfi_offset 8, -28 + 165 .cfi_offset 11, -24 + 166 0008 83B0 sub sp, sp, #12 + 167 .LCFI4: + 168 .cfi_def_cfa_offset 40 + 169 000a 0400 movs r4, r0 + 170 000c 8846 mov r8, r1 + 171 000e 0192 str r2, [sp, #4] + 172 0010 1E00 movs r6, r3 + 173 0012 0AAB add r3, sp, #40 + 174 .LVL13: + 175 0014 1B78 ldrb r3, [r3] + 176 .LVL14: + 177 0016 9B46 mov fp, r3 + 178 0018 0B9D ldr r5, [sp, #44] + 179 001a 0C9F ldr r7, [sp, #48] + ARM GAS /tmp/ccDkMnY2.s page 6 + + + 180 .LVL15: + 110:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint16_t i; + 111:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint8_t bufferIndex = 0; + 112:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint16_t ctr = 1; + 113:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 114:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memset1( AesContext.ksch, '\0', 240 ); + 181 .loc 1 114 0 + 182 001c F022 movs r2, #240 + 183 .LVL16: + 184 001e 0021 movs r1, #0 + 185 .LVL17: + 186 0020 2948 ldr r0, .L14 + 187 .LVL18: + 188 0022 FFF7FEFF bl memset1 + 189 .LVL19: + 115:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_set_key( key, 16, &AesContext ); + 190 .loc 1 115 0 + 191 0026 284A ldr r2, .L14 + 192 0028 1021 movs r1, #16 + 193 002a 0198 ldr r0, [sp, #4] + 194 002c FFF7FEFF bl aes_set_key + 195 .LVL20: + 116:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 117:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[5] = dir; + 196 .loc 1 117 0 + 197 0030 264B ldr r3, .L14+4 + 198 0032 5A46 mov r2, fp + 199 0034 5A71 strb r2, [r3, #5] + 118:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 119:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[6] = ( address ) & 0xFF; + 200 .loc 1 119 0 + 201 0036 9E71 strb r6, [r3, #6] + 120:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[7] = ( address >> 8 ) & 0xFF; + 202 .loc 1 120 0 + 203 0038 320A lsrs r2, r6, #8 + 204 003a DA71 strb r2, [r3, #7] + 121:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[8] = ( address >> 16 ) & 0xFF; + 205 .loc 1 121 0 + 206 003c 320C lsrs r2, r6, #16 + 207 003e 1A72 strb r2, [r3, #8] + 122:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[9] = ( address >> 24 ) & 0xFF; + 208 .loc 1 122 0 + 209 0040 320E lsrs r2, r6, #24 + 210 0042 5A72 strb r2, [r3, #9] + 123:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 124:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[10] = ( sequenceCounter ) & 0xFF; + 211 .loc 1 124 0 + 212 0044 9D72 strb r5, [r3, #10] + 125:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[11] = ( sequenceCounter >> 8 ) & 0xFF; + 213 .loc 1 125 0 + 214 0046 2A0A lsrs r2, r5, #8 + 215 0048 DA72 strb r2, [r3, #11] + 126:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[12] = ( sequenceCounter >> 16 ) & 0xFF; + 216 .loc 1 126 0 + 217 004a 2A0C lsrs r2, r5, #16 + 218 004c 1A73 strb r2, [r3, #12] + 127:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[13] = ( sequenceCounter >> 24 ) & 0xFF; + ARM GAS /tmp/ccDkMnY2.s page 7 + + + 219 .loc 1 127 0 + 220 004e 2D0E lsrs r5, r5, #24 + 221 0050 5D73 strb r5, [r3, #13] + 112:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 222 .loc 1 112 0 + 223 0052 0126 movs r6, #1 + 224 .LVL21: + 111:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint16_t ctr = 1; + 225 .loc 1 111 0 + 226 0054 0025 movs r5, #0 + 128:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 129:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** while( size >= 16 ) + 227 .loc 1 129 0 + 228 0056 0FE0 b .L5 + 229 .LVL22: + 230 .L7: + 130:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 131:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[15] = ( ( ctr ) & 0xFF ); + 132:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** ctr++; + 133:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( aBlock, sBlock, &AesContext ); + 134:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** for( i = 0; i < 16; i++ ) + 135:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 136:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** encBuffer[bufferIndex + i] = buffer[bufferIndex + i] ^ sBlock[i]; + 231 .loc 1 136 0 discriminator 3 + 232 0058 E918 adds r1, r5, r3 + 233 005a 625C ldrb r2, [r4, r1] + 234 005c 1C48 ldr r0, .L14+8 + 235 005e C05C ldrb r0, [r0, r3] + 236 0060 4240 eors r2, r0 + 237 0062 7A54 strb r2, [r7, r1] + 134:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 238 .loc 1 134 0 discriminator 3 + 239 0064 0133 adds r3, r3, #1 + 240 .LVL23: + 241 0066 9BB2 uxth r3, r3 + 242 .LVL24: + 243 .L6: + 134:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 244 .loc 1 134 0 is_stmt 0 discriminator 1 + 245 0068 0F2B cmp r3, #15 + 246 006a F5D9 bls .L7 + 137:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 138:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** size -= 16; + 247 .loc 1 138 0 is_stmt 1 + 248 006c 4346 mov r3, r8 + 249 .LVL25: + 250 006e 103B subs r3, r3, #16 + 251 0070 9BB2 uxth r3, r3 + 252 0072 9846 mov r8, r3 + 253 .LVL26: + 139:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** bufferIndex += 16; + 254 .loc 1 139 0 + 255 0074 1035 adds r5, r5, #16 + 256 .LVL27: + 257 0076 EDB2 uxtb r5, r5 + 258 .LVL28: + 259 .L5: + ARM GAS /tmp/ccDkMnY2.s page 8 + + + 129:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 260 .loc 1 129 0 + 261 0078 4346 mov r3, r8 + 262 007a 0F2B cmp r3, #15 + 263 007c 09D9 bls .L12 + 131:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** ctr++; + 264 .loc 1 131 0 + 265 007e 1348 ldr r0, .L14+4 + 266 0080 C673 strb r6, [r0, #15] + 132:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( aBlock, sBlock, &AesContext ); + 267 .loc 1 132 0 + 268 0082 0136 adds r6, r6, #1 + 269 .LVL29: + 270 0084 B6B2 uxth r6, r6 + 271 .LVL30: + 133:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** for( i = 0; i < 16; i++ ) + 272 .loc 1 133 0 + 273 0086 104A ldr r2, .L14 + 274 0088 1149 ldr r1, .L14+8 + 275 008a FFF7FEFF bl aes_encrypt + 276 .LVL31: + 134:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 277 .loc 1 134 0 + 278 008e 0023 movs r3, #0 + 279 0090 EAE7 b .L6 + 280 .LVL32: + 281 .L12: + 140:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 141:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 142:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** if( size > 0 ) + 282 .loc 1 142 0 + 283 0092 002B cmp r3, #0 + 284 0094 04D1 bne .L13 + 285 .L4: + 143:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 144:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aBlock[15] = ( ( ctr ) & 0xFF ); + 145:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( aBlock, sBlock, &AesContext ); + 146:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** for( i = 0; i < size; i++ ) + 147:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 148:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** encBuffer[bufferIndex + i] = buffer[bufferIndex + i] ^ sBlock[i]; + 149:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 150:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 151:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 286 .loc 1 151 0 + 287 0096 03B0 add sp, sp, #12 + 288 @ sp needed + 289 .LVL33: + 290 .LVL34: + 291 .LVL35: + 292 .LVL36: + 293 0098 0CBC pop {r2, r3} + 294 009a 9046 mov r8, r2 + 295 009c 9B46 mov fp, r3 + 296 009e F0BD pop {r4, r5, r6, r7, pc} + 297 .LVL37: + 298 .L13: + 144:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( aBlock, sBlock, &AesContext ); + ARM GAS /tmp/ccDkMnY2.s page 9 + + + 299 .loc 1 144 0 + 300 00a0 0A48 ldr r0, .L14+4 + 301 00a2 C673 strb r6, [r0, #15] + 145:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** for( i = 0; i < size; i++ ) + 302 .loc 1 145 0 + 303 00a4 084A ldr r2, .L14 + 304 00a6 0A49 ldr r1, .L14+8 + 305 00a8 FFF7FEFF bl aes_encrypt + 306 .LVL38: + 146:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 307 .loc 1 146 0 + 308 00ac 0023 movs r3, #0 + 309 00ae 07E0 b .L10 + 310 .LVL39: + 311 .L11: + 148:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 312 .loc 1 148 0 discriminator 3 + 313 00b0 E918 adds r1, r5, r3 + 314 00b2 625C ldrb r2, [r4, r1] + 315 00b4 0648 ldr r0, .L14+8 + 316 00b6 C05C ldrb r0, [r0, r3] + 317 00b8 4240 eors r2, r0 + 318 00ba 7A54 strb r2, [r7, r1] + 146:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 319 .loc 1 146 0 discriminator 3 + 320 00bc 0133 adds r3, r3, #1 + 321 .LVL40: + 322 00be 9BB2 uxth r3, r3 + 323 .LVL41: + 324 .L10: + 146:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 325 .loc 1 146 0 is_stmt 0 discriminator 1 + 326 00c0 9845 cmp r8, r3 + 327 00c2 F5D8 bhi .L11 + 328 00c4 E7E7 b .L4 + 329 .L15: + 330 00c6 C046 .align 2 + 331 .L14: + 332 00c8 00000000 .word AesContext + 333 00cc 00000000 .word .LANCHOR2 + 334 00d0 00000000 .word .LANCHOR3 + 335 .cfi_endproc + 336 .LFE83: + 338 .section .text.LoRaMacPayloadDecrypt,"ax",%progbits + 339 .align 1 + 340 .global LoRaMacPayloadDecrypt + 341 .syntax unified + 342 .code 16 + 343 .thumb_func + 344 .fpu softvfp + 346 LoRaMacPayloadDecrypt: + 347 .LFB84: + 152:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 153:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacPayloadDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t addr + 154:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 348 .loc 1 154 0 is_stmt 1 + 349 .cfi_startproc + ARM GAS /tmp/ccDkMnY2.s page 10 + + + 350 @ args = 12, pretend = 0, frame = 0 + 351 @ frame_needed = 0, uses_anonymous_args = 0 + 352 .LVL42: + 353 0000 30B5 push {r4, r5, lr} + 354 .LCFI5: + 355 .cfi_def_cfa_offset 12 + 356 .cfi_offset 4, -12 + 357 .cfi_offset 5, -8 + 358 .cfi_offset 14, -4 + 359 0002 85B0 sub sp, sp, #20 + 360 .LCFI6: + 361 .cfi_def_cfa_offset 32 + 362 0004 08AC add r4, sp, #32 + 363 .LVL43: + 364 0006 2478 ldrb r4, [r4] + 365 .LVL44: + 155:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** LoRaMacPayloadEncrypt( buffer, size, key, address, dir, sequenceCounter, decBuffer ); + 366 .loc 1 155 0 + 367 0008 0A9D ldr r5, [sp, #40] + 368 000a 0295 str r5, [sp, #8] + 369 000c 099D ldr r5, [sp, #36] + 370 000e 0195 str r5, [sp, #4] + 371 0010 0094 str r4, [sp] + 372 0012 FFF7FEFF bl LoRaMacPayloadEncrypt + 373 .LVL45: + 156:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 374 .loc 1 156 0 + 375 0016 05B0 add sp, sp, #20 + 376 @ sp needed + 377 0018 30BD pop {r4, r5, pc} + 378 .cfi_endproc + 379 .LFE84: + 381 .section .text.LoRaMacJoinComputeMic,"ax",%progbits + 382 .align 1 + 383 .global LoRaMacJoinComputeMic + 384 .syntax unified + 385 .code 16 + 386 .thumb_func + 387 .fpu softvfp + 389 LoRaMacJoinComputeMic: + 390 .LFB85: + 157:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 158:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacJoinComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t *mic + 159:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 391 .loc 1 159 0 + 392 .cfi_startproc + 393 @ args = 0, pretend = 0, frame = 8 + 394 @ frame_needed = 0, uses_anonymous_args = 0 + 395 .LVL46: + 396 0000 F0B5 push {r4, r5, r6, r7, lr} + 397 .LCFI7: + 398 .cfi_def_cfa_offset 20 + 399 .cfi_offset 4, -20 + 400 .cfi_offset 5, -16 + 401 .cfi_offset 6, -12 + 402 .cfi_offset 7, -8 + 403 .cfi_offset 14, -4 + ARM GAS /tmp/ccDkMnY2.s page 11 + + + 404 0002 83B0 sub sp, sp, #12 + 405 .LCFI8: + 406 .cfi_def_cfa_offset 32 + 407 0004 0190 str r0, [sp, #4] + 408 0006 0C00 movs r4, r1 + 409 0008 1700 movs r7, r2 + 410 000a 1E00 movs r6, r3 + 160:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Init( AesCmacCtx ); + 411 .loc 1 160 0 + 412 000c 0F4D ldr r5, .L18 + 413 000e 2800 movs r0, r5 + 414 .LVL47: + 415 0010 FFF7FEFF bl AES_CMAC_Init + 416 .LVL48: + 161:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 162:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_SetKey( AesCmacCtx, key ); + 417 .loc 1 162 0 + 418 0014 3900 movs r1, r7 + 419 0016 2800 movs r0, r5 + 420 0018 FFF7FEFF bl AES_CMAC_SetKey + 421 .LVL49: + 163:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 164:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Update( AesCmacCtx, buffer, size & 0xFF ); + 422 .loc 1 164 0 + 423 001c FF22 movs r2, #255 + 424 001e 2240 ands r2, r4 + 425 0020 0199 ldr r1, [sp, #4] + 426 0022 2800 movs r0, r5 + 427 0024 FFF7FEFF bl AES_CMAC_Update + 428 .LVL50: + 165:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 166:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** AES_CMAC_Final( Mic, AesCmacCtx ); + 429 .loc 1 166 0 + 430 0028 094C ldr r4, .L18+4 + 431 002a 2900 movs r1, r5 + 432 002c 2000 movs r0, r4 + 433 002e FFF7FEFF bl AES_CMAC_Final + 434 .LVL51: + 167:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 168:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** *mic = ( uint32_t )( ( uint32_t )Mic[3] << 24 | ( uint32_t )Mic[2] << 16 | ( uint32_t )Mic[1] < + 435 .loc 1 168 0 + 436 0032 E378 ldrb r3, [r4, #3] + 437 0034 1B06 lsls r3, r3, #24 + 438 0036 A278 ldrb r2, [r4, #2] + 439 0038 1204 lsls r2, r2, #16 + 440 003a 1343 orrs r3, r2 + 441 003c 6278 ldrb r2, [r4, #1] + 442 003e 1202 lsls r2, r2, #8 + 443 0040 1343 orrs r3, r2 + 444 0042 2278 ldrb r2, [r4] + 445 0044 1343 orrs r3, r2 + 446 0046 3360 str r3, [r6] + 169:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 447 .loc 1 169 0 + 448 0048 03B0 add sp, sp, #12 + 449 @ sp needed + 450 .LVL52: + ARM GAS /tmp/ccDkMnY2.s page 12 + + + 451 .LVL53: + 452 004a F0BD pop {r4, r5, r6, r7, pc} + 453 .L19: + 454 .align 2 + 455 .L18: + 456 004c 00000000 .word AesCmacCtx + 457 0050 00000000 .word .LANCHOR1 + 458 .cfi_endproc + 459 .LFE85: + 461 .section .text.LoRaMacJoinDecrypt,"ax",%progbits + 462 .align 1 + 463 .global LoRaMacJoinDecrypt + 464 .syntax unified + 465 .code 16 + 466 .thumb_func + 467 .fpu softvfp + 469 LoRaMacJoinDecrypt: + 470 .LFB86: + 170:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 171:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacJoinDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint8_t *decBuff + 172:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 471 .loc 1 172 0 + 472 .cfi_startproc + 473 @ args = 0, pretend = 0, frame = 8 + 474 @ frame_needed = 0, uses_anonymous_args = 0 + 475 .LVL54: + 476 0000 F0B5 push {r4, r5, r6, r7, lr} + 477 .LCFI9: + 478 .cfi_def_cfa_offset 20 + 479 .cfi_offset 4, -20 + 480 .cfi_offset 5, -16 + 481 .cfi_offset 6, -12 + 482 .cfi_offset 7, -8 + 483 .cfi_offset 14, -4 + 484 0002 83B0 sub sp, sp, #12 + 485 .LCFI10: + 486 .cfi_def_cfa_offset 32 + 487 0004 0500 movs r5, r0 + 488 0006 0F00 movs r7, r1 + 489 0008 0192 str r2, [sp, #4] + 490 000a 1E00 movs r6, r3 + 173:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memset1( AesContext.ksch, '\0', 240 ); + 491 .loc 1 173 0 + 492 000c 0D4C ldr r4, .L23 + 493 000e F022 movs r2, #240 + 494 .LVL55: + 495 0010 0021 movs r1, #0 + 496 .LVL56: + 497 0012 2000 movs r0, r4 + 498 .LVL57: + 499 0014 FFF7FEFF bl memset1 + 500 .LVL58: + 174:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_set_key( key, 16, &AesContext ); + 501 .loc 1 174 0 + 502 0018 2200 movs r2, r4 + 503 001a 1021 movs r1, #16 + 504 001c 0198 ldr r0, [sp, #4] + ARM GAS /tmp/ccDkMnY2.s page 13 + + + 505 001e FFF7FEFF bl aes_set_key + 506 .LVL59: + 175:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( buffer, decBuffer, &AesContext ); + 507 .loc 1 175 0 + 508 0022 2200 movs r2, r4 + 509 0024 3100 movs r1, r6 + 510 0026 2800 movs r0, r5 + 511 0028 FFF7FEFF bl aes_encrypt + 512 .LVL60: + 176:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** // Check if optional CFList is included + 177:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** if( size >= 16 ) + 513 .loc 1 177 0 + 514 002c 0F2F cmp r7, #15 + 515 002e 01D8 bhi .L22 + 516 .L20: + 178:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 179:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( buffer + 16, decBuffer + 16, &AesContext ); + 180:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 181:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 517 .loc 1 181 0 + 518 0030 03B0 add sp, sp, #12 + 519 @ sp needed + 520 .LVL61: + 521 .LVL62: + 522 0032 F0BD pop {r4, r5, r6, r7, pc} + 523 .LVL63: + 524 .L22: + 179:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 525 .loc 1 179 0 + 526 0034 3100 movs r1, r6 + 527 0036 1031 adds r1, r1, #16 + 528 0038 2800 movs r0, r5 + 529 003a 1030 adds r0, r0, #16 + 530 003c 014A ldr r2, .L23 + 531 003e FFF7FEFF bl aes_encrypt + 532 .LVL64: + 533 .loc 1 181 0 + 534 0042 F5E7 b .L20 + 535 .L24: + 536 .align 2 + 537 .L23: + 538 0044 00000000 .word AesContext + 539 .cfi_endproc + 540 .LFE86: + 542 .section .text.LoRaMacJoinComputeSKeys,"ax",%progbits + 543 .align 1 + 544 .global LoRaMacJoinComputeSKeys + 545 .syntax unified + 546 .code 16 + 547 .thumb_func + 548 .fpu softvfp + 550 LoRaMacJoinComputeSKeys: + 551 .LFB87: + 182:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 183:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** void LoRaMacJoinComputeSKeys( const uint8_t *key, const uint8_t *appNonce, uint16_t devNonce, uint8 + 184:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** { + 552 .loc 1 184 0 + ARM GAS /tmp/ccDkMnY2.s page 14 + + + 553 .cfi_startproc + 554 @ args = 4, pretend = 0, frame = 24 + 555 @ frame_needed = 0, uses_anonymous_args = 0 + 556 .LVL65: + 557 0000 F0B5 push {r4, r5, r6, r7, lr} + 558 .LCFI11: + 559 .cfi_def_cfa_offset 20 + 560 .cfi_offset 4, -20 + 561 .cfi_offset 5, -16 + 562 .cfi_offset 6, -12 + 563 .cfi_offset 7, -8 + 564 .cfi_offset 14, -4 + 565 0002 87B0 sub sp, sp, #28 + 566 .LCFI12: + 567 .cfi_def_cfa_offset 48 + 568 0004 0400 movs r4, r0 + 569 0006 0E00 movs r6, r1 + 570 0008 0093 str r3, [sp] + 571 000a 6846 mov r0, sp + 572 .LVL66: + 573 000c 871D adds r7, r0, #6 + 574 000e C280 strh r2, [r0, #6] + 575 .LVL67: + 185:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint8_t nonce[16]; + 186:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** uint8_t *pDevNonce = ( uint8_t * )&devNonce; + 187:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 188:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memset1( AesContext.ksch, '\0', 240 ); + 576 .loc 1 188 0 + 577 0010 1F4D ldr r5, .L26 + 578 0012 F022 movs r2, #240 + 579 .LVL68: + 580 0014 0021 movs r1, #0 + 581 .LVL69: + 582 0016 2800 movs r0, r5 + 583 0018 FFF7FEFF bl memset1 + 584 .LVL70: + 189:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_set_key( key, 16, &AesContext ); + 585 .loc 1 189 0 + 586 001c 2A00 movs r2, r5 + 587 001e 1021 movs r1, #16 + 588 0020 2000 movs r0, r4 + 589 0022 FFF7FEFF bl aes_set_key + 590 .LVL71: + 190:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 191:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memset1( nonce, 0, sizeof( nonce ) ); + 591 .loc 1 191 0 + 592 0026 02AC add r4, sp, #8 + 593 .LVL72: + 594 0028 1022 movs r2, #16 + 595 002a 0021 movs r1, #0 + 596 002c 2000 movs r0, r4 + 597 002e FFF7FEFF bl memset1 + 598 .LVL73: + 192:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** nonce[0] = 0x01; + 599 .loc 1 192 0 + 600 0032 0123 movs r3, #1 + 601 0034 2370 strb r3, [r4] + ARM GAS /tmp/ccDkMnY2.s page 15 + + + 193:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memcpy1( nonce + 1, appNonce, 6 ); + 602 .loc 1 193 0 + 603 0036 0622 movs r2, #6 + 604 0038 3100 movs r1, r6 + 605 003a 0920 movs r0, #9 + 606 003c 6844 add r0, r0, sp + 607 003e FFF7FEFF bl memcpy1 + 608 .LVL74: + 194:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memcpy1( nonce + 7, pDevNonce, 2 ); + 609 .loc 1 194 0 + 610 0042 0222 movs r2, #2 + 611 0044 3900 movs r1, r7 + 612 0046 0F20 movs r0, #15 + 613 0048 6844 add r0, r0, sp + 614 004a FFF7FEFF bl memcpy1 + 615 .LVL75: + 195:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( nonce, nwkSKey, &AesContext ); + 616 .loc 1 195 0 + 617 004e 2A00 movs r2, r5 + 618 0050 0099 ldr r1, [sp] + 619 0052 2000 movs r0, r4 + 620 0054 FFF7FEFF bl aes_encrypt + 621 .LVL76: + 196:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** + 197:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memset1( nonce, 0, sizeof( nonce ) ); + 622 .loc 1 197 0 + 623 0058 1022 movs r2, #16 + 624 005a 0021 movs r1, #0 + 625 005c 2000 movs r0, r4 + 626 005e FFF7FEFF bl memset1 + 627 .LVL77: + 198:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** nonce[0] = 0x02; + 628 .loc 1 198 0 + 629 0062 0223 movs r3, #2 + 630 0064 2370 strb r3, [r4] + 199:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memcpy1( nonce + 1, appNonce, 6 ); + 631 .loc 1 199 0 + 632 0066 0622 movs r2, #6 + 633 0068 3100 movs r1, r6 + 634 006a 0733 adds r3, r3, #7 + 635 006c 6B44 add r3, r3, sp + 636 006e 1800 movs r0, r3 + 637 0070 FFF7FEFF bl memcpy1 + 638 .LVL78: + 200:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** memcpy1( nonce + 7, pDevNonce, 2 ); + 639 .loc 1 200 0 + 640 0074 0222 movs r2, #2 + 641 0076 3900 movs r1, r7 + 642 0078 0F23 movs r3, #15 + 643 007a 6B44 add r3, r3, sp + 644 007c 1800 movs r0, r3 + 645 007e FFF7FEFF bl memcpy1 + 646 .LVL79: + 201:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** aes_encrypt( nonce, appSKey, &AesContext ); + 647 .loc 1 201 0 + 648 0082 2A00 movs r2, r5 + 649 0084 0C99 ldr r1, [sp, #48] + ARM GAS /tmp/ccDkMnY2.s page 16 + + + 650 0086 2000 movs r0, r4 + 651 0088 FFF7FEFF bl aes_encrypt + 652 .LVL80: + 202:./Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c **** } + 653 .loc 1 202 0 + 654 008c 07B0 add sp, sp, #28 + 655 .LVL81: + 656 @ sp needed + 657 .LVL82: + 658 .LVL83: + 659 008e F0BD pop {r4, r5, r6, r7, pc} + 660 .L27: + 661 .align 2 + 662 .L26: + 663 0090 00000000 .word AesContext + 664 .cfi_endproc + 665 .LFE87: + 667 .section .bss.AesCmacCtx,"aw",%nobits + 668 .align 2 + 671 AesCmacCtx: + 672 0000 00000000 .space 280 + 672 00000000 + 672 00000000 + 672 00000000 + 672 00000000 + 673 .section .bss.AesContext,"aw",%nobits + 674 .align 2 + 677 AesContext: + 678 0000 00000000 .space 241 + 678 00000000 + 678 00000000 + 678 00000000 + 678 00000000 + 679 .section .bss.Mic,"aw",%nobits + 680 .align 2 + 681 .set .LANCHOR1,. + 0 + 684 Mic: + 685 0000 00000000 .space 16 + 685 00000000 + 685 00000000 + 685 00000000 + 686 .section .bss.sBlock,"aw",%nobits + 687 .align 2 + 688 .set .LANCHOR3,. + 0 + 691 sBlock: + 692 0000 00000000 .space 16 + 692 00000000 + 692 00000000 + 692 00000000 + 693 .section .data.MicBlockB0,"aw",%progbits + 694 .align 2 + 695 .set .LANCHOR0,. + 0 + 698 MicBlockB0: + 699 0000 49 .byte 73 + 700 0001 00 .byte 0 + 701 0002 00 .byte 0 + 702 0003 00 .byte 0 + ARM GAS /tmp/ccDkMnY2.s page 17 + + + 703 0004 00 .byte 0 + 704 0005 00 .byte 0 + 705 0006 00 .byte 0 + 706 0007 00 .byte 0 + 707 0008 00 .byte 0 + 708 0009 00 .byte 0 + 709 000a 00 .byte 0 + 710 000b 00 .byte 0 + 711 000c 00 .byte 0 + 712 000d 00 .byte 0 + 713 000e 00 .byte 0 + 714 000f 00 .byte 0 + 715 .section .data.aBlock,"aw",%progbits + 716 .align 2 + 717 .set .LANCHOR2,. + 0 + 720 aBlock: + 721 0000 01 .byte 1 + 722 0001 00 .byte 0 + 723 0002 00 .byte 0 + 724 0003 00 .byte 0 + 725 0004 00 .byte 0 + 726 0005 00 .byte 0 + 727 0006 00 .byte 0 + 728 0007 00 .byte 0 + 729 0008 00 .byte 0 + 730 0009 00 .byte 0 + 731 000a 00 .byte 0 + 732 000b 00 .byte 0 + 733 000c 00 .byte 0 + 734 000d 00 .byte 0 + 735 000e 00 .byte 0 + 736 000f 00 .byte 0 + 737 .text + 738 .Letext0: + 739 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 740 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 741 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 742 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 743 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 744 .file 7 "/usr/arm-none-eabi/include/stdlib.h" + 745 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 746 .file 9 "/usr/arm-none-eabi/include/math.h" + 747 .file 10 "Middlewares/Third_Party/Lora/Crypto/aes.h" + 748 .file 11 "Middlewares/Third_Party/Lora/Crypto/cmac.h" + 749 .file 12 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + ARM GAS /tmp/ccDkMnY2.s page 18 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 LoRaMacCrypto.c + /tmp/ccDkMnY2.s:16 .text.LoRaMacComputeMic:0000000000000000 $t + /tmp/ccDkMnY2.s:23 .text.LoRaMacComputeMic:0000000000000000 LoRaMacComputeMic + /tmp/ccDkMnY2.s:130 .text.LoRaMacComputeMic:0000000000000080 $d + /tmp/ccDkMnY2.s:671 .bss.AesCmacCtx:0000000000000000 AesCmacCtx + /tmp/ccDkMnY2.s:137 .text.LoRaMacPayloadEncrypt:0000000000000000 $t + /tmp/ccDkMnY2.s:144 .text.LoRaMacPayloadEncrypt:0000000000000000 LoRaMacPayloadEncrypt + /tmp/ccDkMnY2.s:332 .text.LoRaMacPayloadEncrypt:00000000000000c8 $d + /tmp/ccDkMnY2.s:677 .bss.AesContext:0000000000000000 AesContext + /tmp/ccDkMnY2.s:339 .text.LoRaMacPayloadDecrypt:0000000000000000 $t + /tmp/ccDkMnY2.s:346 .text.LoRaMacPayloadDecrypt:0000000000000000 LoRaMacPayloadDecrypt + /tmp/ccDkMnY2.s:382 .text.LoRaMacJoinComputeMic:0000000000000000 $t + /tmp/ccDkMnY2.s:389 .text.LoRaMacJoinComputeMic:0000000000000000 LoRaMacJoinComputeMic + /tmp/ccDkMnY2.s:456 .text.LoRaMacJoinComputeMic:000000000000004c $d + /tmp/ccDkMnY2.s:462 .text.LoRaMacJoinDecrypt:0000000000000000 $t + /tmp/ccDkMnY2.s:469 .text.LoRaMacJoinDecrypt:0000000000000000 LoRaMacJoinDecrypt + /tmp/ccDkMnY2.s:538 .text.LoRaMacJoinDecrypt:0000000000000044 $d + /tmp/ccDkMnY2.s:543 .text.LoRaMacJoinComputeSKeys:0000000000000000 $t + /tmp/ccDkMnY2.s:550 .text.LoRaMacJoinComputeSKeys:0000000000000000 LoRaMacJoinComputeSKeys + /tmp/ccDkMnY2.s:663 .text.LoRaMacJoinComputeSKeys:0000000000000090 $d + /tmp/ccDkMnY2.s:668 .bss.AesCmacCtx:0000000000000000 $d + /tmp/ccDkMnY2.s:674 .bss.AesContext:0000000000000000 $d + /tmp/ccDkMnY2.s:680 .bss.Mic:0000000000000000 $d + /tmp/ccDkMnY2.s:684 .bss.Mic:0000000000000000 Mic + /tmp/ccDkMnY2.s:687 .bss.sBlock:0000000000000000 $d + /tmp/ccDkMnY2.s:691 .bss.sBlock:0000000000000000 sBlock + /tmp/ccDkMnY2.s:694 .data.MicBlockB0:0000000000000000 $d + /tmp/ccDkMnY2.s:698 .data.MicBlockB0:0000000000000000 MicBlockB0 + /tmp/ccDkMnY2.s:716 .data.aBlock:0000000000000000 $d + /tmp/ccDkMnY2.s:720 .data.aBlock:0000000000000000 aBlock + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +AES_CMAC_Init +AES_CMAC_SetKey +AES_CMAC_Update +AES_CMAC_Final +memset1 +aes_set_key +aes_encrypt +memcpy1 diff --git a/build/Region.d b/build/Region.d new file mode 100644 index 0000000..b00fb95 --- /dev/null +++ b/build/Region.d @@ -0,0 +1,34 @@ +build/Region.d: Middlewares/Third_Party/Lora/Mac/region/Region.c \ + Middlewares/Third_Party/Lora/Mac/timer.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Mac/region/Region.h \ + Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h + +Middlewares/Third_Party/Lora/Mac/timer.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Mac/region/Region.h: + +Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h: diff --git a/build/Region.lst b/build/Region.lst new file mode 100644 index 0000000..f38f42d --- /dev/null +++ b/build/Region.lst @@ -0,0 +1,2208 @@ +ARM GAS /tmp/cciGOlRU.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "Region.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.RegionIsActive,"ax",%progbits + 16 .align 1 + 17 .global RegionIsActive + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 RegionIsActive: + 24 .LFB82: + 25 .file 1 "./Middlewares/Third_Party/Lora/Mac/region/Region.c" + 1:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** /* + 2:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** ___ _____ _ ___ _ _____ ___ ___ ___ ___ + 9:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + 10:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + 11:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + 12:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** embedded.connectivity.solutions=============== + 13:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 14:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** Description: LoRa MAC region implementation + 15:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 16:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 17:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 18:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) + 19:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** */ + 20:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include + 21:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include + 22:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include + 23:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 24:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "timer.h" + 25:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "LoRaMac.h" + 26:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 27:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 28:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 29:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** // Regional includes + 30:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "Region.h" + 31:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 32:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 33:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + ARM GAS /tmp/cciGOlRU.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** // Setup regions + 35:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_AS923 + 36:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionAS923.h" + 37:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CASE case LORAMAC_REGION_AS923: + 38:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_IS_ACTIVE( ) AS923_CASE { return true; } + 39:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_GET_PHY_PARAM( ) AS923_CASE { return RegionAS923GetPhyParam( getP + 40:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_SET_BAND_TX_DONE( ) AS923_CASE { RegionAS923SetBandTxDone( txDone ); + 41:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_INIT_DEFAULTS( ) AS923_CASE { RegionAS923InitDefaults( type ); br + 42:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_VERIFY( ) AS923_CASE { return RegionAS923Verify( verify, p + 43:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_APPLY_CF_LIST( ) AS923_CASE { RegionAS923ApplyCFList( applyCFList + 44:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHAN_MASK_SET( ) AS923_CASE { return RegionAS923ChanMaskSet( chan + 45:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_ADR_NEXT( ) AS923_CASE { return RegionAS923AdrNext( adrNext, + 46:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_COMPUTE_RX_WINDOW_PARAMETERS( ) AS923_CASE { RegionAS923ComputeRxWindowParameter + 47:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_RX_CONFIG( ) AS923_CASE { return RegionAS923RxConfig( rxConfi + 48:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_TX_CONFIG( ) AS923_CASE { return RegionAS923TxConfig( txConfi + 49:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_LINK_ADR_REQ( ) AS923_CASE { return RegionAS923LinkAdrReq( linkA + 50:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_RX_PARAM_SETUP_REQ( ) AS923_CASE { return RegionAS923RxParamSetupReq( + 51:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_NEW_CHANNEL_REQ( ) AS923_CASE { return RegionAS923NewChannelReq( ne + 52:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_TX_PARAM_SETUP_REQ( ) AS923_CASE { return RegionAS923TxParamSetupReq( + 53:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_DL_CHANNEL_REQ( ) AS923_CASE { return RegionAS923DlChannelReq( dlC + 54:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_ALTERNATE_DR( ) AS923_CASE { return RegionAS923AlternateDr( alte + 55:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CALC_BACKOFF( ) AS923_CASE { RegionAS923CalcBackOff( calcBackOff + 56:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_NEXT_CHANNEL( ) AS923_CASE { return RegionAS923NextChannel( next + 57:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHANNEL_ADD( ) AS923_CASE { return RegionAS923ChannelAdd( chann + 58:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHANNEL_REMOVE( ) AS923_CASE { return RegionAS923ChannelsRemove( c + 59:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_SET_CONTINUOUS_WAVE( ) AS923_CASE { RegionAS923SetContinuousWave( conti + 60:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_APPLY_DR_OFFSET( ) AS923_CASE { return RegionAS923ApplyDrOffset( do + 61:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 62:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_IS_ACTIVE( ) + 63:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_GET_PHY_PARAM( ) + 64:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_SET_BAND_TX_DONE( ) + 65:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_INIT_DEFAULTS( ) + 66:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_VERIFY( ) + 67:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_APPLY_CF_LIST( ) + 68:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHAN_MASK_SET( ) + 69:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_ADR_NEXT( ) + 70:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_COMPUTE_RX_WINDOW_PARAMETERS( ) + 71:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_RX_CONFIG( ) + 72:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_TX_CONFIG( ) + 73:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_LINK_ADR_REQ( ) + 74:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_RX_PARAM_SETUP_REQ( ) + 75:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_NEW_CHANNEL_REQ( ) + 76:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_TX_PARAM_SETUP_REQ( ) + 77:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_DL_CHANNEL_REQ( ) + 78:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_ALTERNATE_DR( ) + 79:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CALC_BACKOFF( ) + 80:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_NEXT_CHANNEL( ) + 81:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHANNEL_ADD( ) + 82:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_CHANNEL_REMOVE( ) + 83:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_SET_CONTINUOUS_WAVE( ) + 84:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AS923_APPLY_DR_OFFSET( ) + 85:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 86:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 87:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_AU915 + 88:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionAU915.h" + 89:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CASE case LORAMAC_REGION_AU915: + 90:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_IS_ACTIVE( ) AU915_CASE { return true; } + ARM GAS /tmp/cciGOlRU.s page 3 + + + 91:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_GET_PHY_PARAM( ) AU915_CASE { return RegionAU915GetPhyParam( getP + 92:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_SET_BAND_TX_DONE( ) AU915_CASE { RegionAU915SetBandTxDone( txDone ); + 93:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_INIT_DEFAULTS( ) AU915_CASE { RegionAU915InitDefaults( type ); br + 94:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_VERIFY( ) AU915_CASE { return RegionAU915Verify( verify, p + 95:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_APPLY_CF_LIST( ) AU915_CASE { RegionAU915ApplyCFList( applyCFList + 96:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHAN_MASK_SET( ) AU915_CASE { return RegionAU915ChanMaskSet( chan + 97:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_ADR_NEXT( ) AU915_CASE { return RegionAU915AdrNext( adrNext, + 98:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_COMPUTE_RX_WINDOW_PARAMETERS( ) AU915_CASE { RegionAU915ComputeRxWindowParameter + 99:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_RX_CONFIG( ) AU915_CASE { return RegionAU915RxConfig( rxConfi + 100:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_TX_CONFIG( ) AU915_CASE { return RegionAU915TxConfig( txConfi + 101:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_LINK_ADR_REQ( ) AU915_CASE { return RegionAU915LinkAdrReq( linkA + 102:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_RX_PARAM_SETUP_REQ( ) AU915_CASE { return RegionAU915RxParamSetupReq( + 103:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_NEW_CHANNEL_REQ( ) AU915_CASE { return RegionAU915NewChannelReq( ne + 104:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_TX_PARAM_SETUP_REQ( ) AU915_CASE { return RegionAU915TxParamSetupReq( + 105:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_DL_CHANNEL_REQ( ) AU915_CASE { return RegionAU915DlChannelReq( dlC + 106:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_ALTERNATE_DR( ) AU915_CASE { return RegionAU915AlternateDr( alte + 107:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CALC_BACKOFF( ) AU915_CASE { RegionAU915CalcBackOff( calcBackOff + 108:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_NEXT_CHANNEL( ) AU915_CASE { return RegionAU915NextChannel( next + 109:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHANNEL_ADD( ) AU915_CASE { return RegionAU915ChannelAdd( chann + 110:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHANNEL_REMOVE( ) AU915_CASE { return RegionAU915ChannelsRemove( c + 111:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_SET_CONTINUOUS_WAVE( ) AU915_CASE { RegionAU915SetContinuousWave( conti + 112:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_APPLY_DR_OFFSET( ) AU915_CASE { return RegionAU915ApplyDrOffset( do + 113:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 114:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_IS_ACTIVE( ) + 115:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_GET_PHY_PARAM( ) + 116:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_SET_BAND_TX_DONE( ) + 117:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_INIT_DEFAULTS( ) + 118:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_VERIFY( ) + 119:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_APPLY_CF_LIST( ) + 120:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHAN_MASK_SET( ) + 121:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_ADR_NEXT( ) + 122:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_COMPUTE_RX_WINDOW_PARAMETERS( ) + 123:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_RX_CONFIG( ) + 124:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_TX_CONFIG( ) + 125:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_LINK_ADR_REQ( ) + 126:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_RX_PARAM_SETUP_REQ( ) + 127:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_NEW_CHANNEL_REQ( ) + 128:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_TX_PARAM_SETUP_REQ( ) + 129:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_DL_CHANNEL_REQ( ) + 130:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_ALTERNATE_DR( ) + 131:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CALC_BACKOFF( ) + 132:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_NEXT_CHANNEL( ) + 133:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHANNEL_ADD( ) + 134:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_CHANNEL_REMOVE( ) + 135:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_SET_CONTINUOUS_WAVE( ) + 136:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define AU915_APPLY_DR_OFFSET( ) + 137:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 138:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 139:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_CN470 + 140:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionCN470.h" + 141:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CASE case LORAMAC_REGION_CN470: + 142:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_IS_ACTIVE( ) CN470_CASE { return true; } + 143:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_GET_PHY_PARAM( ) CN470_CASE { return RegionCN470GetPhyParam( getP + 144:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_SET_BAND_TX_DONE( ) CN470_CASE { RegionCN470SetBandTxDone( txDone ); + 145:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_INIT_DEFAULTS( ) CN470_CASE { RegionCN470InitDefaults( type ); br + 146:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_VERIFY( ) CN470_CASE { return RegionCN470Verify( verify, p + 147:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_APPLY_CF_LIST( ) CN470_CASE { RegionCN470ApplyCFList( applyCFList + ARM GAS /tmp/cciGOlRU.s page 4 + + + 148:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHAN_MASK_SET( ) CN470_CASE { return RegionCN470ChanMaskSet( chan + 149:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_ADR_NEXT( ) CN470_CASE { return RegionCN470AdrNext( adrNext, + 150:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_COMPUTE_RX_WINDOW_PARAMETERS( ) CN470_CASE { RegionCN470ComputeRxWindowParameter + 151:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_RX_CONFIG( ) CN470_CASE { return RegionCN470RxConfig( rxConfi + 152:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_TX_CONFIG( ) CN470_CASE { return RegionCN470TxConfig( txConfi + 153:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_LINK_ADR_REQ( ) CN470_CASE { return RegionCN470LinkAdrReq( linkA + 154:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_RX_PARAM_SETUP_REQ( ) CN470_CASE { return RegionCN470RxParamSetupReq( + 155:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_NEW_CHANNEL_REQ( ) CN470_CASE { return RegionCN470NewChannelReq( ne + 156:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_TX_PARAM_SETUP_REQ( ) CN470_CASE { return RegionCN470TxParamSetupReq( + 157:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_DL_CHANNEL_REQ( ) CN470_CASE { return RegionCN470DlChannelReq( dlC + 158:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_ALTERNATE_DR( ) CN470_CASE { return RegionCN470AlternateDr( alte + 159:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CALC_BACKOFF( ) CN470_CASE { RegionCN470CalcBackOff( calcBackOff + 160:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_NEXT_CHANNEL( ) CN470_CASE { return RegionCN470NextChannel( next + 161:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHANNEL_ADD( ) CN470_CASE { return RegionCN470ChannelAdd( chann + 162:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHANNEL_REMOVE( ) CN470_CASE { return RegionCN470ChannelsRemove( c + 163:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_SET_CONTINUOUS_WAVE( ) CN470_CASE { RegionCN470SetContinuousWave( conti + 164:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_APPLY_DR_OFFSET( ) CN470_CASE { return RegionCN470ApplyDrOffset( do + 165:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 166:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_IS_ACTIVE( ) + 167:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_GET_PHY_PARAM( ) + 168:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_SET_BAND_TX_DONE( ) + 169:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_INIT_DEFAULTS( ) + 170:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_VERIFY( ) + 171:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_APPLY_CF_LIST( ) + 172:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHAN_MASK_SET( ) + 173:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_ADR_NEXT( ) + 174:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_COMPUTE_RX_WINDOW_PARAMETERS( ) + 175:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_RX_CONFIG( ) + 176:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_TX_CONFIG( ) + 177:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_LINK_ADR_REQ( ) + 178:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_RX_PARAM_SETUP_REQ( ) + 179:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_NEW_CHANNEL_REQ( ) + 180:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_TX_PARAM_SETUP_REQ( ) + 181:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_DL_CHANNEL_REQ( ) + 182:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_ALTERNATE_DR( ) + 183:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CALC_BACKOFF( ) + 184:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_NEXT_CHANNEL( ) + 185:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHANNEL_ADD( ) + 186:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_CHANNEL_REMOVE( ) + 187:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_SET_CONTINUOUS_WAVE( ) + 188:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN470_APPLY_DR_OFFSET( ) + 189:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 190:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 191:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_CN779 + 192:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionCN779.h" + 193:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CASE case LORAMAC_REGION_CN779: + 194:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_IS_ACTIVE( ) CN779_CASE { return true; } + 195:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_GET_PHY_PARAM( ) CN779_CASE { return RegionCN779GetPhyParam( getP + 196:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_SET_BAND_TX_DONE( ) CN779_CASE { RegionCN779SetBandTxDone( txDone ); + 197:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_INIT_DEFAULTS( ) CN779_CASE { RegionCN779InitDefaults( type ); br + 198:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_VERIFY( ) CN779_CASE { return RegionCN779Verify( verify, p + 199:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_APPLY_CF_LIST( ) CN779_CASE { RegionCN779ApplyCFList( applyCFList + 200:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHAN_MASK_SET( ) CN779_CASE { return RegionCN779ChanMaskSet( chan + 201:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_ADR_NEXT( ) CN779_CASE { return RegionCN779AdrNext( adrNext, + 202:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_COMPUTE_RX_WINDOW_PARAMETERS( ) CN779_CASE { RegionCN779ComputeRxWindowParameter + 203:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_RX_CONFIG( ) CN779_CASE { return RegionCN779RxConfig( rxConfi + 204:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_TX_CONFIG( ) CN779_CASE { return RegionCN779TxConfig( txConfi + ARM GAS /tmp/cciGOlRU.s page 5 + + + 205:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_LINK_ADR_REQ( ) CN779_CASE { return RegionCN779LinkAdrReq( linkA + 206:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_RX_PARAM_SETUP_REQ( ) CN779_CASE { return RegionCN779RxParamSetupReq( + 207:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_NEW_CHANNEL_REQ( ) CN779_CASE { return RegionCN779NewChannelReq( ne + 208:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_TX_PARAM_SETUP_REQ( ) CN779_CASE { return RegionCN779TxParamSetupReq( + 209:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_DL_CHANNEL_REQ( ) CN779_CASE { return RegionCN779DlChannelReq( dlC + 210:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_ALTERNATE_DR( ) CN779_CASE { return RegionCN779AlternateDr( alte + 211:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CALC_BACKOFF( ) CN779_CASE { RegionCN779CalcBackOff( calcBackOff + 212:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_NEXT_CHANNEL( ) CN779_CASE { return RegionCN779NextChannel( next + 213:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHANNEL_ADD( ) CN779_CASE { return RegionCN779ChannelAdd( chann + 214:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHANNEL_REMOVE( ) CN779_CASE { return RegionCN779ChannelsRemove( c + 215:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_SET_CONTINUOUS_WAVE( ) CN779_CASE { RegionCN779SetContinuousWave( conti + 216:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_APPLY_DR_OFFSET( ) CN779_CASE { return RegionCN779ApplyDrOffset( do + 217:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 218:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_IS_ACTIVE( ) + 219:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_GET_PHY_PARAM( ) + 220:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_SET_BAND_TX_DONE( ) + 221:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_INIT_DEFAULTS( ) + 222:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_VERIFY( ) + 223:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_APPLY_CF_LIST( ) + 224:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHAN_MASK_SET( ) + 225:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_ADR_NEXT( ) + 226:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_COMPUTE_RX_WINDOW_PARAMETERS( ) + 227:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_RX_CONFIG( ) + 228:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_TX_CONFIG( ) + 229:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_LINK_ADR_REQ( ) + 230:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_RX_PARAM_SETUP_REQ( ) + 231:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_NEW_CHANNEL_REQ( ) + 232:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_TX_PARAM_SETUP_REQ( ) + 233:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_DL_CHANNEL_REQ( ) + 234:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_ALTERNATE_DR( ) + 235:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CALC_BACKOFF( ) + 236:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_NEXT_CHANNEL( ) + 237:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHANNEL_ADD( ) + 238:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_CHANNEL_REMOVE( ) + 239:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_SET_CONTINUOUS_WAVE( ) + 240:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define CN779_APPLY_DR_OFFSET( ) + 241:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 242:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 243:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_EU433 + 244:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionEU433.h" + 245:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CASE case LORAMAC_REGION_EU433: + 246:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_IS_ACTIVE( ) EU433_CASE { return true; } + 247:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_GET_PHY_PARAM( ) EU433_CASE { return RegionEU433GetPhyParam( getP + 248:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_SET_BAND_TX_DONE( ) EU433_CASE { RegionEU433SetBandTxDone( txDone ); + 249:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_INIT_DEFAULTS( ) EU433_CASE { RegionEU433InitDefaults( type ); br + 250:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_VERIFY( ) EU433_CASE { return RegionEU433Verify( verify, p + 251:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_APPLY_CF_LIST( ) EU433_CASE { RegionEU433ApplyCFList( applyCFList + 252:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHAN_MASK_SET( ) EU433_CASE { return RegionEU433ChanMaskSet( chan + 253:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_ADR_NEXT( ) EU433_CASE { return RegionEU433AdrNext( adrNext, + 254:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_COMPUTE_RX_WINDOW_PARAMETERS( ) EU433_CASE { RegionEU433ComputeRxWindowParameter + 255:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_RX_CONFIG( ) EU433_CASE { return RegionEU433RxConfig( rxConfi + 256:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_TX_CONFIG( ) EU433_CASE { return RegionEU433TxConfig( txConfi + 257:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_LINK_ADR_REQ( ) EU433_CASE { return RegionEU433LinkAdrReq( linkA + 258:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_RX_PARAM_SETUP_REQ( ) EU433_CASE { return RegionEU433RxParamSetupReq( + 259:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_NEW_CHANNEL_REQ( ) EU433_CASE { return RegionEU433NewChannelReq( ne + 260:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_TX_PARAM_SETUP_REQ( ) EU433_CASE { return RegionEU433TxParamSetupReq( + 261:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_DL_CHANNEL_REQ( ) EU433_CASE { return RegionEU433DlChannelReq( dlC + ARM GAS /tmp/cciGOlRU.s page 6 + + + 262:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_ALTERNATE_DR( ) EU433_CASE { return RegionEU433AlternateDr( alte + 263:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CALC_BACKOFF( ) EU433_CASE { RegionEU433CalcBackOff( calcBackOff + 264:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_NEXT_CHANNEL( ) EU433_CASE { return RegionEU433NextChannel( next + 265:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHANNEL_ADD( ) EU433_CASE { return RegionEU433ChannelAdd( chann + 266:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHANNEL_REMOVE( ) EU433_CASE { return RegionEU433ChannelsRemove( c + 267:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_SET_CONTINUOUS_WAVE( ) EU433_CASE { RegionEU433SetContinuousWave( conti + 268:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_APPLY_DR_OFFSET( ) EU433_CASE { return RegionEU433ApplyDrOffset( do + 269:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 270:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_IS_ACTIVE( ) + 271:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_GET_PHY_PARAM( ) + 272:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_SET_BAND_TX_DONE( ) + 273:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_INIT_DEFAULTS( ) + 274:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_VERIFY( ) + 275:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_APPLY_CF_LIST( ) + 276:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHAN_MASK_SET( ) + 277:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_ADR_NEXT( ) + 278:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_COMPUTE_RX_WINDOW_PARAMETERS( ) + 279:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_RX_CONFIG( ) + 280:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_TX_CONFIG( ) + 281:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_LINK_ADR_REQ( ) + 282:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_RX_PARAM_SETUP_REQ( ) + 283:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_NEW_CHANNEL_REQ( ) + 284:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_TX_PARAM_SETUP_REQ( ) + 285:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_DL_CHANNEL_REQ( ) + 286:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_ALTERNATE_DR( ) + 287:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CALC_BACKOFF( ) + 288:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_NEXT_CHANNEL( ) + 289:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHANNEL_ADD( ) + 290:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_CHANNEL_REMOVE( ) + 291:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_SET_CONTINUOUS_WAVE( ) + 292:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU433_APPLY_DR_OFFSET( ) + 293:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 294:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 295:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_EU868 + 296:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionEU868.h" + 297:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CASE case LORAMAC_REGION_EU868: + 298:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_IS_ACTIVE( ) EU868_CASE { return true; } + 299:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_GET_PHY_PARAM( ) EU868_CASE { return RegionEU868GetPhyParam( getP + 300:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_SET_BAND_TX_DONE( ) EU868_CASE { RegionEU868SetBandTxDone( txDone ); + 301:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_INIT_DEFAULTS( ) EU868_CASE { RegionEU868InitDefaults( type ); br + 302:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_VERIFY( ) EU868_CASE { return RegionEU868Verify( verify, p + 303:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_APPLY_CF_LIST( ) EU868_CASE { RegionEU868ApplyCFList( applyCFList + 304:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHAN_MASK_SET( ) EU868_CASE { return RegionEU868ChanMaskSet( chan + 305:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_ADR_NEXT( ) EU868_CASE { return RegionEU868AdrNext( adrNext, + 306:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_COMPUTE_RX_WINDOW_PARAMETERS( ) EU868_CASE { RegionEU868ComputeRxWindowParameter + 307:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_RX_CONFIG( ) EU868_CASE { return RegionEU868RxConfig( rxConfi + 308:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_TX_CONFIG( ) EU868_CASE { return RegionEU868TxConfig( txConfi + 309:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_LINK_ADR_REQ( ) EU868_CASE { return RegionEU868LinkAdrReq( linkA + 310:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_RX_PARAM_SETUP_REQ( ) EU868_CASE { return RegionEU868RxParamSetupReq( + 311:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_NEW_CHANNEL_REQ( ) EU868_CASE { return RegionEU868NewChannelReq( ne + 312:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_TX_PARAM_SETUP_REQ( ) EU868_CASE { return RegionEU868TxParamSetupReq( + 313:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_DL_CHANNEL_REQ( ) EU868_CASE { return RegionEU868DlChannelReq( dlC + 314:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_ALTERNATE_DR( ) EU868_CASE { return RegionEU868AlternateDr( alte + 315:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CALC_BACKOFF( ) EU868_CASE { RegionEU868CalcBackOff( calcBackOff + 316:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_NEXT_CHANNEL( ) EU868_CASE { return RegionEU868NextChannel( next + 317:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHANNEL_ADD( ) EU868_CASE { return RegionEU868ChannelAdd( chann + 318:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHANNEL_REMOVE( ) EU868_CASE { return RegionEU868ChannelsRemove( c + ARM GAS /tmp/cciGOlRU.s page 7 + + + 319:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_SET_CONTINUOUS_WAVE( ) EU868_CASE { RegionEU868SetContinuousWave( conti + 320:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_APPLY_DR_OFFSET( ) EU868_CASE { return RegionEU868ApplyDrOffset( do + 321:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 322:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_IS_ACTIVE( ) + 323:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_GET_PHY_PARAM( ) + 324:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_SET_BAND_TX_DONE( ) + 325:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_INIT_DEFAULTS( ) + 326:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_VERIFY( ) + 327:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_APPLY_CF_LIST( ) + 328:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHAN_MASK_SET( ) + 329:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_ADR_NEXT( ) + 330:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_COMPUTE_RX_WINDOW_PARAMETERS( ) + 331:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_RX_CONFIG( ) + 332:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_TX_CONFIG( ) + 333:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_LINK_ADR_REQ( ) + 334:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_RX_PARAM_SETUP_REQ( ) + 335:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_NEW_CHANNEL_REQ( ) + 336:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_TX_PARAM_SETUP_REQ( ) + 337:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_DL_CHANNEL_REQ( ) + 338:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_ALTERNATE_DR( ) + 339:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CALC_BACKOFF( ) + 340:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_NEXT_CHANNEL( ) + 341:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHANNEL_ADD( ) + 342:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_CHANNEL_REMOVE( ) + 343:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_SET_CONTINUOUS_WAVE( ) + 344:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define EU868_APPLY_DR_OFFSET( ) + 345:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 346:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 347:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_KR920 + 348:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionKR920.h" + 349:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CASE case LORAMAC_REGION_KR920: + 350:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_IS_ACTIVE( ) KR920_CASE { return true; } + 351:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_GET_PHY_PARAM( ) KR920_CASE { return RegionKR920GetPhyParam( getP + 352:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_SET_BAND_TX_DONE( ) KR920_CASE { RegionKR920SetBandTxDone( txDone ); + 353:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_INIT_DEFAULTS( ) KR920_CASE { RegionKR920InitDefaults( type ); br + 354:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_VERIFY( ) KR920_CASE { return RegionKR920Verify( verify, p + 355:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_APPLY_CF_LIST( ) KR920_CASE { RegionKR920ApplyCFList( applyCFList + 356:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHAN_MASK_SET( ) KR920_CASE { return RegionKR920ChanMaskSet( chan + 357:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_ADR_NEXT( ) KR920_CASE { return RegionKR920AdrNext( adrNext, + 358:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_COMPUTE_RX_WINDOW_PARAMETERS( ) KR920_CASE { RegionKR920ComputeRxWindowParameter + 359:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_RX_CONFIG( ) KR920_CASE { return RegionKR920RxConfig( rxConfi + 360:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_TX_CONFIG( ) KR920_CASE { return RegionKR920TxConfig( txConfi + 361:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_LINK_ADR_REQ( ) KR920_CASE { return RegionKR920LinkAdrReq( linkA + 362:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_RX_PARAM_SETUP_REQ( ) KR920_CASE { return RegionKR920RxParamSetupReq( + 363:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_NEW_CHANNEL_REQ( ) KR920_CASE { return RegionKR920NewChannelReq( ne + 364:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_TX_PARAM_SETUP_REQ( ) KR920_CASE { return RegionKR920TxParamSetupReq( + 365:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_DL_CHANNEL_REQ( ) KR920_CASE { return RegionKR920DlChannelReq( dlC + 366:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_ALTERNATE_DR( ) KR920_CASE { return RegionKR920AlternateDr( alte + 367:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CALC_BACKOFF( ) KR920_CASE { RegionKR920CalcBackOff( calcBackOff + 368:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_NEXT_CHANNEL( ) KR920_CASE { return RegionKR920NextChannel( next + 369:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHANNEL_ADD( ) KR920_CASE { return RegionKR920ChannelAdd( chann + 370:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHANNEL_REMOVE( ) KR920_CASE { return RegionKR920ChannelsRemove( c + 371:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_SET_CONTINUOUS_WAVE( ) KR920_CASE { RegionKR920SetContinuousWave( conti + 372:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_APPLY_DR_OFFSET( ) KR920_CASE { return RegionKR920ApplyDrOffset( do + 373:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 374:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_IS_ACTIVE( ) + 375:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_GET_PHY_PARAM( ) + ARM GAS /tmp/cciGOlRU.s page 8 + + + 376:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_SET_BAND_TX_DONE( ) + 377:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_INIT_DEFAULTS( ) + 378:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_VERIFY( ) + 379:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_APPLY_CF_LIST( ) + 380:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHAN_MASK_SET( ) + 381:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_ADR_NEXT( ) + 382:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_COMPUTE_RX_WINDOW_PARAMETERS( ) + 383:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_RX_CONFIG( ) + 384:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_TX_CONFIG( ) + 385:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_LINK_ADR_REQ( ) + 386:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_RX_PARAM_SETUP_REQ( ) + 387:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_NEW_CHANNEL_REQ( ) + 388:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_TX_PARAM_SETUP_REQ( ) + 389:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_DL_CHANNEL_REQ( ) + 390:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_ALTERNATE_DR( ) + 391:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CALC_BACKOFF( ) + 392:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_NEXT_CHANNEL( ) + 393:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHANNEL_ADD( ) + 394:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_CHANNEL_REMOVE( ) + 395:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_SET_CONTINUOUS_WAVE( ) + 396:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define KR920_APPLY_DR_OFFSET( ) + 397:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 398:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 399:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_IN865 + 400:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionIN865.h" + 401:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CASE case LORAMAC_REGION_IN865: + 402:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_IS_ACTIVE( ) IN865_CASE { return true; } + 403:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_GET_PHY_PARAM( ) IN865_CASE { return RegionIN865GetPhyParam( getP + 404:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_SET_BAND_TX_DONE( ) IN865_CASE { RegionIN865SetBandTxDone( txDone ); + 405:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_INIT_DEFAULTS( ) IN865_CASE { RegionIN865InitDefaults( type ); br + 406:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_VERIFY( ) IN865_CASE { return RegionIN865Verify( verify, p + 407:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_APPLY_CF_LIST( ) IN865_CASE { RegionIN865ApplyCFList( applyCFList + 408:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHAN_MASK_SET( ) IN865_CASE { return RegionIN865ChanMaskSet( chan + 409:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_ADR_NEXT( ) IN865_CASE { return RegionIN865AdrNext( adrNext, + 410:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_COMPUTE_RX_WINDOW_PARAMETERS( ) IN865_CASE { RegionIN865ComputeRxWindowParameter + 411:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_RX_CONFIG( ) IN865_CASE { return RegionIN865RxConfig( rxConfi + 412:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_TX_CONFIG( ) IN865_CASE { return RegionIN865TxConfig( txConfi + 413:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_LINK_ADR_REQ( ) IN865_CASE { return RegionIN865LinkAdrReq( linkA + 414:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_RX_PARAM_SETUP_REQ( ) IN865_CASE { return RegionIN865RxParamSetupReq( + 415:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_NEW_CHANNEL_REQ( ) IN865_CASE { return RegionIN865NewChannelReq( ne + 416:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_TX_PARAM_SETUP_REQ( ) IN865_CASE { return RegionIN865TxParamSetupReq( + 417:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_DL_CHANNEL_REQ( ) IN865_CASE { return RegionIN865DlChannelReq( dlC + 418:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_ALTERNATE_DR( ) IN865_CASE { return RegionIN865AlternateDr( alte + 419:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CALC_BACKOFF( ) IN865_CASE { RegionIN865CalcBackOff( calcBackOff + 420:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_NEXT_CHANNEL( ) IN865_CASE { return RegionIN865NextChannel( next + 421:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHANNEL_ADD( ) IN865_CASE { return RegionIN865ChannelAdd( chann + 422:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHANNEL_REMOVE( ) IN865_CASE { return RegionIN865ChannelsRemove( c + 423:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_SET_CONTINUOUS_WAVE( ) IN865_CASE { RegionIN865SetContinuousWave( conti + 424:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_APPLY_DR_OFFSET( ) IN865_CASE { return RegionIN865ApplyDrOffset( do + 425:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 426:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_IS_ACTIVE( ) + 427:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_GET_PHY_PARAM( ) + 428:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_SET_BAND_TX_DONE( ) + 429:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_INIT_DEFAULTS( ) + 430:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_VERIFY( ) + 431:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_APPLY_CF_LIST( ) + 432:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHAN_MASK_SET( ) + ARM GAS /tmp/cciGOlRU.s page 9 + + + 433:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_ADR_NEXT( ) + 434:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_COMPUTE_RX_WINDOW_PARAMETERS( ) + 435:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_RX_CONFIG( ) + 436:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_TX_CONFIG( ) + 437:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_LINK_ADR_REQ( ) + 438:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_RX_PARAM_SETUP_REQ( ) + 439:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_NEW_CHANNEL_REQ( ) + 440:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_TX_PARAM_SETUP_REQ( ) + 441:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_DL_CHANNEL_REQ( ) + 442:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_ALTERNATE_DR( ) + 443:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CALC_BACKOFF( ) + 444:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_NEXT_CHANNEL( ) + 445:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHANNEL_ADD( ) + 446:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_CHANNEL_REMOVE( ) + 447:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_SET_CONTINUOUS_WAVE( ) + 448:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define IN865_APPLY_DR_OFFSET( ) + 449:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 450:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 451:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_US915 + 452:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionUS915.h" + 453:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CASE case LORAMAC_REGION_US915: + 454:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_IS_ACTIVE( ) US915_CASE { return true; } + 455:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_GET_PHY_PARAM( ) US915_CASE { return RegionUS915GetPhyParam( getP + 456:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_SET_BAND_TX_DONE( ) US915_CASE { RegionUS915SetBandTxDone( txDone ); + 457:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_INIT_DEFAULTS( ) US915_CASE { RegionUS915InitDefaults( type ); br + 458:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_VERIFY( ) US915_CASE { return RegionUS915Verify( verify, p + 459:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_APPLY_CF_LIST( ) US915_CASE { RegionUS915ApplyCFList( applyCFList + 460:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHAN_MASK_SET( ) US915_CASE { return RegionUS915ChanMaskSet( chan + 461:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_ADR_NEXT( ) US915_CASE { return RegionUS915AdrNext( adrNext, + 462:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_COMPUTE_RX_WINDOW_PARAMETERS( ) US915_CASE { RegionUS915ComputeRxWindowParameter + 463:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_RX_CONFIG( ) US915_CASE { return RegionUS915RxConfig( rxConfi + 464:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_TX_CONFIG( ) US915_CASE { return RegionUS915TxConfig( txConfi + 465:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_LINK_ADR_REQ( ) US915_CASE { return RegionUS915LinkAdrReq( linkA + 466:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_RX_PARAM_SETUP_REQ( ) US915_CASE { return RegionUS915RxParamSetupReq( + 467:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_NEW_CHANNEL_REQ( ) US915_CASE { return RegionUS915NewChannelReq( ne + 468:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_TX_PARAM_SETUP_REQ( ) US915_CASE { return RegionUS915TxParamSetupReq( + 469:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_DL_CHANNEL_REQ( ) US915_CASE { return RegionUS915DlChannelReq( dlC + 470:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_ALTERNATE_DR( ) US915_CASE { return RegionUS915AlternateDr( alte + 471:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CALC_BACKOFF( ) US915_CASE { RegionUS915CalcBackOff( calcBackOff + 472:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_NEXT_CHANNEL( ) US915_CASE { return RegionUS915NextChannel( next + 473:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHANNEL_ADD( ) US915_CASE { return RegionUS915ChannelAdd( chann + 474:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHANNEL_REMOVE( ) US915_CASE { return RegionUS915ChannelsRemove( c + 475:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_SET_CONTINUOUS_WAVE( ) US915_CASE { RegionUS915SetContinuousWave( conti + 476:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_APPLY_DR_OFFSET( ) US915_CASE { return RegionUS915ApplyDrOffset( do + 477:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 478:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_IS_ACTIVE( ) + 479:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_GET_PHY_PARAM( ) + 480:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_SET_BAND_TX_DONE( ) + 481:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_INIT_DEFAULTS( ) + 482:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_VERIFY( ) + 483:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_APPLY_CF_LIST( ) + 484:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHAN_MASK_SET( ) + 485:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_ADR_NEXT( ) + 486:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_COMPUTE_RX_WINDOW_PARAMETERS( ) + 487:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_RX_CONFIG( ) + 488:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_TX_CONFIG( ) + 489:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_LINK_ADR_REQ( ) + ARM GAS /tmp/cciGOlRU.s page 10 + + + 490:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_RX_PARAM_SETUP_REQ( ) + 491:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_NEW_CHANNEL_REQ( ) + 492:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_TX_PARAM_SETUP_REQ( ) + 493:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_DL_CHANNEL_REQ( ) + 494:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_ALTERNATE_DR( ) + 495:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CALC_BACKOFF( ) + 496:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_NEXT_CHANNEL( ) + 497:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHANNEL_ADD( ) + 498:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_CHANNEL_REMOVE( ) + 499:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_SET_CONTINUOUS_WAVE( ) + 500:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_APPLY_DR_OFFSET( ) + 501:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 502:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 503:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #ifdef REGION_US915_HYBRID + 504:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #include "RegionUS915-Hybrid.h" + 505:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CASE case LORAMAC_REGION_US915_HYBRID: + 506:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_IS_ACTIVE( ) US915_HYBRID_CASE { return true; } + 507:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_GET_PHY_PARAM( ) US915_HYBRID_CASE { return RegionUS915Hyb + 508:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_SET_BAND_TX_DONE( ) US915_HYBRID_CASE { RegionUS915HybridSetB + 509:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_INIT_DEFAULTS( ) US915_HYBRID_CASE { RegionUS915HybridInit + 510:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_VERIFY( ) US915_HYBRID_CASE { return RegionUS915Hyb + 511:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_APPLY_CF_LIST( ) US915_HYBRID_CASE { RegionUS915HybridAppl + 512:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHAN_MASK_SET( ) US915_HYBRID_CASE { return RegionUS915Hyb + 513:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_ADR_NEXT( ) US915_HYBRID_CASE { return RegionUS915Hyb + 514:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ) US915_HYBRID_CASE { RegionUS915HybridComp + 515:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_RX_CONFIG( ) US915_HYBRID_CASE { return RegionUS915Hyb + 516:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_TX_CONFIG( ) US915_HYBRID_CASE { return RegionUS915Hyb + 517:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_LINK_ADR_REQ( ) US915_HYBRID_CASE { return RegionUS915Hyb + 518:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_RX_PARAM_SETUP_REQ( ) US915_HYBRID_CASE { return RegionUS915Hyb + 519:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_NEW_CHANNEL_REQ( ) US915_HYBRID_CASE { return RegionUS915Hyb + 520:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_TX_PARAM_SETUP_REQ( ) US915_HYBRID_CASE { return RegionUS915Hyb + 521:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_DL_CHANNEL_REQ( ) US915_HYBRID_CASE { return RegionUS915Hyb + 522:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_ALTERNATE_DR( ) US915_HYBRID_CASE { return RegionUS915Hyb + 523:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CALC_BACKOFF( ) US915_HYBRID_CASE { RegionUS915HybridCalc + 524:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_NEXT_CHANNEL( ) US915_HYBRID_CASE { return RegionUS915Hyb + 525:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHANNEL_ADD( ) US915_HYBRID_CASE { return RegionUS915Hyb + 526:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHANNEL_REMOVE( ) US915_HYBRID_CASE { return RegionUS915Hyb + 527:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_SET_CONTINUOUS_WAVE( ) US915_HYBRID_CASE { RegionUS915HybridSetC + 528:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_APPLY_DR_OFFSET( ) US915_HYBRID_CASE { return RegionUS915Hyb + 529:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #else + 530:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_IS_ACTIVE( ) + 531:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_GET_PHY_PARAM( ) + 532:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_SET_BAND_TX_DONE( ) + 533:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_INIT_DEFAULTS( ) + 534:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_VERIFY( ) + 535:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_APPLY_CF_LIST( ) + 536:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHAN_MASK_SET( ) + 537:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_ADR_NEXT( ) + 538:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ) + 539:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_RX_CONFIG( ) + 540:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_TX_CONFIG( ) + 541:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_LINK_ADR_REQ( ) + 542:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_RX_PARAM_SETUP_REQ( ) + 543:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_NEW_CHANNEL_REQ( ) + 544:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_TX_PARAM_SETUP_REQ( ) + 545:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_DL_CHANNEL_REQ( ) + 546:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_ALTERNATE_DR( ) + ARM GAS /tmp/cciGOlRU.s page 11 + + + 547:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CALC_BACKOFF( ) + 548:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_NEXT_CHANNEL( ) + 549:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHANNEL_ADD( ) + 550:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_CHANNEL_REMOVE( ) + 551:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_SET_CONTINUOUS_WAVE( ) + 552:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #define US915_HYBRID_APPLY_DR_OFFSET( ) + 553:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** #endif + 554:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 555:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionIsActive( LoRaMacRegion_t region ) + 556:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 26 .loc 1 556 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 557:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 32 .loc 1 557 0 + 33 0000 0528 cmp r0, #5 + 34 0002 01D0 beq .L6 + 558:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 559:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_IS_ACTIVE( ); + 560:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_IS_ACTIVE( ); + 561:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_IS_ACTIVE( ); + 562:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_IS_ACTIVE( ); + 563:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_IS_ACTIVE( ); + 564:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_IS_ACTIVE( ); + 565:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_IS_ACTIVE( ); + 566:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_IS_ACTIVE( ); + 567:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_IS_ACTIVE( ); + 568:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_IS_ACTIVE( ); + 569:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 570:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 571:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 35 .loc 1 571 0 + 36 0004 0020 movs r0, #0 + 37 .LVL1: + 38 .L2: + 572:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 573:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 574:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 39 .loc 1 574 0 + 40 @ sp needed + 41 0006 7047 bx lr + 42 .LVL2: + 43 .L6: + 564:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_IS_ACTIVE( ); + 44 .loc 1 564 0 + 45 0008 0438 subs r0, r0, #4 + 46 .LVL3: + 47 000a FCE7 b .L2 + 48 .cfi_endproc + 49 .LFE82: + 51 .section .text.RegionGetPhyParam,"ax",%progbits + 52 .align 1 + 53 .global RegionGetPhyParam + 54 .syntax unified + ARM GAS /tmp/cciGOlRU.s page 12 + + + 55 .code 16 + 56 .thumb_func + 57 .fpu softvfp + 59 RegionGetPhyParam: + 60 .LFB83: + 575:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 576:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** PhyParam_t RegionGetPhyParam( LoRaMacRegion_t region, GetPhyParams_t* getPhy ) + 577:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 61 .loc 1 577 0 + 62 .cfi_startproc + 63 @ args = 0, pretend = 0, frame = 0 + 64 @ frame_needed = 0, uses_anonymous_args = 0 + 65 .LVL4: + 66 0000 10B5 push {r4, lr} + 67 .LCFI0: + 68 .cfi_def_cfa_offset 8 + 69 .cfi_offset 4, -8 + 70 .cfi_offset 14, -4 + 578:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** PhyParam_t phyParam = { 0 }; + 579:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 71 .loc 1 579 0 + 72 0002 0528 cmp r0, #5 + 73 0004 01D0 beq .L12 + 580:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 581:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_GET_PHY_PARAM( ); + 582:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_GET_PHY_PARAM( ); + 583:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_GET_PHY_PARAM( ); + 584:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_GET_PHY_PARAM( ); + 585:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_GET_PHY_PARAM( ); + 586:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_GET_PHY_PARAM( ); + 587:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_GET_PHY_PARAM( ); + 588:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_GET_PHY_PARAM( ); + 589:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_GET_PHY_PARAM( ); + 590:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_GET_PHY_PARAM( ); + 591:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 592:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 593:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return phyParam; + 74 .loc 1 593 0 + 75 0006 0020 movs r0, #0 + 76 .LVL5: + 77 .L10: + 594:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 595:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 596:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 78 .loc 1 596 0 + 79 @ sp needed + 80 0008 10BD pop {r4, pc} + 81 .LVL6: + 82 .L12: + 586:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_GET_PHY_PARAM( ); + 83 .loc 1 586 0 + 84 000a 0800 movs r0, r1 + 85 .LVL7: + 86 000c FFF7FEFF bl RegionEU868GetPhyParam + 87 .LVL8: + 88 0010 FAE7 b .L10 + 89 .cfi_endproc + ARM GAS /tmp/cciGOlRU.s page 13 + + + 90 .LFE83: + 92 .section .text.RegionSetBandTxDone,"ax",%progbits + 93 .align 1 + 94 .global RegionSetBandTxDone + 95 .syntax unified + 96 .code 16 + 97 .thumb_func + 98 .fpu softvfp + 100 RegionSetBandTxDone: + 101 .LFB84: + 597:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 598:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionSetBandTxDone( LoRaMacRegion_t region, SetBandTxDoneParams_t* txDone ) + 599:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 102 .loc 1 599 0 + 103 .cfi_startproc + 104 @ args = 0, pretend = 0, frame = 0 + 105 @ frame_needed = 0, uses_anonymous_args = 0 + 106 .LVL9: + 107 0000 10B5 push {r4, lr} + 108 .LCFI1: + 109 .cfi_def_cfa_offset 8 + 110 .cfi_offset 4, -8 + 111 .cfi_offset 14, -4 + 600:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 112 .loc 1 600 0 + 113 0002 0528 cmp r0, #5 + 114 0004 00D0 beq .L16 + 115 .LVL10: + 116 .L13: + 601:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 602:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_SET_BAND_TX_DONE( ); + 603:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_SET_BAND_TX_DONE( ); + 604:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_SET_BAND_TX_DONE( ); + 605:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_SET_BAND_TX_DONE( ); + 606:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_SET_BAND_TX_DONE( ); + 607:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_SET_BAND_TX_DONE( ); + 608:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_SET_BAND_TX_DONE( ); + 609:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_SET_BAND_TX_DONE( ); + 610:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_SET_BAND_TX_DONE( ); + 611:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_SET_BAND_TX_DONE( ); + 612:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 613:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 614:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return; + 615:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 616:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 617:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 117 .loc 1 617 0 + 118 @ sp needed + 119 0006 10BD pop {r4, pc} + 120 .LVL11: + 121 .L16: + 607:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_SET_BAND_TX_DONE( ); + 122 .loc 1 607 0 + 123 0008 0800 movs r0, r1 + 124 .LVL12: + 125 000a FFF7FEFF bl RegionEU868SetBandTxDone + 126 .LVL13: + ARM GAS /tmp/cciGOlRU.s page 14 + + + 127 000e FAE7 b .L13 + 128 .cfi_endproc + 129 .LFE84: + 131 .section .text.RegionInitDefaults,"ax",%progbits + 132 .align 1 + 133 .global RegionInitDefaults + 134 .syntax unified + 135 .code 16 + 136 .thumb_func + 137 .fpu softvfp + 139 RegionInitDefaults: + 140 .LFB85: + 618:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 619:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionInitDefaults( LoRaMacRegion_t region, InitType_t type ) + 620:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 141 .loc 1 620 0 + 142 .cfi_startproc + 143 @ args = 0, pretend = 0, frame = 0 + 144 @ frame_needed = 0, uses_anonymous_args = 0 + 145 .LVL14: + 146 0000 10B5 push {r4, lr} + 147 .LCFI2: + 148 .cfi_def_cfa_offset 8 + 149 .cfi_offset 4, -8 + 150 .cfi_offset 14, -4 + 621:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 151 .loc 1 621 0 + 152 0002 0528 cmp r0, #5 + 153 0004 00D0 beq .L20 + 154 .LVL15: + 155 .L17: + 622:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 623:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_INIT_DEFAULTS( ); + 624:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_INIT_DEFAULTS( ); + 625:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_INIT_DEFAULTS( ); + 626:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_INIT_DEFAULTS( ); + 627:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_INIT_DEFAULTS( ); + 628:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_INIT_DEFAULTS( ); + 629:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_INIT_DEFAULTS( ); + 630:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_INIT_DEFAULTS( ); + 631:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_INIT_DEFAULTS( ); + 632:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_INIT_DEFAULTS( ); + 633:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 634:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 635:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** break; + 636:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 637:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 638:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 156 .loc 1 638 0 + 157 @ sp needed + 158 0006 10BD pop {r4, pc} + 159 .LVL16: + 160 .L20: + 628:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_INIT_DEFAULTS( ); + 161 .loc 1 628 0 + 162 0008 0800 movs r0, r1 + 163 .LVL17: + ARM GAS /tmp/cciGOlRU.s page 15 + + + 164 000a FFF7FEFF bl RegionEU868InitDefaults + 165 .LVL18: + 166 .loc 1 638 0 + 167 000e FAE7 b .L17 + 168 .cfi_endproc + 169 .LFE85: + 171 .section .text.RegionVerify,"ax",%progbits + 172 .align 1 + 173 .global RegionVerify + 174 .syntax unified + 175 .code 16 + 176 .thumb_func + 177 .fpu softvfp + 179 RegionVerify: + 180 .LFB86: + 639:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 640:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionVerify( LoRaMacRegion_t region, VerifyParams_t* verify, PhyAttribute_t phyAttribute ) + 641:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 181 .loc 1 641 0 + 182 .cfi_startproc + 183 @ args = 0, pretend = 0, frame = 0 + 184 @ frame_needed = 0, uses_anonymous_args = 0 + 185 .LVL19: + 186 0000 10B5 push {r4, lr} + 187 .LCFI3: + 188 .cfi_def_cfa_offset 8 + 189 .cfi_offset 4, -8 + 190 .cfi_offset 14, -4 + 191 0002 0B00 movs r3, r1 + 642:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 192 .loc 1 642 0 + 193 0004 0528 cmp r0, #5 + 194 0006 01D0 beq .L26 + 643:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 644:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_VERIFY( ); + 645:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_VERIFY( ); + 646:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_VERIFY( ); + 647:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_VERIFY( ); + 648:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_VERIFY( ); + 649:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_VERIFY( ); + 650:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_VERIFY( ); + 651:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_VERIFY( ); + 652:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_VERIFY( ); + 653:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_VERIFY( ); + 654:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 655:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 656:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 195 .loc 1 656 0 + 196 0008 0020 movs r0, #0 + 197 .LVL20: + 198 .L22: + 657:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 658:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 659:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 199 .loc 1 659 0 + 200 @ sp needed + 201 000a 10BD pop {r4, pc} + ARM GAS /tmp/cciGOlRU.s page 16 + + + 202 .LVL21: + 203 .L26: + 649:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_VERIFY( ); + 204 .loc 1 649 0 + 205 000c 1100 movs r1, r2 + 206 .LVL22: + 207 000e 1800 movs r0, r3 + 208 .LVL23: + 209 0010 FFF7FEFF bl RegionEU868Verify + 210 .LVL24: + 211 0014 F9E7 b .L22 + 212 .cfi_endproc + 213 .LFE86: + 215 .section .text.RegionApplyCFList,"ax",%progbits + 216 .align 1 + 217 .global RegionApplyCFList + 218 .syntax unified + 219 .code 16 + 220 .thumb_func + 221 .fpu softvfp + 223 RegionApplyCFList: + 224 .LFB87: + 660:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 661:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionApplyCFList( LoRaMacRegion_t region, ApplyCFListParams_t* applyCFList ) + 662:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 225 .loc 1 662 0 + 226 .cfi_startproc + 227 @ args = 0, pretend = 0, frame = 0 + 228 @ frame_needed = 0, uses_anonymous_args = 0 + 229 .LVL25: + 230 0000 10B5 push {r4, lr} + 231 .LCFI4: + 232 .cfi_def_cfa_offset 8 + 233 .cfi_offset 4, -8 + 234 .cfi_offset 14, -4 + 663:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 235 .loc 1 663 0 + 236 0002 0528 cmp r0, #5 + 237 0004 00D0 beq .L30 + 238 .LVL26: + 239 .L27: + 664:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 665:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_APPLY_CF_LIST( ); + 666:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_APPLY_CF_LIST( ); + 667:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_APPLY_CF_LIST( ); + 668:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_APPLY_CF_LIST( ); + 669:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_APPLY_CF_LIST( ); + 670:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_APPLY_CF_LIST( ); + 671:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_APPLY_CF_LIST( ); + 672:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_APPLY_CF_LIST( ); + 673:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_APPLY_CF_LIST( ); + 674:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_APPLY_CF_LIST( ); + 675:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 676:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 677:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** break; + 678:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 679:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + ARM GAS /tmp/cciGOlRU.s page 17 + + + 680:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 240 .loc 1 680 0 + 241 @ sp needed + 242 0006 10BD pop {r4, pc} + 243 .LVL27: + 244 .L30: + 670:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_APPLY_CF_LIST( ); + 245 .loc 1 670 0 + 246 0008 0800 movs r0, r1 + 247 .LVL28: + 248 000a FFF7FEFF bl RegionEU868ApplyCFList + 249 .LVL29: + 250 .loc 1 680 0 + 251 000e FAE7 b .L27 + 252 .cfi_endproc + 253 .LFE87: + 255 .section .text.RegionChanMaskSet,"ax",%progbits + 256 .align 1 + 257 .global RegionChanMaskSet + 258 .syntax unified + 259 .code 16 + 260 .thumb_func + 261 .fpu softvfp + 263 RegionChanMaskSet: + 264 .LFB88: + 681:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 682:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionChanMaskSet( LoRaMacRegion_t region, ChanMaskSetParams_t* chanMaskSet ) + 683:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 265 .loc 1 683 0 + 266 .cfi_startproc + 267 @ args = 0, pretend = 0, frame = 0 + 268 @ frame_needed = 0, uses_anonymous_args = 0 + 269 .LVL30: + 270 0000 10B5 push {r4, lr} + 271 .LCFI5: + 272 .cfi_def_cfa_offset 8 + 273 .cfi_offset 4, -8 + 274 .cfi_offset 14, -4 + 684:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 275 .loc 1 684 0 + 276 0002 0528 cmp r0, #5 + 277 0004 01D0 beq .L36 + 685:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 686:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_CHAN_MASK_SET( ); + 687:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_CHAN_MASK_SET( ); + 688:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_CHAN_MASK_SET( ); + 689:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_CHAN_MASK_SET( ); + 690:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_CHAN_MASK_SET( ); + 691:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_CHAN_MASK_SET( ); + 692:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CHAN_MASK_SET( ); + 693:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_CHAN_MASK_SET( ); + 694:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_CHAN_MASK_SET( ); + 695:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_CHAN_MASK_SET( ); + 696:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 697:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 698:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 278 .loc 1 698 0 + ARM GAS /tmp/cciGOlRU.s page 18 + + + 279 0006 0020 movs r0, #0 + 280 .LVL31: + 281 .L32: + 699:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 700:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 701:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 282 .loc 1 701 0 + 283 @ sp needed + 284 0008 10BD pop {r4, pc} + 285 .LVL32: + 286 .L36: + 691:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CHAN_MASK_SET( ); + 287 .loc 1 691 0 + 288 000a 0800 movs r0, r1 + 289 .LVL33: + 290 000c FFF7FEFF bl RegionEU868ChanMaskSet + 291 .LVL34: + 292 0010 FAE7 b .L32 + 293 .cfi_endproc + 294 .LFE88: + 296 .section .text.RegionAdrNext,"ax",%progbits + 297 .align 1 + 298 .global RegionAdrNext + 299 .syntax unified + 300 .code 16 + 301 .thumb_func + 302 .fpu softvfp + 304 RegionAdrNext: + 305 .LFB89: + 702:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 703:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionAdrNext( LoRaMacRegion_t region, AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowO + 704:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 306 .loc 1 704 0 + 307 .cfi_startproc + 308 @ args = 4, pretend = 0, frame = 0 + 309 @ frame_needed = 0, uses_anonymous_args = 0 + 310 .LVL35: + 311 0000 10B5 push {r4, lr} + 312 .LCFI6: + 313 .cfi_def_cfa_offset 8 + 314 .cfi_offset 4, -8 + 315 .cfi_offset 14, -4 + 316 0002 0C00 movs r4, r1 + 317 0004 1100 movs r1, r2 + 318 .LVL36: + 319 0006 1A00 movs r2, r3 + 320 .LVL37: + 705:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 321 .loc 1 705 0 + 322 0008 0528 cmp r0, #5 + 323 000a 01D0 beq .L42 + 706:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 707:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_ADR_NEXT( ); + 708:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_ADR_NEXT( ); + 709:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_ADR_NEXT( ); + 710:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_ADR_NEXT( ); + 711:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_ADR_NEXT( ); + ARM GAS /tmp/cciGOlRU.s page 19 + + + 712:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_ADR_NEXT( ); + 713:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_ADR_NEXT( ); + 714:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_ADR_NEXT( ); + 715:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_ADR_NEXT( ); + 716:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_ADR_NEXT( ); + 717:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 718:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 719:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 324 .loc 1 719 0 + 325 000c 0020 movs r0, #0 + 326 .LVL38: + 327 .L38: + 720:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 721:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 722:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 328 .loc 1 722 0 + 329 @ sp needed + 330 .LVL39: + 331 000e 10BD pop {r4, pc} + 332 .LVL40: + 333 .L42: + 712:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_ADR_NEXT( ); + 334 .loc 1 712 0 + 335 0010 029B ldr r3, [sp, #8] + 336 0012 2000 movs r0, r4 + 337 .LVL41: + 338 0014 FFF7FEFF bl RegionEU868AdrNext + 339 .LVL42: + 340 0018 F9E7 b .L38 + 341 .cfi_endproc + 342 .LFE89: + 344 .section .text.RegionComputeRxWindowParameters,"ax",%progbits + 345 .align 1 + 346 .global RegionComputeRxWindowParameters + 347 .syntax unified + 348 .code 16 + 349 .thumb_func + 350 .fpu softvfp + 352 RegionComputeRxWindowParameters: + 353 .LFB90: + 723:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 724:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionComputeRxWindowParameters( LoRaMacRegion_t region, int8_t datarate, uint8_t minRxSymbols + 725:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 354 .loc 1 725 0 + 355 .cfi_startproc + 356 @ args = 4, pretend = 0, frame = 0 + 357 @ frame_needed = 0, uses_anonymous_args = 0 + 358 .LVL43: + 359 0000 10B5 push {r4, lr} + 360 .LCFI7: + 361 .cfi_def_cfa_offset 8 + 362 .cfi_offset 4, -8 + 363 .cfi_offset 14, -4 + 364 0002 0C00 movs r4, r1 + 365 0004 1100 movs r1, r2 + 366 .LVL44: + 367 0006 1A00 movs r2, r3 + ARM GAS /tmp/cciGOlRU.s page 20 + + + 368 .LVL45: + 726:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 369 .loc 1 726 0 + 370 0008 0528 cmp r0, #5 + 371 000a 00D0 beq .L46 + 372 .LVL46: + 373 .L43: + 727:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 728:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_COMPUTE_RX_WINDOW_PARAMETERS( ); + 729:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_COMPUTE_RX_WINDOW_PARAMETERS( ); + 730:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_COMPUTE_RX_WINDOW_PARAMETERS( ); + 731:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_COMPUTE_RX_WINDOW_PARAMETERS( ); + 732:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_COMPUTE_RX_WINDOW_PARAMETERS( ); + 733:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_COMPUTE_RX_WINDOW_PARAMETERS( ); + 734:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_COMPUTE_RX_WINDOW_PARAMETERS( ); + 735:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_COMPUTE_RX_WINDOW_PARAMETERS( ); + 736:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_COMPUTE_RX_WINDOW_PARAMETERS( ); + 737:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ); + 738:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 739:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 740:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** break; + 741:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 742:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 743:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 374 .loc 1 743 0 + 375 @ sp needed + 376 000c 10BD pop {r4, pc} + 377 .LVL47: + 378 .L46: + 733:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_COMPUTE_RX_WINDOW_PARAMETERS( ); + 379 .loc 1 733 0 + 380 000e 029B ldr r3, [sp, #8] + 381 0010 2000 movs r0, r4 + 382 .LVL48: + 383 0012 FFF7FEFF bl RegionEU868ComputeRxWindowParameters + 384 .LVL49: + 385 .loc 1 743 0 + 386 0016 F9E7 b .L43 + 387 .cfi_endproc + 388 .LFE90: + 390 .section .text.RegionRxConfig,"ax",%progbits + 391 .align 1 + 392 .global RegionRxConfig + 393 .syntax unified + 394 .code 16 + 395 .thumb_func + 396 .fpu softvfp + 398 RegionRxConfig: + 399 .LFB91: + 744:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 745:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionRxConfig( LoRaMacRegion_t region, RxConfigParams_t* rxConfig, int8_t* datarate ) + 746:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 400 .loc 1 746 0 + 401 .cfi_startproc + 402 @ args = 0, pretend = 0, frame = 0 + 403 @ frame_needed = 0, uses_anonymous_args = 0 + 404 .LVL50: + ARM GAS /tmp/cciGOlRU.s page 21 + + + 405 0000 10B5 push {r4, lr} + 406 .LCFI8: + 407 .cfi_def_cfa_offset 8 + 408 .cfi_offset 4, -8 + 409 .cfi_offset 14, -4 + 410 0002 0B00 movs r3, r1 + 747:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 411 .loc 1 747 0 + 412 0004 0528 cmp r0, #5 + 413 0006 01D0 beq .L52 + 748:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 749:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_RX_CONFIG( ); + 750:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_RX_CONFIG( ); + 751:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_RX_CONFIG( ); + 752:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_RX_CONFIG( ); + 753:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_RX_CONFIG( ); + 754:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_RX_CONFIG( ); + 755:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_RX_CONFIG( ); + 756:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_RX_CONFIG( ); + 757:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_RX_CONFIG( ); + 758:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_RX_CONFIG( ); + 759:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 760:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 761:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 414 .loc 1 761 0 + 415 0008 0020 movs r0, #0 + 416 .LVL51: + 417 .L48: + 762:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 763:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 764:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 418 .loc 1 764 0 + 419 @ sp needed + 420 000a 10BD pop {r4, pc} + 421 .LVL52: + 422 .L52: + 754:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_RX_CONFIG( ); + 423 .loc 1 754 0 + 424 000c 1100 movs r1, r2 + 425 .LVL53: + 426 000e 1800 movs r0, r3 + 427 .LVL54: + 428 0010 FFF7FEFF bl RegionEU868RxConfig + 429 .LVL55: + 430 0014 F9E7 b .L48 + 431 .cfi_endproc + 432 .LFE91: + 434 .section .text.RegionTxConfig,"ax",%progbits + 435 .align 1 + 436 .global RegionTxConfig + 437 .syntax unified + 438 .code 16 + 439 .thumb_func + 440 .fpu softvfp + 442 RegionTxConfig: + 443 .LFB92: + 765:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + ARM GAS /tmp/cciGOlRU.s page 22 + + + 766:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionTxConfig( LoRaMacRegion_t region, TxConfigParams_t* txConfig, int8_t* txPower, TimerTime + 767:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 444 .loc 1 767 0 + 445 .cfi_startproc + 446 @ args = 0, pretend = 0, frame = 0 + 447 @ frame_needed = 0, uses_anonymous_args = 0 + 448 .LVL56: + 449 0000 10B5 push {r4, lr} + 450 .LCFI9: + 451 .cfi_def_cfa_offset 8 + 452 .cfi_offset 4, -8 + 453 .cfi_offset 14, -4 + 454 0002 0C00 movs r4, r1 + 455 0004 1100 movs r1, r2 + 456 .LVL57: + 768:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 457 .loc 1 768 0 + 458 0006 0528 cmp r0, #5 + 459 0008 01D0 beq .L58 + 769:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 770:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_TX_CONFIG( ); + 771:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_TX_CONFIG( ); + 772:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_TX_CONFIG( ); + 773:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_TX_CONFIG( ); + 774:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_TX_CONFIG( ); + 775:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_TX_CONFIG( ); + 776:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_TX_CONFIG( ); + 777:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_TX_CONFIG( ); + 778:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_TX_CONFIG( ); + 779:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_TX_CONFIG( ); + 780:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 781:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 782:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 460 .loc 1 782 0 + 461 000a 0020 movs r0, #0 + 462 .LVL58: + 463 .L54: + 783:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 784:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 785:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 464 .loc 1 785 0 + 465 @ sp needed + 466 .LVL59: + 467 000c 10BD pop {r4, pc} + 468 .LVL60: + 469 .L58: + 775:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_TX_CONFIG( ); + 470 .loc 1 775 0 + 471 000e 1A00 movs r2, r3 + 472 0010 2000 movs r0, r4 + 473 .LVL61: + 474 0012 FFF7FEFF bl RegionEU868TxConfig + 475 .LVL62: + 476 0016 F9E7 b .L54 + 477 .cfi_endproc + 478 .LFE92: + 480 .section .text.RegionLinkAdrReq,"ax",%progbits + ARM GAS /tmp/cciGOlRU.s page 23 + + + 481 .align 1 + 482 .global RegionLinkAdrReq + 483 .syntax unified + 484 .code 16 + 485 .thumb_func + 486 .fpu softvfp + 488 RegionLinkAdrReq: + 489 .LFB93: + 786:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 787:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** uint8_t RegionLinkAdrReq( LoRaMacRegion_t region, LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, in + 788:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 490 .loc 1 788 0 + 491 .cfi_startproc + 492 @ args = 8, pretend = 0, frame = 0 + 493 @ frame_needed = 0, uses_anonymous_args = 0 + 494 .LVL63: + 495 0000 10B5 push {r4, lr} + 496 .LCFI10: + 497 .cfi_def_cfa_offset 8 + 498 .cfi_offset 4, -8 + 499 .cfi_offset 14, -4 + 500 0002 82B0 sub sp, sp, #8 + 501 .LCFI11: + 502 .cfi_def_cfa_offset 16 + 503 0004 0C00 movs r4, r1 + 504 0006 1100 movs r1, r2 + 505 .LVL64: + 506 0008 1A00 movs r2, r3 + 507 .LVL65: + 789:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 508 .loc 1 789 0 + 509 000a 0528 cmp r0, #5 + 510 000c 02D0 beq .L64 + 790:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 791:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_LINK_ADR_REQ( ); + 792:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_LINK_ADR_REQ( ); + 793:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_LINK_ADR_REQ( ); + 794:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_LINK_ADR_REQ( ); + 795:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_LINK_ADR_REQ( ); + 796:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_LINK_ADR_REQ( ); + 797:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_LINK_ADR_REQ( ); + 798:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_LINK_ADR_REQ( ); + 799:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_LINK_ADR_REQ( ); + 800:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_LINK_ADR_REQ( ); + 801:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 802:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 803:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 511 .loc 1 803 0 + 512 000e 0020 movs r0, #0 + 513 .LVL66: + 514 .L60: + 804:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 805:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 806:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 515 .loc 1 806 0 + 516 0010 02B0 add sp, sp, #8 + 517 @ sp needed + ARM GAS /tmp/cciGOlRU.s page 24 + + + 518 .LVL67: + 519 0012 10BD pop {r4, pc} + 520 .LVL68: + 521 .L64: + 796:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_LINK_ADR_REQ( ); + 522 .loc 1 796 0 + 523 0014 059B ldr r3, [sp, #20] + 524 0016 0093 str r3, [sp] + 525 0018 049B ldr r3, [sp, #16] + 526 001a 2000 movs r0, r4 + 527 .LVL69: + 528 001c FFF7FEFF bl RegionEU868LinkAdrReq + 529 .LVL70: + 530 0020 F6E7 b .L60 + 531 .cfi_endproc + 532 .LFE93: + 534 .section .text.RegionRxParamSetupReq,"ax",%progbits + 535 .align 1 + 536 .global RegionRxParamSetupReq + 537 .syntax unified + 538 .code 16 + 539 .thumb_func + 540 .fpu softvfp + 542 RegionRxParamSetupReq: + 543 .LFB94: + 807:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 808:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** uint8_t RegionRxParamSetupReq( LoRaMacRegion_t region, RxParamSetupReqParams_t* rxParamSetupReq ) + 809:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 544 .loc 1 809 0 + 545 .cfi_startproc + 546 @ args = 0, pretend = 0, frame = 0 + 547 @ frame_needed = 0, uses_anonymous_args = 0 + 548 .LVL71: + 549 0000 10B5 push {r4, lr} + 550 .LCFI12: + 551 .cfi_def_cfa_offset 8 + 552 .cfi_offset 4, -8 + 553 .cfi_offset 14, -4 + 810:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 554 .loc 1 810 0 + 555 0002 0528 cmp r0, #5 + 556 0004 01D0 beq .L70 + 811:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 812:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_RX_PARAM_SETUP_REQ( ); + 813:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_RX_PARAM_SETUP_REQ( ); + 814:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_RX_PARAM_SETUP_REQ( ); + 815:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_RX_PARAM_SETUP_REQ( ); + 816:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_RX_PARAM_SETUP_REQ( ); + 817:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_RX_PARAM_SETUP_REQ( ); + 818:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_RX_PARAM_SETUP_REQ( ); + 819:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_RX_PARAM_SETUP_REQ( ); + 820:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_RX_PARAM_SETUP_REQ( ); + 821:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_RX_PARAM_SETUP_REQ( ); + 822:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 823:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 824:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 557 .loc 1 824 0 + ARM GAS /tmp/cciGOlRU.s page 25 + + + 558 0006 0020 movs r0, #0 + 559 .LVL72: + 560 .L66: + 825:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 826:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 827:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 561 .loc 1 827 0 + 562 @ sp needed + 563 0008 10BD pop {r4, pc} + 564 .LVL73: + 565 .L70: + 817:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_RX_PARAM_SETUP_REQ( ); + 566 .loc 1 817 0 + 567 000a 0800 movs r0, r1 + 568 .LVL74: + 569 000c FFF7FEFF bl RegionEU868RxParamSetupReq + 570 .LVL75: + 571 0010 FAE7 b .L66 + 572 .cfi_endproc + 573 .LFE94: + 575 .section .text.RegionNewChannelReq,"ax",%progbits + 576 .align 1 + 577 .global RegionNewChannelReq + 578 .syntax unified + 579 .code 16 + 580 .thumb_func + 581 .fpu softvfp + 583 RegionNewChannelReq: + 584 .LFB95: + 828:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 829:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** uint8_t RegionNewChannelReq( LoRaMacRegion_t region, NewChannelReqParams_t* newChannelReq ) + 830:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 585 .loc 1 830 0 + 586 .cfi_startproc + 587 @ args = 0, pretend = 0, frame = 0 + 588 @ frame_needed = 0, uses_anonymous_args = 0 + 589 .LVL76: + 590 0000 10B5 push {r4, lr} + 591 .LCFI13: + 592 .cfi_def_cfa_offset 8 + 593 .cfi_offset 4, -8 + 594 .cfi_offset 14, -4 + 831:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 595 .loc 1 831 0 + 596 0002 0528 cmp r0, #5 + 597 0004 01D0 beq .L76 + 832:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 833:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_NEW_CHANNEL_REQ( ); + 834:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_NEW_CHANNEL_REQ( ); + 835:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_NEW_CHANNEL_REQ( ); + 836:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_NEW_CHANNEL_REQ( ); + 837:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_NEW_CHANNEL_REQ( ); + 838:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_NEW_CHANNEL_REQ( ); + 839:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_NEW_CHANNEL_REQ( ); + 840:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_NEW_CHANNEL_REQ( ); + 841:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_NEW_CHANNEL_REQ( ); + 842:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_NEW_CHANNEL_REQ( ); + ARM GAS /tmp/cciGOlRU.s page 26 + + + 843:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 844:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 845:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 598 .loc 1 845 0 + 599 0006 0020 movs r0, #0 + 600 .LVL77: + 601 .L72: + 846:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 847:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 848:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 602 .loc 1 848 0 + 603 @ sp needed + 604 0008 10BD pop {r4, pc} + 605 .LVL78: + 606 .L76: + 838:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_NEW_CHANNEL_REQ( ); + 607 .loc 1 838 0 + 608 000a 0800 movs r0, r1 + 609 .LVL79: + 610 000c FFF7FEFF bl RegionEU868NewChannelReq + 611 .LVL80: + 612 0010 FAE7 b .L72 + 613 .cfi_endproc + 614 .LFE95: + 616 .section .text.RegionTxParamSetupReq,"ax",%progbits + 617 .align 1 + 618 .global RegionTxParamSetupReq + 619 .syntax unified + 620 .code 16 + 621 .thumb_func + 622 .fpu softvfp + 624 RegionTxParamSetupReq: + 625 .LFB96: + 849:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 850:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** int8_t RegionTxParamSetupReq( LoRaMacRegion_t region, TxParamSetupReqParams_t* txParamSetupReq ) + 851:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 626 .loc 1 851 0 + 627 .cfi_startproc + 628 @ args = 0, pretend = 0, frame = 0 + 629 @ frame_needed = 0, uses_anonymous_args = 0 + 630 .LVL81: + 631 0000 10B5 push {r4, lr} + 632 .LCFI14: + 633 .cfi_def_cfa_offset 8 + 634 .cfi_offset 4, -8 + 635 .cfi_offset 14, -4 + 852:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 636 .loc 1 852 0 + 637 0002 0528 cmp r0, #5 + 638 0004 01D0 beq .L82 + 853:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 854:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_TX_PARAM_SETUP_REQ( ); + 855:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_TX_PARAM_SETUP_REQ( ); + 856:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_TX_PARAM_SETUP_REQ( ); + 857:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_TX_PARAM_SETUP_REQ( ); + 858:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_TX_PARAM_SETUP_REQ( ); + 859:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_TX_PARAM_SETUP_REQ( ); + ARM GAS /tmp/cciGOlRU.s page 27 + + + 860:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_TX_PARAM_SETUP_REQ( ); + 861:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_TX_PARAM_SETUP_REQ( ); + 862:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_TX_PARAM_SETUP_REQ( ); + 863:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_TX_PARAM_SETUP_REQ( ); + 864:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 865:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 866:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 639 .loc 1 866 0 + 640 0006 0020 movs r0, #0 + 641 .LVL82: + 642 .L78: + 867:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 868:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 869:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 643 .loc 1 869 0 + 644 @ sp needed + 645 0008 10BD pop {r4, pc} + 646 .LVL83: + 647 .L82: + 859:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_TX_PARAM_SETUP_REQ( ); + 648 .loc 1 859 0 + 649 000a 0800 movs r0, r1 + 650 .LVL84: + 651 000c FFF7FEFF bl RegionEU868TxParamSetupReq + 652 .LVL85: + 653 0010 FAE7 b .L78 + 654 .cfi_endproc + 655 .LFE96: + 657 .section .text.RegionDlChannelReq,"ax",%progbits + 658 .align 1 + 659 .global RegionDlChannelReq + 660 .syntax unified + 661 .code 16 + 662 .thumb_func + 663 .fpu softvfp + 665 RegionDlChannelReq: + 666 .LFB97: + 870:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 871:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** uint8_t RegionDlChannelReq( LoRaMacRegion_t region, DlChannelReqParams_t* dlChannelReq ) + 872:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 667 .loc 1 872 0 + 668 .cfi_startproc + 669 @ args = 0, pretend = 0, frame = 0 + 670 @ frame_needed = 0, uses_anonymous_args = 0 + 671 .LVL86: + 672 0000 10B5 push {r4, lr} + 673 .LCFI15: + 674 .cfi_def_cfa_offset 8 + 675 .cfi_offset 4, -8 + 676 .cfi_offset 14, -4 + 873:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 677 .loc 1 873 0 + 678 0002 0528 cmp r0, #5 + 679 0004 01D0 beq .L88 + 874:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 875:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_DL_CHANNEL_REQ( ); + 876:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_DL_CHANNEL_REQ( ); + ARM GAS /tmp/cciGOlRU.s page 28 + + + 877:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_DL_CHANNEL_REQ( ); + 878:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_DL_CHANNEL_REQ( ); + 879:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_DL_CHANNEL_REQ( ); + 880:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_DL_CHANNEL_REQ( ); + 881:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_DL_CHANNEL_REQ( ); + 882:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_DL_CHANNEL_REQ( ); + 883:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_DL_CHANNEL_REQ( ); + 884:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_DL_CHANNEL_REQ( ); + 885:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 886:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 887:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 680 .loc 1 887 0 + 681 0006 0020 movs r0, #0 + 682 .LVL87: + 683 .L84: + 888:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 889:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 890:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 684 .loc 1 890 0 + 685 @ sp needed + 686 0008 10BD pop {r4, pc} + 687 .LVL88: + 688 .L88: + 880:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_DL_CHANNEL_REQ( ); + 689 .loc 1 880 0 + 690 000a 0800 movs r0, r1 + 691 .LVL89: + 692 000c FFF7FEFF bl RegionEU868DlChannelReq + 693 .LVL90: + 694 0010 FAE7 b .L84 + 695 .cfi_endproc + 696 .LFE97: + 698 .section .text.RegionAlternateDr,"ax",%progbits + 699 .align 1 + 700 .global RegionAlternateDr + 701 .syntax unified + 702 .code 16 + 703 .thumb_func + 704 .fpu softvfp + 706 RegionAlternateDr: + 707 .LFB98: + 891:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 892:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** int8_t RegionAlternateDr( LoRaMacRegion_t region, AlternateDrParams_t* alternateDr ) + 893:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 708 .loc 1 893 0 + 709 .cfi_startproc + 710 @ args = 0, pretend = 0, frame = 0 + 711 @ frame_needed = 0, uses_anonymous_args = 0 + 712 .LVL91: + 713 0000 10B5 push {r4, lr} + 714 .LCFI16: + 715 .cfi_def_cfa_offset 8 + 716 .cfi_offset 4, -8 + 717 .cfi_offset 14, -4 + 894:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 718 .loc 1 894 0 + 719 0002 0528 cmp r0, #5 + ARM GAS /tmp/cciGOlRU.s page 29 + + + 720 0004 01D0 beq .L94 + 895:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 896:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_ALTERNATE_DR( ); + 897:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_ALTERNATE_DR( ); + 898:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_ALTERNATE_DR( ); + 899:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_ALTERNATE_DR( ); + 900:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_ALTERNATE_DR( ); + 901:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_ALTERNATE_DR( ); + 902:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_ALTERNATE_DR( ); + 903:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_ALTERNATE_DR( ); + 904:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_ALTERNATE_DR( ); + 905:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_ALTERNATE_DR( ); + 906:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 907:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 908:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return 0; + 721 .loc 1 908 0 + 722 0006 0020 movs r0, #0 + 723 .LVL92: + 724 .L90: + 909:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 910:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 911:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 725 .loc 1 911 0 + 726 @ sp needed + 727 0008 10BD pop {r4, pc} + 728 .LVL93: + 729 .L94: + 901:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_ALTERNATE_DR( ); + 730 .loc 1 901 0 + 731 000a 0800 movs r0, r1 + 732 .LVL94: + 733 000c FFF7FEFF bl RegionEU868AlternateDr + 734 .LVL95: + 735 0010 FAE7 b .L90 + 736 .cfi_endproc + 737 .LFE98: + 739 .section .text.RegionCalcBackOff,"ax",%progbits + 740 .align 1 + 741 .global RegionCalcBackOff + 742 .syntax unified + 743 .code 16 + 744 .thumb_func + 745 .fpu softvfp + 747 RegionCalcBackOff: + 748 .LFB99: + 912:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 913:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionCalcBackOff( LoRaMacRegion_t region, CalcBackOffParams_t* calcBackOff ) + 914:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 749 .loc 1 914 0 + 750 .cfi_startproc + 751 @ args = 0, pretend = 0, frame = 0 + 752 @ frame_needed = 0, uses_anonymous_args = 0 + 753 .LVL96: + 754 0000 10B5 push {r4, lr} + 755 .LCFI17: + 756 .cfi_def_cfa_offset 8 + 757 .cfi_offset 4, -8 + ARM GAS /tmp/cciGOlRU.s page 30 + + + 758 .cfi_offset 14, -4 + 915:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 759 .loc 1 915 0 + 760 0002 0528 cmp r0, #5 + 761 0004 00D0 beq .L98 + 762 .LVL97: + 763 .L95: + 916:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 917:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_CALC_BACKOFF( ); + 918:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_CALC_BACKOFF( ); + 919:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_CALC_BACKOFF( ); + 920:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_CALC_BACKOFF( ); + 921:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_CALC_BACKOFF( ); + 922:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_CALC_BACKOFF( ); + 923:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CALC_BACKOFF( ); + 924:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_CALC_BACKOFF( ); + 925:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_CALC_BACKOFF( ); + 926:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_CALC_BACKOFF( ); + 927:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 928:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 929:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** break; + 930:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 931:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 932:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 764 .loc 1 932 0 + 765 @ sp needed + 766 0006 10BD pop {r4, pc} + 767 .LVL98: + 768 .L98: + 922:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CALC_BACKOFF( ); + 769 .loc 1 922 0 + 770 0008 0800 movs r0, r1 + 771 .LVL99: + 772 000a FFF7FEFF bl RegionEU868CalcBackOff + 773 .LVL100: + 774 .loc 1 932 0 + 775 000e FAE7 b .L95 + 776 .cfi_endproc + 777 .LFE99: + 779 .section .text.RegionNextChannel,"ax",%progbits + 780 .align 1 + 781 .global RegionNextChannel + 782 .syntax unified + 783 .code 16 + 784 .thumb_func + 785 .fpu softvfp + 787 RegionNextChannel: + 788 .LFB100: + 933:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 934:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionNextChannel( LoRaMacRegion_t region, NextChanParams_t* nextChanParams, uint8_t* channel, + 935:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 789 .loc 1 935 0 + 790 .cfi_startproc + 791 @ args = 4, pretend = 0, frame = 0 + 792 @ frame_needed = 0, uses_anonymous_args = 0 + 793 .LVL101: + 794 0000 10B5 push {r4, lr} + ARM GAS /tmp/cciGOlRU.s page 31 + + + 795 .LCFI18: + 796 .cfi_def_cfa_offset 8 + 797 .cfi_offset 4, -8 + 798 .cfi_offset 14, -4 + 799 0002 0C00 movs r4, r1 + 800 0004 1100 movs r1, r2 + 801 .LVL102: + 802 0006 1A00 movs r2, r3 + 803 .LVL103: + 936:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 804 .loc 1 936 0 + 805 0008 0528 cmp r0, #5 + 806 000a 01D0 beq .L104 + 937:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 938:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_NEXT_CHANNEL( ); + 939:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_NEXT_CHANNEL( ); + 940:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_NEXT_CHANNEL( ); + 941:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_NEXT_CHANNEL( ); + 942:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_NEXT_CHANNEL( ); + 943:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_NEXT_CHANNEL( ); + 944:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_NEXT_CHANNEL( ); + 945:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_NEXT_CHANNEL( ); + 946:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_NEXT_CHANNEL( ); + 947:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_NEXT_CHANNEL( ); + 948:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 949:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 950:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 807 .loc 1 950 0 + 808 000c 0020 movs r0, #0 + 809 .LVL104: + 810 .L100: + 951:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 952:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 953:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 811 .loc 1 953 0 + 812 @ sp needed + 813 .LVL105: + 814 000e 10BD pop {r4, pc} + 815 .LVL106: + 816 .L104: + 943:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_NEXT_CHANNEL( ); + 817 .loc 1 943 0 + 818 0010 029B ldr r3, [sp, #8] + 819 0012 2000 movs r0, r4 + 820 .LVL107: + 821 0014 FFF7FEFF bl RegionEU868NextChannel + 822 .LVL108: + 823 0018 F9E7 b .L100 + 824 .cfi_endproc + 825 .LFE100: + 827 .section .text.RegionChannelAdd,"ax",%progbits + 828 .align 1 + 829 .global RegionChannelAdd + 830 .syntax unified + 831 .code 16 + 832 .thumb_func + 833 .fpu softvfp + ARM GAS /tmp/cciGOlRU.s page 32 + + + 835 RegionChannelAdd: + 836 .LFB101: + 954:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 955:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** LoRaMacStatus_t RegionChannelAdd( LoRaMacRegion_t region, ChannelAddParams_t* channelAdd ) + 956:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 837 .loc 1 956 0 + 838 .cfi_startproc + 839 @ args = 0, pretend = 0, frame = 0 + 840 @ frame_needed = 0, uses_anonymous_args = 0 + 841 .LVL109: + 842 0000 10B5 push {r4, lr} + 843 .LCFI19: + 844 .cfi_def_cfa_offset 8 + 845 .cfi_offset 4, -8 + 846 .cfi_offset 14, -4 + 957:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 847 .loc 1 957 0 + 848 0002 0528 cmp r0, #5 + 849 0004 03D1 bne .L109 + 958:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 959:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_CHANNEL_ADD( ); + 960:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_CHANNEL_ADD( ); + 961:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_CHANNEL_ADD( ); + 962:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_CHANNEL_ADD( ); + 963:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_CHANNEL_ADD( ); + 964:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_CHANNEL_ADD( ); + 850 .loc 1 964 0 + 851 0006 0800 movs r0, r1 + 852 .LVL110: + 853 0008 FFF7FEFF bl RegionEU868ChannelAdd + 854 .LVL111: + 855 .L106: + 965:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CHANNEL_ADD( ); + 966:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_CHANNEL_ADD( ); + 967:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_CHANNEL_ADD( ); + 968:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_CHANNEL_ADD( ); + 969:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 970:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 971:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return LORAMAC_STATUS_PARAMETER_INVALID; + 972:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 973:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 974:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 856 .loc 1 974 0 + 857 @ sp needed + 858 000c 10BD pop {r4, pc} + 859 .LVL112: + 860 .L109: + 971:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 861 .loc 1 971 0 + 862 000e 0320 movs r0, #3 + 863 .LVL113: + 864 0010 FCE7 b .L106 + 865 .cfi_endproc + 866 .LFE101: + 868 .section .text.RegionChannelsRemove,"ax",%progbits + 869 .align 1 + 870 .global RegionChannelsRemove + ARM GAS /tmp/cciGOlRU.s page 33 + + + 871 .syntax unified + 872 .code 16 + 873 .thumb_func + 874 .fpu softvfp + 876 RegionChannelsRemove: + 877 .LFB102: + 975:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 976:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** bool RegionChannelsRemove( LoRaMacRegion_t region, ChannelRemoveParams_t* channelRemove ) + 977:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 878 .loc 1 977 0 + 879 .cfi_startproc + 880 @ args = 0, pretend = 0, frame = 0 + 881 @ frame_needed = 0, uses_anonymous_args = 0 + 882 .LVL114: + 883 0000 10B5 push {r4, lr} + 884 .LCFI20: + 885 .cfi_def_cfa_offset 8 + 886 .cfi_offset 4, -8 + 887 .cfi_offset 14, -4 + 978:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 888 .loc 1 978 0 + 889 0002 0528 cmp r0, #5 + 890 0004 01D0 beq .L115 + 979:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 980:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_CHANNEL_REMOVE( ); + 981:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_CHANNEL_REMOVE( ); + 982:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_CHANNEL_REMOVE( ); + 983:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_CHANNEL_REMOVE( ); + 984:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_CHANNEL_REMOVE( ); + 985:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_CHANNEL_REMOVE( ); + 986:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CHANNEL_REMOVE( ); + 987:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_CHANNEL_REMOVE( ); + 988:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_CHANNEL_REMOVE( ); + 989:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_CHANNEL_REMOVE( ); + 990:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: + 991:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 992:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return false; + 891 .loc 1 992 0 + 892 0006 0020 movs r0, #0 + 893 .LVL115: + 894 .L111: + 993:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 994:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 995:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 895 .loc 1 995 0 + 896 @ sp needed + 897 0008 10BD pop {r4, pc} + 898 .LVL116: + 899 .L115: + 985:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_CHANNEL_REMOVE( ); + 900 .loc 1 985 0 + 901 000a 0800 movs r0, r1 + 902 .LVL117: + 903 000c FFF7FEFF bl RegionEU868ChannelsRemove + 904 .LVL118: + 905 0010 FAE7 b .L111 + 906 .cfi_endproc + ARM GAS /tmp/cciGOlRU.s page 34 + + + 907 .LFE102: + 909 .section .text.RegionSetContinuousWave,"ax",%progbits + 910 .align 1 + 911 .global RegionSetContinuousWave + 912 .syntax unified + 913 .code 16 + 914 .thumb_func + 915 .fpu softvfp + 917 RegionSetContinuousWave: + 918 .LFB103: + 996:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** + 997:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** void RegionSetContinuousWave( LoRaMacRegion_t region, ContinuousWaveParams_t* continuousWave ) + 998:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 919 .loc 1 998 0 + 920 .cfi_startproc + 921 @ args = 0, pretend = 0, frame = 0 + 922 @ frame_needed = 0, uses_anonymous_args = 0 + 923 .LVL119: + 924 0000 10B5 push {r4, lr} + 925 .LCFI21: + 926 .cfi_def_cfa_offset 8 + 927 .cfi_offset 4, -8 + 928 .cfi_offset 14, -4 + 999:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 929 .loc 1 999 0 + 930 0002 0528 cmp r0, #5 + 931 0004 00D0 beq .L119 + 932 .LVL120: + 933 .L116: +1000:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { +1001:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_SET_CONTINUOUS_WAVE( ); +1002:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_SET_CONTINUOUS_WAVE( ); +1003:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_SET_CONTINUOUS_WAVE( ); +1004:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_SET_CONTINUOUS_WAVE( ); +1005:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_SET_CONTINUOUS_WAVE( ); +1006:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_SET_CONTINUOUS_WAVE( ); +1007:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_SET_CONTINUOUS_WAVE( ); +1008:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_SET_CONTINUOUS_WAVE( ); +1009:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_SET_CONTINUOUS_WAVE( ); +1010:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_SET_CONTINUOUS_WAVE( ); +1011:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: +1012:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { +1013:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** break; +1014:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } +1015:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } +1016:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 934 .loc 1 1016 0 + 935 @ sp needed + 936 0006 10BD pop {r4, pc} + 937 .LVL121: + 938 .L119: +1006:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_SET_CONTINUOUS_WAVE( ); + 939 .loc 1 1006 0 + 940 0008 0800 movs r0, r1 + 941 .LVL122: + 942 000a FFF7FEFF bl RegionEU868SetContinuousWave + 943 .LVL123: + ARM GAS /tmp/cciGOlRU.s page 35 + + + 944 .loc 1 1016 0 + 945 000e FAE7 b .L116 + 946 .cfi_endproc + 947 .LFE103: + 949 .section .text.RegionApplyDrOffset,"ax",%progbits + 950 .align 1 + 951 .global RegionApplyDrOffset + 952 .syntax unified + 953 .code 16 + 954 .thumb_func + 955 .fpu softvfp + 957 RegionApplyDrOffset: + 958 .LFB104: +1017:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** +1018:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** uint8_t RegionApplyDrOffset( LoRaMacRegion_t region, uint8_t downlinkDwellTime, int8_t dr, int8_t d +1019:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { + 959 .loc 1 1019 0 + 960 .cfi_startproc + 961 @ args = 0, pretend = 0, frame = 0 + 962 @ frame_needed = 0, uses_anonymous_args = 0 + 963 .LVL124: + 964 0000 10B5 push {r4, lr} + 965 .LCFI22: + 966 .cfi_def_cfa_offset 8 + 967 .cfi_offset 4, -8 + 968 .cfi_offset 14, -4 + 969 0002 0C00 movs r4, r1 + 970 0004 1100 movs r1, r2 + 971 .LVL125: +1020:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** switch( region ) + 972 .loc 1 1020 0 + 973 0006 0528 cmp r0, #5 + 974 0008 01D0 beq .L125 +1021:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { +1022:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AS923_APPLY_DR_OFFSET( ); +1023:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** AU915_APPLY_DR_OFFSET( ); +1024:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN470_APPLY_DR_OFFSET( ); +1025:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** CN779_APPLY_DR_OFFSET( ); +1026:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU433_APPLY_DR_OFFSET( ); +1027:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** EU868_APPLY_DR_OFFSET( ); +1028:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_APPLY_DR_OFFSET( ); +1029:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** IN865_APPLY_DR_OFFSET( ); +1030:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_APPLY_DR_OFFSET( ); +1031:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** US915_HYBRID_APPLY_DR_OFFSET( ); +1032:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** default: +1033:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** { +1034:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** return dr; + 975 .loc 1 1034 0 + 976 000a D0B2 uxtb r0, r2 + 977 .LVL126: + 978 .L123: +1035:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } +1036:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } +1037:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** } + 979 .loc 1 1037 0 + 980 @ sp needed + 981 000c 10BD pop {r4, pc} + ARM GAS /tmp/cciGOlRU.s page 36 + + + 982 .LVL127: + 983 .L125: +1027:./Middlewares/Third_Party/Lora/Mac/region/Region.c **** KR920_APPLY_DR_OFFSET( ); + 984 .loc 1 1027 0 + 985 000e 1A00 movs r2, r3 + 986 .LVL128: + 987 0010 2000 movs r0, r4 + 988 .LVL129: + 989 0012 FFF7FEFF bl RegionEU868ApplyDrOffset + 990 .LVL130: + 991 0016 F9E7 b .L123 + 992 .cfi_endproc + 993 .LFE104: + 995 .text + 996 .Letext0: + 997 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 998 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 999 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 1000 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1001 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 1002 .file 7 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1003 .file 8 "/usr/arm-none-eabi/include/math.h" + 1004 .file 9 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 1005 .file 10 "Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 1006 .file 11 "./Middlewares/Third_Party/Lora/Mac/region/Region.h" + 1007 .file 12 "./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h" + ARM GAS /tmp/cciGOlRU.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 Region.c + /tmp/cciGOlRU.s:16 .text.RegionIsActive:0000000000000000 $t + /tmp/cciGOlRU.s:23 .text.RegionIsActive:0000000000000000 RegionIsActive + /tmp/cciGOlRU.s:52 .text.RegionGetPhyParam:0000000000000000 $t + /tmp/cciGOlRU.s:59 .text.RegionGetPhyParam:0000000000000000 RegionGetPhyParam + /tmp/cciGOlRU.s:93 .text.RegionSetBandTxDone:0000000000000000 $t + /tmp/cciGOlRU.s:100 .text.RegionSetBandTxDone:0000000000000000 RegionSetBandTxDone + /tmp/cciGOlRU.s:132 .text.RegionInitDefaults:0000000000000000 $t + /tmp/cciGOlRU.s:139 .text.RegionInitDefaults:0000000000000000 RegionInitDefaults + /tmp/cciGOlRU.s:172 .text.RegionVerify:0000000000000000 $t + /tmp/cciGOlRU.s:179 .text.RegionVerify:0000000000000000 RegionVerify + /tmp/cciGOlRU.s:216 .text.RegionApplyCFList:0000000000000000 $t + /tmp/cciGOlRU.s:223 .text.RegionApplyCFList:0000000000000000 RegionApplyCFList + /tmp/cciGOlRU.s:256 .text.RegionChanMaskSet:0000000000000000 $t + /tmp/cciGOlRU.s:263 .text.RegionChanMaskSet:0000000000000000 RegionChanMaskSet + /tmp/cciGOlRU.s:297 .text.RegionAdrNext:0000000000000000 $t + /tmp/cciGOlRU.s:304 .text.RegionAdrNext:0000000000000000 RegionAdrNext + /tmp/cciGOlRU.s:345 .text.RegionComputeRxWindowParameters:0000000000000000 $t + /tmp/cciGOlRU.s:352 .text.RegionComputeRxWindowParameters:0000000000000000 RegionComputeRxWindowParameters + /tmp/cciGOlRU.s:391 .text.RegionRxConfig:0000000000000000 $t + /tmp/cciGOlRU.s:398 .text.RegionRxConfig:0000000000000000 RegionRxConfig + /tmp/cciGOlRU.s:435 .text.RegionTxConfig:0000000000000000 $t + /tmp/cciGOlRU.s:442 .text.RegionTxConfig:0000000000000000 RegionTxConfig + /tmp/cciGOlRU.s:481 .text.RegionLinkAdrReq:0000000000000000 $t + /tmp/cciGOlRU.s:488 .text.RegionLinkAdrReq:0000000000000000 RegionLinkAdrReq + /tmp/cciGOlRU.s:535 .text.RegionRxParamSetupReq:0000000000000000 $t + /tmp/cciGOlRU.s:542 .text.RegionRxParamSetupReq:0000000000000000 RegionRxParamSetupReq + /tmp/cciGOlRU.s:576 .text.RegionNewChannelReq:0000000000000000 $t + /tmp/cciGOlRU.s:583 .text.RegionNewChannelReq:0000000000000000 RegionNewChannelReq + /tmp/cciGOlRU.s:617 .text.RegionTxParamSetupReq:0000000000000000 $t + /tmp/cciGOlRU.s:624 .text.RegionTxParamSetupReq:0000000000000000 RegionTxParamSetupReq + /tmp/cciGOlRU.s:658 .text.RegionDlChannelReq:0000000000000000 $t + /tmp/cciGOlRU.s:665 .text.RegionDlChannelReq:0000000000000000 RegionDlChannelReq + /tmp/cciGOlRU.s:699 .text.RegionAlternateDr:0000000000000000 $t + /tmp/cciGOlRU.s:706 .text.RegionAlternateDr:0000000000000000 RegionAlternateDr + /tmp/cciGOlRU.s:740 .text.RegionCalcBackOff:0000000000000000 $t + /tmp/cciGOlRU.s:747 .text.RegionCalcBackOff:0000000000000000 RegionCalcBackOff + /tmp/cciGOlRU.s:780 .text.RegionNextChannel:0000000000000000 $t + /tmp/cciGOlRU.s:787 .text.RegionNextChannel:0000000000000000 RegionNextChannel + /tmp/cciGOlRU.s:828 .text.RegionChannelAdd:0000000000000000 $t + /tmp/cciGOlRU.s:835 .text.RegionChannelAdd:0000000000000000 RegionChannelAdd + /tmp/cciGOlRU.s:869 .text.RegionChannelsRemove:0000000000000000 $t + /tmp/cciGOlRU.s:876 .text.RegionChannelsRemove:0000000000000000 RegionChannelsRemove + /tmp/cciGOlRU.s:910 .text.RegionSetContinuousWave:0000000000000000 $t + /tmp/cciGOlRU.s:917 .text.RegionSetContinuousWave:0000000000000000 RegionSetContinuousWave + /tmp/cciGOlRU.s:950 .text.RegionApplyDrOffset:0000000000000000 $t + /tmp/cciGOlRU.s:957 .text.RegionApplyDrOffset:0000000000000000 RegionApplyDrOffset + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +RegionEU868GetPhyParam +RegionEU868SetBandTxDone +RegionEU868InitDefaults +RegionEU868Verify +RegionEU868ApplyCFList +RegionEU868ChanMaskSet + ARM GAS /tmp/cciGOlRU.s page 38 + + +RegionEU868AdrNext +RegionEU868ComputeRxWindowParameters +RegionEU868RxConfig +RegionEU868TxConfig +RegionEU868LinkAdrReq +RegionEU868RxParamSetupReq +RegionEU868NewChannelReq +RegionEU868TxParamSetupReq +RegionEU868DlChannelReq +RegionEU868AlternateDr +RegionEU868CalcBackOff +RegionEU868NextChannel +RegionEU868ChannelAdd +RegionEU868ChannelsRemove +RegionEU868SetContinuousWave +RegionEU868ApplyDrOffset diff --git a/build/RegionCommon.d b/build/RegionCommon.d new file mode 100644 index 0000000..2d7645a --- /dev/null +++ b/build/RegionCommon.d @@ -0,0 +1,35 @@ +build/RegionCommon.d: \ + Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c \ + Middlewares/Third_Party/Lora/Mac/timer.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h + +Middlewares/Third_Party/Lora/Mac/timer.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h: diff --git a/build/RegionCommon.lst b/build/RegionCommon.lst new file mode 100644 index 0000000..f1119a8 --- /dev/null +++ b/build/RegionCommon.lst @@ -0,0 +1,1997 @@ +ARM GAS /tmp/ccAkEbCV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "RegionCommon.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.RegionCommonGetJoinDc,"ax",%progbits + 16 .align 1 + 17 .global RegionCommonGetJoinDc + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 RegionCommonGetJoinDc: + 24 .LFB83: + 25 .file 1 "./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c" + 1:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** /* + 2:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ___ _____ _ ___ _ _____ ___ ___ ___ ___ + 9:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + 10:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + 11:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + 12:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** embedded.connectivity.solutions=============== + 13:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 14:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** Description: LoRa MAC common region implementation + 15:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 16:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 17:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 18:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) + 19:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** */ + 20:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 21:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include + 22:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include + 23:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include + 24:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include + 25:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 26:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include "timer.h" + 27:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include "utilities.h" + 28:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include "LoRaMac.h" + 29:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #include "RegionCommon.h" + 30:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 31:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 32:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 33:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #define BACKOFF_DC_1_HOUR 100 + ARM GAS /tmp/ccAkEbCV.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #define BACKOFF_DC_10_HOURS 1000 + 35:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** #define BACKOFF_DC_24_HOURS 10000 + 36:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 37:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 38:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 39:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** static uint8_t CountChannels( uint16_t mask, uint8_t nbBits ) + 40:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 41:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t nbActiveBits = 0; + 42:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 43:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t j = 0; j < nbBits; j++ ) + 44:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 45:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( mask & ( 1 << j ) ) == ( 1 << j ) ) + 46:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 47:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nbActiveBits++; + 48:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 49:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 50:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return nbActiveBits; + 51:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 52:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 53:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 54:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 55:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint16_t RegionCommonGetJoinDc( TimerTime_t elapsedTime ) + 56:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 26 .loc 1 56 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 57:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint16_t dutyCycle = 0; + 58:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 59:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( elapsedTime < 3600000 ) + 32 .loc 1 59 0 + 33 0000 064B ldr r3, .L6 + 34 0002 9842 cmp r0, r3 + 35 0004 07D9 bls .L3 + 60:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 61:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** dutyCycle = BACKOFF_DC_1_HOUR; + 62:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 63:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else if( elapsedTime < ( 3600000 + 36000000 ) ) + 36 .loc 1 63 0 + 37 0006 064B ldr r3, .L6+4 + 38 0008 9842 cmp r0, r3 + 39 000a 01D9 bls .L5 + 64:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 65:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** dutyCycle = BACKOFF_DC_10_HOURS; + 66:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 67:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 68:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 69:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** dutyCycle = BACKOFF_DC_24_HOURS; + 40 .loc 1 69 0 + 41 000c 0548 ldr r0, .L6+8 + 42 .LVL1: + 43 000e 03E0 b .L2 + 44 .LVL2: + 45 .L5: + 65:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + ARM GAS /tmp/ccAkEbCV.s page 3 + + + 46 .loc 1 65 0 + 47 0010 FA20 movs r0, #250 + 48 .LVL3: + 49 0012 8000 lsls r0, r0, #2 + 50 0014 00E0 b .L2 + 51 .LVL4: + 52 .L3: + 61:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 53 .loc 1 61 0 + 54 0016 6420 movs r0, #100 + 55 .LVL5: + 56 .L2: + 70:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 71:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return dutyCycle; + 72:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 57 .loc 1 72 0 + 58 @ sp needed + 59 0018 7047 bx lr + 60 .L7: + 61 001a C046 .align 2 + 62 .L6: + 63 001c 7FEE3600 .word 3599999 + 64 0020 7F3F5C02 .word 39599999 + 65 0024 10270000 .word 10000 + 66 .cfi_endproc + 67 .LFE83: + 69 .section .text.RegionCommonChanVerifyDr,"ax",%progbits + 70 .align 1 + 71 .global RegionCommonChanVerifyDr + 72 .syntax unified + 73 .code 16 + 74 .thumb_func + 75 .fpu softvfp + 77 RegionCommonChanVerifyDr: + 78 .LFB84: + 73:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 74:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bool RegionCommonChanVerifyDr( uint8_t nbChannels, uint16_t* channelsMask, int8_t dr, int8_t minDr, + 75:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 79 .loc 1 75 0 + 80 .cfi_startproc + 81 @ args = 8, pretend = 0, frame = 0 + 82 @ frame_needed = 0, uses_anonymous_args = 0 + 83 .LVL6: + 84 0000 F0B5 push {r4, r5, r6, r7, lr} + 85 .LCFI0: + 86 .cfi_def_cfa_offset 20 + 87 .cfi_offset 4, -20 + 88 .cfi_offset 5, -16 + 89 .cfi_offset 6, -12 + 90 .cfi_offset 7, -8 + 91 .cfi_offset 14, -4 + 92 0002 CE46 mov lr, r9 + 93 0004 4746 mov r7, r8 + 94 0006 80B5 push {r7, lr} + 95 .LCFI1: + 96 .cfi_def_cfa_offset 28 + 97 .cfi_offset 8, -28 + ARM GAS /tmp/ccAkEbCV.s page 4 + + + 98 .cfi_offset 9, -24 + 99 0008 8046 mov r8, r0 + 100 000a 07AC add r4, sp, #28 + 101 .LVL7: + 102 000c 2478 ldrb r4, [r4] + 103 .LVL8: + 104 000e 64B2 sxtb r4, r4 + 105 0010 0898 ldr r0, [sp, #32] + 106 .LVL9: + 107 0012 8146 mov r9, r0 + 108 .LVL10: + 109 .LBB16: + 110 .LBB17: + 76:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( RegionCommonValueInRange( dr, minDr, maxDr ) == 0 ) + 77:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 78:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return false; + 79:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 80:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 81:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t i = 0, k = 0; i < nbChannels; i += 16, k++ ) + 82:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 83:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t j = 0; j < 16; j++ ) + 84:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 85:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( ( channelsMask[k] & ( 1 << j ) ) != 0 ) ) + 86:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** {// Check datarate validity for enabled channels + 87:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( RegionCommonValueInRange( dr, ( channels[i + j].DrRange.Fields.Min & 0x0F ), + 88:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( channels[i + j].DrRange.Fields.Max & 0x0F ) ) = + 89:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 90:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // At least 1 channel has been found we can return OK. + 91:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return true; + 92:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 93:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 94:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 95:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 96:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return false; + 97:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 98:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 99:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t RegionCommonValueInRange( int8_t value, int8_t min, int8_t max ) + 100:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 101:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( value >= min ) && ( value <= max ) ) + 111 .loc 1 101 0 + 112 0014 9A42 cmp r2, r3 + 113 0016 2DDB blt .L14 + 114 0018 A242 cmp r2, r4 + 115 001a 02DC bgt .L18 + 116 .LBE17: + 117 .LBE16: + 118 .LBB18: + 81:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 119 .loc 1 81 0 + 120 001c 0025 movs r5, #0 + 121 001e 0026 movs r6, #0 + 122 0020 22E0 b .L10 + 123 .L18: + 124 .LBE18: + 78:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 125 .loc 1 78 0 + 126 0022 0020 movs r0, #0 + ARM GAS /tmp/ccAkEbCV.s page 5 + + + 127 0024 27E0 b .L9 + 128 .LVL11: + 129 .L11: + 130 .LBB23: + 131 .LBB19: + 83:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 132 .loc 1 83 0 discriminator 2 + 133 0026 0133 adds r3, r3, #1 + 134 .LVL12: + 135 0028 DBB2 uxtb r3, r3 + 136 .LVL13: + 137 .L13: + 83:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 138 .loc 1 83 0 is_stmt 0 discriminator 1 + 139 002a 0F2B cmp r3, #15 + 140 002c 18D8 bhi .L19 + 85:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** {// Check datarate validity for enabled channels + 141 .loc 1 85 0 is_stmt 1 + 142 002e 6C00 lsls r4, r5, #1 + 143 0030 645A ldrh r4, [r4, r1] + 144 0032 1C41 asrs r4, r4, r3 + 145 0034 E007 lsls r0, r4, #31 + 146 0036 F6D5 bpl .L11 + 87:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( channels[i + j].DrRange.Fields.Max & 0x0F ) ) = + 147 .loc 1 87 0 + 148 0038 F018 adds r0, r6, r3 + 149 003a 4400 lsls r4, r0, #1 + 150 003c 2018 adds r0, r4, r0 + 151 003e 8400 lsls r4, r0, #2 + 152 0040 4C44 add r4, r4, r9 + 153 0042 277A ldrb r7, [r4, #8] + 154 0044 3C01 lsls r4, r7, #4 + 155 0046 64B2 sxtb r4, r4 + 156 0048 2411 asrs r4, r4, #4 + 157 004a 0F20 movs r0, #15 + 158 004c 0440 ands r4, r0 + 88:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 159 .loc 1 88 0 + 160 004e 7FB2 sxtb r7, r7 + 161 0050 3F11 asrs r7, r7, #4 + 87:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( channels[i + j].DrRange.Fields.Max & 0x0F ) ) = + 162 .loc 1 87 0 + 163 0052 0740 ands r7, r0 + 164 .LVL14: + 165 .LBB20: + 166 .LBB21: + 167 .loc 1 101 0 + 168 0054 9442 cmp r4, r2 + 169 0056 E6DC bgt .L11 + 170 0058 9742 cmp r7, r2 + 171 005a E4DB blt .L11 + 172 .LBE21: + 173 .LBE20: + 91:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 174 .loc 1 91 0 + 175 005c 0120 movs r0, #1 + 176 005e 0AE0 b .L9 + ARM GAS /tmp/ccAkEbCV.s page 6 + + + 177 .LVL15: + 178 .L19: + 179 .LBE19: + 81:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 180 .loc 1 81 0 discriminator 2 + 181 0060 1036 adds r6, r6, #16 + 182 .LVL16: + 183 0062 F6B2 uxtb r6, r6 + 184 .LVL17: + 185 0064 0135 adds r5, r5, #1 + 186 .LVL18: + 187 0066 EDB2 uxtb r5, r5 + 188 .LVL19: + 189 .L10: + 81:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 190 .loc 1 81 0 is_stmt 0 discriminator 1 + 191 0068 4645 cmp r6, r8 + 192 006a 01D2 bcs .L20 + 193 .LBB22: + 83:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 194 .loc 1 83 0 is_stmt 1 + 195 006c 0023 movs r3, #0 + 196 006e DCE7 b .L13 + 197 .L20: + 198 .LBE22: + 199 .LBE23: + 96:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 200 .loc 1 96 0 + 201 0070 0020 movs r0, #0 + 202 .LBB24: + 203 0072 00E0 b .L9 + 204 .LVL20: + 205 .L14: + 206 .LBE24: + 78:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 207 .loc 1 78 0 + 208 0074 0020 movs r0, #0 + 209 .LVL21: + 210 .L9: + 97:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 211 .loc 1 97 0 + 212 @ sp needed + 213 0076 0CBC pop {r2, r3} + 214 0078 9046 mov r8, r2 + 215 007a 9946 mov r9, r3 + 216 007c F0BD pop {r4, r5, r6, r7, pc} + 217 .cfi_endproc + 218 .LFE84: + 220 .section .text.RegionCommonValueInRange,"ax",%progbits + 221 .align 1 + 222 .global RegionCommonValueInRange + 223 .syntax unified + 224 .code 16 + 225 .thumb_func + 226 .fpu softvfp + 228 RegionCommonValueInRange: + 229 .LFB85: + ARM GAS /tmp/ccAkEbCV.s page 7 + + + 100:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( value >= min ) && ( value <= max ) ) + 230 .loc 1 100 0 + 231 .cfi_startproc + 232 @ args = 0, pretend = 0, frame = 0 + 233 @ frame_needed = 0, uses_anonymous_args = 0 + 234 @ link register save eliminated. + 235 .LVL22: + 236 .loc 1 101 0 + 237 0000 8842 cmp r0, r1 + 238 0002 03DB blt .L23 + 239 .loc 1 101 0 is_stmt 0 discriminator 1 + 240 0004 9042 cmp r0, r2 + 241 0006 03DD ble .L24 + 102:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 103:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return 1; + 104:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 105:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return 0; + 242 .loc 1 105 0 is_stmt 1 + 243 0008 0020 movs r0, #0 + 244 .LVL23: + 245 000a 00E0 b .L22 + 246 .LVL24: + 247 .L23: + 248 000c 0020 movs r0, #0 + 249 .LVL25: + 250 .L22: + 106:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 251 .loc 1 106 0 + 252 @ sp needed + 253 000e 7047 bx lr + 254 .LVL26: + 255 .L24: + 103:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 256 .loc 1 103 0 + 257 0010 0120 movs r0, #1 + 258 .LVL27: + 259 0012 FCE7 b .L22 + 260 .cfi_endproc + 261 .LFE85: + 263 .section .text.RegionCommonChanDisable,"ax",%progbits + 264 .align 1 + 265 .global RegionCommonChanDisable + 266 .syntax unified + 267 .code 16 + 268 .thumb_func + 269 .fpu softvfp + 271 RegionCommonChanDisable: + 272 .LFB86: + 107:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 108:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bool RegionCommonChanDisable( uint16_t* channelsMask, uint8_t id, uint8_t maxChannels ) + 109:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 273 .loc 1 109 0 + 274 .cfi_startproc + 275 @ args = 0, pretend = 0, frame = 0 + 276 @ frame_needed = 0, uses_anonymous_args = 0 + 277 .LVL28: + 278 0000 10B5 push {r4, lr} + ARM GAS /tmp/ccAkEbCV.s page 8 + + + 279 .LCFI2: + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 4, -8 + 282 .cfi_offset 14, -4 + 110:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t index = id / 16; + 283 .loc 1 110 0 + 284 0002 0B09 lsrs r3, r1, #4 + 285 .LVL29: + 111:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 112:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( index > ( maxChannels / 16 ) ) || ( id >= maxChannels ) ) + 286 .loc 1 112 0 + 287 0004 1409 lsrs r4, r2, #4 + 288 0006 9C42 cmp r4, r3 + 289 0008 0CD3 bcc .L27 + 290 .loc 1 112 0 is_stmt 0 discriminator 1 + 291 000a 9142 cmp r1, r2 + 292 000c 0CD2 bcs .L28 + 113:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 114:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return false; + 115:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 116:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 117:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Deactivate channel + 118:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** channelsMask[index] &= ~( 1 << ( id % 16 ) ); + 293 .loc 1 118 0 is_stmt 1 + 294 000e 5B00 lsls r3, r3, #1 + 295 .LVL30: + 296 0010 C318 adds r3, r0, r3 + 297 0012 0F22 movs r2, #15 + 298 .LVL31: + 299 0014 0A40 ands r2, r1 + 300 0016 0121 movs r1, #1 + 301 .LVL32: + 302 0018 9140 lsls r1, r1, r2 + 303 001a 1A88 ldrh r2, [r3] + 304 001c 8A43 bics r2, r1 + 305 001e 1A80 strh r2, [r3] + 119:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 120:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return true; + 306 .loc 1 120 0 + 307 0020 0120 movs r0, #1 + 308 .LVL33: + 309 0022 00E0 b .L26 + 310 .LVL34: + 311 .L27: + 114:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 312 .loc 1 114 0 + 313 0024 0020 movs r0, #0 + 314 .LVL35: + 315 .L26: + 121:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 316 .loc 1 121 0 + 317 @ sp needed + 318 0026 10BD pop {r4, pc} + 319 .LVL36: + 320 .L28: + 114:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 321 .loc 1 114 0 + ARM GAS /tmp/ccAkEbCV.s page 9 + + + 322 0028 0020 movs r0, #0 + 323 .LVL37: + 324 002a FCE7 b .L26 + 325 .cfi_endproc + 326 .LFE86: + 328 .section .text.RegionCommonCountChannels,"ax",%progbits + 329 .align 1 + 330 .global RegionCommonCountChannels + 331 .syntax unified + 332 .code 16 + 333 .thumb_func + 334 .fpu softvfp + 336 RegionCommonCountChannels: + 337 .LFB87: + 122:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 123:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t RegionCommonCountChannels( uint16_t* channelsMask, uint8_t startIdx, uint8_t stopIdx ) + 124:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 338 .loc 1 124 0 + 339 .cfi_startproc + 340 @ args = 0, pretend = 0, frame = 0 + 341 @ frame_needed = 0, uses_anonymous_args = 0 + 342 .LVL38: + 343 0000 F0B5 push {r4, r5, r6, r7, lr} + 344 .LCFI3: + 345 .cfi_def_cfa_offset 20 + 346 .cfi_offset 4, -20 + 347 .cfi_offset 5, -16 + 348 .cfi_offset 6, -12 + 349 .cfi_offset 7, -8 + 350 .cfi_offset 14, -4 + 351 0002 9446 mov ip, r2 + 352 .LVL39: + 125:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t nbChannels = 0; + 126:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 127:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( channelsMask == NULL ) + 353 .loc 1 127 0 + 354 0004 0028 cmp r0, #0 + 355 0006 19D0 beq .L36 + 125:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t nbChannels = 0; + 356 .loc 1 125 0 + 357 0008 0022 movs r2, #0 + 358 .LVL40: + 359 000a 10E0 b .L31 + 360 .LVL41: + 361 .L33: + 362 .LBB25: + 363 .LBB26: + 364 .LBB27: + 365 .LBB28: + 43:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 366 .loc 1 43 0 + 367 000c 0133 adds r3, r3, #1 + 368 .LVL42: + 369 000e DBB2 uxtb r3, r3 + 370 .LVL43: + 371 .L32: + 372 0010 0F2B cmp r3, #15 + ARM GAS /tmp/ccAkEbCV.s page 10 + + + 373 0012 08D8 bhi .L37 + 45:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 374 .loc 1 45 0 + 375 0014 0124 movs r4, #1 + 376 0016 9C40 lsls r4, r4, r3 + 377 0018 2500 movs r5, r4 + 378 001a 3D40 ands r5, r7 + 379 001c AC42 cmp r4, r5 + 380 001e F5D1 bne .L33 + 47:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 381 .loc 1 47 0 + 382 0020 0136 adds r6, r6, #1 + 383 .LVL44: + 384 0022 F6B2 uxtb r6, r6 + 385 .LVL45: + 386 0024 F2E7 b .L33 + 387 .L37: + 388 .LVL46: + 389 .LBE28: + 390 .LBE27: + 391 .LBE26: + 128:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 129:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return 0; + 130:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 131:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 132:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t i = startIdx; i < stopIdx; i++ ) + 133:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 134:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nbChannels += CountChannels( channelsMask[i], 16 ); + 392 .loc 1 134 0 + 393 0026 9219 adds r2, r2, r6 + 394 .LVL47: + 395 0028 D2B2 uxtb r2, r2 + 396 .LVL48: + 132:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 397 .loc 1 132 0 + 398 002a 0131 adds r1, r1, #1 + 399 .LVL49: + 400 002c C9B2 uxtb r1, r1 + 401 .LVL50: + 402 .L31: + 132:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 403 .loc 1 132 0 is_stmt 0 discriminator 1 + 404 002e 6145 cmp r1, ip + 405 0030 05D2 bcs .L30 + 406 .loc 1 134 0 is_stmt 1 discriminator 3 + 407 0032 4B00 lsls r3, r1, #1 + 408 0034 C75A ldrh r7, [r0, r3] + 409 .LVL51: + 410 .LBB31: + 411 .LBB30: + 412 .LBB29: + 43:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 413 .loc 1 43 0 discriminator 3 + 414 0036 0023 movs r3, #0 + 415 .LBE29: + 41:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 416 .loc 1 41 0 discriminator 3 + ARM GAS /tmp/ccAkEbCV.s page 11 + + + 417 0038 0026 movs r6, #0 + 418 003a E9E7 b .L32 + 419 .LVL52: + 420 .L36: + 421 .LBE30: + 422 .LBE31: + 423 .LBE25: + 129:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 424 .loc 1 129 0 + 425 003c 0022 movs r2, #0 + 426 .LVL53: + 427 .L30: + 135:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 136:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 137:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return nbChannels; + 138:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 428 .loc 1 138 0 + 429 003e 1000 movs r0, r2 + 430 .LVL54: + 431 @ sp needed + 432 0040 F0BD pop {r4, r5, r6, r7, pc} + 433 .cfi_endproc + 434 .LFE87: + 436 .section .text.RegionCommonChanMaskCopy,"ax",%progbits + 437 .align 1 + 438 .global RegionCommonChanMaskCopy + 439 .syntax unified + 440 .code 16 + 441 .thumb_func + 442 .fpu softvfp + 444 RegionCommonChanMaskCopy: + 445 .LFB88: + 139:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 140:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** void RegionCommonChanMaskCopy( uint16_t* channelsMaskDest, uint16_t* channelsMaskSrc, uint8_t len ) + 141:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 446 .loc 1 141 0 + 447 .cfi_startproc + 448 @ args = 0, pretend = 0, frame = 0 + 449 @ frame_needed = 0, uses_anonymous_args = 0 + 450 .LVL55: + 451 0000 30B5 push {r4, r5, lr} + 452 .LCFI4: + 453 .cfi_def_cfa_offset 12 + 454 .cfi_offset 4, -12 + 455 .cfi_offset 5, -8 + 456 .cfi_offset 14, -4 + 142:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( channelsMaskDest != NULL ) && ( channelsMaskSrc != NULL ) ) + 457 .loc 1 142 0 + 458 0002 0028 cmp r0, #0 + 459 0004 0AD0 beq .L38 + 460 .loc 1 142 0 is_stmt 0 discriminator 1 + 461 0006 0029 cmp r1, #0 + 462 0008 08D0 beq .L38 + 463 .LBB32: + 143:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 144:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t i = 0; i < len; i++ ) + 464 .loc 1 144 0 is_stmt 1 + ARM GAS /tmp/ccAkEbCV.s page 12 + + + 465 000a 0023 movs r3, #0 + 466 000c 04E0 b .L40 + 467 .LVL56: + 468 .L41: + 145:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 146:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** channelsMaskDest[i] = channelsMaskSrc[i]; + 469 .loc 1 146 0 discriminator 3 + 470 000e 5C00 lsls r4, r3, #1 + 471 0010 0D5B ldrh r5, [r1, r4] + 472 0012 0553 strh r5, [r0, r4] + 144:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 473 .loc 1 144 0 discriminator 3 + 474 0014 0133 adds r3, r3, #1 + 475 .LVL57: + 476 0016 DBB2 uxtb r3, r3 + 477 .LVL58: + 478 .L40: + 144:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 479 .loc 1 144 0 is_stmt 0 discriminator 1 + 480 0018 9342 cmp r3, r2 + 481 001a F8D3 bcc .L41 + 482 .LVL59: + 483 .L38: + 484 .LBE32: + 147:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 148:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 149:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 485 .loc 1 149 0 is_stmt 1 + 486 @ sp needed + 487 001c 30BD pop {r4, r5, pc} + 488 .cfi_endproc + 489 .LFE88: + 491 .section .text.RegionCommonSetBandTxDone,"ax",%progbits + 492 .align 1 + 493 .global RegionCommonSetBandTxDone + 494 .syntax unified + 495 .code 16 + 496 .thumb_func + 497 .fpu softvfp + 499 RegionCommonSetBandTxDone: + 500 .LFB89: + 150:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 151:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** void RegionCommonSetBandTxDone( bool joined, Band_t* band, TimerTime_t lastTxDone ) + 152:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 501 .loc 1 152 0 + 502 .cfi_startproc + 503 @ args = 0, pretend = 0, frame = 0 + 504 @ frame_needed = 0, uses_anonymous_args = 0 + 505 @ link register save eliminated. + 506 .LVL60: + 153:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( joined == true ) + 507 .loc 1 153 0 + 508 0000 0028 cmp r0, #0 + 509 0002 02D1 bne .L46 + 154:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 155:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** band->LastTxDoneTime = lastTxDone; + 156:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + ARM GAS /tmp/ccAkEbCV.s page 13 + + + 157:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 158:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 159:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** band->LastTxDoneTime = lastTxDone; + 510 .loc 1 159 0 + 511 0004 8A60 str r2, [r1, #8] + 160:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** band->LastJoinTxDoneTime = lastTxDone; + 512 .loc 1 160 0 + 513 0006 4A60 str r2, [r1, #4] + 514 .L43: + 161:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 162:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 515 .loc 1 162 0 + 516 @ sp needed + 517 0008 7047 bx lr + 518 .L46: + 155:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 519 .loc 1 155 0 + 520 000a 8A60 str r2, [r1, #8] + 521 000c FCE7 b .L43 + 522 .cfi_endproc + 523 .LFE89: + 525 .section .text.RegionCommonUpdateBandTimeOff,"ax",%progbits + 526 .align 1 + 527 .global RegionCommonUpdateBandTimeOff + 528 .syntax unified + 529 .code 16 + 530 .thumb_func + 531 .fpu softvfp + 533 RegionCommonUpdateBandTimeOff: + 534 .LFB90: + 163:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 164:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** TimerTime_t RegionCommonUpdateBandTimeOff( bool joined, bool dutyCycle, Band_t* bands, uint8_t nbBa + 165:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 535 .loc 1 165 0 + 536 .cfi_startproc + 537 @ args = 0, pretend = 0, frame = 0 + 538 @ frame_needed = 0, uses_anonymous_args = 0 + 539 .LVL61: + 540 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 541 .LCFI5: + 542 .cfi_def_cfa_offset 24 + 543 .cfi_offset 3, -24 + 544 .cfi_offset 4, -20 + 545 .cfi_offset 5, -16 + 546 .cfi_offset 6, -12 + 547 .cfi_offset 7, -8 + 548 .cfi_offset 14, -4 + 549 0002 DE46 mov lr, fp + 550 0004 5746 mov r7, r10 + 551 0006 4E46 mov r6, r9 + 552 0008 4546 mov r5, r8 + 553 000a E0B5 push {r5, r6, r7, lr} + 554 .LCFI6: + 555 .cfi_def_cfa_offset 40 + 556 .cfi_offset 8, -40 + 557 .cfi_offset 9, -36 + 558 .cfi_offset 10, -32 + ARM GAS /tmp/ccAkEbCV.s page 14 + + + 559 .cfi_offset 11, -28 + 560 000c 8046 mov r8, r0 + 561 000e 0E00 movs r6, r1 + 562 0010 9146 mov r9, r2 + 563 0012 1F00 movs r7, r3 + 564 .LVL62: + 565 .LBB33: + 166:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** TimerTime_t nextTxDelay = ( TimerTime_t )( -1 ); + 167:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 168:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Update bands Time OFF + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** for( uint8_t i = 0; i < nbBands; i++ ) + 566 .loc 1 169 0 + 567 0014 0024 movs r4, #0 + 568 .LBE33: + 166:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** TimerTime_t nextTxDelay = ( TimerTime_t )( -1 ); + 569 .loc 1 166 0 + 570 0016 0123 movs r3, #1 + 571 .LVL63: + 572 0018 5B42 rsbs r3, r3, #0 + 573 001a 9A46 mov r10, r3 + 574 .LBB35: + 575 .loc 1 169 0 + 576 001c 37E0 b .L48 + 577 .LVL64: + 578 .L66: + 579 .LBB34: + 170:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 171:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( joined == false ) + 172:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 173:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint32_t txDoneTime = MAX( TimerGetElapsedTime( bands[i].LastJoinTxDoneTime ), + 580 .loc 1 173 0 + 581 001e 2501 lsls r5, r4, #4 + 582 0020 4D44 add r5, r5, r9 + 583 0022 6868 ldr r0, [r5, #4] + 584 0024 FFF7FEFF bl TimerGetElapsedTime + 585 .LVL65: + 586 0028 8346 mov fp, r0 + 587 002a 002E cmp r6, #0 + 588 002c 12D1 bne .L61 + 589 002e 0020 movs r0, #0 + 590 .L50: + 591 .loc 1 173 0 is_stmt 0 discriminator 4 + 592 0030 8345 cmp fp, r0 + 593 0032 13D8 bhi .L62 + 594 .loc 1 173 0 discriminator 6 + 595 0034 002E cmp r6, #0 + 596 0036 15D1 bne .L63 + 597 .loc 1 173 0 + 598 0038 0020 movs r0, #0 + 599 .L52: + 600 .LVL66: + 174:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( dutyCycle == true ) ? TimerGetElapsedTime( bands[i].LastT + 175:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 176:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( bands[i].TimeOff <= txDoneTime ) + 601 .loc 1 176 0 is_stmt 1 discriminator 12 + 602 003a EB68 ldr r3, [r5, #12] + 603 003c 8342 cmp r3, r0 + ARM GAS /tmp/ccAkEbCV.s page 15 + + + 604 003e 01D8 bhi .L53 + 177:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 178:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bands[i].TimeOff = 0; + 605 .loc 1 178 0 + 606 0040 0023 movs r3, #0 + 607 0042 EB60 str r3, [r5, #12] + 608 .L53: + 179:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 180:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( bands[i].TimeOff != 0 ) + 609 .loc 1 180 0 + 610 0044 EB68 ldr r3, [r5, #12] + 611 0046 002B cmp r3, #0 + 612 0048 1FD0 beq .L54 + 181:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 182:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay = MIN( bands[i].TimeOff - txDoneTime, nextTxDelay ); + 613 .loc 1 182 0 + 614 004a 1B1A subs r3, r3, r0 + 615 004c 9A45 cmp r10, r3 + 616 004e 1CD9 bls .L54 + 617 0050 9A46 mov r10, r3 + 618 .LVL67: + 619 0052 1AE0 b .L54 + 620 .LVL68: + 621 .L61: + 173:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( dutyCycle == true ) ? TimerGetElapsedTime( bands[i].LastT + 622 .loc 1 173 0 discriminator 1 + 623 0054 A868 ldr r0, [r5, #8] + 624 0056 FFF7FEFF bl TimerGetElapsedTime + 625 .LVL69: + 626 005a E9E7 b .L50 + 627 .L62: + 173:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( dutyCycle == true ) ? TimerGetElapsedTime( bands[i].LastT + 628 .loc 1 173 0 is_stmt 0 discriminator 5 + 629 005c 6868 ldr r0, [r5, #4] + 630 005e FFF7FEFF bl TimerGetElapsedTime + 631 .LVL70: + 632 0062 EAE7 b .L52 + 633 .L63: + 173:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** ( dutyCycle == true ) ? TimerGetElapsedTime( bands[i].LastT + 634 .loc 1 173 0 discriminator 8 + 635 0064 A868 ldr r0, [r5, #8] + 636 0066 FFF7FEFF bl TimerGetElapsedTime + 637 .LVL71: + 638 006a E6E7 b .L52 + 639 .L67: + 640 .LBE34: + 183:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 184:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 185:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 186:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 187:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( dutyCycle == true ) + 188:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 189:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( bands[i].TimeOff <= TimerGetElapsedTime( bands[i].LastTxDoneTime ) ) + 641 .loc 1 189 0 is_stmt 1 + 642 006c 2501 lsls r5, r4, #4 + 643 006e 4D44 add r5, r5, r9 + 644 0070 EB68 ldr r3, [r5, #12] + ARM GAS /tmp/ccAkEbCV.s page 16 + + + 645 0072 9B46 mov fp, r3 + 646 0074 A868 ldr r0, [r5, #8] + 647 0076 FFF7FEFF bl TimerGetElapsedTime + 648 .LVL72: + 649 007a 8345 cmp fp, r0 + 650 007c 01D8 bhi .L57 + 190:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 191:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bands[i].TimeOff = 0; + 651 .loc 1 191 0 + 652 007e 0023 movs r3, #0 + 653 0080 EB60 str r3, [r5, #12] + 654 .L57: + 192:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 193:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( bands[i].TimeOff != 0 ) + 655 .loc 1 193 0 + 656 0082 EB68 ldr r3, [r5, #12] + 657 0084 9B46 mov fp, r3 + 658 0086 002B cmp r3, #0 + 659 0088 0FD1 bne .L64 + 660 .LVL73: + 661 .L54: + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 662 .loc 1 169 0 discriminator 2 + 663 008a 0134 adds r4, r4, #1 + 664 .LVL74: + 665 008c E4B2 uxtb r4, r4 + 666 .LVL75: + 667 .L48: + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 668 .loc 1 169 0 is_stmt 0 discriminator 1 + 669 008e BC42 cmp r4, r7 + 670 0090 1BD2 bcs .L65 + 171:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 671 .loc 1 171 0 is_stmt 1 + 672 0092 4346 mov r3, r8 + 673 0094 002B cmp r3, #0 + 674 0096 C2D0 beq .L66 + 187:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 675 .loc 1 187 0 + 676 0098 002E cmp r6, #0 + 677 009a E7D1 bne .L67 + 678 .LVL76: + 194:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 195:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay = MIN( bands[i].TimeOff - TimerGetElapsedTime( bands[i].LastTxDoneT + 196:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay ); + 197:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 198:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 199:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 200:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 201:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay = 0; + 202:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bands[i].TimeOff = 0; + 679 .loc 1 202 0 + 680 009c 2301 lsls r3, r4, #4 + 681 009e 4B44 add r3, r3, r9 + 682 00a0 0022 movs r2, #0 + 683 00a2 DA60 str r2, [r3, #12] + 201:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** bands[i].TimeOff = 0; + ARM GAS /tmp/ccAkEbCV.s page 17 + + + 684 .loc 1 201 0 + 685 00a4 0023 movs r3, #0 + 686 00a6 9A46 mov r10, r3 + 687 00a8 EFE7 b .L54 + 688 .LVL77: + 689 .L64: + 195:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay ); + 690 .loc 1 195 0 + 691 00aa A868 ldr r0, [r5, #8] + 692 00ac FFF7FEFF bl TimerGetElapsedTime + 693 .LVL78: + 694 00b0 5B46 mov r3, fp + 695 00b2 181A subs r0, r3, r0 + 696 00b4 5045 cmp r0, r10 + 697 00b6 E8D2 bcs .L54 + 195:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nextTxDelay ); + 698 .loc 1 195 0 is_stmt 0 discriminator 1 + 699 00b8 EB68 ldr r3, [r5, #12] + 700 00ba 9A46 mov r10, r3 + 701 .LVL79: + 702 00bc A868 ldr r0, [r5, #8] + 703 00be FFF7FEFF bl TimerGetElapsedTime + 704 .LVL80: + 705 00c2 5346 mov r3, r10 + 706 00c4 1B1A subs r3, r3, r0 + 707 00c6 9A46 mov r10, r3 + 708 00c8 DFE7 b .L54 + 709 .LVL81: + 710 .L65: + 711 .LBE35: + 203:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 204:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 205:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 206:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return nextTxDelay; + 207:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 712 .loc 1 207 0 is_stmt 1 + 713 00ca 5046 mov r0, r10 + 714 @ sp needed + 715 .LVL82: + 716 .LVL83: + 717 .LVL84: + 718 00cc 3CBC pop {r2, r3, r4, r5} + 719 00ce 9046 mov r8, r2 + 720 00d0 9946 mov r9, r3 + 721 00d2 A246 mov r10, r4 + 722 00d4 AB46 mov fp, r5 + 723 00d6 F8BD pop {r3, r4, r5, r6, r7, pc} + 724 .cfi_endproc + 725 .LFE90: + 727 .section .text.RegionCommonParseLinkAdrReq,"ax",%progbits + 728 .align 1 + 729 .global RegionCommonParseLinkAdrReq + 730 .syntax unified + 731 .code 16 + 732 .thumb_func + 733 .fpu softvfp + 735 RegionCommonParseLinkAdrReq: + ARM GAS /tmp/ccAkEbCV.s page 18 + + + 736 .LFB91: + 208:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 209:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t RegionCommonParseLinkAdrReq( uint8_t* payload, RegionCommonLinkAdrParams_t* linkAdrParams ) + 210:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 737 .loc 1 210 0 + 738 .cfi_startproc + 739 @ args = 0, pretend = 0, frame = 0 + 740 @ frame_needed = 0, uses_anonymous_args = 0 + 741 .LVL85: + 742 0000 10B5 push {r4, lr} + 743 .LCFI7: + 744 .cfi_def_cfa_offset 8 + 745 .cfi_offset 4, -8 + 746 .cfi_offset 14, -4 + 747 .LVL86: + 211:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t retIndex = 0; + 212:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 213:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( payload[0] == SRV_MAC_LINK_ADR_REQ ) + 748 .loc 1 213 0 + 749 0002 0378 ldrb r3, [r0] + 750 0004 032B cmp r3, #3 + 751 0006 01D0 beq .L71 + 211:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t retIndex = 0; + 752 .loc 1 211 0 + 753 0008 0020 movs r0, #0 + 754 .LVL87: + 755 .L69: + 214:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 215:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Parse datarate and tx power + 216:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->Datarate = payload[1]; + 217:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->TxPower = linkAdrParams->Datarate & 0x0F; + 218:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->Datarate = ( linkAdrParams->Datarate >> 4 ) & 0x0F; + 219:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Parse ChMask + 220:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->ChMask = ( uint16_t )payload[2]; + 221:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->ChMask |= ( uint16_t )payload[3] << 8; + 222:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Parse ChMaskCtrl and nbRep + 223:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->NbRep = payload[4]; + 224:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->ChMaskCtrl = ( linkAdrParams->NbRep >> 4 ) & 0x07; + 225:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->NbRep &= 0x0F; + 226:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 227:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // LinkAdrReq has 4 bytes length + 1 byte CMD + 228:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** retIndex = 5; + 229:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 230:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return retIndex; + 231:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 756 .loc 1 231 0 + 757 @ sp needed + 758 000a 10BD pop {r4, pc} + 759 .LVL88: + 760 .L71: + 216:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->TxPower = linkAdrParams->Datarate & 0x0F; + 761 .loc 1 216 0 + 762 000c 4278 ldrb r2, [r0, #1] + 763 000e 54B2 sxtb r4, r2 + 217:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->Datarate = ( linkAdrParams->Datarate >> 4 ) & 0x0F; + 764 .loc 1 217 0 + 765 0010 0C33 adds r3, r3, #12 + ARM GAS /tmp/ccAkEbCV.s page 19 + + + 766 0012 1C40 ands r4, r3 + 767 0014 8C70 strb r4, [r1, #2] + 218:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Parse ChMask + 768 .loc 1 218 0 + 769 0016 1209 lsrs r2, r2, #4 + 770 0018 4A70 strb r2, [r1, #1] + 220:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->ChMask |= ( uint16_t )payload[3] << 8; + 771 .loc 1 220 0 + 772 001a 8278 ldrb r2, [r0, #2] + 773 001c 8A80 strh r2, [r1, #4] + 221:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Parse ChMaskCtrl and nbRep + 774 .loc 1 221 0 + 775 001e C478 ldrb r4, [r0, #3] + 776 0020 2402 lsls r4, r4, #8 + 777 0022 2243 orrs r2, r4 + 778 0024 8A80 strh r2, [r1, #4] + 223:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->ChMaskCtrl = ( linkAdrParams->NbRep >> 4 ) & 0x07; + 779 .loc 1 223 0 + 780 0026 0079 ldrb r0, [r0, #4] + 781 .LVL89: + 224:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** linkAdrParams->NbRep &= 0x0F; + 782 .loc 1 224 0 + 783 0028 0409 lsrs r4, r0, #4 + 784 002a 0722 movs r2, #7 + 785 002c 2240 ands r2, r4 + 786 002e CA70 strb r2, [r1, #3] + 225:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 787 .loc 1 225 0 + 788 0030 0340 ands r3, r0 + 789 0032 0B70 strb r3, [r1] + 790 .LVL90: + 228:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 791 .loc 1 228 0 + 792 0034 0520 movs r0, #5 + 793 0036 E8E7 b .L69 + 794 .cfi_endproc + 795 .LFE91: + 797 .section .text.RegionCommonLinkAdrReqVerifyParams,"ax",%progbits + 798 .align 1 + 799 .global RegionCommonLinkAdrReqVerifyParams + 800 .syntax unified + 801 .code 16 + 802 .thumb_func + 803 .fpu softvfp + 805 RegionCommonLinkAdrReqVerifyParams: + 806 .LFB92: + 232:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 233:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t RegionCommonLinkAdrReqVerifyParams( RegionCommonLinkAdrReqVerifyParams_t* verifyParams, int + 234:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 807 .loc 1 234 0 + 808 .cfi_startproc + 809 @ args = 0, pretend = 0, frame = 0 + 810 @ frame_needed = 0, uses_anonymous_args = 0 + 811 .LVL91: + 812 0000 F0B5 push {r4, r5, r6, r7, lr} + 813 .LCFI8: + 814 .cfi_def_cfa_offset 20 + ARM GAS /tmp/ccAkEbCV.s page 20 + + + 815 .cfi_offset 4, -20 + 816 .cfi_offset 5, -16 + 817 .cfi_offset 6, -12 + 818 .cfi_offset 7, -8 + 819 .cfi_offset 14, -4 + 820 0002 DE46 mov lr, fp + 821 0004 5746 mov r7, r10 + 822 0006 4E46 mov r6, r9 + 823 0008 4546 mov r5, r8 + 824 000a E0B5 push {r5, r6, r7, lr} + 825 .LCFI9: + 826 .cfi_def_cfa_offset 36 + 827 .cfi_offset 8, -36 + 828 .cfi_offset 9, -32 + 829 .cfi_offset 10, -28 + 830 .cfi_offset 11, -24 + 831 000c 83B0 sub sp, sp, #12 + 832 .LCFI10: + 833 .cfi_def_cfa_offset 48 + 834 000e 0400 movs r4, r0 + 835 0010 8B46 mov fp, r1 + 836 0012 9246 mov r10, r2 + 837 0014 9946 mov r9, r3 + 235:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t status = verifyParams->Status; + 838 .loc 1 235 0 + 839 0016 0578 ldrb r5, [r0] + 840 .LVL92: + 236:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** int8_t datarate = verifyParams->Datarate; + 841 .loc 1 236 0 + 842 0018 0223 movs r3, #2 + 843 .LVL93: + 844 001a C356 ldrsb r3, [r0, r3] + 845 001c 9846 mov r8, r3 + 846 .LVL94: + 237:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** int8_t txPower = verifyParams->TxPower; + 847 .loc 1 237 0 + 848 001e 0326 movs r6, #3 + 849 0020 8657 ldrsb r6, [r0, r6] + 850 .LVL95: + 238:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** int8_t nbRepetitions = verifyParams->NbRep; + 851 .loc 1 238 0 + 852 0022 0427 movs r7, #4 + 853 0024 C757 ldrsb r7, [r0, r7] + 854 .LVL96: + 239:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 240:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Handle the case when ADR is off. + 241:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( verifyParams->AdrEnabled == false ) + 855 .loc 1 241 0 + 856 0026 4378 ldrb r3, [r0, #1] + 857 0028 002B cmp r3, #0 + 858 002a 0CD1 bne .L73 + 242:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 243:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // When ADR is off, we are allowed to change the channels mask and the NbRep, + 244:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // if the datarate and the TX power of the LinkAdrReq are set to 0x0F. + 245:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( verifyParams->Datarate != 0x0F ) || ( verifyParams->TxPower != 0x0F ) ) + 859 .loc 1 245 0 + 860 002c 0223 movs r3, #2 + ARM GAS /tmp/ccAkEbCV.s page 21 + + + 861 002e C25E ldrsh r2, [r0, r3] + 862 .LVL97: + 863 0030 204B ldr r3, .L82 + 864 0032 9A42 cmp r2, r3 + 865 0034 02D0 beq .L74 + 866 .LVL98: + 246:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 247:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** status = 0; + 248:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nbRepetitions = verifyParams->CurrentNbRep; + 867 .loc 1 248 0 + 868 0036 0727 movs r7, #7 + 869 .LVL99: + 870 0038 C757 ldrsb r7, [r0, r7] + 871 .LVL100: + 247:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nbRepetitions = verifyParams->CurrentNbRep; + 872 .loc 1 247 0 + 873 003a 0025 movs r5, #0 + 874 .LVL101: + 875 .L74: + 249:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 250:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Get the current datarate and tx power + 251:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** datarate = verifyParams->CurrentDatarate; + 876 .loc 1 251 0 + 877 003c 0523 movs r3, #5 + 878 003e E356 ldrsb r3, [r4, r3] + 879 0040 9846 mov r8, r3 + 880 .LVL102: + 252:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** txPower = verifyParams->CurrentTxPower; + 881 .loc 1 252 0 + 882 0042 0626 movs r6, #6 + 883 .LVL103: + 884 0044 A657 ldrsb r6, [r4, r6] + 885 .LVL104: + 886 .L73: + 253:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 254:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 255:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( status != 0 ) + 887 .loc 1 255 0 + 888 0046 002D cmp r5, #0 + 889 0048 10D1 bne .L80 + 890 .LVL105: + 891 .L75: + 256:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 257:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Verify datarate. The variable phyParam. Value contains the minimum allowed datarate. + 258:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( RegionCommonChanVerifyDr( verifyParams->NbChannels, verifyParams->ChannelsMask, datarat + 259:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** verifyParams->MinDatarate, verifyParams->MaxDatarate, verifyP + 260:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 261:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** status &= 0xFD; // Datarate KO + 262:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 263:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 264:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Verify tx power + 265:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( RegionCommonValueInRange( txPower, verifyParams->MaxTxPower, verifyParams->MinTxPower ) + 266:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 267:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Verify if the maximum TX power is exceeded + 268:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( verifyParams->MaxTxPower > txPower ) + 269:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { // Apply maximum TX power. Accept TX power. + 270:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** txPower = verifyParams->MaxTxPower; + ARM GAS /tmp/ccAkEbCV.s page 22 + + + 271:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 272:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 273:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 274:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** status &= 0xFB; // TxPower KO + 275:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 276:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 277:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 278:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 279:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // If the status is ok, verify the NbRep + 280:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( status == 0x07 ) + 892 .loc 1 280 0 + 893 004a 072D cmp r5, #7 + 894 004c 2DD0 beq .L81 + 895 .L78: + 281:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 282:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( nbRepetitions == 0 ) + 283:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { // Keep the current one + 284:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** nbRepetitions = verifyParams->CurrentNbRep; + 285:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 286:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 287:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 288:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Apply changes + 289:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** *dr = datarate; + 896 .loc 1 289 0 + 897 004e 5B46 mov r3, fp + 898 0050 4246 mov r2, r8 + 899 0052 1A70 strb r2, [r3] + 290:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** *txPow = txPower; + 900 .loc 1 290 0 + 901 0054 5346 mov r3, r10 + 902 0056 1E70 strb r6, [r3] + 291:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** *nbRep = nbRepetitions; + 903 .loc 1 291 0 + 904 0058 4B46 mov r3, r9 + 905 005a 1F70 strb r7, [r3] + 292:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 293:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return status; + 294:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 906 .loc 1 294 0 + 907 005c 2800 movs r0, r5 + 908 005e 03B0 add sp, sp, #12 + 909 @ sp needed + 910 .LVL106: + 911 .LVL107: + 912 .LVL108: + 913 .LVL109: + 914 .LVL110: + 915 .LVL111: + 916 .LVL112: + 917 .LVL113: + 918 0060 3CBC pop {r2, r3, r4, r5} + 919 0062 9046 mov r8, r2 + 920 0064 9946 mov r9, r3 + 921 0066 A246 mov r10, r4 + 922 0068 AB46 mov fp, r5 + 923 006a F0BD pop {r4, r5, r6, r7, pc} + 924 .LVL114: + ARM GAS /tmp/ccAkEbCV.s page 23 + + + 925 .L80: + 258:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** verifyParams->MinDatarate, verifyParams->MaxDatarate, verifyP + 926 .loc 1 258 0 + 927 006c 1023 movs r3, #16 + 928 006e E356 ldrsb r3, [r4, r3] + 929 0070 207A ldrb r0, [r4, #8] + 930 .LVL115: + 931 0072 6269 ldr r2, [r4, #20] + 932 0074 0192 str r2, [sp, #4] + 933 0076 1122 movs r2, #17 + 934 0078 A256 ldrsb r2, [r4, r2] + 935 007a 0092 str r2, [sp] + 936 007c 4246 mov r2, r8 + 937 007e E168 ldr r1, [r4, #12] + 938 .LVL116: + 939 0080 FFF7FEFF bl RegionCommonChanVerifyDr + 940 .LVL117: + 941 0084 0028 cmp r0, #0 + 942 0086 01D1 bne .L76 + 261:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 943 .loc 1 261 0 + 944 0088 0223 movs r3, #2 + 945 008a 9D43 bics r5, r3 + 946 .LVL118: + 947 .L76: + 265:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 948 .loc 1 265 0 + 949 008c 1923 movs r3, #25 + 950 008e E356 ldrsb r3, [r4, r3] + 951 0090 1822 movs r2, #24 + 952 0092 A256 ldrsb r2, [r4, r2] + 953 .LVL119: + 954 .LBB36: + 955 .LBB37: + 101:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 956 .loc 1 101 0 + 957 0094 B342 cmp r3, r6 + 958 0096 01DC bgt .L77 + 959 0098 B242 cmp r2, r6 + 960 009a D6DA bge .L75 + 961 .L77: + 962 .LVL120: + 963 .LBE37: + 964 .LBE36: + 268:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { // Apply maximum TX power. Accept TX power. + 965 .loc 1 268 0 + 966 009c B342 cmp r3, r6 + 967 009e 02DC bgt .L79 + 274:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 968 .loc 1 274 0 + 969 00a0 0423 movs r3, #4 + 970 00a2 9D43 bics r5, r3 + 971 .LVL121: + 972 00a4 D1E7 b .L75 + 973 .L79: + 270:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 974 .loc 1 270 0 + ARM GAS /tmp/ccAkEbCV.s page 24 + + + 975 00a6 1E00 movs r6, r3 + 976 .LVL122: + 977 00a8 CFE7 b .L75 + 978 .LVL123: + 979 .L81: + 282:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { // Keep the current one + 980 .loc 1 282 0 + 981 00aa 002F cmp r7, #0 + 982 00ac CFD1 bne .L78 + 284:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 983 .loc 1 284 0 + 984 00ae 0727 movs r7, #7 + 985 .LVL124: + 986 00b0 E757 ldrsb r7, [r4, r7] + 987 .LVL125: + 988 00b2 CCE7 b .L78 + 989 .L83: + 990 .align 2 + 991 .L82: + 992 00b4 0F0F0000 .word 3855 + 993 .cfi_endproc + 994 .LFE92: + 996 .global __aeabi_i2d + 997 .global __aeabi_ui2d + 998 .global __aeabi_ddiv + 999 .global __aeabi_dmul + 1000 .section .text.RegionCommonComputeSymbolTimeLoRa,"ax",%progbits + 1001 .align 1 + 1002 .global RegionCommonComputeSymbolTimeLoRa + 1003 .syntax unified + 1004 .code 16 + 1005 .thumb_func + 1006 .fpu softvfp + 1008 RegionCommonComputeSymbolTimeLoRa: + 1009 .LFB93: + 295:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 296:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** double RegionCommonComputeSymbolTimeLoRa( uint8_t phyDr, uint32_t bandwidth ) + 297:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1010 .loc 1 297 0 + 1011 .cfi_startproc + 1012 @ args = 0, pretend = 0, frame = 0 + 1013 @ frame_needed = 0, uses_anonymous_args = 0 + 1014 .LVL126: + 1015 0000 D0B5 push {r4, r6, r7, lr} + 1016 .LCFI11: + 1017 .cfi_def_cfa_offset 16 + 1018 .cfi_offset 4, -16 + 1019 .cfi_offset 6, -12 + 1020 .cfi_offset 7, -8 + 1021 .cfi_offset 14, -4 + 1022 0002 0C00 movs r4, r1 + 298:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return ( ( double )( 1 << phyDr ) / ( double )bandwidth ) * 1000; + 1023 .loc 1 298 0 + 1024 0004 0123 movs r3, #1 + 1025 0006 8340 lsls r3, r3, r0 + 1026 0008 1800 movs r0, r3 + 1027 .LVL127: + ARM GAS /tmp/ccAkEbCV.s page 25 + + + 1028 000a FFF7FEFF bl __aeabi_i2d + 1029 .LVL128: + 1030 000e 0600 movs r6, r0 + 1031 0010 0F00 movs r7, r1 + 1032 0012 2000 movs r0, r4 + 1033 0014 FFF7FEFF bl __aeabi_ui2d + 1034 .LVL129: + 1035 0018 0200 movs r2, r0 + 1036 001a 0B00 movs r3, r1 + 1037 001c 3000 movs r0, r6 + 1038 001e 3900 movs r1, r7 + 1039 0020 FFF7FEFF bl __aeabi_ddiv + 1040 .LVL130: + 1041 0024 0022 movs r2, #0 + 1042 0026 024B ldr r3, .L85 + 1043 0028 FFF7FEFF bl __aeabi_dmul + 1044 .LVL131: + 299:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1045 .loc 1 299 0 + 1046 @ sp needed + 1047 .LVL132: + 1048 002c D0BD pop {r4, r6, r7, pc} + 1049 .L86: + 1050 002e C046 .align 2 + 1051 .L85: + 1052 0030 00408F40 .word 1083129856 + 1053 .cfi_endproc + 1054 .LFE93: + 1056 .section .text.RegionCommonComputeSymbolTimeFsk,"ax",%progbits + 1057 .align 1 + 1058 .global RegionCommonComputeSymbolTimeFsk + 1059 .syntax unified + 1060 .code 16 + 1061 .thumb_func + 1062 .fpu softvfp + 1064 RegionCommonComputeSymbolTimeFsk: + 1065 .LFB94: + 300:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 301:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** double RegionCommonComputeSymbolTimeFsk( uint8_t phyDr ) + 302:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1066 .loc 1 302 0 + 1067 .cfi_startproc + 1068 @ args = 0, pretend = 0, frame = 0 + 1069 @ frame_needed = 0, uses_anonymous_args = 0 + 1070 .LVL133: + 1071 0000 10B5 push {r4, lr} + 1072 .LCFI12: + 1073 .cfi_def_cfa_offset 8 + 1074 .cfi_offset 4, -8 + 1075 .cfi_offset 14, -4 + 303:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return ( 8.0 / ( double )phyDr ); // 1 symbol equals 1 byte + 1076 .loc 1 303 0 + 1077 0002 FFF7FEFF bl __aeabi_ui2d + 1078 .LVL134: + 1079 0006 0200 movs r2, r0 + 1080 0008 0B00 movs r3, r1 + 1081 000a 0020 movs r0, #0 + ARM GAS /tmp/ccAkEbCV.s page 26 + + + 1082 000c 0149 ldr r1, .L88 + 1083 000e FFF7FEFF bl __aeabi_ddiv + 1084 .LVL135: + 304:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1085 .loc 1 304 0 + 1086 @ sp needed + 1087 0012 10BD pop {r4, pc} + 1088 .L89: + 1089 .align 2 + 1090 .L88: + 1091 0014 00002040 .word 1075838976 + 1092 .cfi_endproc + 1093 .LFE94: + 1095 .global __aeabi_dadd + 1096 .global __aeabi_d2uiz + 1097 .global __aeabi_dsub + 1098 .global __aeabi_d2iz + 1099 .section .text.RegionCommonComputeRxWindowParameters,"ax",%progbits + 1100 .align 1 + 1101 .global RegionCommonComputeRxWindowParameters + 1102 .syntax unified + 1103 .code 16 + 1104 .thumb_func + 1105 .fpu softvfp + 1107 RegionCommonComputeRxWindowParameters: + 1108 .LFB95: + 305:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 306:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** void RegionCommonComputeRxWindowParameters( double tSymbol, uint8_t minRxSymbols, uint32_t rxError, + 307:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1109 .loc 1 307 0 + 1110 .cfi_startproc + 1111 @ args = 12, pretend = 0, frame = 8 + 1112 @ frame_needed = 0, uses_anonymous_args = 0 + 1113 .LVL136: + 1114 0000 F0B5 push {r4, r5, r6, r7, lr} + 1115 .LCFI13: + 1116 .cfi_def_cfa_offset 20 + 1117 .cfi_offset 4, -20 + 1118 .cfi_offset 5, -16 + 1119 .cfi_offset 6, -12 + 1120 .cfi_offset 7, -8 + 1121 .cfi_offset 14, -4 + 1122 0002 83B0 sub sp, sp, #12 + 1123 .LCFI14: + 1124 .cfi_def_cfa_offset 32 + 1125 0004 0400 movs r4, r0 + 1126 0006 0D00 movs r5, r1 + 1127 0008 1600 movs r6, r2 + 1128 000a 1F00 movs r7, r3 + 308:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** *windowTimeout = MAX( ( uint32_t )ceil( ( ( 2 * minRxSymbols - 8 ) * tSymbol + 2 * rxError ) / + 1129 .loc 1 308 0 + 1130 000c 101F subs r0, r2, #4 + 1131 .LVL137: + 1132 000e 4000 lsls r0, r0, #1 + 1133 0010 FFF7FEFF bl __aeabi_i2d + 1134 .LVL138: + 1135 0014 2200 movs r2, r4 + ARM GAS /tmp/ccAkEbCV.s page 27 + + + 1136 0016 2B00 movs r3, r5 + 1137 0018 FFF7FEFF bl __aeabi_dmul + 1138 .LVL139: + 1139 001c 0090 str r0, [sp] + 1140 001e 0191 str r1, [sp, #4] + 1141 0020 7800 lsls r0, r7, #1 + 1142 0022 FFF7FEFF bl __aeabi_ui2d + 1143 .LVL140: + 1144 0026 009A ldr r2, [sp] + 1145 0028 019B ldr r3, [sp, #4] + 1146 002a FFF7FEFF bl __aeabi_dadd + 1147 .LVL141: + 1148 002e 2200 movs r2, r4 + 1149 0030 2B00 movs r3, r5 + 1150 0032 FFF7FEFF bl __aeabi_ddiv + 1151 .LVL142: + 1152 0036 FFF7FEFF bl ceil + 1153 .LVL143: + 1154 003a FFF7FEFF bl __aeabi_d2uiz + 1155 .LVL144: + 1156 003e 8642 cmp r6, r0 + 1157 0040 00D2 bcs .L91 + 1158 0042 0600 movs r6, r0 + 1159 .L91: + 1160 0044 099B ldr r3, [sp, #36] + 1161 0046 1E60 str r6, [r3] + 309:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** *windowOffset = ( int32_t )ceil( ( 4.0 * tSymbol ) - ( ( *windowTimeout * tSymbol ) / 2.0 ) - w + 1162 .loc 1 309 0 + 1163 0048 0022 movs r2, #0 + 1164 004a 154B ldr r3, .L92 + 1165 004c 2000 movs r0, r4 + 1166 004e 2900 movs r1, r5 + 1167 0050 FFF7FEFF bl __aeabi_dmul + 1168 .LVL145: + 1169 0054 0090 str r0, [sp] + 1170 0056 0191 str r1, [sp, #4] + 1171 0058 3000 movs r0, r6 + 1172 005a FFF7FEFF bl __aeabi_ui2d + 1173 .LVL146: + 1174 005e 2200 movs r2, r4 + 1175 0060 2B00 movs r3, r5 + 1176 0062 FFF7FEFF bl __aeabi_dmul + 1177 .LVL147: + 1178 0066 0022 movs r2, #0 + 1179 0068 0E4B ldr r3, .L92+4 + 1180 006a FFF7FEFF bl __aeabi_dmul + 1181 .LVL148: + 1182 006e 0200 movs r2, r0 + 1183 0070 0B00 movs r3, r1 + 1184 0072 0098 ldr r0, [sp] + 1185 0074 0199 ldr r1, [sp, #4] + 1186 0076 FFF7FEFF bl __aeabi_dsub + 1187 .LVL149: + 1188 007a 0400 movs r4, r0 + 1189 007c 0D00 movs r5, r1 + 1190 007e 0898 ldr r0, [sp, #32] + 1191 0080 FFF7FEFF bl __aeabi_ui2d + ARM GAS /tmp/ccAkEbCV.s page 28 + + + 1192 .LVL150: + 1193 0084 0200 movs r2, r0 + 1194 0086 0B00 movs r3, r1 + 1195 0088 2000 movs r0, r4 + 1196 008a 2900 movs r1, r5 + 1197 008c FFF7FEFF bl __aeabi_dsub + 1198 .LVL151: + 1199 0090 FFF7FEFF bl ceil + 1200 .LVL152: + 1201 0094 FFF7FEFF bl __aeabi_d2iz + 1202 .LVL153: + 1203 0098 0A9B ldr r3, [sp, #40] + 1204 009a 1860 str r0, [r3] + 310:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1205 .loc 1 310 0 + 1206 009c 03B0 add sp, sp, #12 + 1207 @ sp needed + 1208 .LVL154: + 1209 009e F0BD pop {r4, r5, r6, r7, pc} + 1210 .L93: + 1211 .align 2 + 1212 .L92: + 1213 00a0 00001040 .word 1074790400 + 1214 00a4 0000E03F .word 1071644672 + 1215 .cfi_endproc + 1216 .LFE95: + 1218 .global __aeabi_ui2f + 1219 .global __aeabi_fsub + 1220 .global __aeabi_f2d + 1221 .section .text.RegionCommonComputeTxPower,"ax",%progbits + 1222 .align 1 + 1223 .global RegionCommonComputeTxPower + 1224 .syntax unified + 1225 .code 16 + 1226 .thumb_func + 1227 .fpu softvfp + 1229 RegionCommonComputeTxPower: + 1230 .LFB96: + 311:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 312:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** int8_t RegionCommonComputeTxPower( int8_t txPowerIndex, float maxEirp, float antennaGain ) + 313:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1231 .loc 1 313 0 + 1232 .cfi_startproc + 1233 @ args = 0, pretend = 0, frame = 0 + 1234 @ frame_needed = 0, uses_anonymous_args = 0 + 1235 .LVL155: + 1236 0000 70B5 push {r4, r5, r6, lr} + 1237 .LCFI15: + 1238 .cfi_def_cfa_offset 16 + 1239 .cfi_offset 4, -16 + 1240 .cfi_offset 5, -12 + 1241 .cfi_offset 6, -8 + 1242 .cfi_offset 14, -4 + 1243 0002 0D1C adds r5, r1, #0 + 1244 0004 141C adds r4, r2, #0 + 1245 .LVL156: + 314:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** int8_t phyTxPower = 0; + ARM GAS /tmp/ccAkEbCV.s page 29 + + + 315:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 316:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** phyTxPower = ( int8_t )floor( ( maxEirp - ( txPowerIndex * 2U ) ) - antennaGain ); + 1246 .loc 1 316 0 + 1247 0006 4000 lsls r0, r0, #1 + 1248 .LVL157: + 1249 0008 FFF7FEFF bl __aeabi_ui2f + 1250 .LVL158: + 1251 000c 011C adds r1, r0, #0 + 1252 000e 281C adds r0, r5, #0 + 1253 0010 FFF7FEFF bl __aeabi_fsub + 1254 .LVL159: + 1255 0014 211C adds r1, r4, #0 + 1256 0016 FFF7FEFF bl __aeabi_fsub + 1257 .LVL160: + 1258 001a FFF7FEFF bl __aeabi_f2d + 1259 .LVL161: + 1260 001e FFF7FEFF bl floor + 1261 .LVL162: + 1262 0022 FFF7FEFF bl __aeabi_d2iz + 1263 .LVL163: + 1264 0026 40B2 sxtb r0, r0 + 1265 .LVL164: + 317:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 318:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** return phyTxPower; + 319:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1266 .loc 1 319 0 + 1267 @ sp needed + 1268 .LVL165: + 1269 .LVL166: + 1270 0028 70BD pop {r4, r5, r6, pc} + 1271 .cfi_endproc + 1272 .LFE96: + 1274 .section .text.RegionCommonCalcBackOff,"ax",%progbits + 1275 .align 1 + 1276 .global RegionCommonCalcBackOff + 1277 .syntax unified + 1278 .code 16 + 1279 .thumb_func + 1280 .fpu softvfp + 1282 RegionCommonCalcBackOff: + 1283 .LFB97: + 320:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 321:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** void RegionCommonCalcBackOff( RegionCommonCalcBackOffParams_t* calcBackOffParams ) + 322:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1284 .loc 1 322 0 + 1285 .cfi_startproc + 1286 @ args = 0, pretend = 0, frame = 0 + 1287 @ frame_needed = 0, uses_anonymous_args = 0 + 1288 .LVL167: + 1289 0000 10B5 push {r4, lr} + 1290 .LCFI16: + 1291 .cfi_def_cfa_offset 8 + 1292 .cfi_offset 4, -8 + 1293 .cfi_offset 14, -4 + 323:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint8_t bandIdx = calcBackOffParams->Channels[calcBackOffParams->Channel].Band; + 1294 .loc 1 323 0 + 1295 0002 C27A ldrb r2, [r0, #11] + ARM GAS /tmp/ccAkEbCV.s page 30 + + + 1296 0004 5300 lsls r3, r2, #1 + 1297 0006 9B18 adds r3, r3, r2 + 1298 0008 9A00 lsls r2, r3, #2 + 1299 000a 0368 ldr r3, [r0] + 1300 000c 9C46 mov ip, r3 + 1301 000e 6244 add r2, r2, ip + 1302 0010 537A ldrb r3, [r2, #9] + 1303 .LVL168: + 324:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint16_t dutyCycle = calcBackOffParams->Bands[bandIdx].DCycle; + 1304 .loc 1 324 0 + 1305 0012 1B01 lsls r3, r3, #4 + 1306 .LVL169: + 1307 0014 4268 ldr r2, [r0, #4] + 1308 .LVL170: + 1309 0016 D218 adds r2, r2, r3 + 1310 0018 1188 ldrh r1, [r2] + 1311 .LVL171: + 325:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** uint16_t joinDutyCycle = 0; + 326:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 327:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Reset time-off to initial value. + 328:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** calcBackOffParams->Bands[bandIdx].TimeOff = 0; + 1312 .loc 1 328 0 + 1313 001a 0024 movs r4, #0 + 1314 001c D460 str r4, [r2, #12] + 1315 .LVL172: + 329:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** + 330:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( calcBackOffParams->Joined == false ) + 1316 .loc 1 330 0 + 1317 001e 427A ldrb r2, [r0, #9] + 1318 0020 002A cmp r2, #0 + 1319 0022 23D1 bne .L96 + 331:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 332:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Get the join duty cycle + 333:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** joinDutyCycle = RegionCommonGetJoinDc( calcBackOffParams->ElapsedTime ); + 1320 .loc 1 333 0 + 1321 0024 C268 ldr r2, [r0, #12] + 1322 .LVL173: + 1323 .LBB38: + 1324 .LBB39: + 59:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1325 .loc 1 59 0 + 1326 0026 194C ldr r4, .L105 + 1327 0028 A242 cmp r2, r4 + 1328 002a 05D9 bls .L102 + 63:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1329 .loc 1 63 0 + 1330 002c 184C ldr r4, .L105+4 + 1331 002e A242 cmp r2, r4 + 1332 0030 13D8 bhi .L103 + 65:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1333 .loc 1 65 0 + 1334 0032 FA24 movs r4, #250 + 1335 0034 A400 lsls r4, r4, #2 + 1336 0036 00E0 b .L97 + 1337 .L102: + 61:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1338 .loc 1 61 0 + ARM GAS /tmp/ccAkEbCV.s page 31 + + + 1339 0038 6424 movs r4, #100 + 1340 .L97: + 1341 .LVL174: + 1342 .LBE39: + 1343 .LBE38: + 334:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Apply the most restricting duty cycle + 335:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** dutyCycle = MAX( dutyCycle, joinDutyCycle ); + 1344 .loc 1 335 0 + 1345 003a 0A1C adds r2, r1, #0 + 1346 003c A142 cmp r1, r4 + 1347 003e 00D2 bcs .L98 + 1348 0040 221C adds r2, r4, #0 + 1349 .L98: + 1350 0042 92B2 uxth r2, r2 + 1351 .LVL175: + 336:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Reset the timeoff if the last frame was not a join request and when the duty cycle is no + 337:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( ( calcBackOffParams->DutyCycleEnabled == false ) && ( calcBackOffParams->LastTxIsJoinRe + 1352 .loc 1 337 0 + 1353 0044 817A ldrb r1, [r0, #10] + 1354 0046 0029 cmp r1, #0 + 1355 0048 09D1 bne .L99 + 1356 .loc 1 337 0 is_stmt 0 discriminator 1 + 1357 004a 017A ldrb r1, [r0, #8] + 1358 004c 0029 cmp r1, #0 + 1359 004e 06D1 bne .L99 + 338:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 339:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // This is the case when the duty cycle is off and the last uplink frame was not a join + 340:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // This could happen in case of a rejoin, e.g. in compliance test mode. + 341:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // In this special case we have to set the time off to 0, since the join duty cycle sha + 342:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // be applied after the first join request. + 343:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** calcBackOffParams->Bands[bandIdx].TimeOff = 0; + 1360 .loc 1 343 0 is_stmt 1 + 1361 0050 4268 ldr r2, [r0, #4] + 1362 .LVL176: + 1363 0052 D318 adds r3, r2, r3 + 1364 0054 0022 movs r2, #0 + 1365 0056 DA60 str r2, [r3, #12] + 1366 0058 07E0 b .L95 + 1367 .LVL177: + 1368 .L103: + 1369 .LBB41: + 1370 .LBB40: + 69:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1371 .loc 1 69 0 + 1372 005a 0E4C ldr r4, .L105+8 + 1373 005c EDE7 b .L97 + 1374 .LVL178: + 1375 .L99: + 1376 .LBE40: + 1377 .LBE41: + 344:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 345:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 346:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 347:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** // Apply band time-off. + 348:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** calcBackOffParams->Bands[bandIdx].TimeOff = calcBackOffParams->TxTimeOnAir * dutyCycle + 1378 .loc 1 348 0 + 1379 005e 0469 ldr r4, [r0, #16] + ARM GAS /tmp/ccAkEbCV.s page 32 + + + 1380 0060 4168 ldr r1, [r0, #4] + 1381 0062 CB18 adds r3, r1, r3 + 1382 0064 013A subs r2, r2, #1 + 1383 .LVL179: + 1384 0066 6243 muls r2, r4 + 1385 .LVL180: + 1386 0068 DA60 str r2, [r3, #12] + 1387 .L95: + 349:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 350:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 351:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 352:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 353:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** if( calcBackOffParams->DutyCycleEnabled == true ) + 354:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 355:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** calcBackOffParams->Bands[bandIdx].TimeOff = calcBackOffParams->TxTimeOnAir * dutyCycle + 356:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 357:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** else + 358:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 359:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** calcBackOffParams->Bands[bandIdx].TimeOff = 0; + 360:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 361:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 362:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1388 .loc 1 362 0 + 1389 @ sp needed + 1390 006a 10BD pop {r4, pc} + 1391 .LVL181: + 1392 .L96: + 353:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** { + 1393 .loc 1 353 0 + 1394 006c 827A ldrb r2, [r0, #10] + 1395 006e 002A cmp r2, #0 + 1396 0070 04D1 bne .L104 + 359:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1397 .loc 1 359 0 + 1398 0072 4268 ldr r2, [r0, #4] + 1399 0074 D318 adds r3, r2, r3 + 1400 0076 0022 movs r2, #0 + 1401 0078 DA60 str r2, [r3, #12] + 1402 .loc 1 362 0 + 1403 007a F6E7 b .L95 + 1404 .L104: + 355:./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c **** } + 1405 .loc 1 355 0 + 1406 007c 0469 ldr r4, [r0, #16] + 1407 007e 4268 ldr r2, [r0, #4] + 1408 0080 D318 adds r3, r2, r3 + 1409 0082 0139 subs r1, r1, #1 + 1410 .LVL182: + 1411 0084 6143 muls r1, r4 + 1412 .LVL183: + 1413 0086 D960 str r1, [r3, #12] + 1414 0088 EFE7 b .L95 + 1415 .L106: + 1416 008a C046 .align 2 + 1417 .L105: + 1418 008c 7FEE3600 .word 3599999 + 1419 0090 7F3F5C02 .word 39599999 + ARM GAS /tmp/ccAkEbCV.s page 33 + + + 1420 0094 10270000 .word 10000 + 1421 .cfi_endproc + 1422 .LFE97: + 1424 .text + 1425 .Letext0: + 1426 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1427 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 1428 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 1429 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1430 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 1431 .file 7 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1432 .file 8 "/usr/arm-none-eabi/include/math.h" + 1433 .file 9 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 1434 .file 10 "Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 1435 .file 11 "./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h" + 1436 .file 12 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + ARM GAS /tmp/ccAkEbCV.s page 34 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 RegionCommon.c + /tmp/ccAkEbCV.s:16 .text.RegionCommonGetJoinDc:0000000000000000 $t + /tmp/ccAkEbCV.s:23 .text.RegionCommonGetJoinDc:0000000000000000 RegionCommonGetJoinDc + /tmp/ccAkEbCV.s:63 .text.RegionCommonGetJoinDc:000000000000001c $d + /tmp/ccAkEbCV.s:70 .text.RegionCommonChanVerifyDr:0000000000000000 $t + /tmp/ccAkEbCV.s:77 .text.RegionCommonChanVerifyDr:0000000000000000 RegionCommonChanVerifyDr + /tmp/ccAkEbCV.s:221 .text.RegionCommonValueInRange:0000000000000000 $t + /tmp/ccAkEbCV.s:228 .text.RegionCommonValueInRange:0000000000000000 RegionCommonValueInRange + /tmp/ccAkEbCV.s:264 .text.RegionCommonChanDisable:0000000000000000 $t + /tmp/ccAkEbCV.s:271 .text.RegionCommonChanDisable:0000000000000000 RegionCommonChanDisable + /tmp/ccAkEbCV.s:329 .text.RegionCommonCountChannels:0000000000000000 $t + /tmp/ccAkEbCV.s:336 .text.RegionCommonCountChannels:0000000000000000 RegionCommonCountChannels + /tmp/ccAkEbCV.s:437 .text.RegionCommonChanMaskCopy:0000000000000000 $t + /tmp/ccAkEbCV.s:444 .text.RegionCommonChanMaskCopy:0000000000000000 RegionCommonChanMaskCopy + /tmp/ccAkEbCV.s:492 .text.RegionCommonSetBandTxDone:0000000000000000 $t + /tmp/ccAkEbCV.s:499 .text.RegionCommonSetBandTxDone:0000000000000000 RegionCommonSetBandTxDone + /tmp/ccAkEbCV.s:526 .text.RegionCommonUpdateBandTimeOff:0000000000000000 $t + /tmp/ccAkEbCV.s:533 .text.RegionCommonUpdateBandTimeOff:0000000000000000 RegionCommonUpdateBandTimeOff + /tmp/ccAkEbCV.s:728 .text.RegionCommonParseLinkAdrReq:0000000000000000 $t + /tmp/ccAkEbCV.s:735 .text.RegionCommonParseLinkAdrReq:0000000000000000 RegionCommonParseLinkAdrReq + /tmp/ccAkEbCV.s:798 .text.RegionCommonLinkAdrReqVerifyParams:0000000000000000 $t + /tmp/ccAkEbCV.s:805 .text.RegionCommonLinkAdrReqVerifyParams:0000000000000000 RegionCommonLinkAdrReqVerifyParams + /tmp/ccAkEbCV.s:992 .text.RegionCommonLinkAdrReqVerifyParams:00000000000000b4 $d + /tmp/ccAkEbCV.s:1001 .text.RegionCommonComputeSymbolTimeLoRa:0000000000000000 $t + /tmp/ccAkEbCV.s:1008 .text.RegionCommonComputeSymbolTimeLoRa:0000000000000000 RegionCommonComputeSymbolTimeLoRa + /tmp/ccAkEbCV.s:1052 .text.RegionCommonComputeSymbolTimeLoRa:0000000000000030 $d + /tmp/ccAkEbCV.s:1057 .text.RegionCommonComputeSymbolTimeFsk:0000000000000000 $t + /tmp/ccAkEbCV.s:1064 .text.RegionCommonComputeSymbolTimeFsk:0000000000000000 RegionCommonComputeSymbolTimeFsk + /tmp/ccAkEbCV.s:1091 .text.RegionCommonComputeSymbolTimeFsk:0000000000000014 $d + /tmp/ccAkEbCV.s:1100 .text.RegionCommonComputeRxWindowParameters:0000000000000000 $t + /tmp/ccAkEbCV.s:1107 .text.RegionCommonComputeRxWindowParameters:0000000000000000 RegionCommonComputeRxWindowParameters + /tmp/ccAkEbCV.s:1213 .text.RegionCommonComputeRxWindowParameters:00000000000000a0 $d + /tmp/ccAkEbCV.s:1222 .text.RegionCommonComputeTxPower:0000000000000000 $t + /tmp/ccAkEbCV.s:1229 .text.RegionCommonComputeTxPower:0000000000000000 RegionCommonComputeTxPower + /tmp/ccAkEbCV.s:1275 .text.RegionCommonCalcBackOff:0000000000000000 $t + /tmp/ccAkEbCV.s:1282 .text.RegionCommonCalcBackOff:0000000000000000 RegionCommonCalcBackOff + /tmp/ccAkEbCV.s:1418 .text.RegionCommonCalcBackOff:000000000000008c $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +TimerGetElapsedTime +__aeabi_i2d +__aeabi_ui2d +__aeabi_ddiv +__aeabi_dmul +__aeabi_dadd +__aeabi_d2uiz +__aeabi_dsub +__aeabi_d2iz +ceil +__aeabi_ui2f +__aeabi_fsub +__aeabi_f2d +floor diff --git a/build/RegionEU868.d b/build/RegionEU868.d new file mode 100644 index 0000000..f70d056 --- /dev/null +++ b/build/RegionEU868.d @@ -0,0 +1,51 @@ +build/RegionEU868.d: \ + Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c \ + Middlewares/Third_Party/Lora/Phy/radio.h \ + Middlewares/Third_Party/Lora/Mac/timer.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h \ + Middlewares/Third_Party/Lora/Mac/region/Region.h \ + Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h \ + Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h Inc/debug.h \ + Inc/hw_conf.h Inc/vcom.h + +Middlewares/Third_Party/Lora/Phy/radio.h: + +Middlewares/Third_Party/Lora/Mac/timer.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Middlewares/Third_Party/Lora/Mac/region/Region.h: + +Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h: + +Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h: + +Inc/debug.h: + +Inc/hw_conf.h: + +Inc/vcom.h: diff --git a/build/RegionEU868.lst b/build/RegionEU868.lst new file mode 100644 index 0000000..86407fe --- /dev/null +++ b/build/RegionEU868.lst @@ -0,0 +1,4727 @@ +ARM GAS /tmp/cczfoKrY.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "RegionEU868.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.VerifyTxFreq,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 VerifyTxFreq: + 23 .LFB88: + 24 .file 1 "./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c" + 1:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** /* + 2:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ___ _____ _ ___ _ _____ ___ ___ ___ ___ + 9:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + 10:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + 11:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + 12:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** embedded.connectivity.solutions=============== + 13:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 14:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Description: LoRa MAC region EU868 implementation + 15:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 16:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 17:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 18:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) + 19:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** */ + 20:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include + 21:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include + 22:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include + 23:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include + 24:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 25:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "radio.h" + 26:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "timer.h" + 27:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "LoRaMac.h" + 28:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 29:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "utilities.h" + 30:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 31:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "Region.h" + 32:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "RegionCommon.h" + 33:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "RegionEU868.h" + 34:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #include "debug.h" + ARM GAS /tmp/cczfoKrY.s page 2 + + + 35:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 36:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Definitions + 37:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** #define CHANNELS_MASK_SIZE 1 + 38:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 39:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Global attributes + 40:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** /*! + 41:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** * LoRaMAC channels + 42:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** */ + 43:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static ChannelParams_t Channels[EU868_MAX_NB_CHANNELS]; + 44:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 45:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** /*! + 46:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** * LoRaMac bands + 47:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** */ + 48:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static Band_t Bands[EU868_MAX_NB_BANDS] = + 49:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 50:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** EU868_BAND0, + 51:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** EU868_BAND1, + 52:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** EU868_BAND2, + 53:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** EU868_BAND3, + 54:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** EU868_BAND4, + 55:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** }; + 56:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 57:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** /*! + 58:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** * LoRaMac channels mask + 59:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** */ + 60:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + 61:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 62:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** /*! + 63:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** * LoRaMac channels default mask + 64:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** */ + 65:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + 66:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 67:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Static functions + 68:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) + 69:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 70:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t nextLowerDr = 0; + 71:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 72:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( dr == minDr ) + 73:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 74:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextLowerDr = minDr; + 75:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 76:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 77:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 78:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextLowerDr = dr - 1; + 79:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 80:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return nextLowerDr; + 81:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 82:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 83:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static uint32_t GetBandwidth( uint32_t drIndex ) + 84:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 85:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( BandwidthsEU868[drIndex] ) + 86:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 87:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 88:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 125000: + 89:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return 0; + 90:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 250000: + 91:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return 1; + ARM GAS /tmp/cczfoKrY.s page 3 + + + 92:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 500000: + 93:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return 2; + 94:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 95:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 96:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 97:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* chann + 98:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 99:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t txPowerResult = txPower; + 100:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 101:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Limit tx power to the band max + 102:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** txPowerResult = MAX( txPower, maxBandTxPower ); + 103:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 104:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return txPowerResult; + 105:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 106:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 107:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static bool VerifyTxFreq( uint32_t freq, uint8_t *band ) + 108:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 25 .loc 1 108 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 70B5 push {r4, r5, r6, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 16 + 33 .cfi_offset 4, -16 + 34 .cfi_offset 5, -12 + 35 .cfi_offset 6, -8 + 36 .cfi_offset 14, -4 + 37 0002 0400 movs r4, r0 + 38 0004 0D00 movs r5, r1 + 109:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Check radio driver support + 110:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Radio.CheckRfFrequency( freq ) == false ) + 39 .loc 1 110 0 + 40 0006 1C4B ldr r3, .L14 + 41 0008 9B6A ldr r3, [r3, #40] + 42 000a 9847 blx r3 + 43 .LVL1: + 44 000c 0028 cmp r0, #0 + 45 000e 23D0 beq .L2 + 111:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 112:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 113:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 114:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 115:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Check frequency bands + 116:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( freq >= 863000000 ) && ( freq < 865000000 ) ) + 46 .loc 1 116 0 + 47 0010 1A4A ldr r2, .L14+4 + 48 0012 1B4B ldr r3, .L14+8 + 49 0014 E318 adds r3, r4, r3 + 50 0016 9342 cmp r3, r2 + 51 0018 1CD9 bls .L9 + 117:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 118:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 2; + 119:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 120:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( freq >= 865000000 ) && ( freq <= 868000000 ) ) + 52 .loc 1 120 0 + ARM GAS /tmp/cczfoKrY.s page 4 + + + 53 001a 1A4A ldr r2, .L14+12 + 54 001c 1A4B ldr r3, .L14+16 + 55 001e E318 adds r3, r4, r3 + 56 0020 9342 cmp r3, r2 + 57 0022 1AD9 bls .L10 + 121:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 122:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 0; + 123:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 124:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( freq > 868000000 ) && ( freq <= 868600000 ) ) + 58 .loc 1 124 0 + 59 0024 194A ldr r2, .L14+20 + 60 0026 1A4B ldr r3, .L14+24 + 61 0028 E318 adds r3, r4, r3 + 62 002a 9342 cmp r3, r2 + 63 002c 18D9 bls .L11 + 125:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 126:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 1; + 127:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 128:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( freq >= 868700000 ) && ( freq <= 869200000 ) ) + 64 .loc 1 128 0 + 65 002e 194A ldr r2, .L14+28 + 66 0030 194B ldr r3, .L14+32 + 67 0032 E318 adds r3, r4, r3 + 68 0034 9342 cmp r3, r2 + 69 0036 16D9 bls .L12 + 129:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 130:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 2; + 131:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 132:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( freq >= 869400000 ) && ( freq <= 869650000 ) ) + 70 .loc 1 132 0 + 71 0038 184A ldr r2, .L14+36 + 72 003a 194B ldr r3, .L14+40 + 73 003c E318 adds r3, r4, r3 + 74 003e 9342 cmp r3, r2 + 75 0040 14D9 bls .L13 + 133:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 134:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 3; + 135:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 136:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( freq >= 869700000 ) && ( freq <= 870000000 ) ) + 76 .loc 1 136 0 + 77 0042 184B ldr r3, .L14+44 + 78 0044 9C46 mov ip, r3 + 79 0046 6444 add r4, r4, ip + 80 .LVL2: + 81 0048 174B ldr r3, .L14+48 + 82 004a 9C42 cmp r4, r3 + 83 004c 11D8 bhi .L8 + 137:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 138:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *band = 4; + 84 .loc 1 138 0 + 85 004e 0423 movs r3, #4 + 86 0050 2B70 strb r3, [r5] + 87 0052 01E0 b .L2 + 88 .LVL3: + 89 .L9: + 118:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 90 .loc 1 118 0 + ARM GAS /tmp/cczfoKrY.s page 5 + + + 91 0054 0223 movs r3, #2 + 92 0056 2B70 strb r3, [r5] + 93 .LVL4: + 94 .L2: + 139:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 140:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 141:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 142:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 143:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 144:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 145:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 95 .loc 1 145 0 + 96 @ sp needed + 97 .LVL5: + 98 0058 70BD pop {r4, r5, r6, pc} + 99 .LVL6: + 100 .L10: + 122:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 101 .loc 1 122 0 + 102 005a 0023 movs r3, #0 + 103 005c 2B70 strb r3, [r5] + 104 005e FBE7 b .L2 + 105 .L11: + 126:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 106 .loc 1 126 0 + 107 0060 0123 movs r3, #1 + 108 0062 2B70 strb r3, [r5] + 109 0064 F8E7 b .L2 + 110 .L12: + 130:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 111 .loc 1 130 0 + 112 0066 0223 movs r3, #2 + 113 0068 2B70 strb r3, [r5] + 114 006a F5E7 b .L2 + 115 .L13: + 134:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 116 .loc 1 134 0 + 117 006c 0323 movs r3, #3 + 118 006e 2B70 strb r3, [r5] + 119 0070 F2E7 b .L2 + 120 .LVL7: + 121 .L8: + 142:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 122 .loc 1 142 0 + 123 0072 0020 movs r0, #0 + 124 0074 F0E7 b .L2 + 125 .L15: + 126 0076 C046 .align 2 + 127 .L14: + 128 0078 00000000 .word Radio + 129 007c 7F841E00 .word 1999999 + 130 0080 40AA8FCC .word -863000000 + 131 0084 C0C62D00 .word 3000000 + 132 0088 C02571CC .word -865000000 + 133 008c BF270900 .word 599999 + 134 0090 FF5E43CC .word -868000001 + 135 0094 20A10700 .word 500000 + ARM GAS /tmp/cczfoKrY.s page 6 + + + 136 0098 A0B038CC .word -868700000 + 137 009c 90D00300 .word 250000 + 138 00a0 40022ECC .word -869400000 + 139 00a4 606E29CC .word -869700000 + 140 00a8 E0930400 .word 300000 + 141 .cfi_endproc + 142 .LFE88: + 144 .section .text.RegionEU868GetPhyParam,"ax",%progbits + 145 .align 1 + 146 .global RegionEU868GetPhyParam + 147 .syntax unified + 148 .code 16 + 149 .thumb_func + 150 .fpu softvfp + 152 RegionEU868GetPhyParam: + 153 .LFB90: + 146:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 147:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, Cha + 148:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 149:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t nbEnabledChannels = 0; + 150:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t delayTransmission = 0; + 151:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 152:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** for( uint8_t i = 0, k = 0; i < EU868_MAX_NB_CHANNELS; i += 16, k++ ) + 153:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 154:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** for( uint8_t j = 0; j < 16; j++ ) + 155:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 156:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + 157:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 158:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( channels[i + j].Frequency == 0 ) + 159:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the channel is enabled + 160:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** continue; + 161:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 162:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( joined == false ) + 163:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 164:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( EU868_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + 165:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 166:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** continue; + 167:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 168:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + 170:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channels[i + j].DrRange.Fields.Max ) == false ) + 171:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the current channel selection supports the given datarate + 172:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** continue; + 173:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 174:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( bands[channels[i + j].Band].TimeOff > 0 ) + 175:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the band is available for transmission + 176:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** delayTransmission++; + 177:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** continue; + 178:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 179:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** enabledChannels[nbEnabledChannels++] = i + j; + 180:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 181:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 182:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 183:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 184:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *delayTx = delayTransmission; + 185:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return nbEnabledChannels; + 186:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 7 + + + 187:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 188:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** PhyParam_t RegionEU868GetPhyParam( GetPhyParams_t* getPhy ) + 189:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 154 .loc 1 189 0 + 155 .cfi_startproc + 156 @ args = 0, pretend = 0, frame = 0 + 157 @ frame_needed = 0, uses_anonymous_args = 0 + 158 .LVL8: + 159 0000 10B5 push {r4, lr} + 160 .LCFI1: + 161 .cfi_def_cfa_offset 8 + 162 .cfi_offset 4, -8 + 163 .cfi_offset 14, -4 + 164 0002 0200 movs r2, r0 + 190:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** PhyParam_t phyParam = { 0 }; + 165 .loc 1 190 0 + 166 0004 0020 movs r0, #0 + 167 .LVL9: + 191:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 192:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( getPhy->Attribute ) + 168 .loc 1 192 0 + 169 0006 1378 ldrb r3, [r2] + 170 0008 093B subs r3, r3, #9 + 171 000a D9B2 uxtb r1, r3 + 172 000c 1729 cmp r1, #23 + 173 000e 0BD8 bhi .L17 + 174 0010 8B00 lsls r3, r1, #2 + 175 0012 2249 ldr r1, .L40 + 176 0014 CB58 ldr r3, [r1, r3] + 177 0016 9F46 mov pc, r3 + 178 .section .rodata.RegionEU868GetPhyParam,"a",%progbits + 179 .align 2 + 180 .L19: + 181 0000 2E000000 .word .L18 + 182 0004 38000000 .word .L20 + 183 0008 42000000 .word .L21 + 184 000c 46000000 .word .L22 + 185 0010 4A000000 .word .L23 + 186 0014 50000000 .word .L24 + 187 0018 56000000 .word .L25 + 188 001c 5A000000 .word .L26 + 189 0020 5E000000 .word .L27 + 190 0024 64000000 .word .L28 + 191 0028 28000000 .word .L17 + 192 002c 78000000 .word .L29 + 193 0030 28000000 .word .L17 + 194 0034 7C000000 .word .L30 + 195 0038 80000000 .word .L31 + 196 003c 84000000 .word .L32 + 197 0040 88000000 .word .L33 + 198 0044 28000000 .word .L17 + 199 0048 28000000 .word .L17 + 200 004c 8C000000 .word .L34 + 201 0050 92000000 .word .L35 + 202 0054 96000000 .word .L36 + 203 0058 96000000 .word .L36 + 204 005c 18000000 .word .L37 + ARM GAS /tmp/cczfoKrY.s page 8 + + + 205 .section .text.RegionEU868GetPhyParam + 206 .L37: + 193:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 194:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MIN_RX_DR: + 195:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 196:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_RX_MIN_DATARATE; + 197:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 198:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 199:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MIN_TX_DR: + 200:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 201:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_TX_MIN_DATARATE; + 202:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 203:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 204:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_TX_DR: + 205:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 206:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_DEFAULT_DATARATE; + 207:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 208:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 209:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_NEXT_LOWER_TX_DR: + 210:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 211:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, EU868_TX_MIN_DATARATE ); + 207 .loc 1 211 0 + 208 0018 0120 movs r0, #1 + 209 001a 1056 ldrsb r0, [r2, r0] + 210 .LVL10: + 211 .LBB14: + 212 .LBB15: + 72:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 213 .loc 1 72 0 + 214 001c 0028 cmp r0, #0 + 215 001e 04D0 beq .L39 + 78:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 216 .loc 1 78 0 + 217 0020 C0B2 uxtb r0, r0 + 218 0022 0138 subs r0, r0, #1 + 219 .LVL11: + 220 0024 C0B2 uxtb r0, r0 + 221 .LVL12: + 222 .L38: + 223 .LBE15: + 224 .LBE14: + 225 .loc 1 211 0 + 226 0026 40B2 sxtb r0, r0 + 227 .LVL13: + 228 .L17: + 212:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 213:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 214:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_TX_POWER: + 215:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 216:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_DEFAULT_TX_POWER; + 217:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 218:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 219:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MAX_PAYLOAD: + 220:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 221:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = MaxPayloadOfDatarateEU868[getPhy->Datarate]; + 222:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 223:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 9 + + + 224:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MAX_PAYLOAD_REPEATER: + 225:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 226:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = MaxPayloadOfDatarateRepeaterEU868[getPhy->Datarate]; + 227:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 228:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 229:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DUTY_CYCLE: + 230:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 231:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_DUTY_CYCLE_ENABLED; + 232:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 233:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 234:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MAX_RX_WINDOW: + 235:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 236:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_MAX_RX_WINDOW; + 237:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 238:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 239:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_RECEIVE_DELAY1: + 240:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 241:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_RECEIVE_DELAY1; + 242:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 243:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 244:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_RECEIVE_DELAY2: + 245:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 246:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_RECEIVE_DELAY2; + 247:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 248:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 249:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_JOIN_ACCEPT_DELAY1: + 250:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 251:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_JOIN_ACCEPT_DELAY1; + 252:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 253:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 254:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_JOIN_ACCEPT_DELAY2: + 255:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 256:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_JOIN_ACCEPT_DELAY2; + 257:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 258:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 259:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MAX_FCNT_GAP: + 260:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 261:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_MAX_FCNT_GAP; + 262:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 263:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 264:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_ACK_TIMEOUT: + 265:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 266:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = ( EU868_ACKTIMEOUT + randr( -EU868_ACK_TIMEOUT_RND, EU868_ACK_TIMEOUT_ + 267:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 268:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 269:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_DR1_OFFSET: + 270:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 271:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_DEFAULT_RX1_DR_OFFSET; + 272:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 273:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 274:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_RX2_FREQUENCY: + 275:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 276:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_RX_WND_2_FREQ; + 277:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 278:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 279:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_RX2_DR: + 280:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + ARM GAS /tmp/cczfoKrY.s page 10 + + + 281:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_RX_WND_2_DR; + 282:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 283:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 284:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_CHANNELS_MASK: + 285:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 286:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.ChannelsMask = ChannelsMask; + 287:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 288:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 289:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_CHANNELS_DEFAULT_MASK: + 290:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 291:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.ChannelsMask = ChannelsDefaultMask; + 292:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 293:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 294:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_MAX_NB_CHANNELS: + 295:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 296:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = EU868_MAX_NB_CHANNELS; + 297:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 298:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 299:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_CHANNELS: + 300:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 301:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Channels = Channels; + 302:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 303:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 304:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_UPLINK_DWELL_TIME: + 305:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_DOWNLINK_DWELL_TIME: + 306:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 307:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = 0; + 308:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 309:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 310:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_MAX_EIRP: + 311:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 312:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.fValue = EU868_DEFAULT_MAX_EIRP; + 313:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 314:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 315:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_ANTENNA_GAIN: + 316:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 317:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.fValue = EU868_DEFAULT_ANTENNA_GAIN; + 318:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 319:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 320:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_NB_JOIN_TRIALS: + 321:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_NB_JOIN_TRIALS: + 322:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 323:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam.Value = 48; + 324:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 325:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 326:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 327:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 328:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 329:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 330:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 331:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 332:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return phyParam; + 333:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 229 .loc 1 333 0 + 230 @ sp needed + 231 0028 10BD pop {r4, pc} + 232 .LVL14: + ARM GAS /tmp/cczfoKrY.s page 11 + + + 233 .L39: + 234 .LBB17: + 235 .LBB16: + 74:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 236 .loc 1 74 0 + 237 002a 0020 movs r0, #0 + 238 .LVL15: + 239 002c FBE7 b .L38 + 240 .LVL16: + 241 .L18: + 242 .LBE16: + 243 .LBE17: + 221:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 244 .loc 1 221 0 + 245 002e 0123 movs r3, #1 + 246 0030 D356 ldrsb r3, [r2, r3] + 247 0032 1B4A ldr r2, .L40+4 + 248 .LVL17: + 249 0034 D05C ldrb r0, [r2, r3] + 222:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 250 .loc 1 222 0 + 251 0036 F7E7 b .L17 + 252 .LVL18: + 253 .L20: + 226:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 254 .loc 1 226 0 + 255 0038 0123 movs r3, #1 + 256 003a D356 ldrsb r3, [r2, r3] + 257 003c 194A ldr r2, .L40+8 + 258 .LVL19: + 259 003e D05C ldrb r0, [r2, r3] + 227:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 260 .loc 1 227 0 + 261 0040 F2E7 b .L17 + 262 .LVL20: + 263 .L21: + 231:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 264 .loc 1 231 0 + 265 0042 0120 movs r0, #1 + 232:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 266 .loc 1 232 0 + 267 0044 F0E7 b .L17 + 268 .L22: + 236:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 269 .loc 1 236 0 + 270 0046 1848 ldr r0, .L40+12 + 237:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 271 .loc 1 237 0 + 272 0048 EEE7 b .L17 + 273 .L23: + 241:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 274 .loc 1 241 0 + 275 004a FA20 movs r0, #250 + 276 .LVL21: + 277 004c 8000 lsls r0, r0, #2 + 278 .LVL22: + 242:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 12 + + + 279 .loc 1 242 0 + 280 004e EBE7 b .L17 + 281 .L24: + 246:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 282 .loc 1 246 0 + 283 0050 FA20 movs r0, #250 + 284 .LVL23: + 285 0052 C000 lsls r0, r0, #3 + 286 .LVL24: + 247:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 287 .loc 1 247 0 + 288 0054 E8E7 b .L17 + 289 .L25: + 251:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 290 .loc 1 251 0 + 291 0056 1548 ldr r0, .L40+16 + 252:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 292 .loc 1 252 0 + 293 0058 E6E7 b .L17 + 294 .L26: + 256:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 295 .loc 1 256 0 + 296 005a 1548 ldr r0, .L40+20 + 257:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 297 .loc 1 257 0 + 298 005c E4E7 b .L17 + 299 .L27: + 261:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 300 .loc 1 261 0 + 301 005e 8020 movs r0, #128 + 302 .LVL25: + 303 0060 C001 lsls r0, r0, #7 + 304 .LVL26: + 262:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 305 .loc 1 262 0 + 306 0062 E1E7 b .L17 + 307 .L28: + 266:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 308 .loc 1 266 0 + 309 0064 FA21 movs r1, #250 + 310 0066 8900 lsls r1, r1, #2 + 311 0068 1248 ldr r0, .L40+24 + 312 006a FFF7FEFF bl randr + 313 .LVL27: + 314 006e FA23 movs r3, #250 + 315 0070 DB00 lsls r3, r3, #3 + 316 0072 9C46 mov ip, r3 + 317 0074 6044 add r0, r0, ip + 267:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 318 .loc 1 267 0 + 319 0076 D7E7 b .L17 + 320 .LVL28: + 321 .L29: + 276:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 322 .loc 1 276 0 + 323 0078 0F48 ldr r0, .L40+28 + 277:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 13 + + + 324 .loc 1 277 0 + 325 007a D5E7 b .L17 + 326 .L30: + 286:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 327 .loc 1 286 0 + 328 007c 0F48 ldr r0, .L40+32 + 287:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 329 .loc 1 287 0 + 330 007e D3E7 b .L17 + 331 .L31: + 291:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 332 .loc 1 291 0 + 333 0080 0F48 ldr r0, .L40+36 + 292:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 334 .loc 1 292 0 + 335 0082 D1E7 b .L17 + 336 .L32: + 296:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 337 .loc 1 296 0 + 338 0084 1020 movs r0, #16 + 297:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 339 .loc 1 297 0 + 340 0086 CFE7 b .L17 + 341 .L33: + 301:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 342 .loc 1 301 0 + 343 0088 0E48 ldr r0, .L40+40 + 302:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 344 .loc 1 302 0 + 345 008a CDE7 b .L17 + 346 .L34: + 312:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 347 .loc 1 312 0 + 348 008c 8320 movs r0, #131 + 349 .LVL29: + 350 008e C005 lsls r0, r0, #23 + 351 .LVL30: + 313:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 352 .loc 1 313 0 + 353 0090 CAE7 b .L17 + 354 .L35: + 317:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 355 .loc 1 317 0 + 356 0092 0D48 ldr r0, .L40+44 + 318:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 357 .loc 1 318 0 + 358 0094 C8E7 b .L17 + 359 .L36: + 323:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 360 .loc 1 323 0 + 361 0096 3020 movs r0, #48 + 324:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 362 .loc 1 324 0 + 363 0098 C6E7 b .L17 + 364 .L41: + 365 009a C046 .align 2 + 366 .L40: + ARM GAS /tmp/cczfoKrY.s page 14 + + + 367 009c 00000000 .word .L19 + 368 00a0 00000000 .word .LANCHOR0 + 369 00a4 00000000 .word .LANCHOR1 + 370 00a8 B80B0000 .word 3000 + 371 00ac 88130000 .word 5000 + 372 00b0 70170000 .word 6000 + 373 00b4 18FCFFFF .word -1000 + 374 00b8 08E6D333 .word 869525000 + 375 00bc 00000000 .word .LANCHOR2 + 376 00c0 00000000 .word .LANCHOR3 + 377 00c4 00000000 .word Channels + 378 00c8 9A990940 .word 1074370970 + 379 .cfi_endproc + 380 .LFE90: + 382 .section .text.RegionEU868SetBandTxDone,"ax",%progbits + 383 .align 1 + 384 .global RegionEU868SetBandTxDone + 385 .syntax unified + 386 .code 16 + 387 .thumb_func + 388 .fpu softvfp + 390 RegionEU868SetBandTxDone: + 391 .LFB91: + 334:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 335:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868SetBandTxDone( SetBandTxDoneParams_t* txDone ) + 336:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 392 .loc 1 336 0 + 393 .cfi_startproc + 394 @ args = 0, pretend = 0, frame = 0 + 395 @ frame_needed = 0, uses_anonymous_args = 0 + 396 .LVL31: + 397 0000 10B5 push {r4, lr} + 398 .LCFI2: + 399 .cfi_def_cfa_offset 8 + 400 .cfi_offset 4, -8 + 401 .cfi_offset 14, -4 + 337:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->Last + 402 .loc 1 337 0 + 403 0002 0278 ldrb r2, [r0] + 404 0004 5300 lsls r3, r2, #1 + 405 0006 9B18 adds r3, r3, r2 + 406 0008 9A00 lsls r2, r3, #2 + 407 000a 054B ldr r3, .L43 + 408 000c 9B18 adds r3, r3, r2 + 409 000e 5B7A ldrb r3, [r3, #9] + 410 0010 4268 ldr r2, [r0, #4] + 411 0012 1B01 lsls r3, r3, #4 + 412 0014 0349 ldr r1, .L43+4 + 413 0016 C918 adds r1, r1, r3 + 414 0018 4078 ldrb r0, [r0, #1] + 415 .LVL32: + 416 001a FFF7FEFF bl RegionCommonSetBandTxDone + 417 .LVL33: + 338:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 418 .loc 1 338 0 + 419 @ sp needed + 420 001e 10BD pop {r4, pc} + ARM GAS /tmp/cczfoKrY.s page 15 + + + 421 .L44: + 422 .align 2 + 423 .L43: + 424 0020 00000000 .word Channels + 425 0024 00000000 .word .LANCHOR4 + 426 .cfi_endproc + 427 .LFE91: + 429 .section .text.RegionEU868InitDefaults,"ax",%progbits + 430 .align 1 + 431 .global RegionEU868InitDefaults + 432 .syntax unified + 433 .code 16 + 434 .thumb_func + 435 .fpu softvfp + 437 RegionEU868InitDefaults: + 438 .LFB92: + 339:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 340:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868InitDefaults( InitType_t type ) + 341:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 439 .loc 1 341 0 + 440 .cfi_startproc + 441 @ args = 0, pretend = 0, frame = 0 + 442 @ frame_needed = 0, uses_anonymous_args = 0 + 443 .LVL34: + 444 0000 70B5 push {r4, r5, r6, lr} + 445 .LCFI3: + 446 .cfi_def_cfa_offset 16 + 447 .cfi_offset 4, -16 + 448 .cfi_offset 5, -12 + 449 .cfi_offset 6, -8 + 450 .cfi_offset 14, -4 + 342:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( type ) + 451 .loc 1 342 0 + 452 0002 0028 cmp r0, #0 + 453 0004 02D0 beq .L47 + 454 0006 0128 cmp r0, #1 + 455 0008 14D0 beq .L48 + 456 .LVL35: + 457 .L45: + 343:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 344:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case INIT_TYPE_INIT: + 345:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 346:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Channels + 347:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[0] = ( ChannelParams_t ) EU868_LC1; + 348:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[1] = ( ChannelParams_t ) EU868_LC2; + 349:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[2] = ( ChannelParams_t ) EU868_LC3; + 350:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 351:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Initialize the channels default mask + 352:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + 353:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update the channels mask + 354:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + 355:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 356:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 357:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case INIT_TYPE_RESTORE: + 358:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 359:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Restore channels default mask + 360:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] |= ChannelsDefaultMask[0]; + ARM GAS /tmp/cczfoKrY.s page 16 + + + 361:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 362:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 363:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 364:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 365:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 366:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 367:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 368:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 458 .loc 1 368 0 + 459 @ sp needed + 460 000a 70BD pop {r4, r5, r6, pc} + 461 .LVL36: + 462 .L47: + 347:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[1] = ( ChannelParams_t ) EU868_LC2; + 463 .loc 1 347 0 + 464 000c 0D4B ldr r3, .L49 + 465 000e 0E4A ldr r2, .L49+4 + 466 0010 1800 movs r0, r3 + 467 .LVL37: + 468 0012 1100 movs r1, r2 + 469 0014 70C9 ldmia r1!, {r4, r5, r6} + 470 0016 70C0 stmia r0!, {r4, r5, r6} + 348:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[2] = ( ChannelParams_t ) EU868_LC3; + 471 .loc 1 348 0 + 472 0018 70C9 ldmia r1!, {r4, r5, r6} + 473 001a 70C0 stmia r0!, {r4, r5, r6} + 349:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 474 .loc 1 349 0 + 475 001c 1833 adds r3, r3, #24 + 476 001e 1832 adds r2, r2, #24 + 477 0020 13CA ldmia r2!, {r0, r1, r4} + 478 0022 13C3 stmia r3!, {r0, r1, r4} + 352:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update the channels mask + 479 .loc 1 352 0 + 480 0024 0949 ldr r1, .L49+8 + 481 0026 0723 movs r3, #7 + 482 0028 0B80 strh r3, [r1] + 354:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 483 .loc 1 354 0 + 484 002a 0122 movs r2, #1 + 485 002c 0848 ldr r0, .L49+12 + 486 002e FFF7FEFF bl RegionCommonChanMaskCopy + 487 .LVL38: + 355:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 488 .loc 1 355 0 + 489 0032 EAE7 b .L45 + 490 .LVL39: + 491 .L48: + 360:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 492 .loc 1 360 0 + 493 0034 054B ldr r3, .L49+8 + 494 0036 1B88 ldrh r3, [r3] + 495 0038 054A ldr r2, .L49+12 + 496 003a 1188 ldrh r1, [r2] + 497 003c 0B43 orrs r3, r1 + 498 003e 1380 strh r3, [r2] + 499 .loc 1 368 0 + ARM GAS /tmp/cczfoKrY.s page 17 + + + 500 0040 E3E7 b .L45 + 501 .L50: + 502 0042 C046 .align 2 + 503 .L49: + 504 0044 00000000 .word Channels + 505 0048 00000000 .word .LANCHOR5 + 506 004c 00000000 .word .LANCHOR3 + 507 0050 00000000 .word .LANCHOR2 + 508 .cfi_endproc + 509 .LFE92: + 511 .section .text.RegionEU868Verify,"ax",%progbits + 512 .align 1 + 513 .global RegionEU868Verify + 514 .syntax unified + 515 .code 16 + 516 .thumb_func + 517 .fpu softvfp + 519 RegionEU868Verify: + 520 .LFB93: + 369:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 370:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) + 371:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 521 .loc 1 371 0 + 522 .cfi_startproc + 523 @ args = 0, pretend = 0, frame = 0 + 524 @ frame_needed = 0, uses_anonymous_args = 0 + 525 .LVL40: + 526 0000 10B5 push {r4, lr} + 527 .LCFI4: + 528 .cfi_def_cfa_offset 8 + 529 .cfi_offset 4, -8 + 530 .cfi_offset 14, -4 + 372:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( phyAttribute ) + 531 .loc 1 372 0 + 532 0002 0439 subs r1, r1, #4 + 533 .LVL41: + 534 0004 CBB2 uxtb r3, r1 + 535 0006 1A2B cmp r3, #26 + 536 0008 34D8 bhi .L60 + 537 000a 9900 lsls r1, r3, #2 + 538 000c 1A4B ldr r3, .L63 + 539 000e 5B58 ldr r3, [r3, r1] + 540 0010 9F46 mov pc, r3 + 541 .section .rodata.RegionEU868Verify,"a",%progbits + 542 .align 2 + 543 .L54: + 544 0000 16000000 .word .L53 + 545 0004 2A000000 .word .L55 + 546 0008 3E000000 .word .L56 + 547 000c 52000000 .word .L57 + 548 0010 52000000 .word .L57 + 549 0014 74000000 .word .L60 + 550 0018 74000000 .word .L60 + 551 001c 12000000 .word .L58 + 552 0020 74000000 .word .L60 + 553 0024 74000000 .word .L60 + 554 0028 74000000 .word .L60 + ARM GAS /tmp/cczfoKrY.s page 18 + + + 555 002c 74000000 .word .L60 + 556 0030 74000000 .word .L60 + 557 0034 74000000 .word .L60 + 558 0038 74000000 .word .L60 + 559 003c 74000000 .word .L60 + 560 0040 74000000 .word .L60 + 561 0044 74000000 .word .L60 + 562 0048 74000000 .word .L60 + 563 004c 74000000 .word .L60 + 564 0050 74000000 .word .L60 + 565 0054 74000000 .word .L60 + 566 0058 74000000 .word .L60 + 567 005c 74000000 .word .L60 + 568 0060 74000000 .word .L60 + 569 0064 74000000 .word .L60 + 570 0068 66000000 .word .L59 + 571 .section .text.RegionEU868Verify + 572 .L58: + 373:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 374:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_TX_DR: + 375:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 376:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU868_TX_MIN_DATARATE + 377:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 378:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_TX_DR: + 379:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 380:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + 381:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 382:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_RX_DR: + 383:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 384:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU868_RX_MIN_DATARATE + 385:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 386:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DEF_TX_POWER: + 387:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_TX_POWER: + 388:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 389:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Remark: switched min and max! + 390:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return RegionCommonValueInRange( verify->TxPower, EU868_MAX_TX_POWER, EU868_MIN_TX_POWE + 391:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 392:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_DUTY_CYCLE: + 393:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 394:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return EU868_DUTY_CYCLE_ENABLED; + 573 .loc 1 394 0 + 574 0012 0120 movs r0, #1 + 575 .LVL42: + 576 .L52: + 395:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 396:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case PHY_NB_JOIN_TRIALS: + 397:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 398:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( verify->NbJoinTrials < 48 ) + 399:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 400:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 401:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 402:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 403:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 404:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 405:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 406:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 407:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + ARM GAS /tmp/cczfoKrY.s page 19 + + + 408:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 577 .loc 1 408 0 + 578 @ sp needed + 579 0014 10BD pop {r4, pc} + 580 .LVL43: + 581 .L53: + 376:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 582 .loc 1 376 0 + 583 0016 0078 ldrb r0, [r0] + 584 .LVL44: + 585 0018 40B2 sxtb r0, r0 + 586 001a 0722 movs r2, #7 + 587 001c 0021 movs r1, #0 + 588 001e FFF7FEFF bl RegionCommonValueInRange + 589 .LVL45: + 590 0022 431E subs r3, r0, #1 + 591 0024 9841 sbcs r0, r0, r3 + 592 0026 C0B2 uxtb r0, r0 + 593 0028 F4E7 b .L52 + 594 .LVL46: + 595 .L55: + 380:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 596 .loc 1 380 0 + 597 002a 0078 ldrb r0, [r0] + 598 .LVL47: + 599 002c 40B2 sxtb r0, r0 + 600 002e 0522 movs r2, #5 + 601 0030 0021 movs r1, #0 + 602 0032 FFF7FEFF bl RegionCommonValueInRange + 603 .LVL48: + 604 0036 431E subs r3, r0, #1 + 605 0038 9841 sbcs r0, r0, r3 + 606 003a C0B2 uxtb r0, r0 + 607 003c EAE7 b .L52 + 608 .LVL49: + 609 .L56: + 384:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 610 .loc 1 384 0 + 611 003e 0078 ldrb r0, [r0] + 612 .LVL50: + 613 0040 40B2 sxtb r0, r0 + 614 0042 0722 movs r2, #7 + 615 0044 0021 movs r1, #0 + 616 0046 FFF7FEFF bl RegionCommonValueInRange + 617 .LVL51: + 618 004a 431E subs r3, r0, #1 + 619 004c 9841 sbcs r0, r0, r3 + 620 004e C0B2 uxtb r0, r0 + 621 0050 E0E7 b .L52 + 622 .LVL52: + 623 .L57: + 390:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 624 .loc 1 390 0 + 625 0052 0078 ldrb r0, [r0] + 626 .LVL53: + 627 0054 40B2 sxtb r0, r0 + 628 0056 0722 movs r2, #7 + ARM GAS /tmp/cczfoKrY.s page 20 + + + 629 0058 0021 movs r1, #0 + 630 005a FFF7FEFF bl RegionCommonValueInRange + 631 .LVL54: + 632 005e 431E subs r3, r0, #1 + 633 0060 9841 sbcs r0, r0, r3 + 634 0062 C0B2 uxtb r0, r0 + 635 0064 D6E7 b .L52 + 636 .LVL55: + 637 .L59: + 398:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 638 .loc 1 398 0 + 639 0066 0378 ldrb r3, [r0] + 640 0068 2F2B cmp r3, #47 + 641 006a 01D9 bls .L62 + 407:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 642 .loc 1 407 0 + 643 006c 0120 movs r0, #1 + 644 .LVL56: + 645 006e D1E7 b .L52 + 646 .LVL57: + 647 .L62: + 400:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 648 .loc 1 400 0 + 649 0070 0020 movs r0, #0 + 650 .LVL58: + 651 0072 CFE7 b .L52 + 652 .LVL59: + 653 .L60: + 405:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 654 .loc 1 405 0 + 655 0074 0020 movs r0, #0 + 656 .LVL60: + 657 0076 CDE7 b .L52 + 658 .L64: + 659 .align 2 + 660 .L63: + 661 0078 00000000 .word .L54 + 662 .cfi_endproc + 663 .LFE93: + 665 .section .text.RegionEU868ChanMaskSet,"ax",%progbits + 666 .align 1 + 667 .global RegionEU868ChanMaskSet + 668 .syntax unified + 669 .code 16 + 670 .thumb_func + 671 .fpu softvfp + 673 RegionEU868ChanMaskSet: + 674 .LFB95: + 409:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 410:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868ApplyCFList( ApplyCFListParams_t* applyCFList ) + 411:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 412:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelParams_t newChannel; + 413:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelAddParams_t channelAdd; + 414:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelRemoveParams_t channelRemove; + 415:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 416:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Setup default datarate range + 417:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + ARM GAS /tmp/cczfoKrY.s page 21 + + + 418:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 419:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Size of the optional CF list + 420:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( applyCFList->Size != 16 ) + 421:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 422:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return; + 423:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 424:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 425:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Last byte is RFU, don't take it into account + 426:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** for( uint8_t i = 0, chanIdx = EU868_NUMB_DEFAULT_CHANNELS; chanIdx < EU868_MAX_NB_CHANNELS; i+= + 427:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 428:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( chanIdx < ( EU868_NUMB_CHANNELS_CF_LIST + EU868_NUMB_DEFAULT_CHANNELS ) ) + 429:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 430:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Channel frequency + 431:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + 432:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + 433:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + 434:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency *= 100; + 435:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 436:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Initialize alternative frequency to 0 + 437:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Rx1Frequency = 0; + 438:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 439:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 440:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 441:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency = 0; + 442:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.DrRange.Value = 0; + 443:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Rx1Frequency = 0; + 444:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 445:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 446:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( newChannel.Frequency != 0 ) + 447:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 448:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.NewChannel = &newChannel; + 449:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.ChannelId = chanIdx; + 450:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 451:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Try to add all channels + 452:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionEU868ChannelAdd( &channelAdd ); + 453:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 454:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 455:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 456:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelRemove.ChannelId = chanIdx; + 457:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 458:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionEU868ChannelsRemove( &channelRemove ); + 459:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 460:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 461:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 462:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 463:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) + 464:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 675 .loc 1 464 0 + 676 .cfi_startproc + 677 @ args = 0, pretend = 0, frame = 0 + 678 @ frame_needed = 0, uses_anonymous_args = 0 + 679 .LVL61: + 680 0000 10B5 push {r4, lr} + 681 .LCFI5: + 682 .cfi_def_cfa_offset 8 + 683 .cfi_offset 4, -8 + 684 .cfi_offset 14, -4 + ARM GAS /tmp/cczfoKrY.s page 22 + + + 465:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( chanMaskSet->ChannelsMaskType ) + 685 .loc 1 465 0 + 686 0002 0379 ldrb r3, [r0, #4] + 687 0004 002B cmp r3, #0 + 688 0006 03D0 beq .L67 + 689 0008 012B cmp r3, #1 + 690 000a 08D0 beq .L68 + 466:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 467:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case CHANNELS_MASK: + 468:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 469:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + 470:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 471:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 472:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case CHANNELS_DEFAULT_MASK: + 473:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 474:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + 475:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 476:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 477:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 478:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 691 .loc 1 478 0 + 692 000c 0020 movs r0, #0 + 693 .LVL62: + 694 000e 05E0 b .L66 + 695 .LVL63: + 696 .L67: + 469:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 697 .loc 1 469 0 + 698 0010 0168 ldr r1, [r0] + 699 0012 0122 movs r2, #1 + 700 0014 0548 ldr r0, .L71 + 701 .LVL64: + 702 0016 FFF7FEFF bl RegionCommonChanMaskCopy + 703 .LVL65: + 479:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 480:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 704 .loc 1 480 0 + 705 001a 0120 movs r0, #1 + 706 .L66: + 481:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 707 .loc 1 481 0 + 708 @ sp needed + 709 001c 10BD pop {r4, pc} + 710 .LVL66: + 711 .L68: + 474:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 712 .loc 1 474 0 + 713 001e 0168 ldr r1, [r0] + 714 0020 0122 movs r2, #1 + 715 0022 0348 ldr r0, .L71+4 + 716 .LVL67: + 717 0024 FFF7FEFF bl RegionCommonChanMaskCopy + 718 .LVL68: + 480:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 719 .loc 1 480 0 + 720 0028 0120 movs r0, #1 + 475:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 23 + + + 721 .loc 1 475 0 + 722 002a F7E7 b .L66 + 723 .L72: + 724 .align 2 + 725 .L71: + 726 002c 00000000 .word .LANCHOR2 + 727 0030 00000000 .word .LANCHOR3 + 728 .cfi_endproc + 729 .LFE95: + 731 .section .text.RegionEU868AdrNext,"ax",%progbits + 732 .align 1 + 733 .global RegionEU868AdrNext + 734 .syntax unified + 735 .code 16 + 736 .thumb_func + 737 .fpu softvfp + 739 RegionEU868AdrNext: + 740 .LFB96: + 482:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 483:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAc + 484:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 741 .loc 1 484 0 + 742 .cfi_startproc + 743 @ args = 0, pretend = 0, frame = 8 + 744 @ frame_needed = 0, uses_anonymous_args = 0 + 745 .LVL69: + 746 0000 F0B5 push {r4, r5, r6, r7, lr} + 747 .LCFI6: + 748 .cfi_def_cfa_offset 20 + 749 .cfi_offset 4, -20 + 750 .cfi_offset 5, -16 + 751 .cfi_offset 6, -12 + 752 .cfi_offset 7, -8 + 753 .cfi_offset 14, -4 + 754 0002 C646 mov lr, r8 + 755 0004 00B5 push {lr} + 756 .LCFI7: + 757 .cfi_def_cfa_offset 24 + 758 .cfi_offset 8, -24 + 759 0006 82B0 sub sp, sp, #8 + 760 .LCFI8: + 761 .cfi_def_cfa_offset 32 + 762 0008 0400 movs r4, r0 + 763 000a 8846 mov r8, r1 + 764 000c 1700 movs r7, r2 + 765 .LVL70: + 485:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool adrAckReq = false; + 486:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t datarate = adrNext->Datarate; + 766 .loc 1 486 0 + 767 000e 0822 movs r2, #8 + 768 .LVL71: + 769 0010 8256 ldrsb r2, [r0, r2] + 770 .LVL72: + 487:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t txPower = adrNext->TxPower; + 771 .loc 1 487 0 + 772 0012 0926 movs r6, #9 + 773 0014 8657 ldrsb r6, [r0, r6] + ARM GAS /tmp/cczfoKrY.s page 24 + + + 774 .LVL73: + 488:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** GetPhyParams_t getPhy; + 489:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** PhyParam_t phyParam; + 490:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 491:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Report back the adr ack counter + 492:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *adrAckCounter = adrNext->AdrAckCounter; + 775 .loc 1 492 0 + 776 0016 4168 ldr r1, [r0, #4] + 777 .LVL74: + 778 0018 1960 str r1, [r3] + 493:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 494:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( adrNext->AdrEnabled == true ) + 779 .loc 1 494 0 + 780 001a 4578 ldrb r5, [r0, #1] + 781 001c 002D cmp r5, #0 + 782 001e 23D0 beq .L74 + 495:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 496:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( datarate == EU868_TX_MIN_DATARATE ) + 783 .loc 1 496 0 + 784 0020 002A cmp r2, #0 + 785 0022 1ED0 beq .L78 + 497:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 498:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *adrAckCounter = 0; + 499:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** adrAckReq = false; + 500:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 501:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 502:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 503:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( adrNext->AdrAckCounter >= EU868_ADR_ACK_LIMIT ) + 786 .loc 1 503 0 + 787 0024 4368 ldr r3, [r0, #4] + 788 .LVL75: + 789 0026 3F2B cmp r3, #63 + 790 0028 26D9 bls .L77 + 504:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 505:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** adrAckReq = true; + 506:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** txPower = EU868_MAX_TX_POWER; + 791 .loc 1 506 0 + 792 002a 0026 movs r6, #0 + 793 .LVL76: + 794 .L76: + 507:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 508:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 509:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 510:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** adrAckReq = false; + 511:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 512:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( adrNext->AdrAckCounter >= ( EU868_ADR_ACK_LIMIT + EU868_ADR_ACK_DELAY ) ) + 795 .loc 1 512 0 + 796 002c 5F2B cmp r3, #95 + 797 002e 1BD9 bls .L74 + 513:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 514:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( adrNext->AdrAckCounter % EU868_ADR_ACK_DELAY ) == 1 ) + 798 .loc 1 514 0 + 799 0030 1F21 movs r1, #31 + 800 0032 0B40 ands r3, r1 + 801 0034 012B cmp r3, #1 + 802 0036 17D1 bne .L74 + 515:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + ARM GAS /tmp/cczfoKrY.s page 25 + + + 516:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Decrease the datarate + 517:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + 803 .loc 1 517 0 + 804 0038 01A8 add r0, sp, #4 + 805 .LVL77: + 806 003a 1F33 adds r3, r3, #31 + 807 003c 0370 strb r3, [r0] + 518:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** getPhy.Datarate = datarate; + 808 .loc 1 518 0 + 809 003e 4270 strb r2, [r0, #1] + 519:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + 810 .loc 1 519 0 + 811 0040 A37A ldrb r3, [r4, #10] + 812 0042 8370 strb r3, [r0, #2] + 520:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam = RegionEU868GetPhyParam( &getPhy ); + 813 .loc 1 520 0 + 814 0044 FFF7FEFF bl RegionEU868GetPhyParam + 815 .LVL78: + 521:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = phyParam.Value; + 816 .loc 1 521 0 + 817 0048 42B2 sxtb r2, r0 + 818 .LVL79: + 522:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 523:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( datarate == EU868_TX_MIN_DATARATE ) + 819 .loc 1 523 0 + 820 004a 002A cmp r2, #0 + 821 004c 0CD1 bne .L74 + 822 .LVL80: + 524:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 525:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // We must set adrAckReq to false as soon as we reach the lowest datarate + 526:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** adrAckReq = false; + 527:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( adrNext->UpdateChanMask == true ) + 823 .loc 1 527 0 + 824 004e 2578 ldrb r5, [r4] + 825 0050 002D cmp r5, #0 + 826 0052 09D0 beq .L74 + 528:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 529:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Re-enable default channels + 530:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + 827 .loc 1 530 0 + 828 0054 0949 ldr r1, .L79 + 829 0056 0B88 ldrh r3, [r1] + 830 0058 0720 movs r0, #7 + 831 005a 0343 orrs r3, r0 + 832 005c 0B80 strh r3, [r1] + 526:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( adrNext->UpdateChanMask == true ) + 833 .loc 1 526 0 + 834 005e 0025 movs r5, #0 + 835 0060 02E0 b .L74 + 836 .LVL81: + 837 .L78: + 498:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** adrAckReq = false; + 838 .loc 1 498 0 + 839 0062 0021 movs r1, #0 + 840 0064 1960 str r1, [r3] + 499:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 841 .loc 1 499 0 + ARM GAS /tmp/cczfoKrY.s page 26 + + + 842 0066 0025 movs r5, #0 + 843 .LVL82: + 844 .L74: + 531:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 532:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 533:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 534:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 535:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 536:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 537:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 538:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *drOut = datarate; + 845 .loc 1 538 0 + 846 0068 4346 mov r3, r8 + 847 006a 1A70 strb r2, [r3] + 539:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *txPowOut = txPower; + 848 .loc 1 539 0 + 849 006c 3E70 strb r6, [r7] + 540:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return adrAckReq; + 541:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 850 .loc 1 541 0 + 851 006e 2800 movs r0, r5 + 852 0070 02B0 add sp, sp, #8 + 853 @ sp needed + 854 .LVL83: + 855 .LVL84: + 856 .LVL85: + 857 .LVL86: + 858 .LVL87: + 859 0072 04BC pop {r2} + 860 0074 9046 mov r8, r2 + 861 0076 F0BD pop {r4, r5, r6, r7, pc} + 862 .LVL88: + 863 .L77: + 510:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 864 .loc 1 510 0 + 865 0078 0025 movs r5, #0 + 866 007a D7E7 b .L76 + 867 .L80: + 868 .align 2 + 869 .L79: + 870 007c 00000000 .word .LANCHOR2 + 871 .cfi_endproc + 872 .LFE96: + 874 .section .text.RegionEU868ComputeRxWindowParameters,"ax",%progbits + 875 .align 1 + 876 .global RegionEU868ComputeRxWindowParameters + 877 .syntax unified + 878 .code 16 + 879 .thumb_func + 880 .fpu softvfp + 882 RegionEU868ComputeRxWindowParameters: + 883 .LFB97: + 542:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 543:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, + 544:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 884 .loc 1 544 0 + 885 .cfi_startproc + ARM GAS /tmp/cczfoKrY.s page 27 + + + 886 @ args = 0, pretend = 0, frame = 8 + 887 @ frame_needed = 0, uses_anonymous_args = 0 + 888 .LVL89: + 889 0000 70B5 push {r4, r5, r6, lr} + 890 .LCFI9: + 891 .cfi_def_cfa_offset 16 + 892 .cfi_offset 4, -16 + 893 .cfi_offset 5, -12 + 894 .cfi_offset 6, -8 + 895 .cfi_offset 14, -4 + 896 0002 86B0 sub sp, sp, #24 + 897 .LCFI10: + 898 .cfi_def_cfa_offset 40 + 899 0004 0C00 movs r4, r1 + 900 0006 1500 movs r5, r2 + 901 0008 1E00 movs r6, r3 + 902 .LVL90: + 545:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** double tSymbol = 0.0; + 546:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint32_t radioWakeUpTime; + 547:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 548:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Get the datarate, perform a boundary check + 549:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** rxConfigParams->Datarate = MIN( datarate, EU868_RX_MAX_DATARATE ); + 903 .loc 1 549 0 + 904 000a 021C adds r2, r0, #0 + 905 .LVL91: + 906 000c 0728 cmp r0, #7 + 907 000e 00DD ble .L82 + 908 0010 0722 movs r2, #7 + 909 .L82: + 910 0012 53B2 sxtb r3, r2 + 911 .LVL92: + 912 0014 7270 strb r2, [r6, #1] + 913 .LVL93: + 914 .LBB18: + 915 .LBB19: + 85:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 916 .loc 1 85 0 + 917 0016 9900 lsls r1, r3, #2 + 918 .LVL94: + 919 0018 184A ldr r2, .L90 + 920 001a 8A58 ldr r2, [r1, r2] + 921 001c 1849 ldr r1, .L90+4 + 922 001e 8A42 cmp r2, r1 + 923 0020 22D0 beq .L88 + 924 0022 1849 ldr r1, .L90+8 + 925 0024 8A42 cmp r2, r1 + 926 0026 1DD0 beq .L85 + 89:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 250000: + 927 .loc 1 89 0 + 928 0028 0022 movs r2, #0 + 929 .L84: + 930 .LVL95: + 931 .LBE19: + 932 .LBE18: + 550:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** rxConfigParams->Bandwidth = GetBandwidth( rxConfigParams->Datarate ); + 933 .loc 1 550 0 + 934 002a B270 strb r2, [r6, #2] + ARM GAS /tmp/cczfoKrY.s page 28 + + + 551:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 552:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( rxConfigParams->Datarate == DR_7 ) + 935 .loc 1 552 0 + 936 002c 072B cmp r3, #7 + 937 002e 1DD0 beq .L89 + 553:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // FSK + 554:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesEU868[rxConfigParams->Datarate] ); + 555:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 556:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 557:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // LoRa + 558:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesEU868[rxConfigParams->Datarate], Band + 938 .loc 1 558 0 + 939 0030 154A ldr r2, .L90+12 + 940 0032 D05C ldrb r0, [r2, r3] + 941 .LVL96: + 942 0034 9B00 lsls r3, r3, #2 + 943 0036 114A ldr r2, .L90 + 944 0038 9958 ldr r1, [r3, r2] + 945 003a FFF7FEFF bl RegionCommonComputeSymbolTimeLoRa + 946 .LVL97: + 947 003e 0490 str r0, [sp, #16] + 948 0040 0591 str r1, [sp, #20] + 949 .LVL98: + 950 .L87: + 559:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 560:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 561:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** radioWakeUpTime = Radio.GetRadioWakeUpTime(); + 951 .loc 1 561 0 + 952 0042 124B ldr r3, .L90+16 + 953 0044 5B6E ldr r3, [r3, #100] + 954 0046 9847 blx r3 + 955 .LVL99: + 562:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConf + 956 .loc 1 562 0 + 957 0048 3300 movs r3, r6 + 958 004a 0C33 adds r3, r3, #12 + 959 004c 0293 str r3, [sp, #8] + 960 004e 043B subs r3, r3, #4 + 961 0050 0193 str r3, [sp, #4] + 962 0052 0090 str r0, [sp] + 963 0054 2B00 movs r3, r5 + 964 0056 2200 movs r2, r4 + 965 0058 0498 ldr r0, [sp, #16] + 966 005a 0599 ldr r1, [sp, #20] + 967 .LVL100: + 968 005c FFF7FEFF bl RegionCommonComputeRxWindowParameters + 969 .LVL101: + 563:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 970 .loc 1 563 0 + 971 0060 06B0 add sp, sp, #24 + 972 @ sp needed + 973 .LVL102: + 974 .LVL103: + 975 0062 70BD pop {r4, r5, r6, pc} + 976 .LVL104: + 977 .L85: + 978 .LBB21: + ARM GAS /tmp/cczfoKrY.s page 29 + + + 979 .LBB20: + 93:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 980 .loc 1 93 0 + 981 0064 0222 movs r2, #2 + 982 0066 E0E7 b .L84 + 983 .L88: + 91:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 500000: + 984 .loc 1 91 0 + 985 0068 0122 movs r2, #1 + 986 006a DEE7 b .L84 + 987 .LVL105: + 988 .L89: + 989 .LBE20: + 990 .LBE21: + 554:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 991 .loc 1 554 0 + 992 006c 064A ldr r2, .L90+12 + 993 006e D05C ldrb r0, [r2, r3] + 994 .LVL106: + 995 0070 FFF7FEFF bl RegionCommonComputeSymbolTimeFsk + 996 .LVL107: + 997 0074 0490 str r0, [sp, #16] + 998 0076 0591 str r1, [sp, #20] + 999 .LVL108: + 1000 0078 E3E7 b .L87 + 1001 .L91: + 1002 007a C046 .align 2 + 1003 .L90: + 1004 007c 00000000 .word .LANCHOR6 + 1005 0080 90D00300 .word 250000 + 1006 0084 20A10700 .word 500000 + 1007 0088 00000000 .word .LANCHOR7 + 1008 008c 00000000 .word Radio + 1009 .cfi_endproc + 1010 .LFE97: + 1012 .section .text.RegionEU868RxConfig,"ax",%progbits + 1013 .align 1 + 1014 .global RegionEU868RxConfig + 1015 .syntax unified + 1016 .code 16 + 1017 .thumb_func + 1018 .fpu softvfp + 1020 RegionEU868RxConfig: + 1021 .LFB98: + 564:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 565:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) + 566:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1022 .loc 1 566 0 + 1023 .cfi_startproc + 1024 @ args = 0, pretend = 0, frame = 8 + 1025 @ frame_needed = 0, uses_anonymous_args = 0 + 1026 .LVL109: + 1027 0000 F0B5 push {r4, r5, r6, r7, lr} + 1028 .LCFI11: + 1029 .cfi_def_cfa_offset 20 + 1030 .cfi_offset 4, -20 + 1031 .cfi_offset 5, -16 + ARM GAS /tmp/cczfoKrY.s page 30 + + + 1032 .cfi_offset 6, -12 + 1033 .cfi_offset 7, -8 + 1034 .cfi_offset 14, -4 + 1035 0002 8DB0 sub sp, sp, #52 + 1036 .LCFI12: + 1037 .cfi_def_cfa_offset 72 + 1038 0004 0400 movs r4, r0 + 1039 0006 0B91 str r1, [sp, #44] + 567:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RadioModems_t modem; + 568:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t dr = rxConfig->Datarate; + 1040 .loc 1 568 0 + 1041 0008 0126 movs r6, #1 + 1042 000a 8657 ldrsb r6, [r0, r6] + 1043 .LVL110: + 569:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t maxPayload = 0; + 570:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t phyDr = 0; + 571:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint32_t frequency = rxConfig->Frequency; + 1044 .loc 1 571 0 + 1045 000c 4768 ldr r7, [r0, #4] + 1046 .LVL111: + 572:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 573:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Radio.GetStatus( ) != RF_IDLE ) + 1047 .loc 1 573 0 + 1048 000e 334B ldr r3, .L101 + 1049 0010 DB68 ldr r3, [r3, #12] + 1050 0012 9847 blx r3 + 1051 .LVL112: + 1052 0014 0028 cmp r0, #0 + 1053 0016 5ED1 bne .L99 + 574:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 575:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 576:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 577:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 578:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( rxConfig->Window == 0 ) + 1054 .loc 1 578 0 + 1055 0018 E37C ldrb r3, [r4, #19] + 1056 001a 002B cmp r3, #0 + 1057 001c 0BD1 bne .L94 + 579:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 580:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Apply window 1 frequency + 581:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** frequency = Channels[rxConfig->Channel].Frequency; + 1058 .loc 1 581 0 + 1059 001e 2178 ldrb r1, [r4] + 1060 0020 2F4A ldr r2, .L101+4 + 1061 0022 4B00 lsls r3, r1, #1 + 1062 0024 5F18 adds r7, r3, r1 + 1063 .LVL113: + 1064 0026 B800 lsls r0, r7, #2 + 1065 0028 0700 movs r7, r0 + 1066 002a 8058 ldr r0, [r0, r2] + 1067 .LVL114: + 582:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Apply the alternative RX 1 window frequency, if it is available + 583:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + 1068 .loc 1 583 0 + 1069 002c D219 adds r2, r2, r7 + 1070 002e 5768 ldr r7, [r2, #4] + 1071 0030 002F cmp r7, #0 + ARM GAS /tmp/cczfoKrY.s page 31 + + + 1072 0032 00D1 bne .L94 + 581:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Apply the alternative RX 1 window frequency, if it is available + 1073 .loc 1 581 0 + 1074 0034 0700 movs r7, r0 + 1075 .LVL115: + 1076 .L94: + 584:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 585:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** frequency = Channels[rxConfig->Channel].Rx1Frequency; + 586:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 587:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 588:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 589:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Read the physical datarate from the datarates table + 590:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyDr = DataratesEU868[dr]; + 1077 .loc 1 590 0 + 1078 0036 2B4B ldr r3, .L101+8 + 1079 0038 9D57 ldrsb r5, [r3, r6] + 1080 .LVL116: + 591:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 592:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetChannel( frequency ); + 1081 .loc 1 592 0 + 1082 003a 284B ldr r3, .L101 + 1083 003c 5B69 ldr r3, [r3, #20] + 1084 003e 3800 movs r0, r7 + 1085 0040 9847 blx r3 + 1086 .LVL117: + 593:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 594:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Radio configuration + 595:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( dr == DR_7 ) + 1087 .loc 1 595 0 + 1088 0042 072E cmp r6, #7 + 1089 0044 26D0 beq .L100 + 1090 .LVL118: + 596:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 597:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** modem = MODEM_FSK; + 598:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, + 599:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 600:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 601:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 602:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** modem = MODEM_LORA; + 603:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, fal + 1091 .loc 1 603 0 + 1092 0046 254B ldr r3, .L101 + 1093 0048 1F6A ldr r7, [r3, #32] + 1094 .LVL119: + 1095 004a A178 ldrb r1, [r4, #2] + 1096 004c A37C ldrb r3, [r4, #18] + 1097 004e 0993 str r3, [sp, #36] + 1098 0050 0123 movs r3, #1 + 1099 0052 0893 str r3, [sp, #32] + 1100 0054 0023 movs r3, #0 + 1101 0056 0793 str r3, [sp, #28] + 1102 0058 0693 str r3, [sp, #24] + 1103 005a 0593 str r3, [sp, #20] + 1104 005c 0493 str r3, [sp, #16] + 1105 005e 0393 str r3, [sp, #12] + 1106 0060 A268 ldr r2, [r4, #8] + 1107 0062 92B2 uxth r2, r2 + ARM GAS /tmp/cczfoKrY.s page 32 + + + 1108 0064 0292 str r2, [sp, #8] + 1109 0066 0822 movs r2, #8 + 1110 0068 0192 str r2, [sp, #4] + 1111 006a 0093 str r3, [sp] + 1112 006c 0133 adds r3, r3, #1 + 1113 006e 2A00 movs r2, r5 + 1114 0070 0120 movs r0, #1 + 1115 0072 B847 blx r7 + 1116 .LVL120: + 602:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, fal + 1117 .loc 1 602 0 + 1118 0074 0120 movs r0, #1 + 1119 .LVL121: + 1120 .L96: + 604:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 605:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 606:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( rxConfig->RepeaterSupport == true ) + 1121 .loc 1 606 0 + 1122 0076 637C ldrb r3, [r4, #17] + 1123 0078 002B cmp r3, #0 + 1124 007a 29D0 beq .L97 + 607:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 608:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** maxPayload = MaxPayloadOfDatarateRepeaterEU868[dr]; + 1125 .loc 1 608 0 + 1126 007c 1A4B ldr r3, .L101+12 + 1127 007e 995D ldrb r1, [r3, r6] + 1128 .LVL122: + 1129 .L98: + 609:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 610:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 611:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 612:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** maxPayload = MaxPayloadOfDatarateEU868[dr]; + 613:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 614:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 615:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + 1130 .loc 1 615 0 + 1131 0080 164B ldr r3, .L101 + 1132 0082 DB6D ldr r3, [r3, #92] + 1133 0084 0D31 adds r1, r1, #13 + 1134 .LVL123: + 1135 0086 C9B2 uxtb r1, r1 + 1136 0088 9847 blx r3 + 1137 .LVL124: + 616:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** DBG_PRINTF( "RX on freq %d Hz at DR %d\n\r", frequency, dr ); + 617:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 618:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *datarate = (uint8_t) dr; + 1138 .loc 1 618 0 + 1139 008a 0B9B ldr r3, [sp, #44] + 1140 008c 1E70 strb r6, [r3] + 619:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 1141 .loc 1 619 0 + 1142 008e 0120 movs r0, #1 + 1143 .LVL125: + 1144 .L93: + 620:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1145 .loc 1 620 0 + 1146 0090 0DB0 add sp, sp, #52 + ARM GAS /tmp/cczfoKrY.s page 33 + + + 1147 @ sp needed + 1148 .LVL126: + 1149 .LVL127: + 1150 0092 F0BD pop {r4, r5, r6, r7, pc} + 1151 .LVL128: + 1152 .L100: + 598:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1153 .loc 1 598 0 + 1154 0094 114B ldr r3, .L101 + 1155 0096 1F6A ldr r7, [r3, #32] + 1156 .LVL129: + 1157 0098 6B01 lsls r3, r5, #5 + 1158 009a 5B1B subs r3, r3, r5 + 1159 009c 9B00 lsls r3, r3, #2 + 1160 009e 5B19 adds r3, r3, r5 + 1161 00a0 DA00 lsls r2, r3, #3 + 1162 00a2 A37C ldrb r3, [r4, #18] + 1163 00a4 0993 str r3, [sp, #36] + 1164 00a6 0023 movs r3, #0 + 1165 00a8 0893 str r3, [sp, #32] + 1166 00aa 0793 str r3, [sp, #28] + 1167 00ac 0693 str r3, [sp, #24] + 1168 00ae 0121 movs r1, #1 + 1169 00b0 0591 str r1, [sp, #20] + 1170 00b2 0493 str r3, [sp, #16] + 1171 00b4 0393 str r3, [sp, #12] + 1172 00b6 A368 ldr r3, [r4, #8] + 1173 00b8 9BB2 uxth r3, r3 + 1174 00ba 0293 str r3, [sp, #8] + 1175 00bc 0523 movs r3, #5 + 1176 00be 0193 str r3, [sp, #4] + 1177 00c0 0A4B ldr r3, .L101+16 + 1178 00c2 0093 str r3, [sp] + 1179 00c4 0023 movs r3, #0 + 1180 00c6 0A49 ldr r1, .L101+20 + 1181 00c8 0020 movs r0, #0 + 1182 00ca B847 blx r7 + 1183 .LVL130: + 597:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, + 1184 .loc 1 597 0 + 1185 00cc 0020 movs r0, #0 + 1186 00ce D2E7 b .L96 + 1187 .LVL131: + 1188 .L97: + 612:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1189 .loc 1 612 0 + 1190 00d0 084B ldr r3, .L101+24 + 1191 00d2 995D ldrb r1, [r3, r6] + 1192 .LVL132: + 1193 00d4 D4E7 b .L98 + 1194 .LVL133: + 1195 .L99: + 575:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1196 .loc 1 575 0 + 1197 00d6 0020 movs r0, #0 + 1198 00d8 DAE7 b .L93 + 1199 .L102: + ARM GAS /tmp/cczfoKrY.s page 34 + + + 1200 00da C046 .align 2 + 1201 .L101: + 1202 00dc 00000000 .word Radio + 1203 00e0 00000000 .word Channels + 1204 00e4 00000000 .word .LANCHOR7 + 1205 00e8 00000000 .word .LANCHOR1 + 1206 00ec 85450100 .word 83333 + 1207 00f0 50C30000 .word 50000 + 1208 00f4 00000000 .word .LANCHOR0 + 1209 .cfi_endproc + 1210 .LFE98: + 1212 .section .text.RegionEU868TxConfig,"ax",%progbits + 1213 .align 1 + 1214 .global RegionEU868TxConfig + 1215 .syntax unified + 1216 .code 16 + 1217 .thumb_func + 1218 .fpu softvfp + 1220 RegionEU868TxConfig: + 1221 .LFB99: + 621:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 622:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) + 623:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1222 .loc 1 623 0 + 1223 .cfi_startproc + 1224 @ args = 0, pretend = 0, frame = 8 + 1225 @ frame_needed = 0, uses_anonymous_args = 0 + 1226 .LVL134: + 1227 0000 F0B5 push {r4, r5, r6, r7, lr} + 1228 .LCFI13: + 1229 .cfi_def_cfa_offset 20 + 1230 .cfi_offset 4, -20 + 1231 .cfi_offset 5, -16 + 1232 .cfi_offset 6, -12 + 1233 .cfi_offset 7, -8 + 1234 .cfi_offset 14, -4 + 1235 0002 CE46 mov lr, r9 + 1236 0004 4746 mov r7, r8 + 1237 0006 80B5 push {r7, lr} + 1238 .LCFI14: + 1239 .cfi_def_cfa_offset 28 + 1240 .cfi_offset 8, -28 + 1241 .cfi_offset 9, -24 + 1242 0008 8DB0 sub sp, sp, #52 + 1243 .LCFI15: + 1244 .cfi_def_cfa_offset 80 + 1245 000a 0400 movs r4, r0 + 1246 000c 8846 mov r8, r1 + 1247 000e 9146 mov r9, r2 + 624:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RadioModems_t modem; + 625:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t phyDr = DataratesEU868[txConfig->Datarate]; + 1248 .loc 1 625 0 + 1249 0010 0123 movs r3, #1 + 1250 0012 C356 ldrsb r3, [r0, r3] + 1251 0014 3D4A ldr r2, .L112 + 1252 .LVL135: + 1253 0016 D756 ldrsb r7, [r2, r3] + ARM GAS /tmp/cczfoKrY.s page 35 + + + 1254 .LVL136: + 626:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band + 1255 .loc 1 626 0 + 1256 0018 0220 movs r0, #2 + 1257 .LVL137: + 1258 001a 2056 ldrsb r0, [r4, r0] + 1259 001c 2178 ldrb r1, [r4] + 1260 .LVL138: + 1261 001e 4A00 lsls r2, r1, #1 + 1262 0020 5218 adds r2, r2, r1 + 1263 0022 9100 lsls r1, r2, #2 + 1264 0024 3A4A ldr r2, .L112+4 + 1265 0026 5218 adds r2, r2, r1 + 1266 0028 517A ldrb r1, [r2, #9] + 1267 002a 0901 lsls r1, r1, #4 + 1268 002c 394A ldr r2, .L112+8 + 1269 002e 5218 adds r2, r2, r1 + 1270 0030 9278 ldrb r2, [r2, #2] + 1271 0032 52B2 sxtb r2, r2 + 1272 .LVL139: + 1273 .LBB22: + 1274 .LBB23: + 102:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 1275 .loc 1 102 0 + 1276 0034 051C adds r5, r0, #0 + 1277 0036 9042 cmp r0, r2 + 1278 0038 00DA bge .L104 + 1279 003a 151C adds r5, r2, #0 + 1280 .L104: + 1281 003c 6DB2 sxtb r5, r5 + 1282 .LVL140: + 1283 .LBE23: + 1284 .LBE22: + 1285 .LBB24: + 1286 .LBB25: + 85:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1287 .loc 1 85 0 + 1288 003e 9B00 lsls r3, r3, #2 + 1289 .LVL141: + 1290 0040 354A ldr r2, .L112+12 + 1291 0042 9B58 ldr r3, [r3, r2] + 1292 0044 354A ldr r2, .L112+16 + 1293 0046 9342 cmp r3, r2 + 1294 0048 42D0 beq .L110 + 1295 004a 354A ldr r2, .L112+20 + 1296 004c 9342 cmp r3, r2 + 1297 004e 3CD0 beq .L107 + 89:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 250000: + 1298 .loc 1 89 0 + 1299 0050 0023 movs r3, #0 + 1300 0052 0A93 str r3, [sp, #40] + 1301 .LVL142: + 1302 .L106: + 1303 .LBE25: + 1304 .LBE24: + 627:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + 628:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t phyTxPower = 0; + ARM GAS /tmp/cczfoKrY.s page 36 + + + 629:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 630:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Calculate physical TX power + 631:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGa + 1305 .loc 1 631 0 + 1306 0054 A268 ldr r2, [r4, #8] + 1307 0056 6168 ldr r1, [r4, #4] + 1308 0058 2800 movs r0, r5 + 1309 005a FFF7FEFF bl RegionCommonComputeTxPower + 1310 .LVL143: + 1311 005e 0B90 str r0, [sp, #44] + 1312 .LVL144: + 632:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 633:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Setup the radio frequency + 634:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + 1313 .loc 1 634 0 + 1314 0060 304B ldr r3, .L112+24 + 1315 0062 5969 ldr r1, [r3, #20] + 1316 0064 2278 ldrb r2, [r4] + 1317 0066 5300 lsls r3, r2, #1 + 1318 0068 9B18 adds r3, r3, r2 + 1319 006a 9A00 lsls r2, r3, #2 + 1320 006c 284B ldr r3, .L112+4 + 1321 006e D058 ldr r0, [r2, r3] + 1322 0070 8847 blx r1 + 1323 .LVL145: + 635:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 636:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( txConfig->Datarate == DR_7 ) + 1324 .loc 1 636 0 + 1325 0072 0123 movs r3, #1 + 1326 0074 E356 ldrsb r3, [r4, r3] + 1327 0076 072B cmp r3, #7 + 1328 0078 2DD0 beq .L111 + 1329 .LVL146: + 637:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // High Speed FSK channel + 638:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** modem = MODEM_FSK; + 639:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, + 640:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 641:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 642:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 643:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** modem = MODEM_LORA; + 644:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, + 1330 .loc 1 644 0 + 1331 007a 2A4B ldr r3, .L112+24 + 1332 007c 5E6A ldr r6, [r3, #36] + 1333 007e 2A4B ldr r3, .L112+28 + 1334 0080 0893 str r3, [sp, #32] + 1335 0082 0023 movs r3, #0 + 1336 0084 0793 str r3, [sp, #28] + 1337 0086 0693 str r3, [sp, #24] + 1338 0088 0593 str r3, [sp, #20] + 1339 008a 0122 movs r2, #1 + 1340 008c 0492 str r2, [sp, #16] + 1341 008e 0393 str r3, [sp, #12] + 1342 0090 0833 adds r3, r3, #8 + 1343 0092 0293 str r3, [sp, #8] + 1344 0094 0192 str r2, [sp, #4] + 1345 0096 0097 str r7, [sp] + ARM GAS /tmp/cczfoKrY.s page 37 + + + 1346 0098 0A9B ldr r3, [sp, #40] + 1347 009a 0022 movs r2, #0 + 1348 009c 0B99 ldr r1, [sp, #44] + 1349 009e 0120 movs r0, #1 + 1350 00a0 B047 blx r6 + 1351 .LVL147: + 643:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, + 1352 .loc 1 643 0 + 1353 00a2 0126 movs r6, #1 + 1354 .LVL148: + 1355 .L109: + 645:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 646:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** DBG_PRINTF( "TX on freq %d Hz at DR %d\n\r", Channels[txConfig->Channel].Frequency, txConfig->D + 647:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 648:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Setup maximum payload lenght of the radio driver + 649:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + 1356 .loc 1 649 0 + 1357 00a4 1F4F ldr r7, .L112+24 + 1358 .LVL149: + 1359 00a6 217B ldrb r1, [r4, #12] + 1360 00a8 3000 movs r0, r6 + 1361 00aa FB6D ldr r3, [r7, #92] + 1362 00ac 9847 blx r3 + 1363 .LVL150: + 650:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Get the time-on-air of the next tx frame + 651:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + 1364 .loc 1 651 0 + 1365 00ae FB6A ldr r3, [r7, #44] + 1366 00b0 217B ldrb r1, [r4, #12] + 1367 00b2 3000 movs r0, r6 + 1368 00b4 9847 blx r3 + 1369 .LVL151: + 1370 00b6 4B46 mov r3, r9 + 1371 00b8 1860 str r0, [r3] + 652:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 653:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *txPower = txPowerLimited; + 1372 .loc 1 653 0 + 1373 00ba 4346 mov r3, r8 + 1374 00bc 1D70 strb r5, [r3] + 654:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 655:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1375 .loc 1 655 0 + 1376 00be 0120 movs r0, #1 + 1377 00c0 0DB0 add sp, sp, #52 + 1378 @ sp needed + 1379 .LVL152: + 1380 .LVL153: + 1381 .LVL154: + 1382 .LVL155: + 1383 00c2 0CBC pop {r2, r3} + 1384 00c4 9046 mov r8, r2 + 1385 00c6 9946 mov r9, r3 + 1386 00c8 F0BD pop {r4, r5, r6, r7, pc} + 1387 .LVL156: + 1388 .L107: + 1389 .LBB27: + 1390 .LBB26: + ARM GAS /tmp/cczfoKrY.s page 38 + + + 93:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1391 .loc 1 93 0 + 1392 00ca 0223 movs r3, #2 + 1393 00cc 0A93 str r3, [sp, #40] + 1394 .LVL157: + 1395 00ce C1E7 b .L106 + 1396 .LVL158: + 1397 .L110: + 91:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case 500000: + 1398 .loc 1 91 0 + 1399 00d0 0123 movs r3, #1 + 1400 .LVL159: + 1401 00d2 0A93 str r3, [sp, #40] + 1402 .LVL160: + 1403 00d4 BEE7 b .L106 + 1404 .LVL161: + 1405 .L111: + 1406 .LBE26: + 1407 .LBE27: + 639:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1408 .loc 1 639 0 + 1409 00d6 134B ldr r3, .L112+24 + 1410 00d8 5E6A ldr r6, [r3, #36] + 1411 00da 7B01 lsls r3, r7, #5 + 1412 00dc DB1B subs r3, r3, r7 + 1413 00de 9B00 lsls r3, r3, #2 + 1414 00e0 DB19 adds r3, r3, r7 + 1415 00e2 DA00 lsls r2, r3, #3 + 1416 00e4 104B ldr r3, .L112+28 + 1417 00e6 0893 str r3, [sp, #32] + 1418 00e8 0023 movs r3, #0 + 1419 00ea 0793 str r3, [sp, #28] + 1420 00ec 0693 str r3, [sp, #24] + 1421 00ee 0593 str r3, [sp, #20] + 1422 00f0 0121 movs r1, #1 + 1423 00f2 0491 str r1, [sp, #16] + 1424 00f4 0393 str r3, [sp, #12] + 1425 00f6 0431 adds r1, r1, #4 + 1426 00f8 0291 str r1, [sp, #8] + 1427 00fa 0193 str r3, [sp, #4] + 1428 00fc 0092 str r2, [sp] + 1429 00fe 0A9B ldr r3, [sp, #40] + 1430 0100 0A4A ldr r2, .L112+32 + 1431 0102 0B99 ldr r1, [sp, #44] + 1432 0104 0020 movs r0, #0 + 1433 0106 B047 blx r6 + 1434 .LVL162: + 638:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, + 1435 .loc 1 638 0 + 1436 0108 0026 movs r6, #0 + 1437 010a CBE7 b .L109 + 1438 .L113: + 1439 .align 2 + 1440 .L112: + 1441 010c 00000000 .word .LANCHOR7 + 1442 0110 00000000 .word Channels + 1443 0114 00000000 .word .LANCHOR4 + ARM GAS /tmp/cczfoKrY.s page 39 + + + 1444 0118 00000000 .word .LANCHOR6 + 1445 011c 90D00300 .word 250000 + 1446 0120 20A10700 .word 500000 + 1447 0124 00000000 .word Radio + 1448 0128 B80B0000 .word 3000 + 1449 012c A8610000 .word 25000 + 1450 .cfi_endproc + 1451 .LFE99: + 1453 .section .text.RegionEU868LinkAdrReq,"ax",%progbits + 1454 .align 1 + 1455 .global RegionEU868LinkAdrReq + 1456 .syntax unified + 1457 .code 16 + 1458 .thumb_func + 1459 .fpu softvfp + 1461 RegionEU868LinkAdrReq: + 1462 .LFB100: + 656:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 657:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t RegionEU868LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uin + 658:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1463 .loc 1 658 0 + 1464 .cfi_startproc + 1465 @ args = 4, pretend = 0, frame = 48 + 1466 @ frame_needed = 0, uses_anonymous_args = 0 + 1467 .LVL163: + 1468 0000 F0B5 push {r4, r5, r6, r7, lr} + 1469 .LCFI16: + 1470 .cfi_def_cfa_offset 20 + 1471 .cfi_offset 4, -20 + 1472 .cfi_offset 5, -16 + 1473 .cfi_offset 6, -12 + 1474 .cfi_offset 7, -8 + 1475 .cfi_offset 14, -4 + 1476 0002 D646 mov lr, r10 + 1477 0004 4F46 mov r7, r9 + 1478 0006 4646 mov r6, r8 + 1479 0008 C0B5 push {r6, r7, lr} + 1480 .LCFI17: + 1481 .cfi_def_cfa_offset 32 + 1482 .cfi_offset 8, -32 + 1483 .cfi_offset 9, -28 + 1484 .cfi_offset 10, -24 + 1485 000a 8CB0 sub sp, sp, #48 + 1486 .LCFI18: + 1487 .cfi_def_cfa_offset 80 + 1488 000c 0500 movs r5, r0 + 1489 000e 8946 mov r9, r1 + 1490 0010 9046 mov r8, r2 + 1491 0012 9A46 mov r10, r3 + 1492 .LVL164: + 659:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x07; + 660:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonLinkAdrParams_t linkAdrParams; + 661:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t nextIndex = 0; + 662:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t bytesProcessed = 0; + 663:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint16_t chMask = 0; + 1493 .loc 1 663 0 + 1494 0014 2623 movs r3, #38 + ARM GAS /tmp/cczfoKrY.s page 40 + + + 1495 .LVL165: + 1496 0016 6B44 add r3, r3, sp + 1497 0018 0022 movs r2, #0 + 1498 .LVL166: + 1499 001a 1A80 strh r2, [r3] + 662:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint16_t chMask = 0; + 1500 .loc 1 662 0 + 1501 001c 0024 movs r4, #0 + 659:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x07; + 1502 .loc 1 659 0 + 1503 001e 0726 movs r6, #7 + 664:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** GetPhyParams_t getPhy; + 665:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** PhyParam_t phyParam; + 666:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonLinkAdrReqVerifyParams_t linkAdrVerifyParams; + 667:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 668:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** while( bytesProcessed < linkAdrReq->PayloadSize ) + 1504 .loc 1 668 0 + 1505 0020 29E0 b .L115 + 1506 .LVL167: + 1507 .L152: + 1508 .LBB33: + 669:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 670:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Get ADR request parameters + 671:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdr + 672:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 673:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( nextIndex == 0 ) + 674:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; // break loop, since no more request has been found + 675:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 676:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update bytes processed + 677:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bytesProcessed += nextIndex; + 678:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 679:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Revert status, as we only check the last ADR request for the channel mask KO + 680:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status = 0x07; + 681:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 682:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Setup temporary channels mask + 683:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** chMask = linkAdrParams.ChMask; + 684:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 685:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify channels mask + 686:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + 687:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 688:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; // Channel mask KO + 689:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 690:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + 691:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( linkAdrParams.ChMaskCtrl >= 7 ) ) + 692:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 693:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // RFU + 694:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; // Channel mask KO + 695:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 696:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 697:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 698:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** for( uint8_t i = 0; i < EU868_MAX_NB_CHANNELS; i++ ) + 1509 .loc 1 698 0 + 1510 0022 0023 movs r3, #0 + 1511 .LBE33: + 680:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 1512 .loc 1 680 0 + 1513 0024 0726 movs r6, #7 + ARM GAS /tmp/cczfoKrY.s page 41 + + + 1514 0026 0FE0 b .L119 + 1515 .LVL168: + 1516 .L151: + 1517 .LBB34: + 699:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 700:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( linkAdrParams.ChMaskCtrl == 6 ) + 701:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 702:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Channels[i].Frequency != 0 ) + 1518 .loc 1 702 0 + 1519 0028 5A00 lsls r2, r3, #1 + 1520 002a D218 adds r2, r2, r3 + 1521 002c 9000 lsls r0, r2, #2 + 1522 002e 444A ldr r2, .L154 + 1523 0030 8258 ldr r2, [r0, r2] + 1524 0032 002A cmp r2, #0 + 1525 0034 06D0 beq .L121 + 703:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 704:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** chMask |= 1 << i; + 1526 .loc 1 704 0 + 1527 0036 0127 movs r7, #1 + 1528 0038 9F40 lsls r7, r7, r3 + 1529 003a 2620 movs r0, #38 + 1530 003c 6844 add r0, r0, sp + 1531 003e 0288 ldrh r2, [r0] + 1532 0040 3A43 orrs r2, r7 + 1533 0042 0280 strh r2, [r0] + 1534 .L121: + 698:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1535 .loc 1 698 0 discriminator 2 + 1536 0044 0133 adds r3, r3, #1 + 1537 .LVL169: + 1538 0046 DBB2 uxtb r3, r3 + 1539 .LVL170: + 1540 .L119: + 698:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1541 .loc 1 698 0 is_stmt 0 discriminator 1 + 1542 0048 0F2B cmp r3, #15 + 1543 004a 14D8 bhi .L115 + 700:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1544 .loc 1 700 0 is_stmt 1 + 1545 004c 0629 cmp r1, #6 + 1546 004e EBD0 beq .L151 + 705:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 706:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 707:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 708:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 709:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( ( chMask & ( 1 << i ) ) != 0 ) && + 1547 .loc 1 709 0 + 1548 0050 2622 movs r2, #38 + 1549 0052 6A44 add r2, r2, sp + 1550 0054 1288 ldrh r2, [r2] + 1551 0056 1A41 asrs r2, r2, r3 + 1552 0058 D207 lsls r2, r2, #31 + 1553 005a F3D5 bpl .L121 + 710:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( Channels[i].Frequency == 0 ) ) + 1554 .loc 1 710 0 discriminator 1 + 1555 005c 5A00 lsls r2, r3, #1 + ARM GAS /tmp/cczfoKrY.s page 42 + + + 1556 005e D218 adds r2, r2, r3 + 1557 0060 9000 lsls r0, r2, #2 + 1558 0062 374A ldr r2, .L154 + 1559 0064 8258 ldr r2, [r0, r2] + 709:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( Channels[i].Frequency == 0 ) ) + 1560 .loc 1 709 0 discriminator 1 + 1561 0066 002A cmp r2, #0 + 1562 0068 ECD1 bne .L121 + 711:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** {// Trying to enable an undefined channel + 712:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; // Channel mask KO + 1563 .loc 1 712 0 + 1564 006a 0132 adds r2, r2, #1 + 1565 006c 9643 bics r6, r2 + 1566 .LVL171: + 1567 006e E9E7 b .L121 + 1568 .LVL172: + 1569 .L147: + 1570 .LBE34: + 688:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1571 .loc 1 688 0 + 1572 0070 0626 movs r6, #6 + 1573 0072 00E0 b .L115 + 1574 .L148: + 694:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1575 .loc 1 694 0 + 1576 0074 0626 movs r6, #6 + 1577 .LVL173: + 1578 .L115: + 668:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1579 .loc 1 668 0 + 1580 0076 2B79 ldrb r3, [r5, #4] + 1581 0078 A342 cmp r3, r4 + 1582 007a 1AD9 bls .L116 + 671:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 1583 .loc 1 671 0 + 1584 007c 2B68 ldr r3, [r5] + 1585 007e 1819 adds r0, r3, r4 + 1586 0080 0AA9 add r1, sp, #40 + 1587 0082 FFF7FEFF bl RegionCommonParseLinkAdrReq + 1588 .LVL174: + 673:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; // break loop, since no more request has been found + 1589 .loc 1 673 0 + 1590 0086 0028 cmp r0, #0 + 1591 0088 13D0 beq .L116 + 677:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 1592 .loc 1 677 0 + 1593 008a 2418 adds r4, r4, r0 + 1594 .LVL175: + 1595 008c E4B2 uxtb r4, r4 + 1596 .LVL176: + 683:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 1597 .loc 1 683 0 + 1598 008e 0AAB add r3, sp, #40 + 1599 0090 9A88 ldrh r2, [r3, #4] + 1600 0092 2621 movs r1, #38 + 1601 0094 6944 add r1, r1, sp + 1602 0096 0A80 strh r2, [r1] + ARM GAS /tmp/cczfoKrY.s page 43 + + + 686:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1603 .loc 1 686 0 + 1604 0098 D978 ldrb r1, [r3, #3] + 1605 009a 0029 cmp r1, #0 + 1606 009c 01D1 bne .L117 + 686:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1607 .loc 1 686 0 is_stmt 0 discriminator 1 + 1608 009e 002A cmp r2, #0 + 1609 00a0 E6D0 beq .L147 + 1610 .L117: + 690:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( linkAdrParams.ChMaskCtrl >= 7 ) ) + 1611 .loc 1 690 0 is_stmt 1 + 1612 00a2 4B1E subs r3, r1, #1 + 1613 00a4 DBB2 uxtb r3, r3 + 1614 00a6 042B cmp r3, #4 + 1615 00a8 E4D9 bls .L148 + 690:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ( linkAdrParams.ChMaskCtrl >= 7 ) ) + 1616 .loc 1 690 0 is_stmt 0 discriminator 1 + 1617 00aa 0629 cmp r1, #6 + 1618 00ac B9D9 bls .L152 + 694:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1619 .loc 1 694 0 is_stmt 1 + 1620 00ae 0626 movs r6, #6 + 1621 00b0 E1E7 b .L115 + 1622 .LVL177: + 1623 .L116: + 713:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 714:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 715:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 716:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 717:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 718:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 719:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Get the minimum possible datarate + 720:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** getPhy.Attribute = PHY_MIN_TX_DR; + 721:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** getPhy.UplinkDwellTime = linkAdrReq->UplinkDwellTime; + 722:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyParam = RegionEU868GetPhyParam( &getPhy ); + 723:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 724:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.Status = status; + 1624 .loc 1 724 0 + 1625 00b2 01A8 add r0, sp, #4 + 1626 00b4 0670 strb r6, [r0] + 725:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.AdrEnabled = linkAdrReq->AdrEnabled; + 1627 .loc 1 725 0 + 1628 00b6 AB79 ldrb r3, [r5, #6] + 1629 00b8 4370 strb r3, [r0, #1] + 726:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.Datarate = linkAdrParams.Datarate; + 1630 .loc 1 726 0 + 1631 00ba 0AAB add r3, sp, #40 + 1632 00bc 0122 movs r2, #1 + 1633 00be 9A56 ldrsb r2, [r3, r2] + 1634 00c0 8270 strb r2, [r0, #2] + 727:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.TxPower = linkAdrParams.TxPower; + 1635 .loc 1 727 0 + 1636 00c2 0222 movs r2, #2 + 1637 00c4 9A56 ldrsb r2, [r3, r2] + 1638 00c6 C270 strb r2, [r0, #3] + 728:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.NbRep = linkAdrParams.NbRep; + ARM GAS /tmp/cczfoKrY.s page 44 + + + 1639 .loc 1 728 0 + 1640 00c8 1A78 ldrb r2, [r3] + 1641 00ca 0271 strb r2, [r0, #4] + 729:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.CurrentDatarate = linkAdrReq->CurrentDatarate; + 1642 .loc 1 729 0 + 1643 00cc 0722 movs r2, #7 + 1644 00ce AA56 ldrsb r2, [r5, r2] + 1645 00d0 4271 strb r2, [r0, #5] + 730:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.CurrentTxPower = linkAdrReq->CurrentTxPower; + 1646 .loc 1 730 0 + 1647 00d2 0822 movs r2, #8 + 1648 00d4 AA56 ldrsb r2, [r5, r2] + 1649 00d6 8271 strb r2, [r0, #6] + 731:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.CurrentNbRep = linkAdrReq->CurrentNbRep; + 1650 .loc 1 731 0 + 1651 00d8 0922 movs r2, #9 + 1652 00da AA56 ldrsb r2, [r5, r2] + 1653 00dc C271 strb r2, [r0, #7] + 732:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.NbChannels = EU868_MAX_NB_CHANNELS; + 1654 .loc 1 732 0 + 1655 00de 1022 movs r2, #16 + 1656 00e0 0272 strb r2, [r0, #8] + 733:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.ChannelsMask = &chMask; + 1657 .loc 1 733 0 + 1658 00e2 1632 adds r2, r2, #22 + 1659 00e4 6A44 add r2, r2, sp + 1660 00e6 C260 str r2, [r0, #12] + 734:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.MinDatarate = ( int8_t )phyParam.Value; + 1661 .loc 1 734 0 + 1662 00e8 0022 movs r2, #0 + 1663 00ea 0274 strb r2, [r0, #16] + 735:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.MaxDatarate = EU868_TX_MAX_DATARATE; + 1664 .loc 1 735 0 + 1665 00ec 0732 adds r2, r2, #7 + 1666 00ee 4274 strb r2, [r0, #17] + 736:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.Channels = Channels; + 1667 .loc 1 736 0 + 1668 00f0 1349 ldr r1, .L154 + 1669 00f2 4161 str r1, [r0, #20] + 737:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.MinTxPower = EU868_MIN_TX_POWER; + 1670 .loc 1 737 0 + 1671 00f4 0276 strb r2, [r0, #24] + 738:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** linkAdrVerifyParams.MaxTxPower = EU868_MAX_TX_POWER; + 1672 .loc 1 738 0 + 1673 00f6 0022 movs r2, #0 + 1674 00f8 4276 strb r2, [r0, #25] + 739:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 740:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify the parameters and update, if necessary + 741:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status = RegionCommonLinkAdrReqVerifyParams( &linkAdrVerifyParams, &linkAdrParams.Datarate, &li + 1675 .loc 1 741 0 + 1676 00fa 2A32 adds r2, r2, #42 + 1677 00fc 6A44 add r2, r2, sp + 1678 00fe 2921 movs r1, #41 + 1679 0100 6944 add r1, r1, sp + 1680 0102 FFF7FEFF bl RegionCommonLinkAdrReqVerifyParams + 1681 .LVL178: + 742:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + ARM GAS /tmp/cczfoKrY.s page 45 + + + 743:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update channelsMask if everything is correct + 744:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( status == 0x07 ) + 1682 .loc 1 744 0 + 1683 0106 0728 cmp r0, #7 + 1684 0108 13D0 beq .L153 + 1685 .L146: + 745:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 746:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Set the channels mask to a default value + 747:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + 748:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update the channels mask + 749:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] = chMask; + 750:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 751:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 752:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update status variables + 753:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *drOut = linkAdrParams.Datarate; + 1686 .loc 1 753 0 + 1687 010a 0AAB add r3, sp, #40 + 1688 010c 0122 movs r2, #1 + 1689 010e 9A56 ldrsb r2, [r3, r2] + 1690 0110 4946 mov r1, r9 + 1691 0112 0A70 strb r2, [r1] + 754:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *txPowOut = linkAdrParams.TxPower; + 1692 .loc 1 754 0 + 1693 0114 0222 movs r2, #2 + 1694 0116 9A56 ldrsb r2, [r3, r2] + 1695 0118 4146 mov r1, r8 + 1696 011a 0A70 strb r2, [r1] + 755:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *nbRepOut = linkAdrParams.NbRep; + 1697 .loc 1 755 0 + 1698 011c 1B78 ldrb r3, [r3] + 1699 011e 5246 mov r2, r10 + 1700 0120 1370 strb r3, [r2] + 756:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *nbBytesParsed = bytesProcessed; + 1701 .loc 1 756 0 + 1702 0122 149B ldr r3, [sp, #80] + 1703 0124 1C70 strb r4, [r3] + 757:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 758:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return status; + 759:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1704 .loc 1 759 0 + 1705 0126 0CB0 add sp, sp, #48 + 1706 @ sp needed + 1707 .LVL179: + 1708 .LVL180: + 1709 .LVL181: + 1710 .LVL182: + 1711 .LVL183: + 1712 0128 1CBC pop {r2, r3, r4} + 1713 012a 9046 mov r8, r2 + 1714 012c 9946 mov r9, r3 + 1715 012e A246 mov r10, r4 + 1716 0130 F0BD pop {r4, r5, r6, r7, pc} + 1717 .L126: + 1718 .LVL184: + 1719 .L153: + 749:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1720 .loc 1 749 0 + ARM GAS /tmp/cczfoKrY.s page 46 + + + 1721 0132 2623 movs r3, #38 + 1722 0134 6B44 add r3, r3, sp + 1723 0136 1A88 ldrh r2, [r3] + 1724 0138 024B ldr r3, .L154+4 + 1725 013a 1A80 strh r2, [r3] + 1726 013c E5E7 b .L146 + 1727 .L155: + 1728 013e C046 .align 2 + 1729 .L154: + 1730 0140 00000000 .word Channels + 1731 0144 00000000 .word .LANCHOR2 + 1732 .cfi_endproc + 1733 .LFE100: + 1735 .section .text.RegionEU868RxParamSetupReq,"ax",%progbits + 1736 .align 1 + 1737 .global RegionEU868RxParamSetupReq + 1738 .syntax unified + 1739 .code 16 + 1740 .thumb_func + 1741 .fpu softvfp + 1743 RegionEU868RxParamSetupReq: + 1744 .LFB101: + 760:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 761:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t RegionEU868RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) + 762:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1745 .loc 1 762 0 + 1746 .cfi_startproc + 1747 @ args = 0, pretend = 0, frame = 0 + 1748 @ frame_needed = 0, uses_anonymous_args = 0 + 1749 .LVL185: + 1750 0000 70B5 push {r4, r5, r6, lr} + 1751 .LCFI19: + 1752 .cfi_def_cfa_offset 16 + 1753 .cfi_offset 4, -16 + 1754 .cfi_offset 5, -12 + 1755 .cfi_offset 6, -8 + 1756 .cfi_offset 14, -4 + 1757 0002 0500 movs r5, r0 + 1758 .LVL186: + 763:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x07; + 764:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 765:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify radio frequency + 766:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + 1759 .loc 1 766 0 + 1760 0004 0F4B ldr r3, .L161 + 1761 0006 9B6A ldr r3, [r3, #40] + 1762 0008 4068 ldr r0, [r0, #4] + 1763 .LVL187: + 1764 000a 9847 blx r3 + 1765 .LVL188: + 1766 000c 0028 cmp r0, #0 + 1767 000e 16D0 beq .L160 + 763:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x07; + 1768 .loc 1 763 0 + 1769 0010 0724 movs r4, #7 + 1770 .L157: + 1771 .LVL189: + ARM GAS /tmp/cczfoKrY.s page 47 + + + 767:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 768:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; // Channel frequency KO + 769:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 770:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 771:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify datarate + 772:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( rxParamSetupReq->Datarate, EU868_RX_MIN_DATARATE, EU868_RX_MAX_DA + 1772 .loc 1 772 0 + 1773 0012 0020 movs r0, #0 + 1774 0014 2856 ldrsb r0, [r5, r0] + 1775 0016 0722 movs r2, #7 + 1776 0018 0021 movs r1, #0 + 1777 001a FFF7FEFF bl RegionCommonValueInRange + 1778 .LVL190: + 1779 001e 0028 cmp r0, #0 + 1780 0020 01D1 bne .L158 + 773:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 774:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFD; // Datarate KO + 1781 .loc 1 774 0 + 1782 0022 0223 movs r3, #2 + 1783 0024 9C43 bics r4, r3 + 1784 .LVL191: + 1785 .L158: + 775:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 776:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 777:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify datarate offset + 778:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, EU868_MIN_RX1_DR_OFFSET, EU868_MAX_RX1 + 1786 .loc 1 778 0 + 1787 0026 0120 movs r0, #1 + 1788 0028 2856 ldrsb r0, [r5, r0] + 1789 002a 0522 movs r2, #5 + 1790 002c 0021 movs r1, #0 + 1791 002e FFF7FEFF bl RegionCommonValueInRange + 1792 .LVL192: + 1793 0032 0028 cmp r0, #0 + 1794 0034 01D1 bne .L159 + 779:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 780:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFB; // Rx1DrOffset range KO + 1795 .loc 1 780 0 + 1796 0036 0423 movs r3, #4 + 1797 0038 9C43 bics r4, r3 + 1798 .LVL193: + 1799 .L159: + 781:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 782:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 783:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return status; + 784:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1800 .loc 1 784 0 + 1801 003a 2000 movs r0, r4 + 1802 @ sp needed + 1803 .LVL194: + 1804 .LVL195: + 1805 003c 70BD pop {r4, r5, r6, pc} + 1806 .LVL196: + 1807 .L160: + 768:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1808 .loc 1 768 0 + 1809 003e 0624 movs r4, #6 + ARM GAS /tmp/cczfoKrY.s page 48 + + + 1810 0040 E7E7 b .L157 + 1811 .L162: + 1812 0042 C046 .align 2 + 1813 .L161: + 1814 0044 00000000 .word Radio + 1815 .cfi_endproc + 1816 .LFE101: + 1818 .section .text.RegionEU868TxParamSetupReq,"ax",%progbits + 1819 .align 1 + 1820 .global RegionEU868TxParamSetupReq + 1821 .syntax unified + 1822 .code 16 + 1823 .thumb_func + 1824 .fpu softvfp + 1826 RegionEU868TxParamSetupReq: + 1827 .LFB103: + 785:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 786:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t RegionEU868NewChannelReq( NewChannelReqParams_t* newChannelReq ) + 787:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 788:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x03; + 789:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelAddParams_t channelAdd; + 790:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelRemoveParams_t channelRemove; + 791:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 792:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( newChannelReq->NewChannel->Frequency == 0 ) + 793:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 794:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelRemove.ChannelId = newChannelReq->ChannelId; + 795:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 796:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Remove + 797:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionEU868ChannelsRemove( &channelRemove ) == false ) + 798:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 799:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFC; + 800:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 801:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 802:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 803:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 804:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.NewChannel = newChannelReq->NewChannel; + 805:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.ChannelId = newChannelReq->ChannelId; + 806:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 807:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** switch( RegionEU868ChannelAdd( &channelAdd ) ) + 808:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 809:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case LORAMAC_STATUS_OK: + 810:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 811:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 812:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 813:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case LORAMAC_STATUS_FREQUENCY_INVALID: + 814:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 815:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; + 816:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 817:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 818:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case LORAMAC_STATUS_DATARATE_INVALID: + 819:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 820:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFD; + 821:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 822:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 823:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + 824:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 825:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFC; + ARM GAS /tmp/cczfoKrY.s page 49 + + + 826:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 827:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 828:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** default: + 829:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 830:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFC; + 831:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 832:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 833:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 834:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 835:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 836:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return status; + 837:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 838:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 839:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t RegionEU868TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) + 840:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1828 .loc 1 840 0 + 1829 .cfi_startproc + 1830 @ args = 0, pretend = 0, frame = 0 + 1831 @ frame_needed = 0, uses_anonymous_args = 0 + 1832 @ link register save eliminated. + 1833 .LVL197: + 841:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return -1; + 1834 .loc 1 841 0 + 1835 0000 0120 movs r0, #1 + 1836 .LVL198: + 842:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1837 .loc 1 842 0 + 1838 0002 4042 rsbs r0, r0, #0 + 1839 @ sp needed + 1840 0004 7047 bx lr + 1841 .cfi_endproc + 1842 .LFE103: + 1844 .section .text.RegionEU868DlChannelReq,"ax",%progbits + 1845 .align 1 + 1846 .global RegionEU868DlChannelReq + 1847 .syntax unified + 1848 .code 16 + 1849 .thumb_func + 1850 .fpu softvfp + 1852 RegionEU868DlChannelReq: + 1853 .LFB104: + 843:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 844:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t RegionEU868DlChannelReq( DlChannelReqParams_t* dlChannelReq ) + 845:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1854 .loc 1 845 0 + 1855 .cfi_startproc + 1856 @ args = 0, pretend = 0, frame = 8 + 1857 @ frame_needed = 0, uses_anonymous_args = 0 + 1858 .LVL199: + 1859 0000 10B5 push {r4, lr} + 1860 .LCFI20: + 1861 .cfi_def_cfa_offset 8 + 1862 .cfi_offset 4, -8 + 1863 .cfi_offset 14, -4 + 1864 0002 82B0 sub sp, sp, #8 + 1865 .LCFI21: + 1866 .cfi_def_cfa_offset 16 + ARM GAS /tmp/cczfoKrY.s page 50 + + + 1867 0004 0400 movs r4, r0 + 1868 .LVL200: + 846:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x03; + 847:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t band = 0; + 1869 .loc 1 847 0 + 1870 0006 6B46 mov r3, sp + 1871 0008 D91D adds r1, r3, #7 + 1872 000a 0023 movs r3, #0 + 1873 000c 0B70 strb r3, [r1] + 848:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 849:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify if the frequency is supported + 850:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( VerifyTxFreq( dlChannelReq->Rx1Frequency, &band ) == false ) + 1874 .loc 1 850 0 + 1875 000e 4068 ldr r0, [r0, #4] + 1876 .LVL201: + 1877 0010 FFF7FEFF bl VerifyTxFreq + 1878 .LVL202: + 1879 0014 0028 cmp r0, #0 + 1880 0016 0ED0 beq .L168 + 846:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x03; + 1881 .loc 1 846 0 + 1882 0018 0320 movs r0, #3 + 1883 .L165: + 1884 .LVL203: + 851:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 852:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFE; + 853:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 854:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 855:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Verify if an uplink frequency exists + 856:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + 1885 .loc 1 856 0 + 1886 001a 2278 ldrb r2, [r4] + 1887 001c 5300 lsls r3, r2, #1 + 1888 001e 9B18 adds r3, r3, r2 + 1889 0020 9900 lsls r1, r3, #2 + 1890 0022 0A4B ldr r3, .L170 + 1891 0024 CB58 ldr r3, [r1, r3] + 1892 0026 002B cmp r3, #0 + 1893 0028 01D1 bne .L166 + 857:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 858:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** status &= 0xFD; + 1894 .loc 1 858 0 + 1895 002a 0233 adds r3, r3, #2 + 1896 002c 9843 bics r0, r3 + 1897 .LVL204: + 1898 .L166: + 859:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 860:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 861:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Apply Rx1 frequency, if the status is OK + 862:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( status == 0x03 ) + 1899 .loc 1 862 0 + 1900 002e 0328 cmp r0, #3 + 1901 0030 03D0 beq .L169 + 1902 .LVL205: + 1903 .L167: + 863:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 864:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + ARM GAS /tmp/cczfoKrY.s page 51 + + + 865:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 866:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 867:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return status; + 868:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1904 .loc 1 868 0 + 1905 0032 02B0 add sp, sp, #8 + 1906 @ sp needed + 1907 0034 10BD pop {r4, pc} + 1908 .LVL206: + 1909 .L168: + 852:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1910 .loc 1 852 0 + 1911 0036 0220 movs r0, #2 + 1912 0038 EFE7 b .L165 + 1913 .LVL207: + 1914 .L169: + 864:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1915 .loc 1 864 0 + 1916 003a 6468 ldr r4, [r4, #4] + 1917 .LVL208: + 1918 003c 5300 lsls r3, r2, #1 + 1919 003e 9A18 adds r2, r3, r2 + 1920 0040 9100 lsls r1, r2, #2 + 1921 0042 024B ldr r3, .L170 + 1922 0044 5B18 adds r3, r3, r1 + 1923 0046 5C60 str r4, [r3, #4] + 1924 0048 F3E7 b .L167 + 1925 .L171: + 1926 004a C046 .align 2 + 1927 .L170: + 1928 004c 00000000 .word Channels + 1929 .cfi_endproc + 1930 .LFE104: + 1932 .global __aeabi_uidivmod + 1933 .section .text.RegionEU868AlternateDr,"ax",%progbits + 1934 .align 1 + 1935 .global RegionEU868AlternateDr + 1936 .syntax unified + 1937 .code 16 + 1938 .thumb_func + 1939 .fpu softvfp + 1941 RegionEU868AlternateDr: + 1942 .LFB105: + 869:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 870:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t RegionEU868AlternateDr( AlternateDrParams_t* alternateDr ) + 871:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 1943 .loc 1 871 0 + 1944 .cfi_startproc + 1945 @ args = 0, pretend = 0, frame = 0 + 1946 @ frame_needed = 0, uses_anonymous_args = 0 + 1947 .LVL209: + 1948 0000 10B5 push {r4, lr} + 1949 .LCFI22: + 1950 .cfi_def_cfa_offset 8 + 1951 .cfi_offset 4, -8 + 1952 .cfi_offset 14, -4 + 1953 .LVL210: + ARM GAS /tmp/cczfoKrY.s page 52 + + + 872:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t datarate = 0; + 873:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 874:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( alternateDr->NbTrials % 48 ) == 0 ) + 1954 .loc 1 874 0 + 1955 0002 0488 ldrh r4, [r0] + 1956 0004 3021 movs r1, #48 + 1957 0006 2000 movs r0, r4 + 1958 .LVL211: + 1959 0008 FFF7FEFF bl __aeabi_uidivmod + 1960 .LVL212: + 1961 000c 89B2 uxth r1, r1 + 1962 000e 0029 cmp r1, #0 + 1963 0010 0ED0 beq .L174 + 875:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 876:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_0; + 877:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 878:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( alternateDr->NbTrials % 32 ) == 0 ) + 1964 .loc 1 878 0 + 1965 0012 E306 lsls r3, r4, #27 + 1966 0014 0ED0 beq .L175 + 879:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 880:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_1; + 881:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 882:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( alternateDr->NbTrials % 24 ) == 0 ) + 1967 .loc 1 882 0 + 1968 0016 1821 movs r1, #24 + 1969 0018 2000 movs r0, r4 + 1970 001a FFF7FEFF bl __aeabi_uidivmod + 1971 .LVL213: + 1972 001e 89B2 uxth r1, r1 + 1973 0020 0029 cmp r1, #0 + 1974 0022 09D0 beq .L176 + 883:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 884:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_2; + 885:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 886:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( alternateDr->NbTrials % 16 ) == 0 ) + 1975 .loc 1 886 0 + 1976 0024 2307 lsls r3, r4, #28 + 1977 0026 09D0 beq .L177 + 887:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 888:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_3; + 889:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 890:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else if( ( alternateDr->NbTrials % 8 ) == 0 ) + 1978 .loc 1 890 0 + 1979 0028 6307 lsls r3, r4, #29 + 1980 002a 09D1 bne .L178 + 891:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 892:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_4; + 1981 .loc 1 892 0 + 1982 002c 0420 movs r0, #4 + 1983 002e 00E0 b .L173 + 1984 .L174: + 876:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1985 .loc 1 876 0 + 1986 0030 0020 movs r0, #0 + 1987 .L173: + 1988 .LVL214: + ARM GAS /tmp/cczfoKrY.s page 53 + + + 893:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 894:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 895:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 896:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_5; + 897:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 898:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return datarate; + 899:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1989 .loc 1 899 0 + 1990 @ sp needed + 1991 0032 10BD pop {r4, pc} + 1992 .LVL215: + 1993 .L175: + 880:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1994 .loc 1 880 0 + 1995 0034 0120 movs r0, #1 + 1996 0036 FCE7 b .L173 + 1997 .L176: + 884:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 1998 .loc 1 884 0 + 1999 0038 0220 movs r0, #2 + 2000 003a FAE7 b .L173 + 2001 .L177: + 888:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2002 .loc 1 888 0 + 2003 003c 0320 movs r0, #3 + 2004 003e F8E7 b .L173 + 2005 .L178: + 896:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2006 .loc 1 896 0 + 2007 0040 0520 movs r0, #5 + 2008 0042 F6E7 b .L173 + 2009 .cfi_endproc + 2010 .LFE105: + 2012 .section .text.RegionEU868CalcBackOff,"ax",%progbits + 2013 .align 1 + 2014 .global RegionEU868CalcBackOff + 2015 .syntax unified + 2016 .code 16 + 2017 .thumb_func + 2018 .fpu softvfp + 2020 RegionEU868CalcBackOff: + 2021 .LFB106: + 900:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 901:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868CalcBackOff( CalcBackOffParams_t* calcBackOff ) + 902:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2022 .loc 1 902 0 + 2023 .cfi_startproc + 2024 @ args = 0, pretend = 0, frame = 24 + 2025 @ frame_needed = 0, uses_anonymous_args = 0 + 2026 .LVL216: + 2027 0000 00B5 push {lr} + 2028 .LCFI23: + 2029 .cfi_def_cfa_offset 4 + 2030 .cfi_offset 14, -4 + 2031 0002 87B0 sub sp, sp, #28 + 2032 .LCFI24: + 2033 .cfi_def_cfa_offset 32 + ARM GAS /tmp/cczfoKrY.s page 54 + + + 903:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonCalcBackOffParams_t calcBackOffParams; + 904:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 905:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.Channels = Channels; + 2034 .loc 1 905 0 + 2035 0004 01AB add r3, sp, #4 + 2036 0006 0A4A ldr r2, .L180 + 2037 0008 0192 str r2, [sp, #4] + 906:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.Bands = Bands; + 2038 .loc 1 906 0 + 2039 000a 0A4A ldr r2, .L180+4 + 2040 000c 0292 str r2, [sp, #8] + 907:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.LastTxIsJoinRequest = calcBackOff->LastTxIsJoinRequest; + 2041 .loc 1 907 0 + 2042 000e 4278 ldrb r2, [r0, #1] + 2043 0010 1A72 strb r2, [r3, #8] + 908:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.Joined = calcBackOff->Joined; + 2044 .loc 1 908 0 + 2045 0012 0278 ldrb r2, [r0] + 2046 0014 5A72 strb r2, [r3, #9] + 909:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.DutyCycleEnabled = calcBackOff->DutyCycleEnabled; + 2047 .loc 1 909 0 + 2048 0016 8278 ldrb r2, [r0, #2] + 2049 0018 9A72 strb r2, [r3, #10] + 910:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.Channel = calcBackOff->Channel; + 2050 .loc 1 910 0 + 2051 001a C278 ldrb r2, [r0, #3] + 2052 001c DA72 strb r2, [r3, #11] + 911:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.ElapsedTime = calcBackOff->ElapsedTime; + 2053 .loc 1 911 0 + 2054 001e 4268 ldr r2, [r0, #4] + 2055 0020 0492 str r2, [sp, #16] + 912:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** calcBackOffParams.TxTimeOnAir = calcBackOff->TxTimeOnAir; + 2056 .loc 1 912 0 + 2057 0022 8268 ldr r2, [r0, #8] + 2058 0024 0592 str r2, [sp, #20] + 913:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 914:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** RegionCommonCalcBackOff( &calcBackOffParams ); + 2059 .loc 1 914 0 + 2060 0026 1800 movs r0, r3 + 2061 .LVL217: + 2062 0028 FFF7FEFF bl RegionCommonCalcBackOff + 2063 .LVL218: + 915:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2064 .loc 1 915 0 + 2065 002c 07B0 add sp, sp, #28 + 2066 @ sp needed + 2067 002e 00BD pop {pc} + 2068 .L181: + 2069 .align 2 + 2070 .L180: + 2071 0030 00000000 .word Channels + 2072 0034 00000000 .word .LANCHOR4 + 2073 .cfi_endproc + 2074 .LFE106: + 2076 .section .text.RegionEU868NextChannel,"ax",%progbits + 2077 .align 1 + 2078 .global RegionEU868NextChannel + ARM GAS /tmp/cczfoKrY.s page 55 + + + 2079 .syntax unified + 2080 .code 16 + 2081 .thumb_func + 2082 .fpu softvfp + 2084 RegionEU868NextChannel: + 2085 .LFB107: + 916:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 917:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, + 918:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2086 .loc 1 918 0 + 2087 .cfi_startproc + 2088 @ args = 0, pretend = 0, frame = 32 + 2089 @ frame_needed = 0, uses_anonymous_args = 0 + 2090 .LVL219: + 2091 0000 F0B5 push {r4, r5, r6, r7, lr} + 2092 .LCFI25: + 2093 .cfi_def_cfa_offset 20 + 2094 .cfi_offset 4, -20 + 2095 .cfi_offset 5, -16 + 2096 .cfi_offset 6, -12 + 2097 .cfi_offset 7, -8 + 2098 .cfi_offset 14, -4 + 2099 0002 DE46 mov lr, fp + 2100 0004 5746 mov r7, r10 + 2101 0006 4E46 mov r6, r9 + 2102 0008 4546 mov r5, r8 + 2103 000a E0B5 push {r5, r6, r7, lr} + 2104 .LCFI26: + 2105 .cfi_def_cfa_offset 36 + 2106 .cfi_offset 8, -36 + 2107 .cfi_offset 9, -32 + 2108 .cfi_offset 10, -28 + 2109 .cfi_offset 11, -24 + 2110 000c 89B0 sub sp, sp, #36 + 2111 .LCFI27: + 2112 .cfi_def_cfa_offset 72 + 2113 000e 0400 movs r4, r0 + 2114 0010 0391 str r1, [sp, #12] + 2115 0012 9346 mov fp, r2 + 2116 0014 1E00 movs r6, r3 + 2117 .LVL220: + 919:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t nbEnabledChannels = 0; + 920:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t delayTx = 0; + 921:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t enabledChannels[EU868_MAX_NB_CHANNELS] = { 0 }; + 2118 .loc 1 921 0 + 2119 0016 1022 movs r2, #16 + 2120 .LVL221: + 2121 0018 0021 movs r1, #0 + 2122 .LVL222: + 2123 001a 04A8 add r0, sp, #16 + 2124 .LVL223: + 2125 001c FFF7FEFF bl memset + 2126 .LVL224: + 922:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** TimerTime_t nextTxDelay = 0; + 923:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 924:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + 2127 .loc 1 924 0 + ARM GAS /tmp/cczfoKrY.s page 56 + + + 2128 0020 0122 movs r2, #1 + 2129 0022 0021 movs r1, #0 + 2130 0024 4A48 ldr r0, .L199 + 2131 0026 FFF7FEFF bl RegionCommonCountChannels + 2132 .LVL225: + 2133 002a 0028 cmp r0, #0 + 2134 002c 04D1 bne .L183 + 925:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Reactivate default channels + 926:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + 2135 .loc 1 926 0 + 2136 002e 484A ldr r2, .L199 + 2137 0030 1388 ldrh r3, [r2] + 2138 0032 0721 movs r1, #7 + 2139 0034 0B43 orrs r3, r1 + 2140 0036 1380 strh r3, [r2] + 2141 .L183: + 927:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 928:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 929:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + 2142 .loc 1 929 0 + 2143 0038 2568 ldr r5, [r4] + 2144 003a 6068 ldr r0, [r4, #4] + 2145 003c FFF7FEFF bl TimerGetElapsedTime + 2146 .LVL226: + 2147 0040 8542 cmp r5, r0 + 2148 0042 65D8 bhi .L184 + 930:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 931:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Reset Aggregated time off + 932:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *aggregatedTimeOff = 0; + 2149 .loc 1 932 0 + 2150 0044 0023 movs r3, #0 + 2151 0046 3360 str r3, [r6] + 933:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 934:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Update bands Time OFF + 935:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCy + 2152 .loc 1 935 0 + 2153 0048 607A ldrb r0, [r4, #9] + 2154 004a A17A ldrb r1, [r4, #10] + 2155 004c 0533 adds r3, r3, #5 + 2156 004e 414A ldr r2, .L199+4 + 2157 0050 FFF7FEFF bl RegionCommonUpdateBandTimeOff + 2158 .LVL227: + 2159 0054 0290 str r0, [sp, #8] + 2160 .LVL228: + 936:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 937:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Search how many channels are enabled + 938:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datar + 2161 .loc 1 938 0 + 2162 0056 637A ldrb r3, [r4, #9] + 2163 0058 9A46 mov r10, r3 + 2164 005a 0823 movs r3, #8 + 2165 005c E356 ldrsb r3, [r4, r3] + 2166 005e 0193 str r3, [sp, #4] + 2167 .LVL229: + 2168 .LBB39: + 2169 .LBB40: + 2170 .LBB41: + ARM GAS /tmp/cczfoKrY.s page 57 + + + 152:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2171 .loc 1 152 0 + 2172 0060 0026 movs r6, #0 + 2173 .LVL230: + 2174 0062 0027 movs r7, #0 + 2175 .LBE41: + 150:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2176 .loc 1 150 0 + 2177 0064 0023 movs r3, #0 + 2178 0066 9946 mov r9, r3 + 149:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t delayTransmission = 0; + 2179 .loc 1 149 0 + 2180 0068 9846 mov r8, r3 + 2181 .LVL231: + 2182 .L185: + 2183 .LBB43: + 152:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2184 .loc 1 152 0 + 2185 006a 0F2F cmp r7, #15 + 2186 006c 49D9 bls .L195 + 2187 .LVL232: + 2188 .LBE43: + 2189 .LBE40: + 2190 .LBE39: + 939:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask, Channels, + 940:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Bands, enabledChannels, &delayTx ); + 941:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 942:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 943:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 944:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** delayTx++; + 945:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx + 946:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 947:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 948:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( nbEnabledChannels > 0 ) + 2191 .loc 1 948 0 + 2192 006e 4346 mov r3, r8 + 2193 0070 002B cmp r3, #0 + 2194 0072 55D0 beq .L192 + 949:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 950:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // We found a valid channel + 951:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + 2195 .loc 1 951 0 + 2196 0074 4146 mov r1, r8 + 2197 0076 0139 subs r1, r1, #1 + 2198 0078 0020 movs r0, #0 + 2199 007a FFF7FEFF bl randr + 2200 .LVL233: + 2201 007e 04AB add r3, sp, #16 + 2202 0080 1B5C ldrb r3, [r3, r0] + 2203 0082 039A ldr r2, [sp, #12] + 2204 0084 1370 strb r3, [r2] + 952:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 953:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *time = 0; + 2205 .loc 1 953 0 + 2206 0086 0023 movs r3, #0 + 2207 0088 5A46 mov r2, fp + 2208 008a 1360 str r3, [r2] + ARM GAS /tmp/cczfoKrY.s page 58 + + + 954:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 2209 .loc 1 954 0 + 2210 008c 0120 movs r0, #1 + 2211 008e 53E0 b .L193 + 2212 .LVL234: + 2213 .L197: + 2214 .LBB46: + 2215 .LBB45: + 2216 .LBB44: + 2217 .LBB42: + 176:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** continue; + 2218 .loc 1 176 0 + 2219 0090 4B46 mov r3, r9 + 2220 0092 0133 adds r3, r3, #1 + 2221 0094 DBB2 uxtb r3, r3 + 2222 0096 9946 mov r9, r3 + 2223 .LVL235: + 2224 .L186: + 154:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2225 .loc 1 154 0 + 2226 0098 0134 adds r4, r4, #1 + 2227 .LVL236: + 2228 009a E4B2 uxtb r4, r4 + 2229 .LVL237: + 2230 .L190: + 2231 009c 0F2C cmp r4, #15 + 2232 009e 32D8 bhi .L196 + 156:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2233 .loc 1 156 0 + 2234 00a0 7300 lsls r3, r6, #1 + 2235 00a2 2B4A ldr r2, .L199 + 2236 00a4 9B5A ldrh r3, [r3, r2] + 2237 00a6 2341 asrs r3, r3, r4 + 2238 00a8 DB07 lsls r3, r3, #31 + 2239 00aa F5D5 bpl .L186 + 158:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the channel is enabled + 2240 .loc 1 158 0 + 2241 00ac 3919 adds r1, r7, r4 + 2242 00ae 4B00 lsls r3, r1, #1 + 2243 00b0 5B18 adds r3, r3, r1 + 2244 00b2 9900 lsls r1, r3, #2 + 2245 00b4 284D ldr r5, .L199+8 + 2246 00b6 4D19 adds r5, r1, r5 + 2247 00b8 2B68 ldr r3, [r5] + 2248 00ba 002B cmp r3, #0 + 2249 00bc ECD0 beq .L186 + 162:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2250 .loc 1 162 0 + 2251 00be 5346 mov r3, r10 + 2252 00c0 002B cmp r3, #0 + 2253 00c2 03D1 bne .L187 + 164:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2254 .loc 1 164 0 + 2255 00c4 0733 adds r3, r3, #7 + 2256 00c6 2341 asrs r3, r3, r4 + 2257 00c8 DB07 lsls r3, r3, #31 + 2258 00ca E5D5 bpl .L186 + ARM GAS /tmp/cczfoKrY.s page 59 + + + 2259 .L187: + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channels[i + j].DrRange.Fields.Max ) == false ) + 2260 .loc 1 169 0 + 2261 00cc 2A7A ldrb r2, [r5, #8] + 2262 00ce 1101 lsls r1, r2, #4 + 2263 00d0 49B2 sxtb r1, r1 + 2264 00d2 0911 asrs r1, r1, #4 + 170:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the current channel selection supports the given datarate + 2265 .loc 1 170 0 + 2266 00d4 52B2 sxtb r2, r2 + 2267 00d6 1211 asrs r2, r2, #4 + 169:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channels[i + j].DrRange.Fields.Max ) == false ) + 2268 .loc 1 169 0 + 2269 00d8 0198 ldr r0, [sp, #4] + 2270 00da FFF7FEFF bl RegionCommonValueInRange + 2271 .LVL238: + 2272 00de 0028 cmp r0, #0 + 2273 00e0 DAD0 beq .L186 + 174:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { // Check if the band is available for transmission + 2274 .loc 1 174 0 + 2275 00e2 6A7A ldrb r2, [r5, #9] + 2276 00e4 1201 lsls r2, r2, #4 + 2277 00e6 1B4B ldr r3, .L199+4 + 2278 00e8 9B18 adds r3, r3, r2 + 2279 00ea DB68 ldr r3, [r3, #12] + 2280 00ec 002B cmp r3, #0 + 2281 00ee CFD1 bne .L197 + 179:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2282 .loc 1 179 0 + 2283 00f0 4346 mov r3, r8 + 2284 00f2 5A1C adds r2, r3, #1 + 2285 .LVL239: + 2286 00f4 E319 adds r3, r4, r7 + 2287 00f6 04A9 add r1, sp, #16 + 2288 .LVL240: + 2289 00f8 4046 mov r0, r8 + 2290 00fa 0B54 strb r3, [r1, r0] + 2291 00fc D3B2 uxtb r3, r2 + 2292 00fe 9846 mov r8, r3 + 2293 0100 CAE7 b .L186 + 2294 .LVL241: + 2295 .L195: + 154:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2296 .loc 1 154 0 + 2297 0102 0024 movs r4, #0 + 2298 0104 CAE7 b .L190 + 2299 .LVL242: + 2300 .L196: + 2301 .LBE42: + 152:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2302 .loc 1 152 0 + 2303 0106 1037 adds r7, r7, #16 + 2304 .LVL243: + 2305 0108 FFB2 uxtb r7, r7 + 2306 .LVL244: + 2307 010a 0136 adds r6, r6, #1 + 2308 .LVL245: + ARM GAS /tmp/cczfoKrY.s page 60 + + + 2309 010c F6B2 uxtb r6, r6 + 2310 .LVL246: + 2311 010e ACE7 b .L185 + 2312 .LVL247: + 2313 .L184: + 2314 .LBE44: + 2315 .LBE45: + 2316 .LBE46: + 945:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2317 .loc 1 945 0 + 2318 0110 2568 ldr r5, [r4] + 2319 0112 6068 ldr r0, [r4, #4] + 2320 0114 FFF7FEFF bl TimerGetElapsedTime + 2321 .LVL248: + 2322 0118 2B1A subs r3, r5, r0 + 2323 011a 0293 str r3, [sp, #8] + 2324 .LVL249: + 944:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx + 2325 .loc 1 944 0 + 2326 011c 0123 movs r3, #1 + 2327 .LVL250: + 2328 011e 9946 mov r9, r3 + 2329 .LVL251: + 2330 .L192: + 955:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 956:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** else + 957:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 958:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( delayTx > 0 ) + 2331 .loc 1 958 0 + 2332 0120 4B46 mov r3, r9 + 2333 0122 002B cmp r3, #0 + 2334 0124 0FD1 bne .L198 + 959:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 960:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Delay transmission due to AggregatedTimeOff or to a band time off + 961:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *time = nextTxDelay; + 962:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 963:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 964:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Datarate not supported by any channel, restore defaults + 965:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + 2335 .loc 1 965 0 + 2336 0126 0A4A ldr r2, .L199 + 2337 0128 1388 ldrh r3, [r2] + 2338 012a 0721 movs r1, #7 + 2339 012c 0B43 orrs r3, r1 + 2340 012e 1380 strh r3, [r2] + 966:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** *time = 0; + 2341 .loc 1 966 0 + 2342 0130 0023 movs r3, #0 + 2343 0132 5A46 mov r2, fp + 2344 0134 1360 str r3, [r2] + 967:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 2345 .loc 1 967 0 + 2346 0136 0020 movs r0, #0 + 2347 .L193: + 2348 .LVL252: + 968:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 969:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 61 + + + 2349 .loc 1 969 0 + 2350 0138 09B0 add sp, sp, #36 + 2351 @ sp needed + 2352 .LVL253: + 2353 013a 3CBC pop {r2, r3, r4, r5} + 2354 013c 9046 mov r8, r2 + 2355 013e 9946 mov r9, r3 + 2356 0140 A246 mov r10, r4 + 2357 0142 AB46 mov fp, r5 + 2358 0144 F0BD pop {r4, r5, r6, r7, pc} + 2359 .LVL254: + 2360 .L198: + 961:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return true; + 2361 .loc 1 961 0 + 2362 0146 5B46 mov r3, fp + 2363 0148 029A ldr r2, [sp, #8] + 2364 014a 1A60 str r2, [r3] + 962:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2365 .loc 1 962 0 + 2366 014c 0120 movs r0, #1 + 2367 014e F3E7 b .L193 + 2368 .L200: + 2369 .align 2 + 2370 .L199: + 2371 0150 00000000 .word .LANCHOR2 + 2372 0154 00000000 .word .LANCHOR4 + 2373 0158 00000000 .word Channels + 2374 .cfi_endproc + 2375 .LFE107: + 2377 .section .text.RegionEU868ChannelAdd,"ax",%progbits + 2378 .align 1 + 2379 .global RegionEU868ChannelAdd + 2380 .syntax unified + 2381 .code 16 + 2382 .thumb_func + 2383 .fpu softvfp + 2385 RegionEU868ChannelAdd: + 2386 .LFB108: + 970:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 971:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** LoRaMacStatus_t RegionEU868ChannelAdd( ChannelAddParams_t* channelAdd ) + 972:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2387 .loc 1 972 0 + 2388 .cfi_startproc + 2389 @ args = 0, pretend = 0, frame = 8 + 2390 @ frame_needed = 0, uses_anonymous_args = 0 + 2391 .LVL255: + 2392 0000 F0B5 push {r4, r5, r6, r7, lr} + 2393 .LCFI28: + 2394 .cfi_def_cfa_offset 20 + 2395 .cfi_offset 4, -20 + 2396 .cfi_offset 5, -16 + 2397 .cfi_offset 6, -12 + 2398 .cfi_offset 7, -8 + 2399 .cfi_offset 14, -4 + 2400 0002 83B0 sub sp, sp, #12 + 2401 .LCFI29: + 2402 .cfi_def_cfa_offset 32 + ARM GAS /tmp/cczfoKrY.s page 62 + + + 2403 0004 0400 movs r4, r0 + 973:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t band = 0; + 2404 .loc 1 973 0 + 2405 0006 6B46 mov r3, sp + 2406 0008 0022 movs r2, #0 + 2407 000a DA71 strb r2, [r3, #7] + 2408 .LVL256: + 974:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool drInvalid = false; + 975:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool freqInvalid = false; + 976:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t id = channelAdd->ChannelId; + 2409 .loc 1 976 0 + 2410 000c 0579 ldrb r5, [r0, #4] + 2411 .LVL257: + 977:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 978:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( id >= EU868_MAX_NB_CHANNELS ) + 2412 .loc 1 978 0 + 2413 000e 0F2D cmp r5, #15 + 2414 0010 66D8 bhi .L211 + 979:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 980:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return LORAMAC_STATUS_PARAMETER_INVALID; + 981:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 982:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 983:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Validate the datarate range + 984:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, EU868_TX_MIN_DATARATE + 2415 .loc 1 984 0 + 2416 0012 0368 ldr r3, [r0] + 2417 0014 187A ldrb r0, [r3, #8] + 2418 .LVL258: + 2419 0016 0001 lsls r0, r0, #4 + 2420 0018 40B2 sxtb r0, r0 + 2421 001a 0011 asrs r0, r0, #4 + 2422 001c 0732 adds r2, r2, #7 + 2423 001e 0021 movs r1, #0 + 2424 0020 FFF7FEFF bl RegionCommonValueInRange + 2425 .LVL259: + 2426 0024 0028 cmp r0, #0 + 2427 0026 2CD0 beq .L212 + 974:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool freqInvalid = false; + 2428 .loc 1 974 0 + 2429 0028 0026 movs r6, #0 + 2430 .L203: + 2431 .LVL260: + 985:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 986:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** drInvalid = true; + 987:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 988:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, EU868_TX_MIN_DATARATE + 2432 .loc 1 988 0 + 2433 002a 2368 ldr r3, [r4] + 2434 002c 0820 movs r0, #8 + 2435 002e 1856 ldrsb r0, [r3, r0] + 2436 0030 0011 asrs r0, r0, #4 + 2437 0032 0722 movs r2, #7 + 2438 0034 0021 movs r1, #0 + 2439 0036 FFF7FEFF bl RegionCommonValueInRange + 2440 .LVL261: + 2441 003a 0028 cmp r0, #0 + 2442 003c 00D1 bne .L204 + ARM GAS /tmp/cczfoKrY.s page 63 + + + 989:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 990:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** drInvalid = true; + 2443 .loc 1 990 0 + 2444 003e 0126 movs r6, #1 + 2445 .LVL262: + 2446 .L204: + 991:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 992:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + 2447 .loc 1 992 0 + 2448 0040 2368 ldr r3, [r4] + 2449 0042 187A ldrb r0, [r3, #8] + 2450 0044 0301 lsls r3, r0, #4 + 2451 0046 5BB2 sxtb r3, r3 + 2452 0048 1B11 asrs r3, r3, #4 + 2453 004a 40B2 sxtb r0, r0 + 2454 004c 0011 asrs r0, r0, #4 + 2455 004e 8342 cmp r3, r0 + 2456 0050 00DD ble .L205 + 993:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 994:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** drInvalid = true; + 2457 .loc 1 994 0 + 2458 0052 0126 movs r6, #1 + 2459 .LVL263: + 2460 .L205: + 995:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 996:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 997:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Default channels don't accept all values + 998:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( id < EU868_NUMB_DEFAULT_CHANNELS ) + 2461 .loc 1 998 0 + 2462 0054 022D cmp r5, #2 + 2463 0056 18D8 bhi .L215 + 999:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1000:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Validate the datarate range for min: must be DR_0 +1001:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + 2464 .loc 1 1001 0 + 2465 0058 002B cmp r3, #0 + 2466 005a 00DD ble .L207 +1002:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1003:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** drInvalid = true; + 2467 .loc 1 1003 0 + 2468 005c 0126 movs r6, #1 + 2469 .LVL264: + 2470 .L207: +1004:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1005:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE +1006:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, EU868_TX_MA + 2471 .loc 1 1006 0 + 2472 005e 0722 movs r2, #7 + 2473 0060 0521 movs r1, #5 + 2474 0062 FFF7FEFF bl RegionCommonValueInRange + 2475 .LVL265: + 2476 0066 0028 cmp r0, #0 + 2477 0068 00D1 bne .L208 +1007:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1008:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** drInvalid = true; + 2478 .loc 1 1008 0 + 2479 006a 0126 movs r6, #1 + ARM GAS /tmp/cczfoKrY.s page 64 + + + 2480 .LVL266: + 2481 .L208: +1009:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1010:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // We are not allowed to change the frequency +1011:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + 2482 .loc 1 1011 0 + 2483 006c 2368 ldr r3, [r4] + 2484 006e 1968 ldr r1, [r3] + 2485 0070 6B00 lsls r3, r5, #1 + 2486 0072 5B19 adds r3, r3, r5 + 2487 0074 9A00 lsls r2, r3, #2 + 2488 0076 1F4B ldr r3, .L225 + 2489 0078 D358 ldr r3, [r2, r3] + 2490 007a 9942 cmp r1, r3 + 2491 007c 03D0 beq .L223 +1012:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1013:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** freqInvalid = true; + 2492 .loc 1 1013 0 + 2493 007e 0127 movs r7, #1 + 2494 0080 04E0 b .L206 + 2495 .LVL267: + 2496 .L212: + 986:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2497 .loc 1 986 0 + 2498 0082 0126 movs r6, #1 + 2499 0084 D1E7 b .L203 + 2500 .LVL268: + 2501 .L223: + 975:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t id = channelAdd->ChannelId; + 2502 .loc 1 975 0 + 2503 0086 0027 movs r7, #0 + 2504 0088 00E0 b .L206 + 2505 .L215: + 2506 008a 0027 movs r7, #0 + 2507 .L206: + 2508 .LVL269: +1014:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1015:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1016:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1017:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Check frequency +1018:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( freqInvalid == false ) + 2509 .loc 1 1018 0 + 2510 008c 002F cmp r7, #0 + 2511 008e 1DD0 beq .L224 + 2512 .LVL270: + 2513 .L209: +1019:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1020:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( VerifyTxFreq( channelAdd->NewChannel->Frequency, &band ) == false ) +1021:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1022:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** freqInvalid = true; +1023:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1024:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1025:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1026:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Check status +1027:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( ( drInvalid == true ) && ( freqInvalid == true ) ) + 2514 .loc 1 1027 0 + 2515 0090 002E cmp r6, #0 + ARM GAS /tmp/cczfoKrY.s page 65 + + + 2516 0092 01D0 beq .L210 + 2517 .loc 1 1027 0 is_stmt 0 discriminator 1 + 2518 0094 002F cmp r7, #0 + 2519 0096 26D1 bne .L220 + 2520 .L210: +1028:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1029:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return LORAMAC_STATUS_FREQ_AND_DR_INVALID; +1030:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1031:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( drInvalid == true ) + 2521 .loc 1 1031 0 is_stmt 1 + 2522 0098 002E cmp r6, #0 + 2523 009a 26D1 bne .L221 +1032:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1033:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return LORAMAC_STATUS_DATARATE_INVALID; +1034:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1035:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( freqInvalid == true ) + 2524 .loc 1 1035 0 + 2525 009c 002F cmp r7, #0 + 2526 009e 26D1 bne .L222 +1036:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1037:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return LORAMAC_STATUS_FREQUENCY_INVALID; +1038:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1039:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1040:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + 2527 .loc 1 1040 0 + 2528 00a0 6B00 lsls r3, r5, #1 + 2529 00a2 5B19 adds r3, r3, r5 + 2530 00a4 9E00 lsls r6, r3, #2 + 2531 .LVL271: + 2532 00a6 134B ldr r3, .L225 + 2533 00a8 F618 adds r6, r6, r3 + 2534 00aa 2168 ldr r1, [r4] + 2535 00ac 0C22 movs r2, #12 + 2536 00ae 3000 movs r0, r6 + 2537 00b0 FFF7FEFF bl memcpy + 2538 .LVL272: +1041:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[id].Band = band; + 2539 .loc 1 1041 0 + 2540 00b4 6B46 mov r3, sp + 2541 00b6 0733 adds r3, r3, #7 + 2542 00b8 1B78 ldrb r3, [r3] + 2543 00ba 7372 strb r3, [r6, #9] +1042:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelsMask[0] |= ( 1 << id ); + 2544 .loc 1 1042 0 + 2545 00bc 0122 movs r2, #1 + 2546 00be AA40 lsls r2, r2, r5 + 2547 00c0 0D49 ldr r1, .L225+4 + 2548 00c2 0B88 ldrh r3, [r1] + 2549 00c4 1343 orrs r3, r2 + 2550 00c6 0B80 strh r3, [r1] +1043:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return LORAMAC_STATUS_OK; + 2551 .loc 1 1043 0 + 2552 00c8 0020 movs r0, #0 + 2553 00ca 0AE0 b .L202 + 2554 .LVL273: + 2555 .L224: +1020:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + ARM GAS /tmp/cczfoKrY.s page 66 + + + 2556 .loc 1 1020 0 + 2557 00cc 2368 ldr r3, [r4] + 2558 00ce 1868 ldr r0, [r3] + 2559 00d0 6B46 mov r3, sp + 2560 00d2 D91D adds r1, r3, #7 + 2561 00d4 FFF7FEFF bl VerifyTxFreq + 2562 .LVL274: + 2563 00d8 0028 cmp r0, #0 + 2564 00da D9D1 bne .L209 +1022:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2565 .loc 1 1022 0 + 2566 00dc 0137 adds r7, r7, #1 + 2567 .LVL275: + 2568 00de D7E7 b .L209 + 2569 .LVL276: + 2570 .L211: + 980:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2571 .loc 1 980 0 + 2572 00e0 0320 movs r0, #3 + 2573 .LVL277: + 2574 .L202: +1044:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2575 .loc 1 1044 0 + 2576 00e2 03B0 add sp, sp, #12 + 2577 @ sp needed + 2578 .LVL278: + 2579 .LVL279: + 2580 00e4 F0BD pop {r4, r5, r6, r7, pc} + 2581 .LVL280: + 2582 .L220: +1029:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2583 .loc 1 1029 0 + 2584 00e6 0620 movs r0, #6 + 2585 00e8 FBE7 b .L202 + 2586 .L221: +1033:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2587 .loc 1 1033 0 + 2588 00ea 0520 movs r0, #5 + 2589 00ec F9E7 b .L202 + 2590 .L222: +1037:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2591 .loc 1 1037 0 + 2592 00ee 0420 movs r0, #4 + 2593 00f0 F7E7 b .L202 + 2594 .L226: + 2595 00f2 C046 .align 2 + 2596 .L225: + 2597 00f4 00000000 .word Channels + 2598 00f8 00000000 .word .LANCHOR2 + 2599 .cfi_endproc + 2600 .LFE108: + 2602 .section .text.RegionEU868ChannelsRemove,"ax",%progbits + 2603 .align 1 + 2604 .global RegionEU868ChannelsRemove + 2605 .syntax unified + 2606 .code 16 + 2607 .thumb_func + ARM GAS /tmp/cczfoKrY.s page 67 + + + 2608 .fpu softvfp + 2610 RegionEU868ChannelsRemove: + 2611 .LFB109: +1045:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1046:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** bool RegionEU868ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +1047:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2612 .loc 1 1047 0 + 2613 .cfi_startproc + 2614 @ args = 0, pretend = 0, frame = 0 + 2615 @ frame_needed = 0, uses_anonymous_args = 0 + 2616 .LVL281: + 2617 0000 10B5 push {r4, lr} + 2618 .LCFI30: + 2619 .cfi_def_cfa_offset 8 + 2620 .cfi_offset 4, -8 + 2621 .cfi_offset 14, -4 +1048:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t id = channelRemove->ChannelId; + 2622 .loc 1 1048 0 + 2623 0002 0478 ldrb r4, [r0] + 2624 .LVL282: +1049:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1050:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( id < EU868_NUMB_DEFAULT_CHANNELS ) + 2625 .loc 1 1050 0 + 2626 0004 022C cmp r4, #2 + 2627 0006 01D8 bhi .L230 +1051:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1052:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return false; + 2628 .loc 1 1052 0 + 2629 0008 0020 movs r0, #0 + 2630 .LVL283: + 2631 .L228: +1053:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1054:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1055:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Remove the channel from the list of channels +1056:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; +1057:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1058:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return RegionCommonChanDisable( ChannelsMask, id, EU868_MAX_NB_CHANNELS ); +1059:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2632 .loc 1 1059 0 + 2633 @ sp needed + 2634 .LVL284: + 2635 000a 10BD pop {r4, pc} + 2636 .LVL285: + 2637 .L230: +1056:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2638 .loc 1 1056 0 + 2639 000c 6300 lsls r3, r4, #1 + 2640 000e 1B19 adds r3, r3, r4 + 2641 0010 9A00 lsls r2, r3, #2 + 2642 0012 0648 ldr r0, .L231 + 2643 .LVL286: + 2644 0014 8018 adds r0, r0, r2 + 2645 0016 0C22 movs r2, #12 + 2646 0018 0021 movs r1, #0 + 2647 001a FFF7FEFF bl memset + 2648 .LVL287: +1058:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + ARM GAS /tmp/cczfoKrY.s page 68 + + + 2649 .loc 1 1058 0 + 2650 001e 1022 movs r2, #16 + 2651 0020 2100 movs r1, r4 + 2652 0022 0348 ldr r0, .L231+4 + 2653 0024 FFF7FEFF bl RegionCommonChanDisable + 2654 .LVL288: + 2655 0028 EFE7 b .L228 + 2656 .L232: + 2657 002a C046 .align 2 + 2658 .L231: + 2659 002c 00000000 .word Channels + 2660 0030 00000000 .word .LANCHOR2 + 2661 .cfi_endproc + 2662 .LFE109: + 2664 .section .text.RegionEU868ApplyCFList,"ax",%progbits + 2665 .align 1 + 2666 .global RegionEU868ApplyCFList + 2667 .syntax unified + 2668 .code 16 + 2669 .thumb_func + 2670 .fpu softvfp + 2672 RegionEU868ApplyCFList: + 2673 .LFB94: + 411:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelParams_t newChannel; + 2674 .loc 1 411 0 + 2675 .cfi_startproc + 2676 @ args = 0, pretend = 0, frame = 24 + 2677 @ frame_needed = 0, uses_anonymous_args = 0 + 2678 .LVL289: + 2679 0000 70B5 push {r4, r5, r6, lr} + 2680 .LCFI31: + 2681 .cfi_def_cfa_offset 16 + 2682 .cfi_offset 4, -16 + 2683 .cfi_offset 5, -12 + 2684 .cfi_offset 6, -8 + 2685 .cfi_offset 14, -4 + 2686 0002 86B0 sub sp, sp, #24 + 2687 .LCFI32: + 2688 .cfi_def_cfa_offset 40 + 2689 0004 0600 movs r6, r0 + 417:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2690 .loc 1 417 0 + 2691 0006 03AB add r3, sp, #12 + 2692 0008 5022 movs r2, #80 + 2693 000a 1A72 strb r2, [r3, #8] + 420:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2694 .loc 1 420 0 + 2695 000c 0379 ldrb r3, [r0, #4] + 2696 000e 102B cmp r3, #16 + 2697 0010 01D0 beq .L242 + 2698 .LVL290: + 2699 .L233: + 461:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2700 .loc 1 461 0 + 2701 0012 06B0 add sp, sp, #24 + 2702 @ sp needed + 2703 .LVL291: + ARM GAS /tmp/cczfoKrY.s page 69 + + + 2704 0014 70BD pop {r4, r5, r6, pc} + 2705 .LVL292: + 2706 .L242: + 2707 .LBB47: + 426:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2708 .loc 1 426 0 + 2709 0016 0324 movs r4, #3 + 2710 0018 0025 movs r5, #0 + 2711 001a 19E0 b .L235 + 2712 .LVL293: + 2713 .L243: + 431:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + 2714 .loc 1 431 0 + 2715 001c 3268 ldr r2, [r6] + 2716 001e 535D ldrb r3, [r2, r5] + 2717 0020 0393 str r3, [sp, #12] + 432:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + 2718 .loc 1 432 0 + 2719 0022 5219 adds r2, r2, r5 + 2720 0024 5178 ldrb r1, [r2, #1] + 2721 0026 0902 lsls r1, r1, #8 + 2722 0028 0B43 orrs r3, r1 + 2723 002a 0393 str r3, [sp, #12] + 433:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Frequency *= 100; + 2724 .loc 1 433 0 + 2725 002c 9278 ldrb r2, [r2, #2] + 2726 002e 1204 lsls r2, r2, #16 + 2727 0030 1343 orrs r3, r2 + 434:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2728 .loc 1 434 0 + 2729 0032 6422 movs r2, #100 + 2730 0034 5343 muls r3, r2 + 2731 0036 0393 str r3, [sp, #12] + 437:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2732 .loc 1 437 0 + 2733 0038 0023 movs r3, #0 + 2734 003a 0493 str r3, [sp, #16] + 2735 003c 11E0 b .L237 + 2736 .L238: + 456:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2737 .loc 1 456 0 + 2738 003e 6B46 mov r3, sp + 2739 0040 1C70 strb r4, [r3] + 458:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2740 .loc 1 458 0 + 2741 0042 6846 mov r0, sp + 2742 0044 FFF7FEFF bl RegionEU868ChannelsRemove + 2743 .LVL294: + 2744 .L239: + 426:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2745 .loc 1 426 0 discriminator 2 + 2746 0048 0335 adds r5, r5, #3 + 2747 .LVL295: + 2748 004a EDB2 uxtb r5, r5 + 2749 .LVL296: + 2750 004c 0134 adds r4, r4, #1 + 2751 .LVL297: + ARM GAS /tmp/cczfoKrY.s page 70 + + + 2752 004e E4B2 uxtb r4, r4 + 2753 .LVL298: + 2754 .L235: + 426:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2755 .loc 1 426 0 is_stmt 0 discriminator 1 + 2756 0050 0F2C cmp r4, #15 + 2757 0052 DED8 bhi .L233 + 428:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2758 .loc 1 428 0 is_stmt 1 + 2759 0054 072C cmp r4, #7 + 2760 0056 E1D9 bls .L243 + 441:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.DrRange.Value = 0; + 2761 .loc 1 441 0 + 2762 0058 03AA add r2, sp, #12 + 2763 005a 0023 movs r3, #0 + 2764 005c 0393 str r3, [sp, #12] + 442:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** newChannel.Rx1Frequency = 0; + 2765 .loc 1 442 0 + 2766 005e 1372 strb r3, [r2, #8] + 443:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2767 .loc 1 443 0 + 2768 0060 0493 str r3, [sp, #16] + 2769 .L237: + 446:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2770 .loc 1 446 0 + 2771 0062 039B ldr r3, [sp, #12] + 2772 0064 002B cmp r3, #0 + 2773 0066 EAD0 beq .L238 + 448:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.ChannelId = chanIdx; + 2774 .loc 1 448 0 + 2775 0068 01A8 add r0, sp, #4 + 2776 006a 03AB add r3, sp, #12 + 2777 006c 0193 str r3, [sp, #4] + 449:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2778 .loc 1 449 0 + 2779 006e 0471 strb r4, [r0, #4] + 452:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2780 .loc 1 452 0 + 2781 0070 FFF7FEFF bl RegionEU868ChannelAdd + 2782 .LVL299: + 2783 0074 E8E7 b .L239 + 2784 .LBE47: + 2785 .cfi_endproc + 2786 .LFE94: + 2788 .section .text.RegionEU868NewChannelReq,"ax",%progbits + 2789 .align 1 + 2790 .global RegionEU868NewChannelReq + 2791 .syntax unified + 2792 .code 16 + 2793 .thumb_func + 2794 .fpu softvfp + 2796 RegionEU868NewChannelReq: + 2797 .LFB102: + 787:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t status = 0x03; + 2798 .loc 1 787 0 + 2799 .cfi_startproc + 2800 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/cczfoKrY.s page 71 + + + 2801 @ frame_needed = 0, uses_anonymous_args = 0 + 2802 .LVL300: + 2803 0000 00B5 push {lr} + 2804 .LCFI33: + 2805 .cfi_def_cfa_offset 4 + 2806 .cfi_offset 14, -4 + 2807 0002 85B0 sub sp, sp, #20 + 2808 .LCFI34: + 2809 .cfi_def_cfa_offset 24 + 2810 .LVL301: + 792:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2811 .loc 1 792 0 + 2812 0004 0368 ldr r3, [r0] + 2813 0006 1A68 ldr r2, [r3] + 2814 0008 002A cmp r2, #0 + 2815 000a 0BD1 bne .L245 + 794:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2816 .loc 1 794 0 + 2817 000c 0379 ldrb r3, [r0, #4] + 2818 000e 01A8 add r0, sp, #4 + 2819 .LVL302: + 2820 0010 0370 strb r3, [r0] + 797:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2821 .loc 1 797 0 + 2822 0012 FFF7FEFF bl RegionEU868ChannelsRemove + 2823 .LVL303: + 2824 0016 0028 cmp r0, #0 + 2825 0018 02D1 bne .L254 + 799:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2826 .loc 1 799 0 + 2827 001a 0020 movs r0, #0 + 2828 .LVL304: + 2829 .L246: + 837:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2830 .loc 1 837 0 + 2831 001c 05B0 add sp, sp, #20 + 2832 @ sp needed + 2833 001e 00BD pop {pc} + 2834 .LVL305: + 2835 .L254: + 788:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelAddParams_t channelAdd; + 2836 .loc 1 788 0 + 2837 0020 0320 movs r0, #3 + 2838 0022 FBE7 b .L246 + 2839 .LVL306: + 2840 .L245: + 804:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** channelAdd.ChannelId = newChannelReq->ChannelId; + 2841 .loc 1 804 0 + 2842 0024 02AA add r2, sp, #8 + 2843 0026 0293 str r3, [sp, #8] + 805:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2844 .loc 1 805 0 + 2845 0028 0379 ldrb r3, [r0, #4] + 2846 002a 1371 strb r3, [r2, #4] + 807:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2847 .loc 1 807 0 + 2848 002c 1000 movs r0, r2 + ARM GAS /tmp/cczfoKrY.s page 72 + + + 2849 .LVL307: + 2850 002e FFF7FEFF bl RegionEU868ChannelAdd + 2851 .LVL308: + 2852 0032 0428 cmp r0, #4 + 2853 0034 0ED0 beq .L253 + 2854 0036 05D9 bls .L255 + 2855 0038 0528 cmp r0, #5 + 2856 003a 07D0 beq .L250 + 2857 003c 0628 cmp r0, #6 + 2858 003e 07D1 bne .L247 + 2859 .LVL309: + 825:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 2860 .loc 1 825 0 + 2861 0040 0020 movs r0, #0 + 826:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2862 .loc 1 826 0 + 2863 0042 EBE7 b .L246 + 2864 .LVL310: + 2865 .L255: + 807:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2866 .loc 1 807 0 + 2867 0044 0028 cmp r0, #0 + 2868 0046 03D1 bne .L247 + 788:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** ChannelAddParams_t channelAdd; + 2869 .loc 1 788 0 + 2870 0048 0320 movs r0, #3 + 2871 004a E7E7 b .L246 + 2872 .L250: + 2873 .LVL311: + 820:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 2874 .loc 1 820 0 + 2875 004c 0120 movs r0, #1 + 821:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2876 .loc 1 821 0 + 2877 004e E5E7 b .L246 + 2878 .LVL312: + 2879 .L247: + 830:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 2880 .loc 1 830 0 + 2881 0050 0020 movs r0, #0 + 831:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2882 .loc 1 831 0 + 2883 0052 E3E7 b .L246 + 2884 .LVL313: + 2885 .L253: + 815:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** break; + 2886 .loc 1 815 0 + 2887 0054 0220 movs r0, #2 + 2888 0056 E1E7 b .L246 + 2889 .cfi_endproc + 2890 .LFE102: + 2892 .section .text.RegionEU868SetContinuousWave,"ax",%progbits + 2893 .align 1 + 2894 .global RegionEU868SetContinuousWave + 2895 .syntax unified + 2896 .code 16 + 2897 .thumb_func + ARM GAS /tmp/cczfoKrY.s page 73 + + + 2898 .fpu softvfp + 2900 RegionEU868SetContinuousWave: + 2901 .LFB110: +1060:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1061:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** void RegionEU868SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +1062:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2902 .loc 1 1062 0 + 2903 .cfi_startproc + 2904 @ args = 0, pretend = 0, frame = 0 + 2905 @ frame_needed = 0, uses_anonymous_args = 0 + 2906 .LVL314: + 2907 0000 70B5 push {r4, r5, r6, lr} + 2908 .LCFI35: + 2909 .cfi_def_cfa_offset 16 + 2910 .cfi_offset 4, -16 + 2911 .cfi_offset 5, -12 + 2912 .cfi_offset 6, -8 + 2913 .cfi_offset 14, -4 + 2914 0002 0400 movs r4, r0 +1063:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->C + 2915 .loc 1 1063 0 + 2916 0004 0225 movs r5, #2 + 2917 0006 4557 ldrsb r5, [r0, r5] + 2918 0008 0278 ldrb r2, [r0] + 2919 000a 5300 lsls r3, r2, #1 + 2920 000c 9B18 adds r3, r3, r2 + 2921 000e 9900 lsls r1, r3, #2 + 2922 0010 0E4B ldr r3, .L258 + 2923 0012 5B18 adds r3, r3, r1 + 2924 0014 597A ldrb r1, [r3, #9] + 2925 0016 0901 lsls r1, r1, #4 + 2926 0018 0D4B ldr r3, .L258+4 + 2927 001a 5B18 adds r3, r3, r1 + 2928 001c 9B78 ldrb r3, [r3, #2] + 2929 001e 5BB2 sxtb r3, r3 + 2930 .LVL315: + 2931 .LBB48: + 2932 .LBB49: + 102:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** + 2933 .loc 1 102 0 + 2934 0020 281C adds r0, r5, #0 + 2935 .LVL316: + 2936 0022 9D42 cmp r5, r3 + 2937 0024 00DA bge .L257 + 2938 0026 181C adds r0, r3, #0 + 2939 .L257: + 2940 0028 40B2 sxtb r0, r0 + 2941 .LVL317: + 2942 .LBE49: + 2943 .LBE48: +1064:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t phyTxPower = 0; +1065:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint32_t frequency = Channels[continuousWave->Channel].Frequency; + 2944 .loc 1 1065 0 + 2945 002a 5300 lsls r3, r2, #1 + 2946 002c 9B18 adds r3, r3, r2 + 2947 002e 9A00 lsls r2, r3, #2 + 2948 0030 064B ldr r3, .L258 + ARM GAS /tmp/cczfoKrY.s page 74 + + + 2949 0032 D558 ldr r5, [r2, r3] + 2950 .LVL318: +1066:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1067:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** // Calculate physical TX power +1068:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWav + 2951 .loc 1 1068 0 + 2952 0034 A268 ldr r2, [r4, #8] + 2953 0036 6168 ldr r1, [r4, #4] + 2954 0038 FFF7FEFF bl RegionCommonComputeTxPower + 2955 .LVL319: + 2956 003c 0100 movs r1, r0 + 2957 .LVL320: +1069:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1070:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); + 2958 .loc 1 1070 0 + 2959 003e 054B ldr r3, .L258+8 + 2960 0040 5B6C ldr r3, [r3, #68] + 2961 0042 A289 ldrh r2, [r4, #12] + 2962 0044 2800 movs r0, r5 + 2963 0046 9847 blx r3 + 2964 .LVL321: +1071:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 2965 .loc 1 1071 0 + 2966 @ sp needed + 2967 .LVL322: + 2968 .LVL323: + 2969 0048 70BD pop {r4, r5, r6, pc} + 2970 .L259: + 2971 004a C046 .align 2 + 2972 .L258: + 2973 004c 00000000 .word Channels + 2974 0050 00000000 .word .LANCHOR4 + 2975 0054 00000000 .word Radio + 2976 .cfi_endproc + 2977 .LFE110: + 2979 .section .text.RegionEU868ApplyDrOffset,"ax",%progbits + 2980 .align 1 + 2981 .global RegionEU868ApplyDrOffset + 2982 .syntax unified + 2983 .code 16 + 2984 .thumb_func + 2985 .fpu softvfp + 2987 RegionEU868ApplyDrOffset: + 2988 .LFB111: +1072:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1073:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** uint8_t RegionEU868ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +1074:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { + 2989 .loc 1 1074 0 + 2990 .cfi_startproc + 2991 @ args = 0, pretend = 0, frame = 0 + 2992 @ frame_needed = 0, uses_anonymous_args = 0 + 2993 @ link register save eliminated. + 2994 .LVL324: +1075:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** int8_t datarate = dr - drOffset; + 2995 .loc 1 1075 0 + 2996 0000 881A subs r0, r1, r2 + 2997 .LVL325: + ARM GAS /tmp/cczfoKrY.s page 75 + + + 2998 0002 40B2 sxtb r0, r0 + 2999 .LVL326: +1076:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** +1077:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** if( datarate < 0 ) + 3000 .loc 1 1077 0 + 3001 0004 0028 cmp r0, #0 + 3002 0006 01DB blt .L263 + 3003 .LVL327: + 3004 .L261: +1078:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** { +1079:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** datarate = DR_0; +1080:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } +1081:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** return datarate; + 3005 .loc 1 1081 0 + 3006 0008 C0B2 uxtb r0, r0 +1082:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 3007 .loc 1 1082 0 + 3008 @ sp needed + 3009 000a 7047 bx lr + 3010 .L263: +1079:./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c **** } + 3011 .loc 1 1079 0 + 3012 000c 0020 movs r0, #0 + 3013 .LVL328: + 3014 000e FBE7 b .L261 + 3015 .cfi_endproc + 3016 .LFE111: + 3018 .section .rodata + 3019 .align 2 + 3020 .set .LANCHOR5,. + 0 + 3021 .LC0: + 3022 0000 A027BE33 .word 868100000 + 3023 0004 00000000 .word 0 + 3024 0008 50 .byte 80 + 3025 0009 01 .byte 1 + 3026 000a 0000 .space 2 + 3027 .LC1: + 3028 000c E034C133 .word 868300000 + 3029 0010 00000000 .word 0 + 3030 0014 50 .byte 80 + 3031 0015 01 .byte 1 + 3032 0016 0000 .space 2 + 3033 .LC2: + 3034 0018 2042C433 .word 868500000 + 3035 001c 00000000 .word 0 + 3036 0020 50 .byte 80 + 3037 0021 01 .byte 1 + 3038 0022 0000 .space 2 + 3039 .section .bss.Channels,"aw",%nobits + 3040 .align 2 + 3043 Channels: + 3044 0000 00000000 .space 192 + 3044 00000000 + 3044 00000000 + 3044 00000000 + 3044 00000000 + 3045 .section .bss.ChannelsDefaultMask,"aw",%nobits + ARM GAS /tmp/cczfoKrY.s page 76 + + + 3046 .align 2 + 3047 .set .LANCHOR3,. + 0 + 3050 ChannelsDefaultMask: + 3051 0000 0000 .space 2 + 3052 .section .bss.ChannelsMask,"aw",%nobits + 3053 .align 2 + 3054 .set .LANCHOR2,. + 0 + 3057 ChannelsMask: + 3058 0000 0000 .space 2 + 3059 .section .data.Bands,"aw",%progbits + 3060 .align 2 + 3061 .set .LANCHOR4,. + 0 + 3064 Bands: + 3065 0000 6400 .short 100 + 3066 0002 00 .byte 0 + 3067 0003 00 .space 1 + 3068 0004 00000000 .word 0 + 3069 0008 00000000 .word 0 + 3070 000c 00000000 .space 4 + 3071 0010 6400 .short 100 + 3072 0012 00 .byte 0 + 3073 0013 00 .space 1 + 3074 0014 00000000 .word 0 + 3075 0018 00000000 .word 0 + 3076 001c 00000000 .space 4 + 3077 0020 E803 .short 1000 + 3078 0022 00 .byte 0 + 3079 0023 00 .space 1 + 3080 0024 00000000 .word 0 + 3081 0028 00000000 .word 0 + 3082 002c 00000000 .space 4 + 3083 0030 0A00 .short 10 + 3084 0032 00 .byte 0 + 3085 0033 00 .space 1 + 3086 0034 00000000 .word 0 + 3087 0038 00000000 .word 0 + 3088 003c 00000000 .space 4 + 3089 0040 6400 .short 100 + 3090 0042 00 .byte 0 + 3091 0043 00 .space 1 + 3092 0044 00000000 .word 0 + 3093 0048 00000000 .word 0 + 3094 004c 00000000 .space 4 + 3095 .section .rodata.BandwidthsEU868,"a",%progbits + 3096 .align 2 + 3097 .set .LANCHOR6,. + 0 + 3100 BandwidthsEU868: + 3101 0000 48E80100 .word 125000 + 3102 0004 48E80100 .word 125000 + 3103 0008 48E80100 .word 125000 + 3104 000c 48E80100 .word 125000 + 3105 0010 48E80100 .word 125000 + 3106 0014 48E80100 .word 125000 + 3107 0018 90D00300 .word 250000 + 3108 001c 00000000 .word 0 + 3109 .section .rodata.DataratesEU868,"a",%progbits + 3110 .align 2 + ARM GAS /tmp/cczfoKrY.s page 77 + + + 3111 .set .LANCHOR7,. + 0 + 3114 DataratesEU868: + 3115 0000 0C .byte 12 + 3116 0001 0B .byte 11 + 3117 0002 0A .byte 10 + 3118 0003 09 .byte 9 + 3119 0004 08 .byte 8 + 3120 0005 07 .byte 7 + 3121 0006 07 .byte 7 + 3122 0007 32 .byte 50 + 3123 .section .rodata.MaxPayloadOfDatarateEU868,"a",%progbits + 3124 .align 2 + 3125 .set .LANCHOR0,. + 0 + 3128 MaxPayloadOfDatarateEU868: + 3129 0000 33 .byte 51 + 3130 0001 33 .byte 51 + 3131 0002 33 .byte 51 + 3132 0003 73 .byte 115 + 3133 0004 F2 .byte -14 + 3134 0005 F2 .byte -14 + 3135 0006 F2 .byte -14 + 3136 0007 F2 .byte -14 + 3137 .section .rodata.MaxPayloadOfDatarateRepeaterEU868,"a",%progbits + 3138 .align 2 + 3139 .set .LANCHOR1,. + 0 + 3142 MaxPayloadOfDatarateRepeaterEU868: + 3143 0000 33 .byte 51 + 3144 0001 33 .byte 51 + 3145 0002 33 .byte 51 + 3146 0003 73 .byte 115 + 3147 0004 DE .byte -34 + 3148 0005 DE .byte -34 + 3149 0006 DE .byte -34 + 3150 0007 DE .byte -34 + 3151 .text + 3152 .Letext0: + 3153 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3154 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 3155 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 3156 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 3157 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 3158 .file 7 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3159 .file 8 "/usr/arm-none-eabi/include/math.h" + 3160 .file 9 "Middlewares/Third_Party/Lora/Phy/radio.h" + 3161 .file 10 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 3162 .file 11 "Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 3163 .file 12 "./Middlewares/Third_Party/Lora/Mac/region/Region.h" + 3164 .file 13 "./Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h" + 3165 .file 14 "./Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h" + 3166 .file 15 "" + 3167 .file 16 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + ARM GAS /tmp/cczfoKrY.s page 78 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 RegionEU868.c + /tmp/cczfoKrY.s:16 .text.VerifyTxFreq:0000000000000000 $t + /tmp/cczfoKrY.s:22 .text.VerifyTxFreq:0000000000000000 VerifyTxFreq + /tmp/cczfoKrY.s:128 .text.VerifyTxFreq:0000000000000078 $d + /tmp/cczfoKrY.s:145 .text.RegionEU868GetPhyParam:0000000000000000 $t + /tmp/cczfoKrY.s:152 .text.RegionEU868GetPhyParam:0000000000000000 RegionEU868GetPhyParam + /tmp/cczfoKrY.s:179 .rodata.RegionEU868GetPhyParam:0000000000000000 $d + /tmp/cczfoKrY.s:367 .text.RegionEU868GetPhyParam:000000000000009c $d + /tmp/cczfoKrY.s:3043 .bss.Channels:0000000000000000 Channels + /tmp/cczfoKrY.s:383 .text.RegionEU868SetBandTxDone:0000000000000000 $t + /tmp/cczfoKrY.s:390 .text.RegionEU868SetBandTxDone:0000000000000000 RegionEU868SetBandTxDone + /tmp/cczfoKrY.s:424 .text.RegionEU868SetBandTxDone:0000000000000020 $d + /tmp/cczfoKrY.s:430 .text.RegionEU868InitDefaults:0000000000000000 $t + /tmp/cczfoKrY.s:437 .text.RegionEU868InitDefaults:0000000000000000 RegionEU868InitDefaults + /tmp/cczfoKrY.s:504 .text.RegionEU868InitDefaults:0000000000000044 $d + /tmp/cczfoKrY.s:512 .text.RegionEU868Verify:0000000000000000 $t + /tmp/cczfoKrY.s:519 .text.RegionEU868Verify:0000000000000000 RegionEU868Verify + /tmp/cczfoKrY.s:542 .rodata.RegionEU868Verify:0000000000000000 $d + /tmp/cczfoKrY.s:661 .text.RegionEU868Verify:0000000000000078 $d + /tmp/cczfoKrY.s:666 .text.RegionEU868ChanMaskSet:0000000000000000 $t + /tmp/cczfoKrY.s:673 .text.RegionEU868ChanMaskSet:0000000000000000 RegionEU868ChanMaskSet + /tmp/cczfoKrY.s:726 .text.RegionEU868ChanMaskSet:000000000000002c $d + /tmp/cczfoKrY.s:732 .text.RegionEU868AdrNext:0000000000000000 $t + /tmp/cczfoKrY.s:739 .text.RegionEU868AdrNext:0000000000000000 RegionEU868AdrNext + /tmp/cczfoKrY.s:870 .text.RegionEU868AdrNext:000000000000007c $d + /tmp/cczfoKrY.s:875 .text.RegionEU868ComputeRxWindowParameters:0000000000000000 $t + /tmp/cczfoKrY.s:882 .text.RegionEU868ComputeRxWindowParameters:0000000000000000 RegionEU868ComputeRxWindowParameters + /tmp/cczfoKrY.s:1004 .text.RegionEU868ComputeRxWindowParameters:000000000000007c $d + /tmp/cczfoKrY.s:1013 .text.RegionEU868RxConfig:0000000000000000 $t + /tmp/cczfoKrY.s:1020 .text.RegionEU868RxConfig:0000000000000000 RegionEU868RxConfig + /tmp/cczfoKrY.s:1202 .text.RegionEU868RxConfig:00000000000000dc $d + /tmp/cczfoKrY.s:1213 .text.RegionEU868TxConfig:0000000000000000 $t + /tmp/cczfoKrY.s:1220 .text.RegionEU868TxConfig:0000000000000000 RegionEU868TxConfig + /tmp/cczfoKrY.s:1441 .text.RegionEU868TxConfig:000000000000010c $d + /tmp/cczfoKrY.s:1454 .text.RegionEU868LinkAdrReq:0000000000000000 $t + /tmp/cczfoKrY.s:1461 .text.RegionEU868LinkAdrReq:0000000000000000 RegionEU868LinkAdrReq + /tmp/cczfoKrY.s:1730 .text.RegionEU868LinkAdrReq:0000000000000140 $d + /tmp/cczfoKrY.s:1736 .text.RegionEU868RxParamSetupReq:0000000000000000 $t + /tmp/cczfoKrY.s:1743 .text.RegionEU868RxParamSetupReq:0000000000000000 RegionEU868RxParamSetupReq + /tmp/cczfoKrY.s:1814 .text.RegionEU868RxParamSetupReq:0000000000000044 $d + /tmp/cczfoKrY.s:1819 .text.RegionEU868TxParamSetupReq:0000000000000000 $t + /tmp/cczfoKrY.s:1826 .text.RegionEU868TxParamSetupReq:0000000000000000 RegionEU868TxParamSetupReq + /tmp/cczfoKrY.s:1845 .text.RegionEU868DlChannelReq:0000000000000000 $t + /tmp/cczfoKrY.s:1852 .text.RegionEU868DlChannelReq:0000000000000000 RegionEU868DlChannelReq + /tmp/cczfoKrY.s:1928 .text.RegionEU868DlChannelReq:000000000000004c $d + /tmp/cczfoKrY.s:1934 .text.RegionEU868AlternateDr:0000000000000000 $t + /tmp/cczfoKrY.s:1941 .text.RegionEU868AlternateDr:0000000000000000 RegionEU868AlternateDr + /tmp/cczfoKrY.s:2013 .text.RegionEU868CalcBackOff:0000000000000000 $t + /tmp/cczfoKrY.s:2020 .text.RegionEU868CalcBackOff:0000000000000000 RegionEU868CalcBackOff + /tmp/cczfoKrY.s:2071 .text.RegionEU868CalcBackOff:0000000000000030 $d + /tmp/cczfoKrY.s:2077 .text.RegionEU868NextChannel:0000000000000000 $t + /tmp/cczfoKrY.s:2084 .text.RegionEU868NextChannel:0000000000000000 RegionEU868NextChannel + /tmp/cczfoKrY.s:2371 .text.RegionEU868NextChannel:0000000000000150 $d + /tmp/cczfoKrY.s:2378 .text.RegionEU868ChannelAdd:0000000000000000 $t + /tmp/cczfoKrY.s:2385 .text.RegionEU868ChannelAdd:0000000000000000 RegionEU868ChannelAdd + /tmp/cczfoKrY.s:2597 .text.RegionEU868ChannelAdd:00000000000000f4 $d + ARM GAS /tmp/cczfoKrY.s page 79 + + + /tmp/cczfoKrY.s:2603 .text.RegionEU868ChannelsRemove:0000000000000000 $t + /tmp/cczfoKrY.s:2610 .text.RegionEU868ChannelsRemove:0000000000000000 RegionEU868ChannelsRemove + /tmp/cczfoKrY.s:2659 .text.RegionEU868ChannelsRemove:000000000000002c $d + /tmp/cczfoKrY.s:2665 .text.RegionEU868ApplyCFList:0000000000000000 $t + /tmp/cczfoKrY.s:2672 .text.RegionEU868ApplyCFList:0000000000000000 RegionEU868ApplyCFList + /tmp/cczfoKrY.s:2789 .text.RegionEU868NewChannelReq:0000000000000000 $t + /tmp/cczfoKrY.s:2796 .text.RegionEU868NewChannelReq:0000000000000000 RegionEU868NewChannelReq + /tmp/cczfoKrY.s:2893 .text.RegionEU868SetContinuousWave:0000000000000000 $t + /tmp/cczfoKrY.s:2900 .text.RegionEU868SetContinuousWave:0000000000000000 RegionEU868SetContinuousWave + /tmp/cczfoKrY.s:2973 .text.RegionEU868SetContinuousWave:000000000000004c $d + /tmp/cczfoKrY.s:2980 .text.RegionEU868ApplyDrOffset:0000000000000000 $t + /tmp/cczfoKrY.s:2987 .text.RegionEU868ApplyDrOffset:0000000000000000 RegionEU868ApplyDrOffset + /tmp/cczfoKrY.s:3019 .rodata:0000000000000000 $d + /tmp/cczfoKrY.s:3040 .bss.Channels:0000000000000000 $d + /tmp/cczfoKrY.s:3046 .bss.ChannelsDefaultMask:0000000000000000 $d + /tmp/cczfoKrY.s:3050 .bss.ChannelsDefaultMask:0000000000000000 ChannelsDefaultMask + /tmp/cczfoKrY.s:3053 .bss.ChannelsMask:0000000000000000 $d + /tmp/cczfoKrY.s:3057 .bss.ChannelsMask:0000000000000000 ChannelsMask + /tmp/cczfoKrY.s:3060 .data.Bands:0000000000000000 $d + /tmp/cczfoKrY.s:3064 .data.Bands:0000000000000000 Bands + /tmp/cczfoKrY.s:3096 .rodata.BandwidthsEU868:0000000000000000 $d + /tmp/cczfoKrY.s:3100 .rodata.BandwidthsEU868:0000000000000000 BandwidthsEU868 + /tmp/cczfoKrY.s:3110 .rodata.DataratesEU868:0000000000000000 $d + /tmp/cczfoKrY.s:3114 .rodata.DataratesEU868:0000000000000000 DataratesEU868 + /tmp/cczfoKrY.s:3124 .rodata.MaxPayloadOfDatarateEU868:0000000000000000 $d + /tmp/cczfoKrY.s:3128 .rodata.MaxPayloadOfDatarateEU868:0000000000000000 MaxPayloadOfDatarateEU868 + /tmp/cczfoKrY.s:3138 .rodata.MaxPayloadOfDatarateRepeaterEU868:0000000000000000 $d + /tmp/cczfoKrY.s:3142 .rodata.MaxPayloadOfDatarateRepeaterEU868:0000000000000000 MaxPayloadOfDatarateRepeaterEU868 + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +Radio +randr +RegionCommonSetBandTxDone +RegionCommonChanMaskCopy +RegionCommonValueInRange +RegionCommonComputeSymbolTimeLoRa +RegionCommonComputeRxWindowParameters +RegionCommonComputeSymbolTimeFsk +RegionCommonComputeTxPower +RegionCommonParseLinkAdrReq +RegionCommonLinkAdrReqVerifyParams +__aeabi_uidivmod +RegionCommonCalcBackOff +memset +RegionCommonCountChannels +TimerGetElapsedTime +RegionCommonUpdateBandTimeOff +memcpy +RegionCommonChanDisable diff --git a/build/aes.d b/build/aes.d new file mode 100644 index 0000000..633a59a --- /dev/null +++ b/build/aes.d @@ -0,0 +1,4 @@ +build/aes.d: Middlewares/Third_Party/Lora/Crypto/aes.c \ + Middlewares/Third_Party/Lora/Crypto/aes.h + +Middlewares/Third_Party/Lora/Crypto/aes.h: diff --git a/build/aes.lst b/build/aes.lst new file mode 100644 index 0000000..aa21dd7 --- /dev/null +++ b/build/aes.lst @@ -0,0 +1,2834 @@ +ARM GAS /tmp/ccJ0d890.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "aes.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.xor_block,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 xor_block: + 23 .LFB2: + 24 .file 1 "./Middlewares/Third_Party/Lora/Crypto/aes.c" + 1:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* + 2:./Middlewares/Third_Party/Lora/Crypto/aes.c **** --------------------------------------------------------------------------- + 3:./Middlewares/Third_Party/Lora/Crypto/aes.c **** Copyright (c) 1998-2008, Brian Gladman, Worcester, UK. All rights reserved. + 4:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 5:./Middlewares/Third_Party/Lora/Crypto/aes.c **** LICENSE TERMS + 6:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 7:./Middlewares/Third_Party/Lora/Crypto/aes.c **** The redistribution and use of this software (with or without changes) + 8:./Middlewares/Third_Party/Lora/Crypto/aes.c **** is allowed without the payment of fees or royalties provided that: + 9:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 10:./Middlewares/Third_Party/Lora/Crypto/aes.c **** 1. source code distributions include the above copyright notice, this + 11:./Middlewares/Third_Party/Lora/Crypto/aes.c **** list of conditions and the following disclaimer; + 12:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 13:./Middlewares/Third_Party/Lora/Crypto/aes.c **** 2. binary distributions include the above copyright notice, this list + 14:./Middlewares/Third_Party/Lora/Crypto/aes.c **** of conditions and the following disclaimer in their documentation; + 15:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 16:./Middlewares/Third_Party/Lora/Crypto/aes.c **** 3. the name of the copyright holder is not used to endorse products + 17:./Middlewares/Third_Party/Lora/Crypto/aes.c **** built using this software without specific written permission. + 18:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 19:./Middlewares/Third_Party/Lora/Crypto/aes.c **** DISCLAIMER + 20:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 21:./Middlewares/Third_Party/Lora/Crypto/aes.c **** This software is provided 'as is' with no explicit or implied warranties + 22:./Middlewares/Third_Party/Lora/Crypto/aes.c **** in respect of its properties, including, but not limited to, correctness + 23:./Middlewares/Third_Party/Lora/Crypto/aes.c **** and/or fitness for purpose. + 24:./Middlewares/Third_Party/Lora/Crypto/aes.c **** --------------------------------------------------------------------------- + 25:./Middlewares/Third_Party/Lora/Crypto/aes.c **** Issue 09/09/2006 + 26:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 27:./Middlewares/Third_Party/Lora/Crypto/aes.c **** This is an AES implementation that uses only 8-bit byte operations on the + 28:./Middlewares/Third_Party/Lora/Crypto/aes.c **** cipher state (there are options to use 32-bit types if available). + 29:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 30:./Middlewares/Third_Party/Lora/Crypto/aes.c **** The combination of mix columns and byte substitution used here is based on + 31:./Middlewares/Third_Party/Lora/Crypto/aes.c **** that developed by Karl Malbrain. His contribution is acknowledged. + 32:./Middlewares/Third_Party/Lora/Crypto/aes.c **** */ + 33:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 34:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* define if you have a fast memcpy function on your system */ + ARM GAS /tmp/ccJ0d890.s page 2 + + + 35:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if 0 + 36:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define HAVE_MEMCPY + 37:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # include + 38:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # if defined( _MSC_VER ) + 39:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # include + 40:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # pragma intrinsic( memcpy ) + 41:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # endif + 42:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 43:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 44:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 45:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #include + 46:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #include + 47:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 48:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* define if you have fast 32-bit types on your system */ + 49:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if 0 + 50:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define HAVE_UINT_32T + 51:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 52:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 53:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* define if you don't want any tables */ + 54:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if 1 + 55:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define USE_TABLES + 56:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 57:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 58:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* On Intel Core 2 duo VERSION_1 is faster */ + 59:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 60:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* alternative versions (test for performance on your system) */ + 61:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if 1 + 62:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define VERSION_1 + 63:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 64:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 65:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #include "aes.h" + 66:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 67:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //#if defined( HAVE_UINT_32T ) + 68:./Middlewares/Third_Party/Lora/Crypto/aes.c **** // typedef unsigned long uint32_t; + 69:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //#endif + 70:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 71:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* functions for finite field multiplication in the AES Galois field */ + 72:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 73:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define WPOLY 0x011b + 74:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define BPOLY 0x1b + 75:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define DPOLY 0x008d + 76:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 77:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f1(x) (x) + 78:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f2(x) ((x << 1) ^ (((x >> 7) & 1) * WPOLY)) + 79:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f4(x) ((x << 2) ^ (((x >> 6) & 1) * WPOLY) ^ (((x >> 6) & 2) * WPOLY)) + 80:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f8(x) ((x << 3) ^ (((x >> 5) & 1) * WPOLY) ^ (((x >> 5) & 2) * WPOLY) \ + 81:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ^ (((x >> 5) & 4) * WPOLY)) + 82:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define d2(x) (((x) >> 1) ^ ((x) & 1 ? DPOLY : 0)) + 83:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 84:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f3(x) (f2(x) ^ x) + 85:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define f9(x) (f8(x) ^ x) + 86:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define fb(x) (f8(x) ^ f2(x) ^ x) + 87:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define fd(x) (f8(x) ^ f4(x) ^ x) + 88:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define fe(x) (f8(x) ^ f4(x) ^ f2(x)) + 89:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 90:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( USE_TABLES ) + 91:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + ARM GAS /tmp/ccJ0d890.s page 3 + + + 92:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define sb_data(w) { /* S Box data values */ \ + 93:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x63), w(0x7c), w(0x77), w(0x7b), w(0xf2), w(0x6b), w(0x6f), w(0xc5),\ + 94:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x30), w(0x01), w(0x67), w(0x2b), w(0xfe), w(0xd7), w(0xab), w(0x76),\ + 95:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xca), w(0x82), w(0xc9), w(0x7d), w(0xfa), w(0x59), w(0x47), w(0xf0),\ + 96:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xad), w(0xd4), w(0xa2), w(0xaf), w(0x9c), w(0xa4), w(0x72), w(0xc0),\ + 97:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xb7), w(0xfd), w(0x93), w(0x26), w(0x36), w(0x3f), w(0xf7), w(0xcc),\ + 98:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x34), w(0xa5), w(0xe5), w(0xf1), w(0x71), w(0xd8), w(0x31), w(0x15),\ + 99:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x04), w(0xc7), w(0x23), w(0xc3), w(0x18), w(0x96), w(0x05), w(0x9a),\ + 100:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x07), w(0x12), w(0x80), w(0xe2), w(0xeb), w(0x27), w(0xb2), w(0x75),\ + 101:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x09), w(0x83), w(0x2c), w(0x1a), w(0x1b), w(0x6e), w(0x5a), w(0xa0),\ + 102:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x52), w(0x3b), w(0xd6), w(0xb3), w(0x29), w(0xe3), w(0x2f), w(0x84),\ + 103:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x53), w(0xd1), w(0x00), w(0xed), w(0x20), w(0xfc), w(0xb1), w(0x5b),\ + 104:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x6a), w(0xcb), w(0xbe), w(0x39), w(0x4a), w(0x4c), w(0x58), w(0xcf),\ + 105:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xd0), w(0xef), w(0xaa), w(0xfb), w(0x43), w(0x4d), w(0x33), w(0x85),\ + 106:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x45), w(0xf9), w(0x02), w(0x7f), w(0x50), w(0x3c), w(0x9f), w(0xa8),\ + 107:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x51), w(0xa3), w(0x40), w(0x8f), w(0x92), w(0x9d), w(0x38), w(0xf5),\ + 108:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xbc), w(0xb6), w(0xda), w(0x21), w(0x10), w(0xff), w(0xf3), w(0xd2),\ + 109:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xcd), w(0x0c), w(0x13), w(0xec), w(0x5f), w(0x97), w(0x44), w(0x17),\ + 110:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc4), w(0xa7), w(0x7e), w(0x3d), w(0x64), w(0x5d), w(0x19), w(0x73),\ + 111:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x60), w(0x81), w(0x4f), w(0xdc), w(0x22), w(0x2a), w(0x90), w(0x88),\ + 112:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x46), w(0xee), w(0xb8), w(0x14), w(0xde), w(0x5e), w(0x0b), w(0xdb),\ + 113:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe0), w(0x32), w(0x3a), w(0x0a), w(0x49), w(0x06), w(0x24), w(0x5c),\ + 114:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc2), w(0xd3), w(0xac), w(0x62), w(0x91), w(0x95), w(0xe4), w(0x79),\ + 115:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe7), w(0xc8), w(0x37), w(0x6d), w(0x8d), w(0xd5), w(0x4e), w(0xa9),\ + 116:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x6c), w(0x56), w(0xf4), w(0xea), w(0x65), w(0x7a), w(0xae), w(0x08),\ + 117:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xba), w(0x78), w(0x25), w(0x2e), w(0x1c), w(0xa6), w(0xb4), w(0xc6),\ + 118:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe8), w(0xdd), w(0x74), w(0x1f), w(0x4b), w(0xbd), w(0x8b), w(0x8a),\ + 119:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x70), w(0x3e), w(0xb5), w(0x66), w(0x48), w(0x03), w(0xf6), w(0x0e),\ + 120:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x61), w(0x35), w(0x57), w(0xb9), w(0x86), w(0xc1), w(0x1d), w(0x9e),\ + 121:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe1), w(0xf8), w(0x98), w(0x11), w(0x69), w(0xd9), w(0x8e), w(0x94),\ + 122:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x9b), w(0x1e), w(0x87), w(0xe9), w(0xce), w(0x55), w(0x28), w(0xdf),\ + 123:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x8c), w(0xa1), w(0x89), w(0x0d), w(0xbf), w(0xe6), w(0x42), w(0x68),\ + 124:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x41), w(0x99), w(0x2d), w(0x0f), w(0xb0), w(0x54), w(0xbb), w(0x16) } + 125:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 126:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define isb_data(w) { /* inverse S Box data values */ \ + 127:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x52), w(0x09), w(0x6a), w(0xd5), w(0x30), w(0x36), w(0xa5), w(0x38),\ + 128:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xbf), w(0x40), w(0xa3), w(0x9e), w(0x81), w(0xf3), w(0xd7), w(0xfb),\ + 129:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x7c), w(0xe3), w(0x39), w(0x82), w(0x9b), w(0x2f), w(0xff), w(0x87),\ + 130:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x34), w(0x8e), w(0x43), w(0x44), w(0xc4), w(0xde), w(0xe9), w(0xcb),\ + 131:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x54), w(0x7b), w(0x94), w(0x32), w(0xa6), w(0xc2), w(0x23), w(0x3d),\ + 132:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xee), w(0x4c), w(0x95), w(0x0b), w(0x42), w(0xfa), w(0xc3), w(0x4e),\ + 133:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x08), w(0x2e), w(0xa1), w(0x66), w(0x28), w(0xd9), w(0x24), w(0xb2),\ + 134:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x76), w(0x5b), w(0xa2), w(0x49), w(0x6d), w(0x8b), w(0xd1), w(0x25),\ + 135:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x72), w(0xf8), w(0xf6), w(0x64), w(0x86), w(0x68), w(0x98), w(0x16),\ + 136:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xd4), w(0xa4), w(0x5c), w(0xcc), w(0x5d), w(0x65), w(0xb6), w(0x92),\ + 137:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x6c), w(0x70), w(0x48), w(0x50), w(0xfd), w(0xed), w(0xb9), w(0xda),\ + 138:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x5e), w(0x15), w(0x46), w(0x57), w(0xa7), w(0x8d), w(0x9d), w(0x84),\ + 139:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x90), w(0xd8), w(0xab), w(0x00), w(0x8c), w(0xbc), w(0xd3), w(0x0a),\ + 140:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xf7), w(0xe4), w(0x58), w(0x05), w(0xb8), w(0xb3), w(0x45), w(0x06),\ + 141:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xd0), w(0x2c), w(0x1e), w(0x8f), w(0xca), w(0x3f), w(0x0f), w(0x02),\ + 142:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc1), w(0xaf), w(0xbd), w(0x03), w(0x01), w(0x13), w(0x8a), w(0x6b),\ + 143:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x3a), w(0x91), w(0x11), w(0x41), w(0x4f), w(0x67), w(0xdc), w(0xea),\ + 144:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x97), w(0xf2), w(0xcf), w(0xce), w(0xf0), w(0xb4), w(0xe6), w(0x73),\ + 145:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x96), w(0xac), w(0x74), w(0x22), w(0xe7), w(0xad), w(0x35), w(0x85),\ + 146:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe2), w(0xf9), w(0x37), w(0xe8), w(0x1c), w(0x75), w(0xdf), w(0x6e),\ + 147:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x47), w(0xf1), w(0x1a), w(0x71), w(0x1d), w(0x29), w(0xc5), w(0x89),\ + 148:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x6f), w(0xb7), w(0x62), w(0x0e), w(0xaa), w(0x18), w(0xbe), w(0x1b),\ + ARM GAS /tmp/ccJ0d890.s page 4 + + + 149:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xfc), w(0x56), w(0x3e), w(0x4b), w(0xc6), w(0xd2), w(0x79), w(0x20),\ + 150:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x9a), w(0xdb), w(0xc0), w(0xfe), w(0x78), w(0xcd), w(0x5a), w(0xf4),\ + 151:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x1f), w(0xdd), w(0xa8), w(0x33), w(0x88), w(0x07), w(0xc7), w(0x31),\ + 152:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xb1), w(0x12), w(0x10), w(0x59), w(0x27), w(0x80), w(0xec), w(0x5f),\ + 153:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x60), w(0x51), w(0x7f), w(0xa9), w(0x19), w(0xb5), w(0x4a), w(0x0d),\ + 154:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x2d), w(0xe5), w(0x7a), w(0x9f), w(0x93), w(0xc9), w(0x9c), w(0xef),\ + 155:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xa0), w(0xe0), w(0x3b), w(0x4d), w(0xae), w(0x2a), w(0xf5), w(0xb0),\ + 156:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc8), w(0xeb), w(0xbb), w(0x3c), w(0x83), w(0x53), w(0x99), w(0x61),\ + 157:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x17), w(0x2b), w(0x04), w(0x7e), w(0xba), w(0x77), w(0xd6), w(0x26),\ + 158:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe1), w(0x69), w(0x14), w(0x63), w(0x55), w(0x21), w(0x0c), w(0x7d) } + 159:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 160:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define mm_data(w) { /* basic data for forming finite field tables */ \ + 161:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x00), w(0x01), w(0x02), w(0x03), w(0x04), w(0x05), w(0x06), w(0x07),\ + 162:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x08), w(0x09), w(0x0a), w(0x0b), w(0x0c), w(0x0d), w(0x0e), w(0x0f),\ + 163:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x10), w(0x11), w(0x12), w(0x13), w(0x14), w(0x15), w(0x16), w(0x17),\ + 164:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x18), w(0x19), w(0x1a), w(0x1b), w(0x1c), w(0x1d), w(0x1e), w(0x1f),\ + 165:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x20), w(0x21), w(0x22), w(0x23), w(0x24), w(0x25), w(0x26), w(0x27),\ + 166:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x28), w(0x29), w(0x2a), w(0x2b), w(0x2c), w(0x2d), w(0x2e), w(0x2f),\ + 167:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x30), w(0x31), w(0x32), w(0x33), w(0x34), w(0x35), w(0x36), w(0x37),\ + 168:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x38), w(0x39), w(0x3a), w(0x3b), w(0x3c), w(0x3d), w(0x3e), w(0x3f),\ + 169:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x40), w(0x41), w(0x42), w(0x43), w(0x44), w(0x45), w(0x46), w(0x47),\ + 170:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x48), w(0x49), w(0x4a), w(0x4b), w(0x4c), w(0x4d), w(0x4e), w(0x4f),\ + 171:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x50), w(0x51), w(0x52), w(0x53), w(0x54), w(0x55), w(0x56), w(0x57),\ + 172:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x58), w(0x59), w(0x5a), w(0x5b), w(0x5c), w(0x5d), w(0x5e), w(0x5f),\ + 173:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x60), w(0x61), w(0x62), w(0x63), w(0x64), w(0x65), w(0x66), w(0x67),\ + 174:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x68), w(0x69), w(0x6a), w(0x6b), w(0x6c), w(0x6d), w(0x6e), w(0x6f),\ + 175:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x70), w(0x71), w(0x72), w(0x73), w(0x74), w(0x75), w(0x76), w(0x77),\ + 176:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x78), w(0x79), w(0x7a), w(0x7b), w(0x7c), w(0x7d), w(0x7e), w(0x7f),\ + 177:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x80), w(0x81), w(0x82), w(0x83), w(0x84), w(0x85), w(0x86), w(0x87),\ + 178:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x88), w(0x89), w(0x8a), w(0x8b), w(0x8c), w(0x8d), w(0x8e), w(0x8f),\ + 179:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x90), w(0x91), w(0x92), w(0x93), w(0x94), w(0x95), w(0x96), w(0x97),\ + 180:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0x98), w(0x99), w(0x9a), w(0x9b), w(0x9c), w(0x9d), w(0x9e), w(0x9f),\ + 181:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xa0), w(0xa1), w(0xa2), w(0xa3), w(0xa4), w(0xa5), w(0xa6), w(0xa7),\ + 182:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xa8), w(0xa9), w(0xaa), w(0xab), w(0xac), w(0xad), w(0xae), w(0xaf),\ + 183:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xb0), w(0xb1), w(0xb2), w(0xb3), w(0xb4), w(0xb5), w(0xb6), w(0xb7),\ + 184:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xb8), w(0xb9), w(0xba), w(0xbb), w(0xbc), w(0xbd), w(0xbe), w(0xbf),\ + 185:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc0), w(0xc1), w(0xc2), w(0xc3), w(0xc4), w(0xc5), w(0xc6), w(0xc7),\ + 186:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xc8), w(0xc9), w(0xca), w(0xcb), w(0xcc), w(0xcd), w(0xce), w(0xcf),\ + 187:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xd0), w(0xd1), w(0xd2), w(0xd3), w(0xd4), w(0xd5), w(0xd6), w(0xd7),\ + 188:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xd8), w(0xd9), w(0xda), w(0xdb), w(0xdc), w(0xdd), w(0xde), w(0xdf),\ + 189:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe0), w(0xe1), w(0xe2), w(0xe3), w(0xe4), w(0xe5), w(0xe6), w(0xe7),\ + 190:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xe8), w(0xe9), w(0xea), w(0xeb), w(0xec), w(0xed), w(0xee), w(0xef),\ + 191:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xf0), w(0xf1), w(0xf2), w(0xf3), w(0xf4), w(0xf5), w(0xf6), w(0xf7),\ + 192:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w(0xf8), w(0xf9), w(0xfa), w(0xfb), w(0xfc), w(0xfd), w(0xfe), w(0xff) } + 193:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 194:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t sbox[256] = sb_data(f1); + 195:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 196:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 197:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t isbox[256] = isb_data(f1); + 198:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 199:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 200:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfm2_sbox[256] = sb_data(f2); + 201:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfm3_sbox[256] = sb_data(f3); + 202:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 203:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 204:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfmul_9[256] = mm_data(f9); + 205:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfmul_b[256] = mm_data(fb); + ARM GAS /tmp/ccJ0d890.s page 5 + + + 206:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfmul_d[256] = mm_data(fd); + 207:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static const uint8_t gfmul_e[256] = mm_data(fe); + 208:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 209:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 210:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define s_box(x) sbox[(x)] + 211:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 212:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define is_box(x) isbox[(x)] + 213:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 214:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm2_sb(x) gfm2_sbox[(x)] + 215:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm3_sb(x) gfm3_sbox[(x)] + 216:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 217:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_9(x) gfmul_9[(x)] + 218:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_b(x) gfmul_b[(x)] + 219:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_d(x) gfmul_d[(x)] + 220:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_e(x) gfmul_e[(x)] + 221:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 222:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 223:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 224:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* this is the high bit of x right shifted by 1 */ + 225:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* position. Since the starting polynomial has */ + 226:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* 9 bits (0x11b), this right shift keeps the */ + 227:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* values of all top bits within a byte */ + 228:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 229:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static uint8_t hibit(const uint8_t x) + 230:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t r = (uint8_t)((x >> 1) | (x >> 2)); + 231:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 232:./Middlewares/Third_Party/Lora/Crypto/aes.c **** r |= (r >> 2); + 233:./Middlewares/Third_Party/Lora/Crypto/aes.c **** r |= (r >> 4); + 234:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return (r + 1) >> 1; + 235:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 236:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 237:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* return the inverse of the finite field element x */ + 238:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 239:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static uint8_t gf_inv(const uint8_t x) + 240:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t p1 = x, p2 = BPOLY, n1 = hibit(x), n2 = 0x80, v1 = 1, v2 = 0; + 241:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 242:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if(x < 2) + 243:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return x; + 244:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 245:./Middlewares/Third_Party/Lora/Crypto/aes.c **** for( ; ; ) + 246:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 247:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if(n1) + 248:./Middlewares/Third_Party/Lora/Crypto/aes.c **** while(n2 >= n1) /* divide polynomial p2 by p1 */ + 249:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 250:./Middlewares/Third_Party/Lora/Crypto/aes.c **** n2 /= n1; /* shift smaller polynomial left */ + 251:./Middlewares/Third_Party/Lora/Crypto/aes.c **** p2 ^= (p1 * n2) & 0xff; /* and remove from larger one */ + 252:./Middlewares/Third_Party/Lora/Crypto/aes.c **** v2 ^= (v1 * n2); /* shift accumulated value and */ + 253:./Middlewares/Third_Party/Lora/Crypto/aes.c **** n2 = hibit(p2); /* add into result */ + 254:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 255:./Middlewares/Third_Party/Lora/Crypto/aes.c **** else + 256:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return v1; + 257:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 258:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if(n2) /* repeat with values swapped */ + 259:./Middlewares/Third_Party/Lora/Crypto/aes.c **** while(n1 >= n2) + 260:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 261:./Middlewares/Third_Party/Lora/Crypto/aes.c **** n1 /= n2; + 262:./Middlewares/Third_Party/Lora/Crypto/aes.c **** p1 ^= p2 * n1; + ARM GAS /tmp/ccJ0d890.s page 6 + + + 263:./Middlewares/Third_Party/Lora/Crypto/aes.c **** v1 ^= v2 * n1; + 264:./Middlewares/Third_Party/Lora/Crypto/aes.c **** n1 = hibit(p1); + 265:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 266:./Middlewares/Third_Party/Lora/Crypto/aes.c **** else + 267:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return v2; + 268:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 269:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 270:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 271:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* The forward and inverse affine transformations used in the S-box */ + 272:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint8_t fwd_affine(const uint8_t x) + 273:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 274:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_UINT_32T ) + 275:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint32_t w = x; + 276:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w ^= (w << 1) ^ (w << 2) ^ (w << 3) ^ (w << 4); + 277:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0x63 ^ ((w ^ (w >> 8)) & 0xff); + 278:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 279:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0x63 ^ x ^ (x << 1) ^ (x << 2) ^ (x << 3) ^ (x << 4) + 280:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ^ (x >> 7) ^ (x >> 6) ^ (x >> 5) ^ (x >> 4); + 281:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 282:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 283:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 284:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint8_t inv_affine(const uint8_t x) + 285:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 286:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_UINT_32T ) + 287:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint32_t w = x; + 288:./Middlewares/Third_Party/Lora/Crypto/aes.c **** w = (w << 1) ^ (w << 3) ^ (w << 6); + 289:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0x05 ^ ((w ^ (w >> 8)) & 0xff); + 290:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 291:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0x05 ^ (x << 1) ^ (x << 3) ^ (x << 6) + 292:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ^ (x >> 7) ^ (x >> 5) ^ (x >> 2); + 293:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 294:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 295:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 296:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define s_box(x) fwd_affine(gf_inv(x)) + 297:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define is_box(x) gf_inv(inv_affine(x)) + 298:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm2_sb(x) f2(s_box(x)) + 299:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm3_sb(x) f3(s_box(x)) + 300:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_9(x) f9(x) + 301:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_b(x) fb(x) + 302:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_d(x) fd(x) + 303:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #define gfm_e(x) fe(x) + 304:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 305:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 306:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 307:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_MEMCPY ) + 308:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define block_copy_nn(d, s, l) memcpy(d, s, l) + 309:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define block_copy(d, s) memcpy(d, s, N_BLOCK) + 310:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 311:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define block_copy_nn(d, s, l) copy_block_nn(d, s, l) + 312:./Middlewares/Third_Party/Lora/Crypto/aes.c **** # define block_copy(d, s) copy_block(d, s) + 313:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 314:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 315:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void copy_block( void *d, const void *s ) + 316:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 317:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_UINT_32T ) + 318:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 0] = ((uint32_t*)s)[ 0]; + 319:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 1] = ((uint32_t*)s)[ 1]; + ARM GAS /tmp/ccJ0d890.s page 7 + + + 320:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 2] = ((uint32_t*)s)[ 2]; + 321:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 3] = ((uint32_t*)s)[ 3]; + 322:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 323:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 0] = ((uint8_t*)s)[ 0]; + 324:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1]; + 325:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2]; + 326:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3]; + 327:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4]; + 328:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5]; + 329:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6]; + 330:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7]; + 331:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8]; + 332:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9]; + 333:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[10] = ((uint8_t*)s)[10]; + 334:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[11] = ((uint8_t*)s)[11]; + 335:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[12] = ((uint8_t*)s)[12]; + 336:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[13] = ((uint8_t*)s)[13]; + 337:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[14] = ((uint8_t*)s)[14]; + 338:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[15] = ((uint8_t*)s)[15]; + 339:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 340:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 341:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 342:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void copy_block_nn( uint8_t * d, const uint8_t *s, uint8_t nn ) + 343:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 344:./Middlewares/Third_Party/Lora/Crypto/aes.c **** while( nn-- ) + 345:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //*((uint8_t*)d)++ = *((uint8_t*)s)++; + 346:./Middlewares/Third_Party/Lora/Crypto/aes.c **** *d++ = *s++; + 347:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 348:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 349:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void xor_block( void *d, const void *s ) + 350:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 25 .loc 1 350 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: + 351:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_UINT_32T ) + 352:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 0] ^= ((uint32_t*)s)[ 0]; + 353:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 1] ^= ((uint32_t*)s)[ 1]; + 354:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 2] ^= ((uint32_t*)s)[ 2]; + 355:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 3] ^= ((uint32_t*)s)[ 3]; + 356:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 357:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 0] ^= ((uint8_t*)s)[ 0]; + 31 .loc 1 357 0 + 32 0000 0B78 ldrb r3, [r1] + 33 0002 0278 ldrb r2, [r0] + 34 0004 5340 eors r3, r2 + 35 0006 0370 strb r3, [r0] + 358:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 1] ^= ((uint8_t*)s)[ 1]; + 36 .loc 1 358 0 + 37 0008 4B78 ldrb r3, [r1, #1] + 38 000a 4278 ldrb r2, [r0, #1] + 39 000c 5340 eors r3, r2 + 40 000e 4370 strb r3, [r0, #1] + 359:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 2] ^= ((uint8_t*)s)[ 2]; + 41 .loc 1 359 0 + ARM GAS /tmp/ccJ0d890.s page 8 + + + 42 0010 8B78 ldrb r3, [r1, #2] + 43 0012 8278 ldrb r2, [r0, #2] + 44 0014 5340 eors r3, r2 + 45 0016 8370 strb r3, [r0, #2] + 360:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 3] ^= ((uint8_t*)s)[ 3]; + 46 .loc 1 360 0 + 47 0018 CB78 ldrb r3, [r1, #3] + 48 001a C278 ldrb r2, [r0, #3] + 49 001c 5340 eors r3, r2 + 50 001e C370 strb r3, [r0, #3] + 361:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 4] ^= ((uint8_t*)s)[ 4]; + 51 .loc 1 361 0 + 52 0020 0B79 ldrb r3, [r1, #4] + 53 0022 0279 ldrb r2, [r0, #4] + 54 0024 5340 eors r3, r2 + 55 0026 0371 strb r3, [r0, #4] + 362:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 5] ^= ((uint8_t*)s)[ 5]; + 56 .loc 1 362 0 + 57 0028 4B79 ldrb r3, [r1, #5] + 58 002a 4279 ldrb r2, [r0, #5] + 59 002c 5340 eors r3, r2 + 60 002e 4371 strb r3, [r0, #5] + 363:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 6] ^= ((uint8_t*)s)[ 6]; + 61 .loc 1 363 0 + 62 0030 8B79 ldrb r3, [r1, #6] + 63 0032 8279 ldrb r2, [r0, #6] + 64 0034 5340 eors r3, r2 + 65 0036 8371 strb r3, [r0, #6] + 364:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 7] ^= ((uint8_t*)s)[ 7]; + 66 .loc 1 364 0 + 67 0038 CB79 ldrb r3, [r1, #7] + 68 003a C279 ldrb r2, [r0, #7] + 69 003c 5340 eors r3, r2 + 70 003e C371 strb r3, [r0, #7] + 365:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 8] ^= ((uint8_t*)s)[ 8]; + 71 .loc 1 365 0 + 72 0040 0B7A ldrb r3, [r1, #8] + 73 0042 027A ldrb r2, [r0, #8] + 74 0044 5340 eors r3, r2 + 75 0046 0372 strb r3, [r0, #8] + 366:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 9] ^= ((uint8_t*)s)[ 9]; + 76 .loc 1 366 0 + 77 0048 4B7A ldrb r3, [r1, #9] + 78 004a 427A ldrb r2, [r0, #9] + 79 004c 5340 eors r3, r2 + 80 004e 4372 strb r3, [r0, #9] + 367:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[10] ^= ((uint8_t*)s)[10]; + 81 .loc 1 367 0 + 82 0050 8B7A ldrb r3, [r1, #10] + 83 0052 827A ldrb r2, [r0, #10] + 84 0054 5340 eors r3, r2 + 85 0056 8372 strb r3, [r0, #10] + 368:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[11] ^= ((uint8_t*)s)[11]; + 86 .loc 1 368 0 + 87 0058 CB7A ldrb r3, [r1, #11] + 88 005a C27A ldrb r2, [r0, #11] + 89 005c 5340 eors r3, r2 + ARM GAS /tmp/ccJ0d890.s page 9 + + + 90 005e C372 strb r3, [r0, #11] + 369:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[12] ^= ((uint8_t*)s)[12]; + 91 .loc 1 369 0 + 92 0060 0B7B ldrb r3, [r1, #12] + 93 0062 027B ldrb r2, [r0, #12] + 94 0064 5340 eors r3, r2 + 95 0066 0373 strb r3, [r0, #12] + 370:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[13] ^= ((uint8_t*)s)[13]; + 96 .loc 1 370 0 + 97 0068 4B7B ldrb r3, [r1, #13] + 98 006a 427B ldrb r2, [r0, #13] + 99 006c 5340 eors r3, r2 + 100 006e 4373 strb r3, [r0, #13] + 371:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[14] ^= ((uint8_t*)s)[14]; + 101 .loc 1 371 0 + 102 0070 8B7B ldrb r3, [r1, #14] + 103 0072 827B ldrb r2, [r0, #14] + 104 0074 5340 eors r3, r2 + 105 0076 8373 strb r3, [r0, #14] + 372:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[15] ^= ((uint8_t*)s)[15]; + 106 .loc 1 372 0 + 107 0078 CB7B ldrb r3, [r1, #15] + 108 007a C27B ldrb r2, [r0, #15] + 109 007c 5340 eors r3, r2 + 110 007e C373 strb r3, [r0, #15] + 373:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 374:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 111 .loc 1 374 0 + 112 @ sp needed + 113 0080 7047 bx lr + 114 .cfi_endproc + 115 .LFE2: + 117 .section .text.copy_and_key,"ax",%progbits + 118 .align 1 + 119 .syntax unified + 120 .code 16 + 121 .thumb_func + 122 .fpu softvfp + 124 copy_and_key: + 125 .LFB3: + 375:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 376:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void copy_and_key( void *d, const void *s, const void *k ) + 377:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 126 .loc 1 377 0 + 127 .cfi_startproc + 128 @ args = 0, pretend = 0, frame = 0 + 129 @ frame_needed = 0, uses_anonymous_args = 0 + 130 .LVL1: + 131 0000 10B5 push {r4, lr} + 132 .LCFI0: + 133 .cfi_def_cfa_offset 8 + 134 .cfi_offset 4, -8 + 135 .cfi_offset 14, -4 + 378:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( HAVE_UINT_32T ) + 379:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 0] = ((uint32_t*)s)[ 0] ^ ((uint32_t*)k)[ 0]; + 380:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 1] = ((uint32_t*)s)[ 1] ^ ((uint32_t*)k)[ 1]; + 381:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 2] = ((uint32_t*)s)[ 2] ^ ((uint32_t*)k)[ 2]; + ARM GAS /tmp/ccJ0d890.s page 10 + + + 382:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint32_t*)d)[ 3] = ((uint32_t*)s)[ 3] ^ ((uint32_t*)k)[ 3]; + 383:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #elif 1 + 384:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 0] = ((uint8_t*)s)[ 0] ^ ((uint8_t*)k)[ 0]; + 136 .loc 1 384 0 + 137 0002 0B78 ldrb r3, [r1] + 138 0004 1478 ldrb r4, [r2] + 139 0006 6340 eors r3, r4 + 140 0008 0370 strb r3, [r0] + 385:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1] ^ ((uint8_t*)k)[ 1]; + 141 .loc 1 385 0 + 142 000a 4B78 ldrb r3, [r1, #1] + 143 000c 5478 ldrb r4, [r2, #1] + 144 000e 6340 eors r3, r4 + 145 0010 4370 strb r3, [r0, #1] + 386:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2] ^ ((uint8_t*)k)[ 2]; + 146 .loc 1 386 0 + 147 0012 8B78 ldrb r3, [r1, #2] + 148 0014 9478 ldrb r4, [r2, #2] + 149 0016 6340 eors r3, r4 + 150 0018 8370 strb r3, [r0, #2] + 387:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3] ^ ((uint8_t*)k)[ 3]; + 151 .loc 1 387 0 + 152 001a CB78 ldrb r3, [r1, #3] + 153 001c D478 ldrb r4, [r2, #3] + 154 001e 6340 eors r3, r4 + 155 0020 C370 strb r3, [r0, #3] + 388:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4] ^ ((uint8_t*)k)[ 4]; + 156 .loc 1 388 0 + 157 0022 0B79 ldrb r3, [r1, #4] + 158 0024 1479 ldrb r4, [r2, #4] + 159 0026 6340 eors r3, r4 + 160 0028 0371 strb r3, [r0, #4] + 389:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5] ^ ((uint8_t*)k)[ 5]; + 161 .loc 1 389 0 + 162 002a 4B79 ldrb r3, [r1, #5] + 163 002c 5479 ldrb r4, [r2, #5] + 164 002e 6340 eors r3, r4 + 165 0030 4371 strb r3, [r0, #5] + 390:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6] ^ ((uint8_t*)k)[ 6]; + 166 .loc 1 390 0 + 167 0032 8B79 ldrb r3, [r1, #6] + 168 0034 9479 ldrb r4, [r2, #6] + 169 0036 6340 eors r3, r4 + 170 0038 8371 strb r3, [r0, #6] + 391:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7] ^ ((uint8_t*)k)[ 7]; + 171 .loc 1 391 0 + 172 003a CB79 ldrb r3, [r1, #7] + 173 003c D479 ldrb r4, [r2, #7] + 174 003e 6340 eors r3, r4 + 175 0040 C371 strb r3, [r0, #7] + 392:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8] ^ ((uint8_t*)k)[ 8]; + 176 .loc 1 392 0 + 177 0042 0B7A ldrb r3, [r1, #8] + 178 0044 147A ldrb r4, [r2, #8] + 179 0046 6340 eors r3, r4 + 180 0048 0372 strb r3, [r0, #8] + 393:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9] ^ ((uint8_t*)k)[ 9]; + ARM GAS /tmp/ccJ0d890.s page 11 + + + 181 .loc 1 393 0 + 182 004a 4B7A ldrb r3, [r1, #9] + 183 004c 547A ldrb r4, [r2, #9] + 184 004e 6340 eors r3, r4 + 185 0050 4372 strb r3, [r0, #9] + 394:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[10] = ((uint8_t*)s)[10] ^ ((uint8_t*)k)[10]; + 186 .loc 1 394 0 + 187 0052 8B7A ldrb r3, [r1, #10] + 188 0054 947A ldrb r4, [r2, #10] + 189 0056 6340 eors r3, r4 + 190 0058 8372 strb r3, [r0, #10] + 395:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[11] = ((uint8_t*)s)[11] ^ ((uint8_t*)k)[11]; + 191 .loc 1 395 0 + 192 005a CB7A ldrb r3, [r1, #11] + 193 005c D47A ldrb r4, [r2, #11] + 194 005e 6340 eors r3, r4 + 195 0060 C372 strb r3, [r0, #11] + 396:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[12] = ((uint8_t*)s)[12] ^ ((uint8_t*)k)[12]; + 196 .loc 1 396 0 + 197 0062 0B7B ldrb r3, [r1, #12] + 198 0064 147B ldrb r4, [r2, #12] + 199 0066 6340 eors r3, r4 + 200 0068 0373 strb r3, [r0, #12] + 397:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[13] = ((uint8_t*)s)[13] ^ ((uint8_t*)k)[13]; + 201 .loc 1 397 0 + 202 006a 4B7B ldrb r3, [r1, #13] + 203 006c 547B ldrb r4, [r2, #13] + 204 006e 6340 eors r3, r4 + 205 0070 4373 strb r3, [r0, #13] + 398:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[14] = ((uint8_t*)s)[14] ^ ((uint8_t*)k)[14]; + 206 .loc 1 398 0 + 207 0072 8B7B ldrb r3, [r1, #14] + 208 0074 947B ldrb r4, [r2, #14] + 209 0076 6340 eors r3, r4 + 210 0078 8373 strb r3, [r0, #14] + 399:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[15] = ((uint8_t*)s)[15] ^ ((uint8_t*)k)[15]; + 211 .loc 1 399 0 + 212 007a CB7B ldrb r3, [r1, #15] + 213 007c D27B ldrb r2, [r2, #15] + 214 .LVL2: + 215 007e 5340 eors r3, r2 + 216 0080 C373 strb r3, [r0, #15] + 400:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 401:./Middlewares/Third_Party/Lora/Crypto/aes.c **** block_copy(d, s); + 402:./Middlewares/Third_Party/Lora/Crypto/aes.c **** xor_block(d, k); + 403:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 404:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 217 .loc 1 404 0 + 218 @ sp needed + 219 0082 10BD pop {r4, pc} + 220 .cfi_endproc + 221 .LFE3: + 223 .global __aeabi_uidivmod + 224 .section .text.aes_set_key,"ax",%progbits + 225 .align 1 + 226 .global aes_set_key + 227 .syntax unified + ARM GAS /tmp/ccJ0d890.s page 12 + + + 228 .code 16 + 229 .thumb_func + 230 .fpu softvfp + 232 aes_set_key: + 233 .LFB7: + 405:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 406:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void add_round_key( uint8_t d[N_BLOCK], const uint8_t k[N_BLOCK] ) + 407:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 408:./Middlewares/Third_Party/Lora/Crypto/aes.c **** xor_block(d, k); + 409:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 410:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 411:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void shift_sub_rows( uint8_t st[N_BLOCK] ) + 412:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t tt; + 413:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 414:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 0] = s_box(st[ 0]); st[ 4] = s_box(st[ 4]); + 415:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 8] = s_box(st[ 8]); st[12] = s_box(st[12]); + 416:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 417:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[1]; st[ 1] = s_box(st[ 5]); st[ 5] = s_box(st[ 9]); + 418:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 9] = s_box(st[13]); st[13] = s_box( tt ); + 419:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 420:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[2]; st[ 2] = s_box(st[10]); st[10] = s_box( tt ); + 421:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[6]; st[ 6] = s_box(st[14]); st[14] = s_box( tt ); + 422:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 423:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[15]; st[15] = s_box(st[11]); st[11] = s_box(st[ 7]); + 424:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 7] = s_box(st[ 3]); st[ 3] = s_box( tt ); + 425:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 426:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 427:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 428:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 429:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void inv_shift_sub_rows( uint8_t st[N_BLOCK] ) + 430:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t tt; + 431:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 432:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 0] = is_box(st[ 0]); st[ 4] = is_box(st[ 4]); + 433:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 8] = is_box(st[ 8]); st[12] = is_box(st[12]); + 434:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 435:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[13]; st[13] = is_box(st[9]); st[ 9] = is_box(st[5]); + 436:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 5] = is_box(st[1]); st[ 1] = is_box( tt ); + 437:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 438:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[2]; st[ 2] = is_box(st[10]); st[10] = is_box( tt ); + 439:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[6]; st[ 6] = is_box(st[14]); st[14] = is_box( tt ); + 440:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 441:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[3]; st[ 3] = is_box(st[ 7]); st[ 7] = is_box(st[11]); + 442:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[11] = is_box(st[15]); st[15] = is_box( tt ); + 443:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 444:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 445:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 446:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 447:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( VERSION_1 ) + 448:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void mix_sub_columns( uint8_t dt[N_BLOCK] ) + 449:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t st[N_BLOCK]; + 450:./Middlewares/Third_Party/Lora/Crypto/aes.c **** block_copy(st, dt); + 451:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 452:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void mix_sub_columns( uint8_t dt[N_BLOCK], uint8_t st[N_BLOCK] ) + 453:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 454:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 455:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 0] = gfm2_sb(st[0]) ^ gfm3_sb(st[5]) ^ s_box(st[10]) ^ s_box(st[15]); + 456:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 1] = s_box(st[0]) ^ gfm2_sb(st[5]) ^ gfm3_sb(st[10]) ^ s_box(st[15]); + ARM GAS /tmp/ccJ0d890.s page 13 + + + 457:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 2] = s_box(st[0]) ^ s_box(st[5]) ^ gfm2_sb(st[10]) ^ gfm3_sb(st[15]); + 458:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 3] = gfm3_sb(st[0]) ^ s_box(st[5]) ^ s_box(st[10]) ^ gfm2_sb(st[15]); + 459:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 460:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 4] = gfm2_sb(st[4]) ^ gfm3_sb(st[9]) ^ s_box(st[14]) ^ s_box(st[3]); + 461:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 5] = s_box(st[4]) ^ gfm2_sb(st[9]) ^ gfm3_sb(st[14]) ^ s_box(st[3]); + 462:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 6] = s_box(st[4]) ^ s_box(st[9]) ^ gfm2_sb(st[14]) ^ gfm3_sb(st[3]); + 463:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 7] = gfm3_sb(st[4]) ^ s_box(st[9]) ^ s_box(st[14]) ^ gfm2_sb(st[3]); + 464:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 465:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 8] = gfm2_sb(st[8]) ^ gfm3_sb(st[13]) ^ s_box(st[2]) ^ s_box(st[7]); + 466:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 9] = s_box(st[8]) ^ gfm2_sb(st[13]) ^ gfm3_sb(st[2]) ^ s_box(st[7]); + 467:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[10] = s_box(st[8]) ^ s_box(st[13]) ^ gfm2_sb(st[2]) ^ gfm3_sb(st[7]); + 468:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[11] = gfm3_sb(st[8]) ^ s_box(st[13]) ^ s_box(st[2]) ^ gfm2_sb(st[7]); + 469:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 470:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[12] = gfm2_sb(st[12]) ^ gfm3_sb(st[1]) ^ s_box(st[6]) ^ s_box(st[11]); + 471:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[13] = s_box(st[12]) ^ gfm2_sb(st[1]) ^ gfm3_sb(st[6]) ^ s_box(st[11]); + 472:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[14] = s_box(st[12]) ^ s_box(st[1]) ^ gfm2_sb(st[6]) ^ gfm3_sb(st[11]); + 473:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[15] = gfm3_sb(st[12]) ^ s_box(st[1]) ^ s_box(st[6]) ^ gfm2_sb(st[11]); + 474:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 475:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 476:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_DEC_PREKEYED ) + 477:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 478:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( VERSION_1 ) + 479:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void inv_mix_sub_columns( uint8_t dt[N_BLOCK] ) + 480:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t st[N_BLOCK]; + 481:./Middlewares/Third_Party/Lora/Crypto/aes.c **** block_copy(st, dt); + 482:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 483:./Middlewares/Third_Party/Lora/Crypto/aes.c **** static void inv_mix_sub_columns( uint8_t dt[N_BLOCK], uint8_t st[N_BLOCK] ) + 484:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 485:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 486:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 0] = is_box(gfm_e(st[ 0]) ^ gfm_b(st[ 1]) ^ gfm_d(st[ 2]) ^ gfm_9(st[ 3])); + 487:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 5] = is_box(gfm_9(st[ 0]) ^ gfm_e(st[ 1]) ^ gfm_b(st[ 2]) ^ gfm_d(st[ 3])); + 488:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[10] = is_box(gfm_d(st[ 0]) ^ gfm_9(st[ 1]) ^ gfm_e(st[ 2]) ^ gfm_b(st[ 3])); + 489:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[15] = is_box(gfm_b(st[ 0]) ^ gfm_d(st[ 1]) ^ gfm_9(st[ 2]) ^ gfm_e(st[ 3])); + 490:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 491:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 4] = is_box(gfm_e(st[ 4]) ^ gfm_b(st[ 5]) ^ gfm_d(st[ 6]) ^ gfm_9(st[ 7])); + 492:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 9] = is_box(gfm_9(st[ 4]) ^ gfm_e(st[ 5]) ^ gfm_b(st[ 6]) ^ gfm_d(st[ 7])); + 493:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[14] = is_box(gfm_d(st[ 4]) ^ gfm_9(st[ 5]) ^ gfm_e(st[ 6]) ^ gfm_b(st[ 7])); + 494:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 3] = is_box(gfm_b(st[ 4]) ^ gfm_d(st[ 5]) ^ gfm_9(st[ 6]) ^ gfm_e(st[ 7])); + 495:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 496:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 8] = is_box(gfm_e(st[ 8]) ^ gfm_b(st[ 9]) ^ gfm_d(st[10]) ^ gfm_9(st[11])); + 497:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[13] = is_box(gfm_9(st[ 8]) ^ gfm_e(st[ 9]) ^ gfm_b(st[10]) ^ gfm_d(st[11])); + 498:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 2] = is_box(gfm_d(st[ 8]) ^ gfm_9(st[ 9]) ^ gfm_e(st[10]) ^ gfm_b(st[11])); + 499:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 7] = is_box(gfm_b(st[ 8]) ^ gfm_d(st[ 9]) ^ gfm_9(st[10]) ^ gfm_e(st[11])); + 500:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 501:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[12] = is_box(gfm_e(st[12]) ^ gfm_b(st[13]) ^ gfm_d(st[14]) ^ gfm_9(st[15])); + 502:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 1] = is_box(gfm_9(st[12]) ^ gfm_e(st[13]) ^ gfm_b(st[14]) ^ gfm_d(st[15])); + 503:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 6] = is_box(gfm_d(st[12]) ^ gfm_9(st[13]) ^ gfm_e(st[14]) ^ gfm_b(st[15])); + 504:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[11] = is_box(gfm_b(st[12]) ^ gfm_d(st[13]) ^ gfm_9(st[14]) ^ gfm_e(st[15])); + 505:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 506:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 507:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 508:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 509:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_ENC_PREKEYED ) || defined( AES_DEC_PREKEYED ) + 510:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 511:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* Set the cipher key for the pre-keyed version */ + 512:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 513:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return_type aes_set_key( const uint8_t key[], length_type keylen, aes_context ctx[1] ) + ARM GAS /tmp/ccJ0d890.s page 14 + + + 514:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 234 .loc 1 514 0 + 235 .cfi_startproc + 236 @ args = 0, pretend = 0, frame = 8 + 237 @ frame_needed = 0, uses_anonymous_args = 0 + 238 .LVL3: + 239 0000 F0B5 push {r4, r5, r6, r7, lr} + 240 .LCFI1: + 241 .cfi_def_cfa_offset 20 + 242 .cfi_offset 4, -20 + 243 .cfi_offset 5, -16 + 244 .cfi_offset 6, -12 + 245 .cfi_offset 7, -8 + 246 .cfi_offset 14, -4 + 247 0002 DE46 mov lr, fp + 248 0004 5746 mov r7, r10 + 249 0006 4E46 mov r6, r9 + 250 0008 4546 mov r5, r8 + 251 000a E0B5 push {r5, r6, r7, lr} + 252 .LCFI2: + 253 .cfi_def_cfa_offset 36 + 254 .cfi_offset 8, -36 + 255 .cfi_offset 9, -32 + 256 .cfi_offset 10, -28 + 257 .cfi_offset 11, -24 + 258 000c 83B0 sub sp, sp, #12 + 259 .LCFI3: + 260 .cfi_def_cfa_offset 48 + 261 000e 0F00 movs r7, r1 + 262 0010 1400 movs r4, r2 + 515:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint8_t cc, rc, hi; + 516:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 517:./Middlewares/Third_Party/Lora/Crypto/aes.c **** switch( keylen ) + 263 .loc 1 517 0 + 264 0012 1829 cmp r1, #24 + 265 0014 08D0 beq .L5 + 266 0016 2029 cmp r1, #32 + 267 0018 06D0 beq .L5 + 268 001a 1029 cmp r1, #16 + 269 001c 04D0 beq .L5 + 518:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 519:./Middlewares/Third_Party/Lora/Crypto/aes.c **** case 16: + 520:./Middlewares/Third_Party/Lora/Crypto/aes.c **** case 24: + 521:./Middlewares/Third_Party/Lora/Crypto/aes.c **** case 32: + 522:./Middlewares/Third_Party/Lora/Crypto/aes.c **** break; + 523:./Middlewares/Third_Party/Lora/Crypto/aes.c **** default: + 524:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->rnd = 0; + 270 .loc 1 524 0 + 271 001e F023 movs r3, #240 + 272 0020 0022 movs r2, #0 + 273 .LVL4: + 274 0022 E254 strb r2, [r4, r3] + 525:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return ( uint8_t )-1; + 275 .loc 1 525 0 + 276 0024 FF20 movs r0, #255 + 277 .LVL5: + 278 0026 77E0 b .L6 + ARM GAS /tmp/ccJ0d890.s page 15 + + + 279 .LVL6: + 280 .L5: + 526:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 527:./Middlewares/Third_Party/Lora/Crypto/aes.c **** block_copy_nn(ctx->ksch, key, keylen); + 281 .loc 1 527 0 + 282 0028 2100 movs r1, r4 + 283 .LVL7: + 284 002a 3A00 movs r2, r7 + 285 .LVL8: + 286 002c 04E0 b .L7 + 287 .LVL9: + 288 .L8: + 289 .LBB12: + 290 .LBB13: + 346:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 291 .loc 1 346 0 + 292 002e 0278 ldrb r2, [r0] + 293 0030 0A70 strb r2, [r1] + 344:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //*((uint8_t*)d)++ = *((uint8_t*)s)++; + 294 .loc 1 344 0 + 295 0032 1A00 movs r2, r3 + 346:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 296 .loc 1 346 0 + 297 0034 0130 adds r0, r0, #1 + 298 .LVL10: + 299 0036 0131 adds r1, r1, #1 + 300 .LVL11: + 301 .L7: + 344:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //*((uint8_t*)d)++ = *((uint8_t*)s)++; + 302 .loc 1 344 0 + 303 0038 531E subs r3, r2, #1 + 304 003a DBB2 uxtb r3, r3 + 305 .LVL12: + 306 003c 002A cmp r2, #0 + 307 003e F6D1 bne .L8 + 308 .LVL13: + 309 .LBE13: + 310 .LBE12: + 528:./Middlewares/Third_Party/Lora/Crypto/aes.c **** hi = (keylen + 28) << 2; + 311 .loc 1 528 0 + 312 0040 3B00 movs r3, r7 + 313 0042 1C33 adds r3, r3, #28 + 314 0044 DBB2 uxtb r3, r3 + 315 0046 9B00 lsls r3, r3, #2 + 316 0048 DBB2 uxtb r3, r3 + 317 004a 0093 str r3, [sp] + 318 .LVL14: + 529:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->rnd = (hi >> 4) - 1; + 319 .loc 1 529 0 + 320 004c 1B09 lsrs r3, r3, #4 + 321 .LVL15: + 322 004e 013B subs r3, r3, #1 + 323 0050 F032 adds r2, r2, #240 + 324 0052 A354 strb r3, [r4, r2] + 325 .LVL16: + 530:./Middlewares/Third_Party/Lora/Crypto/aes.c **** for( cc = keylen, rc = 1; cc < hi; cc += 4 ) + 326 .loc 1 530 0 + ARM GAS /tmp/ccJ0d890.s page 16 + + + 327 0054 3D00 movs r5, r7 + 328 0056 0123 movs r3, #1 + 329 0058 0193 str r3, [sp, #4] + 330 005a 1DE0 b .L9 + 331 .LVL17: + 332 .L10: + 333 .LBB14: + 531:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t tt, t0, t1, t2, t3; + 532:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 533:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t0 = ctx->ksch[cc - 4]; + 534:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = ctx->ksch[cc - 3]; + 535:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = ctx->ksch[cc - 2]; + 536:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = ctx->ksch[cc - 1]; + 537:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if( cc % keylen == 0 ) + 538:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 539:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = t0; + 540:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t0 = s_box(t1) ^ rc; + 541:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = s_box(t2); + 542:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = s_box(t3); + 543:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = s_box(tt); + 544:./Middlewares/Third_Party/Lora/Crypto/aes.c **** rc = f2(rc); + 545:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 546:./Middlewares/Third_Party/Lora/Crypto/aes.c **** else if( keylen > 24 && cc % keylen == 16 ) + 334 .loc 1 546 0 + 335 005c 182F cmp r7, #24 + 336 005e 01D9 bls .L11 + 337 .loc 1 546 0 is_stmt 0 discriminator 1 + 338 0060 1029 cmp r1, #16 + 339 0062 4AD0 beq .L13 + 340 .LVL18: + 341 .L11: + 547:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 548:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t0 = s_box(t0); + 549:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = s_box(t1); + 550:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = s_box(t2); + 551:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = s_box(t3); + 552:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 553:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = cc - keylen; + 342 .loc 1 553 0 is_stmt 1 discriminator 2 + 343 0064 EB1B subs r3, r5, r7 + 344 0066 DBB2 uxtb r3, r3 + 345 .LVL19: + 554:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->ksch[cc + 0] = ctx->ksch[tt + 0] ^ t0; + 346 .loc 1 554 0 discriminator 2 + 347 0068 E25C ldrb r2, [r4, r3] + 348 006a 5946 mov r1, fp + 349 006c 4A40 eors r2, r1 + 350 006e A255 strb r2, [r4, r6] + 555:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->ksch[cc + 1] = ctx->ksch[tt + 1] ^ t1; + 351 .loc 1 555 0 discriminator 2 + 352 0070 5A1C adds r2, r3, #1 + 353 0072 A25C ldrb r2, [r4, r2] + 354 0074 711C adds r1, r6, #1 + 355 0076 5046 mov r0, r10 + 356 0078 4240 eors r2, r0 + 357 007a 6254 strb r2, [r4, r1] + 556:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->ksch[cc + 2] = ctx->ksch[tt + 2] ^ t2; + ARM GAS /tmp/ccJ0d890.s page 17 + + + 358 .loc 1 556 0 discriminator 2 + 359 007c 9A1C adds r2, r3, #2 + 360 007e A25C ldrb r2, [r4, r2] + 361 0080 B11C adds r1, r6, #2 + 362 0082 4846 mov r0, r9 + 363 0084 4240 eors r2, r0 + 364 0086 6254 strb r2, [r4, r1] + 557:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ctx->ksch[cc + 3] = ctx->ksch[tt + 3] ^ t3; + 365 .loc 1 557 0 discriminator 2 + 366 0088 0333 adds r3, r3, #3 + 367 .LVL20: + 368 008a E35C ldrb r3, [r4, r3] + 369 .LVL21: + 370 008c 0336 adds r6, r6, #3 + 371 008e 4246 mov r2, r8 + 372 0090 5340 eors r3, r2 + 373 0092 A355 strb r3, [r4, r6] + 374 .LBE14: + 530:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t tt, t0, t1, t2, t3; + 375 .loc 1 530 0 discriminator 2 + 376 0094 0435 adds r5, r5, #4 + 377 .LVL22: + 378 0096 EDB2 uxtb r5, r5 + 379 .LVL23: + 380 .L9: + 530:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t tt, t0, t1, t2, t3; + 381 .loc 1 530 0 is_stmt 0 discriminator 1 + 382 0098 009B ldr r3, [sp] + 383 009a 9D42 cmp r5, r3 + 384 009c 3BD2 bcs .L14 + 385 .LBB15: + 533:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = ctx->ksch[cc - 3]; + 386 .loc 1 533 0 is_stmt 1 + 387 009e 2E00 movs r6, r5 + 388 00a0 2B1F subs r3, r5, #4 + 389 00a2 E35C ldrb r3, [r4, r3] + 390 00a4 9B46 mov fp, r3 + 391 .LVL24: + 534:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = ctx->ksch[cc - 2]; + 392 .loc 1 534 0 + 393 00a6 EB1E subs r3, r5, #3 + 394 00a8 E35C ldrb r3, [r4, r3] + 395 00aa 9A46 mov r10, r3 + 396 .LVL25: + 535:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = ctx->ksch[cc - 1]; + 397 .loc 1 535 0 + 398 00ac AB1E subs r3, r5, #2 + 399 00ae E35C ldrb r3, [r4, r3] + 400 00b0 9946 mov r9, r3 + 401 .LVL26: + 536:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if( cc % keylen == 0 ) + 402 .loc 1 536 0 + 403 00b2 6B1E subs r3, r5, #1 + 404 00b4 E35C ldrb r3, [r4, r3] + 405 00b6 9846 mov r8, r3 + 406 .LVL27: + 537:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + ARM GAS /tmp/ccJ0d890.s page 18 + + + 407 .loc 1 537 0 + 408 00b8 3900 movs r1, r7 + 409 00ba 2800 movs r0, r5 + 410 00bc FFF7FEFF bl __aeabi_uidivmod + 411 .LVL28: + 412 00c0 C9B2 uxtb r1, r1 + 413 00c2 0029 cmp r1, #0 + 414 00c4 CAD1 bne .L10 + 415 .LVL29: + 540:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = s_box(t2); + 416 .loc 1 540 0 + 417 00c6 184B ldr r3, .L15 + 418 00c8 5246 mov r2, r10 + 419 00ca 9A5C ldrb r2, [r3, r2] + 420 00cc 0199 ldr r1, [sp, #4] + 421 00ce 4A40 eors r2, r1 + 422 .LVL30: + 541:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = s_box(t3); + 423 .loc 1 541 0 + 424 00d0 4846 mov r0, r9 + 425 00d2 185C ldrb r0, [r3, r0] + 426 00d4 8246 mov r10, r0 + 427 .LVL31: + 542:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = s_box(tt); + 428 .loc 1 542 0 + 429 00d6 4046 mov r0, r8 + 430 00d8 185C ldrb r0, [r3, r0] + 431 00da 8146 mov r9, r0 + 432 .LVL32: + 543:./Middlewares/Third_Party/Lora/Crypto/aes.c **** rc = f2(rc); + 433 .loc 1 543 0 + 434 00dc 5846 mov r0, fp + 435 00de 1B5C ldrb r3, [r3, r0] + 436 00e0 9846 mov r8, r3 + 437 .LVL33: + 544:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 438 .loc 1 544 0 + 439 00e2 0B00 movs r3, r1 + 440 00e4 4900 lsls r1, r1, #1 + 441 00e6 DB09 lsrs r3, r3, #7 + 442 00e8 5800 lsls r0, r3, #1 + 443 00ea 1B18 adds r3, r3, r0 + 444 00ec D800 lsls r0, r3, #3 + 445 00ee 1B18 adds r3, r3, r0 + 446 00f0 4B40 eors r3, r1 + 447 00f2 DBB2 uxtb r3, r3 + 448 00f4 0193 str r3, [sp, #4] + 449 .LVL34: + 540:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = s_box(t2); + 450 .loc 1 540 0 + 451 00f6 9346 mov fp, r2 + 452 .LVL35: + 453 00f8 B4E7 b .L11 + 454 .LVL36: + 455 .L13: + 548:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t1 = s_box(t1); + 456 .loc 1 548 0 + ARM GAS /tmp/ccJ0d890.s page 19 + + + 457 00fa 0B4B ldr r3, .L15 + 458 00fc 5A46 mov r2, fp + 459 00fe 9A5C ldrb r2, [r3, r2] + 460 0100 9346 mov fp, r2 + 461 .LVL37: + 549:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t2 = s_box(t2); + 462 .loc 1 549 0 + 463 0102 5246 mov r2, r10 + 464 0104 9A5C ldrb r2, [r3, r2] + 465 0106 9246 mov r10, r2 + 466 .LVL38: + 550:./Middlewares/Third_Party/Lora/Crypto/aes.c **** t3 = s_box(t3); + 467 .loc 1 550 0 + 468 0108 4A46 mov r2, r9 + 469 010a 9A5C ldrb r2, [r3, r2] + 470 010c 9146 mov r9, r2 + 471 .LVL39: + 551:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 472 .loc 1 551 0 + 473 010e 4246 mov r2, r8 + 474 0110 9B5C ldrb r3, [r3, r2] + 475 0112 9846 mov r8, r3 + 476 .LVL40: + 477 0114 A6E7 b .L11 + 478 .LVL41: + 479 .L14: + 480 .LBE15: + 558:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 559:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0; + 481 .loc 1 559 0 + 482 0116 0020 movs r0, #0 + 483 .LVL42: + 484 .L6: + 560:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 485 .loc 1 560 0 + 486 0118 03B0 add sp, sp, #12 + 487 @ sp needed + 488 .LVL43: + 489 011a 3CBC pop {r2, r3, r4, r5} + 490 011c 9046 mov r8, r2 + 491 011e 9946 mov r9, r3 + 492 0120 A246 mov r10, r4 + 493 0122 AB46 mov fp, r5 + 494 0124 F0BD pop {r4, r5, r6, r7, pc} + 495 .L16: + 496 0126 C046 .align 2 + 497 .L15: + 498 0128 00000000 .word sbox + 499 .cfi_endproc + 500 .LFE7: + 502 .section .text.aes_encrypt,"ax",%progbits + 503 .align 1 + 504 .global aes_encrypt + 505 .syntax unified + 506 .code 16 + 507 .thumb_func + 508 .fpu softvfp + ARM GAS /tmp/ccJ0d890.s page 20 + + + 510 aes_encrypt: + 511 .LFB8: + 561:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 562:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 563:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 564:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( AES_ENC_PREKEYED ) + 565:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 566:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* Encrypt a single block of 16 bytes */ + 567:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 568:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return_type aes_encrypt( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], const aes_context ctx[1] + 569:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 512 .loc 1 569 0 + 513 .cfi_startproc + 514 @ args = 0, pretend = 0, frame = 80 + 515 @ frame_needed = 0, uses_anonymous_args = 0 + 516 .LVL44: + 517 0000 F0B5 push {r4, r5, r6, r7, lr} + 518 .LCFI4: + 519 .cfi_def_cfa_offset 20 + 520 .cfi_offset 4, -20 + 521 .cfi_offset 5, -16 + 522 .cfi_offset 6, -12 + 523 .cfi_offset 7, -8 + 524 .cfi_offset 14, -4 + 525 0002 DE46 mov lr, fp + 526 0004 5746 mov r7, r10 + 527 0006 4E46 mov r6, r9 + 528 0008 4546 mov r5, r8 + 529 000a E0B5 push {r5, r6, r7, lr} + 530 .LCFI5: + 531 .cfi_def_cfa_offset 36 + 532 .cfi_offset 8, -36 + 533 .cfi_offset 9, -32 + 534 .cfi_offset 10, -28 + 535 .cfi_offset 11, -24 + 536 000c 95B0 sub sp, sp, #84 + 537 .LCFI6: + 538 .cfi_def_cfa_offset 120 + 539 000e 0F91 str r1, [sp, #60] + 540 0010 0D92 str r2, [sp, #52] + 570:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if( ctx->rnd ) + 541 .loc 1 570 0 + 542 0012 F023 movs r3, #240 + 543 0014 D35C ldrb r3, [r2, r3] + 544 0016 002B cmp r3, #0 + 545 0018 00D1 bne .LCB519 + 546 001a 5CE1 b .L21 @long jump + 547 .LCB519: + 548 .LBB25: + 571:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 572:./Middlewares/Third_Party/Lora/Crypto/aes.c **** uint8_t s1[N_BLOCK], r; + 573:./Middlewares/Third_Party/Lora/Crypto/aes.c **** copy_and_key( s1, in, ctx->ksch ); + 549 .loc 1 573 0 + 550 001c 0E92 str r2, [sp, #56] + 551 001e 0100 movs r1, r0 + 552 .LVL45: + 553 0020 10A8 add r0, sp, #64 + ARM GAS /tmp/ccJ0d890.s page 21 + + + 554 .LVL46: + 555 0022 FFF7FEFF bl copy_and_key + 556 .LVL47: + 574:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 575:./Middlewares/Third_Party/Lora/Crypto/aes.c **** for( r = 1 ; r < ctx->rnd ; ++r ) + 557 .loc 1 575 0 + 558 0026 0123 movs r3, #1 + 559 0028 0693 str r3, [sp, #24] + 560 002a 08E1 b .L19 + 561 .LVL48: + 562 .L20: + 563 .LBB26: + 564 .LBB27: + 565 .LBB28: + 566 .LBB29: + 323:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1]; + 567 .loc 1 323 0 + 568 002c 10AB add r3, sp, #64 + 569 .LVL49: + 570 002e 1B78 ldrb r3, [r3] + 571 .LVL50: + 572 0030 9C46 mov ip, r3 + 324:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2]; + 573 .loc 1 324 0 + 574 0032 10AB add r3, sp, #64 + 575 .LVL51: + 576 0034 5F78 ldrb r7, [r3, #1] + 577 0036 0997 str r7, [sp, #36] + 325:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3]; + 578 .loc 1 325 0 + 579 0038 9B78 ldrb r3, [r3, #2] + 580 .LVL52: + 581 003a 0093 str r3, [sp] + 326:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4]; + 582 .loc 1 326 0 + 583 003c 10AA add r2, sp, #64 + 584 .LVL53: + 585 003e D278 ldrb r2, [r2, #3] + 586 .LVL54: + 587 0040 0792 str r2, [sp, #28] + 327:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5]; + 588 .loc 1 327 0 + 589 0042 10A9 add r1, sp, #64 + 590 .LVL55: + 591 0044 0979 ldrb r1, [r1, #4] + 592 .LVL56: + 593 0046 0191 str r1, [sp, #4] + 328:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6]; + 594 .loc 1 328 0 + 595 0048 10AE add r6, sp, #64 + 596 .LVL57: + 597 004a 7679 ldrb r6, [r6, #5] + 598 .LVL58: + 599 004c B146 mov r9, r6 + 329:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7]; + 600 .loc 1 329 0 + 601 004e 10AE add r6, sp, #64 + ARM GAS /tmp/ccJ0d890.s page 22 + + + 602 .LVL59: + 603 0050 B679 ldrb r6, [r6, #6] + 604 .LVL60: + 605 0052 0296 str r6, [sp, #8] + 330:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8]; + 606 .loc 1 330 0 + 607 0054 10AD add r5, sp, #64 + 608 .LVL61: + 609 0056 ED79 ldrb r5, [r5, #7] + 610 .LVL62: + 611 0058 0395 str r5, [sp, #12] + 331:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9]; + 612 .loc 1 331 0 + 613 005a 10AC add r4, sp, #64 + 614 .LVL63: + 615 005c 247A ldrb r4, [r4, #8] + 616 .LVL64: + 617 005e 0A94 str r4, [sp, #40] + 332:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[10] = ((uint8_t*)s)[10]; + 618 .loc 1 332 0 + 619 0060 10AB add r3, sp, #64 + 620 .LVL65: + 621 0062 5B7A ldrb r3, [r3, #9] + 622 .LVL66: + 623 0064 0B93 str r3, [sp, #44] + 333:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[11] = ((uint8_t*)s)[11]; + 624 .loc 1 333 0 + 625 0066 10AA add r2, sp, #64 + 626 .LVL67: + 627 0068 927A ldrb r2, [r2, #10] + 628 .LVL68: + 629 006a 9046 mov r8, r2 + 334:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[12] = ((uint8_t*)s)[12]; + 630 .loc 1 334 0 + 631 006c 10AA add r2, sp, #64 + 632 .LVL69: + 633 006e D27A ldrb r2, [r2, #11] + 634 .LVL70: + 635 0070 0892 str r2, [sp, #32] + 335:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[13] = ((uint8_t*)s)[13]; + 636 .loc 1 335 0 + 637 0072 10A9 add r1, sp, #64 + 638 .LVL71: + 639 0074 097B ldrb r1, [r1, #12] + 640 .LVL72: + 641 0076 0491 str r1, [sp, #16] + 336:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[14] = ((uint8_t*)s)[14]; + 642 .loc 1 336 0 + 643 0078 10A8 add r0, sp, #64 + 644 .LVL73: + 645 007a 407B ldrb r0, [r0, #13] + 646 .LVL74: + 647 007c 0590 str r0, [sp, #20] + 337:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[15] = ((uint8_t*)s)[15]; + 648 .loc 1 337 0 + 649 007e 10AB add r3, sp, #64 + 650 .LVL75: + ARM GAS /tmp/ccJ0d890.s page 23 + + + 651 0080 9E7B ldrb r6, [r3, #14] + 338:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 652 .loc 1 338 0 + 653 0082 DF7B ldrb r7, [r3, #15] + 654 .LVL76: + 655 .LBE29: + 656 .LBE28: + 455:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 1] = s_box(st[0]) ^ gfm2_sb(st[5]) ^ gfm3_sb(st[10]) ^ s_box(st[15]); + 657 .loc 1 455 0 + 658 0084 6346 mov r3, ip + 659 .LVL77: + 660 0086 954A ldr r2, .L22 + 661 0088 D45C ldrb r4, [r2, r3] + 662 008a 4B46 mov r3, r9 + 663 008c 944A ldr r2, .L22+4 + 664 008e D35C ldrb r3, [r2, r3] + 665 0090 9A46 mov r10, r3 + 666 0092 9449 ldr r1, .L22+8 + 667 0094 4346 mov r3, r8 + 668 0096 C85C ldrb r0, [r1, r3] + 669 0098 CD5D ldrb r5, [r1, r7] + 670 009a 5346 mov r3, r10 + 671 009c 5C40 eors r4, r3 + 672 009e 4440 eors r4, r0 + 673 00a0 0C95 str r5, [sp, #48] + 674 00a2 6C40 eors r4, r5 + 675 00a4 10AB add r3, sp, #64 + 676 .LVL78: + 677 00a6 1C70 strb r4, [r3] + 456:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 2] = s_box(st[0]) ^ s_box(st[5]) ^ gfm2_sb(st[10]) ^ gfm3_sb(st[15]); + 678 .loc 1 456 0 + 679 00a8 6346 mov r3, ip + 680 .LVL79: + 681 00aa CC5C ldrb r4, [r1, r3] + 682 00ac 4B46 mov r3, r9 + 683 00ae 8B4A ldr r2, .L22 + 684 00b0 D35C ldrb r3, [r2, r3] + 685 00b2 9B46 mov fp, r3 + 686 00b4 4346 mov r3, r8 + 687 00b6 8A4A ldr r2, .L22+4 + 688 00b8 D35C ldrb r3, [r2, r3] + 689 00ba 9A46 mov r10, r3 + 690 00bc 5B46 mov r3, fp + 691 00be 6340 eors r3, r4 + 692 00c0 9B46 mov fp, r3 + 693 00c2 5346 mov r3, r10 + 694 00c4 5D46 mov r5, fp + 695 00c6 6B40 eors r3, r5 + 696 00c8 0C9D ldr r5, [sp, #48] + 697 00ca 5D40 eors r5, r3 + 698 00cc 10AB add r3, sp, #64 + 699 .LVL80: + 700 00ce 5D70 strb r5, [r3, #1] + 457:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 3] = gfm3_sb(st[0]) ^ s_box(st[5]) ^ s_box(st[10]) ^ gfm2_sb(st[15]); + 701 .loc 1 457 0 + 702 00d0 4B46 mov r3, r9 + 703 .LVL81: + ARM GAS /tmp/ccJ0d890.s page 24 + + + 704 00d2 CD5C ldrb r5, [r1, r3] + 705 00d4 4346 mov r3, r8 + 706 00d6 814A ldr r2, .L22 + 707 00d8 D35C ldrb r3, [r2, r3] + 708 00da 9946 mov r9, r3 + 709 00dc 804B ldr r3, .L22+4 + 710 00de DB5D ldrb r3, [r3, r7] + 711 00e0 9846 mov r8, r3 + 712 00e2 6C40 eors r4, r5 + 713 00e4 4B46 mov r3, r9 + 714 00e6 5C40 eors r4, r3 + 715 00e8 4346 mov r3, r8 + 716 00ea 5C40 eors r4, r3 + 717 00ec 10AB add r3, sp, #64 + 718 .LVL82: + 719 00ee 9C70 strb r4, [r3, #2] + 458:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 720 .loc 1 458 0 + 721 00f0 6346 mov r3, ip + 722 .LVL83: + 723 00f2 7B4A ldr r2, .L22+4 + 724 00f4 D45C ldrb r4, [r2, r3] + 725 00f6 794B ldr r3, .L22 + 726 00f8 DF5D ldrb r7, [r3, r7] + 727 00fa 6540 eors r5, r4 + 728 00fc 4540 eors r5, r0 + 729 00fe 7D40 eors r5, r7 + 730 0100 10AB add r3, sp, #64 + 731 .LVL84: + 732 0102 DD70 strb r5, [r3, #3] + 460:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 5] = s_box(st[4]) ^ gfm2_sb(st[9]) ^ gfm3_sb(st[14]) ^ s_box(st[3]); + 733 .loc 1 460 0 + 734 0104 019C ldr r4, [sp, #4] + 735 0106 754B ldr r3, .L22 + 736 .LVL85: + 737 0108 1C5D ldrb r4, [r3, r4] + 738 010a 0B9A ldr r2, [sp, #44] + 739 010c 744B ldr r3, .L22+4 + 740 010e 9F5C ldrb r7, [r3, r2] + 741 0110 885D ldrb r0, [r1, r6] + 742 0112 079D ldr r5, [sp, #28] + 743 0114 4D5D ldrb r5, [r1, r5] + 744 0116 7C40 eors r4, r7 + 745 0118 4440 eors r4, r0 + 746 011a 6C40 eors r4, r5 + 747 011c 10AB add r3, sp, #64 + 748 .LVL86: + 749 011e 1C71 strb r4, [r3, #4] + 461:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 6] = s_box(st[4]) ^ s_box(st[9]) ^ gfm2_sb(st[14]) ^ gfm3_sb(st[3]); + 750 .loc 1 461 0 + 751 0120 019C ldr r4, [sp, #4] + 752 0122 0C5D ldrb r4, [r1, r4] + 753 0124 6D4B ldr r3, .L22 + 754 .LVL87: + 755 0126 9B5C ldrb r3, [r3, r2] + 756 0128 9C46 mov ip, r3 + 757 012a 6D4B ldr r3, .L22+4 + ARM GAS /tmp/ccJ0d890.s page 25 + + + 758 012c 9F5D ldrb r7, [r3, r6] + 759 012e 6346 mov r3, ip + 760 0130 6340 eors r3, r4 + 761 0132 5F40 eors r7, r3 + 762 0134 6F40 eors r7, r5 + 763 0136 10AB add r3, sp, #64 + 764 .LVL88: + 765 0138 5F71 strb r7, [r3, #5] + 462:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 7] = gfm3_sb(st[4]) ^ s_box(st[9]) ^ s_box(st[14]) ^ gfm2_sb(st[3]); + 766 .loc 1 462 0 + 767 013a 8D5C ldrb r5, [r1, r2] + 768 013c 674B ldr r3, .L22 + 769 .LVL89: + 770 013e 9F5D ldrb r7, [r3, r6] + 771 0140 079A ldr r2, [sp, #28] + 772 0142 674B ldr r3, .L22+4 + 773 0144 9E5C ldrb r6, [r3, r2] + 774 0146 6C40 eors r4, r5 + 775 0148 7C40 eors r4, r7 + 776 014a 7440 eors r4, r6 + 777 014c 10AB add r3, sp, #64 + 778 .LVL90: + 779 014e 9C71 strb r4, [r3, #6] + 463:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 780 .loc 1 463 0 + 781 0150 019C ldr r4, [sp, #4] + 782 0152 634B ldr r3, .L22+4 + 783 .LVL91: + 784 0154 1C5D ldrb r4, [r3, r4] + 785 0156 614B ldr r3, .L22 + 786 0158 9E5C ldrb r6, [r3, r2] + 787 015a 6540 eors r5, r4 + 788 015c 4540 eors r5, r0 + 789 015e 7540 eors r5, r6 + 790 0160 10AB add r3, sp, #64 + 791 .LVL92: + 792 0162 DD71 strb r5, [r3, #7] + 465:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[ 9] = s_box(st[8]) ^ gfm2_sb(st[13]) ^ gfm3_sb(st[2]) ^ s_box(st[7]); + 793 .loc 1 465 0 + 794 0164 0A9A ldr r2, [sp, #40] + 795 0166 5D4B ldr r3, .L22 + 796 .LVL93: + 797 0168 9C5C ldrb r4, [r3, r2] + 798 016a 059F ldr r7, [sp, #20] + 799 016c 5C4B ldr r3, .L22+4 + 800 016e DE5D ldrb r6, [r3, r7] + 801 0170 0098 ldr r0, [sp] + 802 0172 085C ldrb r0, [r1, r0] + 803 0174 039D ldr r5, [sp, #12] + 804 0176 4D5D ldrb r5, [r1, r5] + 805 0178 7440 eors r4, r6 + 806 017a 4440 eors r4, r0 + 807 017c 6C40 eors r4, r5 + 808 017e 10AB add r3, sp, #64 + 809 .LVL94: + 810 0180 1C72 strb r4, [r3, #8] + 466:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[10] = s_box(st[8]) ^ s_box(st[13]) ^ gfm2_sb(st[2]) ^ gfm3_sb(st[7]); + ARM GAS /tmp/ccJ0d890.s page 26 + + + 811 .loc 1 466 0 + 812 0182 8C5C ldrb r4, [r1, r2] + 813 0184 554B ldr r3, .L22 + 814 .LVL95: + 815 0186 DF5D ldrb r7, [r3, r7] + 816 0188 009E ldr r6, [sp] + 817 018a 554B ldr r3, .L22+4 + 818 018c 9E5D ldrb r6, [r3, r6] + 819 018e 6740 eors r7, r4 + 820 0190 7E40 eors r6, r7 + 821 0192 6E40 eors r6, r5 + 822 0194 10AB add r3, sp, #64 + 823 .LVL96: + 824 0196 5E72 strb r6, [r3, #9] + 467:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[11] = gfm3_sb(st[8]) ^ s_box(st[13]) ^ s_box(st[2]) ^ gfm2_sb(st[7]); + 825 .loc 1 467 0 + 826 0198 059D ldr r5, [sp, #20] + 827 019a 4D5D ldrb r5, [r1, r5] + 828 019c 009E ldr r6, [sp] + 829 019e 4F4B ldr r3, .L22 + 830 .LVL97: + 831 01a0 9F5D ldrb r7, [r3, r6] + 832 01a2 039E ldr r6, [sp, #12] + 833 01a4 4E4B ldr r3, .L22+4 + 834 01a6 9E5D ldrb r6, [r3, r6] + 835 01a8 6C40 eors r4, r5 + 836 01aa 7C40 eors r4, r7 + 837 01ac 7440 eors r4, r6 + 838 01ae 10AB add r3, sp, #64 + 839 .LVL98: + 840 01b0 9C72 strb r4, [r3, #10] + 468:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 841 .loc 1 468 0 + 842 01b2 4B4B ldr r3, .L22+4 + 843 .LVL99: + 844 01b4 9C5C ldrb r4, [r3, r2] + 845 01b6 039E ldr r6, [sp, #12] + 846 01b8 484B ldr r3, .L22 + 847 01ba 9E5D ldrb r6, [r3, r6] + 848 01bc 6540 eors r5, r4 + 849 01be 6840 eors r0, r5 + 850 01c0 7040 eors r0, r6 + 851 01c2 10AB add r3, sp, #64 + 852 .LVL100: + 853 01c4 D872 strb r0, [r3, #11] + 470:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[13] = s_box(st[12]) ^ gfm2_sb(st[1]) ^ gfm3_sb(st[6]) ^ s_box(st[11]); + 854 .loc 1 470 0 + 855 01c6 049C ldr r4, [sp, #16] + 856 01c8 444B ldr r3, .L22 + 857 .LVL101: + 858 01ca 1C5D ldrb r4, [r3, r4] + 859 01cc 099A ldr r2, [sp, #36] + 860 01ce 444B ldr r3, .L22+4 + 861 01d0 9E5C ldrb r6, [r3, r2] + 862 01d2 0298 ldr r0, [sp, #8] + 863 01d4 085C ldrb r0, [r1, r0] + 864 01d6 089D ldr r5, [sp, #32] + ARM GAS /tmp/ccJ0d890.s page 27 + + + 865 01d8 4D5D ldrb r5, [r1, r5] + 866 01da 7440 eors r4, r6 + 867 01dc 4440 eors r4, r0 + 868 01de 6C40 eors r4, r5 + 869 01e0 10AB add r3, sp, #64 + 870 .LVL102: + 871 01e2 1C73 strb r4, [r3, #12] + 471:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[14] = s_box(st[12]) ^ s_box(st[1]) ^ gfm2_sb(st[6]) ^ gfm3_sb(st[11]); + 872 .loc 1 471 0 + 873 01e4 049C ldr r4, [sp, #16] + 874 01e6 0C5D ldrb r4, [r1, r4] + 875 01e8 3C4B ldr r3, .L22 + 876 .LVL103: + 877 01ea 9F5C ldrb r7, [r3, r2] + 878 01ec 029E ldr r6, [sp, #8] + 879 01ee 3C4B ldr r3, .L22+4 + 880 01f0 9E5D ldrb r6, [r3, r6] + 881 01f2 6740 eors r7, r4 + 882 01f4 7E40 eors r6, r7 + 883 01f6 6E40 eors r6, r5 + 884 01f8 10AB add r3, sp, #64 + 885 .LVL104: + 886 01fa 5E73 strb r6, [r3, #13] + 472:./Middlewares/Third_Party/Lora/Crypto/aes.c **** dt[15] = gfm3_sb(st[12]) ^ s_box(st[1]) ^ s_box(st[6]) ^ gfm2_sb(st[11]); + 887 .loc 1 472 0 + 888 01fc 895C ldrb r1, [r1, r2] + 889 01fe 029E ldr r6, [sp, #8] + 890 0200 364B ldr r3, .L22 + 891 .LVL105: + 892 0202 9E5D ldrb r6, [r3, r6] + 893 0204 089F ldr r7, [sp, #32] + 894 0206 364B ldr r3, .L22+4 + 895 0208 DD5D ldrb r5, [r3, r7] + 896 020a 4C40 eors r4, r1 + 897 020c 7440 eors r4, r6 + 898 020e 6C40 eors r4, r5 + 899 0210 10AB add r3, sp, #64 + 900 .LVL106: + 901 0212 9C73 strb r4, [r3, #14] + 473:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 902 .loc 1 473 0 + 903 0214 049C ldr r4, [sp, #16] + 904 0216 324B ldr r3, .L22+4 + 905 .LVL107: + 906 0218 1A5D ldrb r2, [r3, r4] + 907 021a 304B ldr r3, .L22 + 908 021c DB5D ldrb r3, [r3, r7] + 909 021e 5140 eors r1, r2 + 910 0220 4840 eors r0, r1 + 911 0222 5840 eors r0, r3 + 912 0224 10AB add r3, sp, #64 + 913 .LVL108: + 914 0226 D873 strb r0, [r3, #15] + 915 .LVL109: + 916 .LBE27: + 917 .LBE26: + 576:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( VERSION_1 ) + ARM GAS /tmp/ccJ0d890.s page 28 + + + 577:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 578:./Middlewares/Third_Party/Lora/Crypto/aes.c **** mix_sub_columns( s1 ); + 579:./Middlewares/Third_Party/Lora/Crypto/aes.c **** add_round_key( s1, ctx->ksch + r * N_BLOCK); + 918 .loc 1 579 0 + 919 0228 069C ldr r4, [sp, #24] + 920 022a 2101 lsls r1, r4, #4 + 921 022c 0E9B ldr r3, [sp, #56] + 922 022e 9C46 mov ip, r3 + 923 0230 6144 add r1, r1, ip + 924 .LVL110: + 925 .LBB30: + 926 .LBB31: + 408:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 927 .loc 1 408 0 + 928 0232 10A8 add r0, sp, #64 + 929 .LVL111: + 930 0234 FFF7FEFF bl xor_block + 931 .LVL112: + 932 .LBE31: + 933 .LBE30: + 575:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( VERSION_1 ) + 934 .loc 1 575 0 + 935 0238 631C adds r3, r4, #1 + 936 023a DBB2 uxtb r3, r3 + 937 023c 0693 str r3, [sp, #24] + 938 .LVL113: + 939 .L19: + 575:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #if defined( VERSION_1 ) + 940 .loc 1 575 0 is_stmt 0 discriminator 1 + 941 023e F023 movs r3, #240 + 942 0240 0D9A ldr r2, [sp, #52] + 943 0242 D35C ldrb r3, [r2, r3] + 944 0244 069A ldr r2, [sp, #24] + 945 0246 9342 cmp r3, r2 + 946 0248 00D9 bls .LCB982 + 947 024a EFE6 b .L20 @long jump + 948 .LCB982: + 949 .LVL114: + 950 .LBB32: + 951 .LBB33: + 414:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 8] = s_box(st[ 8]); st[12] = s_box(st[12]); + 952 .loc 1 414 0 is_stmt 1 + 953 024c 10AB add r3, sp, #64 + 954 .LVL115: + 955 024e 1A78 ldrb r2, [r3] + 956 0250 244B ldr r3, .L22+8 + 957 .LVL116: + 958 0252 9A5C ldrb r2, [r3, r2] + 959 0254 10A9 add r1, sp, #64 + 960 .LVL117: + 961 0256 0A70 strb r2, [r1] + 962 0258 0A79 ldrb r2, [r1, #4] + 963 025a 9A5C ldrb r2, [r3, r2] + 964 025c 0A71 strb r2, [r1, #4] + 415:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 965 .loc 1 415 0 + 966 025e 0A7A ldrb r2, [r1, #8] + ARM GAS /tmp/ccJ0d890.s page 29 + + + 967 0260 9A5C ldrb r2, [r3, r2] + 968 0262 0A72 strb r2, [r1, #8] + 969 0264 0A7B ldrb r2, [r1, #12] + 970 0266 9A5C ldrb r2, [r3, r2] + 971 0268 0A73 strb r2, [r1, #12] + 417:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 9] = s_box(st[13]); st[13] = s_box( tt ); + 972 .loc 1 417 0 + 973 026a 4A78 ldrb r2, [r1, #1] + 974 .LVL118: + 975 026c 4979 ldrb r1, [r1, #5] + 976 .LVL119: + 977 026e 595C ldrb r1, [r3, r1] + 978 0270 10A8 add r0, sp, #64 + 979 .LVL120: + 980 0272 4170 strb r1, [r0, #1] + 981 0274 417A ldrb r1, [r0, #9] + 982 0276 595C ldrb r1, [r3, r1] + 983 0278 4171 strb r1, [r0, #5] + 418:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 984 .loc 1 418 0 + 985 027a 417B ldrb r1, [r0, #13] + 986 027c 595C ldrb r1, [r3, r1] + 987 027e 4172 strb r1, [r0, #9] + 988 0280 9A5C ldrb r2, [r3, r2] + 989 .LVL121: + 990 0282 4273 strb r2, [r0, #13] + 420:./Middlewares/Third_Party/Lora/Crypto/aes.c **** tt = st[6]; st[ 6] = s_box(st[14]); st[14] = s_box( tt ); + 991 .loc 1 420 0 + 992 0284 8278 ldrb r2, [r0, #2] + 993 .LVL122: + 994 0286 817A ldrb r1, [r0, #10] + 995 0288 595C ldrb r1, [r3, r1] + 996 028a 8170 strb r1, [r0, #2] + 997 028c 9A5C ldrb r2, [r3, r2] + 998 .LVL123: + 999 028e 8272 strb r2, [r0, #10] + 421:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 1000 .loc 1 421 0 + 1001 0290 8279 ldrb r2, [r0, #6] + 1002 .LVL124: + 1003 0292 817B ldrb r1, [r0, #14] + 1004 0294 595C ldrb r1, [r3, r1] + 1005 0296 8171 strb r1, [r0, #6] + 1006 0298 9A5C ldrb r2, [r3, r2] + 1007 .LVL125: + 1008 029a 8273 strb r2, [r0, #14] + 423:./Middlewares/Third_Party/Lora/Crypto/aes.c **** st[ 7] = s_box(st[ 3]); st[ 3] = s_box( tt ); + 1009 .loc 1 423 0 + 1010 029c C27B ldrb r2, [r0, #15] + 1011 .LVL126: + 1012 029e C17A ldrb r1, [r0, #11] + 1013 02a0 595C ldrb r1, [r3, r1] + 1014 02a2 C173 strb r1, [r0, #15] + 1015 02a4 C179 ldrb r1, [r0, #7] + 1016 02a6 595C ldrb r1, [r3, r1] + 1017 02a8 C172 strb r1, [r0, #11] + 424:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + ARM GAS /tmp/ccJ0d890.s page 30 + + + 1018 .loc 1 424 0 + 1019 02aa C178 ldrb r1, [r0, #3] + 1020 02ac 595C ldrb r1, [r3, r1] + 1021 02ae C171 strb r1, [r0, #7] + 1022 02b0 9B5C ldrb r3, [r3, r2] + 1023 02b2 C370 strb r3, [r0, #3] + 1024 .LVL127: + 1025 .LBE33: + 1026 .LBE32: + 580:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 581:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #else + 582:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { uint8_t s2[N_BLOCK]; + 583:./Middlewares/Third_Party/Lora/Crypto/aes.c **** mix_sub_columns( s2, s1 ); + 584:./Middlewares/Third_Party/Lora/Crypto/aes.c **** copy_and_key( s1, s2, ctx->ksch + r * N_BLOCK); + 585:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 586:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 587:./Middlewares/Third_Party/Lora/Crypto/aes.c **** shift_sub_rows( s1 ); + 588:./Middlewares/Third_Party/Lora/Crypto/aes.c **** copy_and_key( out, s1, ctx->ksch + r * N_BLOCK ); + 1027 .loc 1 588 0 + 1028 02b4 069B ldr r3, [sp, #24] + 1029 02b6 1A01 lsls r2, r3, #4 + 1030 02b8 0D9B ldr r3, [sp, #52] + 1031 02ba 9C46 mov ip, r3 + 1032 02bc 6244 add r2, r2, ip + 1033 02be 0100 movs r1, r0 + 1034 02c0 0F98 ldr r0, [sp, #60] + 1035 02c2 FFF7FEFF bl copy_and_key + 1036 .LVL128: + 1037 .LBE25: + 589:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 590:./Middlewares/Third_Party/Lora/Crypto/aes.c **** else + 591:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return ( uint8_t )-1; + 592:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0; + 1038 .loc 1 592 0 + 1039 02c6 0020 movs r0, #0 + 1040 .LVL129: + 1041 .L18: + 593:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 1042 .loc 1 593 0 + 1043 02c8 15B0 add sp, sp, #84 + 1044 @ sp needed + 1045 02ca 3CBC pop {r2, r3, r4, r5} + 1046 02cc 9046 mov r8, r2 + 1047 02ce 9946 mov r9, r3 + 1048 02d0 A246 mov r10, r4 + 1049 02d2 AB46 mov fp, r5 + 1050 02d4 F0BD pop {r4, r5, r6, r7, pc} + 1051 .LVL130: + 1052 .L21: + 591:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return 0; + 1053 .loc 1 591 0 + 1054 02d6 FF20 movs r0, #255 + 1055 .LVL131: + 1056 02d8 F6E7 b .L18 + 1057 .L23: + 1058 02da C046 .align 2 + 1059 .L22: + ARM GAS /tmp/ccJ0d890.s page 31 + + + 1060 02dc 00000000 .word gfm2_sbox + 1061 02e0 00000000 .word gfm3_sbox + 1062 02e4 00000000 .word sbox + 1063 .cfi_endproc + 1064 .LFE8: + 1066 .section .text.aes_cbc_encrypt,"ax",%progbits + 1067 .align 1 + 1068 .global aes_cbc_encrypt + 1069 .syntax unified + 1070 .code 16 + 1071 .thumb_func + 1072 .fpu softvfp + 1074 aes_cbc_encrypt: + 1075 .LFB9: + 594:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 595:./Middlewares/Third_Party/Lora/Crypto/aes.c **** /* CBC encrypt a number of blocks (input and return an IV) */ + 596:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 597:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return_type aes_cbc_encrypt( const uint8_t *in, uint8_t *out, + 598:./Middlewares/Third_Party/Lora/Crypto/aes.c **** int32_t n_block, uint8_t iv[N_BLOCK], const aes_context ctx[1] ) + 599:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 1076 .loc 1 599 0 + 1077 .cfi_startproc + 1078 @ args = 4, pretend = 0, frame = 0 + 1079 @ frame_needed = 0, uses_anonymous_args = 0 + 1080 .LVL132: + 1081 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1082 .LCFI7: + 1083 .cfi_def_cfa_offset 24 + 1084 .cfi_offset 3, -24 + 1085 .cfi_offset 4, -20 + 1086 .cfi_offset 5, -16 + 1087 .cfi_offset 6, -12 + 1088 .cfi_offset 7, -8 + 1089 .cfi_offset 14, -4 + 1090 0002 0600 movs r6, r0 + 1091 0004 0D00 movs r5, r1 + 1092 0006 1C00 movs r4, r3 + 1093 .LVL133: + 1094 .L25: + 600:./Middlewares/Third_Party/Lora/Crypto/aes.c **** + 601:./Middlewares/Third_Party/Lora/Crypto/aes.c **** while(n_block--) + 1095 .loc 1 601 0 + 1096 0008 571E subs r7, r2, #1 + 1097 .LVL134: + 1098 000a 002A cmp r2, #0 + 1099 000c 2ED0 beq .L29 + 602:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 603:./Middlewares/Third_Party/Lora/Crypto/aes.c **** xor_block(iv, in); + 1100 .loc 1 603 0 + 1101 000e 3100 movs r1, r6 + 1102 0010 2000 movs r0, r4 + 1103 0012 FFF7FEFF bl xor_block + 1104 .LVL135: + 604:./Middlewares/Third_Party/Lora/Crypto/aes.c **** if(aes_encrypt(iv, iv, ctx) != EXIT_SUCCESS) + 1105 .loc 1 604 0 + 1106 0016 069A ldr r2, [sp, #24] + 1107 0018 2100 movs r1, r4 + ARM GAS /tmp/ccJ0d890.s page 32 + + + 1108 001a 2000 movs r0, r4 + 1109 001c FFF7FEFF bl aes_encrypt + 1110 .LVL136: + 1111 0020 0028 cmp r0, #0 + 1112 0022 25D1 bne .L28 + 1113 .LVL137: + 1114 .LBB34: + 1115 .LBB35: + 323:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1]; + 1116 .loc 1 323 0 + 1117 0024 2378 ldrb r3, [r4] + 1118 0026 2B70 strb r3, [r5] + 324:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2]; + 1119 .loc 1 324 0 + 1120 0028 6378 ldrb r3, [r4, #1] + 1121 002a 6B70 strb r3, [r5, #1] + 325:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3]; + 1122 .loc 1 325 0 + 1123 002c A378 ldrb r3, [r4, #2] + 1124 002e AB70 strb r3, [r5, #2] + 326:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4]; + 1125 .loc 1 326 0 + 1126 0030 E378 ldrb r3, [r4, #3] + 1127 0032 EB70 strb r3, [r5, #3] + 327:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5]; + 1128 .loc 1 327 0 + 1129 0034 2379 ldrb r3, [r4, #4] + 1130 0036 2B71 strb r3, [r5, #4] + 328:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6]; + 1131 .loc 1 328 0 + 1132 0038 6379 ldrb r3, [r4, #5] + 1133 003a 6B71 strb r3, [r5, #5] + 329:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7]; + 1134 .loc 1 329 0 + 1135 003c A379 ldrb r3, [r4, #6] + 1136 003e AB71 strb r3, [r5, #6] + 330:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8]; + 1137 .loc 1 330 0 + 1138 0040 E379 ldrb r3, [r4, #7] + 1139 0042 EB71 strb r3, [r5, #7] + 331:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9]; + 1140 .loc 1 331 0 + 1141 0044 237A ldrb r3, [r4, #8] + 1142 0046 2B72 strb r3, [r5, #8] + 332:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[10] = ((uint8_t*)s)[10]; + 1143 .loc 1 332 0 + 1144 0048 637A ldrb r3, [r4, #9] + 1145 004a 6B72 strb r3, [r5, #9] + 333:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[11] = ((uint8_t*)s)[11]; + 1146 .loc 1 333 0 + 1147 004c A37A ldrb r3, [r4, #10] + 1148 004e AB72 strb r3, [r5, #10] + 334:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[12] = ((uint8_t*)s)[12]; + 1149 .loc 1 334 0 + 1150 0050 E37A ldrb r3, [r4, #11] + 1151 0052 EB72 strb r3, [r5, #11] + 335:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[13] = ((uint8_t*)s)[13]; + ARM GAS /tmp/ccJ0d890.s page 33 + + + 1152 .loc 1 335 0 + 1153 0054 237B ldrb r3, [r4, #12] + 1154 0056 2B73 strb r3, [r5, #12] + 336:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[14] = ((uint8_t*)s)[14]; + 1155 .loc 1 336 0 + 1156 0058 637B ldrb r3, [r4, #13] + 1157 005a 6B73 strb r3, [r5, #13] + 337:./Middlewares/Third_Party/Lora/Crypto/aes.c **** ((uint8_t*)d)[15] = ((uint8_t*)s)[15]; + 1158 .loc 1 337 0 + 1159 005c A37B ldrb r3, [r4, #14] + 1160 005e AB73 strb r3, [r5, #14] + 338:./Middlewares/Third_Party/Lora/Crypto/aes.c **** #endif + 1161 .loc 1 338 0 + 1162 0060 E37B ldrb r3, [r4, #15] + 1163 0062 EB73 strb r3, [r5, #15] + 1164 .LVL138: + 1165 .LBE35: + 1166 .LBE34: + 605:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return EXIT_FAILURE; + 606:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //memcpy(out, iv, N_BLOCK); + 607:./Middlewares/Third_Party/Lora/Crypto/aes.c **** block_copy(out, iv); + 608:./Middlewares/Third_Party/Lora/Crypto/aes.c **** in += N_BLOCK; + 1167 .loc 1 608 0 + 1168 0064 1036 adds r6, r6, #16 + 1169 .LVL139: + 609:./Middlewares/Third_Party/Lora/Crypto/aes.c **** out += N_BLOCK; + 1170 .loc 1 609 0 + 1171 0066 1035 adds r5, r5, #16 + 1172 .LVL140: + 601:./Middlewares/Third_Party/Lora/Crypto/aes.c **** { + 1173 .loc 1 601 0 + 1174 0068 3A00 movs r2, r7 + 1175 006a CDE7 b .L25 + 1176 .L29: + 610:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 611:./Middlewares/Third_Party/Lora/Crypto/aes.c **** return EXIT_SUCCESS; + 1177 .loc 1 611 0 + 1178 006c 0020 movs r0, #0 + 1179 .L26: + 612:./Middlewares/Third_Party/Lora/Crypto/aes.c **** } + 1180 .loc 1 612 0 + 1181 @ sp needed + 1182 .LVL141: + 1183 .LVL142: + 1184 .LVL143: + 1185 .LVL144: + 1186 006e F8BD pop {r3, r4, r5, r6, r7, pc} + 1187 .LVL145: + 1188 .L28: + 605:./Middlewares/Third_Party/Lora/Crypto/aes.c **** //memcpy(out, iv, N_BLOCK); + 1189 .loc 1 605 0 + 1190 0070 0120 movs r0, #1 + 1191 0072 FCE7 b .L26 + 1192 .cfi_endproc + 1193 .LFE9: + 1195 .section .rodata.gfm2_sbox,"a",%progbits + 1196 .align 2 + ARM GAS /tmp/ccJ0d890.s page 34 + + + 1199 gfm2_sbox: + 1200 0000 C6 .byte -58 + 1201 0001 F8 .byte -8 + 1202 0002 EE .byte -18 + 1203 0003 F6 .byte -10 + 1204 0004 FF .byte -1 + 1205 0005 D6 .byte -42 + 1206 0006 DE .byte -34 + 1207 0007 91 .byte -111 + 1208 0008 60 .byte 96 + 1209 0009 02 .byte 2 + 1210 000a CE .byte -50 + 1211 000b 56 .byte 86 + 1212 000c E7 .byte -25 + 1213 000d B5 .byte -75 + 1214 000e 4D .byte 77 + 1215 000f EC .byte -20 + 1216 0010 8F .byte -113 + 1217 0011 1F .byte 31 + 1218 0012 89 .byte -119 + 1219 0013 FA .byte -6 + 1220 0014 EF .byte -17 + 1221 0015 B2 .byte -78 + 1222 0016 8E .byte -114 + 1223 0017 FB .byte -5 + 1224 0018 41 .byte 65 + 1225 0019 B3 .byte -77 + 1226 001a 5F .byte 95 + 1227 001b 45 .byte 69 + 1228 001c 23 .byte 35 + 1229 001d 53 .byte 83 + 1230 001e E4 .byte -28 + 1231 001f 9B .byte -101 + 1232 0020 75 .byte 117 + 1233 0021 E1 .byte -31 + 1234 0022 3D .byte 61 + 1235 0023 4C .byte 76 + 1236 0024 6C .byte 108 + 1237 0025 7E .byte 126 + 1238 0026 F5 .byte -11 + 1239 0027 83 .byte -125 + 1240 0028 68 .byte 104 + 1241 0029 51 .byte 81 + 1242 002a D1 .byte -47 + 1243 002b F9 .byte -7 + 1244 002c E2 .byte -30 + 1245 002d AB .byte -85 + 1246 002e 62 .byte 98 + 1247 002f 2A .byte 42 + 1248 0030 08 .byte 8 + 1249 0031 95 .byte -107 + 1250 0032 46 .byte 70 + 1251 0033 9D .byte -99 + 1252 0034 30 .byte 48 + 1253 0035 37 .byte 55 + 1254 0036 0A .byte 10 + 1255 0037 2F .byte 47 + ARM GAS /tmp/ccJ0d890.s page 35 + + + 1256 0038 0E .byte 14 + 1257 0039 24 .byte 36 + 1258 003a 1B .byte 27 + 1259 003b DF .byte -33 + 1260 003c CD .byte -51 + 1261 003d 4E .byte 78 + 1262 003e 7F .byte 127 + 1263 003f EA .byte -22 + 1264 0040 12 .byte 18 + 1265 0041 1D .byte 29 + 1266 0042 58 .byte 88 + 1267 0043 34 .byte 52 + 1268 0044 36 .byte 54 + 1269 0045 DC .byte -36 + 1270 0046 B4 .byte -76 + 1271 0047 5B .byte 91 + 1272 0048 A4 .byte -92 + 1273 0049 76 .byte 118 + 1274 004a B7 .byte -73 + 1275 004b 7D .byte 125 + 1276 004c 52 .byte 82 + 1277 004d DD .byte -35 + 1278 004e 5E .byte 94 + 1279 004f 13 .byte 19 + 1280 0050 A6 .byte -90 + 1281 0051 B9 .byte -71 + 1282 0052 00 .byte 0 + 1283 0053 C1 .byte -63 + 1284 0054 40 .byte 64 + 1285 0055 E3 .byte -29 + 1286 0056 79 .byte 121 + 1287 0057 B6 .byte -74 + 1288 0058 D4 .byte -44 + 1289 0059 8D .byte -115 + 1290 005a 67 .byte 103 + 1291 005b 72 .byte 114 + 1292 005c 94 .byte -108 + 1293 005d 98 .byte -104 + 1294 005e B0 .byte -80 + 1295 005f 85 .byte -123 + 1296 0060 BB .byte -69 + 1297 0061 C5 .byte -59 + 1298 0062 4F .byte 79 + 1299 0063 ED .byte -19 + 1300 0064 86 .byte -122 + 1301 0065 9A .byte -102 + 1302 0066 66 .byte 102 + 1303 0067 11 .byte 17 + 1304 0068 8A .byte -118 + 1305 0069 E9 .byte -23 + 1306 006a 04 .byte 4 + 1307 006b FE .byte -2 + 1308 006c A0 .byte -96 + 1309 006d 78 .byte 120 + 1310 006e 25 .byte 37 + 1311 006f 4B .byte 75 + 1312 0070 A2 .byte -94 + ARM GAS /tmp/ccJ0d890.s page 36 + + + 1313 0071 5D .byte 93 + 1314 0072 80 .byte -128 + 1315 0073 05 .byte 5 + 1316 0074 3F .byte 63 + 1317 0075 21 .byte 33 + 1318 0076 70 .byte 112 + 1319 0077 F1 .byte -15 + 1320 0078 63 .byte 99 + 1321 0079 77 .byte 119 + 1322 007a AF .byte -81 + 1323 007b 42 .byte 66 + 1324 007c 20 .byte 32 + 1325 007d E5 .byte -27 + 1326 007e FD .byte -3 + 1327 007f BF .byte -65 + 1328 0080 81 .byte -127 + 1329 0081 18 .byte 24 + 1330 0082 26 .byte 38 + 1331 0083 C3 .byte -61 + 1332 0084 BE .byte -66 + 1333 0085 35 .byte 53 + 1334 0086 88 .byte -120 + 1335 0087 2E .byte 46 + 1336 0088 93 .byte -109 + 1337 0089 55 .byte 85 + 1338 008a FC .byte -4 + 1339 008b 7A .byte 122 + 1340 008c C8 .byte -56 + 1341 008d BA .byte -70 + 1342 008e 32 .byte 50 + 1343 008f E6 .byte -26 + 1344 0090 C0 .byte -64 + 1345 0091 19 .byte 25 + 1346 0092 9E .byte -98 + 1347 0093 A3 .byte -93 + 1348 0094 44 .byte 68 + 1349 0095 54 .byte 84 + 1350 0096 3B .byte 59 + 1351 0097 0B .byte 11 + 1352 0098 8C .byte -116 + 1353 0099 C7 .byte -57 + 1354 009a 6B .byte 107 + 1355 009b 28 .byte 40 + 1356 009c A7 .byte -89 + 1357 009d BC .byte -68 + 1358 009e 16 .byte 22 + 1359 009f AD .byte -83 + 1360 00a0 DB .byte -37 + 1361 00a1 64 .byte 100 + 1362 00a2 74 .byte 116 + 1363 00a3 14 .byte 20 + 1364 00a4 92 .byte -110 + 1365 00a5 0C .byte 12 + 1366 00a6 48 .byte 72 + 1367 00a7 B8 .byte -72 + 1368 00a8 9F .byte -97 + 1369 00a9 BD .byte -67 + ARM GAS /tmp/ccJ0d890.s page 37 + + + 1370 00aa 43 .byte 67 + 1371 00ab C4 .byte -60 + 1372 00ac 39 .byte 57 + 1373 00ad 31 .byte 49 + 1374 00ae D3 .byte -45 + 1375 00af F2 .byte -14 + 1376 00b0 D5 .byte -43 + 1377 00b1 8B .byte -117 + 1378 00b2 6E .byte 110 + 1379 00b3 DA .byte -38 + 1380 00b4 01 .byte 1 + 1381 00b5 B1 .byte -79 + 1382 00b6 9C .byte -100 + 1383 00b7 49 .byte 73 + 1384 00b8 D8 .byte -40 + 1385 00b9 AC .byte -84 + 1386 00ba F3 .byte -13 + 1387 00bb CF .byte -49 + 1388 00bc CA .byte -54 + 1389 00bd F4 .byte -12 + 1390 00be 47 .byte 71 + 1391 00bf 10 .byte 16 + 1392 00c0 6F .byte 111 + 1393 00c1 F0 .byte -16 + 1394 00c2 4A .byte 74 + 1395 00c3 5C .byte 92 + 1396 00c4 38 .byte 56 + 1397 00c5 57 .byte 87 + 1398 00c6 73 .byte 115 + 1399 00c7 97 .byte -105 + 1400 00c8 CB .byte -53 + 1401 00c9 A1 .byte -95 + 1402 00ca E8 .byte -24 + 1403 00cb 3E .byte 62 + 1404 00cc 96 .byte -106 + 1405 00cd 61 .byte 97 + 1406 00ce 0D .byte 13 + 1407 00cf 0F .byte 15 + 1408 00d0 E0 .byte -32 + 1409 00d1 7C .byte 124 + 1410 00d2 71 .byte 113 + 1411 00d3 CC .byte -52 + 1412 00d4 90 .byte -112 + 1413 00d5 06 .byte 6 + 1414 00d6 F7 .byte -9 + 1415 00d7 1C .byte 28 + 1416 00d8 C2 .byte -62 + 1417 00d9 6A .byte 106 + 1418 00da AE .byte -82 + 1419 00db 69 .byte 105 + 1420 00dc 17 .byte 23 + 1421 00dd 99 .byte -103 + 1422 00de 3A .byte 58 + 1423 00df 27 .byte 39 + 1424 00e0 D9 .byte -39 + 1425 00e1 EB .byte -21 + 1426 00e2 2B .byte 43 + ARM GAS /tmp/ccJ0d890.s page 38 + + + 1427 00e3 22 .byte 34 + 1428 00e4 D2 .byte -46 + 1429 00e5 A9 .byte -87 + 1430 00e6 07 .byte 7 + 1431 00e7 33 .byte 51 + 1432 00e8 2D .byte 45 + 1433 00e9 3C .byte 60 + 1434 00ea 15 .byte 21 + 1435 00eb C9 .byte -55 + 1436 00ec 87 .byte -121 + 1437 00ed AA .byte -86 + 1438 00ee 50 .byte 80 + 1439 00ef A5 .byte -91 + 1440 00f0 03 .byte 3 + 1441 00f1 59 .byte 89 + 1442 00f2 09 .byte 9 + 1443 00f3 1A .byte 26 + 1444 00f4 65 .byte 101 + 1445 00f5 D7 .byte -41 + 1446 00f6 84 .byte -124 + 1447 00f7 D0 .byte -48 + 1448 00f8 82 .byte -126 + 1449 00f9 29 .byte 41 + 1450 00fa 5A .byte 90 + 1451 00fb 1E .byte 30 + 1452 00fc 7B .byte 123 + 1453 00fd A8 .byte -88 + 1454 00fe 6D .byte 109 + 1455 00ff 2C .byte 44 + 1456 .section .rodata.gfm3_sbox,"a",%progbits + 1457 .align 2 + 1460 gfm3_sbox: + 1461 0000 A5 .byte -91 + 1462 0001 84 .byte -124 + 1463 0002 99 .byte -103 + 1464 0003 8D .byte -115 + 1465 0004 0D .byte 13 + 1466 0005 BD .byte -67 + 1467 0006 B1 .byte -79 + 1468 0007 54 .byte 84 + 1469 0008 50 .byte 80 + 1470 0009 03 .byte 3 + 1471 000a A9 .byte -87 + 1472 000b 7D .byte 125 + 1473 000c 19 .byte 25 + 1474 000d 62 .byte 98 + 1475 000e E6 .byte -26 + 1476 000f 9A .byte -102 + 1477 0010 45 .byte 69 + 1478 0011 9D .byte -99 + 1479 0012 40 .byte 64 + 1480 0013 87 .byte -121 + 1481 0014 15 .byte 21 + 1482 0015 EB .byte -21 + 1483 0016 C9 .byte -55 + 1484 0017 0B .byte 11 + 1485 0018 EC .byte -20 + ARM GAS /tmp/ccJ0d890.s page 39 + + + 1486 0019 67 .byte 103 + 1487 001a FD .byte -3 + 1488 001b EA .byte -22 + 1489 001c BF .byte -65 + 1490 001d F7 .byte -9 + 1491 001e 96 .byte -106 + 1492 001f 5B .byte 91 + 1493 0020 C2 .byte -62 + 1494 0021 1C .byte 28 + 1495 0022 AE .byte -82 + 1496 0023 6A .byte 106 + 1497 0024 5A .byte 90 + 1498 0025 41 .byte 65 + 1499 0026 02 .byte 2 + 1500 0027 4F .byte 79 + 1501 0028 5C .byte 92 + 1502 0029 F4 .byte -12 + 1503 002a 34 .byte 52 + 1504 002b 08 .byte 8 + 1505 002c 93 .byte -109 + 1506 002d 73 .byte 115 + 1507 002e 53 .byte 83 + 1508 002f 3F .byte 63 + 1509 0030 0C .byte 12 + 1510 0031 52 .byte 82 + 1511 0032 65 .byte 101 + 1512 0033 5E .byte 94 + 1513 0034 28 .byte 40 + 1514 0035 A1 .byte -95 + 1515 0036 0F .byte 15 + 1516 0037 B5 .byte -75 + 1517 0038 09 .byte 9 + 1518 0039 36 .byte 54 + 1519 003a 9B .byte -101 + 1520 003b 3D .byte 61 + 1521 003c 26 .byte 38 + 1522 003d 69 .byte 105 + 1523 003e CD .byte -51 + 1524 003f 9F .byte -97 + 1525 0040 1B .byte 27 + 1526 0041 9E .byte -98 + 1527 0042 74 .byte 116 + 1528 0043 2E .byte 46 + 1529 0044 2D .byte 45 + 1530 0045 B2 .byte -78 + 1531 0046 EE .byte -18 + 1532 0047 FB .byte -5 + 1533 0048 F6 .byte -10 + 1534 0049 4D .byte 77 + 1535 004a 61 .byte 97 + 1536 004b CE .byte -50 + 1537 004c 7B .byte 123 + 1538 004d 3E .byte 62 + 1539 004e 71 .byte 113 + 1540 004f 97 .byte -105 + 1541 0050 F5 .byte -11 + 1542 0051 68 .byte 104 + ARM GAS /tmp/ccJ0d890.s page 40 + + + 1543 0052 00 .byte 0 + 1544 0053 2C .byte 44 + 1545 0054 60 .byte 96 + 1546 0055 1F .byte 31 + 1547 0056 C8 .byte -56 + 1548 0057 ED .byte -19 + 1549 0058 BE .byte -66 + 1550 0059 46 .byte 70 + 1551 005a D9 .byte -39 + 1552 005b 4B .byte 75 + 1553 005c DE .byte -34 + 1554 005d D4 .byte -44 + 1555 005e E8 .byte -24 + 1556 005f 4A .byte 74 + 1557 0060 6B .byte 107 + 1558 0061 2A .byte 42 + 1559 0062 E5 .byte -27 + 1560 0063 16 .byte 22 + 1561 0064 C5 .byte -59 + 1562 0065 D7 .byte -41 + 1563 0066 55 .byte 85 + 1564 0067 94 .byte -108 + 1565 0068 CF .byte -49 + 1566 0069 10 .byte 16 + 1567 006a 06 .byte 6 + 1568 006b 81 .byte -127 + 1569 006c F0 .byte -16 + 1570 006d 44 .byte 68 + 1571 006e BA .byte -70 + 1572 006f E3 .byte -29 + 1573 0070 F3 .byte -13 + 1574 0071 FE .byte -2 + 1575 0072 C0 .byte -64 + 1576 0073 8A .byte -118 + 1577 0074 AD .byte -83 + 1578 0075 BC .byte -68 + 1579 0076 48 .byte 72 + 1580 0077 04 .byte 4 + 1581 0078 DF .byte -33 + 1582 0079 C1 .byte -63 + 1583 007a 75 .byte 117 + 1584 007b 63 .byte 99 + 1585 007c 30 .byte 48 + 1586 007d 1A .byte 26 + 1587 007e 0E .byte 14 + 1588 007f 6D .byte 109 + 1589 0080 4C .byte 76 + 1590 0081 14 .byte 20 + 1591 0082 35 .byte 53 + 1592 0083 2F .byte 47 + 1593 0084 E1 .byte -31 + 1594 0085 A2 .byte -94 + 1595 0086 CC .byte -52 + 1596 0087 39 .byte 57 + 1597 0088 57 .byte 87 + 1598 0089 F2 .byte -14 + 1599 008a 82 .byte -126 + ARM GAS /tmp/ccJ0d890.s page 41 + + + 1600 008b 47 .byte 71 + 1601 008c AC .byte -84 + 1602 008d E7 .byte -25 + 1603 008e 2B .byte 43 + 1604 008f 95 .byte -107 + 1605 0090 A0 .byte -96 + 1606 0091 98 .byte -104 + 1607 0092 D1 .byte -47 + 1608 0093 7F .byte 127 + 1609 0094 66 .byte 102 + 1610 0095 7E .byte 126 + 1611 0096 AB .byte -85 + 1612 0097 83 .byte -125 + 1613 0098 CA .byte -54 + 1614 0099 29 .byte 41 + 1615 009a D3 .byte -45 + 1616 009b 3C .byte 60 + 1617 009c 79 .byte 121 + 1618 009d E2 .byte -30 + 1619 009e 1D .byte 29 + 1620 009f 76 .byte 118 + 1621 00a0 3B .byte 59 + 1622 00a1 56 .byte 86 + 1623 00a2 4E .byte 78 + 1624 00a3 1E .byte 30 + 1625 00a4 DB .byte -37 + 1626 00a5 0A .byte 10 + 1627 00a6 6C .byte 108 + 1628 00a7 E4 .byte -28 + 1629 00a8 5D .byte 93 + 1630 00a9 6E .byte 110 + 1631 00aa EF .byte -17 + 1632 00ab A6 .byte -90 + 1633 00ac A8 .byte -88 + 1634 00ad A4 .byte -92 + 1635 00ae 37 .byte 55 + 1636 00af 8B .byte -117 + 1637 00b0 32 .byte 50 + 1638 00b1 43 .byte 67 + 1639 00b2 59 .byte 89 + 1640 00b3 B7 .byte -73 + 1641 00b4 8C .byte -116 + 1642 00b5 64 .byte 100 + 1643 00b6 D2 .byte -46 + 1644 00b7 E0 .byte -32 + 1645 00b8 B4 .byte -76 + 1646 00b9 FA .byte -6 + 1647 00ba 07 .byte 7 + 1648 00bb 25 .byte 37 + 1649 00bc AF .byte -81 + 1650 00bd 8E .byte -114 + 1651 00be E9 .byte -23 + 1652 00bf 18 .byte 24 + 1653 00c0 D5 .byte -43 + 1654 00c1 88 .byte -120 + 1655 00c2 6F .byte 111 + 1656 00c3 72 .byte 114 + ARM GAS /tmp/ccJ0d890.s page 42 + + + 1657 00c4 24 .byte 36 + 1658 00c5 F1 .byte -15 + 1659 00c6 C7 .byte -57 + 1660 00c7 51 .byte 81 + 1661 00c8 23 .byte 35 + 1662 00c9 7C .byte 124 + 1663 00ca 9C .byte -100 + 1664 00cb 21 .byte 33 + 1665 00cc DD .byte -35 + 1666 00cd DC .byte -36 + 1667 00ce 86 .byte -122 + 1668 00cf 85 .byte -123 + 1669 00d0 90 .byte -112 + 1670 00d1 42 .byte 66 + 1671 00d2 C4 .byte -60 + 1672 00d3 AA .byte -86 + 1673 00d4 D8 .byte -40 + 1674 00d5 05 .byte 5 + 1675 00d6 01 .byte 1 + 1676 00d7 12 .byte 18 + 1677 00d8 A3 .byte -93 + 1678 00d9 5F .byte 95 + 1679 00da F9 .byte -7 + 1680 00db D0 .byte -48 + 1681 00dc 91 .byte -111 + 1682 00dd 58 .byte 88 + 1683 00de 27 .byte 39 + 1684 00df B9 .byte -71 + 1685 00e0 38 .byte 56 + 1686 00e1 13 .byte 19 + 1687 00e2 B3 .byte -77 + 1688 00e3 33 .byte 51 + 1689 00e4 BB .byte -69 + 1690 00e5 70 .byte 112 + 1691 00e6 89 .byte -119 + 1692 00e7 A7 .byte -89 + 1693 00e8 B6 .byte -74 + 1694 00e9 22 .byte 34 + 1695 00ea 92 .byte -110 + 1696 00eb 20 .byte 32 + 1697 00ec 49 .byte 73 + 1698 00ed FF .byte -1 + 1699 00ee 78 .byte 120 + 1700 00ef 7A .byte 122 + 1701 00f0 8F .byte -113 + 1702 00f1 F8 .byte -8 + 1703 00f2 80 .byte -128 + 1704 00f3 17 .byte 23 + 1705 00f4 DA .byte -38 + 1706 00f5 31 .byte 49 + 1707 00f6 C6 .byte -58 + 1708 00f7 B8 .byte -72 + 1709 00f8 C3 .byte -61 + 1710 00f9 B0 .byte -80 + 1711 00fa 77 .byte 119 + 1712 00fb 11 .byte 17 + 1713 00fc CB .byte -53 + ARM GAS /tmp/ccJ0d890.s page 43 + + + 1714 00fd FC .byte -4 + 1715 00fe D6 .byte -42 + 1716 00ff 3A .byte 58 + 1717 .section .rodata.sbox,"a",%progbits + 1718 .align 2 + 1721 sbox: + 1722 0000 63 .byte 99 + 1723 0001 7C .byte 124 + 1724 0002 77 .byte 119 + 1725 0003 7B .byte 123 + 1726 0004 F2 .byte -14 + 1727 0005 6B .byte 107 + 1728 0006 6F .byte 111 + 1729 0007 C5 .byte -59 + 1730 0008 30 .byte 48 + 1731 0009 01 .byte 1 + 1732 000a 67 .byte 103 + 1733 000b 2B .byte 43 + 1734 000c FE .byte -2 + 1735 000d D7 .byte -41 + 1736 000e AB .byte -85 + 1737 000f 76 .byte 118 + 1738 0010 CA .byte -54 + 1739 0011 82 .byte -126 + 1740 0012 C9 .byte -55 + 1741 0013 7D .byte 125 + 1742 0014 FA .byte -6 + 1743 0015 59 .byte 89 + 1744 0016 47 .byte 71 + 1745 0017 F0 .byte -16 + 1746 0018 AD .byte -83 + 1747 0019 D4 .byte -44 + 1748 001a A2 .byte -94 + 1749 001b AF .byte -81 + 1750 001c 9C .byte -100 + 1751 001d A4 .byte -92 + 1752 001e 72 .byte 114 + 1753 001f C0 .byte -64 + 1754 0020 B7 .byte -73 + 1755 0021 FD .byte -3 + 1756 0022 93 .byte -109 + 1757 0023 26 .byte 38 + 1758 0024 36 .byte 54 + 1759 0025 3F .byte 63 + 1760 0026 F7 .byte -9 + 1761 0027 CC .byte -52 + 1762 0028 34 .byte 52 + 1763 0029 A5 .byte -91 + 1764 002a E5 .byte -27 + 1765 002b F1 .byte -15 + 1766 002c 71 .byte 113 + 1767 002d D8 .byte -40 + 1768 002e 31 .byte 49 + 1769 002f 15 .byte 21 + 1770 0030 04 .byte 4 + 1771 0031 C7 .byte -57 + 1772 0032 23 .byte 35 + ARM GAS /tmp/ccJ0d890.s page 44 + + + 1773 0033 C3 .byte -61 + 1774 0034 18 .byte 24 + 1775 0035 96 .byte -106 + 1776 0036 05 .byte 5 + 1777 0037 9A .byte -102 + 1778 0038 07 .byte 7 + 1779 0039 12 .byte 18 + 1780 003a 80 .byte -128 + 1781 003b E2 .byte -30 + 1782 003c EB .byte -21 + 1783 003d 27 .byte 39 + 1784 003e B2 .byte -78 + 1785 003f 75 .byte 117 + 1786 0040 09 .byte 9 + 1787 0041 83 .byte -125 + 1788 0042 2C .byte 44 + 1789 0043 1A .byte 26 + 1790 0044 1B .byte 27 + 1791 0045 6E .byte 110 + 1792 0046 5A .byte 90 + 1793 0047 A0 .byte -96 + 1794 0048 52 .byte 82 + 1795 0049 3B .byte 59 + 1796 004a D6 .byte -42 + 1797 004b B3 .byte -77 + 1798 004c 29 .byte 41 + 1799 004d E3 .byte -29 + 1800 004e 2F .byte 47 + 1801 004f 84 .byte -124 + 1802 0050 53 .byte 83 + 1803 0051 D1 .byte -47 + 1804 0052 00 .byte 0 + 1805 0053 ED .byte -19 + 1806 0054 20 .byte 32 + 1807 0055 FC .byte -4 + 1808 0056 B1 .byte -79 + 1809 0057 5B .byte 91 + 1810 0058 6A .byte 106 + 1811 0059 CB .byte -53 + 1812 005a BE .byte -66 + 1813 005b 39 .byte 57 + 1814 005c 4A .byte 74 + 1815 005d 4C .byte 76 + 1816 005e 58 .byte 88 + 1817 005f CF .byte -49 + 1818 0060 D0 .byte -48 + 1819 0061 EF .byte -17 + 1820 0062 AA .byte -86 + 1821 0063 FB .byte -5 + 1822 0064 43 .byte 67 + 1823 0065 4D .byte 77 + 1824 0066 33 .byte 51 + 1825 0067 85 .byte -123 + 1826 0068 45 .byte 69 + 1827 0069 F9 .byte -7 + 1828 006a 02 .byte 2 + 1829 006b 7F .byte 127 + ARM GAS /tmp/ccJ0d890.s page 45 + + + 1830 006c 50 .byte 80 + 1831 006d 3C .byte 60 + 1832 006e 9F .byte -97 + 1833 006f A8 .byte -88 + 1834 0070 51 .byte 81 + 1835 0071 A3 .byte -93 + 1836 0072 40 .byte 64 + 1837 0073 8F .byte -113 + 1838 0074 92 .byte -110 + 1839 0075 9D .byte -99 + 1840 0076 38 .byte 56 + 1841 0077 F5 .byte -11 + 1842 0078 BC .byte -68 + 1843 0079 B6 .byte -74 + 1844 007a DA .byte -38 + 1845 007b 21 .byte 33 + 1846 007c 10 .byte 16 + 1847 007d FF .byte -1 + 1848 007e F3 .byte -13 + 1849 007f D2 .byte -46 + 1850 0080 CD .byte -51 + 1851 0081 0C .byte 12 + 1852 0082 13 .byte 19 + 1853 0083 EC .byte -20 + 1854 0084 5F .byte 95 + 1855 0085 97 .byte -105 + 1856 0086 44 .byte 68 + 1857 0087 17 .byte 23 + 1858 0088 C4 .byte -60 + 1859 0089 A7 .byte -89 + 1860 008a 7E .byte 126 + 1861 008b 3D .byte 61 + 1862 008c 64 .byte 100 + 1863 008d 5D .byte 93 + 1864 008e 19 .byte 25 + 1865 008f 73 .byte 115 + 1866 0090 60 .byte 96 + 1867 0091 81 .byte -127 + 1868 0092 4F .byte 79 + 1869 0093 DC .byte -36 + 1870 0094 22 .byte 34 + 1871 0095 2A .byte 42 + 1872 0096 90 .byte -112 + 1873 0097 88 .byte -120 + 1874 0098 46 .byte 70 + 1875 0099 EE .byte -18 + 1876 009a B8 .byte -72 + 1877 009b 14 .byte 20 + 1878 009c DE .byte -34 + 1879 009d 5E .byte 94 + 1880 009e 0B .byte 11 + 1881 009f DB .byte -37 + 1882 00a0 E0 .byte -32 + 1883 00a1 32 .byte 50 + 1884 00a2 3A .byte 58 + 1885 00a3 0A .byte 10 + 1886 00a4 49 .byte 73 + ARM GAS /tmp/ccJ0d890.s page 46 + + + 1887 00a5 06 .byte 6 + 1888 00a6 24 .byte 36 + 1889 00a7 5C .byte 92 + 1890 00a8 C2 .byte -62 + 1891 00a9 D3 .byte -45 + 1892 00aa AC .byte -84 + 1893 00ab 62 .byte 98 + 1894 00ac 91 .byte -111 + 1895 00ad 95 .byte -107 + 1896 00ae E4 .byte -28 + 1897 00af 79 .byte 121 + 1898 00b0 E7 .byte -25 + 1899 00b1 C8 .byte -56 + 1900 00b2 37 .byte 55 + 1901 00b3 6D .byte 109 + 1902 00b4 8D .byte -115 + 1903 00b5 D5 .byte -43 + 1904 00b6 4E .byte 78 + 1905 00b7 A9 .byte -87 + 1906 00b8 6C .byte 108 + 1907 00b9 56 .byte 86 + 1908 00ba F4 .byte -12 + 1909 00bb EA .byte -22 + 1910 00bc 65 .byte 101 + 1911 00bd 7A .byte 122 + 1912 00be AE .byte -82 + 1913 00bf 08 .byte 8 + 1914 00c0 BA .byte -70 + 1915 00c1 78 .byte 120 + 1916 00c2 25 .byte 37 + 1917 00c3 2E .byte 46 + 1918 00c4 1C .byte 28 + 1919 00c5 A6 .byte -90 + 1920 00c6 B4 .byte -76 + 1921 00c7 C6 .byte -58 + 1922 00c8 E8 .byte -24 + 1923 00c9 DD .byte -35 + 1924 00ca 74 .byte 116 + 1925 00cb 1F .byte 31 + 1926 00cc 4B .byte 75 + 1927 00cd BD .byte -67 + 1928 00ce 8B .byte -117 + 1929 00cf 8A .byte -118 + 1930 00d0 70 .byte 112 + 1931 00d1 3E .byte 62 + 1932 00d2 B5 .byte -75 + 1933 00d3 66 .byte 102 + 1934 00d4 48 .byte 72 + 1935 00d5 03 .byte 3 + 1936 00d6 F6 .byte -10 + 1937 00d7 0E .byte 14 + 1938 00d8 61 .byte 97 + 1939 00d9 35 .byte 53 + 1940 00da 57 .byte 87 + 1941 00db B9 .byte -71 + 1942 00dc 86 .byte -122 + 1943 00dd C1 .byte -63 + ARM GAS /tmp/ccJ0d890.s page 47 + + + 1944 00de 1D .byte 29 + 1945 00df 9E .byte -98 + 1946 00e0 E1 .byte -31 + 1947 00e1 F8 .byte -8 + 1948 00e2 98 .byte -104 + 1949 00e3 11 .byte 17 + 1950 00e4 69 .byte 105 + 1951 00e5 D9 .byte -39 + 1952 00e6 8E .byte -114 + 1953 00e7 94 .byte -108 + 1954 00e8 9B .byte -101 + 1955 00e9 1E .byte 30 + 1956 00ea 87 .byte -121 + 1957 00eb E9 .byte -23 + 1958 00ec CE .byte -50 + 1959 00ed 55 .byte 85 + 1960 00ee 28 .byte 40 + 1961 00ef DF .byte -33 + 1962 00f0 8C .byte -116 + 1963 00f1 A1 .byte -95 + 1964 00f2 89 .byte -119 + 1965 00f3 0D .byte 13 + 1966 00f4 BF .byte -65 + 1967 00f5 E6 .byte -26 + 1968 00f6 42 .byte 66 + 1969 00f7 68 .byte 104 + 1970 00f8 41 .byte 65 + 1971 00f9 99 .byte -103 + 1972 00fa 2D .byte 45 + 1973 00fb 0F .byte 15 + 1974 00fc B0 .byte -80 + 1975 00fd 54 .byte 84 + 1976 00fe BB .byte -69 + 1977 00ff 16 .byte 22 + 1978 .text + 1979 .Letext0: + 1980 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1981 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 1982 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 1983 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1984 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 1985 .file 7 "/usr/arm-none-eabi/include/stdlib.h" + 1986 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1987 .file 9 "./Middlewares/Third_Party/Lora/Crypto/aes.h" + ARM GAS /tmp/ccJ0d890.s page 48 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 aes.c + /tmp/ccJ0d890.s:16 .text.xor_block:0000000000000000 $t + /tmp/ccJ0d890.s:22 .text.xor_block:0000000000000000 xor_block + /tmp/ccJ0d890.s:118 .text.copy_and_key:0000000000000000 $t + /tmp/ccJ0d890.s:124 .text.copy_and_key:0000000000000000 copy_and_key + /tmp/ccJ0d890.s:225 .text.aes_set_key:0000000000000000 $t + /tmp/ccJ0d890.s:232 .text.aes_set_key:0000000000000000 aes_set_key + /tmp/ccJ0d890.s:498 .text.aes_set_key:0000000000000128 $d + /tmp/ccJ0d890.s:1721 .rodata.sbox:0000000000000000 sbox + /tmp/ccJ0d890.s:503 .text.aes_encrypt:0000000000000000 $t + /tmp/ccJ0d890.s:510 .text.aes_encrypt:0000000000000000 aes_encrypt + /tmp/ccJ0d890.s:1060 .text.aes_encrypt:00000000000002dc $d + /tmp/ccJ0d890.s:1199 .rodata.gfm2_sbox:0000000000000000 gfm2_sbox + /tmp/ccJ0d890.s:1460 .rodata.gfm3_sbox:0000000000000000 gfm3_sbox + /tmp/ccJ0d890.s:1067 .text.aes_cbc_encrypt:0000000000000000 $t + /tmp/ccJ0d890.s:1074 .text.aes_cbc_encrypt:0000000000000000 aes_cbc_encrypt + /tmp/ccJ0d890.s:1196 .rodata.gfm2_sbox:0000000000000000 $d + /tmp/ccJ0d890.s:1457 .rodata.gfm3_sbox:0000000000000000 $d + /tmp/ccJ0d890.s:1718 .rodata.sbox:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidivmod diff --git a/build/bees.bin b/build/bees.bin new file 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@param[in] dev :Structure instance of bme680_dev. + 85:Drivers/BME680/bme680.c **** * + 86:Drivers/BME680/bme680.c **** * @return Result of API execution status. + 87:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 88:Drivers/BME680/bme680.c **** */ + 89:Drivers/BME680/bme680.c **** static int8_t set_gas_config(struct bme680_dev *dev); + 90:Drivers/BME680/bme680.c **** + 91:Drivers/BME680/bme680.c **** /*! + ARM GAS /tmp/ccvbgJts.s page 3 + + + 92:Drivers/BME680/bme680.c **** * @brief This internal API is used to get the gas configuration of the sensor. + 93:Drivers/BME680/bme680.c **** * + 94:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 95:Drivers/BME680/bme680.c **** * + 96:Drivers/BME680/bme680.c **** * @return Result of API execution status. + 97:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 98:Drivers/BME680/bme680.c **** */ + 99:Drivers/BME680/bme680.c **** static int8_t get_gas_config(struct bme680_dev *dev); + 100:Drivers/BME680/bme680.c **** + 101:Drivers/BME680/bme680.c **** /*! + 102:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Heat duration value. + 103:Drivers/BME680/bme680.c **** * + 104:Drivers/BME680/bme680.c **** * @param[in] dur :Value of the duration to be shared. + 105:Drivers/BME680/bme680.c **** * + 106:Drivers/BME680/bme680.c **** * @return uint8_t threshold duration after calculation. + 107:Drivers/BME680/bme680.c **** */ + 108:Drivers/BME680/bme680.c **** static uint8_t calc_heater_dur(uint16_t dur); + 109:Drivers/BME680/bme680.c **** + 110:Drivers/BME680/bme680.c **** /*! + 111:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the temperature value. + 112:Drivers/BME680/bme680.c **** * + 113:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 114:Drivers/BME680/bme680.c **** * @param[in] temp_adc :Contains the temperature ADC value . + 115:Drivers/BME680/bme680.c **** * + 116:Drivers/BME680/bme680.c **** * @return uint32_t calculated temperature. + 117:Drivers/BME680/bme680.c **** */ + 118:Drivers/BME680/bme680.c **** static int16_t calc_temperature(uint32_t temp_adc, struct bme680_dev *dev); + 119:Drivers/BME680/bme680.c **** + 120:Drivers/BME680/bme680.c **** /*! + 121:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the pressure value. + 122:Drivers/BME680/bme680.c **** * + 123:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 124:Drivers/BME680/bme680.c **** * @param[in] pres_adc :Contains the pressure ADC value . + 125:Drivers/BME680/bme680.c **** * + 126:Drivers/BME680/bme680.c **** * @return uint32_t calculated pressure. + 127:Drivers/BME680/bme680.c **** */ + 128:Drivers/BME680/bme680.c **** static uint32_t calc_pressure(uint32_t pres_adc, const struct bme680_dev *dev); + 129:Drivers/BME680/bme680.c **** + 130:Drivers/BME680/bme680.c **** /*! + 131:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the humidity value. + 132:Drivers/BME680/bme680.c **** * + 133:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 134:Drivers/BME680/bme680.c **** * @param[in] hum_adc :Contains the humidity ADC value. + 135:Drivers/BME680/bme680.c **** * + 136:Drivers/BME680/bme680.c **** * @return uint32_t calculated humidity. + 137:Drivers/BME680/bme680.c **** */ + 138:Drivers/BME680/bme680.c **** static uint32_t calc_humidity(uint16_t hum_adc, const struct bme680_dev *dev); + 139:Drivers/BME680/bme680.c **** + 140:Drivers/BME680/bme680.c **** /*! + 141:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Gas Resistance value. + 142:Drivers/BME680/bme680.c **** * + 143:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 144:Drivers/BME680/bme680.c **** * @param[in] gas_res_adc :Contains the Gas Resistance ADC value. + 145:Drivers/BME680/bme680.c **** * @param[in] gas_range :Contains the range of gas values. + 146:Drivers/BME680/bme680.c **** * + 147:Drivers/BME680/bme680.c **** * @return uint32_t calculated gas resistance. + 148:Drivers/BME680/bme680.c **** */ + ARM GAS /tmp/ccvbgJts.s page 4 + + + 149:Drivers/BME680/bme680.c **** static uint32_t calc_gas_resistance(uint16_t gas_res_adc, uint8_t gas_range, const struct bme680_de + 150:Drivers/BME680/bme680.c **** + 151:Drivers/BME680/bme680.c **** /*! + 152:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Heat Resistance value. + 153:Drivers/BME680/bme680.c **** * + 154:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 155:Drivers/BME680/bme680.c **** * @param[in] temp :Contains the temporary value. + 156:Drivers/BME680/bme680.c **** * + 157:Drivers/BME680/bme680.c **** * @return uint8_t calculated heater resistance. + 158:Drivers/BME680/bme680.c **** */ + 159:Drivers/BME680/bme680.c **** static uint8_t calc_heater_res(uint16_t temp, const struct bme680_dev *dev); + 160:Drivers/BME680/bme680.c **** + 161:Drivers/BME680/bme680.c **** /*! + 162:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the field data of sensor. + 163:Drivers/BME680/bme680.c **** * + 164:Drivers/BME680/bme680.c **** * @param[out] data :Structure instance to hold the data + 165:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 166:Drivers/BME680/bme680.c **** * + 167:Drivers/BME680/bme680.c **** * @return int8_t result of the field data from sensor. + 168:Drivers/BME680/bme680.c **** */ + 169:Drivers/BME680/bme680.c **** static int8_t read_field_data(struct bme680_field_data *data, struct bme680_dev *dev); + 170:Drivers/BME680/bme680.c **** + 171:Drivers/BME680/bme680.c **** /*! + 172:Drivers/BME680/bme680.c **** * @brief This internal API is used to set the memory page + 173:Drivers/BME680/bme680.c **** * based on register address. + 174:Drivers/BME680/bme680.c **** * + 175:Drivers/BME680/bme680.c **** * The value of memory page + 176:Drivers/BME680/bme680.c **** * value | Description + 177:Drivers/BME680/bme680.c **** * --------|-------------- + 178:Drivers/BME680/bme680.c **** * 0 | BME680_PAGE0_SPI + 179:Drivers/BME680/bme680.c **** * 1 | BME680_PAGE1_SPI + 180:Drivers/BME680/bme680.c **** * + 181:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 182:Drivers/BME680/bme680.c **** * @param[in] reg_addr :Contains the register address array. + 183:Drivers/BME680/bme680.c **** * + 184:Drivers/BME680/bme680.c **** * @return Result of API execution status + 185:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 186:Drivers/BME680/bme680.c **** */ + 187:Drivers/BME680/bme680.c **** static int8_t set_mem_page(uint8_t reg_addr, struct bme680_dev *dev); + 188:Drivers/BME680/bme680.c **** + 189:Drivers/BME680/bme680.c **** /*! + 190:Drivers/BME680/bme680.c **** * @brief This internal API is used to get the memory page based + 191:Drivers/BME680/bme680.c **** * on register address. + 192:Drivers/BME680/bme680.c **** * + 193:Drivers/BME680/bme680.c **** * The value of memory page + 194:Drivers/BME680/bme680.c **** * value | Description + 195:Drivers/BME680/bme680.c **** * --------|-------------- + 196:Drivers/BME680/bme680.c **** * 0 | BME680_PAGE0_SPI + 197:Drivers/BME680/bme680.c **** * 1 | BME680_PAGE1_SPI + 198:Drivers/BME680/bme680.c **** * + 199:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 200:Drivers/BME680/bme680.c **** * + 201:Drivers/BME680/bme680.c **** * @return Result of API execution status + 202:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 203:Drivers/BME680/bme680.c **** */ + 204:Drivers/BME680/bme680.c **** static int8_t get_mem_page(struct bme680_dev *dev); + 205:Drivers/BME680/bme680.c **** + ARM GAS /tmp/ccvbgJts.s page 5 + + + 206:Drivers/BME680/bme680.c **** /*! + 207:Drivers/BME680/bme680.c **** * @brief This internal API is used to validate the device pointer for + 208:Drivers/BME680/bme680.c **** * null conditions. + 209:Drivers/BME680/bme680.c **** * + 210:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 211:Drivers/BME680/bme680.c **** * + 212:Drivers/BME680/bme680.c **** * @return Result of API execution status + 213:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 214:Drivers/BME680/bme680.c **** */ + 215:Drivers/BME680/bme680.c **** static int8_t null_ptr_check(const struct bme680_dev *dev); + 216:Drivers/BME680/bme680.c **** + 217:Drivers/BME680/bme680.c **** /*! + 218:Drivers/BME680/bme680.c **** * @brief This internal API is used to check the boundary + 219:Drivers/BME680/bme680.c **** * conditions. + 220:Drivers/BME680/bme680.c **** * + 221:Drivers/BME680/bme680.c **** * @param[in] value :pointer to the value. + 222:Drivers/BME680/bme680.c **** * @param[in] min :minimum value. + 223:Drivers/BME680/bme680.c **** * @param[in] max :maximum value. + 224:Drivers/BME680/bme680.c **** * @param[in] dev :Structure instance of bme680_dev. + 225:Drivers/BME680/bme680.c **** * + 226:Drivers/BME680/bme680.c **** * @return Result of API execution status + 227:Drivers/BME680/bme680.c **** * @retval zero -> Success / +ve value -> Warning / -ve value -> Error + 228:Drivers/BME680/bme680.c **** */ + 229:Drivers/BME680/bme680.c **** static int8_t boundary_check(uint8_t *value, uint8_t min, uint8_t max, struct bme680_dev *dev); + 230:Drivers/BME680/bme680.c **** + 231:Drivers/BME680/bme680.c **** /****************** Global Function Definitions *******************************/ + 232:Drivers/BME680/bme680.c **** /*! + 233:Drivers/BME680/bme680.c **** *@brief This API is the entry point. + 234:Drivers/BME680/bme680.c **** *It reads the chip-id and calibration data from the sensor. + 235:Drivers/BME680/bme680.c **** */ + 236:Drivers/BME680/bme680.c **** int8_t bme680_init(struct bme680_dev *dev) + 237:Drivers/BME680/bme680.c **** { + 238:Drivers/BME680/bme680.c **** int8_t rslt; + 239:Drivers/BME680/bme680.c **** + 240:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 241:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 242:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 243:Drivers/BME680/bme680.c **** /* Soft reset to restore it to default values*/ + 244:Drivers/BME680/bme680.c **** rslt = bme680_soft_reset(dev); + 245:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 246:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_CHIP_ID_ADDR, &dev->chip_id, 1, dev); + 247:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 248:Drivers/BME680/bme680.c **** if (dev->chip_id == BME680_CHIP_ID) { + 249:Drivers/BME680/bme680.c **** /* Get the Calibration data */ + 250:Drivers/BME680/bme680.c **** rslt = get_calib_data(dev); + 251:Drivers/BME680/bme680.c **** } else { + 252:Drivers/BME680/bme680.c **** rslt = BME680_E_DEV_NOT_FOUND; + 253:Drivers/BME680/bme680.c **** } + 254:Drivers/BME680/bme680.c **** } + 255:Drivers/BME680/bme680.c **** } + 256:Drivers/BME680/bme680.c **** } + 257:Drivers/BME680/bme680.c **** + 258:Drivers/BME680/bme680.c **** return rslt; + 259:Drivers/BME680/bme680.c **** } + 260:Drivers/BME680/bme680.c **** + 261:Drivers/BME680/bme680.c **** /*! + 262:Drivers/BME680/bme680.c **** * @brief This API reads the data from the given register address of the sensor. + ARM GAS /tmp/ccvbgJts.s page 6 + + + 263:Drivers/BME680/bme680.c **** */ + 264:Drivers/BME680/bme680.c **** int8_t bme680_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bme680_dev *dev) + 265:Drivers/BME680/bme680.c **** { + 266:Drivers/BME680/bme680.c **** int8_t rslt; + 267:Drivers/BME680/bme680.c **** + 268:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 269:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 270:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 271:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) { + 272:Drivers/BME680/bme680.c **** /* Set the memory page */ + 273:Drivers/BME680/bme680.c **** rslt = set_mem_page(reg_addr, dev); + 274:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 275:Drivers/BME680/bme680.c **** reg_addr = reg_addr | BME680_SPI_RD_MSK; + 276:Drivers/BME680/bme680.c **** } + 277:Drivers/BME680/bme680.c **** dev->com_rslt = dev->read(dev->dev_id, reg_addr, reg_data, len); + 278:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 279:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 280:Drivers/BME680/bme680.c **** } + 281:Drivers/BME680/bme680.c **** + 282:Drivers/BME680/bme680.c **** return rslt; + 283:Drivers/BME680/bme680.c **** } + 284:Drivers/BME680/bme680.c **** + 285:Drivers/BME680/bme680.c **** /*! + 286:Drivers/BME680/bme680.c **** * @brief This API writes the given data to the register address + 287:Drivers/BME680/bme680.c **** * of the sensor. + 288:Drivers/BME680/bme680.c **** */ + 289:Drivers/BME680/bme680.c **** int8_t bme680_set_regs(const uint8_t *reg_addr, const uint8_t *reg_data, uint8_t len, struct bme680 + 290:Drivers/BME680/bme680.c **** { + 291:Drivers/BME680/bme680.c **** int8_t rslt; + 292:Drivers/BME680/bme680.c **** /* Length of the temporary buffer is 2*(length of register)*/ + 293:Drivers/BME680/bme680.c **** uint8_t tmp_buff[BME680_TMP_BUFFER_LENGTH] = { 0 }; + 294:Drivers/BME680/bme680.c **** uint16_t index; + 295:Drivers/BME680/bme680.c **** + 296:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 297:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 298:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 299:Drivers/BME680/bme680.c **** if ((len > 0) && (len < BME680_TMP_BUFFER_LENGTH / 2)) { + 300:Drivers/BME680/bme680.c **** /* Interleave the 2 arrays */ + 301:Drivers/BME680/bme680.c **** for (index = 0; index < len; index++) { + 302:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) { + 303:Drivers/BME680/bme680.c **** /* Set the memory page */ + 304:Drivers/BME680/bme680.c **** rslt = set_mem_page(reg_addr[index], dev); + 305:Drivers/BME680/bme680.c **** tmp_buff[(2 * index)] = reg_addr[index] & BME680_SPI_WR_MSK; + 306:Drivers/BME680/bme680.c **** } else { + 307:Drivers/BME680/bme680.c **** tmp_buff[(2 * index)] = reg_addr[index]; + 308:Drivers/BME680/bme680.c **** } + 309:Drivers/BME680/bme680.c **** tmp_buff[(2 * index) + 1] = reg_data[index]; + 310:Drivers/BME680/bme680.c **** } + 311:Drivers/BME680/bme680.c **** /* Write the interleaved array */ + 312:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 313:Drivers/BME680/bme680.c **** dev->com_rslt = dev->write(dev->dev_id, tmp_buff[0], &tmp_buff[1], (2 * len) - 1); + 314:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 315:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 316:Drivers/BME680/bme680.c **** } + 317:Drivers/BME680/bme680.c **** } else { + 318:Drivers/BME680/bme680.c **** rslt = BME680_E_INVALID_LENGTH; + 319:Drivers/BME680/bme680.c **** } + ARM GAS /tmp/ccvbgJts.s page 7 + + + 320:Drivers/BME680/bme680.c **** } + 321:Drivers/BME680/bme680.c **** + 322:Drivers/BME680/bme680.c **** return rslt; + 323:Drivers/BME680/bme680.c **** } + 324:Drivers/BME680/bme680.c **** + 325:Drivers/BME680/bme680.c **** /*! + 326:Drivers/BME680/bme680.c **** * @brief This API performs the soft reset of the sensor. + 327:Drivers/BME680/bme680.c **** */ + 328:Drivers/BME680/bme680.c **** int8_t bme680_soft_reset(struct bme680_dev *dev) + 329:Drivers/BME680/bme680.c **** { + 330:Drivers/BME680/bme680.c **** int8_t rslt; + 331:Drivers/BME680/bme680.c **** uint8_t reg_addr = BME680_SOFT_RESET_ADDR; + 332:Drivers/BME680/bme680.c **** /* 0xb6 is the soft reset command */ + 333:Drivers/BME680/bme680.c **** uint8_t soft_rst_cmd = BME680_SOFT_RESET_CMD; + 334:Drivers/BME680/bme680.c **** + 335:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 336:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 337:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 338:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) + 339:Drivers/BME680/bme680.c **** rslt = get_mem_page(dev); + 340:Drivers/BME680/bme680.c **** + 341:Drivers/BME680/bme680.c **** /* Reset the device */ + 342:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 343:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &soft_rst_cmd, 1, dev); + 344:Drivers/BME680/bme680.c **** /* Wait for 5ms */ + 345:Drivers/BME680/bme680.c **** dev->delay_ms(BME680_RESET_PERIOD); + 346:Drivers/BME680/bme680.c **** + 347:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 348:Drivers/BME680/bme680.c **** /* After reset get the memory page */ + 349:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) + 350:Drivers/BME680/bme680.c **** rslt = get_mem_page(dev); + 351:Drivers/BME680/bme680.c **** } + 352:Drivers/BME680/bme680.c **** } + 353:Drivers/BME680/bme680.c **** } + 354:Drivers/BME680/bme680.c **** + 355:Drivers/BME680/bme680.c **** return rslt; + 356:Drivers/BME680/bme680.c **** } + 357:Drivers/BME680/bme680.c **** + 358:Drivers/BME680/bme680.c **** /*! + 359:Drivers/BME680/bme680.c **** * @brief This API is used to set the oversampling, filter and T,P,H, gas selection + 360:Drivers/BME680/bme680.c **** * settings in the sensor. + 361:Drivers/BME680/bme680.c **** */ + 362:Drivers/BME680/bme680.c **** int8_t bme680_set_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev) + 363:Drivers/BME680/bme680.c **** { + 364:Drivers/BME680/bme680.c **** int8_t rslt; + 365:Drivers/BME680/bme680.c **** uint8_t reg_addr; + 366:Drivers/BME680/bme680.c **** uint8_t data = 0; + 367:Drivers/BME680/bme680.c **** uint8_t count = 0; + 368:Drivers/BME680/bme680.c **** uint8_t reg_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + 369:Drivers/BME680/bme680.c **** uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + 370:Drivers/BME680/bme680.c **** uint8_t intended_power_mode = dev->power_mode; /* Save intended power mode */ + 371:Drivers/BME680/bme680.c **** + 372:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 373:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 374:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 375:Drivers/BME680/bme680.c **** if (desired_settings & BME680_GAS_MEAS_SEL) + 376:Drivers/BME680/bme680.c **** rslt = set_gas_config(dev); + ARM GAS /tmp/ccvbgJts.s page 8 + + + 377:Drivers/BME680/bme680.c **** + 378:Drivers/BME680/bme680.c **** dev->power_mode = BME680_SLEEP_MODE; + 379:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 380:Drivers/BME680/bme680.c **** rslt = bme680_set_sensor_mode(dev); + 381:Drivers/BME680/bme680.c **** + 382:Drivers/BME680/bme680.c **** /* Selecting the filter */ + 383:Drivers/BME680/bme680.c **** if (desired_settings & BME680_FILTER_SEL) { + 384:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.filter, BME680_FILTER_SIZE_0, BME680_FILTER_SIZE_127, dev); + 385:Drivers/BME680/bme680.c **** reg_addr = BME680_CONF_ODR_FILT_ADDR; + 386:Drivers/BME680/bme680.c **** + 387:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 388:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, &data, 1, dev); + 389:Drivers/BME680/bme680.c **** + 390:Drivers/BME680/bme680.c **** if (desired_settings & BME680_FILTER_SEL) + 391:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_FILTER, dev->tph_sett.filter); + 392:Drivers/BME680/bme680.c **** + 393:Drivers/BME680/bme680.c **** reg_array[count] = reg_addr; /* Append configuration */ + 394:Drivers/BME680/bme680.c **** data_array[count] = data; + 395:Drivers/BME680/bme680.c **** count++; + 396:Drivers/BME680/bme680.c **** } + 397:Drivers/BME680/bme680.c **** + 398:Drivers/BME680/bme680.c **** /* Selecting heater control for the sensor */ + 399:Drivers/BME680/bme680.c **** if (desired_settings & BME680_HCNTRL_SEL) { + 400:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->gas_sett.heatr_ctrl, BME680_ENABLE_HEATER, + 401:Drivers/BME680/bme680.c **** BME680_DISABLE_HEATER, dev); + 402:Drivers/BME680/bme680.c **** reg_addr = BME680_CONF_HEAT_CTRL_ADDR; + 403:Drivers/BME680/bme680.c **** + 404:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 405:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, &data, 1, dev); + 406:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_HCTRL, dev->gas_sett.heatr_ctrl); + 407:Drivers/BME680/bme680.c **** + 408:Drivers/BME680/bme680.c **** reg_array[count] = reg_addr; /* Append configuration */ + 409:Drivers/BME680/bme680.c **** data_array[count] = data; + 410:Drivers/BME680/bme680.c **** count++; + 411:Drivers/BME680/bme680.c **** } + 412:Drivers/BME680/bme680.c **** + 413:Drivers/BME680/bme680.c **** /* Selecting heater T,P oversampling for the sensor */ + 414:Drivers/BME680/bme680.c **** if (desired_settings & (BME680_OST_SEL | BME680_OSP_SEL)) { + 415:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.os_temp, BME680_OS_NONE, BME680_OS_16X, dev); + 416:Drivers/BME680/bme680.c **** reg_addr = BME680_CONF_T_P_MODE_ADDR; + 417:Drivers/BME680/bme680.c **** + 418:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 419:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, &data, 1, dev); + 420:Drivers/BME680/bme680.c **** + 421:Drivers/BME680/bme680.c **** if (desired_settings & BME680_OST_SEL) + 422:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_OST, dev->tph_sett.os_temp); + 423:Drivers/BME680/bme680.c **** + 424:Drivers/BME680/bme680.c **** if (desired_settings & BME680_OSP_SEL) + 425:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_OSP, dev->tph_sett.os_pres); + 426:Drivers/BME680/bme680.c **** + 427:Drivers/BME680/bme680.c **** reg_array[count] = reg_addr; + 428:Drivers/BME680/bme680.c **** data_array[count] = data; + 429:Drivers/BME680/bme680.c **** count++; + 430:Drivers/BME680/bme680.c **** } + 431:Drivers/BME680/bme680.c **** + 432:Drivers/BME680/bme680.c **** /* Selecting humidity oversampling for the sensor */ + 433:Drivers/BME680/bme680.c **** if (desired_settings & BME680_OSH_SEL) { + ARM GAS /tmp/ccvbgJts.s page 9 + + + 434:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.os_hum, BME680_OS_NONE, BME680_OS_16X, dev); + 435:Drivers/BME680/bme680.c **** reg_addr = BME680_CONF_OS_H_ADDR; + 436:Drivers/BME680/bme680.c **** + 437:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 438:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, &data, 1, dev); + 439:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_OSH, dev->tph_sett.os_hum); + 440:Drivers/BME680/bme680.c **** + 441:Drivers/BME680/bme680.c **** reg_array[count] = reg_addr; /* Append configuration */ + 442:Drivers/BME680/bme680.c **** data_array[count] = data; + 443:Drivers/BME680/bme680.c **** count++; + 444:Drivers/BME680/bme680.c **** } + 445:Drivers/BME680/bme680.c **** + 446:Drivers/BME680/bme680.c **** /* Selecting the runGas and NB conversion settings for the sensor */ + 447:Drivers/BME680/bme680.c **** if (desired_settings & (BME680_RUN_GAS_SEL | BME680_NBCONV_SEL)) { + 448:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->gas_sett.run_gas, BME680_RUN_GAS_DISABLE, + 449:Drivers/BME680/bme680.c **** BME680_RUN_GAS_ENABLE, dev); + 450:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 451:Drivers/BME680/bme680.c **** /* Validate boundary conditions */ + 452:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->gas_sett.nb_conv, BME680_NBCONV_MIN, + 453:Drivers/BME680/bme680.c **** BME680_NBCONV_MAX, dev); + 454:Drivers/BME680/bme680.c **** } + 455:Drivers/BME680/bme680.c **** + 456:Drivers/BME680/bme680.c **** reg_addr = BME680_CONF_ODR_RUN_GAS_NBC_ADDR; + 457:Drivers/BME680/bme680.c **** + 458:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 459:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, &data, 1, dev); + 460:Drivers/BME680/bme680.c **** + 461:Drivers/BME680/bme680.c **** if (desired_settings & BME680_RUN_GAS_SEL) + 462:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_RUN_GAS, dev->gas_sett.run_gas); + 463:Drivers/BME680/bme680.c **** + 464:Drivers/BME680/bme680.c **** if (desired_settings & BME680_NBCONV_SEL) + 465:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_NBCONV, dev->gas_sett.nb_conv); + 466:Drivers/BME680/bme680.c **** + 467:Drivers/BME680/bme680.c **** reg_array[count] = reg_addr; /* Append configuration */ + 468:Drivers/BME680/bme680.c **** data_array[count] = data; + 469:Drivers/BME680/bme680.c **** count++; + 470:Drivers/BME680/bme680.c **** } + 471:Drivers/BME680/bme680.c **** + 472:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 473:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(reg_array, data_array, count, dev); + 474:Drivers/BME680/bme680.c **** + 475:Drivers/BME680/bme680.c **** /* Restore previous intended power mode */ + 476:Drivers/BME680/bme680.c **** dev->power_mode = intended_power_mode; + 477:Drivers/BME680/bme680.c **** } + 478:Drivers/BME680/bme680.c **** + 479:Drivers/BME680/bme680.c **** return rslt; + 480:Drivers/BME680/bme680.c **** } + 481:Drivers/BME680/bme680.c **** + 482:Drivers/BME680/bme680.c **** /*! + 483:Drivers/BME680/bme680.c **** * @brief This API is used to get the oversampling, filter and T,P,H, gas selection + 484:Drivers/BME680/bme680.c **** * settings in the sensor. + 485:Drivers/BME680/bme680.c **** */ + 486:Drivers/BME680/bme680.c **** int8_t bme680_get_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev) + 487:Drivers/BME680/bme680.c **** { + 488:Drivers/BME680/bme680.c **** int8_t rslt; + 489:Drivers/BME680/bme680.c **** /* starting address of the register array for burst read*/ + 490:Drivers/BME680/bme680.c **** uint8_t reg_addr = BME680_CONF_HEAT_CTRL_ADDR; + ARM GAS /tmp/ccvbgJts.s page 10 + + + 491:Drivers/BME680/bme680.c **** uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + 492:Drivers/BME680/bme680.c **** + 493:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 494:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 495:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 496:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr, data_array, BME680_REG_BUFFER_LENGTH, dev); + 497:Drivers/BME680/bme680.c **** + 498:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 499:Drivers/BME680/bme680.c **** if (desired_settings & BME680_GAS_MEAS_SEL) + 500:Drivers/BME680/bme680.c **** rslt = get_gas_config(dev); + 501:Drivers/BME680/bme680.c **** + 502:Drivers/BME680/bme680.c **** /* get the T,P,H ,Filter,ODR settings here */ + 503:Drivers/BME680/bme680.c **** if (desired_settings & BME680_FILTER_SEL) + 504:Drivers/BME680/bme680.c **** dev->tph_sett.filter = BME680_GET_BITS(data_array[BME680_REG_FILTER_INDEX], + 505:Drivers/BME680/bme680.c **** BME680_FILTER); + 506:Drivers/BME680/bme680.c **** + 507:Drivers/BME680/bme680.c **** if (desired_settings & (BME680_OST_SEL | BME680_OSP_SEL)) { + 508:Drivers/BME680/bme680.c **** dev->tph_sett.os_temp = BME680_GET_BITS(data_array[BME680_REG_TEMP_INDEX], BME680_OST); + 509:Drivers/BME680/bme680.c **** dev->tph_sett.os_pres = BME680_GET_BITS(data_array[BME680_REG_PRES_INDEX], BME680_OSP); + 510:Drivers/BME680/bme680.c **** } + 511:Drivers/BME680/bme680.c **** + 512:Drivers/BME680/bme680.c **** if (desired_settings & BME680_OSH_SEL) + 513:Drivers/BME680/bme680.c **** dev->tph_sett.os_hum = BME680_GET_BITS_POS_0(data_array[BME680_REG_HUM_INDEX], + 514:Drivers/BME680/bme680.c **** BME680_OSH); + 515:Drivers/BME680/bme680.c **** + 516:Drivers/BME680/bme680.c **** /* get the gas related settings */ + 517:Drivers/BME680/bme680.c **** if (desired_settings & BME680_HCNTRL_SEL) + 518:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_ctrl = BME680_GET_BITS_POS_0(data_array[BME680_REG_HCTRL_INDEX], + 519:Drivers/BME680/bme680.c **** BME680_HCTRL); + 520:Drivers/BME680/bme680.c **** + 521:Drivers/BME680/bme680.c **** if (desired_settings & (BME680_RUN_GAS_SEL | BME680_NBCONV_SEL)) { + 522:Drivers/BME680/bme680.c **** dev->gas_sett.nb_conv = BME680_GET_BITS_POS_0(data_array[BME680_REG_NBCONV_INDEX], + 523:Drivers/BME680/bme680.c **** BME680_NBCONV); + 524:Drivers/BME680/bme680.c **** dev->gas_sett.run_gas = BME680_GET_BITS(data_array[BME680_REG_RUN_GAS_INDEX], + 525:Drivers/BME680/bme680.c **** BME680_RUN_GAS); + 526:Drivers/BME680/bme680.c **** } + 527:Drivers/BME680/bme680.c **** } + 528:Drivers/BME680/bme680.c **** } else { + 529:Drivers/BME680/bme680.c **** rslt = BME680_E_NULL_PTR; + 530:Drivers/BME680/bme680.c **** } + 531:Drivers/BME680/bme680.c **** + 532:Drivers/BME680/bme680.c **** return rslt; + 533:Drivers/BME680/bme680.c **** } + 534:Drivers/BME680/bme680.c **** + 535:Drivers/BME680/bme680.c **** /*! + 536:Drivers/BME680/bme680.c **** * @brief This API is used to set the power mode of the sensor. + 537:Drivers/BME680/bme680.c **** */ + 538:Drivers/BME680/bme680.c **** int8_t bme680_set_sensor_mode(struct bme680_dev *dev) + 539:Drivers/BME680/bme680.c **** { + 540:Drivers/BME680/bme680.c **** int8_t rslt; + 541:Drivers/BME680/bme680.c **** uint8_t tmp_pow_mode; + 542:Drivers/BME680/bme680.c **** uint8_t pow_mode = 0; + 543:Drivers/BME680/bme680.c **** uint8_t reg_addr = BME680_CONF_T_P_MODE_ADDR; + 544:Drivers/BME680/bme680.c **** + 545:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 546:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 547:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + ARM GAS /tmp/ccvbgJts.s page 11 + + + 548:Drivers/BME680/bme680.c **** /* Call recursively until in sleep */ + 549:Drivers/BME680/bme680.c **** do { + 550:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_CONF_T_P_MODE_ADDR, &tmp_pow_mode, 1, dev); + 551:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 552:Drivers/BME680/bme680.c **** /* Put to sleep before changing mode */ + 553:Drivers/BME680/bme680.c **** pow_mode = (tmp_pow_mode & BME680_MODE_MSK); + 554:Drivers/BME680/bme680.c **** + 555:Drivers/BME680/bme680.c **** if (pow_mode != BME680_SLEEP_MODE) { + 556:Drivers/BME680/bme680.c **** tmp_pow_mode = tmp_pow_mode & (~BME680_MODE_MSK); /* Set to sleep */ + 557:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + 558:Drivers/BME680/bme680.c **** dev->delay_ms(BME680_POLL_PERIOD_MS); + 559:Drivers/BME680/bme680.c **** } + 560:Drivers/BME680/bme680.c **** } + 561:Drivers/BME680/bme680.c **** } while (pow_mode != BME680_SLEEP_MODE); + 562:Drivers/BME680/bme680.c **** + 563:Drivers/BME680/bme680.c **** /* Already in sleep */ + 564:Drivers/BME680/bme680.c **** if (dev->power_mode != BME680_SLEEP_MODE) { + 565:Drivers/BME680/bme680.c **** tmp_pow_mode = (tmp_pow_mode & ~BME680_MODE_MSK) | (dev->power_mode & BME680_MODE_MSK); + 566:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 567:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + 568:Drivers/BME680/bme680.c **** } + 569:Drivers/BME680/bme680.c **** } + 570:Drivers/BME680/bme680.c **** + 571:Drivers/BME680/bme680.c **** return rslt; + 572:Drivers/BME680/bme680.c **** } + 573:Drivers/BME680/bme680.c **** + 574:Drivers/BME680/bme680.c **** /*! + 575:Drivers/BME680/bme680.c **** * @brief This API is used to get the power mode of the sensor. + 576:Drivers/BME680/bme680.c **** */ + 577:Drivers/BME680/bme680.c **** int8_t bme680_get_sensor_mode(struct bme680_dev *dev) + 578:Drivers/BME680/bme680.c **** { + 579:Drivers/BME680/bme680.c **** int8_t rslt; + 580:Drivers/BME680/bme680.c **** uint8_t mode; + 581:Drivers/BME680/bme680.c **** + 582:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 583:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 584:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 585:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_CONF_T_P_MODE_ADDR, &mode, 1, dev); + 586:Drivers/BME680/bme680.c **** /* Masking the other register bit info*/ + 587:Drivers/BME680/bme680.c **** dev->power_mode = mode & BME680_MODE_MSK; + 588:Drivers/BME680/bme680.c **** } + 589:Drivers/BME680/bme680.c **** + 590:Drivers/BME680/bme680.c **** return rslt; + 591:Drivers/BME680/bme680.c **** } + 592:Drivers/BME680/bme680.c **** + 593:Drivers/BME680/bme680.c **** /*! + 594:Drivers/BME680/bme680.c **** * @brief This API is used to set the profile duration of the sensor. + 595:Drivers/BME680/bme680.c **** */ + 596:Drivers/BME680/bme680.c **** void bme680_set_profile_dur(uint16_t duration, struct bme680_dev *dev) + 597:Drivers/BME680/bme680.c **** { + 598:Drivers/BME680/bme680.c **** uint32_t tph_dur; /* Calculate in us */ + 599:Drivers/BME680/bme680.c **** + 600:Drivers/BME680/bme680.c **** /* TPH measurement duration */ + 601:Drivers/BME680/bme680.c **** tph_dur = ((uint32_t) (dev->tph_sett.os_temp + dev->tph_sett.os_pres + dev->tph_sett.os_hum) * UIN + 602:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + 603:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 5); /* Gas measurement duration */ + 604:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(500); /* Get it to the closest whole number.*/ + ARM GAS /tmp/ccvbgJts.s page 12 + + + 605:Drivers/BME680/bme680.c **** tph_dur /= UINT32_C(1000); /* Convert to ms */ + 606:Drivers/BME680/bme680.c **** + 607:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(1); /* Wake up duration of 1ms */ + 608:Drivers/BME680/bme680.c **** /* The remaining time should be used for heating */ + 609:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_dur = duration - (uint16_t) tph_dur; + 610:Drivers/BME680/bme680.c **** } + 611:Drivers/BME680/bme680.c **** + 612:Drivers/BME680/bme680.c **** /*! + 613:Drivers/BME680/bme680.c **** * @brief This API is used to get the profile duration of the sensor. + 614:Drivers/BME680/bme680.c **** */ + 615:Drivers/BME680/bme680.c **** void bme680_get_profile_dur(uint16_t *duration, const struct bme680_dev *dev) + 616:Drivers/BME680/bme680.c **** { + 617:Drivers/BME680/bme680.c **** uint32_t tph_dur; /* Calculate in us */ + 618:Drivers/BME680/bme680.c **** + 619:Drivers/BME680/bme680.c **** /* TPH measurement duration */ + 620:Drivers/BME680/bme680.c **** tph_dur = ((uint32_t) (dev->tph_sett.os_temp + dev->tph_sett.os_pres + dev->tph_sett.os_hum) * UIN + 621:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + 622:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 5); /* Gas measurement duration */ + 623:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(500); /* Get it to the closest whole number.*/ + 624:Drivers/BME680/bme680.c **** tph_dur /= UINT32_C(1000); /* Convert to ms */ + 625:Drivers/BME680/bme680.c **** + 626:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(1); /* Wake up duration of 1ms */ + 627:Drivers/BME680/bme680.c **** + 628:Drivers/BME680/bme680.c **** *duration = (uint16_t) tph_dur; + 629:Drivers/BME680/bme680.c **** + 630:Drivers/BME680/bme680.c **** /* Get the gas duration only when the run gas is enabled */ + 631:Drivers/BME680/bme680.c **** if (dev->gas_sett.run_gas) { + 632:Drivers/BME680/bme680.c **** /* The remaining time should be used for heating */ + 633:Drivers/BME680/bme680.c **** *duration += dev->gas_sett.heatr_dur; + 634:Drivers/BME680/bme680.c **** } + 635:Drivers/BME680/bme680.c **** } + 636:Drivers/BME680/bme680.c **** + 637:Drivers/BME680/bme680.c **** /*! + 638:Drivers/BME680/bme680.c **** * @brief This API reads the pressure, temperature and humidity and gas data + 639:Drivers/BME680/bme680.c **** * from the sensor, compensates the data and store it in the bme680_data + 640:Drivers/BME680/bme680.c **** * structure instance passed by the user. + 641:Drivers/BME680/bme680.c **** */ + 642:Drivers/BME680/bme680.c **** int8_t bme680_get_sensor_data(struct bme680_field_data *data, struct bme680_dev *dev) + 643:Drivers/BME680/bme680.c **** { + 644:Drivers/BME680/bme680.c **** int8_t rslt; + 645:Drivers/BME680/bme680.c **** + 646:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 647:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 648:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 649:Drivers/BME680/bme680.c **** /* Reading the sensor data in forced mode only */ + 650:Drivers/BME680/bme680.c **** rslt = read_field_data(data, dev); + 651:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 652:Drivers/BME680/bme680.c **** if (data->status & BME680_NEW_DATA_MSK) + 653:Drivers/BME680/bme680.c **** dev->new_fields = 1; + 654:Drivers/BME680/bme680.c **** else + 655:Drivers/BME680/bme680.c **** dev->new_fields = 0; + 656:Drivers/BME680/bme680.c **** } + 657:Drivers/BME680/bme680.c **** } + 658:Drivers/BME680/bme680.c **** + 659:Drivers/BME680/bme680.c **** return rslt; + 660:Drivers/BME680/bme680.c **** } + 661:Drivers/BME680/bme680.c **** + ARM GAS /tmp/ccvbgJts.s page 13 + + + 662:Drivers/BME680/bme680.c **** /*! + 663:Drivers/BME680/bme680.c **** * @brief This internal API is used to read the calibrated data from the sensor. + 664:Drivers/BME680/bme680.c **** */ + 665:Drivers/BME680/bme680.c **** static int8_t get_calib_data(struct bme680_dev *dev) + 666:Drivers/BME680/bme680.c **** { + 667:Drivers/BME680/bme680.c **** int8_t rslt; + 668:Drivers/BME680/bme680.c **** uint8_t coeff_array[BME680_COEFF_SIZE] = { 0 }; + 669:Drivers/BME680/bme680.c **** uint8_t temp_var = 0; /* Temporary variable */ + 670:Drivers/BME680/bme680.c **** + 671:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 672:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 673:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 674:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_COEFF_ADDR1, coeff_array, BME680_COEFF_ADDR1_LEN, dev); + 675:Drivers/BME680/bme680.c **** /* Append the second half in the same array */ + 676:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 677:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_COEFF_ADDR2, &coeff_array[BME680_COEFF_ADDR1_LEN] + 678:Drivers/BME680/bme680.c **** , BME680_COEFF_ADDR2_LEN, dev); + 679:Drivers/BME680/bme680.c **** + 680:Drivers/BME680/bme680.c **** /* Temperature related coefficients */ + 681:Drivers/BME680/bme680.c **** dev->calib.par_t1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T1_MSB_REG], + 682:Drivers/BME680/bme680.c **** coeff_array[BME680_T1_LSB_REG])); + 683:Drivers/BME680/bme680.c **** dev->calib.par_t2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T2_MSB_REG], + 684:Drivers/BME680/bme680.c **** coeff_array[BME680_T2_LSB_REG])); + 685:Drivers/BME680/bme680.c **** dev->calib.par_t3 = (int8_t) (coeff_array[BME680_T3_REG]); + 686:Drivers/BME680/bme680.c **** + 687:Drivers/BME680/bme680.c **** /* Pressure related coefficients */ + 688:Drivers/BME680/bme680.c **** dev->calib.par_p1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P1_MSB_REG], + 689:Drivers/BME680/bme680.c **** coeff_array[BME680_P1_LSB_REG])); + 690:Drivers/BME680/bme680.c **** dev->calib.par_p2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P2_MSB_REG], + 691:Drivers/BME680/bme680.c **** coeff_array[BME680_P2_LSB_REG])); + 692:Drivers/BME680/bme680.c **** dev->calib.par_p3 = (int8_t) coeff_array[BME680_P3_REG]; + 693:Drivers/BME680/bme680.c **** dev->calib.par_p4 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P4_MSB_REG], + 694:Drivers/BME680/bme680.c **** coeff_array[BME680_P4_LSB_REG])); + 695:Drivers/BME680/bme680.c **** dev->calib.par_p5 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P5_MSB_REG], + 696:Drivers/BME680/bme680.c **** coeff_array[BME680_P5_LSB_REG])); + 697:Drivers/BME680/bme680.c **** dev->calib.par_p6 = (int8_t) (coeff_array[BME680_P6_REG]); + 698:Drivers/BME680/bme680.c **** dev->calib.par_p7 = (int8_t) (coeff_array[BME680_P7_REG]); + 699:Drivers/BME680/bme680.c **** dev->calib.par_p8 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P8_MSB_REG], + 700:Drivers/BME680/bme680.c **** coeff_array[BME680_P8_LSB_REG])); + 701:Drivers/BME680/bme680.c **** dev->calib.par_p9 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P9_MSB_REG], + 702:Drivers/BME680/bme680.c **** coeff_array[BME680_P9_LSB_REG])); + 703:Drivers/BME680/bme680.c **** dev->calib.par_p10 = (uint8_t) (coeff_array[BME680_P10_REG]); + 704:Drivers/BME680/bme680.c **** + 705:Drivers/BME680/bme680.c **** /* Humidity related coefficients */ + 706:Drivers/BME680/bme680.c **** dev->calib.par_h1 = (uint16_t) (((uint16_t) coeff_array[BME680_H1_MSB_REG] << BME680_HUM_REG_SHIF + 707:Drivers/BME680/bme680.c **** | (coeff_array[BME680_H1_LSB_REG] & BME680_BIT_H1_DATA_MSK)); + 708:Drivers/BME680/bme680.c **** dev->calib.par_h2 = (uint16_t) (((uint16_t) coeff_array[BME680_H2_MSB_REG] << BME680_HUM_REG_SHIF + 709:Drivers/BME680/bme680.c **** | ((coeff_array[BME680_H2_LSB_REG]) >> BME680_HUM_REG_SHIFT_VAL)); + 710:Drivers/BME680/bme680.c **** dev->calib.par_h3 = (int8_t) coeff_array[BME680_H3_REG]; + 711:Drivers/BME680/bme680.c **** dev->calib.par_h4 = (int8_t) coeff_array[BME680_H4_REG]; + 712:Drivers/BME680/bme680.c **** dev->calib.par_h5 = (int8_t) coeff_array[BME680_H5_REG]; + 713:Drivers/BME680/bme680.c **** dev->calib.par_h6 = (uint8_t) coeff_array[BME680_H6_REG]; + 714:Drivers/BME680/bme680.c **** dev->calib.par_h7 = (int8_t) coeff_array[BME680_H7_REG]; + 715:Drivers/BME680/bme680.c **** + 716:Drivers/BME680/bme680.c **** /* Gas heater related coefficients */ + 717:Drivers/BME680/bme680.c **** dev->calib.par_gh1 = (int8_t) coeff_array[BME680_GH1_REG]; + 718:Drivers/BME680/bme680.c **** dev->calib.par_gh2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_GH2_MSB_REG], + ARM GAS /tmp/ccvbgJts.s page 14 + + + 719:Drivers/BME680/bme680.c **** coeff_array[BME680_GH2_LSB_REG])); + 720:Drivers/BME680/bme680.c **** dev->calib.par_gh3 = (int8_t) coeff_array[BME680_GH3_REG]; + 721:Drivers/BME680/bme680.c **** + 722:Drivers/BME680/bme680.c **** /* Other coefficients */ + 723:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 724:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_RANGE_ADDR, &temp_var, 1, dev); + 725:Drivers/BME680/bme680.c **** + 726:Drivers/BME680/bme680.c **** dev->calib.res_heat_range = ((temp_var & BME680_RHRANGE_MSK) / 16); + 727:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 728:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_VAL_ADDR, &temp_var, 1, dev); + 729:Drivers/BME680/bme680.c **** + 730:Drivers/BME680/bme680.c **** dev->calib.res_heat_val = (int8_t) temp_var; + 731:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 732:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RANGE_SW_ERR_ADDR, &temp_var, 1, dev); + 733:Drivers/BME680/bme680.c **** } + 734:Drivers/BME680/bme680.c **** } + 735:Drivers/BME680/bme680.c **** dev->calib.range_sw_err = ((int8_t) temp_var & (int8_t) BME680_RSERROR_MSK) / 16; + 736:Drivers/BME680/bme680.c **** } + 737:Drivers/BME680/bme680.c **** + 738:Drivers/BME680/bme680.c **** return rslt; + 739:Drivers/BME680/bme680.c **** } + 740:Drivers/BME680/bme680.c **** + 741:Drivers/BME680/bme680.c **** /*! + 742:Drivers/BME680/bme680.c **** * @brief This internal API is used to set the gas configuration of the sensor. + 743:Drivers/BME680/bme680.c **** */ + 744:Drivers/BME680/bme680.c **** static int8_t set_gas_config(struct bme680_dev *dev) + 745:Drivers/BME680/bme680.c **** { + 746:Drivers/BME680/bme680.c **** int8_t rslt; + 747:Drivers/BME680/bme680.c **** + 748:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 749:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 750:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 751:Drivers/BME680/bme680.c **** + 752:Drivers/BME680/bme680.c **** uint8_t reg_addr[2] = {0}; + 753:Drivers/BME680/bme680.c **** uint8_t reg_data[2] = {0}; + 754:Drivers/BME680/bme680.c **** + 755:Drivers/BME680/bme680.c **** if (dev->power_mode == BME680_FORCED_MODE) { + 756:Drivers/BME680/bme680.c **** reg_addr[0] = BME680_RES_HEAT0_ADDR; + 757:Drivers/BME680/bme680.c **** reg_data[0] = calc_heater_res(dev->gas_sett.heatr_temp, dev); + 758:Drivers/BME680/bme680.c **** reg_addr[1] = BME680_GAS_WAIT0_ADDR; + 759:Drivers/BME680/bme680.c **** reg_data[1] = calc_heater_dur(dev->gas_sett.heatr_dur); + 760:Drivers/BME680/bme680.c **** dev->gas_sett.nb_conv = 0; + 761:Drivers/BME680/bme680.c **** } else { + 762:Drivers/BME680/bme680.c **** rslt = BME680_W_DEFINE_PWR_MODE; + 763:Drivers/BME680/bme680.c **** } + 764:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 765:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(reg_addr, reg_data, 2, dev); + 766:Drivers/BME680/bme680.c **** } + 767:Drivers/BME680/bme680.c **** + 768:Drivers/BME680/bme680.c **** return rslt; + 769:Drivers/BME680/bme680.c **** } + 770:Drivers/BME680/bme680.c **** + 771:Drivers/BME680/bme680.c **** /*! + 772:Drivers/BME680/bme680.c **** * @brief This internal API is used to get the gas configuration of the sensor. + 773:Drivers/BME680/bme680.c **** */ + 774:Drivers/BME680/bme680.c **** static int8_t get_gas_config(struct bme680_dev *dev) + 775:Drivers/BME680/bme680.c **** { + ARM GAS /tmp/ccvbgJts.s page 15 + + + 776:Drivers/BME680/bme680.c **** int8_t rslt; + 777:Drivers/BME680/bme680.c **** /* starting address of the register array for burst read*/ + 778:Drivers/BME680/bme680.c **** uint8_t reg_addr1 = BME680_ADDR_SENS_CONF_START; + 779:Drivers/BME680/bme680.c **** uint8_t reg_addr2 = BME680_ADDR_GAS_CONF_START; + 780:Drivers/BME680/bme680.c **** uint8_t data_array[BME680_GAS_HEATER_PROF_LEN_MAX] = { 0 }; + 781:Drivers/BME680/bme680.c **** uint8_t index; + 782:Drivers/BME680/bme680.c **** + 783:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 784:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 785:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 786:Drivers/BME680/bme680.c **** if (BME680_SPI_INTF == dev->intf) { + 787:Drivers/BME680/bme680.c **** /* Memory page switch the SPI address*/ + 788:Drivers/BME680/bme680.c **** rslt = set_mem_page(reg_addr1, dev); + 789:Drivers/BME680/bme680.c **** } + 790:Drivers/BME680/bme680.c **** + 791:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 792:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr1, data_array, BME680_GAS_HEATER_PROF_LEN_MAX, dev); + 793:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 794:Drivers/BME680/bme680.c **** for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + 795:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_temp = data_array[index]; + 796:Drivers/BME680/bme680.c **** } + 797:Drivers/BME680/bme680.c **** + 798:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr2, data_array, BME680_GAS_HEATER_PROF_LEN_MAX, dev); + 799:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 800:Drivers/BME680/bme680.c **** for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + 801:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_dur = data_array[index]; + 802:Drivers/BME680/bme680.c **** } + 803:Drivers/BME680/bme680.c **** } + 804:Drivers/BME680/bme680.c **** } + 805:Drivers/BME680/bme680.c **** + 806:Drivers/BME680/bme680.c **** return rslt; + 807:Drivers/BME680/bme680.c **** } + 808:Drivers/BME680/bme680.c **** + 809:Drivers/BME680/bme680.c **** /*! + 810:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the temperature value. + 811:Drivers/BME680/bme680.c **** */ + 812:Drivers/BME680/bme680.c **** static int16_t calc_temperature(uint32_t temp_adc, struct bme680_dev *dev) + 813:Drivers/BME680/bme680.c **** { + 814:Drivers/BME680/bme680.c **** int64_t var1; + 815:Drivers/BME680/bme680.c **** int64_t var2; + 816:Drivers/BME680/bme680.c **** int64_t var3; + 817:Drivers/BME680/bme680.c **** int16_t calc_temp; + 818:Drivers/BME680/bme680.c **** + 819:Drivers/BME680/bme680.c **** var1 = ((int32_t) temp_adc >> 3) - ((int32_t) dev->calib.par_t1 << 1); + 820:Drivers/BME680/bme680.c **** var2 = (var1 * (int32_t) dev->calib.par_t2) >> 11; + 821:Drivers/BME680/bme680.c **** var3 = ((var1 >> 1) * (var1 >> 1)) >> 12; + 822:Drivers/BME680/bme680.c **** var3 = ((var3) * ((int32_t) dev->calib.par_t3 << 4)) >> 14; + 823:Drivers/BME680/bme680.c **** dev->calib.t_fine = (int32_t) (var2 + var3); + 824:Drivers/BME680/bme680.c **** calc_temp = (int16_t) (((dev->calib.t_fine * 5) + 128) >> 8); + 825:Drivers/BME680/bme680.c **** + 826:Drivers/BME680/bme680.c **** return calc_temp; + 827:Drivers/BME680/bme680.c **** } + 828:Drivers/BME680/bme680.c **** + 829:Drivers/BME680/bme680.c **** /*! + 830:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the pressure value. + 831:Drivers/BME680/bme680.c **** */ + 832:Drivers/BME680/bme680.c **** static uint32_t calc_pressure(uint32_t pres_adc, const struct bme680_dev *dev) + ARM GAS /tmp/ccvbgJts.s page 16 + + + 833:Drivers/BME680/bme680.c **** { + 834:Drivers/BME680/bme680.c **** int32_t var1 = 0; + 835:Drivers/BME680/bme680.c **** int32_t var2 = 0; + 836:Drivers/BME680/bme680.c **** int32_t var3 = 0; + 837:Drivers/BME680/bme680.c **** int32_t var4 = 0; + 838:Drivers/BME680/bme680.c **** int32_t pressure_comp = 0; + 839:Drivers/BME680/bme680.c **** + 840:Drivers/BME680/bme680.c **** var1 = (((int32_t)dev->calib.t_fine) >> 1) - 64000; + 841:Drivers/BME680/bme680.c **** var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) * + 842:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p6) >> 2; + 843:Drivers/BME680/bme680.c **** var2 = var2 + ((var1 * (int32_t)dev->calib.par_p5) << 1); + 844:Drivers/BME680/bme680.c **** var2 = (var2 >> 2) + ((int32_t)dev->calib.par_p4 << 16); + 845:Drivers/BME680/bme680.c **** var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) * + 846:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p3 << 5)) >> 3) + + 847:Drivers/BME680/bme680.c **** (((int32_t)dev->calib.par_p2 * var1) >> 1); + 848:Drivers/BME680/bme680.c **** var1 = var1 >> 18; + 849:Drivers/BME680/bme680.c **** var1 = ((32768 + var1) * (int32_t)dev->calib.par_p1) >> 15; + 850:Drivers/BME680/bme680.c **** pressure_comp = 1048576 - pres_adc; + 851:Drivers/BME680/bme680.c **** pressure_comp = (int32_t)((pressure_comp - (var2 >> 12)) * ((uint32_t)3125)); + 852:Drivers/BME680/bme680.c **** var4 = (1 << 31); + 853:Drivers/BME680/bme680.c **** if (pressure_comp >= var4) + 854:Drivers/BME680/bme680.c **** pressure_comp = ((pressure_comp / (uint32_t)var1) << 1); + 855:Drivers/BME680/bme680.c **** else + 856:Drivers/BME680/bme680.c **** pressure_comp = ((pressure_comp << 1) / (uint32_t)var1); + 857:Drivers/BME680/bme680.c **** var1 = ((int32_t)dev->calib.par_p9 * (int32_t)(((pressure_comp >> 3) * + 858:Drivers/BME680/bme680.c **** (pressure_comp >> 3)) >> 13)) >> 12; + 859:Drivers/BME680/bme680.c **** var2 = ((int32_t)(pressure_comp >> 2) * + 860:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p8) >> 13; + 861:Drivers/BME680/bme680.c **** var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) * + 862:Drivers/BME680/bme680.c **** (int32_t)(pressure_comp >> 8) * + 863:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p10) >> 17; + 864:Drivers/BME680/bme680.c **** + 865:Drivers/BME680/bme680.c **** pressure_comp = (int32_t)(pressure_comp) + ((var1 + var2 + var3 + + 866:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p7 << 7)) >> 4); + 867:Drivers/BME680/bme680.c **** + 868:Drivers/BME680/bme680.c **** return (uint32_t)pressure_comp; + 869:Drivers/BME680/bme680.c **** + 870:Drivers/BME680/bme680.c **** } + 871:Drivers/BME680/bme680.c **** + 872:Drivers/BME680/bme680.c **** /*! + 873:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the humidity value. + 874:Drivers/BME680/bme680.c **** */ + 875:Drivers/BME680/bme680.c **** static uint32_t calc_humidity(uint16_t hum_adc, const struct bme680_dev *dev) + 876:Drivers/BME680/bme680.c **** { + 877:Drivers/BME680/bme680.c **** int32_t var1; + 878:Drivers/BME680/bme680.c **** int32_t var2; + 879:Drivers/BME680/bme680.c **** int32_t var3; + 880:Drivers/BME680/bme680.c **** int32_t var4; + 881:Drivers/BME680/bme680.c **** int32_t var5; + 882:Drivers/BME680/bme680.c **** int32_t var6; + 883:Drivers/BME680/bme680.c **** int32_t temp_scaled; + 884:Drivers/BME680/bme680.c **** int32_t calc_hum; + 885:Drivers/BME680/bme680.c **** + 886:Drivers/BME680/bme680.c **** temp_scaled = (((int32_t) dev->calib.t_fine * 5) + 128) >> 8; + 887:Drivers/BME680/bme680.c **** var1 = (int32_t) (hum_adc - ((int32_t) ((int32_t) dev->calib.par_h1 * 16))) + 888:Drivers/BME680/bme680.c **** - (((temp_scaled * (int32_t) dev->calib.par_h3) / ((int32_t) 100)) >> 1); + 889:Drivers/BME680/bme680.c **** var2 = ((int32_t) dev->calib.par_h2 + ARM GAS /tmp/ccvbgJts.s page 17 + + + 890:Drivers/BME680/bme680.c **** * (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100)) + 891:Drivers/BME680/bme680.c **** + (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6) + 892:Drivers/BME680/bme680.c **** / ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10; + 893:Drivers/BME680/bme680.c **** var3 = var1 * var2; + 894:Drivers/BME680/bme680.c **** var4 = (int32_t) dev->calib.par_h6 << 7; + 895:Drivers/BME680/bme680.c **** var4 = ((var4) + ((temp_scaled * (int32_t) dev->calib.par_h7) / ((int32_t) 100))) >> 4; + 896:Drivers/BME680/bme680.c **** var5 = ((var3 >> 14) * (var3 >> 14)) >> 10; + 897:Drivers/BME680/bme680.c **** var6 = (var4 * var5) >> 1; + 898:Drivers/BME680/bme680.c **** calc_hum = (((var3 + var6) >> 10) * ((int32_t) 1000)) >> 12; + 899:Drivers/BME680/bme680.c **** + 900:Drivers/BME680/bme680.c **** if (calc_hum > 100000) /* Cap at 100%rH */ + 901:Drivers/BME680/bme680.c **** calc_hum = 100000; + 902:Drivers/BME680/bme680.c **** else if (calc_hum < 0) + 903:Drivers/BME680/bme680.c **** calc_hum = 0; + 904:Drivers/BME680/bme680.c **** + 905:Drivers/BME680/bme680.c **** return (uint32_t) calc_hum; + 906:Drivers/BME680/bme680.c **** } + 907:Drivers/BME680/bme680.c **** + 908:Drivers/BME680/bme680.c **** /*! + 909:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Gas Resistance value. + 910:Drivers/BME680/bme680.c **** */ + 911:Drivers/BME680/bme680.c **** static uint32_t calc_gas_resistance(uint16_t gas_res_adc, uint8_t gas_range, const struct bme680_de + 912:Drivers/BME680/bme680.c **** { + 913:Drivers/BME680/bme680.c **** int64_t var1; + 914:Drivers/BME680/bme680.c **** uint64_t var2; + 915:Drivers/BME680/bme680.c **** int64_t var3; + 916:Drivers/BME680/bme680.c **** uint32_t calc_gas_res; + 917:Drivers/BME680/bme680.c **** + 918:Drivers/BME680/bme680.c **** var1 = (int64_t) ((1340 + (5 * (int64_t) dev->calib.range_sw_err)) * + 919:Drivers/BME680/bme680.c **** ((int64_t) lookupTable1[gas_range])) >> 16; + 920:Drivers/BME680/bme680.c **** var2 = (((int64_t) ((int64_t) gas_res_adc << 15) - (int64_t) (16777216)) + var1); + 921:Drivers/BME680/bme680.c **** var3 = (((int64_t) lookupTable2[gas_range] * (int64_t) var1) >> 9); + 922:Drivers/BME680/bme680.c **** calc_gas_res = (uint32_t) ((var3 + ((int64_t) var2 >> 1)) / (int64_t) var2); + 923:Drivers/BME680/bme680.c **** + 924:Drivers/BME680/bme680.c **** return calc_gas_res; + 925:Drivers/BME680/bme680.c **** } + 926:Drivers/BME680/bme680.c **** + 927:Drivers/BME680/bme680.c **** /*! + 928:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Heat Resistance value. + 929:Drivers/BME680/bme680.c **** */ + 930:Drivers/BME680/bme680.c **** static uint8_t calc_heater_res(uint16_t temp, const struct bme680_dev *dev) + 931:Drivers/BME680/bme680.c **** { + 932:Drivers/BME680/bme680.c **** uint8_t heatr_res; + 933:Drivers/BME680/bme680.c **** int32_t var1; + 934:Drivers/BME680/bme680.c **** int32_t var2; + 935:Drivers/BME680/bme680.c **** int32_t var3; + 936:Drivers/BME680/bme680.c **** int32_t var4; + 937:Drivers/BME680/bme680.c **** int32_t var5; + 938:Drivers/BME680/bme680.c **** int32_t heatr_res_x100; + 939:Drivers/BME680/bme680.c **** + 940:Drivers/BME680/bme680.c **** if (temp < 200) /* Cap temperature */ + 941:Drivers/BME680/bme680.c **** temp = 200; + 942:Drivers/BME680/bme680.c **** else if (temp > 400) + 943:Drivers/BME680/bme680.c **** temp = 400; + 944:Drivers/BME680/bme680.c **** + 945:Drivers/BME680/bme680.c **** var1 = (((int32_t) dev->amb_temp * dev->calib.par_gh3) / 1000) * 256; + 946:Drivers/BME680/bme680.c **** var2 = (dev->calib.par_gh1 + 784) * (((((dev->calib.par_gh2 + 154009) * temp * 5) / 100) + 3276800 + ARM GAS /tmp/ccvbgJts.s page 18 + + + 947:Drivers/BME680/bme680.c **** var3 = var1 + (var2 / 2); + 948:Drivers/BME680/bme680.c **** var4 = (var3 / (dev->calib.res_heat_range + 4)); + 949:Drivers/BME680/bme680.c **** var5 = (131 * dev->calib.res_heat_val) + 65536; + 950:Drivers/BME680/bme680.c **** heatr_res_x100 = (int32_t) (((var4 / var5) - 250) * 34); + 951:Drivers/BME680/bme680.c **** heatr_res = (uint8_t) ((heatr_res_x100 + 50) / 100); + 952:Drivers/BME680/bme680.c **** + 953:Drivers/BME680/bme680.c **** return heatr_res; + 954:Drivers/BME680/bme680.c **** } + 955:Drivers/BME680/bme680.c **** + 956:Drivers/BME680/bme680.c **** /*! + 957:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the Heat duration value. + 958:Drivers/BME680/bme680.c **** */ + 959:Drivers/BME680/bme680.c **** static uint8_t calc_heater_dur(uint16_t dur) + 960:Drivers/BME680/bme680.c **** { + 961:Drivers/BME680/bme680.c **** uint8_t factor = 0; + 962:Drivers/BME680/bme680.c **** uint8_t durval; + 963:Drivers/BME680/bme680.c **** + 964:Drivers/BME680/bme680.c **** if (dur >= 0xfc0) { + 965:Drivers/BME680/bme680.c **** durval = 0xff; /* Max duration*/ + 966:Drivers/BME680/bme680.c **** } else { + 967:Drivers/BME680/bme680.c **** while (dur > 0x3F) { + 968:Drivers/BME680/bme680.c **** dur = dur / 4; + 969:Drivers/BME680/bme680.c **** factor += 1; + 970:Drivers/BME680/bme680.c **** } + 971:Drivers/BME680/bme680.c **** durval = (uint8_t) (dur + (factor * 64)); + 972:Drivers/BME680/bme680.c **** } + 973:Drivers/BME680/bme680.c **** + 974:Drivers/BME680/bme680.c **** return durval; + 975:Drivers/BME680/bme680.c **** } + 976:Drivers/BME680/bme680.c **** + 977:Drivers/BME680/bme680.c **** /*! + 978:Drivers/BME680/bme680.c **** * @brief This internal API is used to calculate the field data of sensor. + 979:Drivers/BME680/bme680.c **** */ + 980:Drivers/BME680/bme680.c **** static int8_t read_field_data(struct bme680_field_data *data, struct bme680_dev *dev) + 981:Drivers/BME680/bme680.c **** { + 982:Drivers/BME680/bme680.c **** int8_t rslt; + 983:Drivers/BME680/bme680.c **** uint8_t buff[BME680_FIELD_LENGTH] = { 0 }; + 984:Drivers/BME680/bme680.c **** uint8_t gas_range; + 985:Drivers/BME680/bme680.c **** uint32_t adc_temp; + 986:Drivers/BME680/bme680.c **** uint32_t adc_pres; + 987:Drivers/BME680/bme680.c **** uint16_t adc_hum; + 988:Drivers/BME680/bme680.c **** uint16_t adc_gas_res; + 989:Drivers/BME680/bme680.c **** uint8_t tries = 10; + 990:Drivers/BME680/bme680.c **** + 991:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ + 992:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); + 993:Drivers/BME680/bme680.c **** do { + 994:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 995:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(((uint8_t) (BME680_FIELD0_ADDR)), buff, (uint16_t) BME680_FIELD_LENGTH, + 996:Drivers/BME680/bme680.c **** dev); + 997:Drivers/BME680/bme680.c **** + 998:Drivers/BME680/bme680.c **** data->status = buff[0] & BME680_NEW_DATA_MSK; + 999:Drivers/BME680/bme680.c **** data->gas_index = buff[0] & BME680_GAS_INDEX_MSK; +1000:Drivers/BME680/bme680.c **** data->meas_index = buff[1]; +1001:Drivers/BME680/bme680.c **** +1002:Drivers/BME680/bme680.c **** /* read the raw data from the sensor */ +1003:Drivers/BME680/bme680.c **** adc_pres = (uint32_t) (((uint32_t) buff[2] * 4096) | ((uint32_t) buff[3] * 16) + ARM GAS /tmp/ccvbgJts.s page 19 + + +1004:Drivers/BME680/bme680.c **** | ((uint32_t) buff[4] / 16)); +1005:Drivers/BME680/bme680.c **** adc_temp = (uint32_t) (((uint32_t) buff[5] * 4096) | ((uint32_t) buff[6] * 16) +1006:Drivers/BME680/bme680.c **** | ((uint32_t) buff[7] / 16)); +1007:Drivers/BME680/bme680.c **** adc_hum = (uint16_t) (((uint32_t) buff[8] * 256) | (uint32_t) buff[9]); +1008:Drivers/BME680/bme680.c **** adc_gas_res = (uint16_t) ((uint32_t) buff[13] * 4 | (((uint32_t) buff[14]) / 64)); +1009:Drivers/BME680/bme680.c **** gas_range = buff[14] & BME680_GAS_RANGE_MSK; +1010:Drivers/BME680/bme680.c **** +1011:Drivers/BME680/bme680.c **** data->status |= buff[14] & BME680_GASM_VALID_MSK; +1012:Drivers/BME680/bme680.c **** data->status |= buff[14] & BME680_HEAT_STAB_MSK; +1013:Drivers/BME680/bme680.c **** +1014:Drivers/BME680/bme680.c **** if (data->status & BME680_NEW_DATA_MSK) { +1015:Drivers/BME680/bme680.c **** data->temperature = calc_temperature(adc_temp, dev); +1016:Drivers/BME680/bme680.c **** data->pressure = calc_pressure(adc_pres, dev); +1017:Drivers/BME680/bme680.c **** data->humidity = calc_humidity(adc_hum, dev); +1018:Drivers/BME680/bme680.c **** data->gas_resistance = calc_gas_resistance(adc_gas_res, gas_range, dev); +1019:Drivers/BME680/bme680.c **** break; +1020:Drivers/BME680/bme680.c **** } +1021:Drivers/BME680/bme680.c **** /* Delay to poll the data */ +1022:Drivers/BME680/bme680.c **** dev->delay_ms(BME680_POLL_PERIOD_MS); +1023:Drivers/BME680/bme680.c **** } +1024:Drivers/BME680/bme680.c **** tries--; +1025:Drivers/BME680/bme680.c **** } while (tries); +1026:Drivers/BME680/bme680.c **** +1027:Drivers/BME680/bme680.c **** if (!tries) +1028:Drivers/BME680/bme680.c **** rslt = BME680_W_NO_NEW_DATA; +1029:Drivers/BME680/bme680.c **** +1030:Drivers/BME680/bme680.c **** return rslt; +1031:Drivers/BME680/bme680.c **** } +1032:Drivers/BME680/bme680.c **** +1033:Drivers/BME680/bme680.c **** /*! +1034:Drivers/BME680/bme680.c **** * @brief This internal API is used to set the memory page based on register address. +1035:Drivers/BME680/bme680.c **** */ +1036:Drivers/BME680/bme680.c **** static int8_t set_mem_page(uint8_t reg_addr, struct bme680_dev *dev) +1037:Drivers/BME680/bme680.c **** { + 25 .loc 1 1037 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 8 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 30B5 push {r4, r5, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 12 + 33 .cfi_offset 4, -12 + 34 .cfi_offset 5, -8 + 35 .cfi_offset 14, -4 + 36 0002 83B0 sub sp, sp, #12 + 37 .LCFI1: + 38 .cfi_def_cfa_offset 24 + 39 0004 0C1E subs r4, r1, #0 + 40 .LVL1: + 41 .LBB51: + 42 .LBB52: +1038:Drivers/BME680/bme680.c **** int8_t rslt; +1039:Drivers/BME680/bme680.c **** uint8_t reg; +1040:Drivers/BME680/bme680.c **** uint8_t mem_page; +1041:Drivers/BME680/bme680.c **** +1042:Drivers/BME680/bme680.c **** /* Check for null pointers in the device structure*/ + ARM GAS /tmp/ccvbgJts.s page 20 + + +1043:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); +1044:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { +1045:Drivers/BME680/bme680.c **** if (reg_addr > 0x7f) +1046:Drivers/BME680/bme680.c **** mem_page = BME680_MEM_PAGE1; +1047:Drivers/BME680/bme680.c **** else +1048:Drivers/BME680/bme680.c **** mem_page = BME680_MEM_PAGE0; +1049:Drivers/BME680/bme680.c **** +1050:Drivers/BME680/bme680.c **** if (mem_page != dev->mem_page) { +1051:Drivers/BME680/bme680.c **** dev->mem_page = mem_page; +1052:Drivers/BME680/bme680.c **** +1053:Drivers/BME680/bme680.c **** dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1); +1054:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) +1055:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; +1056:Drivers/BME680/bme680.c **** +1057:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { +1058:Drivers/BME680/bme680.c **** reg = reg & (~BME680_MEM_PAGE_MSK); +1059:Drivers/BME680/bme680.c **** reg = reg | (dev->mem_page & BME680_MEM_PAGE_MSK); +1060:Drivers/BME680/bme680.c **** +1061:Drivers/BME680/bme680.c **** dev->com_rslt = dev->write(dev->dev_id, BME680_MEM_PAGE_ADDR & BME680_SPI_WR_MSK, +1062:Drivers/BME680/bme680.c **** ®, 1); +1063:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) +1064:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; +1065:Drivers/BME680/bme680.c **** } +1066:Drivers/BME680/bme680.c **** } +1067:Drivers/BME680/bme680.c **** } +1068:Drivers/BME680/bme680.c **** +1069:Drivers/BME680/bme680.c **** return rslt; +1070:Drivers/BME680/bme680.c **** } +1071:Drivers/BME680/bme680.c **** +1072:Drivers/BME680/bme680.c **** /*! +1073:Drivers/BME680/bme680.c **** * @brief This internal API is used to get the memory page based on register address. +1074:Drivers/BME680/bme680.c **** */ +1075:Drivers/BME680/bme680.c **** static int8_t get_mem_page(struct bme680_dev *dev) +1076:Drivers/BME680/bme680.c **** { +1077:Drivers/BME680/bme680.c **** int8_t rslt; +1078:Drivers/BME680/bme680.c **** uint8_t reg; +1079:Drivers/BME680/bme680.c **** +1080:Drivers/BME680/bme680.c **** /* Check for null pointer in the device structure*/ +1081:Drivers/BME680/bme680.c **** rslt = null_ptr_check(dev); +1082:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { +1083:Drivers/BME680/bme680.c **** dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1); +1084:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) +1085:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; +1086:Drivers/BME680/bme680.c **** else +1087:Drivers/BME680/bme680.c **** dev->mem_page = reg & BME680_MEM_PAGE_MSK; +1088:Drivers/BME680/bme680.c **** } +1089:Drivers/BME680/bme680.c **** +1090:Drivers/BME680/bme680.c **** return rslt; +1091:Drivers/BME680/bme680.c **** } +1092:Drivers/BME680/bme680.c **** +1093:Drivers/BME680/bme680.c **** /*! +1094:Drivers/BME680/bme680.c **** * @brief This internal API is used to validate the boundary +1095:Drivers/BME680/bme680.c **** * conditions. +1096:Drivers/BME680/bme680.c **** */ +1097:Drivers/BME680/bme680.c **** static int8_t boundary_check(uint8_t *value, uint8_t min, uint8_t max, struct bme680_dev *dev) +1098:Drivers/BME680/bme680.c **** { +1099:Drivers/BME680/bme680.c **** int8_t rslt = BME680_OK; + ARM GAS /tmp/ccvbgJts.s page 21 + + +1100:Drivers/BME680/bme680.c **** +1101:Drivers/BME680/bme680.c **** if (value != NULL) { +1102:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ +1103:Drivers/BME680/bme680.c **** if (*value < min) { +1104:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ +1105:Drivers/BME680/bme680.c **** *value = min; +1106:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MIN_CORRECTION; +1107:Drivers/BME680/bme680.c **** } +1108:Drivers/BME680/bme680.c **** /* Check if value is above maximum value */ +1109:Drivers/BME680/bme680.c **** if (*value > max) { +1110:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ +1111:Drivers/BME680/bme680.c **** *value = max; +1112:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; +1113:Drivers/BME680/bme680.c **** } +1114:Drivers/BME680/bme680.c **** } else { +1115:Drivers/BME680/bme680.c **** rslt = BME680_E_NULL_PTR; +1116:Drivers/BME680/bme680.c **** } +1117:Drivers/BME680/bme680.c **** +1118:Drivers/BME680/bme680.c **** return rslt; +1119:Drivers/BME680/bme680.c **** } +1120:Drivers/BME680/bme680.c **** +1121:Drivers/BME680/bme680.c **** /*! +1122:Drivers/BME680/bme680.c **** * @brief This internal API is used to validate the device structure pointer for +1123:Drivers/BME680/bme680.c **** * null conditions. +1124:Drivers/BME680/bme680.c **** */ +1125:Drivers/BME680/bme680.c **** static int8_t null_ptr_check(const struct bme680_dev *dev) +1126:Drivers/BME680/bme680.c **** { +1127:Drivers/BME680/bme680.c **** int8_t rslt; +1128:Drivers/BME680/bme680.c **** +1129:Drivers/BME680/bme680.c **** if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_ms == NULL)) { + 43 .loc 1 1129 0 + 44 0006 33D0 beq .L4 + 45 0008 8D6C ldr r5, [r1, #72] + 46 000a 002D cmp r5, #0 + 47 000c 33D0 beq .L5 + 48 000e CB6C ldr r3, [r1, #76] + 49 0010 002B cmp r3, #0 + 50 0012 33D0 beq .L6 + 51 0014 0B6D ldr r3, [r1, #80] + 52 0016 002B cmp r3, #0 + 53 0018 33D0 beq .L7 + 54 .LVL2: + 55 .LBE52: + 56 .LBE51: +1045:Drivers/BME680/bme680.c **** mem_page = BME680_MEM_PAGE1; + 57 .loc 1 1045 0 + 58 001a 40B2 sxtb r0, r0 + 59 001c 0028 cmp r0, #0 + 60 001e 25DB blt .L12 +1048:Drivers/BME680/bme680.c **** + 61 .loc 1 1048 0 + 62 0020 1023 movs r3, #16 + 63 .L3: + 64 .LVL3: +1050:Drivers/BME680/bme680.c **** dev->mem_page = mem_page; + 65 .loc 1 1050 0 + 66 0022 E278 ldrb r2, [r4, #3] + ARM GAS /tmp/ccvbgJts.s page 22 + + + 67 0024 9A42 cmp r2, r3 + 68 0026 2FD0 beq .L9 +1051:Drivers/BME680/bme680.c **** + 69 .loc 1 1051 0 + 70 0028 E370 strb r3, [r4, #3] +1053:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 71 .loc 1 1053 0 + 72 002a 6078 ldrb r0, [r4, #1] + 73 .LVL4: + 74 002c 0123 movs r3, #1 + 75 .LVL5: + 76 002e 6A46 mov r2, sp + 77 0030 0732 adds r2, r2, #7 + 78 0032 F321 movs r1, #243 + 79 .LVL6: + 80 0034 A847 blx r5 + 81 .LVL7: + 82 0036 5423 movs r3, #84 + 83 0038 E054 strb r0, [r4, r3] +1054:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 84 .loc 1 1054 0 + 85 003a 0028 cmp r0, #0 + 86 003c 26D1 bne .L10 + 87 .LVL8: +1058:Drivers/BME680/bme680.c **** reg = reg | (dev->mem_page & BME680_MEM_PAGE_MSK); + 88 .loc 1 1058 0 + 89 003e 6B46 mov r3, sp + 90 0040 DA1D adds r2, r3, #7 + 91 0042 1378 ldrb r3, [r2] + 92 0044 1021 movs r1, #16 + 93 0046 8B43 bics r3, r1 + 94 0048 1900 movs r1, r3 +1059:Drivers/BME680/bme680.c **** + 95 .loc 1 1059 0 + 96 004a 0320 movs r0, #3 + 97 004c 2056 ldrsb r0, [r4, r0] + 98 004e 1023 movs r3, #16 + 99 0050 0340 ands r3, r0 + 100 0052 0B43 orrs r3, r1 + 101 0054 1370 strb r3, [r2] +1061:Drivers/BME680/bme680.c **** ®, 1); + 102 .loc 1 1061 0 + 103 0056 6078 ldrb r0, [r4, #1] + 104 0058 0123 movs r3, #1 + 105 005a 7321 movs r1, #115 + 106 005c E56C ldr r5, [r4, #76] + 107 005e A847 blx r5 + 108 .LVL9: + 109 0060 5422 movs r2, #84 + 110 0062 A054 strb r0, [r4, r2] +1063:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 111 .loc 1 1063 0 + 112 0064 0028 cmp r0, #0 + 113 0066 14D1 bne .L13 + 114 .LVL10: + 115 .L2: +1070:Drivers/BME680/bme680.c **** + ARM GAS /tmp/ccvbgJts.s page 23 + + + 116 .loc 1 1070 0 + 117 0068 03B0 add sp, sp, #12 + 118 @ sp needed + 119 .LVL11: + 120 006a 30BD pop {r4, r5, pc} + 121 .LVL12: + 122 .L12: +1046:Drivers/BME680/bme680.c **** else + 123 .loc 1 1046 0 + 124 006c 0023 movs r3, #0 + 125 006e D8E7 b .L3 + 126 .LVL13: + 127 .L4: + 128 .LBB54: + 129 .LBB53: +1130:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ +1131:Drivers/BME680/bme680.c **** rslt = BME680_E_NULL_PTR; + 130 .loc 1 1131 0 + 131 0070 0120 movs r0, #1 + 132 .LVL14: + 133 0072 4042 rsbs r0, r0, #0 + 134 0074 F8E7 b .L2 + 135 .LVL15: + 136 .L5: + 137 0076 0120 movs r0, #1 + 138 .LVL16: + 139 0078 4042 rsbs r0, r0, #0 + 140 007a F5E7 b .L2 + 141 .LVL17: + 142 .L6: + 143 007c 0120 movs r0, #1 + 144 .LVL18: + 145 007e 4042 rsbs r0, r0, #0 + 146 0080 F2E7 b .L2 + 147 .LVL19: + 148 .L7: + 149 0082 0120 movs r0, #1 + 150 .LVL20: + 151 0084 4042 rsbs r0, r0, #0 + 152 0086 EFE7 b .L2 + 153 .LVL21: + 154 .L9: +1132:Drivers/BME680/bme680.c **** } else { +1133:Drivers/BME680/bme680.c **** /* Device structure is fine */ +1134:Drivers/BME680/bme680.c **** rslt = BME680_OK; + 155 .loc 1 1134 0 + 156 0088 0020 movs r0, #0 + 157 008a EDE7 b .L2 + 158 .LVL22: + 159 .L10: + 160 .LBE53: + 161 .LBE54: +1055:Drivers/BME680/bme680.c **** + 162 .loc 1 1055 0 + 163 008c 0220 movs r0, #2 + 164 008e 4042 rsbs r0, r0, #0 + 165 0090 EAE7 b .L2 + ARM GAS /tmp/ccvbgJts.s page 24 + + + 166 .LVL23: + 167 .L13: +1064:Drivers/BME680/bme680.c **** } + 168 .loc 1 1064 0 + 169 0092 0220 movs r0, #2 + 170 0094 4042 rsbs r0, r0, #0 + 171 0096 E7E7 b .L2 + 172 .cfi_endproc + 173 .LFE21: + 175 .section .text.get_mem_page,"ax",%progbits + 176 .align 1 + 177 .syntax unified + 178 .code 16 + 179 .thumb_func + 180 .fpu softvfp + 182 get_mem_page: + 183 .LFB22: +1076:Drivers/BME680/bme680.c **** int8_t rslt; + 184 .loc 1 1076 0 + 185 .cfi_startproc + 186 @ args = 0, pretend = 0, frame = 8 + 187 @ frame_needed = 0, uses_anonymous_args = 0 + 188 .LVL24: + 189 0000 30B5 push {r4, r5, lr} + 190 .LCFI2: + 191 .cfi_def_cfa_offset 12 + 192 .cfi_offset 4, -12 + 193 .cfi_offset 5, -8 + 194 .cfi_offset 14, -4 + 195 0002 83B0 sub sp, sp, #12 + 196 .LCFI3: + 197 .cfi_def_cfa_offset 24 + 198 0004 041E subs r4, r0, #0 + 199 .LVL25: + 200 .LBB55: + 201 .LBB56: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 202 .loc 1 1129 0 + 203 0006 19D0 beq .L16 + 204 0008 856C ldr r5, [r0, #72] + 205 000a 002D cmp r5, #0 + 206 000c 19D0 beq .L17 + 207 000e C36C ldr r3, [r0, #76] + 208 0010 002B cmp r3, #0 + 209 0012 19D0 beq .L18 + 210 0014 036D ldr r3, [r0, #80] + 211 0016 002B cmp r3, #0 + 212 0018 19D0 beq .L19 + 213 .LVL26: + 214 .LBE56: + 215 .LBE55: +1083:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 216 .loc 1 1083 0 + 217 001a 4078 ldrb r0, [r0, #1] + 218 .LVL27: + 219 001c 0123 movs r3, #1 + 220 001e 6A46 mov r2, sp + ARM GAS /tmp/ccvbgJts.s page 25 + + + 221 0020 0732 adds r2, r2, #7 + 222 0022 F321 movs r1, #243 + 223 0024 A847 blx r5 + 224 .LVL28: + 225 0026 5422 movs r2, #84 + 226 0028 A054 strb r0, [r4, r2] +1084:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 227 .loc 1 1084 0 + 228 002a 0028 cmp r0, #0 + 229 002c 12D1 bne .L20 +1087:Drivers/BME680/bme680.c **** } + 230 .loc 1 1087 0 + 231 002e 6B46 mov r3, sp + 232 0030 DA79 ldrb r2, [r3, #7] + 233 0032 1023 movs r3, #16 + 234 0034 1340 ands r3, r2 + 235 0036 E370 strb r3, [r4, #3] + 236 .L15: + 237 .LVL29: +1091:Drivers/BME680/bme680.c **** + 238 .loc 1 1091 0 + 239 0038 03B0 add sp, sp, #12 + 240 @ sp needed + 241 .LVL30: + 242 003a 30BD pop {r4, r5, pc} + 243 .LVL31: + 244 .L16: + 245 .LBB58: + 246 .LBB57: +1131:Drivers/BME680/bme680.c **** } else { + 247 .loc 1 1131 0 + 248 003c 0120 movs r0, #1 + 249 .LVL32: + 250 003e 4042 rsbs r0, r0, #0 + 251 0040 FAE7 b .L15 + 252 .LVL33: + 253 .L17: + 254 0042 0120 movs r0, #1 + 255 .LVL34: + 256 0044 4042 rsbs r0, r0, #0 + 257 0046 F7E7 b .L15 + 258 .LVL35: + 259 .L18: + 260 0048 0120 movs r0, #1 + 261 .LVL36: + 262 004a 4042 rsbs r0, r0, #0 + 263 004c F4E7 b .L15 + 264 .LVL37: + 265 .L19: + 266 004e 0120 movs r0, #1 + 267 .LVL38: + 268 0050 4042 rsbs r0, r0, #0 + 269 0052 F1E7 b .L15 + 270 .LVL39: + 271 .L20: + 272 .LBE57: + 273 .LBE58: + ARM GAS /tmp/ccvbgJts.s page 26 + + +1085:Drivers/BME680/bme680.c **** else + 274 .loc 1 1085 0 + 275 0054 0220 movs r0, #2 + 276 0056 4042 rsbs r0, r0, #0 + 277 0058 EEE7 b .L15 + 278 .cfi_endproc + 279 .LFE22: + 281 .section .text.bme680_get_regs,"ax",%progbits + 282 .align 1 + 283 .global bme680_get_regs + 284 .syntax unified + 285 .code 16 + 286 .thumb_func + 287 .fpu softvfp + 289 bme680_get_regs: + 290 .LFB1: + 265:Drivers/BME680/bme680.c **** int8_t rslt; + 291 .loc 1 265 0 + 292 .cfi_startproc + 293 @ args = 0, pretend = 0, frame = 8 + 294 @ frame_needed = 0, uses_anonymous_args = 0 + 295 .LVL40: + 296 0000 F0B5 push {r4, r5, r6, r7, lr} + 297 .LCFI4: + 298 .cfi_def_cfa_offset 20 + 299 .cfi_offset 4, -20 + 300 .cfi_offset 5, -16 + 301 .cfi_offset 6, -12 + 302 .cfi_offset 7, -8 + 303 .cfi_offset 14, -4 + 304 0002 83B0 sub sp, sp, #12 + 305 .LCFI5: + 306 .cfi_def_cfa_offset 32 + 307 0004 0500 movs r5, r0 + 308 0006 0191 str r1, [sp, #4] + 309 0008 1700 movs r7, r2 + 310 000a 1E1E subs r6, r3, #0 + 311 .LVL41: + 312 .LBB59: + 313 .LBB60: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 314 .loc 1 1129 0 + 315 000c 23D0 beq .L24 + 316 000e 9B6C ldr r3, [r3, #72] + 317 .LVL42: + 318 0010 002B cmp r3, #0 + 319 0012 23D0 beq .L25 + 320 0014 F36C ldr r3, [r6, #76] + 321 0016 002B cmp r3, #0 + 322 0018 23D0 beq .L26 + 323 001a 336D ldr r3, [r6, #80] + 324 001c 002B cmp r3, #0 + 325 001e 23D0 beq .L27 + 326 .LVL43: + 327 .LBE60: + 328 .LBE59: + 271:Drivers/BME680/bme680.c **** /* Set the memory page */ + ARM GAS /tmp/ccvbgJts.s page 27 + + + 329 .loc 1 271 0 + 330 0020 B378 ldrb r3, [r6, #2] + 331 0022 002B cmp r3, #0 + 332 0024 0DD0 beq .L30 + 333 .LBB63: + 334 .LBB61: + 335 .loc 1 1134 0 + 336 0026 0024 movs r4, #0 + 337 .LVL44: + 338 .L23: + 339 .LBE61: + 340 .LBE63: + 277:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 341 .loc 1 277 0 + 342 0028 7078 ldrb r0, [r6, #1] + 343 002a 3B00 movs r3, r7 + 344 002c 019A ldr r2, [sp, #4] + 345 002e 2900 movs r1, r5 + 346 0030 B56C ldr r5, [r6, #72] + 347 .LVL45: + 348 0032 A847 blx r5 + 349 .LVL46: + 350 0034 5423 movs r3, #84 + 351 0036 F054 strb r0, [r6, r3] + 278:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 352 .loc 1 278 0 + 353 0038 0028 cmp r0, #0 + 354 003a 18D1 bne .L31 + 355 .LVL47: + 356 .L22: + 283:Drivers/BME680/bme680.c **** + 357 .loc 1 283 0 + 358 003c 2000 movs r0, r4 + 359 003e 03B0 add sp, sp, #12 + 360 @ sp needed + 361 .LVL48: + 362 .LVL49: + 363 0040 F0BD pop {r4, r5, r6, r7, pc} + 364 .LVL50: + 365 .L30: + 273:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 366 .loc 1 273 0 + 367 0042 3100 movs r1, r6 + 368 .LVL51: + 369 0044 FFF7FEFF bl set_mem_page + 370 .LVL52: + 371 0048 041E subs r4, r0, #0 + 372 .LVL53: + 274:Drivers/BME680/bme680.c **** reg_addr = reg_addr | BME680_SPI_RD_MSK; + 373 .loc 1 274 0 + 374 004a EDD1 bne .L23 + 275:Drivers/BME680/bme680.c **** } + 375 .loc 1 275 0 + 376 004c 8023 movs r3, #128 + 377 004e 5B42 rsbs r3, r3, #0 + 378 0050 1D43 orrs r5, r3 + 379 0052 EDB2 uxtb r5, r5 + ARM GAS /tmp/ccvbgJts.s page 28 + + + 380 .LVL54: + 381 0054 E8E7 b .L23 + 382 .LVL55: + 383 .L24: + 384 .LBB64: + 385 .LBB62: +1131:Drivers/BME680/bme680.c **** } else { + 386 .loc 1 1131 0 + 387 0056 0124 movs r4, #1 + 388 0058 6442 rsbs r4, r4, #0 + 389 005a EFE7 b .L22 + 390 .LVL56: + 391 .L25: + 392 005c 0124 movs r4, #1 + 393 005e 6442 rsbs r4, r4, #0 + 394 0060 ECE7 b .L22 + 395 .L26: + 396 0062 0124 movs r4, #1 + 397 0064 6442 rsbs r4, r4, #0 + 398 0066 E9E7 b .L22 + 399 .L27: + 400 0068 0124 movs r4, #1 + 401 006a 6442 rsbs r4, r4, #0 + 402 006c E6E7 b .L22 + 403 .LVL57: + 404 .L31: + 405 .LBE62: + 406 .LBE64: + 279:Drivers/BME680/bme680.c **** } + 407 .loc 1 279 0 + 408 006e 0224 movs r4, #2 + 409 .LVL58: + 410 0070 6442 rsbs r4, r4, #0 + 411 0072 E3E7 b .L22 + 412 .cfi_endproc + 413 .LFE1: + 415 .section .text.bme680_set_regs,"ax",%progbits + 416 .align 1 + 417 .global bme680_set_regs + 418 .syntax unified + 419 .code 16 + 420 .thumb_func + 421 .fpu softvfp + 423 bme680_set_regs: + 424 .LFB2: + 290:Drivers/BME680/bme680.c **** int8_t rslt; + 425 .loc 1 290 0 + 426 .cfi_startproc + 427 @ args = 0, pretend = 0, frame = 48 + 428 @ frame_needed = 0, uses_anonymous_args = 0 + 429 .LVL59: + 430 0000 F0B5 push {r4, r5, r6, r7, lr} + 431 .LCFI6: + 432 .cfi_def_cfa_offset 20 + 433 .cfi_offset 4, -20 + 434 .cfi_offset 5, -16 + 435 .cfi_offset 6, -12 + ARM GAS /tmp/ccvbgJts.s page 29 + + + 436 .cfi_offset 7, -8 + 437 .cfi_offset 14, -4 + 438 0002 D646 mov lr, r10 + 439 0004 00B5 push {lr} + 440 .LCFI7: + 441 .cfi_def_cfa_offset 24 + 442 .cfi_offset 10, -24 + 443 0006 8CB0 sub sp, sp, #48 + 444 .LCFI8: + 445 .cfi_def_cfa_offset 72 + 446 0008 0500 movs r5, r0 + 447 000a 0E00 movs r6, r1 + 448 000c 1400 movs r4, r2 + 449 000e 0092 str r2, [sp] + 450 0010 1F00 movs r7, r3 + 293:Drivers/BME680/bme680.c **** uint16_t index; + 451 .loc 1 293 0 + 452 0012 2822 movs r2, #40 + 453 .LVL60: + 454 0014 0021 movs r1, #0 + 455 .LVL61: + 456 0016 02A8 add r0, sp, #8 + 457 .LVL62: + 458 0018 FFF7FEFF bl memset + 459 .LVL63: + 460 .LBB65: + 461 .LBB66: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 462 .loc 1 1129 0 + 463 001c 002F cmp r7, #0 + 464 001e 4AD0 beq .L38 + 465 0020 BB6C ldr r3, [r7, #72] + 466 0022 002B cmp r3, #0 + 467 0024 4BD0 beq .L39 + 468 0026 FB6C ldr r3, [r7, #76] + 469 0028 002B cmp r3, #0 + 470 002a 4CD0 beq .L40 + 471 002c 3B6D ldr r3, [r7, #80] + 472 002e 002B cmp r3, #0 + 473 0030 4DD0 beq .L41 + 474 .LVL64: + 475 .LBE66: + 476 .LBE65: + 299:Drivers/BME680/bme680.c **** /* Interleave the 2 arrays */ + 477 .loc 1 299 0 + 478 0032 631E subs r3, r4, #1 + 479 0034 DBB2 uxtb r3, r3 + 480 0036 122B cmp r3, #18 + 481 0038 03D8 bhi .L44 + 301:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) { + 482 .loc 1 301 0 + 483 003a 0024 movs r4, #0 + 484 .LBB69: + 485 .LBB67: + 486 .loc 1 1134 0 + 487 003c 0023 movs r3, #0 + 488 003e 0193 str r3, [sp, #4] + ARM GAS /tmp/ccvbgJts.s page 30 + + + 489 0040 18E0 b .L34 + 490 .L44: + 491 .LBE67: + 492 .LBE69: + 318:Drivers/BME680/bme680.c **** } + 493 .loc 1 318 0 + 494 0042 0423 movs r3, #4 + 495 0044 5B42 rsbs r3, r3, #0 + 496 0046 0193 str r3, [sp, #4] + 497 0048 30E0 b .L33 + 498 .LVL65: + 499 .L46: + 304:Drivers/BME680/bme680.c **** tmp_buff[(2 * index)] = reg_addr[index] & BME680_SPI_WR_MSK; + 500 .loc 1 304 0 + 501 004a 2B19 adds r3, r5, r4 + 502 004c 9A46 mov r10, r3 + 503 004e 1878 ldrb r0, [r3] + 504 0050 3900 movs r1, r7 + 505 0052 FFF7FEFF bl set_mem_page + 506 .LVL66: + 507 0056 0190 str r0, [sp, #4] + 508 .LVL67: + 305:Drivers/BME680/bme680.c **** } else { + 509 .loc 1 305 0 + 510 0058 6300 lsls r3, r4, #1 + 511 005a 5246 mov r2, r10 + 512 005c 1178 ldrb r1, [r2] + 513 005e 7F22 movs r2, #127 + 514 0060 0A40 ands r2, r1 + 515 0062 02A9 add r1, sp, #8 + 516 0064 CA54 strb r2, [r1, r3] + 517 .LVL68: + 518 .L36: + 309:Drivers/BME680/bme680.c **** } + 519 .loc 1 309 0 discriminator 2 + 520 0066 6300 lsls r3, r4, #1 + 521 0068 0133 adds r3, r3, #1 + 522 006a 325D ldrb r2, [r6, r4] + 523 006c 02A9 add r1, sp, #8 + 524 006e CA54 strb r2, [r1, r3] + 301:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) { + 525 .loc 1 301 0 discriminator 2 + 526 0070 0134 adds r4, r4, #1 + 527 .LVL69: + 528 0072 A4B2 uxth r4, r4 + 529 .LVL70: + 530 .L34: + 301:Drivers/BME680/bme680.c **** if (dev->intf == BME680_SPI_INTF) { + 531 .loc 1 301 0 is_stmt 0 discriminator 1 + 532 0074 6B46 mov r3, sp + 533 0076 1B88 ldrh r3, [r3] + 534 0078 A342 cmp r3, r4 + 535 007a 07D9 bls .L45 + 302:Drivers/BME680/bme680.c **** /* Set the memory page */ + 536 .loc 1 302 0 is_stmt 1 + 537 007c BB78 ldrb r3, [r7, #2] + 538 007e 002B cmp r3, #0 + ARM GAS /tmp/ccvbgJts.s page 31 + + + 539 0080 E3D0 beq .L46 + 307:Drivers/BME680/bme680.c **** } + 540 .loc 1 307 0 + 541 0082 6300 lsls r3, r4, #1 + 542 0084 2A5D ldrb r2, [r5, r4] + 543 0086 02A9 add r1, sp, #8 + 544 0088 CA54 strb r2, [r1, r3] + 545 008a ECE7 b .L36 + 546 .L45: + 312:Drivers/BME680/bme680.c **** dev->com_rslt = dev->write(dev->dev_id, tmp_buff[0], &tmp_buff[1], (2 * len) - 1); + 547 .loc 1 312 0 + 548 008c 019A ldr r2, [sp, #4] + 549 008e 002A cmp r2, #0 + 550 0090 0CD1 bne .L33 + 313:Drivers/BME680/bme680.c **** if (dev->com_rslt != 0) + 551 .loc 1 313 0 + 552 0092 5B00 lsls r3, r3, #1 + 553 0094 013B subs r3, r3, #1 + 554 0096 9BB2 uxth r3, r3 + 555 0098 02AA add r2, sp, #8 + 556 009a 1178 ldrb r1, [r2] + 557 009c 7878 ldrb r0, [r7, #1] + 558 009e 0132 adds r2, r2, #1 + 559 00a0 FC6C ldr r4, [r7, #76] + 560 .LVL71: + 561 00a2 A047 blx r4 + 562 .LVL72: + 563 00a4 5423 movs r3, #84 + 564 00a6 F854 strb r0, [r7, r3] + 314:Drivers/BME680/bme680.c **** rslt = BME680_E_COM_FAIL; + 565 .loc 1 314 0 + 566 00a8 0028 cmp r0, #0 + 567 00aa 14D1 bne .L47 + 568 .LVL73: + 569 .L33: + 323:Drivers/BME680/bme680.c **** + 570 .loc 1 323 0 + 571 00ac 0198 ldr r0, [sp, #4] + 572 00ae 0CB0 add sp, sp, #48 + 573 @ sp needed + 574 .LVL74: + 575 .LVL75: + 576 .LVL76: + 577 00b0 04BC pop {r2} + 578 00b2 9246 mov r10, r2 + 579 00b4 F0BD pop {r4, r5, r6, r7, pc} + 580 .LVL77: + 581 .L38: + 582 .LBB70: + 583 .LBB68: +1131:Drivers/BME680/bme680.c **** } else { + 584 .loc 1 1131 0 + 585 00b6 0123 movs r3, #1 + 586 00b8 5B42 rsbs r3, r3, #0 + 587 00ba 0193 str r3, [sp, #4] + 588 00bc F6E7 b .L33 + 589 .L39: + ARM GAS /tmp/ccvbgJts.s page 32 + + + 590 00be 0123 movs r3, #1 + 591 00c0 5B42 rsbs r3, r3, #0 + 592 00c2 0193 str r3, [sp, #4] + 593 00c4 F2E7 b .L33 + 594 .L40: + 595 00c6 0123 movs r3, #1 + 596 00c8 5B42 rsbs r3, r3, #0 + 597 00ca 0193 str r3, [sp, #4] + 598 00cc EEE7 b .L33 + 599 .L41: + 600 00ce 0123 movs r3, #1 + 601 00d0 5B42 rsbs r3, r3, #0 + 602 00d2 0193 str r3, [sp, #4] + 603 00d4 EAE7 b .L33 + 604 .LVL78: + 605 .L47: + 606 .LBE68: + 607 .LBE70: + 315:Drivers/BME680/bme680.c **** } + 608 .loc 1 315 0 + 609 00d6 0223 movs r3, #2 + 610 00d8 5B42 rsbs r3, r3, #0 + 611 00da 0193 str r3, [sp, #4] + 612 .LVL79: + 613 00dc E6E7 b .L33 + 614 .cfi_endproc + 615 .LFE2: + 617 .section .text.bme680_soft_reset,"ax",%progbits + 618 .align 1 + 619 .global bme680_soft_reset + 620 .syntax unified + 621 .code 16 + 622 .thumb_func + 623 .fpu softvfp + 625 bme680_soft_reset: + 626 .LFB3: + 329:Drivers/BME680/bme680.c **** int8_t rslt; + 627 .loc 1 329 0 + 628 .cfi_startproc + 629 @ args = 0, pretend = 0, frame = 8 + 630 @ frame_needed = 0, uses_anonymous_args = 0 + 631 .LVL80: + 632 0000 30B5 push {r4, r5, lr} + 633 .LCFI9: + 634 .cfi_def_cfa_offset 12 + 635 .cfi_offset 4, -12 + 636 .cfi_offset 5, -8 + 637 .cfi_offset 14, -4 + 638 0002 83B0 sub sp, sp, #12 + 639 .LCFI10: + 640 .cfi_def_cfa_offset 24 + 641 0004 0400 movs r4, r0 + 331:Drivers/BME680/bme680.c **** /* 0xb6 is the soft reset command */ + 642 .loc 1 331 0 + 643 0006 6B46 mov r3, sp + 644 0008 E022 movs r2, #224 + 645 000a DA71 strb r2, [r3, #7] + ARM GAS /tmp/ccvbgJts.s page 33 + + + 333:Drivers/BME680/bme680.c **** + 646 .loc 1 333 0 + 647 000c 6B46 mov r3, sp + 648 000e 2A3A subs r2, r2, #42 + 649 0010 9A71 strb r2, [r3, #6] + 650 .LVL81: + 651 .LBB71: + 652 .LBB72: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 653 .loc 1 1129 0 + 654 0012 0028 cmp r0, #0 + 655 0014 2BD0 beq .L51 + 656 0016 836C ldr r3, [r0, #72] + 657 0018 002B cmp r3, #0 + 658 001a 2BD0 beq .L52 + 659 001c C36C ldr r3, [r0, #76] + 660 001e 002B cmp r3, #0 + 661 0020 2BD0 beq .L53 + 662 0022 036D ldr r3, [r0, #80] + 663 0024 002B cmp r3, #0 + 664 0026 2BD0 beq .L54 + 665 .LVL82: + 666 .LBE72: + 667 .LBE71: + 338:Drivers/BME680/bme680.c **** rslt = get_mem_page(dev); + 668 .loc 1 338 0 + 669 0028 8378 ldrb r3, [r0, #2] + 670 002a 002B cmp r3, #0 + 671 002c 05D0 beq .L56 + 672 .LBB75: + 673 .LBB73: + 674 .loc 1 1134 0 + 675 002e 0025 movs r5, #0 + 676 .LVL83: + 677 .L50: + 678 .LBE73: + 679 .LBE75: + 342:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &soft_rst_cmd, 1, dev); + 680 .loc 1 342 0 + 681 0030 002D cmp r5, #0 + 682 0032 06D0 beq .L57 + 683 .LVL84: + 684 .L49: + 356:Drivers/BME680/bme680.c **** + 685 .loc 1 356 0 + 686 0034 2800 movs r0, r5 + 687 0036 03B0 add sp, sp, #12 + 688 @ sp needed + 689 .LVL85: + 690 .LVL86: + 691 0038 30BD pop {r4, r5, pc} + 692 .LVL87: + 693 .L56: + 339:Drivers/BME680/bme680.c **** + 694 .loc 1 339 0 + 695 003a FFF7FEFF bl get_mem_page + 696 .LVL88: + ARM GAS /tmp/ccvbgJts.s page 34 + + + 697 003e 0500 movs r5, r0 + 698 .LVL89: + 699 0040 F6E7 b .L50 + 700 .LVL90: + 701 .L57: + 343:Drivers/BME680/bme680.c **** /* Wait for 5ms */ + 702 .loc 1 343 0 + 703 0042 2300 movs r3, r4 + 704 0044 0122 movs r2, #1 + 705 0046 6946 mov r1, sp + 706 0048 0631 adds r1, r1, #6 + 707 004a 6846 mov r0, sp + 708 004c 0730 adds r0, r0, #7 + 709 004e FFF7FEFF bl bme680_set_regs + 710 .LVL91: + 711 0052 0500 movs r5, r0 + 712 .LVL92: + 345:Drivers/BME680/bme680.c **** + 713 .loc 1 345 0 + 714 0054 0A20 movs r0, #10 + 715 .LVL93: + 716 0056 236D ldr r3, [r4, #80] + 717 0058 9847 blx r3 + 718 .LVL94: + 347:Drivers/BME680/bme680.c **** /* After reset get the memory page */ + 719 .loc 1 347 0 + 720 005a 002D cmp r5, #0 + 721 005c EAD1 bne .L49 + 349:Drivers/BME680/bme680.c **** rslt = get_mem_page(dev); + 722 .loc 1 349 0 + 723 005e A378 ldrb r3, [r4, #2] + 724 0060 002B cmp r3, #0 + 725 0062 E7D1 bne .L49 + 350:Drivers/BME680/bme680.c **** } + 726 .loc 1 350 0 + 727 0064 2000 movs r0, r4 + 728 0066 FFF7FEFF bl get_mem_page + 729 .LVL95: + 730 006a 0500 movs r5, r0 + 731 .LVL96: + 732 006c E2E7 b .L49 + 733 .LVL97: + 734 .L51: + 735 .LBB76: + 736 .LBB74: +1131:Drivers/BME680/bme680.c **** } else { + 737 .loc 1 1131 0 + 738 006e 0125 movs r5, #1 + 739 0070 6D42 rsbs r5, r5, #0 + 740 0072 DFE7 b .L49 + 741 .L52: + 742 0074 0125 movs r5, #1 + 743 0076 6D42 rsbs r5, r5, #0 + 744 0078 DCE7 b .L49 + 745 .L53: + 746 007a 0125 movs r5, #1 + 747 007c 6D42 rsbs r5, r5, #0 + ARM GAS /tmp/ccvbgJts.s page 35 + + + 748 007e D9E7 b .L49 + 749 .L54: + 750 0080 0125 movs r5, #1 + 751 0082 6D42 rsbs r5, r5, #0 + 752 0084 D6E7 b .L49 + 753 .LBE74: + 754 .LBE76: + 755 .cfi_endproc + 756 .LFE3: + 758 .section .text.bme680_init,"ax",%progbits + 759 .align 1 + 760 .global bme680_init + 761 .syntax unified + 762 .code 16 + 763 .thumb_func + 764 .fpu softvfp + 766 bme680_init: + 767 .LFB0: + 237:Drivers/BME680/bme680.c **** int8_t rslt; + 768 .loc 1 237 0 + 769 .cfi_startproc + 770 @ args = 0, pretend = 0, frame = 72 + 771 @ frame_needed = 0, uses_anonymous_args = 0 + 772 .LVL98: + 773 0000 F0B5 push {r4, r5, r6, r7, lr} + 774 .LCFI11: + 775 .cfi_def_cfa_offset 20 + 776 .cfi_offset 4, -20 + 777 .cfi_offset 5, -16 + 778 .cfi_offset 6, -12 + 779 .cfi_offset 7, -8 + 780 .cfi_offset 14, -4 + 781 0002 93B0 sub sp, sp, #76 + 782 .LCFI12: + 783 .cfi_def_cfa_offset 96 + 784 0004 041E subs r4, r0, #0 + 785 .LVL99: + 786 .LBB83: + 787 .LBB84: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 788 .loc 1 1129 0 + 789 0006 00D1 bne .LCB858 + 790 0008 E1E0 b .L63 @long jump + 791 .LCB858: + 792 000a 836C ldr r3, [r0, #72] + 793 000c 002B cmp r3, #0 + 794 000e 00D1 bne .LCB862 + 795 0010 E0E0 b .L64 @long jump + 796 .LCB862: + 797 0012 C36C ldr r3, [r0, #76] + 798 0014 002B cmp r3, #0 + 799 0016 00D1 bne .LCB866 + 800 0018 DFE0 b .L65 @long jump + 801 .LCB866: + 802 001a 036D ldr r3, [r0, #80] + 803 001c 002B cmp r3, #0 + 804 001e 00D1 bne .LCB870 + ARM GAS /tmp/ccvbgJts.s page 36 + + + 805 0020 DEE0 b .L66 @long jump + 806 .LCB870: + 807 .LVL100: + 808 .LBE84: + 809 .LBE83: + 244:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 810 .loc 1 244 0 + 811 0022 FFF7FEFF bl bme680_soft_reset + 812 .LVL101: + 245:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_CHIP_ID_ADDR, &dev->chip_id, 1, dev); + 813 .loc 1 245 0 + 814 0026 0028 cmp r0, #0 + 815 0028 01D0 beq .L72 + 816 .LVL102: + 817 .L59: + 259:Drivers/BME680/bme680.c **** + 818 .loc 1 259 0 + 819 002a 13B0 add sp, sp, #76 + 820 @ sp needed + 821 .LVL103: + 822 002c F0BD pop {r4, r5, r6, r7, pc} + 823 .LVL104: + 824 .L72: + 246:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 825 .loc 1 246 0 + 826 002e 2300 movs r3, r4 + 827 0030 0122 movs r2, #1 + 828 0032 2100 movs r1, r4 + 829 0034 D030 adds r0, r0, #208 + 830 .LVL105: + 831 0036 FFF7FEFF bl bme680_get_regs + 832 .LVL106: + 247:Drivers/BME680/bme680.c **** if (dev->chip_id == BME680_CHIP_ID) { + 833 .loc 1 247 0 + 834 003a 0028 cmp r0, #0 + 835 003c F5D1 bne .L59 + 248:Drivers/BME680/bme680.c **** /* Get the Calibration data */ + 836 .loc 1 248 0 + 837 003e 2378 ldrb r3, [r4] + 838 0040 612B cmp r3, #97 + 839 0042 00D0 beq .LCB912 + 840 0044 CFE0 b .L67 @long jump + 841 .LCB912: + 842 .LVL107: + 843 .LBB86: + 844 .LBB87: + 668:Drivers/BME680/bme680.c **** uint8_t temp_var = 0; /* Temporary variable */ + 845 .loc 1 668 0 + 846 0046 4122 movs r2, #65 + 847 0048 0021 movs r1, #0 + 848 004a 01A8 add r0, sp, #4 + 849 .LVL108: + 850 004c FFF7FEFF bl memset + 851 .LVL109: + 669:Drivers/BME680/bme680.c **** + 852 .loc 1 669 0 + 853 0050 6B46 mov r3, sp + ARM GAS /tmp/ccvbgJts.s page 37 + + + 854 0052 0022 movs r2, #0 + 855 0054 DA70 strb r2, [r3, #3] + 856 .LVL110: + 857 .LBB88: + 858 .LBB89: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 859 .loc 1 1129 0 + 860 0056 002C cmp r4, #0 + 861 0058 00D1 bne .LCB929 + 862 005a ACE0 b .L68 @long jump + 863 .LCB929: + 864 005c A36C ldr r3, [r4, #72] + 865 005e 002B cmp r3, #0 + 866 0060 00D1 bne .LCB933 + 867 0062 ABE0 b .L69 @long jump + 868 .LCB933: + 869 0064 E36C ldr r3, [r4, #76] + 870 0066 002B cmp r3, #0 + 871 0068 00D1 bne .LCB937 + 872 006a AAE0 b .L70 @long jump + 873 .LCB937: + 874 006c 236D ldr r3, [r4, #80] + 875 006e 002B cmp r3, #0 + 876 0070 00D1 bne .LCB941 + 877 0072 A9E0 b .L71 @long jump + 878 .LCB941: + 879 .LVL111: + 880 .LBE89: + 881 .LBE88: + 674:Drivers/BME680/bme680.c **** /* Append the second half in the same array */ + 882 .loc 1 674 0 + 883 0074 2300 movs r3, r4 + 884 0076 1932 adds r2, r2, #25 + 885 0078 01A9 add r1, sp, #4 + 886 007a 8920 movs r0, #137 + 887 007c FFF7FEFF bl bme680_get_regs + 888 .LVL112: + 676:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_COEFF_ADDR2, &coeff_array[BME680_COEFF_ADDR1_LEN] + 889 .loc 1 676 0 + 890 0080 0028 cmp r0, #0 + 891 0082 6BD0 beq .L73 + 892 .LVL113: + 893 .L61: + 681:Drivers/BME680/bme680.c **** coeff_array[BME680_T1_LSB_REG])); + 894 .loc 1 681 0 + 895 0084 01AB add r3, sp, #4 + 896 0086 2222 movs r2, #34 + 897 0088 995C ldrb r1, [r3, r2] + 898 008a 0902 lsls r1, r1, #8 + 899 008c 013A subs r2, r2, #1 + 900 008e 9A5C ldrb r2, [r3, r2] + 901 0090 0A43 orrs r2, r1 + 902 0092 E282 strh r2, [r4, #22] + 683:Drivers/BME680/bme680.c **** coeff_array[BME680_T2_LSB_REG])); + 903 .loc 1 683 0 + 904 0094 9978 ldrb r1, [r3, #2] + 905 0096 0902 lsls r1, r1, #8 + ARM GAS /tmp/ccvbgJts.s page 38 + + + 906 0098 5A78 ldrb r2, [r3, #1] + 907 009a 0A43 orrs r2, r1 + 908 009c 2283 strh r2, [r4, #24] + 685:Drivers/BME680/bme680.c **** + 909 .loc 1 685 0 + 910 009e 0322 movs r2, #3 + 911 00a0 9A56 ldrsb r2, [r3, r2] + 912 00a2 A276 strb r2, [r4, #26] + 688:Drivers/BME680/bme680.c **** coeff_array[BME680_P1_LSB_REG])); + 913 .loc 1 688 0 + 914 00a4 9979 ldrb r1, [r3, #6] + 915 00a6 0902 lsls r1, r1, #8 + 916 00a8 5A79 ldrb r2, [r3, #5] + 917 00aa 0A43 orrs r2, r1 + 918 00ac A283 strh r2, [r4, #28] + 690:Drivers/BME680/bme680.c **** coeff_array[BME680_P2_LSB_REG])); + 919 .loc 1 690 0 + 920 00ae 197A ldrb r1, [r3, #8] + 921 00b0 0902 lsls r1, r1, #8 + 922 00b2 DA79 ldrb r2, [r3, #7] + 923 00b4 0A43 orrs r2, r1 + 924 00b6 E283 strh r2, [r4, #30] + 692:Drivers/BME680/bme680.c **** dev->calib.par_p4 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P4_MSB_REG], + 925 .loc 1 692 0 + 926 00b8 0922 movs r2, #9 + 927 00ba 9A56 ldrsb r2, [r3, r2] + 928 00bc 2026 movs r6, #32 + 929 00be A255 strb r2, [r4, r6] + 693:Drivers/BME680/bme680.c **** coeff_array[BME680_P4_LSB_REG])); + 930 .loc 1 693 0 + 931 00c0 197B ldrb r1, [r3, #12] + 932 00c2 0902 lsls r1, r1, #8 + 933 00c4 DA7A ldrb r2, [r3, #11] + 934 00c6 0A43 orrs r2, r1 + 935 00c8 6284 strh r2, [r4, #34] + 695:Drivers/BME680/bme680.c **** coeff_array[BME680_P5_LSB_REG])); + 936 .loc 1 695 0 + 937 00ca 997B ldrb r1, [r3, #14] + 938 00cc 0902 lsls r1, r1, #8 + 939 00ce 5A7B ldrb r2, [r3, #13] + 940 00d0 0A43 orrs r2, r1 + 941 00d2 A284 strh r2, [r4, #36] + 697:Drivers/BME680/bme680.c **** dev->calib.par_p7 = (int8_t) (coeff_array[BME680_P7_REG]); + 942 .loc 1 697 0 + 943 00d4 1022 movs r2, #16 + 944 00d6 9A56 ldrsb r2, [r3, r2] + 945 00d8 2625 movs r5, #38 + 946 00da 6255 strb r2, [r4, r5] + 698:Drivers/BME680/bme680.c **** dev->calib.par_p8 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P8_MSB_REG], + 947 .loc 1 698 0 + 948 00dc 0F21 movs r1, #15 + 949 00de 5956 ldrsb r1, [r3, r1] + 950 00e0 2722 movs r2, #39 + 951 00e2 A154 strb r1, [r4, r2] + 699:Drivers/BME680/bme680.c **** coeff_array[BME680_P8_LSB_REG])); + 952 .loc 1 699 0 + 953 00e4 197D ldrb r1, [r3, #20] + ARM GAS /tmp/ccvbgJts.s page 39 + + + 954 00e6 0902 lsls r1, r1, #8 + 955 00e8 DA7C ldrb r2, [r3, #19] + 956 00ea 0A43 orrs r2, r1 + 957 00ec 2285 strh r2, [r4, #40] + 701:Drivers/BME680/bme680.c **** coeff_array[BME680_P9_LSB_REG])); + 958 .loc 1 701 0 + 959 00ee 997D ldrb r1, [r3, #22] + 960 00f0 0902 lsls r1, r1, #8 + 961 00f2 5A7D ldrb r2, [r3, #21] + 962 00f4 0A43 orrs r2, r1 + 963 00f6 6285 strh r2, [r4, #42] + 703:Drivers/BME680/bme680.c **** + 964 .loc 1 703 0 + 965 00f8 D97D ldrb r1, [r3, #23] + 966 00fa 2C22 movs r2, #44 + 967 00fc A154 strb r1, [r4, r2] + 706:Drivers/BME680/bme680.c **** | (coeff_array[BME680_H1_LSB_REG] & BME680_BIT_H1_DATA_MSK)); + 968 .loc 1 706 0 + 969 00fe DF7E ldrb r7, [r3, #27] + 970 0100 3F01 lsls r7, r7, #4 + 707:Drivers/BME680/bme680.c **** dev->calib.par_h2 = (uint16_t) (((uint16_t) coeff_array[BME680_H2_MSB_REG] << BME680_HUM_REG_SHIF + 971 .loc 1 707 0 + 972 0102 9A7E ldrb r2, [r3, #26] + 973 0104 0F21 movs r1, #15 + 974 0106 1140 ands r1, r2 + 706:Drivers/BME680/bme680.c **** | (coeff_array[BME680_H1_LSB_REG] & BME680_BIT_H1_DATA_MSK)); + 975 .loc 1 706 0 + 976 0108 3943 orrs r1, r7 + 977 010a 2181 strh r1, [r4, #8] + 708:Drivers/BME680/bme680.c **** | ((coeff_array[BME680_H2_LSB_REG]) >> BME680_HUM_REG_SHIFT_VAL)); + 978 .loc 1 708 0 + 979 010c 597E ldrb r1, [r3, #25] + 980 010e 0901 lsls r1, r1, #4 + 709:Drivers/BME680/bme680.c **** dev->calib.par_h3 = (int8_t) coeff_array[BME680_H3_REG]; + 981 .loc 1 709 0 + 982 0110 1209 lsrs r2, r2, #4 + 708:Drivers/BME680/bme680.c **** | ((coeff_array[BME680_H2_LSB_REG]) >> BME680_HUM_REG_SHIFT_VAL)); + 983 .loc 1 708 0 + 984 0112 0A43 orrs r2, r1 + 985 0114 6281 strh r2, [r4, #10] + 710:Drivers/BME680/bme680.c **** dev->calib.par_h4 = (int8_t) coeff_array[BME680_H4_REG]; + 986 .loc 1 710 0 + 987 0116 1C22 movs r2, #28 + 988 0118 9A56 ldrsb r2, [r3, r2] + 989 011a 2273 strb r2, [r4, #12] + 711:Drivers/BME680/bme680.c **** dev->calib.par_h5 = (int8_t) coeff_array[BME680_H5_REG]; + 990 .loc 1 711 0 + 991 011c 1D22 movs r2, #29 + 992 011e 9A56 ldrsb r2, [r3, r2] + 993 0120 6273 strb r2, [r4, #13] + 712:Drivers/BME680/bme680.c **** dev->calib.par_h6 = (uint8_t) coeff_array[BME680_H6_REG]; + 994 .loc 1 712 0 + 995 0122 1E22 movs r2, #30 + 996 0124 9A56 ldrsb r2, [r3, r2] + 997 0126 A273 strb r2, [r4, #14] + 713:Drivers/BME680/bme680.c **** dev->calib.par_h7 = (int8_t) coeff_array[BME680_H7_REG]; + 998 .loc 1 713 0 + ARM GAS /tmp/ccvbgJts.s page 40 + + + 999 0128 DA7F ldrb r2, [r3, #31] + 1000 012a E273 strb r2, [r4, #15] + 714:Drivers/BME680/bme680.c **** + 1001 .loc 1 714 0 + 1002 012c 9A57 ldrsb r2, [r3, r6] + 1003 012e 2274 strb r2, [r4, #16] + 717:Drivers/BME680/bme680.c **** dev->calib.par_gh2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_GH2_MSB_REG], + 1004 .loc 1 717 0 + 1005 0130 2522 movs r2, #37 + 1006 0132 9A56 ldrsb r2, [r3, r2] + 1007 0134 6274 strb r2, [r4, #17] + 718:Drivers/BME680/bme680.c **** coeff_array[BME680_GH2_LSB_REG])); + 1008 .loc 1 718 0 + 1009 0136 2422 movs r2, #36 + 1010 0138 995C ldrb r1, [r3, r2] + 1011 013a 0902 lsls r1, r1, #8 + 1012 013c 013A subs r2, r2, #1 + 1013 013e 9A5C ldrb r2, [r3, r2] + 1014 0140 0A43 orrs r2, r1 + 1015 0142 6282 strh r2, [r4, #18] + 720:Drivers/BME680/bme680.c **** + 1016 .loc 1 720 0 + 1017 0144 5B57 ldrsb r3, [r3, r5] + 1018 0146 2375 strb r3, [r4, #20] + 723:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_RANGE_ADDR, &temp_var, 1, dev); + 1019 .loc 1 723 0 + 1020 0148 0028 cmp r0, #0 + 1021 014a 0FD0 beq .L74 + 1022 .LVL114: + 1023 .L62: + 735:Drivers/BME680/bme680.c **** } + 1024 .loc 1 735 0 + 1025 014c 6B46 mov r3, sp + 1026 014e 0333 adds r3, r3, #3 + 1027 0150 1B78 ldrb r3, [r3] + 1028 0152 5BB2 sxtb r3, r3 + 1029 0154 1B11 asrs r3, r3, #4 + 1030 0156 3622 movs r2, #54 + 1031 0158 A354 strb r3, [r4, r2] + 1032 015a 66E7 b .L59 + 1033 .L73: + 677:Drivers/BME680/bme680.c **** , BME680_COEFF_ADDR2_LEN, dev); + 1034 .loc 1 677 0 + 1035 015c 2300 movs r3, r4 + 1036 015e 1022 movs r2, #16 + 1037 0160 1D21 movs r1, #29 + 1038 0162 6944 add r1, r1, sp + 1039 0164 E130 adds r0, r0, #225 + 1040 .LVL115: + 1041 0166 FFF7FEFF bl bme680_get_regs + 1042 .LVL116: + 1043 016a 8BE7 b .L61 + 1044 .L74: + 724:Drivers/BME680/bme680.c **** + 1045 .loc 1 724 0 + 1046 016c 6B46 mov r3, sp + 1047 016e DD1C adds r5, r3, #3 + ARM GAS /tmp/ccvbgJts.s page 41 + + + 1048 0170 2300 movs r3, r4 + 1049 0172 0122 movs r2, #1 + 1050 0174 2900 movs r1, r5 + 1051 0176 0230 adds r0, r0, #2 + 1052 .LVL117: + 1053 0178 FFF7FEFF bl bme680_get_regs + 1054 .LVL118: + 726:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 1055 .loc 1 726 0 + 1056 017c 2A78 ldrb r2, [r5] + 1057 017e 3023 movs r3, #48 + 1058 0180 1340 ands r3, r2 + 1059 0182 1B11 asrs r3, r3, #4 + 1060 0184 3422 movs r2, #52 + 1061 0186 A354 strb r3, [r4, r2] + 727:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_VAL_ADDR, &temp_var, 1, dev); + 1062 .loc 1 727 0 + 1063 0188 0028 cmp r0, #0 + 1064 018a DFD1 bne .L62 + 728:Drivers/BME680/bme680.c **** + 1065 .loc 1 728 0 + 1066 018c 6B46 mov r3, sp + 1067 018e DD1C adds r5, r3, #3 + 1068 0190 2300 movs r3, r4 + 1069 0192 333A subs r2, r2, #51 + 1070 0194 2900 movs r1, r5 + 1071 0196 FFF7FEFF bl bme680_get_regs + 1072 .LVL119: + 730:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 1073 .loc 1 730 0 + 1074 019a 0022 movs r2, #0 + 1075 019c AA56 ldrsb r2, [r5, r2] + 1076 019e 3523 movs r3, #53 + 1077 01a0 E254 strb r2, [r4, r3] + 731:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(BME680_ADDR_RANGE_SW_ERR_ADDR, &temp_var, 1, dev); + 1078 .loc 1 731 0 + 1079 01a2 0028 cmp r0, #0 + 1080 01a4 D2D1 bne .L62 + 732:Drivers/BME680/bme680.c **** } + 1081 .loc 1 732 0 + 1082 01a6 2300 movs r3, r4 + 1083 01a8 0122 movs r2, #1 + 1084 01aa 6946 mov r1, sp + 1085 01ac 0331 adds r1, r1, #3 + 1086 01ae 0430 adds r0, r0, #4 + 1087 .LVL120: + 1088 01b0 FFF7FEFF bl bme680_get_regs + 1089 .LVL121: + 1090 01b4 CAE7 b .L62 + 1091 .LVL122: + 1092 .L68: + 1093 .LBB91: + 1094 .LBB90: +1131:Drivers/BME680/bme680.c **** } else { + 1095 .loc 1 1131 0 + 1096 01b6 0120 movs r0, #1 + 1097 01b8 4042 rsbs r0, r0, #0 + ARM GAS /tmp/ccvbgJts.s page 42 + + + 1098 01ba 36E7 b .L59 + 1099 .L69: + 1100 01bc 0120 movs r0, #1 + 1101 01be 4042 rsbs r0, r0, #0 + 1102 01c0 33E7 b .L59 + 1103 .L70: + 1104 01c2 0120 movs r0, #1 + 1105 01c4 4042 rsbs r0, r0, #0 + 1106 01c6 30E7 b .L59 + 1107 .L71: + 1108 01c8 0120 movs r0, #1 + 1109 01ca 4042 rsbs r0, r0, #0 + 1110 .LVL123: + 1111 01cc 2DE7 b .L59 + 1112 .LVL124: + 1113 .L63: + 1114 .LBE90: + 1115 .LBE91: + 1116 .LBE87: + 1117 .LBE86: + 1118 .LBB92: + 1119 .LBB85: + 1120 01ce 0120 movs r0, #1 + 1121 .LVL125: + 1122 01d0 4042 rsbs r0, r0, #0 + 1123 01d2 2AE7 b .L59 + 1124 .LVL126: + 1125 .L64: + 1126 01d4 0120 movs r0, #1 + 1127 .LVL127: + 1128 01d6 4042 rsbs r0, r0, #0 + 1129 01d8 27E7 b .L59 + 1130 .LVL128: + 1131 .L65: + 1132 01da 0120 movs r0, #1 + 1133 .LVL129: + 1134 01dc 4042 rsbs r0, r0, #0 + 1135 01de 24E7 b .L59 + 1136 .LVL130: + 1137 .L66: + 1138 01e0 0120 movs r0, #1 + 1139 .LVL131: + 1140 01e2 4042 rsbs r0, r0, #0 + 1141 01e4 21E7 b .L59 + 1142 .LVL132: + 1143 .L67: + 1144 .LBE85: + 1145 .LBE92: + 252:Drivers/BME680/bme680.c **** } + 1146 .loc 1 252 0 + 1147 01e6 0320 movs r0, #3 + 1148 .LVL133: + 1149 01e8 4042 rsbs r0, r0, #0 + 1150 01ea 1EE7 b .L59 + 1151 .cfi_endproc + 1152 .LFE0: + 1154 .section .text.bme680_get_sensor_settings,"ax",%progbits + ARM GAS /tmp/ccvbgJts.s page 43 + + + 1155 .align 1 + 1156 .global bme680_get_sensor_settings + 1157 .syntax unified + 1158 .code 16 + 1159 .thumb_func + 1160 .fpu softvfp + 1162 bme680_get_sensor_settings: + 1163 .LFB5: + 487:Drivers/BME680/bme680.c **** int8_t rslt; + 1164 .loc 1 487 0 + 1165 .cfi_startproc + 1166 @ args = 0, pretend = 0, frame = 24 + 1167 @ frame_needed = 0, uses_anonymous_args = 0 + 1168 .LVL134: + 1169 0000 70B5 push {r4, r5, r6, lr} + 1170 .LCFI13: + 1171 .cfi_def_cfa_offset 16 + 1172 .cfi_offset 4, -16 + 1173 .cfi_offset 5, -12 + 1174 .cfi_offset 6, -8 + 1175 .cfi_offset 14, -4 + 1176 0002 86B0 sub sp, sp, #24 + 1177 .LCFI14: + 1178 .cfi_def_cfa_offset 40 + 1179 0004 0600 movs r6, r0 + 1180 0006 0C00 movs r4, r1 + 1181 .LVL135: + 491:Drivers/BME680/bme680.c **** + 1182 .loc 1 491 0 + 1183 0008 0622 movs r2, #6 + 1184 000a 0021 movs r1, #0 + 1185 .LVL136: + 1186 000c 04A8 add r0, sp, #16 + 1187 .LVL137: + 1188 000e FFF7FEFF bl memset + 1189 .LVL138: + 1190 .LBB99: + 1191 .LBB100: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 1192 .loc 1 1129 0 + 1193 0012 002C cmp r4, #0 + 1194 0014 00D1 bne .LCB1301 + 1195 0016 98E0 b .L89 @long jump + 1196 .LCB1301: + 1197 0018 A36C ldr r3, [r4, #72] + 1198 001a 002B cmp r3, #0 + 1199 001c 00D1 bne .LCB1305 + 1200 001e 97E0 b .L90 @long jump + 1201 .LCB1305: + 1202 0020 E36C ldr r3, [r4, #76] + 1203 0022 002B cmp r3, #0 + 1204 0024 00D1 bne .LCB1309 + 1205 0026 96E0 b .L91 @long jump + 1206 .LCB1309: + 1207 0028 236D ldr r3, [r4, #80] + 1208 002a 002B cmp r3, #0 + 1209 002c 00D1 bne .LCB1313 + ARM GAS /tmp/ccvbgJts.s page 44 + + + 1210 002e 95E0 b .L92 @long jump + 1211 .LCB1313: + 1212 .LVL139: + 1213 .LBE100: + 1214 .LBE99: + 496:Drivers/BME680/bme680.c **** + 1215 .loc 1 496 0 + 1216 0030 2300 movs r3, r4 + 1217 0032 0622 movs r2, #6 + 1218 0034 04A9 add r1, sp, #16 + 1219 0036 7020 movs r0, #112 + 1220 0038 FFF7FEFF bl bme680_get_regs + 1221 .LVL140: + 1222 003c 051E subs r5, r0, #0 + 1223 .LVL141: + 498:Drivers/BME680/bme680.c **** if (desired_settings & BME680_GAS_MEAS_SEL) + 1224 .loc 1 498 0 + 1225 003e 34D1 bne .L76 + 499:Drivers/BME680/bme680.c **** rslt = get_gas_config(dev); + 1226 .loc 1 499 0 + 1227 0040 3307 lsls r3, r6, #28 + 1228 0042 35D4 bmi .L99 + 1229 .LVL142: + 1230 .L77: + 503:Drivers/BME680/bme680.c **** dev->tph_sett.filter = BME680_GET_BITS(data_array[BME680_REG_FILTER_INDEX], + 1231 .loc 1 503 0 + 1232 0044 F306 lsls r3, r6, #27 + 1233 0046 06D5 bpl .L85 + 504:Drivers/BME680/bme680.c **** BME680_FILTER); + 1234 .loc 1 504 0 + 1235 0048 04AB add r3, sp, #16 + 1236 004a 5A79 ldrb r2, [r3, #5] + 1237 004c 9210 asrs r2, r2, #2 + 1238 004e 0723 movs r3, #7 + 1239 0050 1340 ands r3, r2 + 1240 0052 3B22 movs r2, #59 + 1241 0054 A354 strb r3, [r4, r2] + 1242 .L85: + 507:Drivers/BME680/bme680.c **** dev->tph_sett.os_temp = BME680_GET_BITS(data_array[BME680_REG_TEMP_INDEX], BME680_OST); + 1243 .loc 1 507 0 + 1244 0056 B307 lsls r3, r6, #30 + 1245 0058 09D0 beq .L86 + 508:Drivers/BME680/bme680.c **** dev->tph_sett.os_pres = BME680_GET_BITS(data_array[BME680_REG_PRES_INDEX], BME680_OSP); + 1246 .loc 1 508 0 + 1247 005a 04AB add r3, sp, #16 + 1248 005c 1B79 ldrb r3, [r3, #4] + 1249 005e 5909 lsrs r1, r3, #5 + 1250 0060 3922 movs r2, #57 + 1251 0062 A154 strb r1, [r4, r2] + 509:Drivers/BME680/bme680.c **** } + 1252 .loc 1 509 0 + 1253 0064 9B10 asrs r3, r3, #2 + 1254 0066 323A subs r2, r2, #50 + 1255 0068 1340 ands r3, r2 + 1256 006a 3332 adds r2, r2, #51 + 1257 006c A354 strb r3, [r4, r2] + 1258 .L86: + ARM GAS /tmp/ccvbgJts.s page 45 + + + 512:Drivers/BME680/bme680.c **** dev->tph_sett.os_hum = BME680_GET_BITS_POS_0(data_array[BME680_REG_HUM_INDEX], + 1259 .loc 1 512 0 + 1260 006e 7307 lsls r3, r6, #29 + 1261 0070 05D5 bpl .L87 + 513:Drivers/BME680/bme680.c **** BME680_OSH); + 1262 .loc 1 513 0 + 1263 0072 04AB add r3, sp, #16 + 1264 0074 9A78 ldrb r2, [r3, #2] + 1265 0076 0723 movs r3, #7 + 1266 0078 1340 ands r3, r2 + 1267 007a 3822 movs r2, #56 + 1268 007c A354 strb r3, [r4, r2] + 1269 .L87: + 517:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_ctrl = BME680_GET_BITS_POS_0(data_array[BME680_REG_HCTRL_INDEX], + 1270 .loc 1 517 0 + 1271 007e B306 lsls r3, r6, #26 + 1272 0080 05D5 bpl .L88 + 518:Drivers/BME680/bme680.c **** BME680_HCTRL); + 1273 .loc 1 518 0 + 1274 0082 04AB add r3, sp, #16 + 1275 0084 1A78 ldrb r2, [r3] + 1276 0086 0823 movs r3, #8 + 1277 0088 1340 ands r3, r2 + 1278 008a 3D22 movs r2, #61 + 1279 008c A354 strb r3, [r4, r2] + 1280 .L88: + 521:Drivers/BME680/bme680.c **** dev->gas_sett.nb_conv = BME680_GET_BITS_POS_0(data_array[BME680_REG_NBCONV_INDEX], + 1281 .loc 1 521 0 + 1282 008e C023 movs r3, #192 + 1283 0090 3342 tst r3, r6 + 1284 0092 0AD0 beq .L76 + 522:Drivers/BME680/bme680.c **** BME680_NBCONV); + 1285 .loc 1 522 0 + 1286 0094 04AB add r3, sp, #16 + 1287 0096 5B78 ldrb r3, [r3, #1] + 1288 0098 0F22 movs r2, #15 + 1289 009a 1A40 ands r2, r3 + 1290 009c 3C21 movs r1, #60 + 1291 009e 6254 strb r2, [r4, r1] + 524:Drivers/BME680/bme680.c **** BME680_RUN_GAS); + 1292 .loc 1 524 0 + 1293 00a0 1B11 asrs r3, r3, #4 + 1294 00a2 0122 movs r2, #1 + 1295 00a4 1340 ands r3, r2 + 1296 00a6 3D32 adds r2, r2, #61 + 1297 00a8 A354 strb r3, [r4, r2] + 1298 .LVL143: + 1299 .L76: + 533:Drivers/BME680/bme680.c **** + 1300 .loc 1 533 0 + 1301 00aa 2800 movs r0, r5 + 1302 00ac 06B0 add sp, sp, #24 + 1303 @ sp needed + 1304 .LVL144: + 1305 .LVL145: + 1306 00ae 70BD pop {r4, r5, r6, pc} + 1307 .LVL146: + ARM GAS /tmp/ccvbgJts.s page 46 + + + 1308 .L99: + 1309 .LBB101: + 1310 .LBB102: + 780:Drivers/BME680/bme680.c **** uint8_t index; + 1311 .loc 1 780 0 + 1312 00b0 0A22 movs r2, #10 + 1313 00b2 0021 movs r1, #0 + 1314 00b4 01A8 add r0, sp, #4 + 1315 .LVL147: + 1316 00b6 FFF7FEFF bl memset + 1317 .LVL148: + 1318 .LBB103: + 1319 .LBB104: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 1320 .loc 1 1129 0 + 1321 00ba 002C cmp r4, #0 + 1322 00bc 39D0 beq .L93 + 1323 00be A36C ldr r3, [r4, #72] + 1324 00c0 002B cmp r3, #0 + 1325 00c2 39D0 beq .L94 + 1326 00c4 E36C ldr r3, [r4, #76] + 1327 00c6 002B cmp r3, #0 + 1328 00c8 39D0 beq .L95 + 1329 00ca 236D ldr r3, [r4, #80] + 1330 00cc 002B cmp r3, #0 + 1331 00ce 39D0 beq .L96 + 1332 .LVL149: + 1333 .LBE104: + 1334 .LBE103: + 786:Drivers/BME680/bme680.c **** /* Memory page switch the SPI address*/ + 1335 .loc 1 786 0 + 1336 00d0 A378 ldrb r3, [r4, #2] + 1337 00d2 002B cmp r3, #0 + 1338 00d4 13D0 beq .L100 + 1339 .LVL150: + 1340 .L79: + 791:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(reg_addr1, data_array, BME680_GAS_HEATER_PROF_LEN_MAX, dev); + 1341 .loc 1 791 0 + 1342 00d6 002D cmp r5, #0 + 1343 00d8 B4D1 bne .L77 + 792:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 1344 .loc 1 792 0 + 1345 00da 2300 movs r3, r4 + 1346 00dc 0A22 movs r2, #10 + 1347 00de 01A9 add r1, sp, #4 + 1348 00e0 5A20 movs r0, #90 + 1349 00e2 FFF7FEFF bl bme680_get_regs + 1350 .LVL151: + 793:Drivers/BME680/bme680.c **** for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + 1351 .loc 1 793 0 + 1352 00e6 0028 cmp r0, #0 + 1353 00e8 18D0 beq .L97 + 1354 .L81: + 798:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 1355 .loc 1 798 0 + 1356 00ea 2300 movs r3, r4 + 1357 00ec 0A22 movs r2, #10 + ARM GAS /tmp/ccvbgJts.s page 47 + + + 1358 00ee 01A9 add r1, sp, #4 + 1359 00f0 6420 movs r0, #100 + 1360 .LVL152: + 1361 00f2 FFF7FEFF bl bme680_get_regs + 1362 .LVL153: + 1363 00f6 051E subs r5, r0, #0 + 1364 .LVL154: + 799:Drivers/BME680/bme680.c **** for (index = 0; index < BME680_GAS_HEATER_PROF_LEN_MAX; index++) + 1365 .loc 1 799 0 + 1366 00f8 A4D1 bne .L77 + 800:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_dur = data_array[index]; + 1367 .loc 1 800 0 + 1368 00fa 0023 movs r3, #0 + 1369 00fc 16E0 b .L83 + 1370 .LVL155: + 1371 .L100: + 788:Drivers/BME680/bme680.c **** } + 1372 .loc 1 788 0 + 1373 00fe 2100 movs r1, r4 + 1374 0100 5A20 movs r0, #90 + 1375 0102 FFF7FEFF bl set_mem_page + 1376 .LVL156: + 1377 0106 0500 movs r5, r0 + 1378 .LVL157: + 1379 0108 E5E7 b .L79 + 1380 .LVL158: + 1381 .L82: + 795:Drivers/BME680/bme680.c **** } + 1382 .loc 1 795 0 + 1383 010a 01AA add r2, sp, #4 + 1384 010c D15C ldrb r1, [r2, r3] + 1385 010e 4022 movs r2, #64 + 1386 0110 A152 strh r1, [r4, r2] + 794:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_temp = data_array[index]; + 1387 .loc 1 794 0 + 1388 0112 0133 adds r3, r3, #1 + 1389 .LVL159: + 1390 0114 DBB2 uxtb r3, r3 + 1391 .LVL160: + 1392 .L80: + 1393 0116 092B cmp r3, #9 + 1394 0118 F7D9 bls .L82 + 1395 011a E6E7 b .L81 + 1396 .LVL161: + 1397 .L97: + 1398 011c 0023 movs r3, #0 + 1399 011e FAE7 b .L80 + 1400 .LVL162: + 1401 .L84: + 801:Drivers/BME680/bme680.c **** } + 1402 .loc 1 801 0 + 1403 0120 01AA add r2, sp, #4 + 1404 0122 D15C ldrb r1, [r2, r3] + 1405 0124 4222 movs r2, #66 + 1406 0126 A152 strh r1, [r4, r2] + 800:Drivers/BME680/bme680.c **** dev->gas_sett.heatr_dur = data_array[index]; + 1407 .loc 1 800 0 + ARM GAS /tmp/ccvbgJts.s page 48 + + + 1408 0128 0133 adds r3, r3, #1 + 1409 .LVL163: + 1410 012a DBB2 uxtb r3, r3 + 1411 .LVL164: + 1412 .L83: + 1413 012c 092B cmp r3, #9 + 1414 012e F7D9 bls .L84 + 1415 0130 88E7 b .L77 + 1416 .LVL165: + 1417 .L93: + 1418 .LBB106: + 1419 .LBB105: +1131:Drivers/BME680/bme680.c **** } else { + 1420 .loc 1 1131 0 + 1421 0132 0125 movs r5, #1 + 1422 .LVL166: + 1423 0134 6D42 rsbs r5, r5, #0 + 1424 0136 85E7 b .L77 + 1425 .LVL167: + 1426 .L94: + 1427 0138 0125 movs r5, #1 + 1428 .LVL168: + 1429 013a 6D42 rsbs r5, r5, #0 + 1430 013c 82E7 b .L77 + 1431 .LVL169: + 1432 .L95: + 1433 013e 0125 movs r5, #1 + 1434 .LVL170: + 1435 0140 6D42 rsbs r5, r5, #0 + 1436 0142 7FE7 b .L77 + 1437 .LVL171: + 1438 .L96: + 1439 0144 0125 movs r5, #1 + 1440 .LVL172: + 1441 0146 6D42 rsbs r5, r5, #0 + 1442 .LVL173: + 1443 0148 7CE7 b .L77 + 1444 .LVL174: + 1445 .L89: + 1446 .LBE105: + 1447 .LBE106: + 1448 .LBE102: + 1449 .LBE101: + 529:Drivers/BME680/bme680.c **** } + 1450 .loc 1 529 0 + 1451 014a 0125 movs r5, #1 + 1452 014c 6D42 rsbs r5, r5, #0 + 1453 014e ACE7 b .L76 + 1454 .L90: + 1455 0150 0125 movs r5, #1 + 1456 0152 6D42 rsbs r5, r5, #0 + 1457 0154 A9E7 b .L76 + 1458 .L91: + 1459 0156 0125 movs r5, #1 + 1460 0158 6D42 rsbs r5, r5, #0 + 1461 015a A6E7 b .L76 + 1462 .L92: + ARM GAS /tmp/ccvbgJts.s page 49 + + + 1463 015c 0125 movs r5, #1 + 1464 015e 6D42 rsbs r5, r5, #0 + 1465 0160 A3E7 b .L76 + 1466 .cfi_endproc + 1467 .LFE5: + 1469 .section .text.bme680_set_sensor_mode,"ax",%progbits + 1470 .align 1 + 1471 .global bme680_set_sensor_mode + 1472 .syntax unified + 1473 .code 16 + 1474 .thumb_func + 1475 .fpu softvfp + 1477 bme680_set_sensor_mode: + 1478 .LFB6: + 539:Drivers/BME680/bme680.c **** int8_t rslt; + 1479 .loc 1 539 0 + 1480 .cfi_startproc + 1481 @ args = 0, pretend = 0, frame = 8 + 1482 @ frame_needed = 0, uses_anonymous_args = 0 + 1483 .LVL175: + 1484 0000 70B5 push {r4, r5, r6, lr} + 1485 .LCFI15: + 1486 .cfi_def_cfa_offset 16 + 1487 .cfi_offset 4, -16 + 1488 .cfi_offset 5, -12 + 1489 .cfi_offset 6, -8 + 1490 .cfi_offset 14, -4 + 1491 0002 82B0 sub sp, sp, #8 + 1492 .LCFI16: + 1493 .cfi_def_cfa_offset 24 + 1494 0004 0600 movs r6, r0 + 1495 .LVL176: + 543:Drivers/BME680/bme680.c **** + 1496 .loc 1 543 0 + 1497 0006 6B46 mov r3, sp + 1498 0008 7422 movs r2, #116 + 1499 000a 9A71 strb r2, [r3, #6] + 1500 .LVL177: + 1501 .LBB107: + 1502 .LBB108: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 1503 .loc 1 1129 0 + 1504 000c 0028 cmp r0, #0 + 1505 000e 48D0 beq .L105 + 1506 0010 836C ldr r3, [r0, #72] + 1507 0012 002B cmp r3, #0 + 1508 0014 48D0 beq .L106 + 1509 0016 C36C ldr r3, [r0, #76] + 1510 0018 002B cmp r3, #0 + 1511 001a 48D0 beq .L107 + 1512 001c 036D ldr r3, [r0, #80] + 1513 001e 002B cmp r3, #0 + 1514 0020 48D0 beq .L108 + 1515 .LBE108: + 1516 .LBE107: + 542:Drivers/BME680/bme680.c **** uint8_t reg_addr = BME680_CONF_T_P_MODE_ADDR; + 1517 .loc 1 542 0 + ARM GAS /tmp/ccvbgJts.s page 50 + + + 1518 0022 0025 movs r5, #0 + 1519 0024 01E0 b .L104 + 1520 .LVL178: + 1521 .L103: + 561:Drivers/BME680/bme680.c **** + 1522 .loc 1 561 0 + 1523 0026 002D cmp r5, #0 + 1524 0028 1ED0 beq .L109 + 1525 .LVL179: + 1526 .L104: + 550:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) { + 1527 .loc 1 550 0 + 1528 002a 3300 movs r3, r6 + 1529 002c 0122 movs r2, #1 + 1530 002e 6946 mov r1, sp + 1531 0030 0731 adds r1, r1, #7 + 1532 0032 7420 movs r0, #116 + 1533 0034 FFF7FEFF bl bme680_get_regs + 1534 .LVL180: + 1535 0038 041E subs r4, r0, #0 + 1536 .LVL181: + 551:Drivers/BME680/bme680.c **** /* Put to sleep before changing mode */ + 1537 .loc 1 551 0 + 1538 003a F4D1 bne .L103 + 553:Drivers/BME680/bme680.c **** + 1539 .loc 1 553 0 + 1540 003c 6B46 mov r3, sp + 1541 003e 0733 adds r3, r3, #7 + 1542 0040 1B78 ldrb r3, [r3] + 1543 0042 0325 movs r5, #3 + 1544 .LVL182: + 1545 0044 1D40 ands r5, r3 + 1546 .LVL183: + 555:Drivers/BME680/bme680.c **** tmp_pow_mode = tmp_pow_mode & (~BME680_MODE_MSK); /* Set to sleep */ + 1547 .loc 1 555 0 + 1548 0046 EED0 beq .L103 + 556:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + 1549 .loc 1 556 0 + 1550 0048 0322 movs r2, #3 + 1551 004a 9343 bics r3, r2 + 1552 004c 6A46 mov r2, sp + 1553 004e D11D adds r1, r2, #7 + 1554 0050 0B70 strb r3, [r1] + 557:Drivers/BME680/bme680.c **** dev->delay_ms(BME680_POLL_PERIOD_MS); + 1555 .loc 1 557 0 + 1556 0052 3300 movs r3, r6 + 1557 0054 0122 movs r2, #1 + 1558 0056 6846 mov r0, sp + 1559 .LVL184: + 1560 0058 0630 adds r0, r0, #6 + 1561 005a FFF7FEFF bl bme680_set_regs + 1562 .LVL185: + 1563 005e 0400 movs r4, r0 + 1564 .LVL186: + 558:Drivers/BME680/bme680.c **** } + 1565 .loc 1 558 0 + 1566 0060 0A20 movs r0, #10 + ARM GAS /tmp/ccvbgJts.s page 51 + + + 1567 .LVL187: + 1568 0062 336D ldr r3, [r6, #80] + 1569 0064 9847 blx r3 + 1570 .LVL188: + 1571 0066 DEE7 b .L103 + 1572 .L109: + 564:Drivers/BME680/bme680.c **** tmp_pow_mode = (tmp_pow_mode & ~BME680_MODE_MSK) | (dev->power_mode & BME680_MODE_MSK); + 1573 .loc 1 564 0 + 1574 0068 4423 movs r3, #68 + 1575 006a F25C ldrb r2, [r6, r3] + 1576 006c 002A cmp r2, #0 + 1577 006e 0BD0 beq .L102 + 565:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 1578 .loc 1 565 0 + 1579 0070 6B46 mov r3, sp + 1580 0072 D91D adds r1, r3, #7 + 1581 0074 DB79 ldrb r3, [r3, #7] + 1582 0076 0320 movs r0, #3 + 1583 0078 8343 bics r3, r0 + 1584 007a 5BB2 sxtb r3, r3 + 1585 007c 52B2 sxtb r2, r2 + 1586 007e 0240 ands r2, r0 + 1587 0080 1343 orrs r3, r2 + 1588 0082 0B70 strb r3, [r1] + 566:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev); + 1589 .loc 1 566 0 + 1590 0084 002C cmp r4, #0 + 1591 0086 02D0 beq .L110 + 1592 .LVL189: + 1593 .L102: + 572:Drivers/BME680/bme680.c **** + 1594 .loc 1 572 0 + 1595 0088 2000 movs r0, r4 + 1596 008a 02B0 add sp, sp, #8 + 1597 @ sp needed + 1598 .LVL190: + 1599 .LVL191: + 1600 008c 70BD pop {r4, r5, r6, pc} + 1601 .LVL192: + 1602 .L110: + 567:Drivers/BME680/bme680.c **** } + 1603 .loc 1 567 0 + 1604 008e 3300 movs r3, r6 + 1605 0090 0122 movs r2, #1 + 1606 0092 6946 mov r1, sp + 1607 0094 0731 adds r1, r1, #7 + 1608 0096 6846 mov r0, sp + 1609 0098 0630 adds r0, r0, #6 + 1610 009a FFF7FEFF bl bme680_set_regs + 1611 .LVL193: + 1612 009e 0400 movs r4, r0 + 1613 .LVL194: + 1614 00a0 F2E7 b .L102 + 1615 .LVL195: + 1616 .L105: + 1617 .LBB110: + 1618 .LBB109: + ARM GAS /tmp/ccvbgJts.s page 52 + + +1131:Drivers/BME680/bme680.c **** } else { + 1619 .loc 1 1131 0 + 1620 00a2 0124 movs r4, #1 + 1621 00a4 6442 rsbs r4, r4, #0 + 1622 00a6 EFE7 b .L102 + 1623 .L106: + 1624 00a8 0124 movs r4, #1 + 1625 00aa 6442 rsbs r4, r4, #0 + 1626 00ac ECE7 b .L102 + 1627 .L107: + 1628 00ae 0124 movs r4, #1 + 1629 00b0 6442 rsbs r4, r4, #0 + 1630 00b2 E9E7 b .L102 + 1631 .L108: + 1632 00b4 0124 movs r4, #1 + 1633 00b6 6442 rsbs r4, r4, #0 + 1634 00b8 E6E7 b .L102 + 1635 .LBE109: + 1636 .LBE110: + 1637 .cfi_endproc + 1638 .LFE6: + 1640 .global __aeabi_idiv + 1641 .section .text.bme680_set_sensor_settings,"ax",%progbits + 1642 .align 1 + 1643 .global bme680_set_sensor_settings + 1644 .syntax unified + 1645 .code 16 + 1646 .thumb_func + 1647 .fpu softvfp + 1649 bme680_set_sensor_settings: + 1650 .LFB4: + 363:Drivers/BME680/bme680.c **** int8_t rslt; + 1651 .loc 1 363 0 + 1652 .cfi_startproc + 1653 @ args = 0, pretend = 0, frame = 24 + 1654 @ frame_needed = 0, uses_anonymous_args = 0 + 1655 .LVL196: + 1656 0000 F0B5 push {r4, r5, r6, r7, lr} + 1657 .LCFI17: + 1658 .cfi_def_cfa_offset 20 + 1659 .cfi_offset 4, -20 + 1660 .cfi_offset 5, -16 + 1661 .cfi_offset 6, -12 + 1662 .cfi_offset 7, -8 + 1663 .cfi_offset 14, -4 + 1664 0002 D646 mov lr, r10 + 1665 0004 4F46 mov r7, r9 + 1666 0006 4646 mov r6, r8 + 1667 0008 C0B5 push {r6, r7, lr} + 1668 .LCFI18: + 1669 .cfi_def_cfa_offset 32 + 1670 .cfi_offset 8, -32 + 1671 .cfi_offset 9, -28 + 1672 .cfi_offset 10, -24 + 1673 000a 86B0 sub sp, sp, #24 + 1674 .LCFI19: + 1675 .cfi_def_cfa_offset 56 + ARM GAS /tmp/ccvbgJts.s page 53 + + + 1676 000c 0600 movs r6, r0 + 1677 000e 0C00 movs r4, r1 + 366:Drivers/BME680/bme680.c **** uint8_t count = 0; + 1678 .loc 1 366 0 + 1679 0010 1723 movs r3, #23 + 1680 0012 6B44 add r3, r3, sp + 1681 0014 0022 movs r2, #0 + 1682 0016 1A70 strb r2, [r3] + 1683 .LVL197: + 368:Drivers/BME680/bme680.c **** uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + 1684 .loc 1 368 0 + 1685 0018 0632 adds r2, r2, #6 + 1686 001a 0021 movs r1, #0 + 1687 .LVL198: + 1688 001c 04A8 add r0, sp, #16 + 1689 .LVL199: + 1690 001e FFF7FEFF bl memset + 1691 .LVL200: + 369:Drivers/BME680/bme680.c **** uint8_t intended_power_mode = dev->power_mode; /* Save intended power mode */ + 1692 .loc 1 369 0 + 1693 0022 0622 movs r2, #6 + 1694 0024 0021 movs r1, #0 + 1695 0026 02A8 add r0, sp, #8 + 1696 0028 FFF7FEFF bl memset + 1697 .LVL201: + 370:Drivers/BME680/bme680.c **** + 1698 .loc 1 370 0 + 1699 002c 4423 movs r3, #68 + 1700 002e E35C ldrb r3, [r4, r3] + 1701 0030 9A46 mov r10, r3 + 1702 .LVL202: + 1703 .LBB134: + 1704 .LBB135: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 1705 .loc 1 1129 0 + 1706 0032 002C cmp r4, #0 + 1707 0034 00D1 bne .LCB1900 + 1708 0036 F6E1 b .L142 @long jump + 1709 .LCB1900: + 1710 0038 A36C ldr r3, [r4, #72] + 1711 003a 002B cmp r3, #0 + 1712 003c 00D1 bne .LCB1904 + 1713 003e F5E1 b .L143 @long jump + 1714 .LCB1904: + 1715 0040 E36C ldr r3, [r4, #76] + 1716 0042 002B cmp r3, #0 + 1717 0044 00D1 bne .LCB1908 + 1718 0046 F4E1 b .L144 @long jump + 1719 .LCB1908: + 1720 0048 236D ldr r3, [r4, #80] + 1721 004a 002B cmp r3, #0 + 1722 004c 00D1 bne .LCB1912 + 1723 004e F3E1 b .L145 @long jump + 1724 .LCB1912: + 1725 .LVL203: + 1726 .LBE135: + 1727 .LBE134: + ARM GAS /tmp/ccvbgJts.s page 54 + + + 375:Drivers/BME680/bme680.c **** rslt = set_gas_config(dev); + 1728 .loc 1 375 0 + 1729 0050 3307 lsls r3, r6, #28 + 1730 0052 35D4 bmi .L162 + 1731 .LBB138: + 1732 .LBB136: + 1733 .loc 1 1134 0 + 1734 0054 0020 movs r0, #0 + 1735 .L113: + 1736 .LVL204: + 1737 .LBE136: + 1738 .LBE138: + 378:Drivers/BME680/bme680.c **** if (rslt == BME680_OK) + 1739 .loc 1 378 0 + 1740 0056 4423 movs r3, #68 + 1741 0058 0022 movs r2, #0 + 1742 005a E254 strb r2, [r4, r3] + 379:Drivers/BME680/bme680.c **** rslt = bme680_set_sensor_mode(dev); + 1743 .loc 1 379 0 + 1744 005c 0028 cmp r0, #0 + 1745 005e 00D1 bne .LCB1933 + 1746 0060 C9E0 b .L163 @long jump + 1747 .LCB1933: + 1748 .LVL205: + 1749 .L120: + 383:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.filter, BME680_FILTER_SIZE_0, BME680_FILTER_SIZE_127, dev); + 1750 .loc 1 383 0 + 1751 0062 F306 lsls r3, r6, #27 + 1752 0064 00D4 bmi .LCB1941 + 1753 0066 CDE0 b .L155 @long jump + 1754 .LCB1941: + 1755 .LVL206: + 1756 .LBB139: + 1757 .LBB140: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 1758 .loc 1 1101 0 + 1759 0068 2300 movs r3, r4 + 1760 006a 3B33 adds r3, r3, #59 + 1761 006c 00D1 bne .LCB1952 + 1762 006e C6E0 b .L156 @long jump + 1763 .LCB1952: +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 1764 .loc 1 1103 0 + 1765 0070 3B23 movs r3, #59 + 1766 0072 E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 1767 .loc 1 1109 0 + 1768 0074 072B cmp r3, #7 + 1769 0076 07D9 bls .L123 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 1770 .loc 1 1111 0 + 1771 0078 3B23 movs r3, #59 + 1772 007a 0722 movs r2, #7 + 1773 007c E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 1774 .loc 1 1112 0 + 1775 007e 3F32 adds r2, r2, #63 + ARM GAS /tmp/ccvbgJts.s page 55 + + + 1776 0080 A35C ldrb r3, [r4, r2] + 1777 0082 0221 movs r1, #2 + 1778 0084 0B43 orrs r3, r1 + 1779 0086 A354 strb r3, [r4, r2] + 1780 .LVL207: + 1781 .L123: + 1782 .LBE140: + 1783 .LBE139: + 388:Drivers/BME680/bme680.c **** + 1784 .loc 1 388 0 + 1785 0088 2300 movs r3, r4 + 1786 008a 0122 movs r2, #1 + 1787 008c 1721 movs r1, #23 + 1788 008e 6944 add r1, r1, sp + 1789 0090 7520 movs r0, #117 + 1790 0092 FFF7FEFF bl bme680_get_regs + 1791 .LVL208: + 1792 .L122: + 391:Drivers/BME680/bme680.c **** + 1793 .loc 1 391 0 + 1794 0096 1722 movs r2, #23 + 1795 0098 6A44 add r2, r2, sp + 1796 009a 1378 ldrb r3, [r2] + 1797 009c 1C21 movs r1, #28 + 1798 009e 8B43 bics r3, r1 + 1799 00a0 5BB2 sxtb r3, r3 + 1800 00a2 1F31 adds r1, r1, #31 + 1801 00a4 655C ldrb r5, [r4, r1] + 1802 00a6 AD00 lsls r5, r5, #2 + 1803 00a8 1F39 subs r1, r1, #31 + 1804 00aa 2940 ands r1, r5 + 1805 00ac 0B43 orrs r3, r1 + 1806 00ae DBB2 uxtb r3, r3 + 1807 00b0 1370 strb r3, [r2] + 393:Drivers/BME680/bme680.c **** data_array[count] = data; + 1808 .loc 1 393 0 + 1809 00b2 04AA add r2, sp, #16 + 1810 00b4 7521 movs r1, #117 + 1811 00b6 1170 strb r1, [r2] + 394:Drivers/BME680/bme680.c **** count++; + 1812 .loc 1 394 0 + 1813 00b8 02AA add r2, sp, #8 + 1814 00ba 1370 strb r3, [r2] + 1815 .LVL209: + 395:Drivers/BME680/bme680.c **** } + 1816 .loc 1 395 0 + 1817 00bc 0125 movs r5, #1 + 1818 00be A2E0 b .L121 + 1819 .LVL210: + 1820 .L162: + 1821 .LBB142: + 1822 .LBB143: + 1823 .LBB144: + 1824 .LBB145: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 1825 .loc 1 1129 0 + 1826 00c0 002C cmp r4, #0 + ARM GAS /tmp/ccvbgJts.s page 56 + + + 1827 00c2 00D1 bne .LCB2028 + 1828 00c4 8BE0 b .L147 @long jump + 1829 .LCB2028: + 1830 00c6 A36C ldr r3, [r4, #72] + 1831 00c8 002B cmp r3, #0 + 1832 00ca 00D1 bne .LCB2032 + 1833 00cc 8AE0 b .L148 @long jump + 1834 .LCB2032: + 1835 00ce E36C ldr r3, [r4, #76] + 1836 00d0 002B cmp r3, #0 + 1837 00d2 00D1 bne .LCB2036 + 1838 00d4 89E0 b .L149 @long jump + 1839 .LCB2036: + 1840 00d6 236D ldr r3, [r4, #80] + 1841 00d8 002B cmp r3, #0 + 1842 00da 00D1 bne .LCB2040 + 1843 00dc 88E0 b .L150 @long jump + 1844 .LCB2040: + 1845 .LVL211: + 1846 .LBE145: + 1847 .LBE144: + 1848 .LBB147: + 752:Drivers/BME680/bme680.c **** uint8_t reg_data[2] = {0}; + 1849 .loc 1 752 0 + 1850 00de 0023 movs r3, #0 + 1851 00e0 6A46 mov r2, sp + 1852 00e2 1380 strh r3, [r2] + 753:Drivers/BME680/bme680.c **** + 1853 .loc 1 753 0 + 1854 00e4 01AA add r2, sp, #4 + 1855 00e6 1380 strh r3, [r2] + 755:Drivers/BME680/bme680.c **** reg_addr[0] = BME680_RES_HEAT0_ADDR; + 1856 .loc 1 755 0 + 1857 00e8 4433 adds r3, r3, #68 + 1858 00ea E35C ldrb r3, [r4, r3] + 1859 00ec 012B cmp r3, #1 + 1860 00ee 01D0 beq .L164 + 762:Drivers/BME680/bme680.c **** } + 1861 .loc 1 762 0 + 1862 00f0 0120 movs r0, #1 + 1863 .LVL212: + 1864 00f2 B0E7 b .L113 + 1865 .LVL213: + 1866 .L164: + 756:Drivers/BME680/bme680.c **** reg_data[0] = calc_heater_res(dev->gas_sett.heatr_temp, dev); + 1867 .loc 1 756 0 + 1868 00f4 5933 adds r3, r3, #89 + 1869 00f6 6A46 mov r2, sp + 1870 00f8 1370 strb r3, [r2] + 757:Drivers/BME680/bme680.c **** reg_addr[1] = BME680_GAS_WAIT0_ADDR; + 1871 .loc 1 757 0 + 1872 00fa 1A3B subs r3, r3, #26 + 1873 00fc E55A ldrh r5, [r4, r3] + 1874 .LVL214: + 1875 .LBB148: + 1876 .LBB149: + 940:Drivers/BME680/bme680.c **** temp = 200; + ARM GAS /tmp/ccvbgJts.s page 57 + + + 1877 .loc 1 940 0 + 1878 00fe C72D cmp r5, #199 + 1879 0100 06D9 bls .L152 + 942:Drivers/BME680/bme680.c **** temp = 400; + 1880 .loc 1 942 0 + 1881 0102 5133 adds r3, r3, #81 + 1882 0104 FF33 adds r3, r3, #255 + 1883 0106 9D42 cmp r5, r3 + 1884 0108 03D9 bls .L116 + 943:Drivers/BME680/bme680.c **** + 1885 .loc 1 943 0 + 1886 010a C825 movs r5, #200 + 1887 .LVL215: + 1888 010c 6D00 lsls r5, r5, #1 + 1889 010e 00E0 b .L116 + 1890 .LVL216: + 1891 .L152: + 941:Drivers/BME680/bme680.c **** else if (temp > 400) + 1892 .loc 1 941 0 + 1893 0110 C825 movs r5, #200 + 1894 .LVL217: + 1895 .L116: + 945:Drivers/BME680/bme680.c **** var2 = (dev->calib.par_gh1 + 784) * (((((dev->calib.par_gh2 + 154009) * temp * 5) / 100) + 3276800 + 1896 .loc 1 945 0 + 1897 0112 0423 movs r3, #4 + 1898 0114 E356 ldrsb r3, [r4, r3] + 1899 0116 1420 movs r0, #20 + 1900 0118 2056 ldrsb r0, [r4, r0] + 1901 011a 5843 muls r0, r3 + 1902 011c FA21 movs r1, #250 + 1903 011e 8900 lsls r1, r1, #2 + 1904 0120 FFF7FEFF bl __aeabi_idiv + 1905 .LVL218: + 1906 0124 0302 lsls r3, r0, #8 + 1907 0126 9946 mov r9, r3 + 1908 .LVL219: + 946:Drivers/BME680/bme680.c **** var3 = var1 + (var2 / 2); + 1909 .loc 1 946 0 + 1910 0128 1123 movs r3, #17 + 1911 .LVL220: + 1912 012a E356 ldrsb r3, [r4, r3] + 1913 012c C422 movs r2, #196 + 1914 012e 9200 lsls r2, r2, #2 + 1915 0130 9046 mov r8, r2 + 1916 0132 9844 add r8, r8, r3 + 1917 0134 1222 movs r2, #18 + 1918 0136 A35E ldrsh r3, [r4, r2] + 1919 0138 C14A ldr r2, .L166 + 1920 013a 9446 mov ip, r2 + 1921 013c 6344 add r3, r3, ip + 1922 013e 6B43 muls r3, r5 + 1923 0140 9800 lsls r0, r3, #2 + 1924 0142 C018 adds r0, r0, r3 + 1925 0144 6421 movs r1, #100 + 1926 0146 FFF7FEFF bl __aeabi_idiv + 1927 .LVL221: + 1928 014a C823 movs r3, #200 + ARM GAS /tmp/ccvbgJts.s page 58 + + + 1929 014c 9B03 lsls r3, r3, #14 + 1930 014e 9C46 mov ip, r3 + 1931 0150 6044 add r0, r0, ip + 1932 0152 0A21 movs r1, #10 + 1933 0154 FFF7FEFF bl __aeabi_idiv + 1934 .LVL222: + 1935 0158 4346 mov r3, r8 + 1936 015a 4343 muls r3, r0 + 1937 .LVL223: + 947:Drivers/BME680/bme680.c **** var4 = (var3 / (dev->calib.res_heat_range + 4)); + 1938 .loc 1 947 0 + 1939 015c D80F lsrs r0, r3, #31 + 1940 015e C018 adds r0, r0, r3 + 1941 0160 4010 asrs r0, r0, #1 + 1942 0162 4844 add r0, r0, r9 + 1943 .LVL224: + 948:Drivers/BME680/bme680.c **** var5 = (131 * dev->calib.res_heat_val) + 65536; + 1944 .loc 1 948 0 + 1945 0164 3423 movs r3, #52 + 1946 .LVL225: + 1947 0166 E15C ldrb r1, [r4, r3] + 1948 0168 0431 adds r1, r1, #4 + 1949 016a FFF7FEFF bl __aeabi_idiv + 1950 .LVL226: + 949:Drivers/BME680/bme680.c **** heatr_res_x100 = (int32_t) (((var4 / var5) - 250) * 34); + 1951 .loc 1 949 0 + 1952 016e 3523 movs r3, #53 + 1953 0170 E356 ldrsb r3, [r4, r3] + 1954 0172 9901 lsls r1, r3, #6 + 1955 0174 C918 adds r1, r1, r3 + 1956 0176 4900 lsls r1, r1, #1 + 1957 0178 C918 adds r1, r1, r3 + 1958 017a 8023 movs r3, #128 + 1959 017c 5B02 lsls r3, r3, #9 + 1960 017e 9C46 mov ip, r3 + 1961 0180 6144 add r1, r1, ip + 1962 .LVL227: + 950:Drivers/BME680/bme680.c **** heatr_res = (uint8_t) ((heatr_res_x100 + 50) / 100); + 1963 .loc 1 950 0 + 1964 0182 FFF7FEFF bl __aeabi_idiv + 1965 .LVL228: + 1966 0186 0300 movs r3, r0 + 1967 0188 FA3B subs r3, r3, #250 + 1968 018a 1801 lsls r0, r3, #4 + 1969 018c C018 adds r0, r0, r3 + 1970 018e 4000 lsls r0, r0, #1 + 1971 .LVL229: + 951:Drivers/BME680/bme680.c **** + 1972 .loc 1 951 0 + 1973 0190 3230 adds r0, r0, #50 + 1974 .LVL230: + 1975 0192 6421 movs r1, #100 + 1976 0194 FFF7FEFF bl __aeabi_idiv + 1977 .LVL231: + 1978 .LBE149: + 1979 .LBE148: + 757:Drivers/BME680/bme680.c **** reg_addr[1] = BME680_GAS_WAIT0_ADDR; + ARM GAS /tmp/ccvbgJts.s page 59 + + + 1980 .loc 1 757 0 + 1981 0198 01AB add r3, sp, #4 + 1982 019a 1870 strb r0, [r3] + 758:Drivers/BME680/bme680.c **** reg_data[1] = calc_heater_dur(dev->gas_sett.heatr_dur); + 1983 .loc 1 758 0 + 1984 019c 6423 movs r3, #100 + 1985 019e 6A46 mov r2, sp + 1986 01a0 5370 strb r3, [r2, #1] + 759:Drivers/BME680/bme680.c **** dev->gas_sett.nb_conv = 0; + 1987 .loc 1 759 0 + 1988 01a2 223B subs r3, r3, #34 + 1989 01a4 E35A ldrh r3, [r4, r3] + 1990 .LVL232: + 1991 .LBB150: + 1992 .LBB151: + 964:Drivers/BME680/bme680.c **** durval = 0xff; /* Max duration*/ + 1993 .loc 1 964 0 + 1994 01a6 A74A ldr r2, .L166+4 + 1995 01a8 9342 cmp r3, r2 + 1996 01aa 16D8 bhi .L154 + 961:Drivers/BME680/bme680.c **** uint8_t durval; + 1997 .loc 1 961 0 + 1998 01ac 0022 movs r2, #0 + 1999 01ae 02E0 b .L118 + 2000 .LVL233: + 2001 .L119: + 968:Drivers/BME680/bme680.c **** factor += 1; + 2002 .loc 1 968 0 + 2003 01b0 9B08 lsrs r3, r3, #2 + 2004 .LVL234: + 969:Drivers/BME680/bme680.c **** } + 2005 .loc 1 969 0 + 2006 01b2 0132 adds r2, r2, #1 + 2007 .LVL235: + 2008 01b4 D2B2 uxtb r2, r2 + 2009 .LVL236: + 2010 .L118: + 967:Drivers/BME680/bme680.c **** dur = dur / 4; + 2011 .loc 1 967 0 + 2012 01b6 3F2B cmp r3, #63 + 2013 01b8 FAD8 bhi .L119 + 971:Drivers/BME680/bme680.c **** } + 2014 .loc 1 971 0 + 2015 01ba DBB2 uxtb r3, r3 + 2016 .LVL237: + 2017 01bc 9201 lsls r2, r2, #6 + 2018 .LVL238: + 2019 01be D2B2 uxtb r2, r2 + 2020 01c0 9B18 adds r3, r3, r2 + 2021 01c2 DBB2 uxtb r3, r3 + 2022 .LVL239: + 2023 .L117: + 2024 .LBE151: + 2025 .LBE150: + 759:Drivers/BME680/bme680.c **** dev->gas_sett.nb_conv = 0; + 2026 .loc 1 759 0 + 2027 01c4 01A9 add r1, sp, #4 + ARM GAS /tmp/ccvbgJts.s page 60 + + + 2028 01c6 4B70 strb r3, [r1, #1] + 760:Drivers/BME680/bme680.c **** } else { + 2029 .loc 1 760 0 + 2030 01c8 3C23 movs r3, #60 + 2031 01ca 0022 movs r2, #0 + 2032 01cc E254 strb r2, [r4, r3] + 2033 .LVL240: + 765:Drivers/BME680/bme680.c **** } + 2034 .loc 1 765 0 + 2035 01ce 2300 movs r3, r4 + 2036 01d0 0232 adds r2, r2, #2 + 2037 01d2 6846 mov r0, sp + 2038 01d4 FFF7FEFF bl bme680_set_regs + 2039 .LVL241: + 2040 01d8 3DE7 b .L113 + 2041 .LVL242: + 2042 .L154: + 2043 .LBB153: + 2044 .LBB152: + 965:Drivers/BME680/bme680.c **** } else { + 2045 .loc 1 965 0 + 2046 01da FF23 movs r3, #255 + 2047 .LVL243: + 2048 01dc F2E7 b .L117 + 2049 .LVL244: + 2050 .L147: + 2051 .LBE152: + 2052 .LBE153: + 2053 .LBE147: + 2054 .LBB154: + 2055 .LBB146: +1131:Drivers/BME680/bme680.c **** } else { + 2056 .loc 1 1131 0 + 2057 01de 0120 movs r0, #1 + 2058 01e0 4042 rsbs r0, r0, #0 + 2059 01e2 38E7 b .L113 + 2060 .L148: + 2061 01e4 0120 movs r0, #1 + 2062 01e6 4042 rsbs r0, r0, #0 + 2063 01e8 35E7 b .L113 + 2064 .L149: + 2065 01ea 0120 movs r0, #1 + 2066 01ec 4042 rsbs r0, r0, #0 + 2067 01ee 32E7 b .L113 + 2068 .L150: + 2069 01f0 0120 movs r0, #1 + 2070 01f2 4042 rsbs r0, r0, #0 + 2071 .LVL245: + 2072 01f4 2FE7 b .L113 + 2073 .LVL246: + 2074 .L163: + 2075 .LBE146: + 2076 .LBE154: + 2077 .LBE143: + 2078 .LBE142: + 380:Drivers/BME680/bme680.c **** + 2079 .loc 1 380 0 + ARM GAS /tmp/ccvbgJts.s page 61 + + + 2080 01f6 2000 movs r0, r4 + 2081 .LVL247: + 2082 01f8 FFF7FEFF bl bme680_set_sensor_mode + 2083 .LVL248: + 2084 01fc 31E7 b .L120 + 2085 .LVL249: + 2086 .L156: + 2087 .LBB155: + 2088 .LBB141: +1115:Drivers/BME680/bme680.c **** } + 2089 .loc 1 1115 0 + 2090 01fe 0120 movs r0, #1 + 2091 .LVL250: + 2092 0200 4042 rsbs r0, r0, #0 + 2093 0202 48E7 b .L122 + 2094 .LVL251: + 2095 .L155: + 2096 .LBE141: + 2097 .LBE155: + 367:Drivers/BME680/bme680.c **** uint8_t reg_array[BME680_REG_BUFFER_LENGTH] = { 0 }; + 2098 .loc 1 367 0 + 2099 0204 0025 movs r5, #0 + 2100 .LVL252: + 2101 .L121: + 399:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->gas_sett.heatr_ctrl, BME680_ENABLE_HEATER, + 2102 .loc 1 399 0 + 2103 0206 B306 lsls r3, r6, #26 + 2104 0208 2CD5 bpl .L124 + 2105 .LVL253: + 2106 .LBB156: + 2107 .LBB157: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 2108 .loc 1 1101 0 + 2109 020a 2300 movs r3, r4 + 2110 020c 3D33 adds r3, r3, #61 + 2111 020e 00D1 bne .LCB2366 + 2112 0210 F3E0 b .L157 @long jump + 2113 .LCB2366: +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 2114 .loc 1 1103 0 + 2115 0212 3D23 movs r3, #61 + 2116 0214 E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 2117 .loc 1 1109 0 + 2118 0216 082B cmp r3, #8 + 2119 0218 07D9 bls .L126 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 2120 .loc 1 1111 0 + 2121 021a 3D23 movs r3, #61 + 2122 021c 0822 movs r2, #8 + 2123 021e E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 2124 .loc 1 1112 0 + 2125 0220 3E32 adds r2, r2, #62 + 2126 0222 A35C ldrb r3, [r4, r2] + 2127 0224 0221 movs r1, #2 + 2128 0226 0B43 orrs r3, r1 + ARM GAS /tmp/ccvbgJts.s page 62 + + + 2129 0228 A354 strb r3, [r4, r2] + 2130 .LVL254: + 2131 .L126: + 2132 .LBE157: + 2133 .LBE156: + 405:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_HCTRL, dev->gas_sett.heatr_ctrl); + 2134 .loc 1 405 0 + 2135 022a 2300 movs r3, r4 + 2136 022c 0122 movs r2, #1 + 2137 022e 1721 movs r1, #23 + 2138 0230 6944 add r1, r1, sp + 2139 0232 7020 movs r0, #112 + 2140 0234 FFF7FEFF bl bme680_get_regs + 2141 .LVL255: + 2142 .L125: + 406:Drivers/BME680/bme680.c **** + 2143 .loc 1 406 0 + 2144 0238 1722 movs r2, #23 + 2145 023a 6A44 add r2, r2, sp + 2146 023c 1378 ldrb r3, [r2] + 2147 023e 0821 movs r1, #8 + 2148 0240 8B43 bics r3, r1 + 2149 0242 5BB2 sxtb r3, r3 + 2150 0244 3531 adds r1, r1, #53 + 2151 0246 6156 ldrsb r1, [r4, r1] + 2152 0248 8C46 mov ip, r1 + 2153 024a 0821 movs r1, #8 + 2154 024c 6746 mov r7, ip + 2155 024e 3940 ands r1, r7 + 2156 0250 0B43 orrs r3, r1 + 2157 0252 DBB2 uxtb r3, r3 + 2158 0254 1370 strb r3, [r2] + 408:Drivers/BME680/bme680.c **** data_array[count] = data; + 2159 .loc 1 408 0 + 2160 0256 04AA add r2, sp, #16 + 2161 0258 7021 movs r1, #112 + 2162 025a 5155 strb r1, [r2, r5] + 409:Drivers/BME680/bme680.c **** count++; + 2163 .loc 1 409 0 + 2164 025c 02AA add r2, sp, #8 + 2165 025e 5355 strb r3, [r2, r5] + 410:Drivers/BME680/bme680.c **** } + 2166 .loc 1 410 0 + 2167 0260 0135 adds r5, r5, #1 + 2168 .LVL256: + 2169 0262 EDB2 uxtb r5, r5 + 2170 .LVL257: + 2171 .L124: + 414:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.os_temp, BME680_OS_NONE, BME680_OS_16X, dev); + 2172 .loc 1 414 0 + 2173 0264 B307 lsls r3, r6, #30 + 2174 0266 3DD0 beq .L127 + 2175 .LVL258: + 2176 .LBB159: + 2177 .LBB160: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 2178 .loc 1 1101 0 + ARM GAS /tmp/ccvbgJts.s page 63 + + + 2179 0268 2300 movs r3, r4 + 2180 026a 3933 adds r3, r3, #57 + 2181 026c 00D1 bne .LCB2453 + 2182 026e C7E0 b .L158 @long jump + 2183 .LCB2453: +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 2184 .loc 1 1103 0 + 2185 0270 3923 movs r3, #57 + 2186 0272 E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 2187 .loc 1 1109 0 + 2188 0274 052B cmp r3, #5 + 2189 0276 07D9 bls .L129 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 2190 .loc 1 1111 0 + 2191 0278 3923 movs r3, #57 + 2192 027a 0522 movs r2, #5 + 2193 027c E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 2194 .loc 1 1112 0 + 2195 027e 4132 adds r2, r2, #65 + 2196 0280 A35C ldrb r3, [r4, r2] + 2197 0282 0221 movs r1, #2 + 2198 0284 0B43 orrs r3, r1 + 2199 0286 A354 strb r3, [r4, r2] + 2200 .LVL259: + 2201 .L129: + 2202 .LBE160: + 2203 .LBE159: + 419:Drivers/BME680/bme680.c **** + 2204 .loc 1 419 0 + 2205 0288 2300 movs r3, r4 + 2206 028a 0122 movs r2, #1 + 2207 028c 1721 movs r1, #23 + 2208 028e 6944 add r1, r1, sp + 2209 0290 7420 movs r0, #116 + 2210 0292 FFF7FEFF bl bme680_get_regs + 2211 .LVL260: + 2212 .L128: + 421:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_OST, dev->tph_sett.os_temp); + 2213 .loc 1 421 0 + 2214 0296 F307 lsls r3, r6, #31 + 2215 0298 09D5 bpl .L130 + 422:Drivers/BME680/bme680.c **** + 2216 .loc 1 422 0 + 2217 029a 1722 movs r2, #23 + 2218 029c 6A44 add r2, r2, sp + 2219 029e 1178 ldrb r1, [r2] + 2220 02a0 1F23 movs r3, #31 + 2221 02a2 0B40 ands r3, r1 + 2222 02a4 3921 movs r1, #57 + 2223 02a6 615C ldrb r1, [r4, r1] + 2224 02a8 4901 lsls r1, r1, #5 + 2225 02aa 0B43 orrs r3, r1 + 2226 02ac 1370 strb r3, [r2] + 2227 .L130: + 424:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_OSP, dev->tph_sett.os_pres); + ARM GAS /tmp/ccvbgJts.s page 64 + + + 2228 .loc 1 424 0 + 2229 02ae B307 lsls r3, r6, #30 + 2230 02b0 0ED5 bpl .L131 + 425:Drivers/BME680/bme680.c **** + 2231 .loc 1 425 0 + 2232 02b2 1722 movs r2, #23 + 2233 02b4 6A44 add r2, r2, sp + 2234 02b6 1378 ldrb r3, [r2] + 2235 02b8 1C21 movs r1, #28 + 2236 02ba 8B43 bics r3, r1 + 2237 02bc 5BB2 sxtb r3, r3 + 2238 02be 1E31 adds r1, r1, #30 + 2239 02c0 615C ldrb r1, [r4, r1] + 2240 02c2 8900 lsls r1, r1, #2 + 2241 02c4 8C46 mov ip, r1 + 2242 02c6 1C21 movs r1, #28 + 2243 02c8 6746 mov r7, ip + 2244 02ca 3940 ands r1, r7 + 2245 02cc 0B43 orrs r3, r1 + 2246 02ce 1370 strb r3, [r2] + 2247 .L131: + 427:Drivers/BME680/bme680.c **** data_array[count] = data; + 2248 .loc 1 427 0 + 2249 02d0 04AB add r3, sp, #16 + 2250 02d2 7422 movs r2, #116 + 2251 02d4 5A55 strb r2, [r3, r5] + 428:Drivers/BME680/bme680.c **** count++; + 2252 .loc 1 428 0 + 2253 02d6 1723 movs r3, #23 + 2254 02d8 6B44 add r3, r3, sp + 2255 02da 1A78 ldrb r2, [r3] + 2256 02dc 02AB add r3, sp, #8 + 2257 02de 5A55 strb r2, [r3, r5] + 429:Drivers/BME680/bme680.c **** } + 2258 .loc 1 429 0 + 2259 02e0 0135 adds r5, r5, #1 + 2260 .LVL261: + 2261 02e2 EDB2 uxtb r5, r5 + 2262 .LVL262: + 2263 .L127: + 433:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->tph_sett.os_hum, BME680_OS_NONE, BME680_OS_16X, dev); + 2264 .loc 1 433 0 + 2265 02e4 7307 lsls r3, r6, #29 + 2266 02e6 2CD5 bpl .L132 + 2267 .LVL263: + 2268 .LBB162: + 2269 .LBB163: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 2270 .loc 1 1101 0 + 2271 02e8 2300 movs r3, r4 + 2272 02ea 3833 adds r3, r3, #56 + 2273 02ec 00D1 bne .LCB2572 + 2274 02ee 8AE0 b .L159 @long jump + 2275 .LCB2572: +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 2276 .loc 1 1103 0 + 2277 02f0 3823 movs r3, #56 + ARM GAS /tmp/ccvbgJts.s page 65 + + + 2278 02f2 E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 2279 .loc 1 1109 0 + 2280 02f4 052B cmp r3, #5 + 2281 02f6 07D9 bls .L134 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 2282 .loc 1 1111 0 + 2283 02f8 3823 movs r3, #56 + 2284 02fa 0522 movs r2, #5 + 2285 02fc E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 2286 .loc 1 1112 0 + 2287 02fe 4132 adds r2, r2, #65 + 2288 0300 A35C ldrb r3, [r4, r2] + 2289 0302 0221 movs r1, #2 + 2290 0304 0B43 orrs r3, r1 + 2291 0306 A354 strb r3, [r4, r2] + 2292 .LVL264: + 2293 .L134: + 2294 .LBE163: + 2295 .LBE162: + 438:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_OSH, dev->tph_sett.os_hum); + 2296 .loc 1 438 0 + 2297 0308 2300 movs r3, r4 + 2298 030a 0122 movs r2, #1 + 2299 030c 1721 movs r1, #23 + 2300 030e 6944 add r1, r1, sp + 2301 0310 7220 movs r0, #114 + 2302 0312 FFF7FEFF bl bme680_get_regs + 2303 .LVL265: + 2304 .L133: + 439:Drivers/BME680/bme680.c **** + 2305 .loc 1 439 0 + 2306 0316 1722 movs r2, #23 + 2307 0318 6A44 add r2, r2, sp + 2308 031a 1378 ldrb r3, [r2] + 2309 031c 0721 movs r1, #7 + 2310 031e 8B43 bics r3, r1 + 2311 0320 5BB2 sxtb r3, r3 + 2312 0322 3131 adds r1, r1, #49 + 2313 0324 6156 ldrsb r1, [r4, r1] + 2314 0326 8C46 mov ip, r1 + 2315 0328 0721 movs r1, #7 + 2316 032a 6746 mov r7, ip + 2317 032c 3940 ands r1, r7 + 2318 032e 0B43 orrs r3, r1 + 2319 0330 DBB2 uxtb r3, r3 + 2320 0332 1370 strb r3, [r2] + 441:Drivers/BME680/bme680.c **** data_array[count] = data; + 2321 .loc 1 441 0 + 2322 0334 04AA add r2, sp, #16 + 2323 0336 7221 movs r1, #114 + 2324 0338 5155 strb r1, [r2, r5] + 442:Drivers/BME680/bme680.c **** count++; + 2325 .loc 1 442 0 + 2326 033a 02AA add r2, sp, #8 + 2327 033c 5355 strb r3, [r2, r5] + ARM GAS /tmp/ccvbgJts.s page 66 + + + 443:Drivers/BME680/bme680.c **** } + 2328 .loc 1 443 0 + 2329 033e 0135 adds r5, r5, #1 + 2330 .LVL266: + 2331 0340 EDB2 uxtb r5, r5 + 2332 .LVL267: + 2333 .L132: + 447:Drivers/BME680/bme680.c **** rslt = boundary_check(&dev->gas_sett.run_gas, BME680_RUN_GAS_DISABLE, + 2334 .loc 1 447 0 + 2335 0342 C023 movs r3, #192 + 2336 0344 3342 tst r3, r6 + 2337 0346 4DD0 beq .L135 + 2338 .LVL268: + 2339 .LBB165: + 2340 .LBB166: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 2341 .loc 1 1101 0 + 2342 0348 2300 movs r3, r4 + 2343 034a 3E33 adds r3, r3, #62 + 2344 034c 5ED0 beq .L160 +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 2345 .loc 1 1103 0 + 2346 034e 3E23 movs r3, #62 + 2347 0350 E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 2348 .loc 1 1109 0 + 2349 0352 012B cmp r3, #1 + 2350 0354 07D9 bls .L137 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 2351 .loc 1 1111 0 + 2352 0356 3E23 movs r3, #62 + 2353 0358 0122 movs r2, #1 + 2354 035a E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 2355 .loc 1 1112 0 + 2356 035c 4532 adds r2, r2, #69 + 2357 035e A35C ldrb r3, [r4, r2] + 2358 0360 0221 movs r1, #2 + 2359 0362 0B43 orrs r3, r1 + 2360 0364 A354 strb r3, [r4, r2] + 2361 .LVL269: + 2362 .L137: + 2363 .LBE166: + 2364 .LBE165: + 2365 .LBB168: + 2366 .LBB169: +1101:Drivers/BME680/bme680.c **** /* Check if value is below minimum value */ + 2367 .loc 1 1101 0 + 2368 0366 2300 movs r3, r4 + 2369 0368 3C33 adds r3, r3, #60 + 2370 036a 52D0 beq .L161 +1103:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to minimum value */ + 2371 .loc 1 1103 0 + 2372 036c 3C23 movs r3, #60 + 2373 036e E35C ldrb r3, [r4, r3] +1109:Drivers/BME680/bme680.c **** /* Auto correct the invalid value to maximum value */ + 2374 .loc 1 1109 0 + ARM GAS /tmp/ccvbgJts.s page 67 + + + 2375 0370 0A2B cmp r3, #10 + 2376 0372 07D9 bls .L138 +1111:Drivers/BME680/bme680.c **** dev->info_msg |= BME680_I_MAX_CORRECTION; + 2377 .loc 1 1111 0 + 2378 0374 3C23 movs r3, #60 + 2379 0376 0A22 movs r2, #10 + 2380 0378 E254 strb r2, [r4, r3] +1112:Drivers/BME680/bme680.c **** } + 2381 .loc 1 1112 0 + 2382 037a 3C32 adds r2, r2, #60 + 2383 037c A35C ldrb r3, [r4, r2] + 2384 037e 0221 movs r1, #2 + 2385 0380 0B43 orrs r3, r1 + 2386 0382 A354 strb r3, [r4, r2] + 2387 .LVL270: + 2388 .L138: + 2389 .LBE169: + 2390 .LBE168: + 459:Drivers/BME680/bme680.c **** + 2391 .loc 1 459 0 + 2392 0384 2300 movs r3, r4 + 2393 0386 0122 movs r2, #1 + 2394 0388 1721 movs r1, #23 + 2395 038a 6944 add r1, r1, sp + 2396 038c 7120 movs r0, #113 + 2397 038e FFF7FEFF bl bme680_get_regs + 2398 .LVL271: + 2399 .L136: + 461:Drivers/BME680/bme680.c **** data = BME680_SET_BITS(data, BME680_RUN_GAS, dev->gas_sett.run_gas); + 2400 .loc 1 461 0 + 2401 0392 7306 lsls r3, r6, #25 + 2402 0394 0ED5 bpl .L139 + 462:Drivers/BME680/bme680.c **** + 2403 .loc 1 462 0 + 2404 0396 1722 movs r2, #23 + 2405 0398 6A44 add r2, r2, sp + 2406 039a 1378 ldrb r3, [r2] + 2407 039c 1021 movs r1, #16 + 2408 039e 8B43 bics r3, r1 + 2409 03a0 5BB2 sxtb r3, r3 + 2410 03a2 2E31 adds r1, r1, #46 + 2411 03a4 615C ldrb r1, [r4, r1] + 2412 03a6 0901 lsls r1, r1, #4 + 2413 03a8 8C46 mov ip, r1 + 2414 03aa 1021 movs r1, #16 + 2415 03ac 6746 mov r7, ip + 2416 03ae 3940 ands r1, r7 + 2417 03b0 0B43 orrs r3, r1 + 2418 03b2 1370 strb r3, [r2] + 2419 .L139: + 464:Drivers/BME680/bme680.c **** data = BME680_SET_BITS_POS_0(data, BME680_NBCONV, dev->gas_sett.nb_conv); + 2420 .loc 1 464 0 + 2421 03b4 3306 lsls r3, r6, #24 + 2422 03b6 0BD5 bpl .L140 + 465:Drivers/BME680/bme680.c **** + 2423 .loc 1 465 0 + 2424 03b8 1722 movs r2, #23 + ARM GAS /tmp/ccvbgJts.s page 68 + + + 2425 03ba 6A44 add r2, r2, sp + 2426 03bc 1378 ldrb r3, [r2] + 2427 03be 0F21 movs r1, #15 + 2428 03c0 8B43 bics r3, r1 + 2429 03c2 5BB2 sxtb r3, r3 + 2430 03c4 2D31 adds r1, r1, #45 + 2431 03c6 6656 ldrsb r6, [r4, r1] + 2432 03c8 2D39 subs r1, r1, #45 + 2433 03ca 3140 ands r1, r6 + 2434 03cc 0B43 orrs r3, r1 + 2435 03ce 1370 strb r3, [r2] + 2436 .L140: + 467:Drivers/BME680/bme680.c **** data_array[count] = data; + 2437 .loc 1 467 0 + 2438 03d0 04AB add r3, sp, #16 + 2439 03d2 7122 movs r2, #113 + 2440 03d4 5A55 strb r2, [r3, r5] + 468:Drivers/BME680/bme680.c **** count++; + 2441 .loc 1 468 0 + 2442 03d6 1723 movs r3, #23 + 2443 03d8 6B44 add r3, r3, sp + 2444 03da 1A78 ldrb r2, [r3] + 2445 03dc 02AB add r3, sp, #8 + 2446 03de 5A55 strb r2, [r3, r5] + 469:Drivers/BME680/bme680.c **** } + 2447 .loc 1 469 0 + 2448 03e0 0135 adds r5, r5, #1 + 2449 .LVL272: + 2450 03e2 EDB2 uxtb r5, r5 + 2451 .LVL273: + 2452 .L135: + 472:Drivers/BME680/bme680.c **** rslt = bme680_set_regs(reg_array, data_array, count, dev); + 2453 .loc 1 472 0 + 2454 03e4 0028 cmp r0, #0 + 2455 03e6 17D0 beq .L165 + 2456 .LVL274: + 2457 .L141: + 476:Drivers/BME680/bme680.c **** } + 2458 .loc 1 476 0 + 2459 03e8 4423 movs r3, #68 + 2460 03ea 5246 mov r2, r10 + 2461 03ec E254 strb r2, [r4, r3] + 2462 .LVL275: + 2463 .L112: + 480:Drivers/BME680/bme680.c **** + 2464 .loc 1 480 0 + 2465 03ee 06B0 add sp, sp, #24 + 2466 @ sp needed + 2467 .LVL276: + 2468 .LVL277: + 2469 03f0 1CBC pop {r2, r3, r4} + 2470 03f2 9046 mov r8, r2 + 2471 03f4 9946 mov r9, r3 + 2472 03f6 A246 mov r10, r4 + 2473 03f8 F0BD pop {r4, r5, r6, r7, pc} + 2474 .LVL278: + 2475 .L157: + ARM GAS /tmp/ccvbgJts.s page 69 + + + 2476 .LBB171: + 2477 .LBB158: +1115:Drivers/BME680/bme680.c **** } + 2478 .loc 1 1115 0 + 2479 03fa 0120 movs r0, #1 + 2480 .LVL279: + 2481 03fc 4042 rsbs r0, r0, #0 + 2482 03fe 1BE7 b .L125 + 2483 .LVL280: + 2484 .L158: + 2485 .LBE158: + 2486 .LBE171: + 2487 .LBB172: + 2488 .LBB161: + 2489 0400 0120 movs r0, #1 + 2490 .LVL281: + 2491 0402 4042 rsbs r0, r0, #0 + 2492 0404 47E7 b .L128 + 2493 .LVL282: + 2494 .L159: + 2495 .LBE161: + 2496 .LBE172: + 2497 .LBB173: + 2498 .LBB164: + 2499 0406 0120 movs r0, #1 + 2500 .LVL283: + 2501 0408 4042 rsbs r0, r0, #0 + 2502 040a 84E7 b .L133 + 2503 .LVL284: + 2504 .L160: + 2505 .LBE164: + 2506 .LBE173: + 2507 .LBB174: + 2508 .LBB167: + 2509 040c 0120 movs r0, #1 + 2510 .LVL285: + 2511 040e 4042 rsbs r0, r0, #0 + 2512 0410 BFE7 b .L136 + 2513 .LVL286: + 2514 .L161: + 2515 .LBE167: + 2516 .LBE174: + 2517 .LBB175: + 2518 .LBB170: + 2519 0412 0120 movs r0, #1 + 2520 0414 4042 rsbs r0, r0, #0 + 2521 0416 BCE7 b .L136 + 2522 .LVL287: + 2523 .L165: + 2524 .LBE170: + 2525 .LBE175: + 473:Drivers/BME680/bme680.c **** + 2526 .loc 1 473 0 + 2527 0418 2300 movs r3, r4 + 2528 041a 2A00 movs r2, r5 + 2529 041c 02A9 add r1, sp, #8 + 2530 041e 04A8 add r0, sp, #16 + ARM GAS /tmp/ccvbgJts.s page 70 + + + 2531 .LVL288: + 2532 0420 FFF7FEFF bl bme680_set_regs + 2533 .LVL289: + 2534 0424 E0E7 b .L141 + 2535 .LVL290: + 2536 .L142: + 2537 .LBB176: + 2538 .LBB137: +1131:Drivers/BME680/bme680.c **** } else { + 2539 .loc 1 1131 0 + 2540 0426 0120 movs r0, #1 + 2541 0428 4042 rsbs r0, r0, #0 + 2542 042a E0E7 b .L112 + 2543 .L143: + 2544 042c 0120 movs r0, #1 + 2545 042e 4042 rsbs r0, r0, #0 + 2546 0430 DDE7 b .L112 + 2547 .L144: + 2548 0432 0120 movs r0, #1 + 2549 0434 4042 rsbs r0, r0, #0 + 2550 0436 DAE7 b .L112 + 2551 .L145: + 2552 0438 0120 movs r0, #1 + 2553 043a 4042 rsbs r0, r0, #0 + 2554 043c D7E7 b .L112 + 2555 .L167: + 2556 043e C046 .align 2 + 2557 .L166: + 2558 0440 99590200 .word 154009 + 2559 0444 BF0F0000 .word 4031 + 2560 .LBE137: + 2561 .LBE176: + 2562 .cfi_endproc + 2563 .LFE4: + 2565 .section .text.bme680_get_sensor_mode,"ax",%progbits + 2566 .align 1 + 2567 .global bme680_get_sensor_mode + 2568 .syntax unified + 2569 .code 16 + 2570 .thumb_func + 2571 .fpu softvfp + 2573 bme680_get_sensor_mode: + 2574 .LFB7: + 578:Drivers/BME680/bme680.c **** int8_t rslt; + 2575 .loc 1 578 0 + 2576 .cfi_startproc + 2577 @ args = 0, pretend = 0, frame = 8 + 2578 @ frame_needed = 0, uses_anonymous_args = 0 + 2579 .LVL291: + 2580 0000 30B5 push {r4, r5, lr} + 2581 .LCFI20: + 2582 .cfi_def_cfa_offset 12 + 2583 .cfi_offset 4, -12 + 2584 .cfi_offset 5, -8 + 2585 .cfi_offset 14, -4 + 2586 0002 83B0 sub sp, sp, #12 + 2587 .LCFI21: + ARM GAS /tmp/ccvbgJts.s page 71 + + + 2588 .cfi_def_cfa_offset 24 + 2589 0004 041E subs r4, r0, #0 + 2590 .LVL292: + 2591 .LBB177: + 2592 .LBB178: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 2593 .loc 1 1129 0 + 2594 0006 17D0 beq .L170 + 2595 0008 836C ldr r3, [r0, #72] + 2596 000a 002B cmp r3, #0 + 2597 000c 17D0 beq .L171 + 2598 000e C36C ldr r3, [r0, #76] + 2599 0010 002B cmp r3, #0 + 2600 0012 17D0 beq .L172 + 2601 0014 036D ldr r3, [r0, #80] + 2602 0016 002B cmp r3, #0 + 2603 0018 17D0 beq .L173 + 2604 .LVL293: + 2605 .LBE178: + 2606 .LBE177: + 585:Drivers/BME680/bme680.c **** /* Masking the other register bit info*/ + 2607 .loc 1 585 0 + 2608 001a 6B46 mov r3, sp + 2609 001c DD1D adds r5, r3, #7 + 2610 001e 0300 movs r3, r0 + 2611 0020 0122 movs r2, #1 + 2612 0022 2900 movs r1, r5 + 2613 0024 7420 movs r0, #116 + 2614 .LVL294: + 2615 0026 FFF7FEFF bl bme680_get_regs + 2616 .LVL295: + 587:Drivers/BME680/bme680.c **** } + 2617 .loc 1 587 0 + 2618 002a 2A78 ldrb r2, [r5] + 2619 002c 0323 movs r3, #3 + 2620 002e 1340 ands r3, r2 + 2621 0030 4422 movs r2, #68 + 2622 0032 A354 strb r3, [r4, r2] + 2623 .LVL296: + 2624 .L169: + 591:Drivers/BME680/bme680.c **** + 2625 .loc 1 591 0 + 2626 0034 03B0 add sp, sp, #12 + 2627 @ sp needed + 2628 .LVL297: + 2629 0036 30BD pop {r4, r5, pc} + 2630 .LVL298: + 2631 .L170: + 2632 .LBB180: + 2633 .LBB179: +1131:Drivers/BME680/bme680.c **** } else { + 2634 .loc 1 1131 0 + 2635 0038 0120 movs r0, #1 + 2636 .LVL299: + 2637 003a 4042 rsbs r0, r0, #0 + 2638 003c FAE7 b .L169 + 2639 .LVL300: + ARM GAS /tmp/ccvbgJts.s page 72 + + + 2640 .L171: + 2641 003e 0120 movs r0, #1 + 2642 .LVL301: + 2643 0040 4042 rsbs r0, r0, #0 + 2644 0042 F7E7 b .L169 + 2645 .LVL302: + 2646 .L172: + 2647 0044 0120 movs r0, #1 + 2648 .LVL303: + 2649 0046 4042 rsbs r0, r0, #0 + 2650 0048 F4E7 b .L169 + 2651 .LVL304: + 2652 .L173: + 2653 004a 0120 movs r0, #1 + 2654 .LVL305: + 2655 004c 4042 rsbs r0, r0, #0 + 2656 004e F1E7 b .L169 + 2657 .LBE179: + 2658 .LBE180: + 2659 .cfi_endproc + 2660 .LFE7: + 2662 .global __aeabi_uidiv + 2663 .section .text.bme680_set_profile_dur,"ax",%progbits + 2664 .align 1 + 2665 .global bme680_set_profile_dur + 2666 .syntax unified + 2667 .code 16 + 2668 .thumb_func + 2669 .fpu softvfp + 2671 bme680_set_profile_dur: + 2672 .LFB8: + 597:Drivers/BME680/bme680.c **** uint32_t tph_dur; /* Calculate in us */ + 2673 .loc 1 597 0 + 2674 .cfi_startproc + 2675 @ args = 0, pretend = 0, frame = 0 + 2676 @ frame_needed = 0, uses_anonymous_args = 0 + 2677 .LVL306: + 2678 0000 70B5 push {r4, r5, r6, lr} + 2679 .LCFI22: + 2680 .cfi_def_cfa_offset 16 + 2681 .cfi_offset 4, -16 + 2682 .cfi_offset 5, -12 + 2683 .cfi_offset 6, -8 + 2684 .cfi_offset 14, -4 + 2685 0002 0500 movs r5, r0 + 2686 0004 0C00 movs r4, r1 + 601:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + 2687 .loc 1 601 0 + 2688 0006 3923 movs r3, #57 + 2689 0008 C85C ldrb r0, [r1, r3] + 2690 .LVL307: + 2691 000a 0133 adds r3, r3, #1 + 2692 000c CB5C ldrb r3, [r1, r3] + 2693 000e C018 adds r0, r0, r3 + 2694 0010 3823 movs r3, #56 + 2695 0012 CB5C ldrb r3, [r1, r3] + 2696 0014 C318 adds r3, r0, r3 + ARM GAS /tmp/ccvbgJts.s page 73 + + + 2697 0016 0748 ldr r0, .L175 + 2698 0018 5843 muls r0, r3 + 2699 .LVL308: + 604:Drivers/BME680/bme680.c **** tph_dur /= UINT32_C(1000); /* Convert to ms */ + 2700 .loc 1 604 0 + 2701 001a 074B ldr r3, .L175+4 + 2702 001c 9C46 mov ip, r3 + 2703 001e 6044 add r0, r0, ip + 2704 .LVL309: + 605:Drivers/BME680/bme680.c **** + 2705 .loc 1 605 0 + 2706 0020 FA21 movs r1, #250 + 2707 .LVL310: + 2708 0022 8900 lsls r1, r1, #2 + 2709 0024 FFF7FEFF bl __aeabi_uidiv + 2710 .LVL311: + 607:Drivers/BME680/bme680.c **** /* The remaining time should be used for heating */ + 2711 .loc 1 607 0 + 2712 0028 0130 adds r0, r0, #1 + 2713 .LVL312: + 609:Drivers/BME680/bme680.c **** } + 2714 .loc 1 609 0 + 2715 002a 80B2 uxth r0, r0 + 2716 .LVL313: + 2717 002c 281A subs r0, r5, r0 + 2718 002e 4223 movs r3, #66 + 2719 0030 E052 strh r0, [r4, r3] + 610:Drivers/BME680/bme680.c **** + 2720 .loc 1 610 0 + 2721 @ sp needed + 2722 .LVL314: + 2723 0032 70BD pop {r4, r5, r6, pc} + 2724 .L176: + 2725 .align 2 + 2726 .L175: + 2727 0034 AB070000 .word 1963 + 2728 0038 B9120000 .word 4793 + 2729 .cfi_endproc + 2730 .LFE8: + 2732 .section .text.bme680_get_profile_dur,"ax",%progbits + 2733 .align 1 + 2734 .global bme680_get_profile_dur + 2735 .syntax unified + 2736 .code 16 + 2737 .thumb_func + 2738 .fpu softvfp + 2740 bme680_get_profile_dur: + 2741 .LFB9: + 616:Drivers/BME680/bme680.c **** uint32_t tph_dur; /* Calculate in us */ + 2742 .loc 1 616 0 + 2743 .cfi_startproc + 2744 @ args = 0, pretend = 0, frame = 0 + 2745 @ frame_needed = 0, uses_anonymous_args = 0 + 2746 .LVL315: + 2747 0000 70B5 push {r4, r5, r6, lr} + 2748 .LCFI23: + 2749 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccvbgJts.s page 74 + + + 2750 .cfi_offset 4, -16 + 2751 .cfi_offset 5, -12 + 2752 .cfi_offset 6, -8 + 2753 .cfi_offset 14, -4 + 2754 0002 0400 movs r4, r0 + 2755 0004 0D00 movs r5, r1 + 620:Drivers/BME680/bme680.c **** tph_dur += UINT32_C(477 * 4); /* TPH switching duration */ + 2756 .loc 1 620 0 + 2757 0006 3923 movs r3, #57 + 2758 0008 C85C ldrb r0, [r1, r3] + 2759 .LVL316: + 2760 000a 0133 adds r3, r3, #1 + 2761 000c CB5C ldrb r3, [r1, r3] + 2762 000e C018 adds r0, r0, r3 + 2763 0010 3823 movs r3, #56 + 2764 0012 CB5C ldrb r3, [r1, r3] + 2765 0014 C318 adds r3, r0, r3 + 2766 0016 0A48 ldr r0, .L179 + 2767 0018 5843 muls r0, r3 + 2768 .LVL317: + 623:Drivers/BME680/bme680.c **** tph_dur /= UINT32_C(1000); /* Convert to ms */ + 2769 .loc 1 623 0 + 2770 001a 0A4B ldr r3, .L179+4 + 2771 001c 9C46 mov ip, r3 + 2772 001e 6044 add r0, r0, ip + 2773 .LVL318: + 624:Drivers/BME680/bme680.c **** + 2774 .loc 1 624 0 + 2775 0020 FA21 movs r1, #250 + 2776 .LVL319: + 2777 0022 8900 lsls r1, r1, #2 + 2778 0024 FFF7FEFF bl __aeabi_uidiv + 2779 .LVL320: + 626:Drivers/BME680/bme680.c **** + 2780 .loc 1 626 0 + 2781 0028 0130 adds r0, r0, #1 + 2782 .LVL321: + 628:Drivers/BME680/bme680.c **** + 2783 .loc 1 628 0 + 2784 002a 80B2 uxth r0, r0 + 2785 .LVL322: + 2786 002c 2080 strh r0, [r4] + 631:Drivers/BME680/bme680.c **** /* The remaining time should be used for heating */ + 2787 .loc 1 631 0 + 2788 002e 3E23 movs r3, #62 + 2789 0030 EB5C ldrb r3, [r5, r3] + 2790 0032 002B cmp r3, #0 + 2791 0034 03D0 beq .L177 + 633:Drivers/BME680/bme680.c **** } + 2792 .loc 1 633 0 + 2793 0036 4223 movs r3, #66 + 2794 0038 EB5A ldrh r3, [r5, r3] + 2795 003a C018 adds r0, r0, r3 + 2796 003c 2080 strh r0, [r4] + 2797 .L177: + 635:Drivers/BME680/bme680.c **** + 2798 .loc 1 635 0 + ARM GAS /tmp/ccvbgJts.s page 75 + + + 2799 @ sp needed + 2800 .LVL323: + 2801 .LVL324: + 2802 003e 70BD pop {r4, r5, r6, pc} + 2803 .L180: + 2804 .align 2 + 2805 .L179: + 2806 0040 AB070000 .word 1963 + 2807 0044 B9120000 .word 4793 + 2808 .cfi_endproc + 2809 .LFE9: + 2811 .global __aeabi_lmul + 2812 .global __aeabi_ldivmod + 2813 .section .text.bme680_get_sensor_data,"ax",%progbits + 2814 .align 1 + 2815 .global bme680_get_sensor_data + 2816 .syntax unified + 2817 .code 16 + 2818 .thumb_func + 2819 .fpu softvfp + 2821 bme680_get_sensor_data: + 2822 .LFB10: + 643:Drivers/BME680/bme680.c **** int8_t rslt; + 2823 .loc 1 643 0 + 2824 .cfi_startproc + 2825 @ args = 0, pretend = 0, frame = 40 + 2826 @ frame_needed = 0, uses_anonymous_args = 0 + 2827 .LVL325: + 2828 0000 F0B5 push {r4, r5, r6, r7, lr} + 2829 .LCFI24: + 2830 .cfi_def_cfa_offset 20 + 2831 .cfi_offset 4, -20 + 2832 .cfi_offset 5, -16 + 2833 .cfi_offset 6, -12 + 2834 .cfi_offset 7, -8 + 2835 .cfi_offset 14, -4 + 2836 0002 DE46 mov lr, fp + 2837 0004 5746 mov r7, r10 + 2838 0006 4E46 mov r6, r9 + 2839 0008 4546 mov r5, r8 + 2840 000a E0B5 push {r5, r6, r7, lr} + 2841 .LCFI25: + 2842 .cfi_def_cfa_offset 36 + 2843 .cfi_offset 8, -36 + 2844 .cfi_offset 9, -32 + 2845 .cfi_offset 10, -28 + 2846 .cfi_offset 11, -24 + 2847 000c 8BB0 sub sp, sp, #44 + 2848 .LCFI26: + 2849 .cfi_def_cfa_offset 80 + 2850 000e 8146 mov r9, r0 + 2851 0010 0D1E subs r5, r1, #0 + 2852 .LVL326: + 2853 .LBB195: + 2854 .LBB196: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 2855 .loc 1 1129 0 + ARM GAS /tmp/ccvbgJts.s page 76 + + + 2856 0012 00D1 bne .LCB3283 + 2857 0014 C8E1 b .L191 @long jump + 2858 .LCB3283: + 2859 0016 8B6C ldr r3, [r1, #72] + 2860 0018 002B cmp r3, #0 + 2861 001a 00D1 bne .LCB3287 + 2862 001c C8E1 b .L192 @long jump + 2863 .LCB3287: + 2864 001e CB6C ldr r3, [r1, #76] + 2865 0020 002B cmp r3, #0 + 2866 0022 00D1 bne .LCB3291 + 2867 0024 C8E1 b .L193 @long jump + 2868 .LCB3291: + 2869 0026 0B6D ldr r3, [r1, #80] + 2870 0028 002B cmp r3, #0 + 2871 002a 00D1 bne .LCB3295 + 2872 002c C8E1 b .L194 @long jump + 2873 .LCB3295: + 2874 .LVL327: + 2875 .LBE196: + 2876 .LBE195: + 2877 .LBB198: + 2878 .LBB199: + 983:Drivers/BME680/bme680.c **** uint8_t gas_range; + 2879 .loc 1 983 0 + 2880 002e 0F22 movs r2, #15 + 2881 0030 0021 movs r1, #0 + 2882 .LVL328: + 2883 0032 06A8 add r0, sp, #24 + 2884 .LVL329: + 2885 0034 FFF7FEFF bl memset + 2886 .LVL330: + 2887 .LBB200: + 2888 .LBB201: +1129:Drivers/BME680/bme680.c **** /* Device structure pointer is not valid */ + 2889 .loc 1 1129 0 + 2890 0038 002D cmp r5, #0 + 2891 003a 0ED0 beq .L195 + 2892 003c AB6C ldr r3, [r5, #72] + 2893 003e 002B cmp r3, #0 + 2894 0040 12D0 beq .L196 + 2895 0042 EB6C ldr r3, [r5, #76] + 2896 0044 002B cmp r3, #0 + 2897 0046 13D0 beq .L197 + 2898 0048 2B6D ldr r3, [r5, #80] + 2899 004a 002B cmp r3, #0 + 2900 004c 02D0 beq .L202 + 2901 .loc 1 1134 0 + 2902 004e 0023 movs r3, #0 + 2903 0050 0193 str r3, [sp, #4] + 2904 0052 05E0 b .L183 + 2905 .L202: +1131:Drivers/BME680/bme680.c **** } else { + 2906 .loc 1 1131 0 + 2907 0054 013B subs r3, r3, #1 + 2908 0056 0193 str r3, [sp, #4] + 2909 0058 02E0 b .L183 + ARM GAS /tmp/ccvbgJts.s page 77 + + + 2910 .L195: + 2911 005a 0123 movs r3, #1 + 2912 005c 5B42 rsbs r3, r3, #0 + 2913 005e 0193 str r3, [sp, #4] + 2914 .L183: + 2915 .loc 1 1134 0 + 2916 0060 0A24 movs r4, #10 + 2917 0062 019E ldr r6, [sp, #4] + 2918 0064 4F46 mov r7, r9 + 2919 0066 28E1 b .L188 + 2920 .L196: +1131:Drivers/BME680/bme680.c **** } else { + 2921 .loc 1 1131 0 + 2922 0068 0123 movs r3, #1 + 2923 006a 5B42 rsbs r3, r3, #0 + 2924 006c 0193 str r3, [sp, #4] + 2925 006e F7E7 b .L183 + 2926 .L197: + 2927 0070 0123 movs r3, #1 + 2928 0072 5B42 rsbs r3, r3, #0 + 2929 0074 0193 str r3, [sp, #4] + 2930 0076 F3E7 b .L183 + 2931 .LVL331: + 2932 .L204: + 2933 0078 0196 str r6, [sp, #4] + 2934 007a B946 mov r9, r7 + 2935 007c 029F ldr r7, [sp, #8] + 2936 .LVL332: + 2937 .LBE201: + 2938 .LBE200: + 2939 .LBB202: + 2940 .LBB203: + 819:Drivers/BME680/bme680.c **** var2 = (var1 * (int32_t) dev->calib.par_t2) >> 11; + 2941 .loc 1 819 0 + 2942 007e C010 asrs r0, r0, #3 + 2943 .LVL333: + 2944 0080 EB8A ldrh r3, [r5, #22] + 2945 0082 5B00 lsls r3, r3, #1 + 2946 0084 C01A subs r0, r0, r3 + 2947 0086 C117 asrs r1, r0, #31 + 2948 .LVL334: + 820:Drivers/BME680/bme680.c **** var3 = ((var1 >> 1) * (var1 >> 1)) >> 12; + 2949 .loc 1 820 0 + 2950 0088 1823 movs r3, #24 + 2951 008a EA5E ldrsh r2, [r5, r3] + 2952 008c D317 asrs r3, r2, #31 + 2953 008e 0290 str r0, [sp, #8] + 2954 .LVL335: + 2955 0090 0491 str r1, [sp, #16] + 2956 0092 FFF7FEFF bl __aeabi_lmul + 2957 .LVL336: + 2958 0096 4905 lsls r1, r1, #21 + 2959 0098 C60A lsrs r6, r0, #11 + 2960 .LVL337: + 2961 009a 0E43 orrs r6, r1 + 2962 .LVL338: + 821:Drivers/BME680/bme680.c **** var3 = ((var3) * ((int32_t) dev->calib.par_t3 << 4)) >> 14; + ARM GAS /tmp/ccvbgJts.s page 78 + + + 2963 .loc 1 821 0 + 2964 009c 0499 ldr r1, [sp, #16] + 2965 009e CB07 lsls r3, r1, #31 + 2966 00a0 0298 ldr r0, [sp, #8] + 2967 00a2 4008 lsrs r0, r0, #1 + 2968 00a4 1843 orrs r0, r3 + 2969 00a6 0200 movs r2, r0 + 2970 00a8 0B00 movs r3, r1 + 2971 00aa FFF7FEFF bl __aeabi_lmul + 2972 .LVL339: + 2973 00ae 0B05 lsls r3, r1, #20 + 2974 00b0 000B lsrs r0, r0, #12 + 2975 00b2 1843 orrs r0, r3 + 2976 00b4 0913 asrs r1, r1, #12 + 2977 .LVL340: + 822:Drivers/BME680/bme680.c **** dev->calib.t_fine = (int32_t) (var2 + var3); + 2978 .loc 1 822 0 + 2979 00b6 1A22 movs r2, #26 + 2980 00b8 AA56 ldrsb r2, [r5, r2] + 2981 00ba 1201 lsls r2, r2, #4 + 2982 00bc D317 asrs r3, r2, #31 + 2983 00be FFF7FEFF bl __aeabi_lmul + 2984 .LVL341: + 2985 00c2 8904 lsls r1, r1, #18 + 2986 00c4 800B lsrs r0, r0, #14 + 2987 00c6 0843 orrs r0, r1 + 823:Drivers/BME680/bme680.c **** calc_temp = (int16_t) (((dev->calib.t_fine * 5) + 128) >> 8); + 2988 .loc 1 823 0 + 2989 00c8 3018 adds r0, r6, r0 + 2990 00ca 2863 str r0, [r5, #48] + 824:Drivers/BME680/bme680.c **** + 2991 .loc 1 824 0 + 2992 00cc 8300 lsls r3, r0, #2 + 2993 00ce 1B18 adds r3, r3, r0 + 2994 00d0 8033 adds r3, r3, #128 + 2995 00d2 1B12 asrs r3, r3, #8 + 2996 .LVL342: + 2997 .LBE203: + 2998 .LBE202: +1015:Drivers/BME680/bme680.c **** data->pressure = calc_pressure(adc_pres, dev); + 2999 .loc 1 1015 0 + 3000 00d4 4A46 mov r2, r9 + 3001 00d6 9380 strh r3, [r2, #4] + 3002 .LVL343: + 3003 .LBB204: + 3004 .LBB205: + 840:Drivers/BME680/bme680.c **** var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) * + 3005 .loc 1 840 0 + 3006 00d8 2B6B ldr r3, [r5, #48] + 3007 00da 5A10 asrs r2, r3, #1 + 3008 00dc BA4B ldr r3, .L207 + 3009 00de 9C46 mov ip, r3 + 3010 00e0 6244 add r2, r2, ip + 3011 .LVL344: + 841:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p6) >> 2; + 3012 .loc 1 841 0 + 3013 00e2 9110 asrs r1, r2, #2 + ARM GAS /tmp/ccvbgJts.s page 79 + + + 3014 00e4 4943 muls r1, r1 + 3015 00e6 C812 asrs r0, r1, #11 + 842:Drivers/BME680/bme680.c **** var2 = var2 + ((var1 * (int32_t)dev->calib.par_p5) << 1); + 3016 .loc 1 842 0 + 3017 00e8 2623 movs r3, #38 + 3018 00ea EB56 ldrsb r3, [r5, r3] + 841:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p6) >> 2; + 3019 .loc 1 841 0 + 3020 00ec 4343 muls r3, r0 + 3021 00ee 9B10 asrs r3, r3, #2 + 3022 .LVL345: + 843:Drivers/BME680/bme680.c **** var2 = (var2 >> 2) + ((int32_t)dev->calib.par_p4 << 16); + 3023 .loc 1 843 0 + 3024 00f0 2426 movs r6, #36 + 3025 00f2 A85F ldrsh r0, [r5, r6] + 3026 00f4 5043 muls r0, r2 + 3027 00f6 4000 lsls r0, r0, #1 + 3028 00f8 1B18 adds r3, r3, r0 + 3029 .LVL346: + 844:Drivers/BME680/bme680.c **** var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) * + 3030 .loc 1 844 0 + 3031 00fa 9B10 asrs r3, r3, #2 + 3032 .LVL347: + 3033 00fc 2226 movs r6, #34 + 3034 00fe A85F ldrsh r0, [r5, r6] + 3035 .LVL348: + 3036 0100 0004 lsls r0, r0, #16 + 3037 0102 1B18 adds r3, r3, r0 + 3038 .LVL349: + 845:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p3 << 5)) >> 3) + + 3039 .loc 1 845 0 + 3040 0104 4813 asrs r0, r1, #13 + 846:Drivers/BME680/bme680.c **** (((int32_t)dev->calib.par_p2 * var1) >> 1); + 3041 .loc 1 846 0 + 3042 0106 2021 movs r1, #32 + 3043 0108 6956 ldrsb r1, [r5, r1] + 3044 010a 4901 lsls r1, r1, #5 + 845:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p3 << 5)) >> 3) + + 3045 .loc 1 845 0 + 3046 010c 4143 muls r1, r0 + 846:Drivers/BME680/bme680.c **** (((int32_t)dev->calib.par_p2 * var1) >> 1); + 3047 .loc 1 846 0 + 3048 010e C910 asrs r1, r1, #3 + 847:Drivers/BME680/bme680.c **** var1 = var1 >> 18; + 3049 .loc 1 847 0 + 3050 0110 1E26 movs r6, #30 + 3051 0112 A85F ldrsh r0, [r5, r6] + 3052 0114 4243 muls r2, r0 + 3053 .LVL350: + 3054 0116 5210 asrs r2, r2, #1 + 845:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p3 << 5)) >> 3) + + 3055 .loc 1 845 0 + 3056 0118 8918 adds r1, r1, r2 + 3057 .LVL351: + 848:Drivers/BME680/bme680.c **** var1 = ((32768 + var1) * (int32_t)dev->calib.par_p1) >> 15; + 3058 .loc 1 848 0 + 3059 011a 8914 asrs r1, r1, #18 + ARM GAS /tmp/ccvbgJts.s page 80 + + + 3060 .LVL352: + 849:Drivers/BME680/bme680.c **** pressure_comp = 1048576 - pres_adc; + 3061 .loc 1 849 0 + 3062 011c 8022 movs r2, #128 + 3063 011e 1202 lsls r2, r2, #8 + 3064 0120 9446 mov ip, r2 + 3065 0122 6144 add r1, r1, ip + 3066 .LVL353: + 3067 0124 AA8B ldrh r2, [r5, #28] + 3068 0126 5143 muls r1, r2 + 3069 .LVL354: + 3070 0128 C913 asrs r1, r1, #15 + 3071 .LVL355: + 850:Drivers/BME680/bme680.c **** pressure_comp = (int32_t)((pressure_comp - (var2 >> 12)) * ((uint32_t)3125)); + 3072 .loc 1 850 0 + 3073 012a 8020 movs r0, #128 + 3074 012c 4003 lsls r0, r0, #13 + 3075 012e C01B subs r0, r0, r7 + 3076 .LVL356: + 851:Drivers/BME680/bme680.c **** var4 = (1 << 31); + 3077 .loc 1 851 0 + 3078 0130 1B13 asrs r3, r3, #12 + 3079 .LVL357: + 3080 0132 C01A subs r0, r0, r3 + 3081 .LVL358: + 3082 0134 A54B ldr r3, .L207+4 + 3083 0136 5843 muls r0, r3 + 3084 .LVL359: + 854:Drivers/BME680/bme680.c **** else + 3085 .loc 1 854 0 + 3086 0138 FFF7FEFF bl __aeabi_uidiv + 3087 .LVL360: + 3088 013c 4000 lsls r0, r0, #1 + 3089 .LVL361: + 857:Drivers/BME680/bme680.c **** (pressure_comp >> 3)) >> 13)) >> 12; + 3090 .loc 1 857 0 + 3091 013e 2A23 movs r3, #42 + 3092 0140 E95E ldrsh r1, [r5, r3] + 3093 0142 C210 asrs r2, r0, #3 + 3094 0144 5243 muls r2, r2 + 858:Drivers/BME680/bme680.c **** var2 = ((int32_t)(pressure_comp >> 2) * + 3095 .loc 1 858 0 + 3096 0146 5313 asrs r3, r2, #13 + 857:Drivers/BME680/bme680.c **** (pressure_comp >> 3)) >> 13)) >> 12; + 3097 .loc 1 857 0 + 3098 0148 4B43 muls r3, r1 + 3099 014a 1A13 asrs r2, r3, #12 + 3100 .LVL362: + 859:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p8) >> 13; + 3101 .loc 1 859 0 + 3102 014c 8310 asrs r3, r0, #2 + 860:Drivers/BME680/bme680.c **** var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) * + 3103 .loc 1 860 0 + 3104 014e 2826 movs r6, #40 + 3105 0150 A95F ldrsh r1, [r5, r6] + 859:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p8) >> 13; + 3106 .loc 1 859 0 + ARM GAS /tmp/ccvbgJts.s page 81 + + + 3107 0152 5943 muls r1, r3 + 3108 0154 4913 asrs r1, r1, #13 + 3109 .LVL363: + 861:Drivers/BME680/bme680.c **** (int32_t)(pressure_comp >> 8) * + 3110 .loc 1 861 0 + 3111 0156 0612 asrs r6, r0, #8 + 3112 0158 3300 movs r3, r6 + 3113 015a 7343 muls r3, r6 + 3114 015c 5E43 muls r6, r3 + 863:Drivers/BME680/bme680.c **** + 3115 .loc 1 863 0 + 3116 015e 2C23 movs r3, #44 + 3117 0160 EB5C ldrb r3, [r5, r3] + 862:Drivers/BME680/bme680.c **** (int32_t)dev->calib.par_p10) >> 17; + 3118 .loc 1 862 0 + 3119 0162 7343 muls r3, r6 + 861:Drivers/BME680/bme680.c **** (int32_t)(pressure_comp >> 8) * + 3120 .loc 1 861 0 + 3121 0164 5B14 asrs r3, r3, #17 + 3122 .LVL364: + 865:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p7 << 7)) >> 4); + 3123 .loc 1 865 0 + 3124 0166 5118 adds r1, r2, r1 + 3125 .LVL365: + 3126 0168 5B18 adds r3, r3, r1 + 3127 .LVL366: + 866:Drivers/BME680/bme680.c **** + 3128 .loc 1 866 0 + 3129 016a 2722 movs r2, #39 + 3130 .LVL367: + 3131 016c AA56 ldrsb r2, [r5, r2] + 3132 016e D201 lsls r2, r2, #7 + 865:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p7 << 7)) >> 4); + 3133 .loc 1 865 0 + 3134 0170 9B18 adds r3, r3, r2 + 866:Drivers/BME680/bme680.c **** + 3135 .loc 1 866 0 + 3136 0172 1B11 asrs r3, r3, #4 + 865:Drivers/BME680/bme680.c **** ((int32_t)dev->calib.par_p7 << 7)) >> 4); + 3137 .loc 1 865 0 + 3138 0174 C018 adds r0, r0, r3 + 3139 .LVL368: + 3140 .LBE205: + 3141 .LBE204: +1016:Drivers/BME680/bme680.c **** data->humidity = calc_humidity(adc_hum, dev); + 3142 .loc 1 1016 0 + 3143 0176 4B46 mov r3, r9 + 3144 0178 9860 str r0, [r3, #8] + 3145 .LVL369: + 3146 .LBB206: + 3147 .LBB207: + 886:Drivers/BME680/bme680.c **** var1 = (int32_t) (hum_adc - ((int32_t) ((int32_t) dev->calib.par_h1 * 16))) + 3148 .loc 1 886 0 + 3149 017a 2B6B ldr r3, [r5, #48] + 3150 017c 9E00 lsls r6, r3, #2 + 3151 017e F618 adds r6, r6, r3 + 3152 0180 8036 adds r6, r6, #128 + ARM GAS /tmp/ccvbgJts.s page 82 + + + 3153 0182 3612 asrs r6, r6, #8 + 3154 .LVL370: + 887:Drivers/BME680/bme680.c **** - (((temp_scaled * (int32_t) dev->calib.par_h3) / ((int32_t) 100)) >> 1); + 3155 .loc 1 887 0 + 3156 0184 2F89 ldrh r7, [r5, #8] + 3157 0186 3F01 lsls r7, r7, #4 + 3158 0188 5B46 mov r3, fp + 3159 018a DF1B subs r7, r3, r7 + 888:Drivers/BME680/bme680.c **** var2 = ((int32_t) dev->calib.par_h2 + 3160 .loc 1 888 0 + 3161 018c 0C20 movs r0, #12 + 3162 018e 2856 ldrsb r0, [r5, r0] + 3163 0190 7043 muls r0, r6 + 3164 0192 6421 movs r1, #100 + 3165 0194 FFF7FEFF bl __aeabi_idiv + 3166 .LVL371: + 3167 0198 4010 asrs r0, r0, #1 + 887:Drivers/BME680/bme680.c **** - (((temp_scaled * (int32_t) dev->calib.par_h3) / ((int32_t) 100)) >> 1); + 3168 .loc 1 887 0 + 3169 019a 3B1A subs r3, r7, r0 + 3170 019c 0293 str r3, [sp, #8] + 3171 .LVL372: + 889:Drivers/BME680/bme680.c **** * (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100)) + 3172 .loc 1 889 0 + 3173 019e 6A89 ldrh r2, [r5, #10] + 3174 01a0 9346 mov fp, r2 + 3175 .LVL373: + 890:Drivers/BME680/bme680.c **** + (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6) + 3176 .loc 1 890 0 + 3177 01a2 0D20 movs r0, #13 + 3178 01a4 2856 ldrsb r0, [r5, r0] + 3179 01a6 7043 muls r0, r6 + 3180 01a8 6421 movs r1, #100 + 3181 01aa FFF7FEFF bl __aeabi_idiv + 3182 .LVL374: + 3183 01ae 0700 movs r7, r0 + 891:Drivers/BME680/bme680.c **** / ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10; + 3184 .loc 1 891 0 + 3185 01b0 0E20 movs r0, #14 + 3186 01b2 2856 ldrsb r0, [r5, r0] + 3187 01b4 7043 muls r0, r6 + 3188 01b6 6421 movs r1, #100 + 3189 01b8 FFF7FEFF bl __aeabi_idiv + 3190 .LVL375: + 3191 01bc 7043 muls r0, r6 + 3192 01be 8011 asrs r0, r0, #6 + 892:Drivers/BME680/bme680.c **** var3 = var1 * var2; + 3193 .loc 1 892 0 + 3194 01c0 6421 movs r1, #100 + 3195 01c2 FFF7FEFF bl __aeabi_idiv + 3196 .LVL376: + 891:Drivers/BME680/bme680.c **** / ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10; + 3197 .loc 1 891 0 + 3198 01c6 3F18 adds r7, r7, r0 + 892:Drivers/BME680/bme680.c **** var3 = var1 * var2; + 3199 .loc 1 892 0 + 3200 01c8 8022 movs r2, #128 + ARM GAS /tmp/ccvbgJts.s page 83 + + + 3201 01ca D201 lsls r2, r2, #7 + 3202 01cc 9446 mov ip, r2 + 3203 01ce 6744 add r7, r7, ip + 890:Drivers/BME680/bme680.c **** + (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6) + 3204 .loc 1 890 0 + 3205 01d0 5A46 mov r2, fp + 3206 01d2 5743 muls r7, r2 + 889:Drivers/BME680/bme680.c **** * (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100)) + 3207 .loc 1 889 0 + 3208 01d4 BF12 asrs r7, r7, #10 + 3209 .LVL377: + 893:Drivers/BME680/bme680.c **** var4 = (int32_t) dev->calib.par_h6 << 7; + 3210 .loc 1 893 0 + 3211 01d6 029B ldr r3, [sp, #8] + 3212 01d8 5F43 muls r7, r3 + 3213 .LVL378: + 894:Drivers/BME680/bme680.c **** var4 = ((var4) + ((temp_scaled * (int32_t) dev->calib.par_h7) / ((int32_t) 100))) >> 4; + 3214 .loc 1 894 0 + 3215 01da E87B ldrb r0, [r5, #15] + 3216 01dc C301 lsls r3, r0, #7 + 3217 01de 9B46 mov fp, r3 + 3218 .LVL379: + 895:Drivers/BME680/bme680.c **** var5 = ((var3 >> 14) * (var3 >> 14)) >> 10; + 3219 .loc 1 895 0 + 3220 01e0 1020 movs r0, #16 + 3221 01e2 2856 ldrsb r0, [r5, r0] + 3222 01e4 7043 muls r0, r6 + 3223 01e6 6421 movs r1, #100 + 3224 01e8 FFF7FEFF bl __aeabi_idiv + 3225 .LVL380: + 3226 01ec 5844 add r0, r0, fp + 3227 01ee 0011 asrs r0, r0, #4 + 3228 .LVL381: + 896:Drivers/BME680/bme680.c **** var6 = (var4 * var5) >> 1; + 3229 .loc 1 896 0 + 3230 01f0 BB13 asrs r3, r7, #14 + 3231 01f2 5B43 muls r3, r3 + 3232 01f4 9B12 asrs r3, r3, #10 + 3233 .LVL382: + 897:Drivers/BME680/bme680.c **** calc_hum = (((var3 + var6) >> 10) * ((int32_t) 1000)) >> 12; + 3234 .loc 1 897 0 + 3235 01f6 4343 muls r3, r0 + 3236 .LVL383: + 3237 01f8 5B10 asrs r3, r3, #1 + 3238 .LVL384: + 898:Drivers/BME680/bme680.c **** + 3239 .loc 1 898 0 + 3240 01fa FF18 adds r7, r7, r3 + 3241 .LVL385: + 3242 01fc BF12 asrs r7, r7, #10 + 3243 01fe 7B01 lsls r3, r7, #5 + 3244 .LVL386: + 3245 0200 DB1B subs r3, r3, r7 + 3246 0202 9B00 lsls r3, r3, #2 + 3247 0204 DB19 adds r3, r3, r7 + 3248 0206 DB00 lsls r3, r3, #3 + 3249 0208 1B13 asrs r3, r3, #12 + ARM GAS /tmp/ccvbgJts.s page 84 + + + 3250 .LVL387: + 900:Drivers/BME680/bme680.c **** calc_hum = 100000; + 3251 .loc 1 900 0 + 3252 020a 714A ldr r2, .L207+8 + 3253 020c 9342 cmp r3, r2 + 3254 020e 03DC bgt .L199 + 902:Drivers/BME680/bme680.c **** calc_hum = 0; + 3255 .loc 1 902 0 + 3256 0210 002B cmp r3, #0 + 3257 0212 02DA bge .L186 + 903:Drivers/BME680/bme680.c **** + 3258 .loc 1 903 0 + 3259 0214 0023 movs r3, #0 + 3260 .LVL388: + 3261 0216 00E0 b .L186 + 3262 .LVL389: + 3263 .L199: + 901:Drivers/BME680/bme680.c **** else if (calc_hum < 0) + 3264 .loc 1 901 0 + 3265 0218 6D4B ldr r3, .L207+8 + 3266 .LVL390: + 3267 .L186: + 3268 .LBE207: + 3269 .LBE206: +1017:Drivers/BME680/bme680.c **** data->gas_resistance = calc_gas_resistance(adc_gas_res, gas_range, dev); + 3270 .loc 1 1017 0 + 3271 021a 4A46 mov r2, r9 + 3272 021c D360 str r3, [r2, #12] + 3273 .LVL391: + 3274 .LBB208: + 3275 .LBB209: + 918:Drivers/BME680/bme680.c **** ((int64_t) lookupTable1[gas_range])) >> 16; + 3276 .loc 1 918 0 + 3277 021e 3623 movs r3, #54 + 3278 0220 EE56 ldrsb r6, [r5, r3] + 3279 0222 3000 movs r0, r6 + 3280 0224 F617 asrs r6, r6, #31 + 3281 0226 3100 movs r1, r6 + 3282 0228 870F lsrs r7, r0, #30 + 3283 022a B300 lsls r3, r6, #2 + 3284 022c 3B43 orrs r3, r7 + 3285 022e 8200 lsls r2, r0, #2 + 3286 0230 1218 adds r2, r2, r0 + 3287 0232 4B41 adcs r3, r3, r1 + 3288 0234 6748 ldr r0, .L207+12 + 3289 0236 0021 movs r1, #0 + 3290 0238 8018 adds r0, r0, r2 + 3291 023a 5941 adcs r1, r1, r3 + 919:Drivers/BME680/bme680.c **** var2 = (((int64_t) ((int64_t) gas_res_adc << 15) - (int64_t) (16777216)) + var1); + 3292 .loc 1 919 0 + 3293 023c 5346 mov r3, r10 + 3294 023e 9B00 lsls r3, r3, #2 + 3295 0240 9A46 mov r10, r3 + 3296 .LVL392: + 3297 0242 654B ldr r3, .L207+16 + 3298 0244 5246 mov r2, r10 + 3299 0246 D258 ldr r2, [r2, r3] + ARM GAS /tmp/ccvbgJts.s page 85 + + + 918:Drivers/BME680/bme680.c **** ((int64_t) lookupTable1[gas_range])) >> 16; + 3300 .loc 1 918 0 + 3301 0248 0023 movs r3, #0 + 3302 024a FFF7FEFF bl __aeabi_lmul + 3303 .LVL393: + 3304 024e 0B04 lsls r3, r1, #16 + 3305 0250 060C lsrs r6, r0, #16 + 3306 0252 1E43 orrs r6, r3 + 3307 0254 0F14 asrs r7, r1, #16 + 3308 .LVL394: + 920:Drivers/BME680/bme680.c **** var3 = (((int64_t) lookupTable2[gas_range] * (int64_t) var1) >> 9); + 3309 .loc 1 920 0 + 3310 0256 0021 movs r1, #0 + 3311 0258 4346 mov r3, r8 + 3312 025a D803 lsls r0, r3, #15 + 3313 025c FF22 movs r2, #255 + 3314 025e 1206 lsls r2, r2, #24 + 3315 0260 0123 movs r3, #1 + 3316 0262 5B42 rsbs r3, r3, #0 + 3317 0264 1218 adds r2, r2, r0 + 3318 0266 4B41 adcs r3, r3, r1 + 3319 0268 9219 adds r2, r2, r6 + 3320 026a 7B41 adcs r3, r3, r7 + 3321 026c 0492 str r2, [sp, #16] + 3322 026e 0593 str r3, [sp, #20] + 3323 .LVL395: + 921:Drivers/BME680/bme680.c **** calc_gas_res = (uint32_t) ((var3 + ((int64_t) var2 >> 1)) / (int64_t) var2); + 3324 .loc 1 921 0 + 3325 0270 5A4B ldr r3, .L207+20 + 3326 0272 5146 mov r1, r10 + 3327 0274 CA58 ldr r2, [r1, r3] + 3328 .LVL396: + 3329 0276 0023 movs r3, #0 + 3330 0278 3000 movs r0, r6 + 3331 027a 3900 movs r1, r7 + 3332 027c FFF7FEFF bl __aeabi_lmul + 3333 .LVL397: + 3334 0280 CE05 lsls r6, r1, #23 + 3335 .LVL398: + 3336 0282 430A lsrs r3, r0, #9 + 3337 0284 3343 orrs r3, r6 + 3338 0286 0293 str r3, [sp, #8] + 3339 0288 4B12 asrs r3, r1, #9 + 3340 028a 0393 str r3, [sp, #12] + 3341 .LVL399: + 922:Drivers/BME680/bme680.c **** + 3342 .loc 1 922 0 + 3343 028c 049A ldr r2, [sp, #16] + 3344 028e 059B ldr r3, [sp, #20] + 3345 0290 DE07 lsls r6, r3, #31 + 3346 0292 5008 lsrs r0, r2, #1 + 3347 0294 3043 orrs r0, r6 + 3348 0296 1600 movs r6, r2 + 3349 0298 1F00 movs r7, r3 + 3350 029a 5910 asrs r1, r3, #1 + 3351 029c 029A ldr r2, [sp, #8] + 3352 029e 039B ldr r3, [sp, #12] + ARM GAS /tmp/ccvbgJts.s page 86 + + + 3353 02a0 8018 adds r0, r0, r2 + 3354 02a2 5941 adcs r1, r1, r3 + 3355 02a4 3200 movs r2, r6 + 3356 02a6 3B00 movs r3, r7 + 3357 02a8 FFF7FEFF bl __aeabi_ldivmod + 3358 .LVL400: + 3359 .LBE209: + 3360 .LBE208: +1018:Drivers/BME680/bme680.c **** break; + 3361 .loc 1 1018 0 + 3362 02ac 4B46 mov r3, r9 + 3363 02ae 1861 str r0, [r3, #16] + 3364 02b0 5EE0 b .L187 + 3365 .LVL401: + 3366 .L184: +1024:Drivers/BME680/bme680.c **** } while (tries); + 3367 .loc 1 1024 0 + 3368 02b2 013C subs r4, r4, #1 + 3369 .LVL402: + 3370 02b4 E4B2 uxtb r4, r4 + 3371 .LVL403: +1025:Drivers/BME680/bme680.c **** + 3372 .loc 1 1025 0 + 3373 02b6 002C cmp r4, #0 + 3374 02b8 58D0 beq .L203 + 3375 .LVL404: + 3376 .L188: + 994:Drivers/BME680/bme680.c **** rslt = bme680_get_regs(((uint8_t) (BME680_FIELD0_ADDR)), buff, (uint16_t) BME680_FIELD_LENGTH, + 3377 .loc 1 994 0 + 3378 02ba 002E cmp r6, #0 + 3379 02bc F9D1 bne .L184 + 995:Drivers/BME680/bme680.c **** dev); + 3380 .loc 1 995 0 + 3381 02be 2B00 movs r3, r5 + 3382 02c0 0F22 movs r2, #15 + 3383 02c2 06A9 add r1, sp, #24 + 3384 02c4 1D20 movs r0, #29 + 3385 02c6 FFF7FEFF bl bme680_get_regs + 3386 .LVL405: + 3387 02ca 0600 movs r6, r0 + 3388 .LVL406: + 998:Drivers/BME680/bme680.c **** data->gas_index = buff[0] & BME680_GAS_INDEX_MSK; + 3389 .loc 1 998 0 + 3390 02cc 06AB add r3, sp, #24 + 3391 02ce 1B78 ldrb r3, [r3] + 3392 02d0 7F22 movs r2, #127 + 3393 02d2 1900 movs r1, r3 + 3394 02d4 9143 bics r1, r2 + 3395 02d6 8C46 mov ip, r1 + 999:Drivers/BME680/bme680.c **** data->meas_index = buff[1]; + 3396 .loc 1 999 0 + 3397 02d8 703A subs r2, r2, #112 + 3398 02da 9246 mov r10, r2 + 3399 02dc 1340 ands r3, r2 + 3400 02de 7B70 strb r3, [r7, #1] +1000:Drivers/BME680/bme680.c **** + 3401 .loc 1 1000 0 + ARM GAS /tmp/ccvbgJts.s page 87 + + + 3402 02e0 06AB add r3, sp, #24 + 3403 02e2 5B78 ldrb r3, [r3, #1] + 3404 02e4 BB70 strb r3, [r7, #2] +1003:Drivers/BME680/bme680.c **** | ((uint32_t) buff[4] / 16)); + 3405 .loc 1 1003 0 + 3406 02e6 06AB add r3, sp, #24 + 3407 02e8 9A78 ldrb r2, [r3, #2] + 3408 02ea 1203 lsls r2, r2, #12 + 3409 02ec DB78 ldrb r3, [r3, #3] + 3410 02ee 1B01 lsls r3, r3, #4 + 3411 02f0 1A43 orrs r2, r3 +1004:Drivers/BME680/bme680.c **** adc_temp = (uint32_t) (((uint32_t) buff[5] * 4096) | ((uint32_t) buff[6] * 16) + 3412 .loc 1 1004 0 + 3413 02f2 06AB add r3, sp, #24 + 3414 02f4 1B79 ldrb r3, [r3, #4] + 3415 02f6 1B09 lsrs r3, r3, #4 +1003:Drivers/BME680/bme680.c **** | ((uint32_t) buff[4] / 16)); + 3416 .loc 1 1003 0 + 3417 02f8 1A43 orrs r2, r3 + 3418 02fa 0292 str r2, [sp, #8] + 3419 .LVL407: +1005:Drivers/BME680/bme680.c **** | ((uint32_t) buff[7] / 16)); + 3420 .loc 1 1005 0 + 3421 02fc 06AB add r3, sp, #24 + 3422 02fe 5879 ldrb r0, [r3, #5] + 3423 .LVL408: + 3424 0300 0003 lsls r0, r0, #12 + 3425 0302 9B79 ldrb r3, [r3, #6] + 3426 0304 1B01 lsls r3, r3, #4 + 3427 0306 1843 orrs r0, r3 +1006:Drivers/BME680/bme680.c **** adc_hum = (uint16_t) (((uint32_t) buff[8] * 256) | (uint32_t) buff[9]); + 3428 .loc 1 1006 0 + 3429 0308 06AB add r3, sp, #24 + 3430 030a DB79 ldrb r3, [r3, #7] + 3431 030c 1B09 lsrs r3, r3, #4 +1005:Drivers/BME680/bme680.c **** | ((uint32_t) buff[7] / 16)); + 3432 .loc 1 1005 0 + 3433 030e 1843 orrs r0, r3 + 3434 .LVL409: +1007:Drivers/BME680/bme680.c **** adc_gas_res = (uint16_t) ((uint32_t) buff[13] * 4 | (((uint32_t) buff[14]) / 64)); + 3435 .loc 1 1007 0 + 3436 0310 06AB add r3, sp, #24 + 3437 0312 197A ldrb r1, [r3, #8] + 3438 0314 0902 lsls r1, r1, #8 + 3439 0316 5B7A ldrb r3, [r3, #9] + 3440 0318 1943 orrs r1, r3 + 3441 031a 8B46 mov fp, r1 + 3442 .LVL410: +1008:Drivers/BME680/bme680.c **** gas_range = buff[14] & BME680_GAS_RANGE_MSK; + 3443 .loc 1 1008 0 + 3444 031c 06AB add r3, sp, #24 + 3445 031e 5B7B ldrb r3, [r3, #13] + 3446 0320 9B00 lsls r3, r3, #2 + 3447 0322 9846 mov r8, r3 + 3448 0324 06AB add r3, sp, #24 + 3449 0326 9B7B ldrb r3, [r3, #14] + 3450 0328 9A09 lsrs r2, r3, #6 + ARM GAS /tmp/ccvbgJts.s page 88 + + + 3451 .LVL411: + 3452 032a 9146 mov r9, r2 + 3453 032c 4246 mov r2, r8 + 3454 032e 4946 mov r1, r9 + 3455 0330 0A43 orrs r2, r1 + 3456 0332 9046 mov r8, r2 + 3457 .LVL412: +1009:Drivers/BME680/bme680.c **** + 3458 .loc 1 1009 0 + 3459 0334 5246 mov r2, r10 + 3460 0336 1A40 ands r2, r3 + 3461 0338 9246 mov r10, r2 + 3462 .LVL413: +1011:Drivers/BME680/bme680.c **** data->status |= buff[14] & BME680_HEAT_STAB_MSK; + 3463 .loc 1 1011 0 + 3464 033a 5BB2 sxtb r3, r3 + 3465 033c 9946 mov r9, r3 + 3466 033e 2023 movs r3, #32 + 3467 0340 4A46 mov r2, r9 + 3468 0342 1340 ands r3, r2 + 3469 0344 6246 mov r2, ip + 3470 0346 1343 orrs r3, r2 + 3471 0348 5BB2 sxtb r3, r3 +1012:Drivers/BME680/bme680.c **** + 3472 .loc 1 1012 0 + 3473 034a 06AA add r2, sp, #24 + 3474 034c 927B ldrb r2, [r2, #14] + 3475 034e 52B2 sxtb r2, r2 + 3476 0350 9146 mov r9, r2 + 3477 0352 1022 movs r2, #16 + 3478 0354 9446 mov ip, r2 + 3479 0356 4A46 mov r2, r9 + 3480 0358 6146 mov r1, ip + 3481 035a 0A40 ands r2, r1 + 3482 035c 1343 orrs r3, r2 + 3483 035e 3B70 strb r3, [r7] +1014:Drivers/BME680/bme680.c **** data->temperature = calc_temperature(adc_temp, dev); + 3484 .loc 1 1014 0 + 3485 0360 00D5 bpl .LCB3947 + 3486 0362 89E6 b .L204 @long jump + 3487 .LCB3947: +1022:Drivers/BME680/bme680.c **** } + 3488 .loc 1 1022 0 + 3489 0364 0A20 movs r0, #10 + 3490 .LVL414: + 3491 0366 2B6D ldr r3, [r5, #80] + 3492 0368 9847 blx r3 + 3493 .LVL415: + 3494 036a A2E7 b .L184 + 3495 .LVL416: + 3496 .L203: + 3497 036c 0196 str r6, [sp, #4] + 3498 036e B946 mov r9, r7 + 3499 .LVL417: + 3500 .L187: +1027:Drivers/BME680/bme680.c **** rslt = BME680_W_NO_NEW_DATA; + 3501 .loc 1 1027 0 + ARM GAS /tmp/ccvbgJts.s page 89 + + + 3502 0370 002C cmp r4, #0 + 3503 0372 12D0 beq .L205 + 3504 .LVL418: + 3505 .L189: + 3506 .LBE199: + 3507 .LBE198: + 651:Drivers/BME680/bme680.c **** if (data->status & BME680_NEW_DATA_MSK) + 3508 .loc 1 651 0 + 3509 0374 019B ldr r3, [sp, #4] + 3510 0376 002B cmp r3, #0 + 3511 0378 07D1 bne .L182 + 652:Drivers/BME680/bme680.c **** dev->new_fields = 1; + 3512 .loc 1 652 0 + 3513 037a 4B46 mov r3, r9 + 3514 037c 1B78 ldrb r3, [r3] + 3515 037e 5BB2 sxtb r3, r3 + 3516 0380 002B cmp r3, #0 + 3517 0382 0DDB blt .L206 + 655:Drivers/BME680/bme680.c **** } + 3518 .loc 1 655 0 + 3519 0384 4523 movs r3, #69 + 3520 0386 0022 movs r2, #0 + 3521 0388 EA54 strb r2, [r5, r3] + 3522 .LVL419: + 3523 .L182: + 660:Drivers/BME680/bme680.c **** + 3524 .loc 1 660 0 + 3525 038a 0198 ldr r0, [sp, #4] + 3526 038c 0BB0 add sp, sp, #44 + 3527 @ sp needed + 3528 .LVL420: + 3529 .LVL421: + 3530 038e 3CBC pop {r2, r3, r4, r5} + 3531 0390 9046 mov r8, r2 + 3532 0392 9946 mov r9, r3 + 3533 0394 A246 mov r10, r4 + 3534 0396 AB46 mov fp, r5 + 3535 0398 F0BD pop {r4, r5, r6, r7, pc} + 3536 .LVL422: + 3537 .L205: + 3538 .LBB211: + 3539 .LBB210: +1028:Drivers/BME680/bme680.c **** + 3540 .loc 1 1028 0 + 3541 039a 0223 movs r3, #2 + 3542 039c 0193 str r3, [sp, #4] + 3543 .LVL423: + 3544 039e E9E7 b .L189 + 3545 .LVL424: + 3546 .L206: + 3547 .LBE210: + 3548 .LBE211: + 653:Drivers/BME680/bme680.c **** else + 3549 .loc 1 653 0 + 3550 03a0 4523 movs r3, #69 + 3551 03a2 0122 movs r2, #1 + 3552 03a4 EA54 strb r2, [r5, r3] + ARM GAS /tmp/ccvbgJts.s page 90 + + + 3553 03a6 F0E7 b .L182 + 3554 .LVL425: + 3555 .L191: + 3556 .LBB212: + 3557 .LBB197: +1131:Drivers/BME680/bme680.c **** } else { + 3558 .loc 1 1131 0 + 3559 03a8 0123 movs r3, #1 + 3560 03aa 5B42 rsbs r3, r3, #0 + 3561 03ac 0193 str r3, [sp, #4] + 3562 03ae ECE7 b .L182 + 3563 .L192: + 3564 03b0 0123 movs r3, #1 + 3565 03b2 5B42 rsbs r3, r3, #0 + 3566 03b4 0193 str r3, [sp, #4] + 3567 03b6 E8E7 b .L182 + 3568 .L193: + 3569 03b8 0123 movs r3, #1 + 3570 03ba 5B42 rsbs r3, r3, #0 + 3571 03bc 0193 str r3, [sp, #4] + 3572 03be E4E7 b .L182 + 3573 .L194: + 3574 03c0 0123 movs r3, #1 + 3575 03c2 5B42 rsbs r3, r3, #0 + 3576 03c4 0193 str r3, [sp, #4] + 3577 03c6 E0E7 b .L182 + 3578 .L208: + 3579 .align 2 + 3580 .L207: + 3581 03c8 0006FFFF .word -64000 + 3582 03cc 350C0000 .word 3125 + 3583 03d0 A0860100 .word 100000 + 3584 03d4 3C050000 .word 1340 + 3585 03d8 00000000 .word .LANCHOR0 + 3586 03dc 00000000 .word .LANCHOR1 + 3587 .LBE197: + 3588 .LBE212: + 3589 .cfi_endproc + 3590 .LFE10: + 3592 .global lookupTable2 + 3593 .global lookupTable1 + 3594 .section .data.lookupTable1,"aw",%progbits + 3595 .align 2 + 3596 .set .LANCHOR0,. + 0 + 3599 lookupTable1: + 3600 0000 FFFFFF7F .word 2147483647 + 3601 0004 FFFFFF7F .word 2147483647 + 3602 0008 FFFFFF7F .word 2147483647 + 3603 000c FFFFFF7F .word 2147483647 + 3604 0010 FFFFFF7F .word 2147483647 + 3605 0014 EA51B87E .word 2126008810 + 3606 0018 FFFFFF7F .word 2147483647 + 3607 001c 21DBF97E .word 2130303777 + 3608 0020 FFFFFF7F .word 2147483647 + 3609 0024 FFFFFF7F .word 2147483647 + 3610 0028 C776BE7F .word 2143188679 + 3611 002c F4285C7F .word 2136746228 + ARM GAS /tmp/ccvbgJts.s page 91 + + + 3612 0030 FFFFFF7F .word 2147483647 + 3613 0034 EA51B87E .word 2126008810 + 3614 0038 FFFFFF7F .word 2147483647 + 3615 003c FFFFFF7F .word 2147483647 + 3616 .section .data.lookupTable2,"aw",%progbits + 3617 .align 2 + 3618 .set .LANCHOR1,. + 0 + 3621 lookupTable2: + 3622 0000 000024F4 .word -198967296 + 3623 0004 0000127A .word 2048000000 + 3624 0008 0000093D .word 1024000000 + 3625 000c 0080841E .word 512000000 + 3626 0010 FF583E0F .word 255744255 + 3627 0014 548C9307 .word 127110228 + 3628 0018 0090D003 .word 64000000 + 3629 001c 1038EC01 .word 32258064 + 3630 0020 9062F400 .word 16016016 + 3631 0024 00127A00 .word 8000000 + 3632 0028 00093D00 .word 4000000 + 3633 002c 80841E00 .word 2000000 + 3634 0030 40420F00 .word 1000000 + 3635 0034 20A10700 .word 500000 + 3636 0038 90D00300 .word 250000 + 3637 003c 48E80100 .word 125000 + 3638 .text + 3639 .Letext0: + 3640 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3641 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3642 .file 4 "Drivers/BME680/bme680_defs.h" + 3643 .file 5 "" + ARM GAS /tmp/ccvbgJts.s page 92 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 bme680.c + /tmp/ccvbgJts.s:16 .text.set_mem_page:0000000000000000 $t + /tmp/ccvbgJts.s:22 .text.set_mem_page:0000000000000000 set_mem_page + /tmp/ccvbgJts.s:176 .text.get_mem_page:0000000000000000 $t + /tmp/ccvbgJts.s:182 .text.get_mem_page:0000000000000000 get_mem_page + /tmp/ccvbgJts.s:282 .text.bme680_get_regs:0000000000000000 $t + /tmp/ccvbgJts.s:289 .text.bme680_get_regs:0000000000000000 bme680_get_regs + /tmp/ccvbgJts.s:416 .text.bme680_set_regs:0000000000000000 $t + /tmp/ccvbgJts.s:423 .text.bme680_set_regs:0000000000000000 bme680_set_regs + /tmp/ccvbgJts.s:618 .text.bme680_soft_reset:0000000000000000 $t + /tmp/ccvbgJts.s:625 .text.bme680_soft_reset:0000000000000000 bme680_soft_reset + /tmp/ccvbgJts.s:759 .text.bme680_init:0000000000000000 $t + /tmp/ccvbgJts.s:766 .text.bme680_init:0000000000000000 bme680_init + /tmp/ccvbgJts.s:1155 .text.bme680_get_sensor_settings:0000000000000000 $t + /tmp/ccvbgJts.s:1162 .text.bme680_get_sensor_settings:0000000000000000 bme680_get_sensor_settings + /tmp/ccvbgJts.s:1470 .text.bme680_set_sensor_mode:0000000000000000 $t + /tmp/ccvbgJts.s:1477 .text.bme680_set_sensor_mode:0000000000000000 bme680_set_sensor_mode + /tmp/ccvbgJts.s:1642 .text.bme680_set_sensor_settings:0000000000000000 $t + /tmp/ccvbgJts.s:1649 .text.bme680_set_sensor_settings:0000000000000000 bme680_set_sensor_settings + /tmp/ccvbgJts.s:2558 .text.bme680_set_sensor_settings:0000000000000440 $d + /tmp/ccvbgJts.s:2566 .text.bme680_get_sensor_mode:0000000000000000 $t + /tmp/ccvbgJts.s:2573 .text.bme680_get_sensor_mode:0000000000000000 bme680_get_sensor_mode + /tmp/ccvbgJts.s:2664 .text.bme680_set_profile_dur:0000000000000000 $t + /tmp/ccvbgJts.s:2671 .text.bme680_set_profile_dur:0000000000000000 bme680_set_profile_dur + /tmp/ccvbgJts.s:2727 .text.bme680_set_profile_dur:0000000000000034 $d + /tmp/ccvbgJts.s:2733 .text.bme680_get_profile_dur:0000000000000000 $t + /tmp/ccvbgJts.s:2740 .text.bme680_get_profile_dur:0000000000000000 bme680_get_profile_dur + /tmp/ccvbgJts.s:2806 .text.bme680_get_profile_dur:0000000000000040 $d + /tmp/ccvbgJts.s:2814 .text.bme680_get_sensor_data:0000000000000000 $t + /tmp/ccvbgJts.s:2821 .text.bme680_get_sensor_data:0000000000000000 bme680_get_sensor_data + /tmp/ccvbgJts.s:3581 .text.bme680_get_sensor_data:00000000000003c8 $d + /tmp/ccvbgJts.s:3621 .data.lookupTable2:0000000000000000 lookupTable2 + /tmp/ccvbgJts.s:3599 .data.lookupTable1:0000000000000000 lookupTable1 + /tmp/ccvbgJts.s:3595 .data.lookupTable1:0000000000000000 $d + /tmp/ccvbgJts.s:3617 .data.lookupTable2:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +memset +__aeabi_idiv +__aeabi_uidiv +__aeabi_lmul +__aeabi_ldivmod diff --git a/build/cmac.d b/build/cmac.d new file mode 100644 index 0000000..979f7d8 --- /dev/null +++ b/build/cmac.d @@ -0,0 +1,25 @@ +build/cmac.d: Middlewares/Third_Party/Lora/Crypto/cmac.c \ + Middlewares/Third_Party/Lora/Crypto/aes.h \ + Middlewares/Third_Party/Lora/Crypto/cmac.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h + +Middlewares/Third_Party/Lora/Crypto/aes.h: + +Middlewares/Third_Party/Lora/Crypto/cmac.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: diff --git a/build/cmac.lst b/build/cmac.lst new file mode 100644 index 0000000..86f7f84 --- /dev/null +++ b/build/cmac.lst @@ -0,0 +1,844 @@ +ARM GAS /tmp/ccUuuSOT.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "cmac.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.AES_CMAC_Init,"ax",%progbits + 16 .align 1 + 17 .global AES_CMAC_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 AES_CMAC_Init: + 24 .LFB82: + 25 .file 1 "./Middlewares/Third_Party/Lora/Crypto/cmac.c" + 1:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /************************************************************************** + 2:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** Copyright (C) 2009 Lander Casado, Philippas Tsigas + 3:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 4:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** All rights reserved. + 5:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 6:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** Permission is hereby granted, free of charge, to any person obtaining + 7:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** a copy of this software and associated documentation files + 8:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** (the "Software"), to deal with the Software without restriction, including + 9:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** without limitation the rights to use, copy, modify, merge, publish, + 10:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** distribute, sublicense, and/or sell copies of the Software, and to + 11:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** permit persons to whom the Software is furnished to do so, subject to + 12:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** the following conditions: + 13:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 14:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** Redistributions of source code must retain the above copyright notice, + 15:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** this list of conditions and the following disclaimers. Redistributions in + 16:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** binary form must reproduce the above copyright notice, this list of + 17:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** conditions and the following disclaimers in the documentation and/or + 18:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** other materials provided with the distribution. + 19:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 20:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** In no event shall the authors or copyright holders be liable for any special, + 21:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** incidental, indirect or consequential damages of any kind, or any damages + 22:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** whatsoever resulting from loss of use, data or profits, whether or not + 23:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** advised of the possibility of damage, and on any theory of liability, + 24:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** arising out of or in connection with the use or performance of this software. + 25:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 26:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + 27:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + 28:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + 29:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + 30:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + 31:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + 32:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** DEALINGS WITH THE SOFTWARE + 33:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + ARM GAS /tmp/ccUuuSOT.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** *****************************************************************************/ + 35:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //#include + 36:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //#include + 37:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #include + 38:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #include "aes.h" + 39:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #include "cmac.h" + 40:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #include "utilities.h" + 41:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 42:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #define LSHIFT(v, r) do { \ + 43:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** int32_t i; \ + 44:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** for (i = 0; i < 15; i++) \ + 45:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** (r)[i] = (v)[i] << 1 | (v)[i + 1] >> 7; \ + 46:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** (r)[15] = (v)[15] << 1; \ + 47:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } while (0) + 48:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 49:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** #define XOR(v, r) do { \ + 50:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** int32_t i; \ + 51:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** for (i = 0; i < 16; i++) \ + 52:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** { \ + 53:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** (r)[i] = (r)[i] ^ (v)[i]; \ + 54:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } \ + 55:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } while (0) \ + 56:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 57:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 58:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** void AES_CMAC_Init(AES_CMAC_CTX *ctx) + 59:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** { + 26 .loc 1 59 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 10B5 push {r4, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 4, -8 + 35 .cfi_offset 14, -4 + 36 0002 0400 movs r4, r0 + 60:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memset1(ctx->X, 0, sizeof ctx->X); + 37 .loc 1 60 0 + 38 0004 F130 adds r0, r0, #241 + 39 .LVL1: + 40 0006 1022 movs r2, #16 + 41 0008 0021 movs r1, #0 + 42 000a FFF7FEFF bl memset1 + 43 .LVL2: + 61:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** ctx->M_n = 0; + 44 .loc 1 61 0 + 45 000e 8A23 movs r3, #138 + 46 0010 5B00 lsls r3, r3, #1 + 47 0012 0022 movs r2, #0 + 48 0014 E250 str r2, [r4, r3] + 62:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memset1(ctx->rijndael.ksch, '\0', 240); + 49 .loc 1 62 0 + 50 0016 F032 adds r2, r2, #240 + 51 0018 0021 movs r1, #0 + 52 001a 2000 movs r0, r4 + 53 001c FFF7FEFF bl memset1 + ARM GAS /tmp/ccUuuSOT.s page 3 + + + 54 .LVL3: + 63:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 55 .loc 1 63 0 + 56 @ sp needed + 57 .LVL4: + 58 0020 10BD pop {r4, pc} + 59 .cfi_endproc + 60 .LFE82: + 62 .section .text.AES_CMAC_SetKey,"ax",%progbits + 63 .align 1 + 64 .global AES_CMAC_SetKey + 65 .syntax unified + 66 .code 16 + 67 .thumb_func + 68 .fpu softvfp + 70 AES_CMAC_SetKey: + 71 .LFB83: + 64:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 65:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** void AES_CMAC_SetKey(AES_CMAC_CTX *ctx, const uint8_t key[AES_CMAC_KEY_LENGTH]) + 66:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** { + 72 .loc 1 66 0 + 73 .cfi_startproc + 74 @ args = 0, pretend = 0, frame = 0 + 75 @ frame_needed = 0, uses_anonymous_args = 0 + 76 .LVL5: + 77 0000 10B5 push {r4, lr} + 78 .LCFI1: + 79 .cfi_def_cfa_offset 8 + 80 .cfi_offset 4, -8 + 81 .cfi_offset 14, -4 + 82 0002 0200 movs r2, r0 + 83 0004 0800 movs r0, r1 + 84 .LVL6: + 67:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_set_key_enc_only(&ctx->rijndael, key, 128); + 68:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** aes_set_key( key, AES_CMAC_KEY_LENGTH, &ctx->rijndael); + 85 .loc 1 68 0 + 86 0006 1021 movs r1, #16 + 87 .LVL7: + 88 0008 FFF7FEFF bl aes_set_key + 89 .LVL8: + 69:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 90 .loc 1 69 0 + 91 @ sp needed + 92 000c 10BD pop {r4, pc} + 93 .cfi_endproc + 94 .LFE83: + 96 .section .text.AES_CMAC_Update,"ax",%progbits + 97 .align 1 + 98 .global AES_CMAC_Update + 99 .syntax unified + 100 .code 16 + 101 .thumb_func + 102 .fpu softvfp + 104 AES_CMAC_Update: + 105 .LFB84: + 70:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 71:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** void AES_CMAC_Update(AES_CMAC_CTX *ctx, const uint8_t *data, uint32_t len) + ARM GAS /tmp/ccUuuSOT.s page 4 + + + 72:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** { + 106 .loc 1 72 0 + 107 .cfi_startproc + 108 @ args = 0, pretend = 0, frame = 16 + 109 @ frame_needed = 0, uses_anonymous_args = 0 + 110 .LVL9: + 111 0000 F0B5 push {r4, r5, r6, r7, lr} + 112 .LCFI2: + 113 .cfi_def_cfa_offset 20 + 114 .cfi_offset 4, -20 + 115 .cfi_offset 5, -16 + 116 .cfi_offset 6, -12 + 117 .cfi_offset 7, -8 + 118 .cfi_offset 14, -4 + 119 0002 C646 mov lr, r8 + 120 0004 00B5 push {lr} + 121 .LCFI3: + 122 .cfi_def_cfa_offset 24 + 123 .cfi_offset 8, -24 + 124 0006 84B0 sub sp, sp, #16 + 125 .LCFI4: + 126 .cfi_def_cfa_offset 40 + 127 0008 0400 movs r4, r0 + 128 000a 0D00 movs r5, r1 + 129 000c 1600 movs r6, r2 + 73:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** uint32_t mlen; + 74:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** uint8_t in[16]; + 75:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 76:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** if (ctx->M_n > 0) { + 130 .loc 1 76 0 + 131 000e 8A23 movs r3, #138 + 132 0010 5B00 lsls r3, r3, #1 + 133 0012 C058 ldr r0, [r0, r3] + 134 .LVL10: + 135 0014 0028 cmp r0, #0 + 136 0016 4AD0 beq .L9 + 77:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** mlen = MIN(16 - ctx->M_n, len); + 137 .loc 1 77 0 + 138 0018 053B subs r3, r3, #5 + 139 001a FF3B subs r3, r3, #255 + 140 001c 1B1A subs r3, r3, r0 + 141 001e 9846 mov r8, r3 + 142 0020 1F00 movs r7, r3 + 143 0022 9342 cmp r3, r2 + 144 0024 00D9 bls .L5 + 145 0026 1700 movs r7, r2 + 146 .L5: + 147 .LVL11: + 78:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memcpy1(ctx->M_last + ctx->M_n, data, mlen); + 148 .loc 1 78 0 + 149 0028 A31C adds r3, r4, #2 + 150 002a FF33 adds r3, r3, #255 + 151 002c BAB2 uxth r2, r7 + 152 .LVL12: + 153 002e 1818 adds r0, r3, r0 + 154 0030 2900 movs r1, r5 + 155 .LVL13: + ARM GAS /tmp/ccUuuSOT.s page 5 + + + 156 0032 FFF7FEFF bl memcpy1 + 157 .LVL14: + 79:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** ctx->M_n += mlen; + 158 .loc 1 79 0 + 159 0036 8A22 movs r2, #138 + 160 0038 5200 lsls r2, r2, #1 + 161 003a A358 ldr r3, [r4, r2] + 162 003c FB18 adds r3, r7, r3 + 163 003e A350 str r3, [r4, r2] + 80:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** if (ctx->M_n < 16 || len == mlen) + 164 .loc 1 80 0 + 165 0040 0F2B cmp r3, #15 + 166 0042 41D9 bls .L3 + 167 .loc 1 80 0 is_stmt 0 discriminator 1 + 168 0044 B045 cmp r8, r6 + 169 0046 3FD2 bcs .L3 + 170 .LBB2: + 81:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** return; + 82:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** XOR(ctx->M_last, ctx->X); + 171 .loc 1 82 0 is_stmt 1 + 172 0048 0022 movs r2, #0 + 173 004a 09E0 b .L7 + 174 .LVL15: + 175 .L8: + 176 .loc 1 82 0 is_stmt 0 discriminator 3 + 177 004c A318 adds r3, r4, r2 + 178 004e 1800 movs r0, r3 + 179 0050 F130 adds r0, r0, #241 + 180 0052 0178 ldrb r1, [r0] + 181 0054 0233 adds r3, r3, #2 + 182 0056 FF33 adds r3, r3, #255 + 183 0058 1B78 ldrb r3, [r3] + 184 005a 4B40 eors r3, r1 + 185 005c 0370 strb r3, [r0] + 186 005e 0132 adds r2, r2, #1 + 187 .LVL16: + 188 .L7: + 189 .loc 1 82 0 discriminator 1 + 190 0060 0F2A cmp r2, #15 + 191 0062 F3DD ble .L8 + 192 .LBE2: + 83:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_encrypt(&ctx->rijndael, ctx->X, ctx->X); + 84:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** aes_encrypt( ctx->X, ctx->X, &ctx->rijndael); + 193 .loc 1 84 0 is_stmt 1 + 194 0064 2200 movs r2, r4 + 195 .LVL17: + 196 0066 2000 movs r0, r4 + 197 0068 F130 adds r0, r0, #241 + 198 006a 0100 movs r1, r0 + 199 006c FFF7FEFF bl aes_encrypt + 200 .LVL18: + 85:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** data += mlen; + 201 .loc 1 85 0 + 202 0070 ED19 adds r5, r5, r7 + 203 .LVL19: + 86:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** len -= mlen; + 204 .loc 1 86 0 + ARM GAS /tmp/ccUuuSOT.s page 6 + + + 205 0072 F61B subs r6, r6, r7 + 206 .LVL20: + 207 0074 1BE0 b .L9 + 208 .LVL21: + 209 .L10: + 210 .LBB3: + 87:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 88:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** while (len > 16) { /* not last block */ + 89:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 90:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** XOR(data, ctx->X); + 211 .loc 1 90 0 discriminator 3 + 212 0076 E218 adds r2, r4, r3 + 213 0078 F132 adds r2, r2, #241 + 214 007a 1178 ldrb r1, [r2] + 215 007c E85C ldrb r0, [r5, r3] + 216 007e 4140 eors r1, r0 + 217 0080 1170 strb r1, [r2] + 218 0082 0133 adds r3, r3, #1 + 219 .LVL22: + 220 .L11: + 221 .loc 1 90 0 is_stmt 0 discriminator 1 + 222 0084 0F2B cmp r3, #15 + 223 0086 F6DD ble .L10 + 224 .LBE3: + 91:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_encrypt(&ctx->rijndael, ctx->X, ctx->X); + 92:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 93:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memcpy1(in, &ctx->X[0], 16); //Bestela ez du ondo iten + 225 .loc 1 93 0 is_stmt 1 + 226 0088 1022 movs r2, #16 + 227 008a 2700 movs r7, r4 + 228 008c F137 adds r7, r7, #241 + 229 008e 3900 movs r1, r7 + 230 0090 6846 mov r0, sp + 231 0092 FFF7FEFF bl memcpy1 + 232 .LVL23: + 94:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** aes_encrypt( in, in, &ctx->rijndael); + 233 .loc 1 94 0 + 234 0096 2200 movs r2, r4 + 235 0098 6946 mov r1, sp + 236 009a 6846 mov r0, sp + 237 009c FFF7FEFF bl aes_encrypt + 238 .LVL24: + 95:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memcpy1(&ctx->X[0], in, 16); + 239 .loc 1 95 0 + 240 00a0 1022 movs r2, #16 + 241 00a2 6946 mov r1, sp + 242 00a4 3800 movs r0, r7 + 243 00a6 FFF7FEFF bl memcpy1 + 244 .LVL25: + 96:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 97:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** data += 16; + 245 .loc 1 97 0 + 246 00aa 1035 adds r5, r5, #16 + 247 .LVL26: + 98:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** len -= 16; + 248 .loc 1 98 0 + 249 00ac 103E subs r6, r6, #16 + ARM GAS /tmp/ccUuuSOT.s page 7 + + + 250 .LVL27: + 251 .L9: + 88:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 252 .loc 1 88 0 + 253 00ae 102E cmp r6, #16 + 254 00b0 01D9 bls .L14 + 255 .LBB4: + 90:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_encrypt(&ctx->rijndael, ctx->X, ctx->X); + 256 .loc 1 90 0 + 257 00b2 0023 movs r3, #0 + 258 00b4 E6E7 b .L11 + 259 .L14: + 260 .LBE4: + 99:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 100:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /* potential last block, save it */ + 101:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memcpy1(ctx->M_last, data, len); + 261 .loc 1 101 0 + 262 00b6 A01C adds r0, r4, #2 + 263 00b8 FF30 adds r0, r0, #255 + 264 00ba B2B2 uxth r2, r6 + 265 00bc 2900 movs r1, r5 + 266 00be FFF7FEFF bl memcpy1 + 267 .LVL28: + 102:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** ctx->M_n = len; + 268 .loc 1 102 0 + 269 00c2 8A23 movs r3, #138 + 270 00c4 5B00 lsls r3, r3, #1 + 271 00c6 E650 str r6, [r4, r3] + 272 .L3: + 103:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 273 .loc 1 103 0 + 274 00c8 04B0 add sp, sp, #16 + 275 @ sp needed + 276 .LVL29: + 277 .LVL30: + 278 .LVL31: + 279 00ca 04BC pop {r2} + 280 00cc 9046 mov r8, r2 + 281 00ce F0BD pop {r4, r5, r6, r7, pc} + 282 .cfi_endproc + 283 .LFE84: + 285 .section .text.AES_CMAC_Final,"ax",%progbits + 286 .align 1 + 287 .global AES_CMAC_Final + 288 .syntax unified + 289 .code 16 + 290 .thumb_func + 291 .fpu softvfp + 293 AES_CMAC_Final: + 294 .LFB85: + 104:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 105:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** void AES_CMAC_Final(uint8_t digest[AES_CMAC_DIGEST_LENGTH], AES_CMAC_CTX *ctx) + 106:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** { + 295 .loc 1 106 0 + 296 .cfi_startproc + 297 @ args = 0, pretend = 0, frame = 32 + 298 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccUuuSOT.s page 8 + + + 299 .LVL32: + 300 0000 70B5 push {r4, r5, r6, lr} + 301 .LCFI5: + 302 .cfi_def_cfa_offset 16 + 303 .cfi_offset 4, -16 + 304 .cfi_offset 5, -12 + 305 .cfi_offset 6, -8 + 306 .cfi_offset 14, -4 + 307 0002 88B0 sub sp, sp, #32 + 308 .LCFI6: + 309 .cfi_def_cfa_offset 48 + 310 0004 0400 movs r4, r0 + 311 0006 0D00 movs r5, r1 + 107:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** uint8_t K[16]; + 108:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** uint8_t in[16]; + 109:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /* generate subkey K1 */ + 110:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memset1(K, '\0', 16); + 312 .loc 1 110 0 + 313 0008 04AE add r6, sp, #16 + 314 000a 1022 movs r2, #16 + 315 000c 0021 movs r1, #0 + 316 .LVL33: + 317 000e 3000 movs r0, r6 + 318 .LVL34: + 319 0010 FFF7FEFF bl memset1 + 320 .LVL35: + 111:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 112:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_encrypt(&ctx->rijndael, K, K); + 113:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 114:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** aes_encrypt( K, K, &ctx->rijndael); + 321 .loc 1 114 0 + 322 0014 2A00 movs r2, r5 + 323 0016 3100 movs r1, r6 + 324 0018 3000 movs r0, r6 + 325 001a FFF7FEFF bl aes_encrypt + 326 .LVL36: + 115:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 116:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** if (K[0] & 0x80) { + 327 .loc 1 116 0 + 328 001e 0023 movs r3, #0 + 329 0020 F356 ldrsb r3, [r6, r3] + 330 0022 002B cmp r3, #0 + 331 0024 15DB blt .L36 + 332 .LBB5: + 117:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 118:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** K[15] ^= 0x87; + 119:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } else + 120:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 333 .loc 1 120 0 + 334 0026 0022 movs r2, #0 + 335 0028 1EE0 b .L17 + 336 .LVL37: + 337 .L18: + 338 .LBE5: + 339 .LBB6: + 117:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 340 .loc 1 117 0 discriminator 3 + ARM GAS /tmp/ccUuuSOT.s page 9 + + + 341 002a 04A9 add r1, sp, #16 + 342 002c 885C ldrb r0, [r1, r2] + 343 002e 4000 lsls r0, r0, #1 + 344 0030 561C adds r6, r2, #1 + 345 0032 8B5D ldrb r3, [r1, r6] + 346 0034 DB09 lsrs r3, r3, #7 + 347 0036 0343 orrs r3, r0 + 348 0038 8B54 strb r3, [r1, r2] + 349 .LVL38: + 350 003a 3200 movs r2, r6 + 351 .LVL39: + 352 .L16: + 117:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 353 .loc 1 117 0 is_stmt 0 discriminator 1 + 354 003c 0E2A cmp r2, #14 + 355 003e F4DD ble .L18 + 117:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 356 .loc 1 117 0 discriminator 4 + 357 0040 04A9 add r1, sp, #16 + 358 0042 CB7B ldrb r3, [r1, #15] + 359 0044 5B00 lsls r3, r3, #1 + 360 0046 DBB2 uxtb r3, r3 + 361 .LBE6: + 118:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } else + 362 .loc 1 118 0 is_stmt 1 discriminator 4 + 363 0048 7922 movs r2, #121 + 364 .LVL40: + 365 004a 5242 rsbs r2, r2, #0 + 366 004c 5340 eors r3, r2 + 367 004e CB73 strb r3, [r1, #15] + 368 0050 10E0 b .L19 + 369 .L36: + 370 .LBB7: + 117:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 371 .loc 1 117 0 + 372 0052 0022 movs r2, #0 + 373 0054 F2E7 b .L16 + 374 .LVL41: + 375 .L20: + 376 .LBE7: + 377 .LBB8: + 378 .loc 1 120 0 discriminator 3 + 379 0056 04A9 add r1, sp, #16 + 380 0058 885C ldrb r0, [r1, r2] + 381 005a 4000 lsls r0, r0, #1 + 382 005c 561C adds r6, r2, #1 + 383 005e 8B5D ldrb r3, [r1, r6] + 384 0060 DB09 lsrs r3, r3, #7 + 385 0062 0343 orrs r3, r0 + 386 0064 8B54 strb r3, [r1, r2] + 387 .LVL42: + 388 0066 3200 movs r2, r6 + 389 .LVL43: + 390 .L17: + 391 .loc 1 120 0 is_stmt 0 discriminator 1 + 392 0068 0E2A cmp r2, #14 + 393 006a F4DD ble .L20 + ARM GAS /tmp/ccUuuSOT.s page 10 + + + 394 .loc 1 120 0 discriminator 4 + 395 006c 04AA add r2, sp, #16 + 396 .LVL44: + 397 006e D37B ldrb r3, [r2, #15] + 398 0070 5B00 lsls r3, r3, #1 + 399 0072 D373 strb r3, [r2, #15] + 400 .L19: + 401 .LBE8: + 121:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 122:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 123:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** if (ctx->M_n == 16) { + 402 .loc 1 123 0 is_stmt 1 + 403 0074 8A23 movs r3, #138 + 404 0076 5B00 lsls r3, r3, #1 + 405 0078 EB58 ldr r3, [r5, r3] + 406 007a 102B cmp r3, #16 + 407 007c 12D0 beq .L40 + 124:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /* last block was a complete block */ + 125:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** XOR(K, ctx->M_last); + 126:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 127:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } else { + 128:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /* generate subkey K2 */ + 129:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** if (K[0] & 0x80) { + 408 .loc 1 129 0 + 409 007e 04AB add r3, sp, #16 + 410 0080 1B78 ldrb r3, [r3] + 411 0082 5BB2 sxtb r3, r3 + 412 0084 002B cmp r3, #0 + 413 0086 23DB blt .L38 + 414 .LBB9: + 130:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 131:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** K[15] ^= 0x87; + 132:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } else + 133:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 415 .loc 1 133 0 + 416 0088 0022 movs r2, #0 + 417 008a 2CE0 b .L26 + 418 .LVL45: + 419 .L23: + 420 .LBE9: + 421 .LBB10: + 125:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 422 .loc 1 125 0 discriminator 3 + 423 008c EA18 adds r2, r5, r3 + 424 008e 0232 adds r2, r2, #2 + 425 0090 FF32 adds r2, r2, #255 + 426 0092 1178 ldrb r1, [r2] + 427 0094 04A8 add r0, sp, #16 + 428 0096 C05C ldrb r0, [r0, r3] + 429 0098 4140 eors r1, r0 + 430 009a 1170 strb r1, [r2] + 431 009c 0133 adds r3, r3, #1 + 432 .LVL46: + 433 .L21: + 125:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 434 .loc 1 125 0 is_stmt 0 discriminator 1 + 435 009e 0F2B cmp r3, #15 + ARM GAS /tmp/ccUuuSOT.s page 11 + + + 436 00a0 F4DD ble .L23 + 437 00a2 48E0 b .L24 + 438 .LVL47: + 439 .L40: + 125:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 440 .loc 1 125 0 + 441 00a4 0023 movs r3, #0 + 442 00a6 FAE7 b .L21 + 443 .LVL48: + 444 .L27: + 445 .LBE10: + 446 .LBB11: + 130:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 447 .loc 1 130 0 is_stmt 1 discriminator 3 + 448 00a8 04A9 add r1, sp, #16 + 449 00aa 885C ldrb r0, [r1, r2] + 450 00ac 4000 lsls r0, r0, #1 + 451 00ae 561C adds r6, r2, #1 + 452 00b0 8B5D ldrb r3, [r1, r6] + 453 00b2 DB09 lsrs r3, r3, #7 + 454 00b4 0343 orrs r3, r0 + 455 00b6 8B54 strb r3, [r1, r2] + 456 .LVL49: + 457 00b8 3200 movs r2, r6 + 458 .LVL50: + 459 .L25: + 130:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 460 .loc 1 130 0 is_stmt 0 discriminator 1 + 461 00ba 0E2A cmp r2, #14 + 462 00bc F4DD ble .L27 + 130:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 463 .loc 1 130 0 discriminator 4 + 464 00be 04A9 add r1, sp, #16 + 465 00c0 CB7B ldrb r3, [r1, #15] + 466 00c2 5B00 lsls r3, r3, #1 + 467 00c4 DBB2 uxtb r3, r3 + 468 .LBE11: + 131:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } else + 469 .loc 1 131 0 is_stmt 1 discriminator 4 + 470 00c6 7922 movs r2, #121 + 471 .LVL51: + 472 00c8 5242 rsbs r2, r2, #0 + 473 00ca 5340 eors r3, r2 + 474 00cc CB73 strb r3, [r1, #15] + 475 00ce 10E0 b .L28 + 476 .L38: + 477 .LBB12: + 130:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** LSHIFT(K, K); + 478 .loc 1 130 0 + 479 00d0 0022 movs r2, #0 + 480 00d2 F2E7 b .L25 + 481 .LVL52: + 482 .L29: + 483 .LBE12: + 484 .LBB13: + 485 .loc 1 133 0 discriminator 3 + 486 00d4 04A9 add r1, sp, #16 + ARM GAS /tmp/ccUuuSOT.s page 12 + + + 487 00d6 885C ldrb r0, [r1, r2] + 488 00d8 4000 lsls r0, r0, #1 + 489 00da 561C adds r6, r2, #1 + 490 00dc 8B5D ldrb r3, [r1, r6] + 491 00de DB09 lsrs r3, r3, #7 + 492 00e0 0343 orrs r3, r0 + 493 00e2 8B54 strb r3, [r1, r2] + 494 .LVL53: + 495 00e4 3200 movs r2, r6 + 496 .LVL54: + 497 .L26: + 498 .loc 1 133 0 is_stmt 0 discriminator 1 + 499 00e6 0E2A cmp r2, #14 + 500 00e8 F4DD ble .L29 + 501 .loc 1 133 0 discriminator 4 + 502 00ea 04AA add r2, sp, #16 + 503 .LVL55: + 504 00ec D37B ldrb r3, [r2, #15] + 505 00ee 5B00 lsls r3, r3, #1 + 506 00f0 D373 strb r3, [r2, #15] + 507 .L28: + 508 .LBE13: + 134:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 135:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** /* padding(M_last) */ + 136:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** ctx->M_last[ctx->M_n] = 0x80; + 509 .loc 1 136 0 is_stmt 1 + 510 00f2 8A23 movs r3, #138 + 511 00f4 5B00 lsls r3, r3, #1 + 512 00f6 EB58 ldr r3, [r5, r3] + 513 00f8 EB18 adds r3, r5, r3 + 514 00fa 0233 adds r3, r3, #2 + 515 00fc FF33 adds r3, r3, #255 + 516 00fe 8022 movs r2, #128 + 517 0100 1A70 strb r2, [r3] + 137:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** while (++ctx->M_n < 16) + 518 .loc 1 137 0 + 519 0102 04E0 b .L30 + 520 .L31: + 138:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** ctx->M_last[ctx->M_n] = 0; + 521 .loc 1 138 0 + 522 0104 EB18 adds r3, r5, r3 + 523 0106 0233 adds r3, r3, #2 + 524 0108 FF33 adds r3, r3, #255 + 525 010a 0022 movs r2, #0 + 526 010c 1A70 strb r2, [r3] + 527 .L30: + 137:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** while (++ctx->M_n < 16) + 528 .loc 1 137 0 + 529 010e 8A22 movs r2, #138 + 530 0110 5200 lsls r2, r2, #1 + 531 0112 AB58 ldr r3, [r5, r2] + 532 0114 0133 adds r3, r3, #1 + 533 0116 AB50 str r3, [r5, r2] + 534 0118 0F2B cmp r3, #15 + 535 011a F3D9 bls .L31 + 536 .LBB14: + 139:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + ARM GAS /tmp/ccUuuSOT.s page 13 + + + 140:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** XOR(K, ctx->M_last); + 537 .loc 1 140 0 + 538 011c 0023 movs r3, #0 + 539 011e 08E0 b .L32 + 540 .LVL56: + 541 .L33: + 542 .loc 1 140 0 is_stmt 0 discriminator 3 + 543 0120 EA18 adds r2, r5, r3 + 544 0122 0232 adds r2, r2, #2 + 545 0124 FF32 adds r2, r2, #255 + 546 0126 1178 ldrb r1, [r2] + 547 0128 04A8 add r0, sp, #16 + 548 012a C05C ldrb r0, [r0, r3] + 549 012c 4140 eors r1, r0 + 550 012e 1170 strb r1, [r2] + 551 0130 0133 adds r3, r3, #1 + 552 .LVL57: + 553 .L32: + 554 .loc 1 140 0 discriminator 1 + 555 0132 0F2B cmp r3, #15 + 556 0134 F4DD ble .L33 + 557 .LVL58: + 558 .L24: + 559 0136 0022 movs r2, #0 + 560 0138 09E0 b .L34 + 561 .LVL59: + 562 .L35: + 563 .LBE14: + 564 .LBB15: + 141:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 142:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 143:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 144:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** XOR(ctx->M_last, ctx->X); + 565 .loc 1 144 0 is_stmt 1 discriminator 3 + 566 013a AB18 adds r3, r5, r2 + 567 013c 1800 movs r0, r3 + 568 013e F130 adds r0, r0, #241 + 569 0140 0178 ldrb r1, [r0] + 570 0142 0233 adds r3, r3, #2 + 571 0144 FF33 adds r3, r3, #255 + 572 0146 1B78 ldrb r3, [r3] + 573 0148 4B40 eors r3, r1 + 574 014a 0370 strb r3, [r0] + 575 014c 0132 adds r2, r2, #1 + 576 .LVL60: + 577 .L34: + 578 .loc 1 144 0 is_stmt 0 discriminator 1 + 579 014e 0F2A cmp r2, #15 + 580 0150 F3DD ble .L35 + 581 .LBE15: + 145:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 146:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** //rijndael_encrypt(&ctx->rijndael, ctx->X, digest); + 147:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 148:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memcpy1(in, &ctx->X[0], 16); //Bestela ez du ondo iten + 582 .loc 1 148 0 is_stmt 1 + 583 0152 2900 movs r1, r5 + 584 0154 F131 adds r1, r1, #241 + ARM GAS /tmp/ccUuuSOT.s page 14 + + + 585 0156 1022 movs r2, #16 + 586 .LVL61: + 587 0158 6846 mov r0, sp + 588 015a FFF7FEFF bl memcpy1 + 589 .LVL62: + 149:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** aes_encrypt(in, digest, &ctx->rijndael); + 590 .loc 1 149 0 + 591 015e 2A00 movs r2, r5 + 592 0160 2100 movs r1, r4 + 593 0162 6846 mov r0, sp + 594 0164 FFF7FEFF bl aes_encrypt + 595 .LVL63: + 150:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** memset1(K, 0, sizeof K); + 596 .loc 1 150 0 + 597 0168 1022 movs r2, #16 + 598 016a 0021 movs r1, #0 + 599 016c 04A8 add r0, sp, #16 + 600 016e FFF7FEFF bl memset1 + 601 .LVL64: + 151:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** + 152:./Middlewares/Third_Party/Lora/Crypto/cmac.c **** } + 602 .loc 1 152 0 + 603 0172 08B0 add sp, sp, #32 + 604 @ sp needed + 605 .LVL65: + 606 .LVL66: + 607 0174 70BD pop {r4, r5, r6, pc} + 608 .cfi_endproc + 609 .LFE85: + 611 .text + 612 .Letext0: + 613 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 614 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 615 .file 4 "./Middlewares/Third_Party/Lora/Crypto/aes.h" + 616 .file 5 "./Middlewares/Third_Party/Lora/Crypto/cmac.h" + 617 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 618 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 619 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 620 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 621 .file 10 "/usr/arm-none-eabi/include/math.h" + 622 .file 11 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + ARM GAS /tmp/ccUuuSOT.s page 15 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 cmac.c + /tmp/ccUuuSOT.s:16 .text.AES_CMAC_Init:0000000000000000 $t + /tmp/ccUuuSOT.s:23 .text.AES_CMAC_Init:0000000000000000 AES_CMAC_Init + /tmp/ccUuuSOT.s:63 .text.AES_CMAC_SetKey:0000000000000000 $t + /tmp/ccUuuSOT.s:70 .text.AES_CMAC_SetKey:0000000000000000 AES_CMAC_SetKey + /tmp/ccUuuSOT.s:97 .text.AES_CMAC_Update:0000000000000000 $t + /tmp/ccUuuSOT.s:104 .text.AES_CMAC_Update:0000000000000000 AES_CMAC_Update + /tmp/ccUuuSOT.s:286 .text.AES_CMAC_Final:0000000000000000 $t + /tmp/ccUuuSOT.s:293 .text.AES_CMAC_Final:0000000000000000 AES_CMAC_Final + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +memset1 +aes_set_key +memcpy1 +aes_encrypt diff --git a/build/debug.d b/build/debug.d new file mode 100644 index 0000000..11d6d9d --- /dev/null +++ b/build/debug.d @@ -0,0 +1,135 @@ +build/debug.d: Src/debug.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: diff --git a/build/debug.lst b/build/debug.lst new file mode 100644 index 0000000..e7d7652 --- /dev/null +++ b/build/debug.lst @@ -0,0 +1,326 @@ +ARM GAS /tmp/ccWwZZVi.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "debug.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.DBG_Init,"ax",%progbits + 16 .align 1 + 17 .global DBG_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 DBG_Init: + 24 .LFB96: + 25 .file 1 "./Src/debug.c" + 1:./Src/debug.c **** + 2:./Src/debug.c **** /****************************************************************************** + 3:./Src/debug.c **** * @file debug.c + 4:./Src/debug.c **** * @author MCD Application Team + 5:./Src/debug.c **** * @version V1.1.2 + 6:./Src/debug.c **** * @date 08-September-2017 + 7:./Src/debug.c **** * @brief debug API + 8:./Src/debug.c **** ****************************************************************************** + 9:./Src/debug.c **** * @attention + 10:./Src/debug.c **** * + 11:./Src/debug.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 12:./Src/debug.c **** * All rights reserved.

+ 13:./Src/debug.c **** * + 14:./Src/debug.c **** * Redistribution and use in source and binary forms, with or without + 15:./Src/debug.c **** * modification, are permitted, provided that the following conditions are met: + 16:./Src/debug.c **** * + 17:./Src/debug.c **** * 1. Redistribution of source code must retain the above copyright notice, + 18:./Src/debug.c **** * this list of conditions and the following disclaimer. + 19:./Src/debug.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 20:./Src/debug.c **** * this list of conditions and the following disclaimer in the documentation + 21:./Src/debug.c **** * and/or other materials provided with the distribution. + 22:./Src/debug.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 23:./Src/debug.c **** * contributors to this software may be used to endorse or promote products + 24:./Src/debug.c **** * derived from this software without specific written permission. + 25:./Src/debug.c **** * 4. This software, including modifications and/or derivative works of this + 26:./Src/debug.c **** * software, must execute solely and exclusively on microcontroller or + 27:./Src/debug.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 28:./Src/debug.c **** * 5. Redistribution and use of this software other than as permitted under + 29:./Src/debug.c **** * this license is void and will automatically terminate your rights under + 30:./Src/debug.c **** * this license. + 31:./Src/debug.c **** * + 32:./Src/debug.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 33:./Src/debug.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + ARM GAS /tmp/ccWwZZVi.s page 2 + + + 34:./Src/debug.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 35:./Src/debug.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 36:./Src/debug.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 37:./Src/debug.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 38:./Src/debug.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 39:./Src/debug.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 40:./Src/debug.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 41:./Src/debug.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 42:./Src/debug.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 43:./Src/debug.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 44:./Src/debug.c **** * + 45:./Src/debug.c **** ****************************************************************************** + 46:./Src/debug.c **** */ + 47:./Src/debug.c **** + 48:./Src/debug.c **** /* Includes ------------------------------------------------------------------*/ + 49:./Src/debug.c **** #include "hw.h" + 50:./Src/debug.c **** + 51:./Src/debug.c **** /** + 52:./Src/debug.c **** * @brief Initializes the debug + 53:./Src/debug.c **** * @param None + 54:./Src/debug.c **** * @retval None + 55:./Src/debug.c **** */ + 56:./Src/debug.c **** void DBG_Init( void ) + 57:./Src/debug.c **** { + 26 .loc 1 57 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 24 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 30B5 push {r4, r5, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 12 + 33 .cfi_offset 4, -12 + 34 .cfi_offset 5, -8 + 35 .cfi_offset 14, -4 + 36 0002 87B0 sub sp, sp, #28 + 37 .LCFI1: + 38 .cfi_def_cfa_offset 40 + 58:./Src/debug.c **** #ifdef DEBUG + 59:./Src/debug.c **** GPIO_InitTypeDef gpioinitstruct = {0}; + 60:./Src/debug.c **** + 61:./Src/debug.c **** /* Enable the GPIO_B Clock */ + 62:./Src/debug.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 63:./Src/debug.c **** + 64:./Src/debug.c **** /* Configure the GPIO pin */ + 65:./Src/debug.c **** gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + 66:./Src/debug.c **** gpioinitstruct.Pull = GPIO_PULLUP; + 67:./Src/debug.c **** gpioinitstruct.Speed = GPIO_SPEED_HIGH; + 68:./Src/debug.c **** + 69:./Src/debug.c **** gpioinitstruct.Pin = (GPIO_PIN_12 | GPIO_PIN_13| GPIO_PIN_14 | GPIO_PIN_15); + 70:./Src/debug.c **** HAL_GPIO_Init(GPIOB, &gpioinitstruct); + 71:./Src/debug.c **** + 72:./Src/debug.c **** /* Reset debug Pins */ + 73:./Src/debug.c **** HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); + 74:./Src/debug.c **** HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET); + 75:./Src/debug.c **** HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); + 76:./Src/debug.c **** HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, GPIO_PIN_RESET); + 77:./Src/debug.c **** #if 0 + ARM GAS /tmp/ccWwZZVi.s page 3 + + + 78:./Src/debug.c **** HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); + 79:./Src/debug.c **** #endif + 80:./Src/debug.c **** + 81:./Src/debug.c **** __HAL_RCC_DBGMCU_CLK_ENABLE( ); + 82:./Src/debug.c **** + 83:./Src/debug.c **** HAL_DBGMCU_EnableDBGSleepMode( ); + 84:./Src/debug.c **** HAL_DBGMCU_EnableDBGStopMode( ); + 85:./Src/debug.c **** HAL_DBGMCU_EnableDBGStandbyMode( ); + 86:./Src/debug.c **** + 87:./Src/debug.c **** #else /* DEBUG */ + 88:./Src/debug.c **** /* sw interface off*/ + 89:./Src/debug.c **** GPIO_InitTypeDef GPIO_InitStructure ={0}; + 39 .loc 1 89 0 + 40 0004 0C22 movs r2, #12 + 41 0006 0021 movs r1, #0 + 42 0008 03A8 add r0, sp, #12 + 43 000a FFF7FEFF bl memset + 44 .LVL0: + 90:./Src/debug.c **** + 91:./Src/debug.c **** GPIO_InitStructure.Mode = GPIO_MODE_ANALOG; + 45 .loc 1 91 0 + 46 000e 0323 movs r3, #3 + 47 0010 0293 str r3, [sp, #8] + 92:./Src/debug.c **** GPIO_InitStructure.Pull = GPIO_NOPULL; + 93:./Src/debug.c **** GPIO_InitStructure.Pin = (GPIO_PIN_13 | GPIO_PIN_14); + 48 .loc 1 93 0 + 49 0012 C023 movs r3, #192 + 50 0014 DB01 lsls r3, r3, #7 + 51 0016 0193 str r3, [sp, #4] + 52 .LBB2: + 94:./Src/debug.c **** __GPIOA_CLK_ENABLE() ; + 53 .loc 1 94 0 + 54 0018 104C ldr r4, .L2 + 55 001a E36A ldr r3, [r4, #44] + 56 001c 0125 movs r5, #1 + 57 001e 2B43 orrs r3, r5 + 58 0020 E362 str r3, [r4, #44] + 59 0022 E36A ldr r3, [r4, #44] + 60 0024 2B40 ands r3, r5 + 61 0026 0093 str r3, [sp] + 62 0028 009B ldr r3, [sp] + 63 .LBE2: + 95:./Src/debug.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + 64 .loc 1 95 0 + 65 002a A020 movs r0, #160 + 66 002c 01A9 add r1, sp, #4 + 67 002e C005 lsls r0, r0, #23 + 68 0030 FFF7FEFF bl HAL_GPIO_Init + 69 .LVL1: + 96:./Src/debug.c **** __GPIOA_CLK_DISABLE() ; + 70 .loc 1 96 0 + 71 0034 E36A ldr r3, [r4, #44] + 72 0036 AB43 bics r3, r5 + 73 0038 E362 str r3, [r4, #44] + 97:./Src/debug.c **** + 98:./Src/debug.c **** __HAL_RCC_DBGMCU_CLK_ENABLE( ); + 74 .loc 1 98 0 + ARM GAS /tmp/ccWwZZVi.s page 4 + + + 75 003a 626B ldr r2, [r4, #52] + 76 003c 8023 movs r3, #128 + 77 003e DB03 lsls r3, r3, #15 + 78 0040 1343 orrs r3, r2 + 79 0042 6363 str r3, [r4, #52] + 99:./Src/debug.c **** HAL_DBGMCU_DisableDBGSleepMode( ); + 80 .loc 1 99 0 + 81 0044 FFF7FEFF bl HAL_DBGMCU_DisableDBGSleepMode + 82 .LVL2: + 100:./Src/debug.c **** HAL_DBGMCU_DisableDBGStopMode( ); + 83 .loc 1 100 0 + 84 0048 FFF7FEFF bl HAL_DBGMCU_DisableDBGStopMode + 85 .LVL3: + 101:./Src/debug.c **** HAL_DBGMCU_DisableDBGStandbyMode( ); + 86 .loc 1 101 0 + 87 004c FFF7FEFF bl HAL_DBGMCU_DisableDBGStandbyMode + 88 .LVL4: + 102:./Src/debug.c **** __HAL_RCC_DBGMCU_CLK_DISABLE( ); + 89 .loc 1 102 0 + 90 0050 636B ldr r3, [r4, #52] + 91 0052 034A ldr r2, .L2+4 + 92 0054 1340 ands r3, r2 + 93 0056 6363 str r3, [r4, #52] + 103:./Src/debug.c **** #endif + 104:./Src/debug.c **** } + 94 .loc 1 104 0 + 95 0058 07B0 add sp, sp, #28 + 96 @ sp needed + 97 005a 30BD pop {r4, r5, pc} + 98 .L3: + 99 .align 2 + 100 .L2: + 101 005c 00100240 .word 1073876992 + 102 0060 FFFFBFFF .word -4194305 + 103 .cfi_endproc + 104 .LFE96: + 106 .section .text._Error_Handler,"ax",%progbits + 107 .align 1 + 108 .global _Error_Handler + 109 .syntax unified + 110 .code 16 + 111 .thumb_func + 112 .fpu softvfp + 114 _Error_Handler: + 115 .LFB97: + 105:./Src/debug.c **** + 106:./Src/debug.c **** #if 0 + 107:./Src/debug.c **** /** + 108:./Src/debug.c **** * @brief Error_Handler + 109:./Src/debug.c **** * @param None + 110:./Src/debug.c **** * @retval None + 111:./Src/debug.c **** */ + 112:./Src/debug.c **** void Error_Handler(void) + 113:./Src/debug.c **** { + 114:./Src/debug.c **** DBG_PRINTF("Error_Handler\n\r"); + 115:./Src/debug.c **** while(1); + 116:./Src/debug.c **** } + ARM GAS /tmp/ccWwZZVi.s page 5 + + + 117:./Src/debug.c **** #endif + 118:./Src/debug.c **** + 119:./Src/debug.c **** void _Error_Handler(char * file, int line) + 120:./Src/debug.c **** { + 116 .loc 1 120 0 + 117 .cfi_startproc + 118 @ args = 0, pretend = 0, frame = 0 + 119 @ frame_needed = 0, uses_anonymous_args = 0 + 120 .LVL5: + 121 0000 10B5 push {r4, lr} + 122 .LCFI2: + 123 .cfi_def_cfa_offset 8 + 124 .cfi_offset 4, -8 + 125 .cfi_offset 14, -4 + 121:./Src/debug.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 122:./Src/debug.c **** PRINTF("INIT ERROR, %s:%d", file, (uint16_t) line); + 126 .loc 1 122 0 + 127 0002 0A04 lsls r2, r1, #16 + 128 0004 120C lsrs r2, r2, #16 + 129 0006 0100 movs r1, r0 + 130 .LVL6: + 131 0008 0148 ldr r0, .L5 + 132 .LVL7: + 133 000a FFF7FEFF bl vcom_Send + 134 .LVL8: + 123:./Src/debug.c **** /* USER CODE END Error_Handler_Debug */ + 124:./Src/debug.c **** } + 135 .loc 1 124 0 + 136 @ sp needed + 137 000e 10BD pop {r4, pc} + 138 .L6: + 139 .align 2 + 140 .L5: + 141 0010 00000000 .word .LC0 + 142 .cfi_endproc + 143 .LFE97: + 145 .section .rodata._Error_Handler.str1.4,"aMS",%progbits,1 + 146 .align 2 + 147 .LC0: + 148 0000 494E4954 .ascii "INIT ERROR, %s:%d\000" + 148 20455252 + 148 4F522C20 + 148 25733A25 + 148 6400 + 149 .text + 150 .Letext0: + 151 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 152 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 153 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 154 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 155 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 156 .file 7 "/usr/arm-none-eabi/include/math.h" + 157 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 158 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 159 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 160 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 161 .file 12 "Inc/vcom.h" + ARM GAS /tmp/ccWwZZVi.s page 6 + + + 162 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 163 .file 14 "" + ARM GAS /tmp/ccWwZZVi.s page 7 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 debug.c + /tmp/ccWwZZVi.s:16 .text.DBG_Init:0000000000000000 $t + /tmp/ccWwZZVi.s:23 .text.DBG_Init:0000000000000000 DBG_Init + /tmp/ccWwZZVi.s:101 .text.DBG_Init:000000000000005c $d + /tmp/ccWwZZVi.s:107 .text._Error_Handler:0000000000000000 $t + /tmp/ccWwZZVi.s:114 .text._Error_Handler:0000000000000000 _Error_Handler + /tmp/ccWwZZVi.s:141 .text._Error_Handler:0000000000000010 $d + /tmp/ccWwZZVi.s:146 .rodata._Error_Handler.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +memset +HAL_GPIO_Init +HAL_DBGMCU_DisableDBGSleepMode +HAL_DBGMCU_DisableDBGStopMode +HAL_DBGMCU_DisableDBGStandbyMode +vcom_Send diff --git a/build/delay.d b/build/delay.d new file mode 100644 index 0000000..98ea7f9 --- /dev/null +++ b/build/delay.d @@ -0,0 +1,141 @@ +build/delay.d: Middlewares/Third_Party/Lora/Utilities/delay.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: diff --git a/build/delay.lst b/build/delay.lst new file mode 100644 index 0000000..992cf05 --- /dev/null +++ b/build/delay.lst @@ -0,0 +1,199 @@ +ARM GAS /tmp/ccRLwJE7.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "delay.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.DelayMs,"ax",%progbits + 16 .align 1 + 17 .global DelayMs + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 DelayMs: + 24 .LFB96: + 25 .file 1 "./Middlewares/Third_Party/Lora/Utilities/delay.c" + 1:./Middlewares/Third_Party/Lora/Utilities/delay.c **** /* + 2:./Middlewares/Third_Party/Lora/Utilities/delay.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Utilities/delay.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Utilities/delay.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Utilities/delay.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Utilities/delay.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Utilities/delay.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 9:./Middlewares/Third_Party/Lora/Utilities/delay.c **** Description: Delay functions implementation + 10:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 11:./Middlewares/Third_Party/Lora/Utilities/delay.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 13:./Middlewares/Third_Party/Lora/Utilities/delay.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Middlewares/Third_Party/Lora/Utilities/delay.c **** */ + 15:./Middlewares/Third_Party/Lora/Utilities/delay.c **** /****************************************************************************** + 16:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @file delay.c + 17:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @author MCD Application Team + 18:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @version V1.1.2 + 19:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @date 08-September-2017 + 20:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @brief Delay function + 21:./Middlewares/Third_Party/Lora/Utilities/delay.c **** ****************************************************************************** + 22:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * @attention + 23:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * + 24:./Middlewares/Third_Party/Lora/Utilities/delay.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * All rights reserved.

+ 26:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * + 27:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * Redistribution and use in source and binary forms, with or without + 28:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * + 30:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * this list of conditions and the following disclaimer. + 32:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/ccRLwJE7.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * and/or other materials provided with the distribution. + 35:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * contributors to this software may be used to endorse or promote products + 37:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * derived from this software without specific written permission. + 38:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * this license is void and will automatically terminate your rights under + 43:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * this license. + 44:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * + 45:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Middlewares/Third_Party/Lora/Utilities/delay.c **** * + 58:./Middlewares/Third_Party/Lora/Utilities/delay.c **** ****************************************************************************** + 59:./Middlewares/Third_Party/Lora/Utilities/delay.c **** */ + 60:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 61:./Middlewares/Third_Party/Lora/Utilities/delay.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Middlewares/Third_Party/Lora/Utilities/delay.c **** #include "hw.h" + 63:./Middlewares/Third_Party/Lora/Utilities/delay.c **** #include "timeServer.h" + 64:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 65:./Middlewares/Third_Party/Lora/Utilities/delay.c **** void DelayMs( uint32_t ms ) + 66:./Middlewares/Third_Party/Lora/Utilities/delay.c **** { + 26 .loc 1 66 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 10B5 push {r4, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 4, -8 + 35 .cfi_offset 14, -4 + 67:./Middlewares/Third_Party/Lora/Utilities/delay.c **** HW_RTC_DelayMs( ms ); + 36 .loc 1 67 0 + 37 0002 FFF7FEFF bl HW_RTC_DelayMs + 38 .LVL1: + 68:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 69:./Middlewares/Third_Party/Lora/Utilities/delay.c **** } + 39 .loc 1 69 0 + 40 @ sp needed + 41 0006 10BD pop {r4, pc} + 42 .cfi_endproc + 43 .LFE96: + 45 .global __aeabi_fmul + 46 .global __aeabi_f2uiz + 47 .section .text.Delay,"ax",%progbits + ARM GAS /tmp/ccRLwJE7.s page 3 + + + 48 .align 1 + 49 .global Delay + 50 .syntax unified + 51 .code 16 + 52 .thumb_func + 53 .fpu softvfp + 55 Delay: + 56 .LFB97: + 70:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 71:./Middlewares/Third_Party/Lora/Utilities/delay.c **** void Delay( float s ) + 72:./Middlewares/Third_Party/Lora/Utilities/delay.c **** { + 57 .loc 1 72 0 + 58 .cfi_startproc + 59 @ args = 0, pretend = 0, frame = 0 + 60 @ frame_needed = 0, uses_anonymous_args = 0 + 61 .LVL2: + 62 0000 10B5 push {r4, lr} + 63 .LCFI1: + 64 .cfi_def_cfa_offset 8 + 65 .cfi_offset 4, -8 + 66 .cfi_offset 14, -4 + 73:./Middlewares/Third_Party/Lora/Utilities/delay.c **** DelayMs( (uint32_t) (s * 1000.0f) ); + 67 .loc 1 73 0 + 68 0002 0449 ldr r1, .L3 + 69 0004 FFF7FEFF bl __aeabi_fmul + 70 .LVL3: + 71 0008 FFF7FEFF bl __aeabi_f2uiz + 72 .LVL4: + 73 .LBB4: + 74 .LBB5: + 67:./Middlewares/Third_Party/Lora/Utilities/delay.c **** + 75 .loc 1 67 0 + 76 000c FFF7FEFF bl HW_RTC_DelayMs + 77 .LVL5: + 78 .LBE5: + 79 .LBE4: + 74:./Middlewares/Third_Party/Lora/Utilities/delay.c **** } + 80 .loc 1 74 0 + 81 @ sp needed + 82 0010 10BD pop {r4, pc} + 83 .L4: + 84 0012 C046 .align 2 + 85 .L3: + 86 0014 00007A44 .word 1148846080 + 87 .cfi_endproc + 88 .LFE97: + 90 .text + 91 .Letext0: + 92 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 93 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 94 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 95 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 96 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 97 .file 7 "/usr/arm-none-eabi/include/math.h" + 98 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 99 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 100 .file 10 "Inc/hw_rtc.h" + ARM GAS /tmp/ccRLwJE7.s page 4 + + + ARM GAS /tmp/ccRLwJE7.s page 5 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 delay.c + /tmp/ccRLwJE7.s:16 .text.DelayMs:0000000000000000 $t + /tmp/ccRLwJE7.s:23 .text.DelayMs:0000000000000000 DelayMs + /tmp/ccRLwJE7.s:48 .text.Delay:0000000000000000 $t + /tmp/ccRLwJE7.s:55 .text.Delay:0000000000000000 Delay + /tmp/ccRLwJE7.s:86 .text.Delay:0000000000000014 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HW_RTC_DelayMs +__aeabi_fmul +__aeabi_f2uiz diff --git a/build/hw_gpio.d b/build/hw_gpio.d new file mode 100644 index 0000000..e523ccd --- /dev/null +++ b/build/hw_gpio.d @@ -0,0 +1,135 @@ +build/hw_gpio.d: Src/hw_gpio.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: diff --git a/build/hw_gpio.lst b/build/hw_gpio.lst new file mode 100644 index 0000000..1408729 --- /dev/null +++ b/build/hw_gpio.lst @@ -0,0 +1,672 @@ +ARM GAS /tmp/ccpOZGrp.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "hw_gpio.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HW_GPIO_Init,"ax",%progbits + 16 .align 1 + 17 .global HW_GPIO_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HW_GPIO_Init: + 24 .LFB96: + 25 .file 1 "./Src/hw_gpio.c" + 1:./Src/hw_gpio.c **** /* + 2:./Src/hw_gpio.c **** / _____) _ | | + 3:./Src/hw_gpio.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/hw_gpio.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/hw_gpio.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/hw_gpio.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/hw_gpio.c **** (C)2013 Semtech + 8:./Src/hw_gpio.c **** + 9:./Src/hw_gpio.c **** Description: Bleeper board GPIO driver implementation + 10:./Src/hw_gpio.c **** + 11:./Src/hw_gpio.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/hw_gpio.c **** + 13:./Src/hw_gpio.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Src/hw_gpio.c **** */ + 15:./Src/hw_gpio.c **** /****************************************************************************** + 16:./Src/hw_gpio.c **** * @file hw_gpio.c + 17:./Src/hw_gpio.c **** * @author MCD Application Team + 18:./Src/hw_gpio.c **** * @version V1.1.2 + 19:./Src/hw_gpio.c **** * @date 08-September-2017 + 20:./Src/hw_gpio.c **** * @brief driver for GPIO + 21:./Src/hw_gpio.c **** ****************************************************************************** + 22:./Src/hw_gpio.c **** * @attention + 23:./Src/hw_gpio.c **** * + 24:./Src/hw_gpio.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/hw_gpio.c **** * All rights reserved.

+ 26:./Src/hw_gpio.c **** * + 27:./Src/hw_gpio.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/hw_gpio.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/hw_gpio.c **** * + 30:./Src/hw_gpio.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/hw_gpio.c **** * this list of conditions and the following disclaimer. + 32:./Src/hw_gpio.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/hw_gpio.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/ccpOZGrp.s page 2 + + + 34:./Src/hw_gpio.c **** * and/or other materials provided with the distribution. + 35:./Src/hw_gpio.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/hw_gpio.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/hw_gpio.c **** * derived from this software without specific written permission. + 38:./Src/hw_gpio.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/hw_gpio.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/hw_gpio.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/hw_gpio.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/hw_gpio.c **** * this license is void and will automatically terminate your rights under + 43:./Src/hw_gpio.c **** * this license. + 44:./Src/hw_gpio.c **** * + 45:./Src/hw_gpio.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/hw_gpio.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/hw_gpio.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/hw_gpio.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/hw_gpio.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/hw_gpio.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/hw_gpio.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/hw_gpio.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/hw_gpio.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/hw_gpio.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/hw_gpio.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/hw_gpio.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/hw_gpio.c **** * + 58:./Src/hw_gpio.c **** ****************************************************************************** + 59:./Src/hw_gpio.c **** */ + 60:./Src/hw_gpio.c **** + 61:./Src/hw_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Src/hw_gpio.c **** #include "hw.h" + 63:./Src/hw_gpio.c **** + 64:./Src/hw_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 65:./Src/hw_gpio.c **** /* Private define ------------------------------------------------------------*/ + 66:./Src/hw_gpio.c **** /* Private macro -------------------------------------------------------------*/ + 67:./Src/hw_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 68:./Src/hw_gpio.c **** static GpioIrqHandler *GpioIrq[16] = { NULL }; + 69:./Src/hw_gpio.c **** + 70:./Src/hw_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 71:./Src/hw_gpio.c **** + 72:./Src/hw_gpio.c **** static uint8_t HW_GPIO_GetBitPos(uint16_t GPIO_Pin); + 73:./Src/hw_gpio.c **** + 74:./Src/hw_gpio.c **** /* Exported functions ---------------------------------------------------------*/ + 75:./Src/hw_gpio.c **** /*! + 76:./Src/hw_gpio.c **** * @brief Initializes the given GPIO object + 77:./Src/hw_gpio.c **** * + 78:./Src/hw_gpio.c **** * @param GPIOx: where x can be (A..E and H) + 79:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 80:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 81:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 82:./Src/hw_gpio.c **** * @param [IN] initStruct GPIO_InitTypeDef intit structure + 83:./Src/hw_gpio.c **** * @retval none + 84:./Src/hw_gpio.c **** */ + 85:./Src/hw_gpio.c **** void HW_GPIO_Init( GPIO_TypeDef* port, uint16_t GPIO_Pin, GPIO_InitTypeDef* initStruct) + 86:./Src/hw_gpio.c **** { + 26 .loc 1 86 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 24 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccpOZGrp.s page 3 + + + 30 .LVL0: + 31 0000 30B5 push {r4, r5, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 12 + 34 .cfi_offset 4, -12 + 35 .cfi_offset 5, -8 + 36 .cfi_offset 14, -4 + 37 0002 87B0 sub sp, sp, #28 + 38 .LCFI1: + 39 .cfi_def_cfa_offset 40 + 87:./Src/hw_gpio.c **** + 88:./Src/hw_gpio.c **** RCC_GPIO_CLK_ENABLE( (uint32_t) port); + 40 .loc 1 88 0 + 41 0004 224C ldr r4, .L10 + 42 0006 A042 cmp r0, r4 + 43 0008 23D0 beq .L3 + 44 000a 0FD9 bls .L9 + 45 000c 214C ldr r4, .L10+4 + 46 000e A042 cmp r0, r4 + 47 0010 29D0 beq .L6 + 48 0012 214C ldr r4, .L10+8 + 49 0014 A042 cmp r0, r4 + 50 0016 30D1 bne .L2 + 51 .LBB6: + 52 .loc 1 88 0 is_stmt 0 discriminator 5 + 53 0018 204C ldr r4, .L10+12 + 54 001a E56A ldr r5, [r4, #44] + 55 001c 0823 movs r3, #8 + 56 001e 1D43 orrs r5, r3 + 57 0020 E562 str r5, [r4, #44] + 58 0022 E46A ldr r4, [r4, #44] + 59 0024 2340 ands r3, r4 + 60 0026 0493 str r3, [sp, #16] + 61 0028 049B ldr r3, [sp, #16] + 62 .LBE6: + 63 002a 0CE0 b .L8 + 64 .L9: + 65 .loc 1 88 0 + 66 002c A024 movs r4, #160 + 67 002e E405 lsls r4, r4, #23 + 68 0030 A042 cmp r0, r4 + 69 0032 22D1 bne .L2 + 70 .LBB7: + 71 .loc 1 88 0 discriminator 2 + 72 0034 194C ldr r4, .L10+12 + 73 0036 E56A ldr r5, [r4, #44] + 74 0038 0123 movs r3, #1 + 75 003a 1D43 orrs r5, r3 + 76 003c E562 str r5, [r4, #44] + 77 003e E46A ldr r4, [r4, #44] + 78 0040 2340 ands r3, r4 + 79 0042 0193 str r3, [sp, #4] + 80 0044 019B ldr r3, [sp, #4] + 81 .L8: + 82 .LBE7: + 89:./Src/hw_gpio.c **** + 90:./Src/hw_gpio.c **** initStruct->Pin = GPIO_Pin ; + ARM GAS /tmp/ccpOZGrp.s page 4 + + + 83 .loc 1 90 0 is_stmt 1 + 84 0046 1160 str r1, [r2] + 91:./Src/hw_gpio.c **** + 92:./Src/hw_gpio.c **** HAL_GPIO_Init( port, initStruct ); + 85 .loc 1 92 0 + 86 0048 1100 movs r1, r2 + 87 .LVL1: + 88 004a FFF7FEFF bl HAL_GPIO_Init + 89 .LVL2: + 93:./Src/hw_gpio.c **** } + 90 .loc 1 93 0 + 91 004e 07B0 add sp, sp, #28 + 92 @ sp needed + 93 0050 30BD pop {r4, r5, pc} + 94 .LVL3: + 95 .L3: + 96 .LBB8: + 88:./Src/hw_gpio.c **** + 97 .loc 1 88 0 discriminator 3 + 98 0052 124C ldr r4, .L10+12 + 99 0054 E56A ldr r5, [r4, #44] + 100 0056 0223 movs r3, #2 + 101 0058 1D43 orrs r5, r3 + 102 005a E562 str r5, [r4, #44] + 103 005c E46A ldr r4, [r4, #44] + 104 005e 2340 ands r3, r4 + 105 0060 0293 str r3, [sp, #8] + 106 0062 029B ldr r3, [sp, #8] + 107 .LBE8: + 108 0064 EFE7 b .L8 + 109 .L6: + 110 .LBB9: + 88:./Src/hw_gpio.c **** + 111 .loc 1 88 0 is_stmt 0 discriminator 4 + 112 0066 0D4C ldr r4, .L10+12 + 113 0068 E56A ldr r5, [r4, #44] + 114 006a 0423 movs r3, #4 + 115 006c 1D43 orrs r5, r3 + 116 006e E562 str r5, [r4, #44] + 117 0070 E46A ldr r4, [r4, #44] + 118 0072 2340 ands r3, r4 + 119 0074 0393 str r3, [sp, #12] + 120 0076 039B ldr r3, [sp, #12] + 121 .LBE9: + 122 0078 E5E7 b .L8 + 123 .L2: + 124 .LBB10: + 88:./Src/hw_gpio.c **** + 125 .loc 1 88 0 discriminator 1 + 126 007a 084C ldr r4, .L10+12 + 127 007c E56A ldr r5, [r4, #44] + 128 007e 8023 movs r3, #128 + 129 0080 1D43 orrs r5, r3 + 130 0082 E562 str r5, [r4, #44] + 131 0084 E46A ldr r4, [r4, #44] + 132 0086 2340 ands r3, r4 + 133 0088 0593 str r3, [sp, #20] + ARM GAS /tmp/ccpOZGrp.s page 5 + + + 134 008a 059B ldr r3, [sp, #20] + 135 008c DBE7 b .L8 + 136 .L11: + 137 008e C046 .align 2 + 138 .L10: + 139 0090 00040050 .word 1342178304 + 140 0094 00080050 .word 1342179328 + 141 0098 000C0050 .word 1342180352 + 142 009c 00100240 .word 1073876992 + 143 .LBE10: + 144 .cfi_endproc + 145 .LFE96: + 147 .section .text.HW_GPIO_SetIrq,"ax",%progbits + 148 .align 1 + 149 .global HW_GPIO_SetIrq + 150 .syntax unified + 151 .code 16 + 152 .thumb_func + 153 .fpu softvfp + 155 HW_GPIO_SetIrq: + 156 .LFB97: + 94:./Src/hw_gpio.c **** + 95:./Src/hw_gpio.c **** /*! + 96:./Src/hw_gpio.c **** * @brief Records the interrupt handler for the GPIO object + 97:./Src/hw_gpio.c **** * + 98:./Src/hw_gpio.c **** * @param GPIOx: where x can be (A..E and H) + 99:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 100:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 101:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 102:./Src/hw_gpio.c **** * @param [IN] prio NVIC priority (0 is highest) + 103:./Src/hw_gpio.c **** * @param [IN] irqHandler points to the function to execute + 104:./Src/hw_gpio.c **** * @retval none + 105:./Src/hw_gpio.c **** */ + 106:./Src/hw_gpio.c **** void HW_GPIO_SetIrq( GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint32_t prio, GpioIrqHandler *irqHan + 107:./Src/hw_gpio.c **** { + 157 .loc 1 107 0 is_stmt 1 + 158 .cfi_startproc + 159 @ args = 0, pretend = 0, frame = 0 + 160 @ frame_needed = 0, uses_anonymous_args = 0 + 161 .LVL4: + 162 0000 70B5 push {r4, r5, r6, lr} + 163 .LCFI2: + 164 .cfi_def_cfa_offset 16 + 165 .cfi_offset 4, -16 + 166 .cfi_offset 5, -12 + 167 .cfi_offset 6, -8 + 168 .cfi_offset 14, -4 + 169 0002 1400 movs r4, r2 + 170 .LVL5: + 171 .LBB11: + 172 .LBB12: + 108:./Src/hw_gpio.c **** IRQn_Type IRQnb; + 109:./Src/hw_gpio.c **** + 110:./Src/hw_gpio.c **** uint32_t BitPos = HW_GPIO_GetBitPos( GPIO_Pin ) ; + 111:./Src/hw_gpio.c **** + 112:./Src/hw_gpio.c **** if ( irqHandler != NULL) + 113:./Src/hw_gpio.c **** { + ARM GAS /tmp/ccpOZGrp.s page 6 + + + 114:./Src/hw_gpio.c **** GpioIrq[ BitPos ] = irqHandler; + 115:./Src/hw_gpio.c **** + 116:./Src/hw_gpio.c **** IRQnb = MSP_GetIRQn( GPIO_Pin ); + 117:./Src/hw_gpio.c **** + 118:./Src/hw_gpio.c **** HAL_NVIC_SetPriority( IRQnb , prio, 0); + 119:./Src/hw_gpio.c **** + 120:./Src/hw_gpio.c **** HAL_NVIC_EnableIRQ( IRQnb ); + 121:./Src/hw_gpio.c **** } + 122:./Src/hw_gpio.c **** } + 123:./Src/hw_gpio.c **** + 124:./Src/hw_gpio.c **** /*! + 125:./Src/hw_gpio.c **** * @brief Execute the interrupt from the object + 126:./Src/hw_gpio.c **** * + 127:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 128:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 129:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 130:./Src/hw_gpio.c **** * @retval none + 131:./Src/hw_gpio.c **** */ + 132:./Src/hw_gpio.c **** void HW_GPIO_IrqHandler( uint16_t GPIO_Pin ) + 133:./Src/hw_gpio.c **** { + 134:./Src/hw_gpio.c **** uint32_t BitPos = HW_GPIO_GetBitPos( GPIO_Pin ); + 135:./Src/hw_gpio.c **** + 136:./Src/hw_gpio.c **** if ( GpioIrq[ BitPos ] != NULL) + 137:./Src/hw_gpio.c **** { + 138:./Src/hw_gpio.c **** GpioIrq[ BitPos ] ( ); + 139:./Src/hw_gpio.c **** } + 140:./Src/hw_gpio.c **** } + 141:./Src/hw_gpio.c **** + 142:./Src/hw_gpio.c **** /*! + 143:./Src/hw_gpio.c **** * @brief Writes the given value to the GPIO output + 144:./Src/hw_gpio.c **** * + 145:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 146:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 147:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 148:./Src/hw_gpio.c **** * @param [IN] value New GPIO output value + 149:./Src/hw_gpio.c **** * @retval none + 150:./Src/hw_gpio.c **** */ + 151:./Src/hw_gpio.c **** void HW_GPIO_Write( GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint32_t value ) + 152:./Src/hw_gpio.c **** { + 153:./Src/hw_gpio.c **** HAL_GPIO_WritePin( GPIOx, GPIO_Pin , (GPIO_PinState) value ); + 154:./Src/hw_gpio.c **** } + 155:./Src/hw_gpio.c **** + 156:./Src/hw_gpio.c **** /*! + 157:./Src/hw_gpio.c **** * @brief Reads the current GPIO input value + 158:./Src/hw_gpio.c **** * + 159:./Src/hw_gpio.c **** * @param GPIOx: where x can be (A..E and H) + 160:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 161:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 162:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 163:./Src/hw_gpio.c **** * @retval value Current GPIO input value + 164:./Src/hw_gpio.c **** */ + 165:./Src/hw_gpio.c **** uint32_t HW_GPIO_Read( GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin ) + 166:./Src/hw_gpio.c **** { + 167:./Src/hw_gpio.c **** return HAL_GPIO_ReadPin( GPIOx, GPIO_Pin); + 168:./Src/hw_gpio.c **** } + 169:./Src/hw_gpio.c **** + 170:./Src/hw_gpio.c **** /* Private functions ---------------------------------------------------------*/ + ARM GAS /tmp/ccpOZGrp.s page 7 + + + 171:./Src/hw_gpio.c **** + 172:./Src/hw_gpio.c **** /*! + 173:./Src/hw_gpio.c **** * @brief Get the position of the bit set in the GPIO_Pin + 174:./Src/hw_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 175:./Src/hw_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 176:./Src/hw_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 177:./Src/hw_gpio.c **** * @retval the position of the bit + 178:./Src/hw_gpio.c **** */ + 179:./Src/hw_gpio.c **** static uint8_t HW_GPIO_GetBitPos(uint16_t GPIO_Pin) + 180:./Src/hw_gpio.c **** { + 181:./Src/hw_gpio.c **** uint8_t PinPos=0; + 182:./Src/hw_gpio.c **** + 183:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xFF00 ) != 0) { PinPos |= 0x8; } + 173 .loc 1 183 0 + 174 0004 FF22 movs r2, #255 + 175 .LVL6: + 176 0006 0800 movs r0, r1 + 177 .LVL7: + 178 0008 9043 bics r0, r2 + 179 000a 021E subs r2, r0, #0 + 180 000c 00D0 beq .L13 + 181 000e 0822 movs r2, #8 + 182 .L13: + 183 .LVL8: + 184:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xF0F0 ) != 0) { PinPos |= 0x4; } + 184 .loc 1 184 0 + 185 0010 0F48 ldr r0, .L19 + 186 0012 0142 tst r1, r0 + 187 0014 01D0 beq .L14 + 188 0016 0420 movs r0, #4 + 189 0018 0243 orrs r2, r0 + 190 .LVL9: + 191 .L14: + 185:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xCCCC ) != 0) { PinPos |= 0x2; } + 192 .loc 1 185 0 + 193 001a 0E48 ldr r0, .L19+4 + 194 001c 0142 tst r1, r0 + 195 001e 01D0 beq .L15 + 196 0020 0220 movs r0, #2 + 197 0022 0243 orrs r2, r0 + 198 .LVL10: + 199 .L15: + 186:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xAAAA ) != 0) { PinPos |= 0x1; } + 200 .loc 1 186 0 + 201 0024 0C48 ldr r0, .L19+8 + 202 0026 0142 tst r1, r0 + 203 0028 01D0 beq .L16 + 204 002a 0120 movs r0, #1 + 205 002c 0243 orrs r2, r0 + 206 .LVL11: + 207 .L16: + 208 .LBE12: + 209 .LBE11: + 112:./Src/hw_gpio.c **** { + 210 .loc 1 112 0 + 211 002e 002B cmp r3, #0 + 212 0030 0DD0 beq .L12 + ARM GAS /tmp/ccpOZGrp.s page 8 + + + 114:./Src/hw_gpio.c **** + 213 .loc 1 114 0 + 214 0032 9200 lsls r2, r2, #2 + 215 .LVL12: + 216 0034 0948 ldr r0, .L19+12 + 217 0036 1350 str r3, [r2, r0] + 116:./Src/hw_gpio.c **** + 218 .loc 1 116 0 + 219 0038 0800 movs r0, r1 + 220 003a FFF7FEFF bl MSP_GetIRQn + 221 .LVL13: + 222 003e 0500 movs r5, r0 + 223 .LVL14: + 118:./Src/hw_gpio.c **** + 224 .loc 1 118 0 + 225 0040 0022 movs r2, #0 + 226 0042 2100 movs r1, r4 + 227 0044 FFF7FEFF bl HAL_NVIC_SetPriority + 228 .LVL15: + 120:./Src/hw_gpio.c **** } + 229 .loc 1 120 0 + 230 0048 2800 movs r0, r5 + 231 004a FFF7FEFF bl HAL_NVIC_EnableIRQ + 232 .LVL16: + 233 .L12: + 122:./Src/hw_gpio.c **** + 234 .loc 1 122 0 + 235 @ sp needed + 236 .LVL17: + 237 004e 70BD pop {r4, r5, r6, pc} + 238 .L20: + 239 .align 2 + 240 .L19: + 241 0050 F0F0FFFF .word -3856 + 242 0054 CCCCFFFF .word -13108 + 243 0058 AAAAFFFF .word -21846 + 244 005c 00000000 .word .LANCHOR0 + 245 .cfi_endproc + 246 .LFE97: + 248 .section .text.HW_GPIO_IrqHandler,"ax",%progbits + 249 .align 1 + 250 .global HW_GPIO_IrqHandler + 251 .syntax unified + 252 .code 16 + 253 .thumb_func + 254 .fpu softvfp + 256 HW_GPIO_IrqHandler: + 257 .LFB98: + 133:./Src/hw_gpio.c **** uint32_t BitPos = HW_GPIO_GetBitPos( GPIO_Pin ); + 258 .loc 1 133 0 + 259 .cfi_startproc + 260 @ args = 0, pretend = 0, frame = 0 + 261 @ frame_needed = 0, uses_anonymous_args = 0 + 262 .LVL18: + 263 0000 10B5 push {r4, lr} + 264 .LCFI3: + 265 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccpOZGrp.s page 9 + + + 266 .cfi_offset 4, -8 + 267 .cfi_offset 14, -4 + 268 .LVL19: + 269 .LBB13: + 270 .LBB14: + 183:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xF0F0 ) != 0) { PinPos |= 0x4; } + 271 .loc 1 183 0 + 272 0002 FF23 movs r3, #255 + 273 0004 0200 movs r2, r0 + 274 0006 9A43 bics r2, r3 + 275 0008 131E subs r3, r2, #0 + 276 000a 00D0 beq .L22 + 277 000c 0823 movs r3, #8 + 278 .L22: + 279 .LVL20: + 184:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xCCCC ) != 0) { PinPos |= 0x2; } + 280 .loc 1 184 0 + 281 000e 0B4A ldr r2, .L28 + 282 0010 1042 tst r0, r2 + 283 0012 01D0 beq .L23 + 284 0014 0422 movs r2, #4 + 285 0016 1343 orrs r3, r2 + 286 .LVL21: + 287 .L23: + 185:./Src/hw_gpio.c **** if ( ( GPIO_Pin & 0xAAAA ) != 0) { PinPos |= 0x1; } + 288 .loc 1 185 0 + 289 0018 094A ldr r2, .L28+4 + 290 001a 1042 tst r0, r2 + 291 001c 01D0 beq .L24 + 292 001e 0222 movs r2, #2 + 293 0020 1343 orrs r3, r2 + 294 .LVL22: + 295 .L24: + 296 .loc 1 186 0 + 297 0022 084A ldr r2, .L28+8 + 298 0024 1042 tst r0, r2 + 299 0026 01D0 beq .L25 + 300 0028 0122 movs r2, #1 + 301 002a 1343 orrs r3, r2 + 302 .LVL23: + 303 .L25: + 304 .LBE14: + 305 .LBE13: + 136:./Src/hw_gpio.c **** { + 306 .loc 1 136 0 + 307 002c 9B00 lsls r3, r3, #2 + 308 .LVL24: + 309 002e 064A ldr r2, .L28+12 + 310 0030 9B58 ldr r3, [r3, r2] + 311 0032 002B cmp r3, #0 + 312 0034 00D0 beq .L21 + 138:./Src/hw_gpio.c **** } + 313 .loc 1 138 0 + 314 0036 9847 blx r3 + 315 .LVL25: + 316 .L21: + 140:./Src/hw_gpio.c **** + ARM GAS /tmp/ccpOZGrp.s page 10 + + + 317 .loc 1 140 0 + 318 @ sp needed + 319 0038 10BD pop {r4, pc} + 320 .L29: + 321 003a C046 .align 2 + 322 .L28: + 323 003c F0F0FFFF .word -3856 + 324 0040 CCCCFFFF .word -13108 + 325 0044 AAAAFFFF .word -21846 + 326 0048 00000000 .word .LANCHOR0 + 327 .cfi_endproc + 328 .LFE98: + 330 .section .text.HW_GPIO_Write,"ax",%progbits + 331 .align 1 + 332 .global HW_GPIO_Write + 333 .syntax unified + 334 .code 16 + 335 .thumb_func + 336 .fpu softvfp + 338 HW_GPIO_Write: + 339 .LFB99: + 152:./Src/hw_gpio.c **** HAL_GPIO_WritePin( GPIOx, GPIO_Pin , (GPIO_PinState) value ); + 340 .loc 1 152 0 + 341 .cfi_startproc + 342 @ args = 0, pretend = 0, frame = 0 + 343 @ frame_needed = 0, uses_anonymous_args = 0 + 344 .LVL26: + 345 0000 10B5 push {r4, lr} + 346 .LCFI4: + 347 .cfi_def_cfa_offset 8 + 348 .cfi_offset 4, -8 + 349 .cfi_offset 14, -4 + 153:./Src/hw_gpio.c **** } + 350 .loc 1 153 0 + 351 0002 D2B2 uxtb r2, r2 + 352 .LVL27: + 353 0004 FFF7FEFF bl HAL_GPIO_WritePin + 354 .LVL28: + 154:./Src/hw_gpio.c **** + 355 .loc 1 154 0 + 356 @ sp needed + 357 0008 10BD pop {r4, pc} + 358 .cfi_endproc + 359 .LFE99: + 361 .section .text.HW_GPIO_Read,"ax",%progbits + 362 .align 1 + 363 .global HW_GPIO_Read + 364 .syntax unified + 365 .code 16 + 366 .thumb_func + 367 .fpu softvfp + 369 HW_GPIO_Read: + 370 .LFB100: + 166:./Src/hw_gpio.c **** return HAL_GPIO_ReadPin( GPIOx, GPIO_Pin); + 371 .loc 1 166 0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccpOZGrp.s page 11 + + + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 .LVL29: + 376 0000 10B5 push {r4, lr} + 377 .LCFI5: + 378 .cfi_def_cfa_offset 8 + 379 .cfi_offset 4, -8 + 380 .cfi_offset 14, -4 + 167:./Src/hw_gpio.c **** } + 381 .loc 1 167 0 + 382 0002 FFF7FEFF bl HAL_GPIO_ReadPin + 383 .LVL30: + 168:./Src/hw_gpio.c **** + 384 .loc 1 168 0 + 385 @ sp needed + 386 0006 10BD pop {r4, pc} + 387 .cfi_endproc + 388 .LFE100: + 390 .section .bss.GpioIrq,"aw",%nobits + 391 .align 2 + 392 .set .LANCHOR0,. + 0 + 395 GpioIrq: + 396 0000 00000000 .space 64 + 396 00000000 + 396 00000000 + 396 00000000 + 396 00000000 + 397 .text + 398 .Letext0: + 399 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 400 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 401 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 402 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 403 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 404 .file 7 "/usr/arm-none-eabi/include/math.h" + 405 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 406 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 407 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 408 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 409 .file 12 "Inc/hw_gpio.h" + 410 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + ARM GAS /tmp/ccpOZGrp.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 hw_gpio.c + /tmp/ccpOZGrp.s:16 .text.HW_GPIO_Init:0000000000000000 $t + /tmp/ccpOZGrp.s:23 .text.HW_GPIO_Init:0000000000000000 HW_GPIO_Init + /tmp/ccpOZGrp.s:139 .text.HW_GPIO_Init:0000000000000090 $d + /tmp/ccpOZGrp.s:148 .text.HW_GPIO_SetIrq:0000000000000000 $t + /tmp/ccpOZGrp.s:155 .text.HW_GPIO_SetIrq:0000000000000000 HW_GPIO_SetIrq + /tmp/ccpOZGrp.s:241 .text.HW_GPIO_SetIrq:0000000000000050 $d + /tmp/ccpOZGrp.s:249 .text.HW_GPIO_IrqHandler:0000000000000000 $t + /tmp/ccpOZGrp.s:256 .text.HW_GPIO_IrqHandler:0000000000000000 HW_GPIO_IrqHandler + /tmp/ccpOZGrp.s:323 .text.HW_GPIO_IrqHandler:000000000000003c $d + /tmp/ccpOZGrp.s:331 .text.HW_GPIO_Write:0000000000000000 $t + /tmp/ccpOZGrp.s:338 .text.HW_GPIO_Write:0000000000000000 HW_GPIO_Write + /tmp/ccpOZGrp.s:362 .text.HW_GPIO_Read:0000000000000000 $t + /tmp/ccpOZGrp.s:369 .text.HW_GPIO_Read:0000000000000000 HW_GPIO_Read + /tmp/ccpOZGrp.s:391 .bss.GpioIrq:0000000000000000 $d + /tmp/ccpOZGrp.s:395 .bss.GpioIrq:0000000000000000 GpioIrq + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GPIO_Init +MSP_GetIRQn +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +HAL_GPIO_WritePin +HAL_GPIO_ReadPin diff --git a/build/hw_i2c.d b/build/hw_i2c.d new file mode 100644 index 0000000..c2023d5 --- /dev/null +++ b/build/hw_i2c.d @@ -0,0 +1,141 @@ +build/hw_i2c.d: Src/hw_i2c.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h Inc/hw_i2c.h Inc/main.h Inc/debug.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Inc/hw_i2c.h: + +Inc/main.h: + +Inc/debug.h: diff --git a/build/hw_i2c.lst b/build/hw_i2c.lst new file mode 100644 index 0000000..38e7f8c --- /dev/null +++ b/build/hw_i2c.lst @@ -0,0 +1,486 @@ +ARM GAS /tmp/ccdg55Po.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "hw_i2c.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.MX_I2C1_Init,"ax",%progbits + 16 .align 1 + 17 .global MX_I2C1_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 MX_I2C1_Init: + 24 .LFB97: + 25 .file 1 "./Src/hw_i2c.c" + 1:./Src/hw_i2c.c **** /** + 2:./Src/hw_i2c.c **** ****************************************************************************** + 3:./Src/hw_i2c.c **** * File Name : I2C.c + 4:./Src/hw_i2c.c **** * Description : This file provides code for the configuration + 5:./Src/hw_i2c.c **** * of the I2C instances. + 6:./Src/hw_i2c.c **** ****************************************************************************** + 7:./Src/hw_i2c.c **** ** This notice applies to any and all portions of this file + 8:./Src/hw_i2c.c **** * that are not between comment pairs USER CODE BEGIN and + 9:./Src/hw_i2c.c **** * USER CODE END. Other portions of this file, whether + 10:./Src/hw_i2c.c **** * inserted by the user or by software development tools + 11:./Src/hw_i2c.c **** * are owned by their respective copyright owners. + 12:./Src/hw_i2c.c **** * + 13:./Src/hw_i2c.c **** * COPYRIGHT(c) 2017 STMicroelectronics + 14:./Src/hw_i2c.c **** * + 15:./Src/hw_i2c.c **** * Redistribution and use in source and binary forms, with or without modification, + 16:./Src/hw_i2c.c **** * are permitted provided that the following conditions are met: + 17:./Src/hw_i2c.c **** * 1. Redistributions of source code must retain the above copyright notice, + 18:./Src/hw_i2c.c **** * this list of conditions and the following disclaimer. + 19:./Src/hw_i2c.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 20:./Src/hw_i2c.c **** * this list of conditions and the following disclaimer in the documentation + 21:./Src/hw_i2c.c **** * and/or other materials provided with the distribution. + 22:./Src/hw_i2c.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 23:./Src/hw_i2c.c **** * may be used to endorse or promote products derived from this software + 24:./Src/hw_i2c.c **** * without specific prior written permission. + 25:./Src/hw_i2c.c **** * + 26:./Src/hw_i2c.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 27:./Src/hw_i2c.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 28:./Src/hw_i2c.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 29:./Src/hw_i2c.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 30:./Src/hw_i2c.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 31:./Src/hw_i2c.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 32:./Src/hw_i2c.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 33:./Src/hw_i2c.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + ARM GAS /tmp/ccdg55Po.s page 2 + + + 34:./Src/hw_i2c.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 35:./Src/hw_i2c.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 36:./Src/hw_i2c.c **** * + 37:./Src/hw_i2c.c **** ****************************************************************************** + 38:./Src/hw_i2c.c **** */ + 39:./Src/hw_i2c.c **** + 40:./Src/hw_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 41:./Src/hw_i2c.c **** #include "hw.h" + 42:./Src/hw_i2c.c **** #include "hw_i2c.h" + 43:./Src/hw_i2c.c **** #include "debug.h" + 44:./Src/hw_i2c.c **** + 45:./Src/hw_i2c.c **** static inline uint32_t setupTiming(void) + 46:./Src/hw_i2c.c **** { + 47:./Src/hw_i2c.c **** const uint32_t presc = 15; + 48:./Src/hw_i2c.c **** + 49:./Src/hw_i2c.c **** // delays + 50:./Src/hw_i2c.c **** const uint32_t sdadel = 2; + 51:./Src/hw_i2c.c **** const uint32_t scldel = 2; + 52:./Src/hw_i2c.c **** + 53:./Src/hw_i2c.c **** const uint32_t scll = 6; + 54:./Src/hw_i2c.c **** const uint32_t sclh = 7; + 55:./Src/hw_i2c.c **** + 56:./Src/hw_i2c.c **** return presc << I2C_TIMINGR_PRESC_Pos | + 57:./Src/hw_i2c.c **** scldel << I2C_TIMINGR_SCLDEL_Pos | + 58:./Src/hw_i2c.c **** sdadel << I2C_TIMINGR_SDADEL_Pos | + 59:./Src/hw_i2c.c **** sclh << I2C_TIMINGR_SCLH_Pos | + 60:./Src/hw_i2c.c **** scll << I2C_TIMINGR_SCLL_Pos; + 61:./Src/hw_i2c.c **** } + 62:./Src/hw_i2c.c **** + 63:./Src/hw_i2c.c **** I2C_HandleTypeDef hi2c1; + 64:./Src/hw_i2c.c **** + 65:./Src/hw_i2c.c **** /* I2C1 init function */ + 66:./Src/hw_i2c.c **** void MX_I2C1_Init(void) + 67:./Src/hw_i2c.c **** { + 26 .loc 1 67 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 10B5 push {r4, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 4, -8 + 34 .cfi_offset 14, -4 + 68:./Src/hw_i2c.c **** hi2c1.Instance = I2C1; + 35 .loc 1 68 0 + 36 0002 1748 ldr r0, .L8 + 37 0004 174B ldr r3, .L8+4 + 38 0006 0360 str r3, [r0] + 39 .LVL0: + 69:./Src/hw_i2c.c **** hi2c1.Init.Timing = setupTiming(); //0x00000708; + 40 .loc 1 69 0 + 41 0008 174B ldr r3, .L8+8 + 42 000a 4360 str r3, [r0, #4] + 70:./Src/hw_i2c.c **** hi2c1.Init.OwnAddress1 = 0; + 43 .loc 1 70 0 + 44 000c 0023 movs r3, #0 + 45 000e 8360 str r3, [r0, #8] + ARM GAS /tmp/ccdg55Po.s page 3 + + + 71:./Src/hw_i2c.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 46 .loc 1 71 0 + 47 0010 0122 movs r2, #1 + 48 0012 C260 str r2, [r0, #12] + 72:./Src/hw_i2c.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 49 .loc 1 72 0 + 50 0014 0361 str r3, [r0, #16] + 73:./Src/hw_i2c.c **** hi2c1.Init.OwnAddress2 = 0; + 51 .loc 1 73 0 + 52 0016 4361 str r3, [r0, #20] + 74:./Src/hw_i2c.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 53 .loc 1 74 0 + 54 0018 8361 str r3, [r0, #24] + 75:./Src/hw_i2c.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 55 .loc 1 75 0 + 56 001a C361 str r3, [r0, #28] + 76:./Src/hw_i2c.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 57 .loc 1 76 0 + 58 001c 0362 str r3, [r0, #32] + 77:./Src/hw_i2c.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 59 .loc 1 77 0 + 60 001e FFF7FEFF bl HAL_I2C_Init + 61 .LVL1: + 62 0022 0028 cmp r0, #0 + 63 0024 0CD1 bne .L5 + 64 .L2: + 78:./Src/hw_i2c.c **** { + 79:./Src/hw_i2c.c **** _Error_Handler(__FILE__, __LINE__); + 80:./Src/hw_i2c.c **** } + 81:./Src/hw_i2c.c **** + 82:./Src/hw_i2c.c **** /**Configure Analogue filter + 83:./Src/hw_i2c.c **** */ + 84:./Src/hw_i2c.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 65 .loc 1 84 0 + 66 0026 0021 movs r1, #0 + 67 0028 0D48 ldr r0, .L8 + 68 002a FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 69 .LVL2: + 70 002e 0028 cmp r0, #0 + 71 0030 0BD1 bne .L6 + 72 .L3: + 85:./Src/hw_i2c.c **** { + 86:./Src/hw_i2c.c **** _Error_Handler(__FILE__, __LINE__); + 87:./Src/hw_i2c.c **** } + 88:./Src/hw_i2c.c **** + 89:./Src/hw_i2c.c **** /**Configure Digital filter + 90:./Src/hw_i2c.c **** */ + 91:./Src/hw_i2c.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 73 .loc 1 91 0 + 74 0032 0021 movs r1, #0 + 75 0034 0A48 ldr r0, .L8 + 76 0036 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 77 .LVL3: + 78 003a 0028 cmp r0, #0 + 79 003c 0AD1 bne .L7 + 80 .L1: + 92:./Src/hw_i2c.c **** { + ARM GAS /tmp/ccdg55Po.s page 4 + + + 93:./Src/hw_i2c.c **** _Error_Handler(__FILE__, __LINE__); + 94:./Src/hw_i2c.c **** } + 95:./Src/hw_i2c.c **** + 96:./Src/hw_i2c.c **** } + 81 .loc 1 96 0 + 82 @ sp needed + 83 003e 10BD pop {r4, pc} + 84 .L5: + 79:./Src/hw_i2c.c **** } + 85 .loc 1 79 0 + 86 0040 4F21 movs r1, #79 + 87 0042 0A48 ldr r0, .L8+12 + 88 0044 FFF7FEFF bl _Error_Handler + 89 .LVL4: + 90 0048 EDE7 b .L2 + 91 .L6: + 86:./Src/hw_i2c.c **** } + 92 .loc 1 86 0 + 93 004a 5621 movs r1, #86 + 94 004c 0748 ldr r0, .L8+12 + 95 004e FFF7FEFF bl _Error_Handler + 96 .LVL5: + 97 0052 EEE7 b .L3 + 98 .L7: + 93:./Src/hw_i2c.c **** } + 99 .loc 1 93 0 + 100 0054 5D21 movs r1, #93 + 101 0056 0548 ldr r0, .L8+12 + 102 0058 FFF7FEFF bl _Error_Handler + 103 .LVL6: + 104 .loc 1 96 0 + 105 005c EFE7 b .L1 + 106 .L9: + 107 005e C046 .align 2 + 108 .L8: + 109 0060 00000000 .word .LANCHOR0 + 110 0064 00540040 .word 1073763328 + 111 0068 060722F0 .word -266205434 + 112 006c 00000000 .word .LC1 + 113 .cfi_endproc + 114 .LFE97: + 116 .section .text.HAL_I2C_MspInit,"ax",%progbits + 117 .align 1 + 118 .global HAL_I2C_MspInit + 119 .syntax unified + 120 .code 16 + 121 .thumb_func + 122 .fpu softvfp + 124 HAL_I2C_MspInit: + 125 .LFB98: + 97:./Src/hw_i2c.c **** + 98:./Src/hw_i2c.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) + 99:./Src/hw_i2c.c **** { + 126 .loc 1 99 0 + 127 .cfi_startproc + 128 @ args = 0, pretend = 0, frame = 24 + 129 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccdg55Po.s page 5 + + + 130 .LVL7: + 131 0000 00B5 push {lr} + 132 .LCFI1: + 133 .cfi_def_cfa_offset 4 + 134 .cfi_offset 14, -4 + 135 0002 87B0 sub sp, sp, #28 + 136 .LCFI2: + 137 .cfi_def_cfa_offset 32 + 100:./Src/hw_i2c.c **** + 101:./Src/hw_i2c.c **** GPIO_InitTypeDef GPIO_InitStruct; + 102:./Src/hw_i2c.c **** if(i2cHandle->Instance==I2C1) + 138 .loc 1 102 0 + 139 0004 0268 ldr r2, [r0] + 140 0006 0D4B ldr r3, .L13 + 141 0008 9A42 cmp r2, r3 + 142 000a 01D0 beq .L12 + 143 .LVL8: + 144 .L10: + 103:./Src/hw_i2c.c **** { + 104:./Src/hw_i2c.c **** /* USER CODE BEGIN I2C1_MspInit 0 */ + 105:./Src/hw_i2c.c **** + 106:./Src/hw_i2c.c **** /* USER CODE END I2C1_MspInit 0 */ + 107:./Src/hw_i2c.c **** + 108:./Src/hw_i2c.c **** /**I2C1 GPIO Configuration + 109:./Src/hw_i2c.c **** PB8 ------> I2C1_SCL + 110:./Src/hw_i2c.c **** PB9 ------> I2C1_SDA + 111:./Src/hw_i2c.c **** */ + 112:./Src/hw_i2c.c **** GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + 113:./Src/hw_i2c.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 114:./Src/hw_i2c.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; + 115:./Src/hw_i2c.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 116:./Src/hw_i2c.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 117:./Src/hw_i2c.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 118:./Src/hw_i2c.c **** + 119:./Src/hw_i2c.c **** /* I2C1 clock enable */ + 120:./Src/hw_i2c.c **** __HAL_RCC_I2C1_CLK_ENABLE(); + 121:./Src/hw_i2c.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 122:./Src/hw_i2c.c **** + 123:./Src/hw_i2c.c **** /* USER CODE END I2C1_MspInit 1 */ + 124:./Src/hw_i2c.c **** } + 125:./Src/hw_i2c.c **** } + 145 .loc 1 125 0 + 146 000c 07B0 add sp, sp, #28 + 147 @ sp needed + 148 000e 00BD pop {pc} + 149 .LVL9: + 150 .L12: + 112:./Src/hw_i2c.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 151 .loc 1 112 0 + 152 0010 C023 movs r3, #192 + 153 0012 9B00 lsls r3, r3, #2 + 154 0014 0193 str r3, [sp, #4] + 113:./Src/hw_i2c.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; + 155 .loc 1 113 0 + 156 0016 1223 movs r3, #18 + 157 0018 0293 str r3, [sp, #8] + 114:./Src/hw_i2c.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + ARM GAS /tmp/ccdg55Po.s page 6 + + + 158 .loc 1 114 0 + 159 001a 113B subs r3, r3, #17 + 160 001c 0393 str r3, [sp, #12] + 115:./Src/hw_i2c.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 161 .loc 1 115 0 + 162 001e 0233 adds r3, r3, #2 + 163 0020 0493 str r3, [sp, #16] + 116:./Src/hw_i2c.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 164 .loc 1 116 0 + 165 0022 0133 adds r3, r3, #1 + 166 0024 0593 str r3, [sp, #20] + 117:./Src/hw_i2c.c **** + 167 .loc 1 117 0 + 168 0026 01A9 add r1, sp, #4 + 169 0028 0548 ldr r0, .L13+4 + 170 .LVL10: + 171 002a FFF7FEFF bl HAL_GPIO_Init + 172 .LVL11: + 120:./Src/hw_i2c.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 173 .loc 1 120 0 + 174 002e 054A ldr r2, .L13+8 + 175 0030 916B ldr r1, [r2, #56] + 176 0032 8023 movs r3, #128 + 177 0034 9B03 lsls r3, r3, #14 + 178 0036 0B43 orrs r3, r1 + 179 0038 9363 str r3, [r2, #56] + 180 .loc 1 125 0 + 181 003a E7E7 b .L10 + 182 .L14: + 183 .align 2 + 184 .L13: + 185 003c 00540040 .word 1073763328 + 186 0040 00040050 .word 1342178304 + 187 0044 00100240 .word 1073876992 + 188 .cfi_endproc + 189 .LFE98: + 191 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 192 .align 1 + 193 .global HAL_I2C_MspDeInit + 194 .syntax unified + 195 .code 16 + 196 .thumb_func + 197 .fpu softvfp + 199 HAL_I2C_MspDeInit: + 200 .LFB99: + 126:./Src/hw_i2c.c **** + 127:./Src/hw_i2c.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) + 128:./Src/hw_i2c.c **** { + 201 .loc 1 128 0 + 202 .cfi_startproc + 203 @ args = 0, pretend = 0, frame = 0 + 204 @ frame_needed = 0, uses_anonymous_args = 0 + 205 .LVL12: + 206 0000 10B5 push {r4, lr} + 207 .LCFI3: + 208 .cfi_def_cfa_offset 8 + 209 .cfi_offset 4, -8 + ARM GAS /tmp/ccdg55Po.s page 7 + + + 210 .cfi_offset 14, -4 + 129:./Src/hw_i2c.c **** + 130:./Src/hw_i2c.c **** if(i2cHandle->Instance==I2C1) + 211 .loc 1 130 0 + 212 0002 0268 ldr r2, [r0] + 213 0004 074B ldr r3, .L18 + 214 0006 9A42 cmp r2, r3 + 215 0008 00D0 beq .L17 + 216 .LVL13: + 217 .L15: + 131:./Src/hw_i2c.c **** { + 132:./Src/hw_i2c.c **** /* USER CODE BEGIN I2C1_MspDeInit 0 */ + 133:./Src/hw_i2c.c **** + 134:./Src/hw_i2c.c **** /* USER CODE END I2C1_MspDeInit 0 */ + 135:./Src/hw_i2c.c **** /* Peripheral clock disable */ + 136:./Src/hw_i2c.c **** __HAL_RCC_I2C1_CLK_DISABLE(); + 137:./Src/hw_i2c.c **** + 138:./Src/hw_i2c.c **** /**I2C1 GPIO Configuration + 139:./Src/hw_i2c.c **** PB8 ------> I2C1_SCL + 140:./Src/hw_i2c.c **** PB9 ------> I2C1_SDA + 141:./Src/hw_i2c.c **** */ + 142:./Src/hw_i2c.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); + 143:./Src/hw_i2c.c **** + 144:./Src/hw_i2c.c **** /* USER CODE BEGIN I2C1_MspDeInit 1 */ + 145:./Src/hw_i2c.c **** + 146:./Src/hw_i2c.c **** /* USER CODE END I2C1_MspDeInit 1 */ + 147:./Src/hw_i2c.c **** } + 148:./Src/hw_i2c.c **** } + 218 .loc 1 148 0 + 219 @ sp needed + 220 000a 10BD pop {r4, pc} + 221 .LVL14: + 222 .L17: + 136:./Src/hw_i2c.c **** + 223 .loc 1 136 0 + 224 000c 064A ldr r2, .L18+4 + 225 000e 936B ldr r3, [r2, #56] + 226 0010 0649 ldr r1, .L18+8 + 227 0012 0B40 ands r3, r1 + 228 0014 9363 str r3, [r2, #56] + 142:./Src/hw_i2c.c **** + 229 .loc 1 142 0 + 230 0016 C021 movs r1, #192 + 231 0018 8900 lsls r1, r1, #2 + 232 001a 0548 ldr r0, .L18+12 + 233 .LVL15: + 234 001c FFF7FEFF bl HAL_GPIO_DeInit + 235 .LVL16: + 236 .loc 1 148 0 + 237 0020 F3E7 b .L15 + 238 .L19: + 239 0022 C046 .align 2 + 240 .L18: + 241 0024 00540040 .word 1073763328 + 242 0028 00100240 .word 1073876992 + 243 002c FFFFDFFF .word -2097153 + 244 0030 00040050 .word 1342178304 + ARM GAS /tmp/ccdg55Po.s page 8 + + + 245 .cfi_endproc + 246 .LFE99: + 248 .global hi2c1 + 249 .section .bss.hi2c1,"aw",%nobits + 250 .align 2 + 251 .set .LANCHOR0,. + 0 + 254 hi2c1: + 255 0000 00000000 .space 76 + 255 00000000 + 255 00000000 + 255 00000000 + 255 00000000 + 256 .section .rodata.MX_I2C1_Init.str1.4,"aMS",%progbits,1 + 257 .align 2 + 258 .LC1: + 259 0000 2E2F5372 .ascii "./Src/hw_i2c.c\000" + 259 632F6877 + 259 5F693263 + 259 2E6300 + 260 .text + 261 .Letext0: + 262 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 263 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 264 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 265 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 266 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 267 .file 7 "/usr/arm-none-eabi/include/math.h" + 268 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 269 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 270 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 271 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 272 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 273 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 274 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h" + 275 .file 15 "Inc/hw_i2c.h" + 276 .file 16 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h" + 277 .file 17 "Inc/debug.h" + ARM GAS /tmp/ccdg55Po.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 hw_i2c.c + /tmp/ccdg55Po.s:16 .text.MX_I2C1_Init:0000000000000000 $t + /tmp/ccdg55Po.s:23 .text.MX_I2C1_Init:0000000000000000 MX_I2C1_Init + /tmp/ccdg55Po.s:109 .text.MX_I2C1_Init:0000000000000060 $d + /tmp/ccdg55Po.s:117 .text.HAL_I2C_MspInit:0000000000000000 $t + /tmp/ccdg55Po.s:124 .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit + /tmp/ccdg55Po.s:185 .text.HAL_I2C_MspInit:000000000000003c $d + /tmp/ccdg55Po.s:192 .text.HAL_I2C_MspDeInit:0000000000000000 $t + /tmp/ccdg55Po.s:199 .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit + /tmp/ccdg55Po.s:241 .text.HAL_I2C_MspDeInit:0000000000000024 $d + /tmp/ccdg55Po.s:254 .bss.hi2c1:0000000000000000 hi2c1 + /tmp/ccdg55Po.s:250 .bss.hi2c1:0000000000000000 $d + /tmp/ccdg55Po.s:257 .rodata.MX_I2C1_Init.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_I2C_Init +HAL_I2CEx_ConfigAnalogFilter +HAL_I2CEx_ConfigDigitalFilter +_Error_Handler +HAL_GPIO_Init +HAL_GPIO_DeInit diff --git a/build/hw_rtc.d b/build/hw_rtc.d new file mode 100644 index 0000000..622eea4 --- /dev/null +++ b/build/hw_rtc.d @@ -0,0 +1,138 @@ +build/hw_rtc.d: Src/hw_rtc.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/low_power.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/low_power.h: diff --git a/build/hw_rtc.lst b/build/hw_rtc.lst new file mode 100644 index 0000000..9a7a2c1 --- /dev/null +++ b/build/hw_rtc.lst @@ -0,0 +1,2705 @@ +ARM GAS /tmp/ccGAhXKe.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "hw_rtc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HW_RTC_GetCalendarValue,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 HW_RTC_GetCalendarValue: + 23 .LFB113: + 24 .file 1 "./Src/hw_rtc.c" + 1:./Src/hw_rtc.c **** /* + 2:./Src/hw_rtc.c **** / _____) _ | | + 3:./Src/hw_rtc.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/hw_rtc.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/hw_rtc.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/hw_rtc.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/hw_rtc.c **** (C)2013 Semtech + 8:./Src/hw_rtc.c **** + 9:./Src/hw_rtc.c **** Description: MCU RTC timer + 10:./Src/hw_rtc.c **** + 11:./Src/hw_rtc.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/hw_rtc.c **** + 13:./Src/hw_rtc.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Src/hw_rtc.c **** */ + 15:./Src/hw_rtc.c **** /******************************************************************************* + 16:./Src/hw_rtc.c **** * @file hw_rtc.c + 17:./Src/hw_rtc.c **** * @author MCD Application Team + 18:./Src/hw_rtc.c **** * @version V1.1.2 + 19:./Src/hw_rtc.c **** * @date 08-September-2017 + 20:./Src/hw_rtc.c **** * @brief driver for RTC + 21:./Src/hw_rtc.c **** ****************************************************************************** + 22:./Src/hw_rtc.c **** * @attention + 23:./Src/hw_rtc.c **** * + 24:./Src/hw_rtc.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/hw_rtc.c **** * All rights reserved.

+ 26:./Src/hw_rtc.c **** * + 27:./Src/hw_rtc.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/hw_rtc.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/hw_rtc.c **** * + 30:./Src/hw_rtc.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/hw_rtc.c **** * this list of conditions and the following disclaimer. + 32:./Src/hw_rtc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/hw_rtc.c **** * this list of conditions and the following disclaimer in the documentation + 34:./Src/hw_rtc.c **** * and/or other materials provided with the distribution. + ARM GAS /tmp/ccGAhXKe.s page 2 + + + 35:./Src/hw_rtc.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/hw_rtc.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/hw_rtc.c **** * derived from this software without specific written permission. + 38:./Src/hw_rtc.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/hw_rtc.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/hw_rtc.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/hw_rtc.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/hw_rtc.c **** * this license is void and will automatically terminate your rights under + 43:./Src/hw_rtc.c **** * this license. + 44:./Src/hw_rtc.c **** * + 45:./Src/hw_rtc.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/hw_rtc.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/hw_rtc.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/hw_rtc.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/hw_rtc.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/hw_rtc.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/hw_rtc.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/hw_rtc.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/hw_rtc.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/hw_rtc.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/hw_rtc.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/hw_rtc.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/hw_rtc.c **** * + 58:./Src/hw_rtc.c **** ****************************************************************************** + 59:./Src/hw_rtc.c **** */ + 60:./Src/hw_rtc.c **** + 61:./Src/hw_rtc.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Src/hw_rtc.c **** #include "hw.h" + 63:./Src/hw_rtc.c **** #include "low_power.h" + 64:./Src/hw_rtc.c **** + 65:./Src/hw_rtc.c **** /* Private typedef -----------------------------------------------------------*/ + 66:./Src/hw_rtc.c **** typedef struct + 67:./Src/hw_rtc.c **** { + 68:./Src/hw_rtc.c **** TimerTime_t Rtc_Time; /* Reference time */ + 69:./Src/hw_rtc.c **** + 70:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_Calndr_Time; /* Reference time in calendar format */ + 71:./Src/hw_rtc.c **** + 72:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_Calndr_Date; /* Reference date in calendar format */ + 73:./Src/hw_rtc.c **** + 74:./Src/hw_rtc.c **** } RtcTimerContext_t; + 75:./Src/hw_rtc.c **** + 76:./Src/hw_rtc.c **** /* Private define ------------------------------------------------------------*/ + 77:./Src/hw_rtc.c **** + 78:./Src/hw_rtc.c **** /* MCU Wake Up Time */ + 79:./Src/hw_rtc.c **** #define MIN_ALARM_DELAY 3 /* in ticks */ + 80:./Src/hw_rtc.c **** + 81:./Src/hw_rtc.c **** /* subsecond number of bits */ + 82:./Src/hw_rtc.c **** #define N_PREDIV_S 10 + 83:./Src/hw_rtc.c **** + 84:./Src/hw_rtc.c **** /* Synchonuous prediv */ + 85:./Src/hw_rtc.c **** #define PREDIV_S ((1<>N_PREDIV_S) + 101:./Src/hw_rtc.c **** + 102:./Src/hw_rtc.c **** #define COMMON_FACTOR 3 + 103:./Src/hw_rtc.c **** #define CONV_NUMER (MSEC_NUMBER>>COMMON_FACTOR) + 104:./Src/hw_rtc.c **** #define CONV_DENOM (1<<(N_PREDIV_S-COMMON_FACTOR)) + 105:./Src/hw_rtc.c **** + 106:./Src/hw_rtc.c **** #define DAYS_IN_LEAP_YEAR (uint32_t) 366 + 107:./Src/hw_rtc.c **** + 108:./Src/hw_rtc.c **** #define DAYS_IN_YEAR (uint32_t) 365 + 109:./Src/hw_rtc.c **** + 110:./Src/hw_rtc.c **** #define SECONDS_IN_1DAY (uint32_t) 86400 + 111:./Src/hw_rtc.c **** + 112:./Src/hw_rtc.c **** #define SECONDS_IN_1HOUR (uint32_t) 3600 + 113:./Src/hw_rtc.c **** + 114:./Src/hw_rtc.c **** #define SECONDS_IN_1MINUTE (uint32_t) 60 + 115:./Src/hw_rtc.c **** + 116:./Src/hw_rtc.c **** #define MINUTES_IN_1HOUR (uint32_t) 60 + 117:./Src/hw_rtc.c **** + 118:./Src/hw_rtc.c **** #define HOURS_IN_1DAY (uint32_t) 24 + 119:./Src/hw_rtc.c **** + 120:./Src/hw_rtc.c **** #define DAYS_IN_MONTH_CORRECTION_NORM ((uint32_t) 0x99AAA0 ) + 121:./Src/hw_rtc.c **** #define DAYS_IN_MONTH_CORRECTION_LEAP ((uint32_t) 0x445550 ) + 122:./Src/hw_rtc.c **** + 123:./Src/hw_rtc.c **** + 124:./Src/hw_rtc.c **** /* Calculates ceiling(X/N) */ + 125:./Src/hw_rtc.c **** #define DIVC(X,N) ( ( (X) + (N) -1 ) / (N) ) + 126:./Src/hw_rtc.c **** + 127:./Src/hw_rtc.c **** + 128:./Src/hw_rtc.c **** /* Private macro -------------------------------------------------------------*/ + 129:./Src/hw_rtc.c **** /* Private variables ---------------------------------------------------------*/ + 130:./Src/hw_rtc.c **** /*! + 131:./Src/hw_rtc.c **** * \brief Indicates if the RTC is already Initalized or not + 132:./Src/hw_rtc.c **** */ + 133:./Src/hw_rtc.c **** static bool HW_RTC_Initalized = false; + 134:./Src/hw_rtc.c **** + 135:./Src/hw_rtc.c **** /*! + 136:./Src/hw_rtc.c **** * \brief compensates MCU wakeup time + 137:./Src/hw_rtc.c **** */ + 138:./Src/hw_rtc.c **** + 139:./Src/hw_rtc.c **** static bool McuWakeUpTimeInitialized = false; + 140:./Src/hw_rtc.c **** + 141:./Src/hw_rtc.c **** /*! + 142:./Src/hw_rtc.c **** * \brief compensates MCU wakeup time + 143:./Src/hw_rtc.c **** */ + 144:./Src/hw_rtc.c **** + 145:./Src/hw_rtc.c **** static int16_t McuWakeUpTimeCal = 0; + 146:./Src/hw_rtc.c **** + 147:./Src/hw_rtc.c **** /*! + 148:./Src/hw_rtc.c **** * Number of days in each month on a normal year + ARM GAS /tmp/ccGAhXKe.s page 4 + + + 149:./Src/hw_rtc.c **** */ + 150:./Src/hw_rtc.c **** static const uint8_t DaysInMonth[] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + 151:./Src/hw_rtc.c **** + 152:./Src/hw_rtc.c **** /*! + 153:./Src/hw_rtc.c **** * Number of days in each month on a leap year + 154:./Src/hw_rtc.c **** */ + 155:./Src/hw_rtc.c **** static const uint8_t DaysInMonthLeapYear[] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + 156:./Src/hw_rtc.c **** + 157:./Src/hw_rtc.c **** static RTC_HandleTypeDef RtcHandle={0}; + 158:./Src/hw_rtc.c **** + 159:./Src/hw_rtc.c **** static RTC_AlarmTypeDef RTC_AlarmStructure; + 160:./Src/hw_rtc.c **** + 161:./Src/hw_rtc.c **** /*! + 162:./Src/hw_rtc.c **** * Keep the value of the RTC timer when the RTC alarm is set + 163:./Src/hw_rtc.c **** * Set with the HW_RTC_SetTimerContext function + 164:./Src/hw_rtc.c **** * Value is kept as a Reference to calculate alarm + 165:./Src/hw_rtc.c **** */ + 166:./Src/hw_rtc.c **** static RtcTimerContext_t RtcTimerContext; + 167:./Src/hw_rtc.c **** + 168:./Src/hw_rtc.c **** /* Private function prototypes -----------------------------------------------*/ + 169:./Src/hw_rtc.c **** + 170:./Src/hw_rtc.c **** static void HW_RTC_SetConfig( void ); + 171:./Src/hw_rtc.c **** + 172:./Src/hw_rtc.c **** static void HW_RTC_SetAlarmConfig( void ); + 173:./Src/hw_rtc.c **** + 174:./Src/hw_rtc.c **** static void HW_RTC_StartWakeUpAlarm( uint32_t timeoutValue ); + 175:./Src/hw_rtc.c **** + 176:./Src/hw_rtc.c **** static TimerTime_t HW_RTC_GetCalendarValue( RTC_DateTypeDef* RTC_DateStruct, RTC_TimeTypeDef* RTC_ + 177:./Src/hw_rtc.c **** + 178:./Src/hw_rtc.c **** /* Exported functions ---------------------------------------------------------*/ + 179:./Src/hw_rtc.c **** + 180:./Src/hw_rtc.c **** /*! + 181:./Src/hw_rtc.c **** * @brief Initializes the RTC timer + 182:./Src/hw_rtc.c **** * @note The timer is based on the RTC + 183:./Src/hw_rtc.c **** * @param none + 184:./Src/hw_rtc.c **** * @retval none + 185:./Src/hw_rtc.c **** */ + 186:./Src/hw_rtc.c **** void HW_RTC_Init( void ) + 187:./Src/hw_rtc.c **** { + 188:./Src/hw_rtc.c **** if( HW_RTC_Initalized == false ) + 189:./Src/hw_rtc.c **** { + 190:./Src/hw_rtc.c **** HW_RTC_SetConfig( ); + 191:./Src/hw_rtc.c **** HW_RTC_SetAlarmConfig( ); + 192:./Src/hw_rtc.c **** HW_RTC_SetTimerContext( ); + 193:./Src/hw_rtc.c **** HW_RTC_Initalized = true; + 194:./Src/hw_rtc.c **** } + 195:./Src/hw_rtc.c **** } + 196:./Src/hw_rtc.c **** + 197:./Src/hw_rtc.c **** /*! + 198:./Src/hw_rtc.c **** * @brief Configures the RTC timer + 199:./Src/hw_rtc.c **** * @note The timer is based on the RTC + 200:./Src/hw_rtc.c **** * @param none + 201:./Src/hw_rtc.c **** * @retval none + 202:./Src/hw_rtc.c **** */ + 203:./Src/hw_rtc.c **** static void HW_RTC_SetConfig( void ) + 204:./Src/hw_rtc.c **** { + 205:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + ARM GAS /tmp/ccGAhXKe.s page 5 + + + 206:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct; + 207:./Src/hw_rtc.c **** + 208:./Src/hw_rtc.c **** RtcHandle.Instance = RTC; + 209:./Src/hw_rtc.c **** + 210:./Src/hw_rtc.c **** RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; + 211:./Src/hw_rtc.c **** RtcHandle.Init.AsynchPrediv = PREDIV_A; /* RTC_ASYNCH_PREDIV; */ + 212:./Src/hw_rtc.c **** RtcHandle.Init.SynchPrediv = PREDIV_S; /* RTC_SYNCH_PREDIV; */ + 213:./Src/hw_rtc.c **** RtcHandle.Init.OutPut = RTC_OUTPUT; + 214:./Src/hw_rtc.c **** RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 215:./Src/hw_rtc.c **** RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 216:./Src/hw_rtc.c **** + 217:./Src/hw_rtc.c **** HAL_RTC_Init( &RtcHandle ); + 218:./Src/hw_rtc.c **** + 219:./Src/hw_rtc.c **** /*Monday 1st January 2016*/ + 220:./Src/hw_rtc.c **** RTC_DateStruct.Year = 0; + 221:./Src/hw_rtc.c **** RTC_DateStruct.Month = RTC_MONTH_JANUARY; + 222:./Src/hw_rtc.c **** RTC_DateStruct.Date = 1; + 223:./Src/hw_rtc.c **** RTC_DateStruct.WeekDay = RTC_WEEKDAY_MONDAY; + 224:./Src/hw_rtc.c **** HAL_RTC_SetDate(&RtcHandle , &RTC_DateStruct, RTC_FORMAT_BIN); + 225:./Src/hw_rtc.c **** + 226:./Src/hw_rtc.c **** /*at 0:0:0*/ + 227:./Src/hw_rtc.c **** RTC_TimeStruct.Hours = 0; + 228:./Src/hw_rtc.c **** RTC_TimeStruct.Minutes = 0; + 229:./Src/hw_rtc.c **** + 230:./Src/hw_rtc.c **** RTC_TimeStruct.Seconds = 0; + 231:./Src/hw_rtc.c **** RTC_TimeStruct.TimeFormat = 0; + 232:./Src/hw_rtc.c **** RTC_TimeStruct.SubSeconds = 0; + 233:./Src/hw_rtc.c **** RTC_TimeStruct.StoreOperation = RTC_DAYLIGHTSAVING_NONE; + 234:./Src/hw_rtc.c **** RTC_TimeStruct.DayLightSaving = RTC_STOREOPERATION_RESET; + 235:./Src/hw_rtc.c **** + 236:./Src/hw_rtc.c **** HAL_RTC_SetTime(&RtcHandle , &RTC_TimeStruct, RTC_FORMAT_BIN); + 237:./Src/hw_rtc.c **** + 238:./Src/hw_rtc.c **** /*Enable Direct Read of the calendar registers (not through Shadow) */ + 239:./Src/hw_rtc.c **** HAL_RTCEx_EnableBypassShadow(&RtcHandle); + 240:./Src/hw_rtc.c **** } + 241:./Src/hw_rtc.c **** + 242:./Src/hw_rtc.c **** /*! + 243:./Src/hw_rtc.c **** * @brief calculates the wake up time between wake up and mcu start + 244:./Src/hw_rtc.c **** * @note resulotion in RTC_ALARM_TIME_BASE in timer ticks + 245:./Src/hw_rtc.c **** * @param none + 246:./Src/hw_rtc.c **** * @retval none + 247:./Src/hw_rtc.c **** */ + 248:./Src/hw_rtc.c **** void HW_RTC_setMcuWakeUpTime( void ) + 249:./Src/hw_rtc.c **** { + 250:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 251:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct; + 252:./Src/hw_rtc.c **** + 253:./Src/hw_rtc.c **** TimerTime_t now, hit; + 254:./Src/hw_rtc.c **** int16_t McuWakeUpTime; + 255:./Src/hw_rtc.c **** + 256:./Src/hw_rtc.c **** if ((McuWakeUpTimeInitialized == false) && + 257:./Src/hw_rtc.c **** ( HAL_NVIC_GetPendingIRQ( RTC_Alarm_IRQn ) == 1)) + 258:./Src/hw_rtc.c **** { /* warning: works ok if now is below 30 days + 259:./Src/hw_rtc.c **** it is ok since it's done once at first alarm wake-up*/ + 260:./Src/hw_rtc.c **** McuWakeUpTimeInitialized = true; + 261:./Src/hw_rtc.c **** now = HW_RTC_GetCalendarValue( &RTC_DateStruct, &RTC_TimeStruct ); + 262:./Src/hw_rtc.c **** + ARM GAS /tmp/ccGAhXKe.s page 6 + + + 263:./Src/hw_rtc.c **** DBG_GPIO_SET(GPIOB, GPIO_PIN_13); + 264:./Src/hw_rtc.c **** DBG_GPIO_RST(GPIOB, GPIO_PIN_13); + 265:./Src/hw_rtc.c **** HAL_RTC_GetAlarm(&RtcHandle, &RTC_AlarmStructure, RTC_ALARM_A, RTC_FORMAT_BIN ); + 266:./Src/hw_rtc.c **** hit = RTC_AlarmStructure.AlarmTime.Seconds+ + 267:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Minutes+ + 268:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Hours+ + 269:./Src/hw_rtc.c **** 24*(RTC_AlarmStructure.AlarmDateWeekDay))); + 270:./Src/hw_rtc.c **** hit = ( hit << N_PREDIV_S ) + (PREDIV_S - RTC_AlarmStructure.AlarmTime.SubSeconds); + 271:./Src/hw_rtc.c **** + 272:./Src/hw_rtc.c **** McuWakeUpTime = (int16_t) ((now-hit)); + 273:./Src/hw_rtc.c **** McuWakeUpTimeCal += McuWakeUpTime; + 274:./Src/hw_rtc.c **** DBG_PRINTF("Cal=%d, %d\n\r",McuWakeUpTimeCal, McuWakeUpTime); + 275:./Src/hw_rtc.c **** } + 276:./Src/hw_rtc.c **** } + 277:./Src/hw_rtc.c **** + 278:./Src/hw_rtc.c **** int16_t HW_RTC_getMcuWakeUpTime( void ) + 279:./Src/hw_rtc.c **** { + 280:./Src/hw_rtc.c **** return McuWakeUpTimeCal; + 281:./Src/hw_rtc.c **** } + 282:./Src/hw_rtc.c **** + 283:./Src/hw_rtc.c **** /*! + 284:./Src/hw_rtc.c **** * @brief returns the wake up time in ticks + 285:./Src/hw_rtc.c **** * @param none + 286:./Src/hw_rtc.c **** * @retval wake up time in ticks + 287:./Src/hw_rtc.c **** */ + 288:./Src/hw_rtc.c **** uint32_t HW_RTC_GetMinimumTimeout( void ) + 289:./Src/hw_rtc.c **** { + 290:./Src/hw_rtc.c **** return( MIN_ALARM_DELAY ); + 291:./Src/hw_rtc.c **** } + 292:./Src/hw_rtc.c **** + 293:./Src/hw_rtc.c **** /*! + 294:./Src/hw_rtc.c **** * @brief converts time in ms to time in ticks + 295:./Src/hw_rtc.c **** * @param [IN] time in milliseconds + 296:./Src/hw_rtc.c **** * @retval returns time in timer ticks + 297:./Src/hw_rtc.c **** */ + 298:./Src/hw_rtc.c **** uint32_t HW_RTC_ms2Tick( TimerTime_t timeMicroSec ) + 299:./Src/hw_rtc.c **** { + 300:./Src/hw_rtc.c **** /*return( ( timeMicroSec / RTC_ALARM_TIME_BASE ) ); */ + 301:./Src/hw_rtc.c **** return ( uint32_t) ( ( ((uint64_t)timeMicroSec) * CONV_DENOM ) / CONV_NUMER ); + 302:./Src/hw_rtc.c **** } + 303:./Src/hw_rtc.c **** + 304:./Src/hw_rtc.c **** /*! + 305:./Src/hw_rtc.c **** * @brief converts time in ticks to time in ms + 306:./Src/hw_rtc.c **** * @param [IN] time in timer ticks + 307:./Src/hw_rtc.c **** * @retval returns time in milliseconds + 308:./Src/hw_rtc.c **** */ + 309:./Src/hw_rtc.c **** TimerTime_t HW_RTC_Tick2ms( uint32_t tick ) + 310:./Src/hw_rtc.c **** { + 311:./Src/hw_rtc.c **** /*return( ( timeMicroSec * RTC_ALARM_TIME_BASE ) ); */ + 312:./Src/hw_rtc.c **** return ( ( (uint64_t)( tick )* CONV_NUMER ) / CONV_DENOM ); + 313:./Src/hw_rtc.c **** } + 314:./Src/hw_rtc.c **** + 315:./Src/hw_rtc.c **** /*! + 316:./Src/hw_rtc.c **** * @brief Set the alarm + 317:./Src/hw_rtc.c **** * @note The alarm is set at now (read in this funtion) + timeout + 318:./Src/hw_rtc.c **** * @param timeout Duration of the Timer ticks + 319:./Src/hw_rtc.c **** */ + ARM GAS /tmp/ccGAhXKe.s page 7 + + + 320:./Src/hw_rtc.c **** void HW_RTC_SetAlarm( uint32_t timeout ) + 321:./Src/hw_rtc.c **** { + 322:./Src/hw_rtc.c **** /* we don't go in Low Power mode for timeout below MIN_ALARM_DELAY */ + 323:./Src/hw_rtc.c **** if ( (MIN_ALARM_DELAY + McuWakeUpTimeCal ) < ((timeout - HW_RTC_GetTimerElapsedTime( ) )) ) + 324:./Src/hw_rtc.c **** { + 325:./Src/hw_rtc.c **** LowPower_Enable( e_LOW_POWER_RTC ); + 326:./Src/hw_rtc.c **** } + 327:./Src/hw_rtc.c **** else + 328:./Src/hw_rtc.c **** { + 329:./Src/hw_rtc.c **** LowPower_Disable( e_LOW_POWER_RTC ); + 330:./Src/hw_rtc.c **** } + 331:./Src/hw_rtc.c **** + 332:./Src/hw_rtc.c **** if( LowPower_GetState() == 0 ) + 333:./Src/hw_rtc.c **** { + 334:./Src/hw_rtc.c **** LowPower_Enable( e_LOW_POWER_RTC ); + 335:./Src/hw_rtc.c **** timeout = timeout - McuWakeUpTimeCal; + 336:./Src/hw_rtc.c **** } + 337:./Src/hw_rtc.c **** + 338:./Src/hw_rtc.c **** HW_RTC_StartWakeUpAlarm( timeout ); + 339:./Src/hw_rtc.c **** } + 340:./Src/hw_rtc.c **** + 341:./Src/hw_rtc.c **** /*! + 342:./Src/hw_rtc.c **** * @brief Get the RTC timer elapsed time since the last Alarm was set + 343:./Src/hw_rtc.c **** * @param none + 344:./Src/hw_rtc.c **** * @retval RTC Elapsed time in ticks + 345:./Src/hw_rtc.c **** */ + 346:./Src/hw_rtc.c **** uint32_t HW_RTC_GetTimerElapsedTime( void ) + 347:./Src/hw_rtc.c **** { + 348:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 349:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct; + 350:./Src/hw_rtc.c **** + 351:./Src/hw_rtc.c **** TimerTime_t CalendarValue = HW_RTC_GetCalendarValue(&RTC_DateStruct, &RTC_TimeStruct ); + 352:./Src/hw_rtc.c **** + 353:./Src/hw_rtc.c **** return( ( uint32_t )( CalendarValue - RtcTimerContext.Rtc_Time )); + 354:./Src/hw_rtc.c **** } + 355:./Src/hw_rtc.c **** + 356:./Src/hw_rtc.c **** /*! + 357:./Src/hw_rtc.c **** * @brief Get the RTC timer value + 358:./Src/hw_rtc.c **** * @param none + 359:./Src/hw_rtc.c **** * @retval RTC Timer value in ticks + 360:./Src/hw_rtc.c **** */ + 361:./Src/hw_rtc.c **** uint32_t HW_RTC_GetTimerValue( void ) + 362:./Src/hw_rtc.c **** { + 363:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 364:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct; + 365:./Src/hw_rtc.c **** + 366:./Src/hw_rtc.c **** uint32_t CalendarValue = (uint32_t) HW_RTC_GetCalendarValue(&RTC_DateStruct, &RTC_TimeStruct ); + 367:./Src/hw_rtc.c **** + 368:./Src/hw_rtc.c **** return( CalendarValue ); + 369:./Src/hw_rtc.c **** } + 370:./Src/hw_rtc.c **** + 371:./Src/hw_rtc.c **** /*! + 372:./Src/hw_rtc.c **** * @brief Stop the Alarm + 373:./Src/hw_rtc.c **** * @param none + 374:./Src/hw_rtc.c **** * @retval none + 375:./Src/hw_rtc.c **** */ + 376:./Src/hw_rtc.c **** void HW_RTC_StopAlarm( void ) + ARM GAS /tmp/ccGAhXKe.s page 8 + + + 377:./Src/hw_rtc.c **** { + 378:./Src/hw_rtc.c **** + 379:./Src/hw_rtc.c **** /* Clear RTC Alarm Flag */ + 380:./Src/hw_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG( &RtcHandle, RTC_FLAG_ALRAF); + 381:./Src/hw_rtc.c **** + 382:./Src/hw_rtc.c **** /* Disable the Alarm A interrupt */ + 383:./Src/hw_rtc.c **** + 384:./Src/hw_rtc.c **** HAL_RTC_DeactivateAlarm(&RtcHandle, RTC_ALARM_A ); + 385:./Src/hw_rtc.c **** } + 386:./Src/hw_rtc.c **** + 387:./Src/hw_rtc.c **** /*! + 388:./Src/hw_rtc.c **** * @brief RTC IRQ Handler on the RTC Alarm + 389:./Src/hw_rtc.c **** * @param none + 390:./Src/hw_rtc.c **** * @retval none + 391:./Src/hw_rtc.c **** */ + 392:./Src/hw_rtc.c **** void HW_RTC_IrqHandler ( void ) + 393:./Src/hw_rtc.c **** { + 394:./Src/hw_rtc.c **** RTC_HandleTypeDef* hrtc=&RtcHandle; + 395:./Src/hw_rtc.c **** /* enable low power at irq*/ + 396:./Src/hw_rtc.c **** LowPower_Enable( e_LOW_POWER_RTC ); + 397:./Src/hw_rtc.c **** + 398:./Src/hw_rtc.c **** /* Get the AlarmA interrupt source enable status */ + 399:./Src/hw_rtc.c **** if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) + 400:./Src/hw_rtc.c **** { + 401:./Src/hw_rtc.c **** /* Get the pending status of the AlarmA Interrupt */ + 402:./Src/hw_rtc.c **** if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET) + 403:./Src/hw_rtc.c **** { + 404:./Src/hw_rtc.c **** /* Clear the AlarmA interrupt pending bit */ + 405:./Src/hw_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + 406:./Src/hw_rtc.c **** /* Clear the EXTI's line Flag for RTC Alarm */ + 407:./Src/hw_rtc.c **** __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + 408:./Src/hw_rtc.c **** /* AlarmA callback */ + 409:./Src/hw_rtc.c **** HAL_RTC_AlarmAEventCallback(hrtc); + 410:./Src/hw_rtc.c **** } + 411:./Src/hw_rtc.c **** } + 412:./Src/hw_rtc.c **** } + 413:./Src/hw_rtc.c **** + 414:./Src/hw_rtc.c **** + 415:./Src/hw_rtc.c **** /*! + 416:./Src/hw_rtc.c **** * @brief a delay of delay ms by polling RTC + 417:./Src/hw_rtc.c **** * @param delay in ms + 418:./Src/hw_rtc.c **** * @retval none + 419:./Src/hw_rtc.c **** */ + 420:./Src/hw_rtc.c **** void HW_RTC_DelayMs( uint32_t delay ) + 421:./Src/hw_rtc.c **** { + 422:./Src/hw_rtc.c **** TimerTime_t delayValue = 0; + 423:./Src/hw_rtc.c **** TimerTime_t timeout = 0; + 424:./Src/hw_rtc.c **** + 425:./Src/hw_rtc.c **** delayValue = HW_RTC_ms2Tick( delay ); + 426:./Src/hw_rtc.c **** + 427:./Src/hw_rtc.c **** /* Wait delay ms */ + 428:./Src/hw_rtc.c **** timeout = HW_RTC_GetTimerValue( ); + 429:./Src/hw_rtc.c **** while( ( ( HW_RTC_GetTimerValue( ) - timeout ) ) < delayValue ) + 430:./Src/hw_rtc.c **** { + 431:./Src/hw_rtc.c **** __NOP( ); + 432:./Src/hw_rtc.c **** } + 433:./Src/hw_rtc.c **** } + ARM GAS /tmp/ccGAhXKe.s page 9 + + + 434:./Src/hw_rtc.c **** + 435:./Src/hw_rtc.c **** /*! + 436:./Src/hw_rtc.c **** * @brief set Time Reference set also the RTC_DateStruct and RTC_TimeStruct + 437:./Src/hw_rtc.c **** * @param none + 438:./Src/hw_rtc.c **** * @retval Timer Value + 439:./Src/hw_rtc.c **** */ + 440:./Src/hw_rtc.c **** uint32_t HW_RTC_SetTimerContext( void ) + 441:./Src/hw_rtc.c **** { + 442:./Src/hw_rtc.c **** RtcTimerContext.Rtc_Time = HW_RTC_GetCalendarValue( &RtcTimerContext.RTC_Calndr_Date, &RtcTimerCo + 443:./Src/hw_rtc.c **** return ( uint32_t ) RtcTimerContext.Rtc_Time; + 444:./Src/hw_rtc.c **** } + 445:./Src/hw_rtc.c **** + 446:./Src/hw_rtc.c **** /*! + 447:./Src/hw_rtc.c **** * @brief Get the RTC timer Reference + 448:./Src/hw_rtc.c **** * @param none + 449:./Src/hw_rtc.c **** * @retval Timer Value in Ticks + 450:./Src/hw_rtc.c **** */ + 451:./Src/hw_rtc.c **** uint32_t HW_RTC_GetTimerContext( void ) + 452:./Src/hw_rtc.c **** { + 453:./Src/hw_rtc.c **** return (uint32_t) RtcTimerContext.Rtc_Time; + 454:./Src/hw_rtc.c **** } + 455:./Src/hw_rtc.c **** /* Private functions ---------------------------------------------------------*/ + 456:./Src/hw_rtc.c **** + 457:./Src/hw_rtc.c **** /*! + 458:./Src/hw_rtc.c **** * @brief configure alarm at init + 459:./Src/hw_rtc.c **** * @param none + 460:./Src/hw_rtc.c **** * @retval none + 461:./Src/hw_rtc.c **** */ + 462:./Src/hw_rtc.c **** static void HW_RTC_SetAlarmConfig( void ) + 463:./Src/hw_rtc.c **** { + 464:./Src/hw_rtc.c **** HAL_RTC_DeactivateAlarm(&RtcHandle, RTC_ALARM_A); + 465:./Src/hw_rtc.c **** } + 466:./Src/hw_rtc.c **** + 467:./Src/hw_rtc.c **** /*! + 468:./Src/hw_rtc.c **** * @brief start wake up alarm + 469:./Src/hw_rtc.c **** * @note alarm in RtcTimerContext.Rtc_Time + timeoutValue + 470:./Src/hw_rtc.c **** * @param timeoutValue in ticks + 471:./Src/hw_rtc.c **** * @retval none + 472:./Src/hw_rtc.c **** */ + 473:./Src/hw_rtc.c **** static void HW_RTC_StartWakeUpAlarm( uint32_t timeoutValue ) + 474:./Src/hw_rtc.c **** { + 475:./Src/hw_rtc.c **** uint16_t rtcAlarmSubSeconds = 0; + 476:./Src/hw_rtc.c **** uint16_t rtcAlarmSeconds = 0; + 477:./Src/hw_rtc.c **** uint16_t rtcAlarmMinutes = 0; + 478:./Src/hw_rtc.c **** uint16_t rtcAlarmHours = 0; + 479:./Src/hw_rtc.c **** uint16_t rtcAlarmDays = 0; + 480:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct = RtcTimerContext.RTC_Calndr_Time; + 481:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct = RtcTimerContext.RTC_Calndr_Date; + 482:./Src/hw_rtc.c **** + 483:./Src/hw_rtc.c **** HW_RTC_StopAlarm( ); + 484:./Src/hw_rtc.c **** DBG_GPIO_SET(GPIOB, GPIO_PIN_13); + 485:./Src/hw_rtc.c **** + 486:./Src/hw_rtc.c **** /*reverse counter */ + 487:./Src/hw_rtc.c **** rtcAlarmSubSeconds = PREDIV_S - RTC_TimeStruct.SubSeconds; + 488:./Src/hw_rtc.c **** rtcAlarmSubSeconds += ( timeoutValue & PREDIV_S); + 489:./Src/hw_rtc.c **** /* convert timeout to seconds */ + 490:./Src/hw_rtc.c **** timeoutValue >>= N_PREDIV_S; /* convert timeout in seconds */ + ARM GAS /tmp/ccGAhXKe.s page 10 + + + 491:./Src/hw_rtc.c **** + 492:./Src/hw_rtc.c **** /*convert microsecs to RTC format and add to 'Now' */ + 493:./Src/hw_rtc.c **** rtcAlarmDays = RTC_DateStruct.Date; + 494:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1DAY) + 495:./Src/hw_rtc.c **** { + 496:./Src/hw_rtc.c **** timeoutValue -= SECONDS_IN_1DAY; + 497:./Src/hw_rtc.c **** rtcAlarmDays++; + 498:./Src/hw_rtc.c **** } + 499:./Src/hw_rtc.c **** + 500:./Src/hw_rtc.c **** /* calc hours */ + 501:./Src/hw_rtc.c **** rtcAlarmHours = RTC_TimeStruct.Hours; + 502:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1HOUR) + 503:./Src/hw_rtc.c **** { + 504:./Src/hw_rtc.c **** timeoutValue -= SECONDS_IN_1HOUR; + 505:./Src/hw_rtc.c **** rtcAlarmHours++; + 506:./Src/hw_rtc.c **** } + 507:./Src/hw_rtc.c **** + 508:./Src/hw_rtc.c **** /* calc minutes */ + 509:./Src/hw_rtc.c **** rtcAlarmMinutes = RTC_TimeStruct.Minutes; + 510:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1MINUTE) + 511:./Src/hw_rtc.c **** { + 512:./Src/hw_rtc.c **** timeoutValue -= SECONDS_IN_1MINUTE; + 513:./Src/hw_rtc.c **** rtcAlarmMinutes++; + 514:./Src/hw_rtc.c **** } + 515:./Src/hw_rtc.c **** + 516:./Src/hw_rtc.c **** /* calc seconds */ + 517:./Src/hw_rtc.c **** rtcAlarmSeconds = RTC_TimeStruct.Seconds + timeoutValue; + 518:./Src/hw_rtc.c **** + 519:./Src/hw_rtc.c **** /***** correct for modulo********/ + 520:./Src/hw_rtc.c **** while (rtcAlarmSubSeconds >= (PREDIV_S+1)) + 521:./Src/hw_rtc.c **** { + 522:./Src/hw_rtc.c **** rtcAlarmSubSeconds -= (PREDIV_S+1); + 523:./Src/hw_rtc.c **** rtcAlarmSeconds++; + 524:./Src/hw_rtc.c **** } + 525:./Src/hw_rtc.c **** + 526:./Src/hw_rtc.c **** while (rtcAlarmSeconds >= SECONDS_IN_1MINUTE) + 527:./Src/hw_rtc.c **** { + 528:./Src/hw_rtc.c **** rtcAlarmSeconds -= SECONDS_IN_1MINUTE; + 529:./Src/hw_rtc.c **** rtcAlarmMinutes++; + 530:./Src/hw_rtc.c **** } + 531:./Src/hw_rtc.c **** + 532:./Src/hw_rtc.c **** while (rtcAlarmMinutes >= MINUTES_IN_1HOUR) + 533:./Src/hw_rtc.c **** { + 534:./Src/hw_rtc.c **** rtcAlarmMinutes -= MINUTES_IN_1HOUR; + 535:./Src/hw_rtc.c **** rtcAlarmHours++; + 536:./Src/hw_rtc.c **** } + 537:./Src/hw_rtc.c **** + 538:./Src/hw_rtc.c **** while (rtcAlarmHours >= HOURS_IN_1DAY) + 539:./Src/hw_rtc.c **** { + 540:./Src/hw_rtc.c **** rtcAlarmHours -= HOURS_IN_1DAY; + 541:./Src/hw_rtc.c **** rtcAlarmDays++; + 542:./Src/hw_rtc.c **** } + 543:./Src/hw_rtc.c **** + 544:./Src/hw_rtc.c **** if( RTC_DateStruct.Year % 4 == 0 ) + 545:./Src/hw_rtc.c **** { + 546:./Src/hw_rtc.c **** if( rtcAlarmDays > DaysInMonthLeapYear[ RTC_DateStruct.Month - 1 ] ) + 547:./Src/hw_rtc.c **** { + ARM GAS /tmp/ccGAhXKe.s page 11 + + + 548:./Src/hw_rtc.c **** rtcAlarmDays = rtcAlarmDays % DaysInMonthLeapYear[ RTC_DateStruct.Month - 1 ]; + 549:./Src/hw_rtc.c **** } + 550:./Src/hw_rtc.c **** } + 551:./Src/hw_rtc.c **** else + 552:./Src/hw_rtc.c **** { + 553:./Src/hw_rtc.c **** if( rtcAlarmDays > DaysInMonth[ RTC_DateStruct.Month - 1 ] ) + 554:./Src/hw_rtc.c **** { + 555:./Src/hw_rtc.c **** rtcAlarmDays = rtcAlarmDays % DaysInMonth[ RTC_DateStruct.Month - 1 ]; + 556:./Src/hw_rtc.c **** } + 557:./Src/hw_rtc.c **** } + 558:./Src/hw_rtc.c **** + 559:./Src/hw_rtc.c **** /* Set RTC_AlarmStructure with calculated values*/ + 560:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.SubSeconds = PREDIV_S-rtcAlarmSubSeconds; + 561:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmSubSecondMask = HW_RTC_ALARMSUBSECONDMASK; + 562:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Seconds = rtcAlarmSeconds; + 563:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Minutes = rtcAlarmMinutes; + 564:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Hours = rtcAlarmHours; + 565:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmDateWeekDay = ( uint8_t )rtcAlarmDays; + 566:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.TimeFormat = RTC_TimeStruct.TimeFormat; + 567:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE; + 568:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmMask = RTC_ALARMMASK_NONE; + 569:./Src/hw_rtc.c **** RTC_AlarmStructure.Alarm = RTC_ALARM_A; + 570:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 571:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + 572:./Src/hw_rtc.c **** + 573:./Src/hw_rtc.c **** /* Set RTC_Alarm */ + 574:./Src/hw_rtc.c **** HAL_RTC_SetAlarm_IT( &RtcHandle, &RTC_AlarmStructure, RTC_FORMAT_BIN ); + 575:./Src/hw_rtc.c **** + 576:./Src/hw_rtc.c **** /* Debug Printf*/ + 577:./Src/hw_rtc.c **** DBG( HW_RTC_GetCalendarValue( &RTC_DateStruct, &RTC_TimeStruct ); ); + 578:./Src/hw_rtc.c **** DBG_PRINTF("it's %d:%d:%d:%d ", RTC_TimeStruct.Hours, RTC_TimeStruct.Minutes, RTC_TimeStruct.Seco + 579:./Src/hw_rtc.c **** DBG_PRINTF("WU@ %d:%d:%d:%d\n\r", rtcAlarmHours, rtcAlarmMinutes, rtcAlarmSeconds, (rtcAlarmSubSe + 580:./Src/hw_rtc.c **** + 581:./Src/hw_rtc.c **** DBG_GPIO_RST(GPIOB, GPIO_PIN_13); + 582:./Src/hw_rtc.c **** } + 583:./Src/hw_rtc.c **** + 584:./Src/hw_rtc.c **** + 585:./Src/hw_rtc.c **** /*! + 586:./Src/hw_rtc.c **** * @brief get current time from calendar in ticks + 587:./Src/hw_rtc.c **** * @param pointer to RTC_DateStruct + 588:./Src/hw_rtc.c **** * @param pointer to RTC_TimeStruct + 589:./Src/hw_rtc.c **** * @retval time in ticks + 590:./Src/hw_rtc.c **** */ + 591:./Src/hw_rtc.c **** static TimerTime_t HW_RTC_GetCalendarValue( RTC_DateTypeDef* RTC_DateStruct, RTC_TimeTypeDef* RTC_T + 592:./Src/hw_rtc.c **** { + 25 .loc 1 592 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 24 + 33 .cfi_offset 3, -24 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + 36 .cfi_offset 6, -12 + ARM GAS /tmp/ccGAhXKe.s page 12 + + + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 39 0002 0600 movs r6, r0 + 40 0004 0C00 movs r4, r1 + 41 .LVL1: + 593:./Src/hw_rtc.c **** TimerTime_t calendarValue = 0; + 594:./Src/hw_rtc.c **** uint32_t first_read; + 595:./Src/hw_rtc.c **** uint32_t correction; + 596:./Src/hw_rtc.c **** + 597:./Src/hw_rtc.c **** /* Get Time and Date*/ + 598:./Src/hw_rtc.c **** HAL_RTC_GetTime( &RtcHandle, RTC_TimeStruct, RTC_FORMAT_BIN ); + 42 .loc 1 598 0 + 43 0006 0022 movs r2, #0 + 44 0008 2448 ldr r0, .L6 + 45 .LVL2: + 46 000a FFF7FEFF bl HAL_RTC_GetTime + 47 .LVL3: + 48 .L2: + 599:./Src/hw_rtc.c **** + 600:./Src/hw_rtc.c **** /* make sure it is correct due to asynchronus nature of RTC*/ + 601:./Src/hw_rtc.c **** do { + 602:./Src/hw_rtc.c **** first_read = RTC_TimeStruct->SubSeconds; + 49 .loc 1 602 0 discriminator 1 + 50 000e 6768 ldr r7, [r4, #4] + 51 .LVL4: + 603:./Src/hw_rtc.c **** HAL_RTC_GetDate( &RtcHandle, RTC_DateStruct, RTC_FORMAT_BIN ); + 52 .loc 1 603 0 discriminator 1 + 53 0010 224D ldr r5, .L6 + 54 0012 0022 movs r2, #0 + 55 0014 3100 movs r1, r6 + 56 0016 2800 movs r0, r5 + 57 0018 FFF7FEFF bl HAL_RTC_GetDate + 58 .LVL5: + 604:./Src/hw_rtc.c **** HAL_RTC_GetTime( &RtcHandle, RTC_TimeStruct, RTC_FORMAT_BIN ); + 59 .loc 1 604 0 discriminator 1 + 60 001c 0022 movs r2, #0 + 61 001e 2100 movs r1, r4 + 62 0020 2800 movs r0, r5 + 63 0022 FFF7FEFF bl HAL_RTC_GetTime + 64 .LVL6: + 605:./Src/hw_rtc.c **** } while (first_read != RTC_TimeStruct->SubSeconds); + 65 .loc 1 605 0 discriminator 1 + 66 0026 6268 ldr r2, [r4, #4] + 67 0028 BA42 cmp r2, r7 + 68 002a F0D1 bne .L2 + 606:./Src/hw_rtc.c **** + 607:./Src/hw_rtc.c **** /* calculte amount of elapsed days since 01/01/2000 */ + 608:./Src/hw_rtc.c **** calendarValue= DIVC( (DAYS_IN_YEAR*3 + DAYS_IN_LEAP_YEAR)* RTC_DateStruct->Year , 4); + 69 .loc 1 608 0 + 70 002c F178 ldrb r1, [r6, #3] + 71 002e 1C4B ldr r3, .L6+4 + 72 0030 4B43 muls r3, r1 + 73 0032 0333 adds r3, r3, #3 + 74 0034 9D08 lsrs r5, r3, #2 + 75 .LVL7: + 609:./Src/hw_rtc.c **** + 610:./Src/hw_rtc.c **** correction = ( (RTC_DateStruct->Year % 4) == 0 ) ? DAYS_IN_MONTH_CORRECTION_LEAP : DAYS_IN_MONTH_ + ARM GAS /tmp/ccGAhXKe.s page 13 + + + 76 .loc 1 610 0 + 77 0036 8B07 lsls r3, r1, #30 + 78 0038 2ED0 beq .L5 + 79 003a 1A4F ldr r7, .L6+8 + 80 .LVL8: + 81 .L3: + 611:./Src/hw_rtc.c **** + 612:./Src/hw_rtc.c **** calendarValue +=( DIVC( (RTC_DateStruct->Month-1)*(30+31) ,2 ) - (((correction>> ((RTC_DateStruct + 82 .loc 1 612 0 discriminator 4 + 83 003c 7078 ldrb r0, [r6, #1] + 84 003e 0138 subs r0, r0, #1 + 85 0040 0301 lsls r3, r0, #4 + 86 0042 1B1A subs r3, r3, r0 + 87 0044 9B00 lsls r3, r3, #2 + 88 0046 1B18 adds r3, r3, r0 + 89 0048 0133 adds r3, r3, #1 + 90 004a D90F lsrs r1, r3, #31 + 91 004c C918 adds r1, r1, r3 + 92 004e 4910 asrs r1, r1, #1 + 93 0050 4000 lsls r0, r0, #1 + 94 0052 C740 lsrs r7, r7, r0 + 95 .LVL9: + 96 0054 0323 movs r3, #3 + 97 0056 3B40 ands r3, r7 + 98 0058 CB1A subs r3, r1, r3 + 99 005a 5B19 adds r3, r3, r5 + 100 .LVL10: + 613:./Src/hw_rtc.c **** + 614:./Src/hw_rtc.c **** calendarValue += (RTC_DateStruct->Date -1); + 101 .loc 1 614 0 discriminator 4 + 102 005c B178 ldrb r1, [r6, #2] + 103 005e CB18 adds r3, r1, r3 + 104 .LVL11: + 105 0060 013B subs r3, r3, #1 + 106 .LVL12: + 615:./Src/hw_rtc.c **** + 616:./Src/hw_rtc.c **** /* convert from days to seconds */ + 617:./Src/hw_rtc.c **** calendarValue *= SECONDS_IN_1DAY; + 107 .loc 1 617 0 discriminator 4 + 108 0062 5900 lsls r1, r3, #1 + 109 0064 CB18 adds r3, r1, r3 + 110 .LVL13: + 111 0066 1901 lsls r1, r3, #4 + 112 0068 CB1A subs r3, r1, r3 + 113 006a 1901 lsls r1, r3, #4 + 114 006c C91A subs r1, r1, r3 + 115 006e CE01 lsls r6, r1, #7 + 116 .LVL14: + 618:./Src/hw_rtc.c **** + 619:./Src/hw_rtc.c **** calendarValue += ( ( uint32_t )RTC_TimeStruct->Seconds + + 117 .loc 1 619 0 discriminator 4 + 118 0070 A778 ldrb r7, [r4, #2] + 620:./Src/hw_rtc.c **** ( ( uint32_t )RTC_TimeStruct->Minutes * SECONDS_IN_1MINUTE ) + + 621:./Src/hw_rtc.c **** ( ( uint32_t )RTC_TimeStruct->Hours * SECONDS_IN_1HOUR ) ) ; + 119 .loc 1 621 0 discriminator 4 + 120 0072 2578 ldrb r5, [r4] + 121 0074 2901 lsls r1, r5, #4 + ARM GAS /tmp/ccGAhXKe.s page 14 + + + 122 0076 4D1B subs r5, r1, r5 + 123 0078 2901 lsls r1, r5, #4 + 124 007a 491B subs r1, r1, r5 + 125 007c 0B01 lsls r3, r1, #4 + 620:./Src/hw_rtc.c **** ( ( uint32_t )RTC_TimeStruct->Minutes * SECONDS_IN_1MINUTE ) + + 126 .loc 1 620 0 discriminator 4 + 127 007e 6078 ldrb r0, [r4, #1] + 128 0080 0101 lsls r1, r0, #4 + 129 0082 091A subs r1, r1, r0 + 130 0084 8800 lsls r0, r1, #2 + 131 0086 1818 adds r0, r3, r0 + 132 0088 C019 adds r0, r0, r7 + 619:./Src/hw_rtc.c **** ( ( uint32_t )RTC_TimeStruct->Minutes * SECONDS_IN_1MINUTE ) + + 133 .loc 1 619 0 discriminator 4 + 134 008a 8019 adds r0, r0, r6 + 135 .LVL15: + 622:./Src/hw_rtc.c **** + 623:./Src/hw_rtc.c **** + 624:./Src/hw_rtc.c **** + 625:./Src/hw_rtc.c **** calendarValue = (calendarValue<SubSeconds); + 136 .loc 1 625 0 discriminator 4 + 137 008c 8002 lsls r0, r0, #10 + 138 .LVL16: + 139 008e 801A subs r0, r0, r2 + 140 0090 054B ldr r3, .L6+12 + 141 .LVL17: + 142 0092 9C46 mov ip, r3 + 143 0094 6044 add r0, r0, ip + 144 .LVL18: + 626:./Src/hw_rtc.c **** + 627:./Src/hw_rtc.c **** return( calendarValue ); + 628:./Src/hw_rtc.c **** } + 145 .loc 1 628 0 discriminator 4 + 146 @ sp needed + 147 .LVL19: + 148 0096 F8BD pop {r3, r4, r5, r6, r7, pc} + 149 .LVL20: + 150 .L5: + 610:./Src/hw_rtc.c **** + 151 .loc 1 610 0 + 152 0098 044F ldr r7, .L6+16 + 153 .LVL21: + 154 009a CFE7 b .L3 + 155 .L7: + 156 .align 2 + 157 .L6: + 158 009c 00000000 .word .LANCHOR0 + 159 00a0 B5050000 .word 1461 + 160 00a4 A0AA9900 .word 10070688 + 161 00a8 FF030000 .word 1023 + 162 00ac 50554400 .word 4478288 + 163 .cfi_endproc + 164 .LFE113: + 166 .section .text.HW_RTC_Init,"ax",%progbits + 167 .align 1 + 168 .global HW_RTC_Init + 169 .syntax unified + ARM GAS /tmp/ccGAhXKe.s page 15 + + + 170 .code 16 + 171 .thumb_func + 172 .fpu softvfp + 174 HW_RTC_Init: + 175 .LFB96: + 187:./Src/hw_rtc.c **** if( HW_RTC_Initalized == false ) + 176 .loc 1 187 0 + 177 .cfi_startproc + 178 @ args = 0, pretend = 0, frame = 24 + 179 @ frame_needed = 0, uses_anonymous_args = 0 + 180 0000 70B5 push {r4, r5, r6, lr} + 181 .LCFI1: + 182 .cfi_def_cfa_offset 16 + 183 .cfi_offset 4, -16 + 184 .cfi_offset 5, -12 + 185 .cfi_offset 6, -8 + 186 .cfi_offset 14, -4 + 187 0002 86B0 sub sp, sp, #24 + 188 .LCFI2: + 189 .cfi_def_cfa_offset 40 + 188:./Src/hw_rtc.c **** { + 190 .loc 1 188 0 + 191 0004 1E4B ldr r3, .L11 + 192 0006 1B78 ldrb r3, [r3] + 193 0008 002B cmp r3, #0 + 194 000a 01D0 beq .L10 + 195 .L8: + 195:./Src/hw_rtc.c **** + 196 .loc 1 195 0 + 197 000c 06B0 add sp, sp, #24 + 198 @ sp needed + 199 000e 70BD pop {r4, r5, r6, pc} + 200 .L10: + 201 .LBB26: + 202 .LBB27: + 208:./Src/hw_rtc.c **** + 203 .loc 1 208 0 + 204 0010 1C4C ldr r4, .L11+4 + 205 0012 1D4B ldr r3, .L11+8 + 206 0014 2360 str r3, [r4] + 210:./Src/hw_rtc.c **** RtcHandle.Init.AsynchPrediv = PREDIV_A; /* RTC_ASYNCH_PREDIV; */ + 207 .loc 1 210 0 + 208 0016 0025 movs r5, #0 + 209 0018 6560 str r5, [r4, #4] + 211:./Src/hw_rtc.c **** RtcHandle.Init.SynchPrediv = PREDIV_S; /* RTC_SYNCH_PREDIV; */ + 210 .loc 1 211 0 + 211 001a 1F23 movs r3, #31 + 212 001c A360 str r3, [r4, #8] + 212:./Src/hw_rtc.c **** RtcHandle.Init.OutPut = RTC_OUTPUT; + 213 .loc 1 212 0 + 214 001e 1B4B ldr r3, .L11+12 + 215 0020 E360 str r3, [r4, #12] + 213:./Src/hw_rtc.c **** RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 216 .loc 1 213 0 + 217 0022 2561 str r5, [r4, #16] + 214:./Src/hw_rtc.c **** RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 218 .loc 1 214 0 + ARM GAS /tmp/ccGAhXKe.s page 16 + + + 219 0024 A561 str r5, [r4, #24] + 215:./Src/hw_rtc.c **** + 220 .loc 1 215 0 + 221 0026 E561 str r5, [r4, #28] + 217:./Src/hw_rtc.c **** + 222 .loc 1 217 0 + 223 0028 2000 movs r0, r4 + 224 002a FFF7FEFF bl HAL_RTC_Init + 225 .LVL22: + 220:./Src/hw_rtc.c **** RTC_DateStruct.Month = RTC_MONTH_JANUARY; + 226 .loc 1 220 0 + 227 002e 6B46 mov r3, sp + 228 0030 DD70 strb r5, [r3, #3] + 221:./Src/hw_rtc.c **** RTC_DateStruct.Date = 1; + 229 .loc 1 221 0 + 230 0032 0126 movs r6, #1 + 231 0034 5E70 strb r6, [r3, #1] + 222:./Src/hw_rtc.c **** RTC_DateStruct.WeekDay = RTC_WEEKDAY_MONDAY; + 232 .loc 1 222 0 + 233 0036 9E70 strb r6, [r3, #2] + 223:./Src/hw_rtc.c **** HAL_RTC_SetDate(&RtcHandle , &RTC_DateStruct, RTC_FORMAT_BIN); + 234 .loc 1 223 0 + 235 0038 1E70 strb r6, [r3] + 224:./Src/hw_rtc.c **** + 236 .loc 1 224 0 + 237 003a 0022 movs r2, #0 + 238 003c 6946 mov r1, sp + 239 003e 2000 movs r0, r4 + 240 0040 FFF7FEFF bl HAL_RTC_SetDate + 241 .LVL23: + 227:./Src/hw_rtc.c **** RTC_TimeStruct.Minutes = 0; + 242 .loc 1 227 0 + 243 0044 01A9 add r1, sp, #4 + 244 0046 0D70 strb r5, [r1] + 228:./Src/hw_rtc.c **** + 245 .loc 1 228 0 + 246 0048 4D70 strb r5, [r1, #1] + 230:./Src/hw_rtc.c **** RTC_TimeStruct.TimeFormat = 0; + 247 .loc 1 230 0 + 248 004a 8D70 strb r5, [r1, #2] + 231:./Src/hw_rtc.c **** RTC_TimeStruct.SubSeconds = 0; + 249 .loc 1 231 0 + 250 004c CD70 strb r5, [r1, #3] + 232:./Src/hw_rtc.c **** RTC_TimeStruct.StoreOperation = RTC_DAYLIGHTSAVING_NONE; + 251 .loc 1 232 0 + 252 004e 4D60 str r5, [r1, #4] + 233:./Src/hw_rtc.c **** RTC_TimeStruct.DayLightSaving = RTC_STOREOPERATION_RESET; + 253 .loc 1 233 0 + 254 0050 0D61 str r5, [r1, #16] + 234:./Src/hw_rtc.c **** + 255 .loc 1 234 0 + 256 0052 CD60 str r5, [r1, #12] + 236:./Src/hw_rtc.c **** + 257 .loc 1 236 0 + 258 0054 0022 movs r2, #0 + 259 0056 2000 movs r0, r4 + 260 0058 FFF7FEFF bl HAL_RTC_SetTime + ARM GAS /tmp/ccGAhXKe.s page 17 + + + 261 .LVL24: + 239:./Src/hw_rtc.c **** } + 262 .loc 1 239 0 + 263 005c 2000 movs r0, r4 + 264 005e FFF7FEFF bl HAL_RTCEx_EnableBypassShadow + 265 .LVL25: + 266 .LBE27: + 267 .LBE26: + 268 .LBB28: + 269 .LBB29: + 464:./Src/hw_rtc.c **** } + 270 .loc 1 464 0 + 271 0062 8021 movs r1, #128 + 272 0064 4900 lsls r1, r1, #1 + 273 0066 2000 movs r0, r4 + 274 0068 FFF7FEFF bl HAL_RTC_DeactivateAlarm + 275 .LVL26: + 276 .LBE29: + 277 .LBE28: + 278 .LBB30: + 279 .LBB31: + 442:./Src/hw_rtc.c **** return ( uint32_t ) RtcTimerContext.Rtc_Time; + 280 .loc 1 442 0 + 281 006c 084C ldr r4, .L11+16 + 282 006e 211D adds r1, r4, #4 + 283 0070 2000 movs r0, r4 + 284 0072 1830 adds r0, r0, #24 + 285 0074 FFF7FEFF bl HW_RTC_GetCalendarValue + 286 .LVL27: + 287 0078 2060 str r0, [r4] + 288 .LBE31: + 289 .LBE30: + 193:./Src/hw_rtc.c **** } + 290 .loc 1 193 0 + 291 007a 014B ldr r3, .L11 + 292 007c 1E70 strb r6, [r3] + 195:./Src/hw_rtc.c **** + 293 .loc 1 195 0 + 294 007e C5E7 b .L8 + 295 .L12: + 296 .align 2 + 297 .L11: + 298 0080 00000000 .word .LANCHOR1 + 299 0084 00000000 .word .LANCHOR0 + 300 0088 00280040 .word 1073752064 + 301 008c FF030000 .word 1023 + 302 0090 00000000 .word .LANCHOR2 + 303 .cfi_endproc + 304 .LFE96: + 306 .section .text.HW_RTC_setMcuWakeUpTime,"ax",%progbits + 307 .align 1 + 308 .global HW_RTC_setMcuWakeUpTime + 309 .syntax unified + 310 .code 16 + 311 .thumb_func + 312 .fpu softvfp + 314 HW_RTC_setMcuWakeUpTime: + ARM GAS /tmp/ccGAhXKe.s page 18 + + + 315 .LFB98: + 249:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 316 .loc 1 249 0 + 317 .cfi_startproc + 318 @ args = 0, pretend = 0, frame = 24 + 319 @ frame_needed = 0, uses_anonymous_args = 0 + 320 0000 70B5 push {r4, r5, r6, lr} + 321 .LCFI3: + 322 .cfi_def_cfa_offset 16 + 323 .cfi_offset 4, -16 + 324 .cfi_offset 5, -12 + 325 .cfi_offset 6, -8 + 326 .cfi_offset 14, -4 + 327 0002 86B0 sub sp, sp, #24 + 328 .LCFI4: + 329 .cfi_def_cfa_offset 40 + 256:./Src/hw_rtc.c **** ( HAL_NVIC_GetPendingIRQ( RTC_Alarm_IRQn ) == 1)) + 330 .loc 1 256 0 + 331 0004 1C4B ldr r3, .L16 + 332 0006 1B78 ldrb r3, [r3] + 333 0008 002B cmp r3, #0 + 334 000a 01D0 beq .L15 + 335 .L13: + 276:./Src/hw_rtc.c **** + 336 .loc 1 276 0 + 337 000c 06B0 add sp, sp, #24 + 338 @ sp needed + 339 000e 70BD pop {r4, r5, r6, pc} + 340 .L15: + 257:./Src/hw_rtc.c **** { /* warning: works ok if now is below 30 days + 341 .loc 1 257 0 discriminator 1 + 342 0010 0220 movs r0, #2 + 343 0012 FFF7FEFF bl HAL_NVIC_GetPendingIRQ + 344 .LVL28: + 256:./Src/hw_rtc.c **** ( HAL_NVIC_GetPendingIRQ( RTC_Alarm_IRQn ) == 1)) + 345 .loc 1 256 0 discriminator 1 + 346 0016 0128 cmp r0, #1 + 347 0018 F8D1 bne .L13 + 260:./Src/hw_rtc.c **** now = HW_RTC_GetCalendarValue( &RTC_DateStruct, &RTC_TimeStruct ); + 348 .loc 1 260 0 + 349 001a 174B ldr r3, .L16 + 350 001c 0122 movs r2, #1 + 351 001e 1A70 strb r2, [r3] + 261:./Src/hw_rtc.c **** + 352 .loc 1 261 0 + 353 0020 01A9 add r1, sp, #4 + 354 0022 6846 mov r0, sp + 355 0024 FFF7FEFF bl HW_RTC_GetCalendarValue + 356 .LVL29: + 357 0028 0400 movs r4, r0 + 358 .LVL30: + 265:./Src/hw_rtc.c **** hit = RTC_AlarmStructure.AlarmTime.Seconds+ + 359 .loc 1 265 0 + 360 002a 8022 movs r2, #128 + 361 002c 134D ldr r5, .L16+4 + 362 002e 0023 movs r3, #0 + 363 0030 5200 lsls r2, r2, #1 + ARM GAS /tmp/ccGAhXKe.s page 19 + + + 364 0032 2900 movs r1, r5 + 365 0034 1248 ldr r0, .L16+8 + 366 .LVL31: + 367 0036 FFF7FEFF bl HAL_RTC_GetAlarm + 368 .LVL32: + 266:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Minutes+ + 369 .loc 1 266 0 + 370 003a A878 ldrb r0, [r5, #2] + 267:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Hours+ + 371 .loc 1 267 0 + 372 003c 6B78 ldrb r3, [r5, #1] + 268:./Src/hw_rtc.c **** 24*(RTC_AlarmStructure.AlarmDateWeekDay))); + 373 .loc 1 268 0 + 374 003e 2978 ldrb r1, [r5] + 269:./Src/hw_rtc.c **** hit = ( hit << N_PREDIV_S ) + (PREDIV_S - RTC_AlarmStructure.AlarmTime.SubSeconds); + 375 .loc 1 269 0 + 376 0040 2022 movs r2, #32 + 377 0042 AA5C ldrb r2, [r5, r2] + 378 0044 5600 lsls r6, r2, #1 + 379 0046 B618 adds r6, r6, r2 + 380 0048 F200 lsls r2, r6, #3 + 268:./Src/hw_rtc.c **** 24*(RTC_AlarmStructure.AlarmDateWeekDay))); + 381 .loc 1 268 0 + 382 004a 8A18 adds r2, r1, r2 + 383 004c 1101 lsls r1, r2, #4 + 384 004e 891A subs r1, r1, r2 + 385 0050 8A00 lsls r2, r1, #2 + 267:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Hours+ + 386 .loc 1 267 0 + 387 0052 9A18 adds r2, r3, r2 + 388 0054 1301 lsls r3, r2, #4 + 389 0056 9B1A subs r3, r3, r2 + 390 0058 9A00 lsls r2, r3, #2 + 266:./Src/hw_rtc.c **** 60*(RTC_AlarmStructure.AlarmTime.Minutes+ + 391 .loc 1 266 0 + 392 005a 8018 adds r0, r0, r2 + 393 .LVL33: + 270:./Src/hw_rtc.c **** + 394 .loc 1 270 0 + 395 005c 8002 lsls r0, r0, #10 + 396 .LVL34: + 397 005e 6B68 ldr r3, [r5, #4] + 398 0060 C01A subs r0, r0, r3 + 399 0062 084B ldr r3, .L16+12 + 400 0064 9C46 mov ip, r3 + 401 0066 6044 add r0, r0, ip + 402 .LVL35: + 272:./Src/hw_rtc.c **** McuWakeUpTimeCal += McuWakeUpTime; + 403 .loc 1 272 0 + 404 0068 201A subs r0, r4, r0 + 405 .LVL36: + 406 006a 80B2 uxth r0, r0 + 407 .LVL37: + 273:./Src/hw_rtc.c **** DBG_PRINTF("Cal=%d, %d\n\r",McuWakeUpTimeCal, McuWakeUpTime); + 408 .loc 1 273 0 + 409 006c 064B ldr r3, .L16+16 + 410 .LVL38: + ARM GAS /tmp/ccGAhXKe.s page 20 + + + 411 006e 1C88 ldrh r4, [r3] + 412 .LVL39: + 413 0070 0019 adds r0, r0, r4 + 414 .LVL40: + 415 0072 1880 strh r0, [r3] + 276:./Src/hw_rtc.c **** + 416 .loc 1 276 0 + 417 0074 CAE7 b .L13 + 418 .L17: + 419 0076 C046 .align 2 + 420 .L16: + 421 0078 00000000 .word .LANCHOR3 + 422 007c 00000000 .word .LANCHOR4 + 423 0080 00000000 .word .LANCHOR0 + 424 0084 FF030000 .word 1023 + 425 0088 00000000 .word .LANCHOR5 + 426 .cfi_endproc + 427 .LFE98: + 429 .section .text.HW_RTC_getMcuWakeUpTime,"ax",%progbits + 430 .align 1 + 431 .global HW_RTC_getMcuWakeUpTime + 432 .syntax unified + 433 .code 16 + 434 .thumb_func + 435 .fpu softvfp + 437 HW_RTC_getMcuWakeUpTime: + 438 .LFB99: + 279:./Src/hw_rtc.c **** return McuWakeUpTimeCal; + 439 .loc 1 279 0 + 440 .cfi_startproc + 441 @ args = 0, pretend = 0, frame = 0 + 442 @ frame_needed = 0, uses_anonymous_args = 0 + 443 @ link register save eliminated. + 280:./Src/hw_rtc.c **** } + 444 .loc 1 280 0 + 445 0000 014B ldr r3, .L19 + 446 0002 0020 movs r0, #0 + 447 0004 185E ldrsh r0, [r3, r0] + 281:./Src/hw_rtc.c **** + 448 .loc 1 281 0 + 449 @ sp needed + 450 0006 7047 bx lr + 451 .L20: + 452 .align 2 + 453 .L19: + 454 0008 00000000 .word .LANCHOR5 + 455 .cfi_endproc + 456 .LFE99: + 458 .section .text.HW_RTC_GetMinimumTimeout,"ax",%progbits + 459 .align 1 + 460 .global HW_RTC_GetMinimumTimeout + 461 .syntax unified + 462 .code 16 + 463 .thumb_func + 464 .fpu softvfp + 466 HW_RTC_GetMinimumTimeout: + 467 .LFB100: + ARM GAS /tmp/ccGAhXKe.s page 21 + + + 289:./Src/hw_rtc.c **** return( MIN_ALARM_DELAY ); + 468 .loc 1 289 0 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 0 + 471 @ frame_needed = 0, uses_anonymous_args = 0 + 472 @ link register save eliminated. + 291:./Src/hw_rtc.c **** + 473 .loc 1 291 0 + 474 0000 0320 movs r0, #3 + 475 @ sp needed + 476 0002 7047 bx lr + 477 .cfi_endproc + 478 .LFE100: + 480 .global __aeabi_uldivmod + 481 .section .text.HW_RTC_ms2Tick,"ax",%progbits + 482 .align 1 + 483 .global HW_RTC_ms2Tick + 484 .syntax unified + 485 .code 16 + 486 .thumb_func + 487 .fpu softvfp + 489 HW_RTC_ms2Tick: + 490 .LFB101: + 299:./Src/hw_rtc.c **** /*return( ( timeMicroSec / RTC_ALARM_TIME_BASE ) ); */ + 491 .loc 1 299 0 + 492 .cfi_startproc + 493 @ args = 0, pretend = 0, frame = 0 + 494 @ frame_needed = 0, uses_anonymous_args = 0 + 495 .LVL41: + 496 0000 10B5 push {r4, lr} + 497 .LCFI5: + 498 .cfi_def_cfa_offset 8 + 499 .cfi_offset 4, -8 + 500 .cfi_offset 14, -4 + 301:./Src/hw_rtc.c **** } + 501 .loc 1 301 0 + 502 0002 410E lsrs r1, r0, #25 + 503 0004 C001 lsls r0, r0, #7 + 504 .LVL42: + 505 0006 7D22 movs r2, #125 + 506 0008 0023 movs r3, #0 + 507 000a FFF7FEFF bl __aeabi_uldivmod + 508 .LVL43: + 302:./Src/hw_rtc.c **** + 509 .loc 1 302 0 + 510 @ sp needed + 511 000e 10BD pop {r4, pc} + 512 .cfi_endproc + 513 .LFE101: + 515 .section .text.HW_RTC_Tick2ms,"ax",%progbits + 516 .align 1 + 517 .global HW_RTC_Tick2ms + 518 .syntax unified + 519 .code 16 + 520 .thumb_func + 521 .fpu softvfp + 523 HW_RTC_Tick2ms: + ARM GAS /tmp/ccGAhXKe.s page 22 + + + 524 .LFB102: + 310:./Src/hw_rtc.c **** /*return( ( timeMicroSec * RTC_ALARM_TIME_BASE ) ); */ + 525 .loc 1 310 0 + 526 .cfi_startproc + 527 @ args = 0, pretend = 0, frame = 0 + 528 @ frame_needed = 0, uses_anonymous_args = 0 + 529 .LVL44: + 530 0000 70B5 push {r4, r5, r6, lr} + 531 .LCFI6: + 532 .cfi_def_cfa_offset 16 + 533 .cfi_offset 4, -16 + 534 .cfi_offset 5, -12 + 535 .cfi_offset 6, -8 + 536 .cfi_offset 14, -4 + 312:./Src/hw_rtc.c **** } + 537 .loc 1 312 0 + 538 0002 0400 movs r4, r0 + 539 0004 0025 movs r5, #0 + 540 0006 C30E lsrs r3, r0, #27 + 541 0008 4201 lsls r2, r0, #5 + 542 000a 121B subs r2, r2, r4 + 543 000c AB41 sbcs r3, r3, r5 + 544 000e 960F lsrs r6, r2, #30 + 545 0010 9900 lsls r1, r3, #2 + 546 0012 3143 orrs r1, r6 + 547 0014 9000 lsls r0, r2, #2 + 548 .LVL45: + 549 0016 0019 adds r0, r0, r4 + 550 0018 6941 adcs r1, r1, r5 + 551 001a 4B06 lsls r3, r1, #25 + 552 001c C009 lsrs r0, r0, #7 + 553 001e 1843 orrs r0, r3 + 313:./Src/hw_rtc.c **** + 554 .loc 1 313 0 + 555 @ sp needed + 556 .LVL46: + 557 0020 70BD pop {r4, r5, r6, pc} + 558 .cfi_endproc + 559 .LFE102: + 561 .global __aeabi_idivmod + 562 .section .text.HW_RTC_SetAlarm,"ax",%progbits + 563 .align 1 + 564 .global HW_RTC_SetAlarm + 565 .syntax unified + 566 .code 16 + 567 .thumb_func + 568 .fpu softvfp + 570 HW_RTC_SetAlarm: + 571 .LFB103: + 321:./Src/hw_rtc.c **** /* we don't go in Low Power mode for timeout below MIN_ALARM_DELAY */ + 572 .loc 1 321 0 + 573 .cfi_startproc + 574 @ args = 0, pretend = 0, frame = 24 + 575 @ frame_needed = 0, uses_anonymous_args = 0 + 576 .LVL47: + 577 0000 F0B5 push {r4, r5, r6, r7, lr} + 578 .LCFI7: + ARM GAS /tmp/ccGAhXKe.s page 23 + + + 579 .cfi_def_cfa_offset 20 + 580 .cfi_offset 4, -20 + 581 .cfi_offset 5, -16 + 582 .cfi_offset 6, -12 + 583 .cfi_offset 7, -8 + 584 .cfi_offset 14, -4 + 585 0002 87B0 sub sp, sp, #28 + 586 .LCFI8: + 587 .cfi_def_cfa_offset 48 + 588 0004 0400 movs r4, r0 + 323:./Src/hw_rtc.c **** { + 589 .loc 1 323 0 + 590 0006 5D4B ldr r3, .L45 + 591 0008 0025 movs r5, #0 + 592 000a 5D5F ldrsh r5, [r3, r5] + 593 000c 0335 adds r5, r5, #3 + 594 .LBB38: + 595 .LBB39: + 351:./Src/hw_rtc.c **** + 596 .loc 1 351 0 + 597 000e 01A9 add r1, sp, #4 + 598 0010 6846 mov r0, sp + 599 .LVL48: + 600 0012 FFF7FEFF bl HW_RTC_GetCalendarValue + 601 .LVL49: + 353:./Src/hw_rtc.c **** } + 602 .loc 1 353 0 + 603 0016 5A4B ldr r3, .L45+4 + 604 0018 1B68 ldr r3, [r3] + 605 001a C01A subs r0, r0, r3 + 606 .LVL50: + 607 .LBE39: + 608 .LBE38: + 323:./Src/hw_rtc.c **** { + 609 .loc 1 323 0 + 610 001c 201A subs r0, r4, r0 + 611 001e 8542 cmp r5, r0 + 612 0020 28D2 bcs .L25 + 325:./Src/hw_rtc.c **** } + 613 .loc 1 325 0 + 614 0022 0120 movs r0, #1 + 615 0024 FFF7FEFF bl LowPower_Enable + 616 .LVL51: + 617 .L26: + 332:./Src/hw_rtc.c **** { + 618 .loc 1 332 0 + 619 0028 FFF7FEFF bl LowPower_GetState + 620 .LVL52: + 621 002c 0028 cmp r0, #0 + 622 002e 25D0 beq .L44 + 623 .L27: + 624 .LVL53: + 625 .LBB40: + 626 .LBB41: + 480:./Src/hw_rtc.c **** RTC_DateTypeDef RTC_DateStruct = RtcTimerContext.RTC_Calndr_Date; + 627 .loc 1 480 0 + 628 0030 01AD add r5, sp, #4 + ARM GAS /tmp/ccGAhXKe.s page 24 + + + 629 0032 5349 ldr r1, .L45+4 + 630 0034 2A00 movs r2, r5 + 631 0036 0B1D adds r3, r1, #4 + 632 0038 C1CB ldmia r3!, {r0, r6, r7} + 633 003a C1C2 stmia r2!, {r0, r6, r7} + 634 003c 41CB ldmia r3!, {r0, r6} + 635 003e 41C2 stmia r2!, {r0, r6} + 481:./Src/hw_rtc.c **** + 636 .loc 1 481 0 + 637 0040 8B69 ldr r3, [r1, #24] + 638 0042 0093 str r3, [sp] + 639 .LBB42: + 640 .LBB43: + 380:./Src/hw_rtc.c **** + 641 .loc 1 380 0 + 642 0044 4F48 ldr r0, .L45+8 + 643 0046 0168 ldr r1, [r0] + 644 0048 CA68 ldr r2, [r1, #12] + 645 004a FF23 movs r3, #255 + 646 004c 1A40 ands r2, r3 + 647 004e 4E4B ldr r3, .L45+12 + 648 0050 1343 orrs r3, r2 + 649 0052 CB60 str r3, [r1, #12] + 384:./Src/hw_rtc.c **** } + 650 .loc 1 384 0 + 651 0054 8021 movs r1, #128 + 652 0056 4900 lsls r1, r1, #1 + 653 0058 FFF7FEFF bl HAL_RTC_DeactivateAlarm + 654 .LVL54: + 655 .LBE43: + 656 .LBE42: + 487:./Src/hw_rtc.c **** rtcAlarmSubSeconds += ( timeoutValue & PREDIV_S); + 657 .loc 1 487 0 + 658 005c AB88 ldrh r3, [r5, #4] + 659 005e 4B4F ldr r7, .L45+16 + 660 0060 FF1A subs r7, r7, r3 + 661 0062 BFB2 uxth r7, r7 + 662 .LVL55: + 488:./Src/hw_rtc.c **** /* convert timeout to seconds */ + 663 .loc 1 488 0 + 664 0064 A305 lsls r3, r4, #22 + 665 0066 9B0D lsrs r3, r3, #22 + 666 0068 FF18 adds r7, r7, r3 + 667 .LVL56: + 668 006a BFB2 uxth r7, r7 + 669 .LVL57: + 490:./Src/hw_rtc.c **** + 670 .loc 1 490 0 + 671 006c A30A lsrs r3, r4, #10 + 672 .LVL58: + 493:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1DAY) + 673 .loc 1 493 0 + 674 006e 6A46 mov r2, sp + 675 0070 9078 ldrb r0, [r2, #2] + 676 .LVL59: + 677 0072 10E0 b .L28 + 678 .LVL60: + ARM GAS /tmp/ccGAhXKe.s page 25 + + + 679 .L25: + 680 .LBE41: + 681 .LBE40: + 329:./Src/hw_rtc.c **** } + 682 .loc 1 329 0 + 683 0074 0120 movs r0, #1 + 684 0076 FFF7FEFF bl LowPower_Disable + 685 .LVL61: + 686 007a D5E7 b .L26 + 687 .L44: + 334:./Src/hw_rtc.c **** timeout = timeout - McuWakeUpTimeCal; + 688 .loc 1 334 0 + 689 007c 0130 adds r0, r0, #1 + 690 007e FFF7FEFF bl LowPower_Enable + 691 .LVL62: + 335:./Src/hw_rtc.c **** } + 692 .loc 1 335 0 + 693 0082 3E4B ldr r3, .L45 + 694 0084 0022 movs r2, #0 + 695 0086 9B5E ldrsh r3, [r3, r2] + 696 0088 E41A subs r4, r4, r3 + 697 .LVL63: + 698 008a D1E7 b .L27 + 699 .LVL64: + 700 .L29: + 701 .LBB45: + 702 .LBB44: + 496:./Src/hw_rtc.c **** rtcAlarmDays++; + 703 .loc 1 496 0 + 704 008c 404A ldr r2, .L45+20 + 705 008e 9446 mov ip, r2 + 706 0090 6344 add r3, r3, ip + 707 .LVL65: + 497:./Src/hw_rtc.c **** } + 708 .loc 1 497 0 + 709 0092 0130 adds r0, r0, #1 + 710 .LVL66: + 711 0094 80B2 uxth r0, r0 + 712 .LVL67: + 713 .L28: + 494:./Src/hw_rtc.c **** { + 714 .loc 1 494 0 + 715 0096 3F4A ldr r2, .L45+24 + 716 0098 9342 cmp r3, r2 + 717 009a F7D8 bhi .L29 + 501:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1HOUR) + 718 .loc 1 501 0 + 719 009c 01AA add r2, sp, #4 + 720 009e 1478 ldrb r4, [r2] + 721 .LVL68: + 722 00a0 04E0 b .L30 + 723 .L31: + 504:./Src/hw_rtc.c **** rtcAlarmHours++; + 724 .loc 1 504 0 + 725 00a2 3D4A ldr r2, .L45+28 + 726 00a4 9446 mov ip, r2 + 727 00a6 6344 add r3, r3, ip + ARM GAS /tmp/ccGAhXKe.s page 26 + + + 728 .LVL69: + 505:./Src/hw_rtc.c **** } + 729 .loc 1 505 0 + 730 00a8 0134 adds r4, r4, #1 + 731 .LVL70: + 732 00aa A4B2 uxth r4, r4 + 733 .LVL71: + 734 .L30: + 502:./Src/hw_rtc.c **** { + 735 .loc 1 502 0 + 736 00ac 3B4A ldr r2, .L45+32 + 737 00ae 9342 cmp r3, r2 + 738 00b0 F7D8 bhi .L31 + 509:./Src/hw_rtc.c **** while (timeoutValue >= SECONDS_IN_1MINUTE) + 739 .loc 1 509 0 + 740 00b2 01AA add r2, sp, #4 + 741 00b4 5578 ldrb r5, [r2, #1] + 742 .LVL72: + 743 00b6 02E0 b .L32 + 744 .L33: + 512:./Src/hw_rtc.c **** rtcAlarmMinutes++; + 745 .loc 1 512 0 + 746 00b8 3C3B subs r3, r3, #60 + 747 .LVL73: + 513:./Src/hw_rtc.c **** } + 748 .loc 1 513 0 + 749 00ba 0135 adds r5, r5, #1 + 750 .LVL74: + 751 00bc ADB2 uxth r5, r5 + 752 .LVL75: + 753 .L32: + 510:./Src/hw_rtc.c **** { + 754 .loc 1 510 0 + 755 00be 3B2B cmp r3, #59 + 756 00c0 FAD8 bhi .L33 + 517:./Src/hw_rtc.c **** + 757 .loc 1 517 0 + 758 00c2 01AA add r2, sp, #4 + 759 00c4 9678 ldrb r6, [r2, #2] + 760 00c6 9BB2 uxth r3, r3 + 761 .LVL76: + 762 00c8 F618 adds r6, r6, r3 + 763 00ca B6B2 uxth r6, r6 + 764 .LVL77: + 765 00cc 05E0 b .L34 + 766 .L35: + 522:./Src/hw_rtc.c **** rtcAlarmSeconds++; + 767 .loc 1 522 0 + 768 00ce 344B ldr r3, .L45+36 + 769 00d0 9C46 mov ip, r3 + 770 00d2 6744 add r7, r7, ip + 771 .LVL78: + 772 00d4 BFB2 uxth r7, r7 + 773 .LVL79: + 523:./Src/hw_rtc.c **** } + 774 .loc 1 523 0 + 775 00d6 0136 adds r6, r6, #1 + ARM GAS /tmp/ccGAhXKe.s page 27 + + + 776 .LVL80: + 777 00d8 B6B2 uxth r6, r6 + 778 .LVL81: + 779 .L34: + 520:./Src/hw_rtc.c **** { + 780 .loc 1 520 0 + 781 00da 2C4B ldr r3, .L45+16 + 782 00dc 9F42 cmp r7, r3 + 783 00de F6D8 bhi .L35 + 784 00e0 03E0 b .L36 + 785 .L37: + 528:./Src/hw_rtc.c **** rtcAlarmMinutes++; + 786 .loc 1 528 0 + 787 00e2 3C3E subs r6, r6, #60 + 788 .LVL82: + 789 00e4 B6B2 uxth r6, r6 + 790 .LVL83: + 529:./Src/hw_rtc.c **** } + 791 .loc 1 529 0 + 792 00e6 0135 adds r5, r5, #1 + 793 .LVL84: + 794 00e8 ADB2 uxth r5, r5 + 795 .LVL85: + 796 .L36: + 526:./Src/hw_rtc.c **** { + 797 .loc 1 526 0 + 798 00ea 3B2E cmp r6, #59 + 799 00ec F9D8 bhi .L37 + 800 00ee 03E0 b .L38 + 801 .L39: + 534:./Src/hw_rtc.c **** rtcAlarmHours++; + 802 .loc 1 534 0 + 803 00f0 3C3D subs r5, r5, #60 + 804 .LVL86: + 805 00f2 ADB2 uxth r5, r5 + 806 .LVL87: + 535:./Src/hw_rtc.c **** } + 807 .loc 1 535 0 + 808 00f4 0134 adds r4, r4, #1 + 809 .LVL88: + 810 00f6 A4B2 uxth r4, r4 + 811 .LVL89: + 812 .L38: + 532:./Src/hw_rtc.c **** { + 813 .loc 1 532 0 + 814 00f8 3B2D cmp r5, #59 + 815 00fa F9D8 bhi .L39 + 816 00fc 03E0 b .L40 + 817 .L41: + 540:./Src/hw_rtc.c **** rtcAlarmDays++; + 818 .loc 1 540 0 + 819 00fe 183C subs r4, r4, #24 + 820 .LVL90: + 821 0100 A4B2 uxth r4, r4 + 822 .LVL91: + 541:./Src/hw_rtc.c **** } + 823 .loc 1 541 0 + ARM GAS /tmp/ccGAhXKe.s page 28 + + + 824 0102 0130 adds r0, r0, #1 + 825 .LVL92: + 826 0104 80B2 uxth r0, r0 + 827 .LVL93: + 828 .L40: + 538:./Src/hw_rtc.c **** { + 829 .loc 1 538 0 + 830 0106 172C cmp r4, #23 + 831 0108 F9D8 bhi .L41 + 544:./Src/hw_rtc.c **** { + 832 .loc 1 544 0 + 833 010a 6B46 mov r3, sp + 834 010c DB78 ldrb r3, [r3, #3] + 835 010e 9B07 lsls r3, r3, #30 + 836 0110 0BD1 bne .L42 + 546:./Src/hw_rtc.c **** { + 837 .loc 1 546 0 + 838 0112 6B46 mov r3, sp + 839 0114 5B78 ldrb r3, [r3, #1] + 840 0116 013B subs r3, r3, #1 + 841 0118 224A ldr r2, .L45+40 + 842 011a D15C ldrb r1, [r2, r3] + 843 011c 8BB2 uxth r3, r1 + 844 011e 9842 cmp r0, r3 + 845 0120 0ED9 bls .L43 + 548:./Src/hw_rtc.c **** } + 846 .loc 1 548 0 + 847 0122 FFF7FEFF bl __aeabi_idivmod + 848 .LVL94: + 849 0126 88B2 uxth r0, r1 + 850 .LVL95: + 851 0128 0AE0 b .L43 + 852 .L42: + 553:./Src/hw_rtc.c **** { + 853 .loc 1 553 0 + 854 012a 6B46 mov r3, sp + 855 012c 5B78 ldrb r3, [r3, #1] + 856 012e 013B subs r3, r3, #1 + 857 0130 1D4A ldr r2, .L45+44 + 858 0132 D15C ldrb r1, [r2, r3] + 859 0134 8BB2 uxth r3, r1 + 860 0136 9842 cmp r0, r3 + 861 0138 02D9 bls .L43 + 555:./Src/hw_rtc.c **** } + 862 .loc 1 555 0 + 863 013a FFF7FEFF bl __aeabi_idivmod + 864 .LVL96: + 865 013e 88B2 uxth r0, r1 + 866 .LVL97: + 867 .L43: + 560:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmSubSecondMask = HW_RTC_ALARMSUBSECONDMASK; + 868 .loc 1 560 0 + 869 0140 124B ldr r3, .L45+16 + 870 0142 DF1B subs r7, r3, r7 + 871 .LVL98: + 872 0144 1949 ldr r1, .L45+48 + 873 0146 4F60 str r7, [r1, #4] + ARM GAS /tmp/ccGAhXKe.s page 29 + + + 561:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Seconds = rtcAlarmSeconds; + 874 .loc 1 561 0 + 875 0148 A023 movs r3, #160 + 876 014a 1B05 lsls r3, r3, #20 + 877 014c 8B61 str r3, [r1, #24] + 562:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Minutes = rtcAlarmMinutes; + 878 .loc 1 562 0 + 879 014e 8E70 strb r6, [r1, #2] + 563:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.Hours = rtcAlarmHours; + 880 .loc 1 563 0 + 881 0150 4D70 strb r5, [r1, #1] + 564:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmDateWeekDay = ( uint8_t )rtcAlarmDays; + 882 .loc 1 564 0 + 883 0152 0C70 strb r4, [r1] + 565:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.TimeFormat = RTC_TimeStruct.TimeFormat; + 884 .loc 1 565 0 + 885 0154 2023 movs r3, #32 + 886 0156 C854 strb r0, [r1, r3] + 566:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE; + 887 .loc 1 566 0 + 888 0158 01AB add r3, sp, #4 + 889 015a DB78 ldrb r3, [r3, #3] + 890 015c CB70 strb r3, [r1, #3] + 567:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmMask = RTC_ALARMMASK_NONE; + 891 .loc 1 567 0 + 892 015e 0023 movs r3, #0 + 893 0160 CB61 str r3, [r1, #28] + 568:./Src/hw_rtc.c **** RTC_AlarmStructure.Alarm = RTC_ALARM_A; + 894 .loc 1 568 0 + 895 0162 4B61 str r3, [r1, #20] + 569:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 896 .loc 1 569 0 + 897 0164 8022 movs r2, #128 + 898 0166 5200 lsls r2, r2, #1 + 899 0168 4A62 str r2, [r1, #36] + 570:./Src/hw_rtc.c **** RTC_AlarmStructure.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + 900 .loc 1 570 0 + 901 016a CB60 str r3, [r1, #12] + 571:./Src/hw_rtc.c **** + 902 .loc 1 571 0 + 903 016c 0B61 str r3, [r1, #16] + 574:./Src/hw_rtc.c **** + 904 .loc 1 574 0 + 905 016e 0022 movs r2, #0 + 906 0170 0448 ldr r0, .L45+8 + 907 .LVL99: + 908 0172 FFF7FEFF bl HAL_RTC_SetAlarm_IT + 909 .LVL100: + 910 .LBE44: + 911 .LBE45: + 339:./Src/hw_rtc.c **** + 912 .loc 1 339 0 + 913 0176 07B0 add sp, sp, #28 + 914 @ sp needed + 915 0178 F0BD pop {r4, r5, r6, r7, pc} + 916 .L46: + 917 017a C046 .align 2 + ARM GAS /tmp/ccGAhXKe.s page 30 + + + 918 .L45: + 919 017c 00000000 .word .LANCHOR5 + 920 0180 00000000 .word .LANCHOR2 + 921 0184 00000000 .word .LANCHOR0 + 922 0188 7FFEFFFF .word -385 + 923 018c FF030000 .word 1023 + 924 0190 80AEFEFF .word -86400 + 925 0194 7F510100 .word 86399 + 926 0198 F0F1FFFF .word -3600 + 927 019c 0F0E0000 .word 3599 + 928 01a0 00FCFFFF .word -1024 + 929 01a4 00000000 .word .LANCHOR6 + 930 01a8 00000000 .word .LANCHOR7 + 931 01ac 00000000 .word .LANCHOR4 + 932 .cfi_endproc + 933 .LFE103: + 935 .section .text.HW_RTC_GetTimerElapsedTime,"ax",%progbits + 936 .align 1 + 937 .global HW_RTC_GetTimerElapsedTime + 938 .syntax unified + 939 .code 16 + 940 .thumb_func + 941 .fpu softvfp + 943 HW_RTC_GetTimerElapsedTime: + 944 .LFB104: + 347:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 945 .loc 1 347 0 + 946 .cfi_startproc + 947 @ args = 0, pretend = 0, frame = 24 + 948 @ frame_needed = 0, uses_anonymous_args = 0 + 949 0000 00B5 push {lr} + 950 .LCFI9: + 951 .cfi_def_cfa_offset 4 + 952 .cfi_offset 14, -4 + 953 0002 87B0 sub sp, sp, #28 + 954 .LCFI10: + 955 .cfi_def_cfa_offset 32 + 351:./Src/hw_rtc.c **** + 956 .loc 1 351 0 + 957 0004 01A9 add r1, sp, #4 + 958 0006 6846 mov r0, sp + 959 0008 FFF7FEFF bl HW_RTC_GetCalendarValue + 960 .LVL101: + 353:./Src/hw_rtc.c **** } + 961 .loc 1 353 0 + 962 000c 024B ldr r3, .L48 + 963 000e 1B68 ldr r3, [r3] + 964 0010 C01A subs r0, r0, r3 + 965 .LVL102: + 354:./Src/hw_rtc.c **** + 966 .loc 1 354 0 + 967 0012 07B0 add sp, sp, #28 + 968 @ sp needed + 969 0014 00BD pop {pc} + 970 .L49: + 971 0016 C046 .align 2 + 972 .L48: + ARM GAS /tmp/ccGAhXKe.s page 31 + + + 973 0018 00000000 .word .LANCHOR2 + 974 .cfi_endproc + 975 .LFE104: + 977 .section .text.HW_RTC_GetTimerValue,"ax",%progbits + 978 .align 1 + 979 .global HW_RTC_GetTimerValue + 980 .syntax unified + 981 .code 16 + 982 .thumb_func + 983 .fpu softvfp + 985 HW_RTC_GetTimerValue: + 986 .LFB105: + 362:./Src/hw_rtc.c **** RTC_TimeTypeDef RTC_TimeStruct; + 987 .loc 1 362 0 + 988 .cfi_startproc + 989 @ args = 0, pretend = 0, frame = 24 + 990 @ frame_needed = 0, uses_anonymous_args = 0 + 991 0000 00B5 push {lr} + 992 .LCFI11: + 993 .cfi_def_cfa_offset 4 + 994 .cfi_offset 14, -4 + 995 0002 87B0 sub sp, sp, #28 + 996 .LCFI12: + 997 .cfi_def_cfa_offset 32 + 366:./Src/hw_rtc.c **** + 998 .loc 1 366 0 + 999 0004 01A9 add r1, sp, #4 + 1000 0006 6846 mov r0, sp + 1001 0008 FFF7FEFF bl HW_RTC_GetCalendarValue + 1002 .LVL103: + 369:./Src/hw_rtc.c **** + 1003 .loc 1 369 0 + 1004 000c 07B0 add sp, sp, #28 + 1005 @ sp needed + 1006 000e 00BD pop {pc} + 1007 .cfi_endproc + 1008 .LFE105: + 1010 .section .text.HW_RTC_StopAlarm,"ax",%progbits + 1011 .align 1 + 1012 .global HW_RTC_StopAlarm + 1013 .syntax unified + 1014 .code 16 + 1015 .thumb_func + 1016 .fpu softvfp + 1018 HW_RTC_StopAlarm: + 1019 .LFB106: + 377:./Src/hw_rtc.c **** + 1020 .loc 1 377 0 + 1021 .cfi_startproc + 1022 @ args = 0, pretend = 0, frame = 0 + 1023 @ frame_needed = 0, uses_anonymous_args = 0 + 1024 0000 10B5 push {r4, lr} + 1025 .LCFI13: + 1026 .cfi_def_cfa_offset 8 + 1027 .cfi_offset 4, -8 + 1028 .cfi_offset 14, -4 + 380:./Src/hw_rtc.c **** + ARM GAS /tmp/ccGAhXKe.s page 32 + + + 1029 .loc 1 380 0 + 1030 0002 0648 ldr r0, .L52 + 1031 0004 0168 ldr r1, [r0] + 1032 0006 CA68 ldr r2, [r1, #12] + 1033 0008 FF23 movs r3, #255 + 1034 000a 1A40 ands r2, r3 + 1035 000c 044B ldr r3, .L52+4 + 1036 000e 1343 orrs r3, r2 + 1037 0010 CB60 str r3, [r1, #12] + 384:./Src/hw_rtc.c **** } + 1038 .loc 1 384 0 + 1039 0012 8021 movs r1, #128 + 1040 0014 4900 lsls r1, r1, #1 + 1041 0016 FFF7FEFF bl HAL_RTC_DeactivateAlarm + 1042 .LVL104: + 385:./Src/hw_rtc.c **** + 1043 .loc 1 385 0 + 1044 @ sp needed + 1045 001a 10BD pop {r4, pc} + 1046 .L53: + 1047 .align 2 + 1048 .L52: + 1049 001c 00000000 .word .LANCHOR0 + 1050 0020 7FFEFFFF .word -385 + 1051 .cfi_endproc + 1052 .LFE106: + 1054 .section .text.HW_RTC_IrqHandler,"ax",%progbits + 1055 .align 1 + 1056 .global HW_RTC_IrqHandler + 1057 .syntax unified + 1058 .code 16 + 1059 .thumb_func + 1060 .fpu softvfp + 1062 HW_RTC_IrqHandler: + 1063 .LFB107: + 393:./Src/hw_rtc.c **** RTC_HandleTypeDef* hrtc=&RtcHandle; + 1064 .loc 1 393 0 + 1065 .cfi_startproc + 1066 @ args = 0, pretend = 0, frame = 0 + 1067 @ frame_needed = 0, uses_anonymous_args = 0 + 1068 0000 10B5 push {r4, lr} + 1069 .LCFI14: + 1070 .cfi_def_cfa_offset 8 + 1071 .cfi_offset 4, -8 + 1072 .cfi_offset 14, -4 + 1073 .LVL105: + 396:./Src/hw_rtc.c **** + 1074 .loc 1 396 0 + 1075 0002 0120 movs r0, #1 + 1076 0004 FFF7FEFF bl LowPower_Enable + 1077 .LVL106: + 399:./Src/hw_rtc.c **** { + 1078 .loc 1 399 0 + 1079 0008 0B4B ldr r3, .L57 + 1080 000a 1B68 ldr r3, [r3] + 1081 000c 9A68 ldr r2, [r3, #8] + 1082 000e D204 lsls r2, r2, #19 + ARM GAS /tmp/ccGAhXKe.s page 33 + + + 1083 0010 02D5 bpl .L54 + 402:./Src/hw_rtc.c **** { + 1084 .loc 1 402 0 + 1085 0012 DA68 ldr r2, [r3, #12] + 1086 0014 D205 lsls r2, r2, #23 + 1087 0016 00D4 bmi .L56 + 1088 .L54: + 412:./Src/hw_rtc.c **** + 1089 .loc 1 412 0 + 1090 @ sp needed + 1091 0018 10BD pop {r4, pc} + 1092 .L56: + 405:./Src/hw_rtc.c **** /* Clear the EXTI's line Flag for RTC Alarm */ + 1093 .loc 1 405 0 + 1094 001a D968 ldr r1, [r3, #12] + 1095 001c FF22 movs r2, #255 + 1096 001e 1140 ands r1, r2 + 1097 0020 064A ldr r2, .L57+4 + 1098 0022 0A43 orrs r2, r1 + 1099 0024 DA60 str r2, [r3, #12] + 407:./Src/hw_rtc.c **** /* AlarmA callback */ + 1100 .loc 1 407 0 + 1101 0026 064B ldr r3, .L57+8 + 1102 0028 8022 movs r2, #128 + 1103 002a 9202 lsls r2, r2, #10 + 1104 002c 5A61 str r2, [r3, #20] + 409:./Src/hw_rtc.c **** } + 1105 .loc 1 409 0 + 1106 002e 0248 ldr r0, .L57 + 1107 0030 FFF7FEFF bl HAL_RTC_AlarmAEventCallback + 1108 .LVL107: + 412:./Src/hw_rtc.c **** + 1109 .loc 1 412 0 + 1110 0034 F0E7 b .L54 + 1111 .L58: + 1112 0036 C046 .align 2 + 1113 .L57: + 1114 0038 00000000 .word .LANCHOR0 + 1115 003c 7FFEFFFF .word -385 + 1116 0040 00040140 .word 1073808384 + 1117 .cfi_endproc + 1118 .LFE107: + 1120 .section .text.HW_RTC_DelayMs,"ax",%progbits + 1121 .align 1 + 1122 .global HW_RTC_DelayMs + 1123 .syntax unified + 1124 .code 16 + 1125 .thumb_func + 1126 .fpu softvfp + 1128 HW_RTC_DelayMs: + 1129 .LFB108: + 421:./Src/hw_rtc.c **** TimerTime_t delayValue = 0; + 1130 .loc 1 421 0 + 1131 .cfi_startproc + 1132 @ args = 0, pretend = 0, frame = 24 + 1133 @ frame_needed = 0, uses_anonymous_args = 0 + 1134 .LVL108: + ARM GAS /tmp/ccGAhXKe.s page 34 + + + 1135 0000 30B5 push {r4, r5, lr} + 1136 .LCFI15: + 1137 .cfi_def_cfa_offset 12 + 1138 .cfi_offset 4, -12 + 1139 .cfi_offset 5, -8 + 1140 .cfi_offset 14, -4 + 1141 0002 87B0 sub sp, sp, #28 + 1142 .LCFI16: + 1143 .cfi_def_cfa_offset 40 + 1144 .LVL109: + 1145 .LBB46: + 1146 .LBB47: + 301:./Src/hw_rtc.c **** } + 1147 .loc 1 301 0 + 1148 0004 410E lsrs r1, r0, #25 + 1149 0006 C001 lsls r0, r0, #7 + 1150 .LVL110: + 1151 0008 7D22 movs r2, #125 + 1152 000a 0023 movs r3, #0 + 1153 000c FFF7FEFF bl __aeabi_uldivmod + 1154 .LVL111: + 1155 0010 0400 movs r4, r0 + 1156 .LVL112: + 1157 .LBE47: + 1158 .LBE46: + 1159 .LBB48: + 1160 .LBB49: + 366:./Src/hw_rtc.c **** + 1161 .loc 1 366 0 + 1162 0012 01A9 add r1, sp, #4 + 1163 0014 6846 mov r0, sp + 1164 0016 FFF7FEFF bl HW_RTC_GetCalendarValue + 1165 .LVL113: + 1166 001a 0500 movs r5, r0 + 1167 .LVL114: + 1168 .LBE49: + 1169 .LBE48: + 429:./Src/hw_rtc.c **** { + 1170 .loc 1 429 0 + 1171 001c 00E0 b .L60 + 1172 .L61: + 1173 .LBB50: + 1174 .LBB51: + 1175 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + ARM GAS /tmp/ccGAhXKe.s page 35 + + + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccGAhXKe.s page 36 + + + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccGAhXKe.s page 37 + + + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + ARM GAS /tmp/ccGAhXKe.s page 38 + + + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccGAhXKe.s page 39 + + + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccGAhXKe.s page 40 + + + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */ + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0); + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + ARM GAS /tmp/ccGAhXKe.s page 41 + + + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop"); + 1176 .loc 2 375 0 + 1177 .syntax divided + 1178 @ 375 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1179 001e C046 nop + 1180 @ 0 "" 2 + 1181 .thumb + 1182 .syntax unified + 1183 .L60: + 1184 .LBE51: + 1185 .LBE50: + 1186 .LBB52: + 1187 .LBB53: + 366:./Src/hw_rtc.c **** + 1188 .loc 1 366 0 + 1189 0020 01A9 add r1, sp, #4 + 1190 0022 6846 mov r0, sp + 1191 0024 FFF7FEFF bl HW_RTC_GetCalendarValue + 1192 .LVL115: + 1193 .LBE53: + 1194 .LBE52: + 429:./Src/hw_rtc.c **** { + 1195 .loc 1 429 0 + 1196 0028 401B subs r0, r0, r5 + 1197 002a A042 cmp r0, r4 + 1198 002c F7D3 bcc .L61 + 433:./Src/hw_rtc.c **** + 1199 .loc 1 433 0 + 1200 002e 07B0 add sp, sp, #28 + 1201 @ sp needed + 1202 0030 30BD pop {r4, r5, pc} + 1203 .cfi_endproc + 1204 .LFE108: + 1206 .section .text.HW_RTC_SetTimerContext,"ax",%progbits + 1207 .align 1 + 1208 .global HW_RTC_SetTimerContext + 1209 .syntax unified + 1210 .code 16 + ARM GAS /tmp/ccGAhXKe.s page 42 + + + 1211 .thumb_func + 1212 .fpu softvfp + 1214 HW_RTC_SetTimerContext: + 1215 .LFB109: + 441:./Src/hw_rtc.c **** RtcTimerContext.Rtc_Time = HW_RTC_GetCalendarValue( &RtcTimerContext.RTC_Calndr_Date, &RtcTimerCo + 1216 .loc 1 441 0 + 1217 .cfi_startproc + 1218 @ args = 0, pretend = 0, frame = 0 + 1219 @ frame_needed = 0, uses_anonymous_args = 0 + 1220 0000 10B5 push {r4, lr} + 1221 .LCFI17: + 1222 .cfi_def_cfa_offset 8 + 1223 .cfi_offset 4, -8 + 1224 .cfi_offset 14, -4 + 442:./Src/hw_rtc.c **** return ( uint32_t ) RtcTimerContext.Rtc_Time; + 1225 .loc 1 442 0 + 1226 0002 044C ldr r4, .L63 + 1227 0004 211D adds r1, r4, #4 + 1228 0006 2000 movs r0, r4 + 1229 0008 1830 adds r0, r0, #24 + 1230 000a FFF7FEFF bl HW_RTC_GetCalendarValue + 1231 .LVL116: + 1232 000e 2060 str r0, [r4] + 444:./Src/hw_rtc.c **** + 1233 .loc 1 444 0 + 1234 @ sp needed + 1235 0010 10BD pop {r4, pc} + 1236 .L64: + 1237 0012 C046 .align 2 + 1238 .L63: + 1239 0014 00000000 .word .LANCHOR2 + 1240 .cfi_endproc + 1241 .LFE109: + 1243 .section .text.HW_RTC_GetTimerContext,"ax",%progbits + 1244 .align 1 + 1245 .global HW_RTC_GetTimerContext + 1246 .syntax unified + 1247 .code 16 + 1248 .thumb_func + 1249 .fpu softvfp + 1251 HW_RTC_GetTimerContext: + 1252 .LFB110: + 452:./Src/hw_rtc.c **** return (uint32_t) RtcTimerContext.Rtc_Time; + 1253 .loc 1 452 0 + 1254 .cfi_startproc + 1255 @ args = 0, pretend = 0, frame = 0 + 1256 @ frame_needed = 0, uses_anonymous_args = 0 + 1257 @ link register save eliminated. + 453:./Src/hw_rtc.c **** } + 1258 .loc 1 453 0 + 1259 0000 014B ldr r3, .L66 + 1260 0002 1868 ldr r0, [r3] + 454:./Src/hw_rtc.c **** /* Private functions ---------------------------------------------------------*/ + 1261 .loc 1 454 0 + 1262 @ sp needed + 1263 0004 7047 bx lr + 1264 .L67: + ARM GAS /tmp/ccGAhXKe.s page 43 + + + 1265 0006 C046 .align 2 + 1266 .L66: + 1267 0008 00000000 .word .LANCHOR2 + 1268 .cfi_endproc + 1269 .LFE110: + 1271 .section .bss.HW_RTC_Initalized,"aw",%nobits + 1272 .set .LANCHOR1,. + 0 + 1275 HW_RTC_Initalized: + 1276 0000 00 .space 1 + 1277 .section .bss.McuWakeUpTimeCal,"aw",%nobits + 1278 .align 1 + 1279 .set .LANCHOR5,. + 0 + 1282 McuWakeUpTimeCal: + 1283 0000 0000 .space 2 + 1284 .section .bss.McuWakeUpTimeInitialized,"aw",%nobits + 1285 .set .LANCHOR3,. + 0 + 1288 McuWakeUpTimeInitialized: + 1289 0000 00 .space 1 + 1290 .section .bss.RTC_AlarmStructure,"aw",%nobits + 1291 .align 2 + 1292 .set .LANCHOR4,. + 0 + 1295 RTC_AlarmStructure: + 1296 0000 00000000 .space 40 + 1296 00000000 + 1296 00000000 + 1296 00000000 + 1296 00000000 + 1297 .section .bss.RtcHandle,"aw",%nobits + 1298 .align 2 + 1299 .set .LANCHOR0,. + 0 + 1302 RtcHandle: + 1303 0000 00000000 .space 36 + 1303 00000000 + 1303 00000000 + 1303 00000000 + 1303 00000000 + 1304 .section .bss.RtcTimerContext,"aw",%nobits + 1305 .align 2 + 1306 .set .LANCHOR2,. + 0 + 1309 RtcTimerContext: + 1310 0000 00000000 .space 28 + 1310 00000000 + 1310 00000000 + 1310 00000000 + 1310 00000000 + 1311 .section .rodata.DaysInMonth,"a",%progbits + 1312 .align 2 + 1313 .set .LANCHOR7,. + 0 + 1316 DaysInMonth: + 1317 0000 1F .byte 31 + 1318 0001 1C .byte 28 + 1319 0002 1F .byte 31 + 1320 0003 1E .byte 30 + 1321 0004 1F .byte 31 + 1322 0005 1E .byte 30 + 1323 0006 1F .byte 31 + 1324 0007 1F .byte 31 + ARM GAS /tmp/ccGAhXKe.s page 44 + + + 1325 0008 1E .byte 30 + 1326 0009 1F .byte 31 + 1327 000a 1E .byte 30 + 1328 000b 1F .byte 31 + 1329 .section .rodata.DaysInMonthLeapYear,"a",%progbits + 1330 .align 2 + 1331 .set .LANCHOR6,. + 0 + 1334 DaysInMonthLeapYear: + 1335 0000 1F .byte 31 + 1336 0001 1D .byte 29 + 1337 0002 1F .byte 31 + 1338 0003 1E .byte 30 + 1339 0004 1F .byte 31 + 1340 0005 1E .byte 30 + 1341 0006 1F .byte 31 + 1342 0007 1F .byte 31 + 1343 0008 1E .byte 30 + 1344 0009 1F .byte 31 + 1345 000a 1E .byte 30 + 1346 000b 1F .byte 31 + 1347 .text + 1348 .Letext0: + 1349 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1350 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 1351 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 1352 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1353 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + 1354 .file 8 "/usr/arm-none-eabi/include/math.h" + 1355 .file 9 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1356 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1357 .file 11 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1358 .file 12 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1359 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 1360 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h" + 1361 .file 15 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 1362 .file 16 "Inc/hw_msp.h" + 1363 .file 17 "Middlewares/Third_Party/Lora/Utilities/low_power.h" + 1364 .file 18 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + 1365 .file 19 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h" + ARM GAS /tmp/ccGAhXKe.s page 45 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 hw_rtc.c + /tmp/ccGAhXKe.s:16 .text.HW_RTC_GetCalendarValue:0000000000000000 $t + /tmp/ccGAhXKe.s:22 .text.HW_RTC_GetCalendarValue:0000000000000000 HW_RTC_GetCalendarValue + /tmp/ccGAhXKe.s:158 .text.HW_RTC_GetCalendarValue:000000000000009c $d + /tmp/ccGAhXKe.s:167 .text.HW_RTC_Init:0000000000000000 $t + /tmp/ccGAhXKe.s:174 .text.HW_RTC_Init:0000000000000000 HW_RTC_Init + /tmp/ccGAhXKe.s:298 .text.HW_RTC_Init:0000000000000080 $d + /tmp/ccGAhXKe.s:307 .text.HW_RTC_setMcuWakeUpTime:0000000000000000 $t + /tmp/ccGAhXKe.s:314 .text.HW_RTC_setMcuWakeUpTime:0000000000000000 HW_RTC_setMcuWakeUpTime + /tmp/ccGAhXKe.s:421 .text.HW_RTC_setMcuWakeUpTime:0000000000000078 $d + /tmp/ccGAhXKe.s:430 .text.HW_RTC_getMcuWakeUpTime:0000000000000000 $t + /tmp/ccGAhXKe.s:437 .text.HW_RTC_getMcuWakeUpTime:0000000000000000 HW_RTC_getMcuWakeUpTime + /tmp/ccGAhXKe.s:454 .text.HW_RTC_getMcuWakeUpTime:0000000000000008 $d + /tmp/ccGAhXKe.s:459 .text.HW_RTC_GetMinimumTimeout:0000000000000000 $t + /tmp/ccGAhXKe.s:466 .text.HW_RTC_GetMinimumTimeout:0000000000000000 HW_RTC_GetMinimumTimeout + /tmp/ccGAhXKe.s:482 .text.HW_RTC_ms2Tick:0000000000000000 $t + /tmp/ccGAhXKe.s:489 .text.HW_RTC_ms2Tick:0000000000000000 HW_RTC_ms2Tick + /tmp/ccGAhXKe.s:516 .text.HW_RTC_Tick2ms:0000000000000000 $t + /tmp/ccGAhXKe.s:523 .text.HW_RTC_Tick2ms:0000000000000000 HW_RTC_Tick2ms + /tmp/ccGAhXKe.s:563 .text.HW_RTC_SetAlarm:0000000000000000 $t + /tmp/ccGAhXKe.s:570 .text.HW_RTC_SetAlarm:0000000000000000 HW_RTC_SetAlarm + /tmp/ccGAhXKe.s:919 .text.HW_RTC_SetAlarm:000000000000017c $d + /tmp/ccGAhXKe.s:936 .text.HW_RTC_GetTimerElapsedTime:0000000000000000 $t + /tmp/ccGAhXKe.s:943 .text.HW_RTC_GetTimerElapsedTime:0000000000000000 HW_RTC_GetTimerElapsedTime + /tmp/ccGAhXKe.s:973 .text.HW_RTC_GetTimerElapsedTime:0000000000000018 $d + /tmp/ccGAhXKe.s:978 .text.HW_RTC_GetTimerValue:0000000000000000 $t + /tmp/ccGAhXKe.s:985 .text.HW_RTC_GetTimerValue:0000000000000000 HW_RTC_GetTimerValue + /tmp/ccGAhXKe.s:1011 .text.HW_RTC_StopAlarm:0000000000000000 $t + /tmp/ccGAhXKe.s:1018 .text.HW_RTC_StopAlarm:0000000000000000 HW_RTC_StopAlarm + /tmp/ccGAhXKe.s:1049 .text.HW_RTC_StopAlarm:000000000000001c $d + /tmp/ccGAhXKe.s:1055 .text.HW_RTC_IrqHandler:0000000000000000 $t + /tmp/ccGAhXKe.s:1062 .text.HW_RTC_IrqHandler:0000000000000000 HW_RTC_IrqHandler + /tmp/ccGAhXKe.s:1114 .text.HW_RTC_IrqHandler:0000000000000038 $d + /tmp/ccGAhXKe.s:1121 .text.HW_RTC_DelayMs:0000000000000000 $t + /tmp/ccGAhXKe.s:1128 .text.HW_RTC_DelayMs:0000000000000000 HW_RTC_DelayMs + /tmp/ccGAhXKe.s:1207 .text.HW_RTC_SetTimerContext:0000000000000000 $t + /tmp/ccGAhXKe.s:1214 .text.HW_RTC_SetTimerContext:0000000000000000 HW_RTC_SetTimerContext + /tmp/ccGAhXKe.s:1239 .text.HW_RTC_SetTimerContext:0000000000000014 $d + /tmp/ccGAhXKe.s:1244 .text.HW_RTC_GetTimerContext:0000000000000000 $t + /tmp/ccGAhXKe.s:1251 .text.HW_RTC_GetTimerContext:0000000000000000 HW_RTC_GetTimerContext + /tmp/ccGAhXKe.s:1267 .text.HW_RTC_GetTimerContext:0000000000000008 $d + /tmp/ccGAhXKe.s:1275 .bss.HW_RTC_Initalized:0000000000000000 HW_RTC_Initalized + /tmp/ccGAhXKe.s:1276 .bss.HW_RTC_Initalized:0000000000000000 $d + /tmp/ccGAhXKe.s:1278 .bss.McuWakeUpTimeCal:0000000000000000 $d + /tmp/ccGAhXKe.s:1282 .bss.McuWakeUpTimeCal:0000000000000000 McuWakeUpTimeCal + /tmp/ccGAhXKe.s:1288 .bss.McuWakeUpTimeInitialized:0000000000000000 McuWakeUpTimeInitialized + /tmp/ccGAhXKe.s:1289 .bss.McuWakeUpTimeInitialized:0000000000000000 $d + /tmp/ccGAhXKe.s:1291 .bss.RTC_AlarmStructure:0000000000000000 $d + /tmp/ccGAhXKe.s:1295 .bss.RTC_AlarmStructure:0000000000000000 RTC_AlarmStructure + /tmp/ccGAhXKe.s:1298 .bss.RtcHandle:0000000000000000 $d + /tmp/ccGAhXKe.s:1302 .bss.RtcHandle:0000000000000000 RtcHandle + /tmp/ccGAhXKe.s:1305 .bss.RtcTimerContext:0000000000000000 $d + /tmp/ccGAhXKe.s:1309 .bss.RtcTimerContext:0000000000000000 RtcTimerContext + /tmp/ccGAhXKe.s:1312 .rodata.DaysInMonth:0000000000000000 $d + /tmp/ccGAhXKe.s:1316 .rodata.DaysInMonth:0000000000000000 DaysInMonth + /tmp/ccGAhXKe.s:1330 .rodata.DaysInMonthLeapYear:0000000000000000 $d + ARM GAS /tmp/ccGAhXKe.s page 46 + + + /tmp/ccGAhXKe.s:1334 .rodata.DaysInMonthLeapYear:0000000000000000 DaysInMonthLeapYear + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_RTC_GetTime +HAL_RTC_GetDate +HAL_RTC_Init +HAL_RTC_SetDate +HAL_RTC_SetTime +HAL_RTCEx_EnableBypassShadow +HAL_RTC_DeactivateAlarm +HAL_NVIC_GetPendingIRQ +HAL_RTC_GetAlarm +__aeabi_uldivmod +__aeabi_idivmod +LowPower_Enable +LowPower_GetState +LowPower_Disable +HAL_RTC_SetAlarm_IT +HAL_RTC_AlarmAEventCallback diff --git a/build/hw_spi.d b/build/hw_spi.d new file mode 100644 index 0000000..442210b --- /dev/null +++ b/build/hw_spi.d @@ -0,0 +1,135 @@ +build/hw_spi.d: Src/hw_spi.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: diff --git a/build/hw_spi.lst b/build/hw_spi.lst new file mode 100644 index 0000000..f09d0e7 --- /dev/null +++ b/build/hw_spi.lst @@ -0,0 +1,824 @@ +ARM GAS /tmp/cchlfLgp.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "hw_spi.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HW_SPI_IoInit,"ax",%progbits + 16 .align 1 + 17 .global HW_SPI_IoInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HW_SPI_IoInit: + 24 .LFB98: + 25 .file 1 "./Src/hw_spi.c" + 1:./Src/hw_spi.c **** /* + 2:./Src/hw_spi.c **** / _____) _ | | + 3:./Src/hw_spi.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/hw_spi.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/hw_spi.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/hw_spi.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/hw_spi.c **** (C)2013 Semtech + 8:./Src/hw_spi.c **** + 9:./Src/hw_spi.c **** Description: Bleeper board SPI driver implementation + 10:./Src/hw_spi.c **** + 11:./Src/hw_spi.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/hw_spi.c **** + 13:./Src/hw_spi.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Src/hw_spi.c **** */ + 15:./Src/hw_spi.c **** /******************************************************************************* + 16:./Src/hw_spi.c **** * @file hw_spi.c + 17:./Src/hw_spi.c **** * @author MCD Application Team + 18:./Src/hw_spi.c **** * @version V1.1.2 + 19:./Src/hw_spi.c **** * @date 08-September-2017 + 20:./Src/hw_spi.c **** * @brief manages the SPI interface + 21:./Src/hw_spi.c **** ****************************************************************************** + 22:./Src/hw_spi.c **** * @attention + 23:./Src/hw_spi.c **** * + 24:./Src/hw_spi.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/hw_spi.c **** * All rights reserved.

+ 26:./Src/hw_spi.c **** * + 27:./Src/hw_spi.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/hw_spi.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/hw_spi.c **** * + 30:./Src/hw_spi.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/hw_spi.c **** * this list of conditions and the following disclaimer. + 32:./Src/hw_spi.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/hw_spi.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/cchlfLgp.s page 2 + + + 34:./Src/hw_spi.c **** * and/or other materials provided with the distribution. + 35:./Src/hw_spi.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/hw_spi.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/hw_spi.c **** * derived from this software without specific written permission. + 38:./Src/hw_spi.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/hw_spi.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/hw_spi.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/hw_spi.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/hw_spi.c **** * this license is void and will automatically terminate your rights under + 43:./Src/hw_spi.c **** * this license. + 44:./Src/hw_spi.c **** * + 45:./Src/hw_spi.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/hw_spi.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/hw_spi.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/hw_spi.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/hw_spi.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/hw_spi.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/hw_spi.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/hw_spi.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/hw_spi.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/hw_spi.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/hw_spi.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/hw_spi.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/hw_spi.c **** * + 58:./Src/hw_spi.c **** ****************************************************************************** + 59:./Src/hw_spi.c **** */ + 60:./Src/hw_spi.c **** + 61:./Src/hw_spi.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Src/hw_spi.c **** #include "hw.h" + 63:./Src/hw_spi.c **** #include "utilities.h" + 64:./Src/hw_spi.c **** + 65:./Src/hw_spi.c **** + 66:./Src/hw_spi.c **** /* Private typedef -----------------------------------------------------------*/ + 67:./Src/hw_spi.c **** /* Private define ------------------------------------------------------------*/ + 68:./Src/hw_spi.c **** /* Private macro -------------------------------------------------------------*/ + 69:./Src/hw_spi.c **** /* Private variables ---------------------------------------------------------*/ + 70:./Src/hw_spi.c **** static SPI_HandleTypeDef hspi; + 71:./Src/hw_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 72:./Src/hw_spi.c **** + 73:./Src/hw_spi.c **** /*! + 74:./Src/hw_spi.c **** * @brief Calculates Spi Divisor based on Spi Frequency and Mcu Frequency + 75:./Src/hw_spi.c **** * + 76:./Src/hw_spi.c **** * @param [IN] Spi Frequency + 77:./Src/hw_spi.c **** * @retval Spi divisor + 78:./Src/hw_spi.c **** */ + 79:./Src/hw_spi.c **** static uint32_t SpiFrequency( uint32_t hz ); + 80:./Src/hw_spi.c **** + 81:./Src/hw_spi.c **** /* Exported functions ---------------------------------------------------------*/ + 82:./Src/hw_spi.c **** + 83:./Src/hw_spi.c **** /*! + 84:./Src/hw_spi.c **** * @brief Initializes the SPI object and MCU peripheral + 85:./Src/hw_spi.c **** * + 86:./Src/hw_spi.c **** * @param [IN] none + 87:./Src/hw_spi.c **** */ + 88:./Src/hw_spi.c **** void HW_SPI_Init( void ) + 89:./Src/hw_spi.c **** { + 90:./Src/hw_spi.c **** + ARM GAS /tmp/cchlfLgp.s page 3 + + + 91:./Src/hw_spi.c **** /*##-1- Configure the SPI peripheral */ + 92:./Src/hw_spi.c **** /* Set the SPI parameters */ + 93:./Src/hw_spi.c **** + 94:./Src/hw_spi.c **** hspi.Instance = SPI1; + 95:./Src/hw_spi.c **** + 96:./Src/hw_spi.c **** hspi.Init.BaudRatePrescaler = SpiFrequency( 10000000 ); + 97:./Src/hw_spi.c **** hspi.Init.Direction = SPI_DIRECTION_2LINES; + 98:./Src/hw_spi.c **** hspi.Init.Mode = SPI_MODE_MASTER; + 99:./Src/hw_spi.c **** hspi.Init.CLKPolarity = SPI_POLARITY_LOW; + 100:./Src/hw_spi.c **** hspi.Init.CLKPhase = SPI_PHASE_1EDGE; + 101:./Src/hw_spi.c **** hspi.Init.DataSize = SPI_DATASIZE_8BIT; + 102:./Src/hw_spi.c **** hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 103:./Src/hw_spi.c **** hspi.Init.FirstBit = SPI_FIRSTBIT_MSB; + 104:./Src/hw_spi.c **** hspi.Init.NSS = SPI_NSS_SOFT; + 105:./Src/hw_spi.c **** hspi.Init.TIMode = SPI_TIMODE_DISABLE; + 106:./Src/hw_spi.c **** + 107:./Src/hw_spi.c **** + 108:./Src/hw_spi.c **** SPI_CLK_ENABLE(); + 109:./Src/hw_spi.c **** + 110:./Src/hw_spi.c **** + 111:./Src/hw_spi.c **** if(HAL_SPI_Init( &hspi) != HAL_OK) + 112:./Src/hw_spi.c **** { + 113:./Src/hw_spi.c **** /* Initialization Error */ + 114:./Src/hw_spi.c **** Error_Handler(); + 115:./Src/hw_spi.c **** } + 116:./Src/hw_spi.c **** + 117:./Src/hw_spi.c **** /*##-2- Configure the SPI GPIOs */ + 118:./Src/hw_spi.c **** HW_SPI_IoInit( ); + 119:./Src/hw_spi.c **** } + 120:./Src/hw_spi.c **** + 121:./Src/hw_spi.c **** /*! + 122:./Src/hw_spi.c **** * @brief De-initializes the SPI object and MCU peripheral + 123:./Src/hw_spi.c **** * + 124:./Src/hw_spi.c **** * @param [IN] none + 125:./Src/hw_spi.c **** */ + 126:./Src/hw_spi.c **** void HW_SPI_DeInit( void ) + 127:./Src/hw_spi.c **** { + 128:./Src/hw_spi.c **** + 129:./Src/hw_spi.c **** HAL_SPI_DeInit( &hspi); + 130:./Src/hw_spi.c **** + 131:./Src/hw_spi.c **** /*##-1- Reset peripherals ####*/ + 132:./Src/hw_spi.c **** __HAL_RCC_SPI1_FORCE_RESET(); + 133:./Src/hw_spi.c **** __HAL_RCC_SPI1_RELEASE_RESET(); + 134:./Src/hw_spi.c **** /*##-2- Configure the SPI GPIOs */ + 135:./Src/hw_spi.c **** HW_SPI_IoDeInit( ); + 136:./Src/hw_spi.c **** } + 137:./Src/hw_spi.c **** + 138:./Src/hw_spi.c **** void HW_SPI_IoInit( void ) + 139:./Src/hw_spi.c **** { + 26 .loc 1 139 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 24 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 10B5 push {r4, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 4, -8 + ARM GAS /tmp/cchlfLgp.s page 4 + + + 34 .cfi_offset 14, -4 + 35 0002 86B0 sub sp, sp, #24 + 36 .LCFI1: + 37 .cfi_def_cfa_offset 32 + 140:./Src/hw_spi.c **** GPIO_InitTypeDef initStruct={0}; + 38 .loc 1 140 0 + 39 0004 1422 movs r2, #20 + 40 0006 0021 movs r1, #0 + 41 0008 01A8 add r0, sp, #4 + 42 000a FFF7FEFF bl memset + 43 .LVL0: + 141:./Src/hw_spi.c **** + 142:./Src/hw_spi.c **** + 143:./Src/hw_spi.c **** initStruct.Mode =GPIO_MODE_AF_PP; + 44 .loc 1 143 0 + 45 000e 0223 movs r3, #2 + 46 0010 0293 str r3, [sp, #8] + 144:./Src/hw_spi.c **** initStruct.Pull = GPIO_PULLDOWN; + 47 .loc 1 144 0 + 48 0012 0393 str r3, [sp, #12] + 145:./Src/hw_spi.c **** initStruct.Speed = GPIO_SPEED_HIGH; + 49 .loc 1 145 0 + 50 0014 0133 adds r3, r3, #1 + 51 0016 0493 str r3, [sp, #16] + 146:./Src/hw_spi.c **** initStruct.Alternate= SPI1_AF ; + 147:./Src/hw_spi.c **** + 148:./Src/hw_spi.c **** HW_GPIO_Init( RADIO_SCLK_PORT, RADIO_SCLK_PIN, &initStruct); + 52 .loc 1 148 0 + 53 0018 A024 movs r4, #160 + 54 001a E405 lsls r4, r4, #23 + 55 001c 01AA add r2, sp, #4 + 56 001e 2021 movs r1, #32 + 57 0020 2000 movs r0, r4 + 58 0022 FFF7FEFF bl HW_GPIO_Init + 59 .LVL1: + 149:./Src/hw_spi.c **** HW_GPIO_Init( RADIO_MISO_PORT, RADIO_MISO_PIN, &initStruct); + 60 .loc 1 149 0 + 61 0026 01AA add r2, sp, #4 + 62 0028 4021 movs r1, #64 + 63 002a 2000 movs r0, r4 + 64 002c FFF7FEFF bl HW_GPIO_Init + 65 .LVL2: + 150:./Src/hw_spi.c **** HW_GPIO_Init( RADIO_MOSI_PORT, RADIO_MOSI_PIN, &initStruct); + 66 .loc 1 150 0 + 67 0030 01AA add r2, sp, #4 + 68 0032 8021 movs r1, #128 + 69 0034 2000 movs r0, r4 + 70 0036 FFF7FEFF bl HW_GPIO_Init + 71 .LVL3: + 151:./Src/hw_spi.c **** + 152:./Src/hw_spi.c **** initStruct.Mode = GPIO_MODE_OUTPUT_PP; + 72 .loc 1 152 0 + 73 003a 0123 movs r3, #1 + 74 003c 0293 str r3, [sp, #8] + 153:./Src/hw_spi.c **** initStruct.Pull = GPIO_PULLUP; + 75 .loc 1 153 0 + 76 003e 0393 str r3, [sp, #12] + ARM GAS /tmp/cchlfLgp.s page 5 + + + 154:./Src/hw_spi.c **** + 155:./Src/hw_spi.c **** HW_GPIO_Init( RADIO_NSS_PORT, RADIO_NSS_PIN, &initStruct ); + 77 .loc 1 155 0 + 78 0040 064C ldr r4, .L2 + 79 0042 01AA add r2, sp, #4 + 80 0044 4021 movs r1, #64 + 81 0046 2000 movs r0, r4 + 82 0048 FFF7FEFF bl HW_GPIO_Init + 83 .LVL4: + 156:./Src/hw_spi.c **** + 157:./Src/hw_spi.c **** HW_GPIO_Write ( RADIO_NSS_PORT, RADIO_NSS_PIN, 1 ); + 84 .loc 1 157 0 + 85 004c 0122 movs r2, #1 + 86 004e 4021 movs r1, #64 + 87 0050 2000 movs r0, r4 + 88 0052 FFF7FEFF bl HW_GPIO_Write + 89 .LVL5: + 158:./Src/hw_spi.c **** } + 90 .loc 1 158 0 + 91 0056 06B0 add sp, sp, #24 + 92 @ sp needed + 93 0058 10BD pop {r4, pc} + 94 .L3: + 95 005a C046 .align 2 + 96 .L2: + 97 005c 00040050 .word 1342178304 + 98 .cfi_endproc + 99 .LFE98: + 101 .section .text.HW_SPI_Init,"ax",%progbits + 102 .align 1 + 103 .global HW_SPI_Init + 104 .syntax unified + 105 .code 16 + 106 .thumb_func + 107 .fpu softvfp + 109 HW_SPI_Init: + 110 .LFB96: + 89:./Src/hw_spi.c **** + 111 .loc 1 89 0 + 112 .cfi_startproc + 113 @ args = 0, pretend = 0, frame = 0 + 114 @ frame_needed = 0, uses_anonymous_args = 0 + 115 0000 10B5 push {r4, lr} + 116 .LCFI2: + 117 .cfi_def_cfa_offset 8 + 118 .cfi_offset 4, -8 + 119 .cfi_offset 14, -4 + 94:./Src/hw_spi.c **** + 120 .loc 1 94 0 + 121 0002 1F4B ldr r3, .L17 + 122 0004 1F4A ldr r2, .L17+4 + 123 0006 1A60 str r2, [r3] + 124 .LVL6: + 125 .LBB4: + 126 .LBB5: + 159:./Src/hw_spi.c **** + 160:./Src/hw_spi.c **** void HW_SPI_IoDeInit( void ) + ARM GAS /tmp/cchlfLgp.s page 6 + + + 161:./Src/hw_spi.c **** { + 162:./Src/hw_spi.c **** GPIO_InitTypeDef initStruct={0}; + 163:./Src/hw_spi.c **** + 164:./Src/hw_spi.c **** initStruct.Mode =GPIO_MODE_OUTPUT_PP; + 165:./Src/hw_spi.c **** + 166:./Src/hw_spi.c **** initStruct.Pull =GPIO_PULLDOWN ; + 167:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_MOSI_PORT, RADIO_MOSI_PIN, &initStruct ); + 168:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_MOSI_PORT, RADIO_MOSI_PIN, 0 ); + 169:./Src/hw_spi.c **** + 170:./Src/hw_spi.c **** initStruct.Pull =GPIO_PULLDOWN; + 171:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_MISO_PORT, RADIO_MISO_PIN, &initStruct ); + 172:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_MISO_PORT, RADIO_MISO_PIN, 0 ); + 173:./Src/hw_spi.c **** + 174:./Src/hw_spi.c **** initStruct.Pull =GPIO_PULLDOWN ; + 175:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_SCLK_PORT, RADIO_SCLK_PIN, &initStruct ); + 176:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_SCLK_PORT, RADIO_SCLK_PIN, 0 ); + 177:./Src/hw_spi.c **** + 178:./Src/hw_spi.c **** initStruct.Pull = GPIO_PULLUP; + 179:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_NSS_PORT, RADIO_NSS_PIN , &initStruct ); + 180:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN , 1 ); + 181:./Src/hw_spi.c **** } + 182:./Src/hw_spi.c **** + 183:./Src/hw_spi.c **** /*! + 184:./Src/hw_spi.c **** * @brief Sends outData and receives inData + 185:./Src/hw_spi.c **** * + 186:./Src/hw_spi.c **** * @param [IN] outData Byte to be sent + 187:./Src/hw_spi.c **** * @retval inData Received byte. + 188:./Src/hw_spi.c **** */ + 189:./Src/hw_spi.c **** uint16_t HW_SPI_InOut( uint16_t txData ) + 190:./Src/hw_spi.c **** { + 191:./Src/hw_spi.c **** uint16_t rxData ; + 192:./Src/hw_spi.c **** + 193:./Src/hw_spi.c **** HAL_SPI_TransmitReceive( &hspi, ( uint8_t * ) &txData, ( uint8_t* ) &rxData, 1, HAL_MAX_DELAY); + 194:./Src/hw_spi.c **** + 195:./Src/hw_spi.c **** return rxData; + 196:./Src/hw_spi.c **** } + 197:./Src/hw_spi.c **** + 198:./Src/hw_spi.c **** /* Private functions ---------------------------------------------------------*/ + 199:./Src/hw_spi.c **** + 200:./Src/hw_spi.c **** static uint32_t SpiFrequency( uint32_t hz ) + 201:./Src/hw_spi.c **** { + 202:./Src/hw_spi.c **** uint32_t divisor = 0; + 203:./Src/hw_spi.c **** uint32_t SysClkTmp = SystemCoreClock; + 127 .loc 1 203 0 + 128 0008 1F4B ldr r3, .L17+8 + 129 000a 1A68 ldr r2, [r3] + 130 .LVL7: + 202:./Src/hw_spi.c **** uint32_t SysClkTmp = SystemCoreClock; + 131 .loc 1 202 0 + 132 000c 0023 movs r3, #0 + 133 .LVL8: + 134 .L5: + 204:./Src/hw_spi.c **** uint32_t baudRate; + 205:./Src/hw_spi.c **** + 206:./Src/hw_spi.c **** while( SysClkTmp > hz) + 135 .loc 1 206 0 + 136 000e 1F49 ldr r1, .L17+12 + ARM GAS /tmp/cchlfLgp.s page 7 + + + 137 0010 8A42 cmp r2, r1 + 138 0012 03D9 bls .L6 + 207:./Src/hw_spi.c **** { + 208:./Src/hw_spi.c **** divisor++; + 139 .loc 1 208 0 + 140 0014 0133 adds r3, r3, #1 + 141 .LVL9: + 209:./Src/hw_spi.c **** SysClkTmp= ( SysClkTmp >> 1); + 142 .loc 1 209 0 + 143 0016 5208 lsrs r2, r2, #1 + 144 .LVL10: + 210:./Src/hw_spi.c **** + 211:./Src/hw_spi.c **** if (divisor >= 7) + 145 .loc 1 211 0 + 146 0018 062B cmp r3, #6 + 147 001a F8D9 bls .L5 + 148 .L6: + 212:./Src/hw_spi.c **** break; + 213:./Src/hw_spi.c **** } + 214:./Src/hw_spi.c **** + 215:./Src/hw_spi.c **** baudRate =((( divisor & 0x4 ) == 0 )? 0x0 : SPI_CR1_BR_2 )| + 149 .loc 1 215 0 + 150 001c 5A07 lsls r2, r3, #29 + 151 001e 24D4 bmi .L12 + 152 .LVL11: + 153 0020 0022 movs r2, #0 + 154 .L8: + 216:./Src/hw_spi.c **** ((( divisor & 0x2 ) == 0 )? 0x0 : SPI_CR1_BR_1 )| + 155 .loc 1 216 0 + 156 0022 9907 lsls r1, r3, #30 + 157 0024 23D4 bmi .L13 + 158 0026 0021 movs r1, #0 + 159 .L9: + 215:./Src/hw_spi.c **** ((( divisor & 0x2 ) == 0 )? 0x0 : SPI_CR1_BR_1 )| + 160 .loc 1 215 0 + 161 0028 0A43 orrs r2, r1 + 217:./Src/hw_spi.c **** ((( divisor & 0x1 ) == 0 )? 0x0 : SPI_CR1_BR_0 ); + 162 .loc 1 217 0 + 163 002a DB07 lsls r3, r3, #31 + 164 002c 21D5 bpl .L15 + 165 .LVL12: + 166 002e 0823 movs r3, #8 + 167 .L10: + 215:./Src/hw_spi.c **** ((( divisor & 0x2 ) == 0 )? 0x0 : SPI_CR1_BR_1 )| + 168 .loc 1 215 0 + 169 0030 1343 orrs r3, r2 + 170 .LVL13: + 171 .LBE5: + 172 .LBE4: + 96:./Src/hw_spi.c **** hspi.Init.Direction = SPI_DIRECTION_2LINES; + 173 .loc 1 96 0 + 174 0032 1348 ldr r0, .L17 + 175 0034 C361 str r3, [r0, #28] + 97:./Src/hw_spi.c **** hspi.Init.Mode = SPI_MODE_MASTER; + 176 .loc 1 97 0 + 177 0036 0023 movs r3, #0 + 178 0038 8360 str r3, [r0, #8] + ARM GAS /tmp/cchlfLgp.s page 8 + + + 98:./Src/hw_spi.c **** hspi.Init.CLKPolarity = SPI_POLARITY_LOW; + 179 .loc 1 98 0 + 180 003a 8222 movs r2, #130 + 181 003c 5200 lsls r2, r2, #1 + 182 003e 4260 str r2, [r0, #4] + 99:./Src/hw_spi.c **** hspi.Init.CLKPhase = SPI_PHASE_1EDGE; + 183 .loc 1 99 0 + 184 0040 0361 str r3, [r0, #16] + 100:./Src/hw_spi.c **** hspi.Init.DataSize = SPI_DATASIZE_8BIT; + 185 .loc 1 100 0 + 186 0042 4361 str r3, [r0, #20] + 101:./Src/hw_spi.c **** hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 187 .loc 1 101 0 + 188 0044 C360 str r3, [r0, #12] + 102:./Src/hw_spi.c **** hspi.Init.FirstBit = SPI_FIRSTBIT_MSB; + 189 .loc 1 102 0 + 190 0046 8362 str r3, [r0, #40] + 103:./Src/hw_spi.c **** hspi.Init.NSS = SPI_NSS_SOFT; + 191 .loc 1 103 0 + 192 0048 0362 str r3, [r0, #32] + 104:./Src/hw_spi.c **** hspi.Init.TIMode = SPI_TIMODE_DISABLE; + 193 .loc 1 104 0 + 194 004a FC32 adds r2, r2, #252 + 195 004c 8261 str r2, [r0, #24] + 105:./Src/hw_spi.c **** + 196 .loc 1 105 0 + 197 004e 4362 str r3, [r0, #36] + 108:./Src/hw_spi.c **** + 198 .loc 1 108 0 + 199 0050 0F4A ldr r2, .L17+16 + 200 0052 516B ldr r1, [r2, #52] + 201 0054 8023 movs r3, #128 + 202 0056 5B01 lsls r3, r3, #5 + 203 0058 0B43 orrs r3, r1 + 204 005a 5363 str r3, [r2, #52] + 111:./Src/hw_spi.c **** { + 205 .loc 1 111 0 + 206 005c FFF7FEFF bl HAL_SPI_Init + 207 .LVL14: + 208 0060 0028 cmp r0, #0 + 209 0062 08D1 bne .L16 + 210 .L11: + 118:./Src/hw_spi.c **** } + 211 .loc 1 118 0 + 212 0064 FFF7FEFF bl HW_SPI_IoInit + 213 .LVL15: + 119:./Src/hw_spi.c **** + 214 .loc 1 119 0 + 215 @ sp needed + 216 0068 10BD pop {r4, pc} + 217 .LVL16: + 218 .L12: + 219 .LBB7: + 220 .LBB6: + 215:./Src/hw_spi.c **** ((( divisor & 0x2 ) == 0 )? 0x0 : SPI_CR1_BR_1 )| + 221 .loc 1 215 0 + 222 006a 2022 movs r2, #32 + ARM GAS /tmp/cchlfLgp.s page 9 + + + 223 006c D9E7 b .L8 + 224 .L13: + 216:./Src/hw_spi.c **** ((( divisor & 0x1 ) == 0 )? 0x0 : SPI_CR1_BR_0 ); + 225 .loc 1 216 0 + 226 006e 1021 movs r1, #16 + 227 0070 DAE7 b .L9 + 228 .LVL17: + 229 .L15: + 230 .loc 1 217 0 + 231 0072 0023 movs r3, #0 + 232 0074 DCE7 b .L10 + 233 .LVL18: + 234 .L16: + 235 .LBE6: + 236 .LBE7: + 114:./Src/hw_spi.c **** } + 237 .loc 1 114 0 + 238 0076 7221 movs r1, #114 + 239 0078 0648 ldr r0, .L17+20 + 240 007a FFF7FEFF bl _Error_Handler + 241 .LVL19: + 242 007e F1E7 b .L11 + 243 .L18: + 244 .align 2 + 245 .L17: + 246 0080 00000000 .word .LANCHOR0 + 247 0084 00300140 .word 1073819648 + 248 0088 00000000 .word SystemCoreClock + 249 008c 80969800 .word 10000000 + 250 0090 00100240 .word 1073876992 + 251 0094 00000000 .word .LC2 + 252 .cfi_endproc + 253 .LFE96: + 255 .section .text.HW_SPI_IoDeInit,"ax",%progbits + 256 .align 1 + 257 .global HW_SPI_IoDeInit + 258 .syntax unified + 259 .code 16 + 260 .thumb_func + 261 .fpu softvfp + 263 HW_SPI_IoDeInit: + 264 .LFB99: + 161:./Src/hw_spi.c **** GPIO_InitTypeDef initStruct={0}; + 265 .loc 1 161 0 + 266 .cfi_startproc + 267 @ args = 0, pretend = 0, frame = 24 + 268 @ frame_needed = 0, uses_anonymous_args = 0 + 269 0000 70B5 push {r4, r5, r6, lr} + 270 .LCFI3: + 271 .cfi_def_cfa_offset 16 + 272 .cfi_offset 4, -16 + 273 .cfi_offset 5, -12 + 274 .cfi_offset 6, -8 + 275 .cfi_offset 14, -4 + 276 0002 86B0 sub sp, sp, #24 + 277 .LCFI4: + 278 .cfi_def_cfa_offset 40 + ARM GAS /tmp/cchlfLgp.s page 10 + + + 162:./Src/hw_spi.c **** + 279 .loc 1 162 0 + 280 0004 1422 movs r2, #20 + 281 0006 0021 movs r1, #0 + 282 0008 01A8 add r0, sp, #4 + 283 000a FFF7FEFF bl memset + 284 .LVL20: + 164:./Src/hw_spi.c **** + 285 .loc 1 164 0 + 286 000e 0126 movs r6, #1 + 287 0010 0296 str r6, [sp, #8] + 166:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_MOSI_PORT, RADIO_MOSI_PIN, &initStruct ); + 288 .loc 1 166 0 + 289 0012 0225 movs r5, #2 + 290 0014 0395 str r5, [sp, #12] + 167:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_MOSI_PORT, RADIO_MOSI_PIN, 0 ); + 291 .loc 1 167 0 + 292 0016 A024 movs r4, #160 + 293 0018 E405 lsls r4, r4, #23 + 294 001a 01AA add r2, sp, #4 + 295 001c 8021 movs r1, #128 + 296 001e 2000 movs r0, r4 + 297 0020 FFF7FEFF bl HW_GPIO_Init + 298 .LVL21: + 168:./Src/hw_spi.c **** + 299 .loc 1 168 0 + 300 0024 0022 movs r2, #0 + 301 0026 8021 movs r1, #128 + 302 0028 2000 movs r0, r4 + 303 002a FFF7FEFF bl HW_GPIO_Write + 304 .LVL22: + 170:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_MISO_PORT, RADIO_MISO_PIN, &initStruct ); + 305 .loc 1 170 0 + 306 002e 0395 str r5, [sp, #12] + 171:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_MISO_PORT, RADIO_MISO_PIN, 0 ); + 307 .loc 1 171 0 + 308 0030 01AA add r2, sp, #4 + 309 0032 4021 movs r1, #64 + 310 0034 2000 movs r0, r4 + 311 0036 FFF7FEFF bl HW_GPIO_Init + 312 .LVL23: + 172:./Src/hw_spi.c **** + 313 .loc 1 172 0 + 314 003a 0022 movs r2, #0 + 315 003c 4021 movs r1, #64 + 316 003e 2000 movs r0, r4 + 317 0040 FFF7FEFF bl HW_GPIO_Write + 318 .LVL24: + 174:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_SCLK_PORT, RADIO_SCLK_PIN, &initStruct ); + 319 .loc 1 174 0 + 320 0044 0395 str r5, [sp, #12] + 175:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_SCLK_PORT, RADIO_SCLK_PIN, 0 ); + 321 .loc 1 175 0 + 322 0046 01AA add r2, sp, #4 + 323 0048 2021 movs r1, #32 + 324 004a 2000 movs r0, r4 + 325 004c FFF7FEFF bl HW_GPIO_Init + ARM GAS /tmp/cchlfLgp.s page 11 + + + 326 .LVL25: + 176:./Src/hw_spi.c **** + 327 .loc 1 176 0 + 328 0050 0022 movs r2, #0 + 329 0052 2021 movs r1, #32 + 330 0054 2000 movs r0, r4 + 331 0056 FFF7FEFF bl HW_GPIO_Write + 332 .LVL26: + 178:./Src/hw_spi.c **** HW_GPIO_Init ( RADIO_NSS_PORT, RADIO_NSS_PIN , &initStruct ); + 333 .loc 1 178 0 + 334 005a 0396 str r6, [sp, #12] + 179:./Src/hw_spi.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN , 1 ); + 335 .loc 1 179 0 + 336 005c 064C ldr r4, .L20 + 337 005e 01AA add r2, sp, #4 + 338 0060 4021 movs r1, #64 + 339 0062 2000 movs r0, r4 + 340 0064 FFF7FEFF bl HW_GPIO_Init + 341 .LVL27: + 180:./Src/hw_spi.c **** } + 342 .loc 1 180 0 + 343 0068 0122 movs r2, #1 + 344 006a 4021 movs r1, #64 + 345 006c 2000 movs r0, r4 + 346 006e FFF7FEFF bl HW_GPIO_Write + 347 .LVL28: + 181:./Src/hw_spi.c **** + 348 .loc 1 181 0 + 349 0072 06B0 add sp, sp, #24 + 350 @ sp needed + 351 0074 70BD pop {r4, r5, r6, pc} + 352 .L21: + 353 0076 C046 .align 2 + 354 .L20: + 355 0078 00040050 .word 1342178304 + 356 .cfi_endproc + 357 .LFE99: + 359 .section .text.HW_SPI_DeInit,"ax",%progbits + 360 .align 1 + 361 .global HW_SPI_DeInit + 362 .syntax unified + 363 .code 16 + 364 .thumb_func + 365 .fpu softvfp + 367 HW_SPI_DeInit: + 368 .LFB97: + 127:./Src/hw_spi.c **** + 369 .loc 1 127 0 + 370 .cfi_startproc + 371 @ args = 0, pretend = 0, frame = 0 + 372 @ frame_needed = 0, uses_anonymous_args = 0 + 373 0000 10B5 push {r4, lr} + 374 .LCFI5: + 375 .cfi_def_cfa_offset 8 + 376 .cfi_offset 4, -8 + 377 .cfi_offset 14, -4 + 129:./Src/hw_spi.c **** + ARM GAS /tmp/cchlfLgp.s page 12 + + + 378 .loc 1 129 0 + 379 0002 0848 ldr r0, .L23 + 380 0004 FFF7FEFF bl HAL_SPI_DeInit + 381 .LVL29: + 132:./Src/hw_spi.c **** __HAL_RCC_SPI1_RELEASE_RESET(); + 382 .loc 1 132 0 + 383 0008 074B ldr r3, .L23+4 + 384 000a 596A ldr r1, [r3, #36] + 385 000c 8022 movs r2, #128 + 386 000e 5201 lsls r2, r2, #5 + 387 0010 0A43 orrs r2, r1 + 388 0012 5A62 str r2, [r3, #36] + 133:./Src/hw_spi.c **** /*##-2- Configure the SPI GPIOs */ + 389 .loc 1 133 0 + 390 0014 5A6A ldr r2, [r3, #36] + 391 0016 0549 ldr r1, .L23+8 + 392 0018 0A40 ands r2, r1 + 393 001a 5A62 str r2, [r3, #36] + 135:./Src/hw_spi.c **** } + 394 .loc 1 135 0 + 395 001c FFF7FEFF bl HW_SPI_IoDeInit + 396 .LVL30: + 136:./Src/hw_spi.c **** + 397 .loc 1 136 0 + 398 @ sp needed + 399 0020 10BD pop {r4, pc} + 400 .L24: + 401 0022 C046 .align 2 + 402 .L23: + 403 0024 00000000 .word .LANCHOR0 + 404 0028 00100240 .word 1073876992 + 405 002c FFEFFFFF .word -4097 + 406 .cfi_endproc + 407 .LFE97: + 409 .section .text.HW_SPI_InOut,"ax",%progbits + 410 .align 1 + 411 .global HW_SPI_InOut + 412 .syntax unified + 413 .code 16 + 414 .thumb_func + 415 .fpu softvfp + 417 HW_SPI_InOut: + 418 .LFB100: + 190:./Src/hw_spi.c **** uint16_t rxData ; + 419 .loc 1 190 0 + 420 .cfi_startproc + 421 @ args = 0, pretend = 0, frame = 16 + 422 @ frame_needed = 0, uses_anonymous_args = 0 + 423 .LVL31: + 424 0000 10B5 push {r4, lr} + 425 .LCFI6: + 426 .cfi_def_cfa_offset 8 + 427 .cfi_offset 4, -8 + 428 .cfi_offset 14, -4 + 429 0002 86B0 sub sp, sp, #24 + 430 .LCFI7: + 431 .cfi_def_cfa_offset 32 + ARM GAS /tmp/cchlfLgp.s page 13 + + + 432 0004 0E21 movs r1, #14 + 433 0006 6944 add r1, r1, sp + 434 0008 0880 strh r0, [r1] + 193:./Src/hw_spi.c **** + 435 .loc 1 193 0 + 436 000a 1624 movs r4, #22 + 437 000c 6C44 add r4, r4, sp + 438 000e 0123 movs r3, #1 + 439 0010 5B42 rsbs r3, r3, #0 + 440 0012 0093 str r3, [sp] + 441 0014 0233 adds r3, r3, #2 + 442 0016 2200 movs r2, r4 + 443 0018 0248 ldr r0, .L26 + 444 .LVL32: + 445 001a FFF7FEFF bl HAL_SPI_TransmitReceive + 446 .LVL33: + 195:./Src/hw_spi.c **** } + 447 .loc 1 195 0 + 448 001e 2088 ldrh r0, [r4] + 196:./Src/hw_spi.c **** + 449 .loc 1 196 0 + 450 0020 06B0 add sp, sp, #24 + 451 @ sp needed + 452 0022 10BD pop {r4, pc} + 453 .L27: + 454 .align 2 + 455 .L26: + 456 0024 00000000 .word .LANCHOR0 + 457 .cfi_endproc + 458 .LFE100: + 460 .section .bss.hspi,"aw",%nobits + 461 .align 2 + 462 .set .LANCHOR0,. + 0 + 465 hspi: + 466 0000 00000000 .space 88 + 466 00000000 + 466 00000000 + 466 00000000 + 466 00000000 + 467 .section .rodata.HW_SPI_Init.str1.4,"aMS",%progbits,1 + 468 .align 2 + 469 .LC2: + 470 0000 2E2F5372 .ascii "./Src/hw_spi.c\000" + 470 632F6877 + 470 5F737069 + 470 2E6300 + 471 .text + 472 .Letext0: + 473 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 474 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 475 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 476 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 477 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 478 .file 7 "/usr/arm-none-eabi/include/math.h" + 479 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 480 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 481 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + ARM GAS /tmp/cchlfLgp.s page 14 + + + 482 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 483 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 484 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 485 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h" + 486 .file 15 "Inc/hw_gpio.h" + 487 .file 16 "Inc/debug.h" + 488 .file 17 "" + ARM GAS /tmp/cchlfLgp.s page 15 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 hw_spi.c + /tmp/cchlfLgp.s:16 .text.HW_SPI_IoInit:0000000000000000 $t + /tmp/cchlfLgp.s:23 .text.HW_SPI_IoInit:0000000000000000 HW_SPI_IoInit + /tmp/cchlfLgp.s:97 .text.HW_SPI_IoInit:000000000000005c $d + /tmp/cchlfLgp.s:102 .text.HW_SPI_Init:0000000000000000 $t + /tmp/cchlfLgp.s:109 .text.HW_SPI_Init:0000000000000000 HW_SPI_Init + /tmp/cchlfLgp.s:246 .text.HW_SPI_Init:0000000000000080 $d + /tmp/cchlfLgp.s:256 .text.HW_SPI_IoDeInit:0000000000000000 $t + /tmp/cchlfLgp.s:263 .text.HW_SPI_IoDeInit:0000000000000000 HW_SPI_IoDeInit + /tmp/cchlfLgp.s:355 .text.HW_SPI_IoDeInit:0000000000000078 $d + /tmp/cchlfLgp.s:360 .text.HW_SPI_DeInit:0000000000000000 $t + /tmp/cchlfLgp.s:367 .text.HW_SPI_DeInit:0000000000000000 HW_SPI_DeInit + /tmp/cchlfLgp.s:403 .text.HW_SPI_DeInit:0000000000000024 $d + /tmp/cchlfLgp.s:410 .text.HW_SPI_InOut:0000000000000000 $t + /tmp/cchlfLgp.s:417 .text.HW_SPI_InOut:0000000000000000 HW_SPI_InOut + /tmp/cchlfLgp.s:456 .text.HW_SPI_InOut:0000000000000024 $d + /tmp/cchlfLgp.s:461 .bss.hspi:0000000000000000 $d + /tmp/cchlfLgp.s:465 .bss.hspi:0000000000000000 hspi + /tmp/cchlfLgp.s:468 .rodata.HW_SPI_Init.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +memset +HW_GPIO_Init +HW_GPIO_Write +HAL_SPI_Init +_Error_Handler +SystemCoreClock +HAL_SPI_DeInit +HAL_SPI_TransmitReceive diff --git a/build/lora.d b/build/lora.d new file mode 100644 index 0000000..ab2294f --- /dev/null +++ b/build/lora.d @@ -0,0 +1,155 @@ +build/lora.d: Middlewares/Third_Party/Lora/Core/lora.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Core/lora.h Inc/Commissioning.h \ + Middlewares/Third_Party/Lora/Mac/region/Region.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Core/lora.h: + +Inc/Commissioning.h: + +Middlewares/Third_Party/Lora/Mac/region/Region.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h: diff --git a/build/lora.lst b/build/lora.lst new file mode 100644 index 0000000..da4f5ad --- /dev/null +++ b/build/lora.lst @@ -0,0 +1,2559 @@ +ARM GAS /tmp/ccY05lmV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "lora.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.McpsConfirm,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 McpsConfirm: + 23 .LFB100: + 24 .file 1 "./Middlewares/Third_Party/Lora/Core/lora.c" + 1:./Middlewares/Third_Party/Lora/Core/lora.c **** /* + 2:./Middlewares/Third_Party/Lora/Core/lora.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Core/lora.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Core/lora.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Core/lora.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Core/lora.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Core/lora.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Core/lora.c **** + 9:./Middlewares/Third_Party/Lora/Core/lora.c **** Description: LoRaMac classA device implementation + 10:./Middlewares/Third_Party/Lora/Core/lora.c **** + 11:./Middlewares/Third_Party/Lora/Core/lora.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Middlewares/Third_Party/Lora/Core/lora.c **** + 13:./Middlewares/Third_Party/Lora/Core/lora.c **** Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene + 14:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 15:./Middlewares/Third_Party/Lora/Core/lora.c **** /****************************************************************************** + 16:./Middlewares/Third_Party/Lora/Core/lora.c **** * @file lora.c + 17:./Middlewares/Third_Party/Lora/Core/lora.c **** * @author MCD Application Team + 18:./Middlewares/Third_Party/Lora/Core/lora.c **** * @version V1.1.2 + 19:./Middlewares/Third_Party/Lora/Core/lora.c **** * @date 08-September-2017 + 20:./Middlewares/Third_Party/Lora/Core/lora.c **** * @brief lora API to drive the lora state Machine + 21:./Middlewares/Third_Party/Lora/Core/lora.c **** ****************************************************************************** + 22:./Middlewares/Third_Party/Lora/Core/lora.c **** * @attention + 23:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 24:./Middlewares/Third_Party/Lora/Core/lora.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Middlewares/Third_Party/Lora/Core/lora.c **** * All rights reserved.

+ 26:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 27:./Middlewares/Third_Party/Lora/Core/lora.c **** * Redistribution and use in source and binary forms, with or without + 28:./Middlewares/Third_Party/Lora/Core/lora.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 30:./Middlewares/Third_Party/Lora/Core/lora.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Middlewares/Third_Party/Lora/Core/lora.c **** * this list of conditions and the following disclaimer. + 32:./Middlewares/Third_Party/Lora/Core/lora.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Middlewares/Third_Party/Lora/Core/lora.c **** * this list of conditions and the following disclaimer in the documentation + 34:./Middlewares/Third_Party/Lora/Core/lora.c **** * and/or other materials provided with the distribution. + ARM GAS /tmp/ccY05lmV.s page 2 + + + 35:./Middlewares/Third_Party/Lora/Core/lora.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Middlewares/Third_Party/Lora/Core/lora.c **** * contributors to this software may be used to endorse or promote products + 37:./Middlewares/Third_Party/Lora/Core/lora.c **** * derived from this software without specific written permission. + 38:./Middlewares/Third_Party/Lora/Core/lora.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Middlewares/Third_Party/Lora/Core/lora.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Middlewares/Third_Party/Lora/Core/lora.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Middlewares/Third_Party/Lora/Core/lora.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Middlewares/Third_Party/Lora/Core/lora.c **** * this license is void and will automatically terminate your rights under + 43:./Middlewares/Third_Party/Lora/Core/lora.c **** * this license. + 44:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 45:./Middlewares/Third_Party/Lora/Core/lora.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Middlewares/Third_Party/Lora/Core/lora.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Middlewares/Third_Party/Lora/Core/lora.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Middlewares/Third_Party/Lora/Core/lora.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Middlewares/Third_Party/Lora/Core/lora.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Middlewares/Third_Party/Lora/Core/lora.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Middlewares/Third_Party/Lora/Core/lora.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Middlewares/Third_Party/Lora/Core/lora.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Middlewares/Third_Party/Lora/Core/lora.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Middlewares/Third_Party/Lora/Core/lora.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Middlewares/Third_Party/Lora/Core/lora.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Middlewares/Third_Party/Lora/Core/lora.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 58:./Middlewares/Third_Party/Lora/Core/lora.c **** ****************************************************************************** + 59:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 60:./Middlewares/Third_Party/Lora/Core/lora.c **** + 61:./Middlewares/Third_Party/Lora/Core/lora.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Middlewares/Third_Party/Lora/Core/lora.c **** #include "hw.h" + 63:./Middlewares/Third_Party/Lora/Core/lora.c **** #include "timeServer.h" + 64:./Middlewares/Third_Party/Lora/Core/lora.c **** #include "LoRaMac.h" + 65:./Middlewares/Third_Party/Lora/Core/lora.c **** #include "lora.h" + 66:./Middlewares/Third_Party/Lora/Core/lora.c **** + 67:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 68:./Middlewares/Third_Party/Lora/Core/lora.c **** * Join requests trials duty cycle. + 69:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 70:./Middlewares/Third_Party/Lora/Core/lora.c **** #define OVER_THE_AIR_ACTIVATION_DUTYCYCLE 10000 // 10 [s] value in ms + 71:./Middlewares/Third_Party/Lora/Core/lora.c **** + 72:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_EU868 ) + 73:./Middlewares/Third_Party/Lora/Core/lora.c **** + 74:./Middlewares/Third_Party/Lora/Core/lora.c **** #include "LoRaMacTest.h" + 75:./Middlewares/Third_Party/Lora/Core/lora.c **** + 76:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 77:./Middlewares/Third_Party/Lora/Core/lora.c **** * LoRaWAN ETSI duty cycle control enable/disable + 78:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 79:./Middlewares/Third_Party/Lora/Core/lora.c **** * \remark Please note that ETSI mandates duty cycled transmissions. Use only for test purposes + 80:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 81:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LORAWAN_DUTYCYCLE_ON true + 82:./Middlewares/Third_Party/Lora/Core/lora.c **** + 83:./Middlewares/Third_Party/Lora/Core/lora.c **** #define USE_SEMTECH_DEFAULT_CHANNEL_LINEUP 0 + 84:./Middlewares/Third_Party/Lora/Core/lora.c **** + 85:./Middlewares/Third_Party/Lora/Core/lora.c **** #if( USE_SEMTECH_DEFAULT_CHANNEL_LINEUP == 1 ) + 86:./Middlewares/Third_Party/Lora/Core/lora.c **** + 87:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC4 { 867100000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + 88:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC5 { 867300000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + 89:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC6 { 867500000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + 90:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC7 { 867700000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + 91:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC8 { 867900000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + ARM GAS /tmp/ccY05lmV.s page 3 + + + 92:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC9 { 868800000, 0, { ( ( DR_7 << 4 ) | DR_7 ) }, 2 } + 93:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LC10 { 868300000, 0, { ( ( DR_6 << 4 ) | DR_6 ) }, 1 } + 94:./Middlewares/Third_Party/Lora/Core/lora.c **** + 95:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 96:./Middlewares/Third_Party/Lora/Core/lora.c **** + 97:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 98:./Middlewares/Third_Party/Lora/Core/lora.c **** + 99:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t DevEui[] = LORAWAN_DEVICE_EUI; + 100:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t AppEui[] = LORAWAN_APPLICATION_EUI; + 101:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t AppKey[] = LORAWAN_APPLICATION_KEY; + 102:./Middlewares/Third_Party/Lora/Core/lora.c **** + 103:./Middlewares/Third_Party/Lora/Core/lora.c **** #if( OVER_THE_AIR_ACTIVATION == 0 ) + 104:./Middlewares/Third_Party/Lora/Core/lora.c **** + 105:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t NwkSKey[] = LORAWAN_NWKSKEY; + 106:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t AppSKey[] = LORAWAN_APPSKEY; + 107:./Middlewares/Third_Party/Lora/Core/lora.c **** + 108:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 109:./Middlewares/Third_Party/Lora/Core/lora.c **** * Device address + 110:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 111:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint32_t DevAddr = LORAWAN_DEVICE_ADDRESS; + 112:./Middlewares/Third_Party/Lora/Core/lora.c **** + 113:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 114:./Middlewares/Third_Party/Lora/Core/lora.c **** + 115:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 116:./Middlewares/Third_Party/Lora/Core/lora.c **** * User application data buffer size + 117:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 118:./Middlewares/Third_Party/Lora/Core/lora.c **** #define LORAWAN_APP_DATA_BUFF_SIZE 64 + 119:./Middlewares/Third_Party/Lora/Core/lora.c **** + 120:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 121:./Middlewares/Third_Party/Lora/Core/lora.c **** * User application data + 122:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 123:./Middlewares/Third_Party/Lora/Core/lora.c **** static uint8_t AppDataBuff[LORAWAN_APP_DATA_BUFF_SIZE]; + 124:./Middlewares/Third_Party/Lora/Core/lora.c **** + 125:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 126:./Middlewares/Third_Party/Lora/Core/lora.c **** * User application data structure + 127:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 128:./Middlewares/Third_Party/Lora/Core/lora.c **** static lora_AppData_t AppData={ AppDataBuff, 0 ,0 }; + 129:./Middlewares/Third_Party/Lora/Core/lora.c **** + 130:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 131:./Middlewares/Third_Party/Lora/Core/lora.c **** * Indicates if the node is sending confirmed or unconfirmed messages + 132:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 133:./Middlewares/Third_Party/Lora/Core/lora.c **** static FunctionalState IsTxConfirmed ; + 134:./Middlewares/Third_Party/Lora/Core/lora.c **** + 135:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 136:./Middlewares/Third_Party/Lora/Core/lora.c **** * Defines the LoRa parameters at Init + 137:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 138:./Middlewares/Third_Party/Lora/Core/lora.c **** static LoRaParam_t* LoRaParamInit; + 139:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 140:./Middlewares/Third_Party/Lora/Core/lora.c **** * Timer to handle the application data transmission duty cycle + 141:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 142:./Middlewares/Third_Party/Lora/Core/lora.c **** static TimerEvent_t TxNextPacketTimer; + 143:./Middlewares/Third_Party/Lora/Core/lora.c **** + 144:./Middlewares/Third_Party/Lora/Core/lora.c **** static DeviceState_t DeviceState = DEVICE_STATE_INIT ; + 145:./Middlewares/Third_Party/Lora/Core/lora.c **** + 146:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 147:./Middlewares/Third_Party/Lora/Core/lora.c **** * Timer to handle the state of LED1 + 148:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + ARM GAS /tmp/ccY05lmV.s page 4 + + + 149:./Middlewares/Third_Party/Lora/Core/lora.c **** + 150:./Middlewares/Third_Party/Lora/Core/lora.c **** static LoRaMacPrimitives_t LoRaMacPrimitives; + 151:./Middlewares/Third_Party/Lora/Core/lora.c **** static LoRaMacCallback_t LoRaMacCallbacks; + 152:./Middlewares/Third_Party/Lora/Core/lora.c **** static MibRequestConfirm_t mibReq; + 153:./Middlewares/Third_Party/Lora/Core/lora.c **** + 154:./Middlewares/Third_Party/Lora/Core/lora.c **** static LoRaMainCallback_t *LoRaMainCallbacks; + 155:./Middlewares/Third_Party/Lora/Core/lora.c **** + 156:./Middlewares/Third_Party/Lora/Core/lora.c **** + 157:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 158:./Middlewares/Third_Party/Lora/Core/lora.c **** * Indicates if a new packet can be sent + 159:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 160:./Middlewares/Third_Party/Lora/Core/lora.c **** static bool NextTx = true; + 161:./Middlewares/Third_Party/Lora/Core/lora.c **** + 162:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 163:./Middlewares/Third_Party/Lora/Core/lora.c **** * LoRaWAN compliance tests support data + 164:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 165:./Middlewares/Third_Party/Lora/Core/lora.c **** struct ComplianceTest_s + 166:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 167:./Middlewares/Third_Party/Lora/Core/lora.c **** bool Running; + 168:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t State; + 169:./Middlewares/Third_Party/Lora/Core/lora.c **** FunctionalState IsTxConfirmed; + 170:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t AppPort; + 171:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t AppDataSize; + 172:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t *AppDataBuffer; + 173:./Middlewares/Third_Party/Lora/Core/lora.c **** uint16_t DownLinkCounter; + 174:./Middlewares/Third_Party/Lora/Core/lora.c **** bool LinkCheck; + 175:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t DemodMargin; + 176:./Middlewares/Third_Party/Lora/Core/lora.c **** uint8_t NbGateways; + 177:./Middlewares/Third_Party/Lora/Core/lora.c **** }ComplianceTest; + 178:./Middlewares/Third_Party/Lora/Core/lora.c **** + 179:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 180:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief Prepares the payload of the frame + 181:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 182:./Middlewares/Third_Party/Lora/Core/lora.c **** static void PrepareTxFrame( void) + 183:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 184:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.Running == true ) + 185:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 186:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.LinkCheck == true ) + 187:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 188:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.LinkCheck = false; + 189:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 3; + 190:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[0] = 5; + 191:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[1] = ComplianceTest.DemodMargin; + 192:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[2] = ComplianceTest.NbGateways; + 193:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 194:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 195:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 196:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 197:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( ComplianceTest.State ) + 198:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 199:./Middlewares/Third_Party/Lora/Core/lora.c **** case 4: + 200:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 201:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 202:./Middlewares/Third_Party/Lora/Core/lora.c **** case 1: + 203:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 2; + 204:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[0] = ComplianceTest.DownLinkCounter >> 8; + 205:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[1] = ComplianceTest.DownLinkCounter; + ARM GAS /tmp/ccY05lmV.s page 5 + + + 206:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 207:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 208:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 209:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 210:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 211:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 212:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMainCallbacks->LoraTxData(&AppData, &IsTxConfirmed); + 213:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 214:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 215:./Middlewares/Third_Party/Lora/Core/lora.c **** + 216:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 217:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief Prepares the payload of the frame + 218:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 219:./Middlewares/Third_Party/Lora/Core/lora.c **** * \retval [0: frame could be send, 1: error] + 220:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 221:./Middlewares/Third_Party/Lora/Core/lora.c **** static bool SendFrame( void ) + 222:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 223:./Middlewares/Third_Party/Lora/Core/lora.c **** McpsReq_t mcpsReq; + 224:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacTxInfo_t txInfo; + 225:./Middlewares/Third_Party/Lora/Core/lora.c **** + 226:./Middlewares/Third_Party/Lora/Core/lora.c **** if( LoRaMacQueryTxPossible( AppData.BuffSize, &txInfo ) != LORAMAC_STATUS_OK ) + 227:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 228:./Middlewares/Third_Party/Lora/Core/lora.c **** // Send empty frame in order to flush MAC commands + 229:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Type = MCPS_UNCONFIRMED; + 230:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBuffer = NULL; + 231:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBufferSize = 0; + 232:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.Datarate = LoRaParamInit->TxDatarate; + 233:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 234:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 235:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 236:./Middlewares/Third_Party/Lora/Core/lora.c **** if( IsTxConfirmed == DISABLE ) + 237:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 238:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Type = MCPS_UNCONFIRMED; + 239:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fPort = AppData.Port; + 240:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBuffer = AppData.Buff; + 241:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBufferSize = AppData.BuffSize; + 242:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.Datarate = LoRaParamInit->TxDatarate; + 243:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 244:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 245:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 246:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Type = MCPS_CONFIRMED; + 247:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fPort = AppData.Port; + 248:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fBuffer = AppData.Buff; + 249:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fBufferSize = AppData.BuffSize; + 250:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.NbTrials = 8; + 251:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.Datarate = LoRaParamInit->TxDatarate; + 252:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 253:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 254:./Middlewares/Third_Party/Lora/Core/lora.c **** if( LoRaMacMcpsRequest( &mcpsReq ) == LORAMAC_STATUS_OK ) + 255:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 256:./Middlewares/Third_Party/Lora/Core/lora.c **** return false; + 257:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 258:./Middlewares/Third_Party/Lora/Core/lora.c **** return true; + 259:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 260:./Middlewares/Third_Party/Lora/Core/lora.c **** + 261:./Middlewares/Third_Party/Lora/Core/lora.c **** void OnSendEvent( void ) + 262:./Middlewares/Third_Party/Lora/Core/lora.c **** { + ARM GAS /tmp/ccY05lmV.s page 6 + + + 263:./Middlewares/Third_Party/Lora/Core/lora.c **** MibRequestConfirm_t _mibReq; + 264:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacStatus_t status; + 265:./Middlewares/Third_Party/Lora/Core/lora.c **** + 266:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Type = MIB_NETWORK_JOINED; + 267:./Middlewares/Third_Party/Lora/Core/lora.c **** status = LoRaMacMibGetRequestConfirm( &_mibReq ); + 268:./Middlewares/Third_Party/Lora/Core/lora.c **** + 269:./Middlewares/Third_Party/Lora/Core/lora.c **** if( status == LORAMAC_STATUS_OK ) + 270:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 271:./Middlewares/Third_Party/Lora/Core/lora.c **** if( _mibReq.Param.IsNetworkJoined == true ) + 272:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 273:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SEND; + 274:./Middlewares/Third_Party/Lora/Core/lora.c **** NextTx = true; + 275:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 276:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 277:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 278:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_JOIN; + 279:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 280:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 281:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 282:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 283:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief Function executed on TxNextPacket Timeout event + 284:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 285:./Middlewares/Third_Party/Lora/Core/lora.c **** static void OnTxNextPacketTimerEvent( void ) + 286:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 287:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStop( &TxNextPacketTimer ); + 288:./Middlewares/Third_Party/Lora/Core/lora.c **** OnSendEvent(); + 289:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 290:./Middlewares/Third_Party/Lora/Core/lora.c **** + 291:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 292:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief MCPS-Confirm event function + 293:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 294:./Middlewares/Third_Party/Lora/Core/lora.c **** * \param [IN] McpsConfirm - Pointer to the confirm structure, + 295:./Middlewares/Third_Party/Lora/Core/lora.c **** * containing confirm attributes. + 296:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 297:./Middlewares/Third_Party/Lora/Core/lora.c **** static void McpsConfirm( McpsConfirm_t *mcpsConfirm ) + 298:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 25 .loc 1 298 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: + 299:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mcpsConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + 300:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 301:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( mcpsConfirm->McpsRequest ) + 302:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 303:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_UNCONFIRMED: + 304:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 305:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Datarate + 306:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check TxPower + 307:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 308:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 309:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_CONFIRMED: + 310:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 311:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Datarate + 312:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check TxPower + 313:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check AckReceived + ARM GAS /tmp/ccY05lmV.s page 7 + + + 314:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check NbTrials + 315:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 316:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 317:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_PROPRIETARY: + 318:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 319:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 320:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 321:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 322:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 323:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 324:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 325:./Middlewares/Third_Party/Lora/Core/lora.c **** NextTx = true; + 31 .loc 1 325 0 + 32 0000 014B ldr r3, .L2 + 33 0002 0122 movs r2, #1 + 34 0004 1A70 strb r2, [r3] + 326:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 35 .loc 1 326 0 + 36 @ sp needed + 37 0006 7047 bx lr + 38 .L3: + 39 .align 2 + 40 .L2: + 41 0008 00000000 .word .LANCHOR0 + 42 .cfi_endproc + 43 .LFE100: + 45 .section .text.MlmeConfirm,"ax",%progbits + 46 .align 1 + 47 .syntax unified + 48 .code 16 + 49 .thumb_func + 50 .fpu softvfp + 52 MlmeConfirm: + 53 .LFB102: + 327:./Middlewares/Third_Party/Lora/Core/lora.c **** + 328:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 329:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief MCPS-Indication event function + 330:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 331:./Middlewares/Third_Party/Lora/Core/lora.c **** * \param [IN] mcpsIndication - Pointer to the indication structure, + 332:./Middlewares/Third_Party/Lora/Core/lora.c **** * containing indication attributes. + 333:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 334:./Middlewares/Third_Party/Lora/Core/lora.c **** static void McpsIndication( McpsIndication_t *mcpsIndication ) + 335:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 336:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mcpsIndication->Status != LORAMAC_EVENT_INFO_STATUS_OK ) + 337:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 338:./Middlewares/Third_Party/Lora/Core/lora.c **** return; + 339:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 340:./Middlewares/Third_Party/Lora/Core/lora.c **** + 341:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( mcpsIndication->McpsIndication ) + 342:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 343:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_UNCONFIRMED: + 344:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 345:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 346:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 347:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_CONFIRMED: + 348:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 349:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + ARM GAS /tmp/ccY05lmV.s page 8 + + + 350:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 351:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_PROPRIETARY: + 352:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 353:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 354:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 355:./Middlewares/Third_Party/Lora/Core/lora.c **** case MCPS_MULTICAST: + 356:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 357:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 358:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 359:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 360:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 361:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 362:./Middlewares/Third_Party/Lora/Core/lora.c **** + 363:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Multicast + 364:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Port + 365:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Datarate + 366:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check FramePending + 367:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Buffer + 368:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check BufferSize + 369:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Rssi + 370:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check Snr + 371:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check RxSlot + 372:./Middlewares/Third_Party/Lora/Core/lora.c **** + 373:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.Running == true ) + 374:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 375:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DownLinkCounter++; + 376:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 377:./Middlewares/Third_Party/Lora/Core/lora.c **** + 378:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mcpsIndication->RxData == true ) + 379:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 380:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( mcpsIndication->Port ) + 381:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 382:./Middlewares/Third_Party/Lora/Core/lora.c **** case 224: + 383:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.Running == false ) + 384:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 385:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check compliance test enable command (i) + 386:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ( mcpsIndication->BufferSize == 4 ) && + 387:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[0] == 0x01 ) && + 388:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[1] == 0x01 ) && + 389:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[2] == 0x01 ) && + 390:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[3] == 0x01 ) ) + 391:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 392:./Middlewares/Third_Party/Lora/Core/lora.c **** IsTxConfirmed = DISABLE; + 393:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Port = 224; + 394:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 2; + 395:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DownLinkCounter = 0; + 396:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.LinkCheck = false; + 397:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DemodMargin = 0; + 398:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.NbGateways = 0; + 399:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = true; + 400:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 401:./Middlewares/Third_Party/Lora/Core/lora.c **** + 402:./Middlewares/Third_Party/Lora/Core/lora.c **** MibRequestConfirm_t _mibReq; + 403:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Type = MIB_ADR; + 404:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Param.AdrEnable = true; + 405:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &_mibReq ); + 406:./Middlewares/Third_Party/Lora/Core/lora.c **** + ARM GAS /tmp/ccY05lmV.s page 9 + + + 407:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_EU868 ) + 408:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacTestSetDutyCycleOn( false ); + 409:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 410:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 411:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 412:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 413:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 414:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = mcpsIndication->Buffer[0]; + 415:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( ComplianceTest.State ) + 416:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 417:./Middlewares/Third_Party/Lora/Core/lora.c **** case 0: // Check compliance test disable command (ii) + 418:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DownLinkCounter = 0; + 419:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = false; + 420:./Middlewares/Third_Party/Lora/Core/lora.c **** + 421:./Middlewares/Third_Party/Lora/Core/lora.c **** MibRequestConfirm_t _mibReq; + 422:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Type = MIB_ADR; + 423:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + 424:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &_mibReq ); + 425:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_EU868 ) + 426:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacTestSetDutyCycleOn( LORAWAN_DUTYCYCLE_ON ); + 427:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 428:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 429:./Middlewares/Third_Party/Lora/Core/lora.c **** case 1: // (iii, iv) + 430:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 2; + 431:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 432:./Middlewares/Third_Party/Lora/Core/lora.c **** case 2: // Enable confirmed messages (v) + 433:./Middlewares/Third_Party/Lora/Core/lora.c **** IsTxConfirmed = ENABLE; + 434:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 435:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 436:./Middlewares/Third_Party/Lora/Core/lora.c **** case 3: // Disable confirmed messages (vi) + 437:./Middlewares/Third_Party/Lora/Core/lora.c **** IsTxConfirmed = DISABLE; + 438:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 439:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 440:./Middlewares/Third_Party/Lora/Core/lora.c **** case 4: // (vii) + 441:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = mcpsIndication->BufferSize; + 442:./Middlewares/Third_Party/Lora/Core/lora.c **** + 443:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[0] = 4; + 444:./Middlewares/Third_Party/Lora/Core/lora.c **** for( uint8_t i = 1; i < AppData.BuffSize; i++ ) + 445:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 446:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[i] = mcpsIndication->Buffer[i] + 1; + 447:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 448:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 449:./Middlewares/Third_Party/Lora/Core/lora.c **** case 5: // (viii) + 450:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 451:./Middlewares/Third_Party/Lora/Core/lora.c **** MlmeReq_t mlmeReq; + 452:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Type = MLME_LINK_CHECK; + 453:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 454:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 455:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 456:./Middlewares/Third_Party/Lora/Core/lora.c **** case 6: // (ix) + 457:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 458:./Middlewares/Third_Party/Lora/Core/lora.c **** MlmeReq_t mlmeReq; + 459:./Middlewares/Third_Party/Lora/Core/lora.c **** + 460:./Middlewares/Third_Party/Lora/Core/lora.c **** // Disable TestMode and revert back to normal operation + 461:./Middlewares/Third_Party/Lora/Core/lora.c **** + 462:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DownLinkCounter = 0; + 463:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = false; + ARM GAS /tmp/ccY05lmV.s page 10 + + + 464:./Middlewares/Third_Party/Lora/Core/lora.c **** + 465:./Middlewares/Third_Party/Lora/Core/lora.c **** MibRequestConfirm_t mibReq; + 466:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_ADR; + 467:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + 468:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 469:./Middlewares/Third_Party/Lora/Core/lora.c **** + 470:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Type = MLME_JOIN; + 471:./Middlewares/Third_Party/Lora/Core/lora.c **** + 472:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.DevEui = DevEui; + 473:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppEui = AppEui; + 474:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppKey = AppKey; + 475:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.NbTrials = 3; + 476:./Middlewares/Third_Party/Lora/Core/lora.c **** + 477:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 478:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SLEEP; + 479:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 480:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 481:./Middlewares/Third_Party/Lora/Core/lora.c **** case 7: // (x) + 482:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 483:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mcpsIndication->BufferSize == 3 ) + 484:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 485:./Middlewares/Third_Party/Lora/Core/lora.c **** MlmeReq_t mlmeReq; + 486:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Type = MLME_TXCW; + 487:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Timeout = ( uint16_t )( ( mcpsIndication->Buffer[1] << + 488:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 489:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 490:./Middlewares/Third_Party/Lora/Core/lora.c **** else if( mcpsIndication->BufferSize == 7 ) + 491:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 492:./Middlewares/Third_Party/Lora/Core/lora.c **** MlmeReq_t mlmeReq; + 493:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Type = MLME_TXCW_1; + 494:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Timeout = ( uint16_t )( ( mcpsIndication->Buffer[1] << + 495:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Frequency = ( uint32_t )( ( mcpsIndication->Buffer[3] + 496:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Power = mcpsIndication->Buffer[6]; + 497:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 498:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 499:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 500:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 501:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 502:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 503:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 504:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 505:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 506:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 507:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 508:./Middlewares/Third_Party/Lora/Core/lora.c **** + 509:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Port = mcpsIndication->Port; + 510:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = mcpsIndication->BufferSize; + 511:./Middlewares/Third_Party/Lora/Core/lora.c **** memcpy1( AppData.Buff, mcpsIndication->Buffer, AppData.BuffSize ); + 512:./Middlewares/Third_Party/Lora/Core/lora.c **** + 513:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMainCallbacks->LoraRxData( &AppData ); + 514:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 515:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 516:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 517:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 518:./Middlewares/Third_Party/Lora/Core/lora.c **** + 519:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 520:./Middlewares/Third_Party/Lora/Core/lora.c **** * \brief MLME-Confirm event function + ARM GAS /tmp/ccY05lmV.s page 11 + + + 521:./Middlewares/Third_Party/Lora/Core/lora.c **** * + 522:./Middlewares/Third_Party/Lora/Core/lora.c **** * \param [IN] MlmeConfirm - Pointer to the confirm structure, + 523:./Middlewares/Third_Party/Lora/Core/lora.c **** * containing confirm attributes. + 524:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 525:./Middlewares/Third_Party/Lora/Core/lora.c **** static void MlmeConfirm( MlmeConfirm_t *mlmeConfirm ) + 526:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 54 .loc 1 526 0 + 55 .cfi_startproc + 56 @ args = 0, pretend = 0, frame = 0 + 57 @ frame_needed = 0, uses_anonymous_args = 0 + 58 @ link register save eliminated. + 59 .LVL1: + 527:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( mlmeConfirm->MlmeRequest ) + 60 .loc 1 527 0 + 61 0000 0378 ldrb r3, [r0] + 62 0002 002B cmp r3, #0 + 63 0004 05D0 beq .L6 + 64 0006 012B cmp r3, #1 + 65 0008 0ED0 beq .L7 + 66 .L5: + 528:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 529:./Middlewares/Third_Party/Lora/Core/lora.c **** case MLME_JOIN: + 530:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 531:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mlmeConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + 532:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 533:./Middlewares/Third_Party/Lora/Core/lora.c **** // Status is OK, node has joined the network + 534:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_JOINED; + 535:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 536:./Middlewares/Third_Party/Lora/Core/lora.c **** else + 537:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 538:./Middlewares/Third_Party/Lora/Core/lora.c **** // Join was not successful. Try to join again + 539:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_JOIN; + 540:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 541:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 542:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 543:./Middlewares/Third_Party/Lora/Core/lora.c **** case MLME_LINK_CHECK: + 544:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 545:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mlmeConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + 546:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 547:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check DemodMargin + 548:./Middlewares/Third_Party/Lora/Core/lora.c **** // Check NbGateways + 549:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.Running == true ) + 550:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 551:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.LinkCheck = true; + 552:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DemodMargin = mlmeConfirm->DemodMargin; + 553:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.NbGateways = mlmeConfirm->NbGateways; + 554:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 555:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 556:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 557:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 558:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 559:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 560:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 561:./Middlewares/Third_Party/Lora/Core/lora.c **** NextTx = true; + 67 .loc 1 561 0 + 68 000a 0F4B ldr r3, .L9 + 69 000c 0122 movs r2, #1 + ARM GAS /tmp/ccY05lmV.s page 12 + + + 70 000e 1A70 strb r2, [r3] + 562:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 71 .loc 1 562 0 + 72 @ sp needed + 73 0010 7047 bx lr + 74 .L6: + 531:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 75 .loc 1 531 0 + 76 0012 4378 ldrb r3, [r0, #1] + 77 0014 002B cmp r3, #0 + 78 0016 03D1 bne .L8 + 534:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 79 .loc 1 534 0 + 80 0018 0C4B ldr r3, .L9+4 + 81 001a 0222 movs r2, #2 + 82 001c 1A70 strb r2, [r3] + 83 001e F4E7 b .L5 + 84 .L8: + 539:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 85 .loc 1 539 0 + 86 0020 0A4B ldr r3, .L9+4 + 87 0022 0122 movs r2, #1 + 88 0024 1A70 strb r2, [r3] + 89 0026 F0E7 b .L5 + 90 .L7: + 545:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 91 .loc 1 545 0 + 92 0028 4378 ldrb r3, [r0, #1] + 93 002a 002B cmp r3, #0 + 94 002c EDD1 bne .L5 + 549:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 95 .loc 1 549 0 + 96 002e 084B ldr r3, .L9+8 + 97 0030 1B78 ldrb r3, [r3] + 98 0032 002B cmp r3, #0 + 99 0034 E9D0 beq .L5 + 551:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DemodMargin = mlmeConfirm->DemodMargin; + 100 .loc 1 551 0 + 101 0036 064B ldr r3, .L9+8 + 102 0038 0122 movs r2, #1 + 103 003a 9A73 strb r2, [r3, #14] + 552:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.NbGateways = mlmeConfirm->NbGateways; + 104 .loc 1 552 0 + 105 003c 027A ldrb r2, [r0, #8] + 106 003e DA73 strb r2, [r3, #15] + 553:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 107 .loc 1 553 0 + 108 0040 427A ldrb r2, [r0, #9] + 109 0042 1A74 strb r2, [r3, #16] + 110 0044 E1E7 b .L5 + 111 .L10: + 112 0046 C046 .align 2 + 113 .L9: + 114 0048 00000000 .word .LANCHOR0 + 115 004c 00000000 .word .LANCHOR1 + 116 0050 00000000 .word .LANCHOR2 + 117 .cfi_endproc + ARM GAS /tmp/ccY05lmV.s page 13 + + + 118 .LFE102: + 120 .section .text.McpsIndication,"ax",%progbits + 121 .align 1 + 122 .syntax unified + 123 .code 16 + 124 .thumb_func + 125 .fpu softvfp + 127 McpsIndication: + 128 .LFB101: + 335:./Middlewares/Third_Party/Lora/Core/lora.c **** if( mcpsIndication->Status != LORAMAC_EVENT_INFO_STATUS_OK ) + 129 .loc 1 335 0 + 130 .cfi_startproc + 131 @ args = 0, pretend = 0, frame = 32 + 132 @ frame_needed = 0, uses_anonymous_args = 0 + 133 .LVL2: + 134 0000 10B5 push {r4, lr} + 135 .LCFI0: + 136 .cfi_def_cfa_offset 8 + 137 .cfi_offset 4, -8 + 138 .cfi_offset 14, -4 + 139 0002 88B0 sub sp, sp, #32 + 140 .LCFI1: + 141 .cfi_def_cfa_offset 40 + 336:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 142 .loc 1 336 0 + 143 0004 4378 ldrb r3, [r0, #1] + 144 0006 002B cmp r3, #0 + 145 0008 00D0 beq .LCB99 + 146 000a E1E0 b .L11 @long jump + 147 .LCB99: + 373:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 148 .loc 1 373 0 + 149 000c 714B ldr r3, .L34 + 150 000e 1B78 ldrb r3, [r3] + 151 0010 002B cmp r3, #0 + 152 0012 03D0 beq .L13 + 375:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 153 .loc 1 375 0 + 154 0014 6F49 ldr r1, .L34 + 155 0016 8A89 ldrh r2, [r1, #12] + 156 0018 0132 adds r2, r2, #1 + 157 001a 8A81 strh r2, [r1, #12] + 158 .L13: + 378:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 159 .loc 1 378 0 + 160 001c 427B ldrb r2, [r0, #13] + 161 001e 002A cmp r2, #0 + 162 0020 00D1 bne .LCB112 + 163 0022 D5E0 b .L11 @long jump + 164 .LCB112: + 380:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 165 .loc 1 380 0 + 166 0024 C278 ldrb r2, [r0, #3] + 167 0026 E02A cmp r2, #224 + 168 0028 00D0 beq .LCB115 + 169 002a C3E0 b .L31 @long jump + 170 .LCB115: + ARM GAS /tmp/ccY05lmV.s page 14 + + + 383:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 171 .loc 1 383 0 + 172 002c 002B cmp r3, #0 + 173 002e 2DD1 bne .L16 + 386:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[0] == 0x01 ) && + 174 .loc 1 386 0 + 175 0030 037B ldrb r3, [r0, #12] + 176 0032 042B cmp r3, #4 + 177 0034 00D0 beq .LCB120 + 178 0036 CBE0 b .L11 @long jump + 179 .LCB120: + 387:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[1] == 0x01 ) && + 180 .loc 1 387 0 discriminator 1 + 181 0038 8368 ldr r3, [r0, #8] + 182 003a 1A78 ldrb r2, [r3] + 386:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[0] == 0x01 ) && + 183 .loc 1 386 0 discriminator 1 + 184 003c 012A cmp r2, #1 + 185 003e 00D0 beq .LCB124 + 186 0040 C6E0 b .L11 @long jump + 187 .LCB124: + 388:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[2] == 0x01 ) && + 188 .loc 1 388 0 + 189 0042 5A78 ldrb r2, [r3, #1] + 387:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[1] == 0x01 ) && + 190 .loc 1 387 0 + 191 0044 012A cmp r2, #1 + 192 0046 00D0 beq .LCB127 + 193 0048 C2E0 b .L11 @long jump + 194 .LCB127: + 389:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[3] == 0x01 ) ) + 195 .loc 1 389 0 + 196 004a 9A78 ldrb r2, [r3, #2] + 388:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[2] == 0x01 ) && + 197 .loc 1 388 0 + 198 004c 012A cmp r2, #1 + 199 004e 00D0 beq .LCB130 + 200 0050 BEE0 b .L11 @long jump + 201 .LCB130: + 390:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 202 .loc 1 390 0 + 203 0052 DB78 ldrb r3, [r3, #3] + 389:./Middlewares/Third_Party/Lora/Core/lora.c **** ( mcpsIndication->Buffer[3] == 0x01 ) ) + 204 .loc 1 389 0 + 205 0054 012B cmp r3, #1 + 206 0056 00D0 beq .LCB133 + 207 0058 BAE0 b .L11 @long jump + 208 .LCB133: + 209 .LBB2: + 392:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Port = 224; + 210 .loc 1 392 0 + 211 005a 0024 movs r4, #0 + 212 005c 5E4B ldr r3, .L34+4 + 213 005e 1C70 strb r4, [r3] + 393:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 2; + 214 .loc 1 393 0 + 215 0060 5E4B ldr r3, .L34+8 + ARM GAS /tmp/ccY05lmV.s page 15 + + + 216 0062 DF32 adds r2, r2, #223 + 217 0064 5A71 strb r2, [r3, #5] + 394:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DownLinkCounter = 0; + 218 .loc 1 394 0 + 219 0066 0221 movs r1, #2 + 220 0068 1971 strb r1, [r3, #4] + 395:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.LinkCheck = false; + 221 .loc 1 395 0 + 222 006a 5A4B ldr r3, .L34 + 223 006c 9C81 strh r4, [r3, #12] + 396:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.DemodMargin = 0; + 224 .loc 1 396 0 + 225 006e 9C73 strb r4, [r3, #14] + 397:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.NbGateways = 0; + 226 .loc 1 397 0 + 227 0070 DC73 strb r4, [r3, #15] + 398:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = true; + 228 .loc 1 398 0 + 229 0072 1C74 strb r4, [r3, #16] + 399:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 230 .loc 1 399 0 + 231 0074 DF3A subs r2, r2, #223 + 232 0076 1A70 strb r2, [r3] + 400:./Middlewares/Third_Party/Lora/Core/lora.c **** + 233 .loc 1 400 0 + 234 0078 5A70 strb r2, [r3, #1] + 403:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Param.AdrEnable = true; + 235 .loc 1 403 0 + 236 007a 03A8 add r0, sp, #12 + 237 .LVL3: + 238 007c 0170 strb r1, [r0] + 404:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &_mibReq ); + 239 .loc 1 404 0 + 240 007e 0271 strb r2, [r0, #4] + 405:./Middlewares/Third_Party/Lora/Core/lora.c **** + 241 .loc 1 405 0 + 242 0080 FFF7FEFF bl LoRaMacMibSetRequestConfirm + 243 .LVL4: + 408:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 244 .loc 1 408 0 + 245 0084 2000 movs r0, r4 + 246 0086 FFF7FEFF bl LoRaMacTestSetDutyCycleOn + 247 .LVL5: + 248 008a A1E0 b .L11 + 249 .LVL6: + 250 .L16: + 251 .LBE2: + 414:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( ComplianceTest.State ) + 252 .loc 1 414 0 + 253 008c 8268 ldr r2, [r0, #8] + 254 008e 1378 ldrb r3, [r2] + 255 0090 5049 ldr r1, .L34 + 256 0092 4B70 strb r3, [r1, #1] + 415:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 257 .loc 1 415 0 + 258 0094 072B cmp r3, #7 + 259 0096 00D9 bls .LCB171 + ARM GAS /tmp/ccY05lmV.s page 16 + + + 260 0098 9AE0 b .L11 @long jump + 261 .LCB171: + 262 009a 9B00 lsls r3, r3, #2 + 263 009c 5049 ldr r1, .L34+12 + 264 009e CB58 ldr r3, [r1, r3] + 265 00a0 9F46 mov pc, r3 + 266 .section .rodata.McpsIndication,"a",%progbits + 267 .align 2 + 268 .L19: + 269 0000 A2000000 .word .L18 + 270 0004 C4000000 .word .L20 + 271 0008 CC000000 .word .L21 + 272 000c D8000000 .word .L22 + 273 0010 E6000000 .word .L23 + 274 0014 10010000 .word .L24 + 275 0018 1C010000 .word .L25 + 276 001c 5A010000 .word .L26 + 277 .section .text.McpsIndication + 278 .L18: + 279 .LBB3: + 418:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = false; + 280 .loc 1 418 0 + 281 00a2 4C4B ldr r3, .L34 + 282 00a4 0022 movs r2, #0 + 283 00a6 9A81 strh r2, [r3, #12] + 419:./Middlewares/Third_Party/Lora/Core/lora.c **** + 284 .loc 1 419 0 + 285 00a8 1A70 strb r2, [r3] + 422:./Middlewares/Third_Party/Lora/Core/lora.c **** _mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + 286 .loc 1 422 0 + 287 00aa 03A8 add r0, sp, #12 + 288 .LVL7: + 289 00ac 0223 movs r3, #2 + 290 00ae 0370 strb r3, [r0] + 423:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &_mibReq ); + 291 .loc 1 423 0 + 292 00b0 4C4B ldr r3, .L34+16 + 293 00b2 1B68 ldr r3, [r3] + 294 00b4 5B7A ldrb r3, [r3, #9] + 295 00b6 0371 strb r3, [r0, #4] + 424:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_EU868 ) + 296 .loc 1 424 0 + 297 00b8 FFF7FEFF bl LoRaMacMibSetRequestConfirm + 298 .LVL8: + 426:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 299 .loc 1 426 0 + 300 00bc 0120 movs r0, #1 + 301 00be FFF7FEFF bl LoRaMacTestSetDutyCycleOn + 302 .LVL9: + 428:./Middlewares/Third_Party/Lora/Core/lora.c **** case 1: // (iii, iv) + 303 .loc 1 428 0 + 304 00c2 85E0 b .L11 + 305 .LVL10: + 306 .L20: + 430:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 307 .loc 1 430 0 + 308 00c4 454B ldr r3, .L34+8 + ARM GAS /tmp/ccY05lmV.s page 17 + + + 309 00c6 0222 movs r2, #2 + 310 00c8 1A71 strb r2, [r3, #4] + 431:./Middlewares/Third_Party/Lora/Core/lora.c **** case 2: // Enable confirmed messages (v) + 311 .loc 1 431 0 + 312 00ca 81E0 b .L11 + 313 .L21: + 433:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 314 .loc 1 433 0 + 315 00cc 0123 movs r3, #1 + 316 00ce 424A ldr r2, .L34+4 + 317 00d0 1370 strb r3, [r2] + 434:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 318 .loc 1 434 0 + 319 00d2 404A ldr r2, .L34 + 320 00d4 5370 strb r3, [r2, #1] + 435:./Middlewares/Third_Party/Lora/Core/lora.c **** case 3: // Disable confirmed messages (vi) + 321 .loc 1 435 0 + 322 00d6 7BE0 b .L11 + 323 .L22: + 437:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 324 .loc 1 437 0 + 325 00d8 3F4B ldr r3, .L34+4 + 326 00da 0022 movs r2, #0 + 327 00dc 1A70 strb r2, [r3] + 438:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 328 .loc 1 438 0 + 329 00de 3D4B ldr r3, .L34 + 330 00e0 0132 adds r2, r2, #1 + 331 00e2 5A70 strb r2, [r3, #1] + 439:./Middlewares/Third_Party/Lora/Core/lora.c **** case 4: // (vii) + 332 .loc 1 439 0 + 333 00e4 74E0 b .L11 + 334 .L23: + 441:./Middlewares/Third_Party/Lora/Core/lora.c **** + 335 .loc 1 441 0 + 336 00e6 027B ldrb r2, [r0, #12] + 337 00e8 3C4B ldr r3, .L34+8 + 338 00ea 1A71 strb r2, [r3, #4] + 443:./Middlewares/Third_Party/Lora/Core/lora.c **** for( uint8_t i = 1; i < AppData.BuffSize; i++ ) + 339 .loc 1 443 0 + 340 00ec 1B68 ldr r3, [r3] + 341 00ee 0422 movs r2, #4 + 342 00f0 1A70 strb r2, [r3] + 343 .LVL11: + 344 .LBB4: + 444:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 345 .loc 1 444 0 + 346 00f2 0123 movs r3, #1 + 347 00f4 07E0 b .L27 + 348 .LVL12: + 349 .L28: + 446:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 350 .loc 1 446 0 discriminator 3 + 351 00f6 8268 ldr r2, [r0, #8] + 352 00f8 D25C ldrb r2, [r2, r3] + 353 00fa 3849 ldr r1, .L34+8 + 354 00fc 0968 ldr r1, [r1] + ARM GAS /tmp/ccY05lmV.s page 18 + + + 355 00fe 0132 adds r2, r2, #1 + 356 0100 CA54 strb r2, [r1, r3] + 444:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 357 .loc 1 444 0 discriminator 3 + 358 0102 0133 adds r3, r3, #1 + 359 .LVL13: + 360 0104 DBB2 uxtb r3, r3 + 361 .LVL14: + 362 .L27: + 444:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 363 .loc 1 444 0 is_stmt 0 discriminator 1 + 364 0106 354A ldr r2, .L34+8 + 365 0108 1279 ldrb r2, [r2, #4] + 366 010a 9A42 cmp r2, r3 + 367 010c F3D8 bhi .L28 + 368 010e 5FE0 b .L11 + 369 .LVL15: + 370 .L24: + 371 .LBE4: + 372 .LBB5: + 452:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 373 .loc 1 452 0 is_stmt 1 discriminator 4 + 374 0110 03A8 add r0, sp, #12 + 375 .LVL16: + 376 0112 0123 movs r3, #1 + 377 0114 0370 strb r3, [r0] + 453:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 378 .loc 1 453 0 discriminator 4 + 379 0116 FFF7FEFF bl LoRaMacMlmeRequest + 380 .LVL17: + 381 .LBE5: + 455:./Middlewares/Third_Party/Lora/Core/lora.c **** case 6: // (ix) + 382 .loc 1 455 0 discriminator 4 + 383 011a 59E0 b .L11 + 384 .LVL18: + 385 .L25: + 386 .LBB6: + 462:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.Running = false; + 387 .loc 1 462 0 discriminator 5 + 388 011c 2D4B ldr r3, .L34 + 389 011e 0022 movs r2, #0 + 390 0120 9A81 strh r2, [r3, #12] + 463:./Middlewares/Third_Party/Lora/Core/lora.c **** + 391 .loc 1 463 0 discriminator 5 + 392 0122 1A70 strb r2, [r3] + 466:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + 393 .loc 1 466 0 discriminator 5 + 394 0124 0223 movs r3, #2 + 395 0126 6A46 mov r2, sp + 396 0128 1370 strb r3, [r2] + 467:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 397 .loc 1 467 0 discriminator 5 + 398 012a 2E4B ldr r3, .L34+16 + 399 012c 1B68 ldr r3, [r3] + 400 012e 5B7A ldrb r3, [r3, #9] + 401 0130 1371 strb r3, [r2, #4] + 468:./Middlewares/Third_Party/Lora/Core/lora.c **** + ARM GAS /tmp/ccY05lmV.s page 19 + + + 402 .loc 1 468 0 discriminator 5 + 403 0132 6846 mov r0, sp + 404 .LVL19: + 405 0134 FFF7FEFF bl LoRaMacMibSetRequestConfirm + 406 .LVL20: + 470:./Middlewares/Third_Party/Lora/Core/lora.c **** + 407 .loc 1 470 0 discriminator 5 + 408 0138 03A8 add r0, sp, #12 + 409 013a 0023 movs r3, #0 + 410 013c 0370 strb r3, [r0] + 472:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppEui = AppEui; + 411 .loc 1 472 0 discriminator 5 + 412 013e 2A4B ldr r3, .L34+20 + 413 0140 4360 str r3, [r0, #4] + 473:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppKey = AppKey; + 414 .loc 1 473 0 discriminator 5 + 415 0142 2A4B ldr r3, .L34+24 + 416 0144 8360 str r3, [r0, #8] + 474:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.NbTrials = 3; + 417 .loc 1 474 0 discriminator 5 + 418 0146 2A4B ldr r3, .L34+28 + 419 0148 C360 str r3, [r0, #12] + 475:./Middlewares/Third_Party/Lora/Core/lora.c **** + 420 .loc 1 475 0 discriminator 5 + 421 014a 0323 movs r3, #3 + 422 014c 0374 strb r3, [r0, #16] + 477:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SLEEP; + 423 .loc 1 477 0 discriminator 5 + 424 014e FFF7FEFF bl LoRaMacMlmeRequest + 425 .LVL21: + 478:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 426 .loc 1 478 0 discriminator 5 + 427 0152 284B ldr r3, .L34+32 + 428 0154 0522 movs r2, #5 + 429 0156 1A70 strb r2, [r3] + 430 .LBE6: + 480:./Middlewares/Third_Party/Lora/Core/lora.c **** case 7: // (x) + 431 .loc 1 480 0 discriminator 5 + 432 0158 3AE0 b .L11 + 433 .LVL22: + 434 .L26: + 483:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 435 .loc 1 483 0 + 436 015a 037B ldrb r3, [r0, #12] + 437 015c 032B cmp r3, #3 + 438 015e 05D0 beq .L32 + 490:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 439 .loc 1 490 0 + 440 0160 072B cmp r3, #7 + 441 0162 0ED0 beq .L33 + 442 .LVL23: + 443 .L30: + 499:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 444 .loc 1 499 0 + 445 0164 1B4B ldr r3, .L34 + 446 0166 0122 movs r2, #1 + 447 0168 5A70 strb r2, [r3, #1] + ARM GAS /tmp/ccY05lmV.s page 20 + + + 501:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 448 .loc 1 501 0 + 449 016a 31E0 b .L11 + 450 .LVL24: + 451 .L32: + 452 .LBB7: + 486:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Timeout = ( uint16_t )( ( mcpsIndication->Buffer[1] << + 453 .loc 1 486 0 + 454 016c 03A8 add r0, sp, #12 + 455 .LVL25: + 456 016e 013B subs r3, r3, #1 + 457 0170 0370 strb r3, [r0] + 487:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 458 .loc 1 487 0 + 459 0172 5178 ldrb r1, [r2, #1] + 460 0174 0902 lsls r1, r1, #8 + 461 0176 9378 ldrb r3, [r2, #2] + 462 0178 0B43 orrs r3, r1 + 463 017a 8380 strh r3, [r0, #4] + 488:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 464 .loc 1 488 0 + 465 017c FFF7FEFF bl LoRaMacMlmeRequest + 466 .LVL26: + 467 .LBE7: + 468 0180 F0E7 b .L30 + 469 .LVL27: + 470 .L33: + 471 .LBB8: + 493:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Timeout = ( uint16_t )( ( mcpsIndication->Buffer[1] << + 472 .loc 1 493 0 + 473 0182 03A9 add r1, sp, #12 + 474 0184 043B subs r3, r3, #4 + 475 0186 0B70 strb r3, [r1] + 494:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Frequency = ( uint32_t )( ( mcpsIndication->Buffer[3] + 476 .loc 1 494 0 + 477 0188 5478 ldrb r4, [r2, #1] + 478 018a 2402 lsls r4, r4, #8 + 479 018c 9378 ldrb r3, [r2, #2] + 480 018e 2343 orrs r3, r4 + 481 0190 8B80 strh r3, [r1, #4] + 495:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.TxCw.Power = mcpsIndication->Buffer[6]; + 482 .loc 1 495 0 + 483 0192 D378 ldrb r3, [r2, #3] + 484 0194 1B04 lsls r3, r3, #16 + 485 0196 1479 ldrb r4, [r2, #4] + 486 0198 2402 lsls r4, r4, #8 + 487 019a 2343 orrs r3, r4 + 488 019c 5279 ldrb r2, [r2, #5] + 489 019e 1343 orrs r3, r2 + 490 01a0 6422 movs r2, #100 + 491 01a2 5343 muls r3, r2 + 492 01a4 0593 str r3, [sp, #20] + 496:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 493 .loc 1 496 0 + 494 01a6 8368 ldr r3, [r0, #8] + 495 01a8 9B79 ldrb r3, [r3, #6] + 496 01aa 0B73 strb r3, [r1, #12] + ARM GAS /tmp/ccY05lmV.s page 21 + + + 497:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 497 .loc 1 497 0 + 498 01ac 0800 movs r0, r1 + 499 .LVL28: + 500 01ae FFF7FEFF bl LoRaMacMlmeRequest + 501 .LVL29: + 502 01b2 D7E7 b .L30 + 503 .LVL30: + 504 .L31: + 505 .LBE8: + 506 .LBE3: + 509:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = mcpsIndication->BufferSize; + 507 .loc 1 509 0 + 508 01b4 094C ldr r4, .L34+8 + 509 01b6 6271 strb r2, [r4, #5] + 510:./Middlewares/Third_Party/Lora/Core/lora.c **** memcpy1( AppData.Buff, mcpsIndication->Buffer, AppData.BuffSize ); + 510 .loc 1 510 0 + 511 01b8 027B ldrb r2, [r0, #12] + 512 01ba 2271 strb r2, [r4, #4] + 511:./Middlewares/Third_Party/Lora/Core/lora.c **** + 513 .loc 1 511 0 + 514 01bc 8168 ldr r1, [r0, #8] + 515 01be 92B2 uxth r2, r2 + 516 01c0 2068 ldr r0, [r4] + 517 .LVL31: + 518 01c2 FFF7FEFF bl memcpy1 + 519 .LVL32: + 513:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 520 .loc 1 513 0 + 521 01c6 0C4B ldr r3, .L34+36 + 522 01c8 1B68 ldr r3, [r3] + 523 01ca 1B69 ldr r3, [r3, #16] + 524 01cc 2000 movs r0, r4 + 525 01ce 9847 blx r3 + 526 .LVL33: + 527 .L11: + 517:./Middlewares/Third_Party/Lora/Core/lora.c **** + 528 .loc 1 517 0 + 529 01d0 08B0 add sp, sp, #32 + 530 @ sp needed + 531 01d2 10BD pop {r4, pc} + 532 .L35: + 533 .align 2 + 534 .L34: + 535 01d4 00000000 .word .LANCHOR2 + 536 01d8 00000000 .word .LANCHOR3 + 537 01dc 00000000 .word .LANCHOR4 + 538 01e0 00000000 .word .L19 + 539 01e4 00000000 .word .LANCHOR5 + 540 01e8 00000000 .word .LANCHOR6 + 541 01ec 00000000 .word .LANCHOR7 + 542 01f0 00000000 .word .LANCHOR8 + 543 01f4 00000000 .word .LANCHOR1 + 544 01f8 00000000 .word .LANCHOR9 + 545 .cfi_endproc + 546 .LFE101: + 548 .section .text.OnSendEvent,"ax",%progbits + ARM GAS /tmp/ccY05lmV.s page 22 + + + 549 .align 1 + 550 .global OnSendEvent + 551 .syntax unified + 552 .code 16 + 553 .thumb_func + 554 .fpu softvfp + 556 OnSendEvent: + 557 .LFB98: + 262:./Middlewares/Third_Party/Lora/Core/lora.c **** MibRequestConfirm_t _mibReq; + 558 .loc 1 262 0 + 559 .cfi_startproc + 560 @ args = 0, pretend = 0, frame = 16 + 561 @ frame_needed = 0, uses_anonymous_args = 0 + 562 0000 00B5 push {lr} + 563 .LCFI2: + 564 .cfi_def_cfa_offset 4 + 565 .cfi_offset 14, -4 + 566 0002 85B0 sub sp, sp, #20 + 567 .LCFI3: + 568 .cfi_def_cfa_offset 24 + 266:./Middlewares/Third_Party/Lora/Core/lora.c **** status = LoRaMacMibGetRequestConfirm( &_mibReq ); + 569 .loc 1 266 0 + 570 0004 01A8 add r0, sp, #4 + 571 0006 0123 movs r3, #1 + 572 0008 0370 strb r3, [r0] + 267:./Middlewares/Third_Party/Lora/Core/lora.c **** + 573 .loc 1 267 0 + 574 000a FFF7FEFF bl LoRaMacMibGetRequestConfirm + 575 .LVL34: + 269:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 576 .loc 1 269 0 + 577 000e 0028 cmp r0, #0 + 578 0010 06D1 bne .L36 + 271:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 579 .loc 1 271 0 + 580 0012 01AB add r3, sp, #4 + 581 0014 1B79 ldrb r3, [r3, #4] + 582 0016 002B cmp r3, #0 + 583 0018 04D1 bne .L39 + 278:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 584 .loc 1 278 0 + 585 001a 064B ldr r3, .L40 + 586 001c 0122 movs r2, #1 + 587 001e 1A70 strb r2, [r3] + 588 .L36: + 281:./Middlewares/Third_Party/Lora/Core/lora.c **** /*! + 589 .loc 1 281 0 + 590 0020 05B0 add sp, sp, #20 + 591 @ sp needed + 592 0022 00BD pop {pc} + 593 .L39: + 273:./Middlewares/Third_Party/Lora/Core/lora.c **** NextTx = true; + 594 .loc 1 273 0 + 595 0024 034B ldr r3, .L40 + 596 0026 0322 movs r2, #3 + 597 0028 1A70 strb r2, [r3] + 274:./Middlewares/Third_Party/Lora/Core/lora.c **** } + ARM GAS /tmp/ccY05lmV.s page 23 + + + 598 .loc 1 274 0 + 599 002a 034B ldr r3, .L40+4 + 600 002c 023A subs r2, r2, #2 + 601 002e 1A70 strb r2, [r3] + 602 0030 F6E7 b .L36 + 603 .L41: + 604 0032 C046 .align 2 + 605 .L40: + 606 0034 00000000 .word .LANCHOR1 + 607 0038 00000000 .word .LANCHOR0 + 608 .cfi_endproc + 609 .LFE98: + 611 .section .text.OnTxNextPacketTimerEvent,"ax",%progbits + 612 .align 1 + 613 .syntax unified + 614 .code 16 + 615 .thumb_func + 616 .fpu softvfp + 618 OnTxNextPacketTimerEvent: + 619 .LFB99: + 286:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStop( &TxNextPacketTimer ); + 620 .loc 1 286 0 + 621 .cfi_startproc + 622 @ args = 0, pretend = 0, frame = 0 + 623 @ frame_needed = 0, uses_anonymous_args = 0 + 624 0000 10B5 push {r4, lr} + 625 .LCFI4: + 626 .cfi_def_cfa_offset 8 + 627 .cfi_offset 4, -8 + 628 .cfi_offset 14, -4 + 287:./Middlewares/Third_Party/Lora/Core/lora.c **** OnSendEvent(); + 629 .loc 1 287 0 + 630 0002 0348 ldr r0, .L43 + 631 0004 FFF7FEFF bl TimerStop + 632 .LVL35: + 288:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 633 .loc 1 288 0 + 634 0008 FFF7FEFF bl OnSendEvent + 635 .LVL36: + 289:./Middlewares/Third_Party/Lora/Core/lora.c **** + 636 .loc 1 289 0 + 637 @ sp needed + 638 000c 10BD pop {r4, pc} + 639 .L44: + 640 000e C046 .align 2 + 641 .L43: + 642 0010 00000000 .word .LANCHOR10 + 643 .cfi_endproc + 644 .LFE99: + 646 .section .text.lora_Init,"ax",%progbits + 647 .align 1 + 648 .global lora_Init + 649 .syntax unified + 650 .code 16 + 651 .thumb_func + 652 .fpu softvfp + 654 lora_Init: + ARM GAS /tmp/ccY05lmV.s page 24 + + + 655 .LFB103: + 563:./Middlewares/Third_Party/Lora/Core/lora.c **** /** + 564:./Middlewares/Third_Party/Lora/Core/lora.c **** * lora Init + 565:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 566:./Middlewares/Third_Party/Lora/Core/lora.c **** void lora_Init (LoRaMainCallback_t *callbacks, LoRaParam_t* LoRaParam ) + 567:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 656 .loc 1 567 0 + 657 .cfi_startproc + 658 @ args = 0, pretend = 0, frame = 0 + 659 @ frame_needed = 0, uses_anonymous_args = 0 + 660 .LVL37: + 661 0000 10B5 push {r4, lr} + 662 .LCFI5: + 663 .cfi_def_cfa_offset 8 + 664 .cfi_offset 4, -8 + 665 .cfi_offset 14, -4 + 568:./Middlewares/Third_Party/Lora/Core/lora.c **** /* init the DeviceState*/ + 569:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState= DEVICE_STATE_INIT; + 666 .loc 1 569 0 + 667 0002 224B ldr r3, .L52 + 668 0004 0022 movs r2, #0 + 669 0006 1A70 strb r2, [r3] + 570:./Middlewares/Third_Party/Lora/Core/lora.c **** + 571:./Middlewares/Third_Party/Lora/Core/lora.c **** /* init the Tx Duty Cycle*/ + 572:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaParamInit = LoRaParam; + 670 .loc 1 572 0 + 671 0008 214B ldr r3, .L52+4 + 672 000a 1960 str r1, [r3] + 573:./Middlewares/Third_Party/Lora/Core/lora.c **** + 574:./Middlewares/Third_Party/Lora/Core/lora.c **** /* init the main call backs*/ + 575:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMainCallbacks = callbacks; + 673 .loc 1 575 0 + 674 000c 214B ldr r3, .L52+8 + 675 000e 1860 str r0, [r3] + 576:./Middlewares/Third_Party/Lora/Core/lora.c **** + 577:./Middlewares/Third_Party/Lora/Core/lora.c **** #if (STATIC_DEVICE_EUI != 1) + 578:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMainCallbacks->BoardGetUniqueId( DevEui ); + 676 .loc 1 578 0 + 677 0010 4368 ldr r3, [r0, #4] + 678 0012 214C ldr r4, .L52+12 + 679 0014 2000 movs r0, r4 + 680 .LVL38: + 681 0016 9847 blx r3 + 682 .LVL39: + 579:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 580:./Middlewares/Third_Party/Lora/Core/lora.c **** + 581:./Middlewares/Third_Party/Lora/Core/lora.c **** #if( OVER_THE_AIR_ACTIVATION != 0 ) + 582:./Middlewares/Third_Party/Lora/Core/lora.c **** + 583:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("OTAA\n\r"); + 683 .loc 1 583 0 + 684 0018 2048 ldr r0, .L52+16 + 685 001a FFF7FEFF bl vcom_Send + 686 .LVL40: + 584:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("DevEui= %02X", DevEui[0]) ;for(int i=1; i<8 ; i++) {PRINTF("-%02X", DevEui[i]); }; PRINTF + 687 .loc 1 584 0 + 688 001e 2178 ldrb r1, [r4] + 689 0020 1F48 ldr r0, .L52+20 + ARM GAS /tmp/ccY05lmV.s page 25 + + + 690 0022 FFF7FEFF bl vcom_Send + 691 .LVL41: + 692 .LBB9: + 693 0026 0124 movs r4, #1 + 694 0028 05E0 b .L46 + 695 .LVL42: + 696 .L47: + 697 .loc 1 584 0 is_stmt 0 discriminator 3 + 698 002a 1B4B ldr r3, .L52+12 + 699 002c 195D ldrb r1, [r3, r4] + 700 002e 1D48 ldr r0, .L52+24 + 701 0030 FFF7FEFF bl vcom_Send + 702 .LVL43: + 703 0034 0134 adds r4, r4, #1 + 704 .LVL44: + 705 .L46: + 706 .loc 1 584 0 discriminator 1 + 707 0036 072C cmp r4, #7 + 708 0038 F7DD ble .L47 + 709 .LBE9: + 710 .loc 1 584 0 discriminator 4 + 711 003a 1B48 ldr r0, .L52+28 + 712 003c FFF7FEFF bl vcom_Send + 713 .LVL45: + 585:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("AppEui= %02X", AppEui[0]) ;for(int i=1; i<8 ; i++) {PRINTF("-%02X", AppEui[i]); }; PRINTF + 714 .loc 1 585 0 is_stmt 1 discriminator 4 + 715 0040 1A4B ldr r3, .L52+32 + 716 0042 1978 ldrb r1, [r3] + 717 0044 1A48 ldr r0, .L52+36 + 718 0046 FFF7FEFF bl vcom_Send + 719 .LVL46: + 720 .LBB10: + 721 004a 0124 movs r4, #1 + 722 .LVL47: + 723 004c 05E0 b .L48 + 724 .LVL48: + 725 .L49: + 726 .loc 1 585 0 is_stmt 0 discriminator 3 + 727 004e 174B ldr r3, .L52+32 + 728 0050 195D ldrb r1, [r3, r4] + 729 0052 1448 ldr r0, .L52+24 + 730 0054 FFF7FEFF bl vcom_Send + 731 .LVL49: + 732 0058 0134 adds r4, r4, #1 + 733 .LVL50: + 734 .L48: + 735 .loc 1 585 0 discriminator 1 + 736 005a 072C cmp r4, #7 + 737 005c F7DD ble .L49 + 738 .LBE10: + 739 .loc 1 585 0 discriminator 4 + 740 005e 1248 ldr r0, .L52+28 + 741 0060 FFF7FEFF bl vcom_Send + 742 .LVL51: + 586:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("AppKey= %02X", AppKey[0]) ;for(int i=1; i<16; i++) {PRINTF(" %02X", AppKey[i]); }; PRINTF + 743 .loc 1 586 0 is_stmt 1 discriminator 4 + 744 0064 134B ldr r3, .L52+40 + ARM GAS /tmp/ccY05lmV.s page 26 + + + 745 0066 1978 ldrb r1, [r3] + 746 0068 1348 ldr r0, .L52+44 + 747 006a FFF7FEFF bl vcom_Send + 748 .LVL52: + 749 .LBB11: + 750 006e 0124 movs r4, #1 + 751 .LVL53: + 752 0070 05E0 b .L50 + 753 .LVL54: + 754 .L51: + 755 .loc 1 586 0 is_stmt 0 discriminator 3 + 756 0072 104B ldr r3, .L52+40 + 757 0074 195D ldrb r1, [r3, r4] + 758 0076 1148 ldr r0, .L52+48 + 759 0078 FFF7FEFF bl vcom_Send + 760 .LVL55: + 761 007c 0134 adds r4, r4, #1 + 762 .LVL56: + 763 .L50: + 764 .loc 1 586 0 discriminator 1 + 765 007e 0F2C cmp r4, #15 + 766 0080 F7DD ble .L51 + 767 .LBE11: + 768 .loc 1 586 0 discriminator 4 + 769 0082 0F48 ldr r0, .L52+52 + 770 0084 FFF7FEFF bl vcom_Send + 771 .LVL57: + 587:./Middlewares/Third_Party/Lora/Core/lora.c **** #else + 588:./Middlewares/Third_Party/Lora/Core/lora.c **** + 589:./Middlewares/Third_Party/Lora/Core/lora.c **** #if (STATIC_DEVICE_ADDRESS != 1) + 590:./Middlewares/Third_Party/Lora/Core/lora.c **** // Random seed initialization + 591:./Middlewares/Third_Party/Lora/Core/lora.c **** srand1( LoRaMainCallbacks->BoardGetRandomSeed( ) ); + 592:./Middlewares/Third_Party/Lora/Core/lora.c **** // Choose a random device address + 593:./Middlewares/Third_Party/Lora/Core/lora.c **** DevAddr = randr( 0, 0x01FFFFFF ); + 594:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 595:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("ABP\n\r"); + 596:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("DevEui= %02X", DevEui[0]) ;for(int i=1; i<8 ; i++) {PRINTF("-%02X", DevEui[i]); }; PRINTF + 597:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("DevAdd= %08X\n\r", DevAddr) ; + 598:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("NwkSKey= %02X", NwkSKey[0]) ;for(int i=1; i<16 ; i++) {PRINTF(" %02X", NwkSKey[i]); }; PR + 599:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("AppSKey= %02X", AppSKey[0]) ;for(int i=1; i<16 ; i++) {PRINTF(" %02X", AppSKey[i]); }; PR + 600:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 601:./Middlewares/Third_Party/Lora/Core/lora.c **** + 602:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 772 .loc 1 602 0 is_stmt 1 discriminator 4 + 773 @ sp needed + 774 .LVL58: + 775 0088 10BD pop {r4, pc} + 776 .L53: + 777 008a C046 .align 2 + 778 .L52: + 779 008c 00000000 .word .LANCHOR1 + 780 0090 00000000 .word .LANCHOR5 + 781 0094 00000000 .word .LANCHOR9 + 782 0098 00000000 .word .LANCHOR6 + 783 009c 00000000 .word .LC21 + 784 00a0 08000000 .word .LC23 + 785 00a4 18000000 .word .LC25 + ARM GAS /tmp/ccY05lmV.s page 27 + + + 786 00a8 20000000 .word .LC27 + 787 00ac 00000000 .word .LANCHOR7 + 788 00b0 24000000 .word .LC30 + 789 00b4 00000000 .word .LANCHOR8 + 790 00b8 34000000 .word .LC33 + 791 00bc 44000000 .word .LC35 + 792 00c0 4C000000 .word .LC37 + 793 .cfi_endproc + 794 .LFE103: + 796 .section .text.lora_fsm,"ax",%progbits + 797 .align 1 + 798 .global lora_fsm + 799 .syntax unified + 800 .code 16 + 801 .thumb_func + 802 .fpu softvfp + 804 lora_fsm: + 805 .LFB104: + 603:./Middlewares/Third_Party/Lora/Core/lora.c **** + 604:./Middlewares/Third_Party/Lora/Core/lora.c **** /** + 605:./Middlewares/Third_Party/Lora/Core/lora.c **** * lora class A state machine + 606:./Middlewares/Third_Party/Lora/Core/lora.c **** */ + 607:./Middlewares/Third_Party/Lora/Core/lora.c **** + 608:./Middlewares/Third_Party/Lora/Core/lora.c **** void lora_fsm( void) + 609:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 806 .loc 1 609 0 + 807 .cfi_startproc + 808 @ args = 0, pretend = 0, frame = 24 + 809 @ frame_needed = 0, uses_anonymous_args = 0 + 810 0000 30B5 push {r4, r5, lr} + 811 .LCFI6: + 812 .cfi_def_cfa_offset 12 + 813 .cfi_offset 4, -12 + 814 .cfi_offset 5, -8 + 815 .cfi_offset 14, -4 + 816 0002 87B0 sub sp, sp, #28 + 817 .LCFI7: + 818 .cfi_def_cfa_offset 40 + 610:./Middlewares/Third_Party/Lora/Core/lora.c **** switch( DeviceState ) + 819 .loc 1 610 0 + 820 0004 7E4B ldr r3, .L82 + 821 0006 1A78 ldrb r2, [r3] + 822 0008 052A cmp r2, #5 + 823 000a 00D9 bls .LCB684 + 824 000c F4E0 b .L55 @long jump + 825 .LCB684: + 826 000e 9300 lsls r3, r2, #2 + 827 0010 7C4A ldr r2, .L82+4 + 828 0012 D358 ldr r3, [r2, r3] + 829 0014 9F46 mov pc, r3 + 830 .section .rodata.lora_fsm,"a",%progbits + 831 .align 2 + 832 .L57: + 833 0000 16000000 .word .L56 + 834 0004 80000000 .word .L58 + 835 0008 B2000000 .word .L59 + 836 000c C0000000 .word .L60 + ARM GAS /tmp/ccY05lmV.s page 28 + + + 837 0010 F8010000 .word .L55 + 838 0014 7C000000 .word .L54 + 839 .section .text.lora_fsm + 840 .L56: + 611:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 612:./Middlewares/Third_Party/Lora/Core/lora.c **** case DEVICE_STATE_INIT: + 613:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 614:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacPrimitives.MacMcpsConfirm = McpsConfirm; + 841 .loc 1 614 0 + 842 0016 7C48 ldr r0, .L82+8 + 843 0018 7C4B ldr r3, .L82+12 + 844 001a 0360 str r3, [r0] + 615:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacPrimitives.MacMcpsIndication = McpsIndication; + 845 .loc 1 615 0 + 846 001c 7C4B ldr r3, .L82+16 + 847 001e 4360 str r3, [r0, #4] + 616:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacPrimitives.MacMlmeConfirm = MlmeConfirm; + 848 .loc 1 616 0 + 849 0020 7C4B ldr r3, .L82+20 + 850 0022 8360 str r3, [r0, #8] + 617:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacCallbacks.GetBatteryLevel = LoRaMainCallbacks->BoardGetBatteryLevel; + 851 .loc 1 617 0 + 852 0024 7C4B ldr r3, .L82+24 + 853 0026 1B68 ldr r3, [r3] + 854 0028 1B68 ldr r3, [r3] + 855 002a 7C49 ldr r1, .L82+28 + 856 002c 0B60 str r3, [r1] + 618:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_AS923 ) + 619:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_AS923 + 620:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_AU915 ) + 621:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_AU915 + 622:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_CN470 ) + 623:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_CN470 + 624:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_CN779 ) + 625:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_CN779 + 626:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_EU433 ) + 627:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_EU433 + 628:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_IN865 ) + 629:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_IN865 + 630:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_EU868 ) + 631:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_EU868 + 857 .loc 1 631 0 + 858 002e 0522 movs r2, #5 + 859 0030 FFF7FEFF bl LoRaMacInitialization + 860 .LVL59: + 632:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_KR920 ) + 633:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_KR920 + 634:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_US915 ) + 635:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_US915 + 636:./Middlewares/Third_Party/Lora/Core/lora.c **** #elif defined( REGION_US915_HYBRID ) + 637:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacInitialization( &LoRaMacPrimitives, &LoRaMacCallbacks, LORAMAC_REGION_US915_ + 638:./Middlewares/Third_Party/Lora/Core/lora.c **** #else + 639:./Middlewares/Third_Party/Lora/Core/lora.c **** #error "Please define a region in the compiler options." + 640:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 641:./Middlewares/Third_Party/Lora/Core/lora.c **** + 642:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerInit( &TxNextPacketTimer, OnTxNextPacketTimerEvent ); + 861 .loc 1 642 0 + ARM GAS /tmp/ccY05lmV.s page 29 + + + 862 0034 7A49 ldr r1, .L82+32 + 863 0036 7B48 ldr r0, .L82+36 + 864 0038 FFF7FEFF bl TimerInit + 865 .LVL60: + 643:./Middlewares/Third_Party/Lora/Core/lora.c **** + 644:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_ADR; + 866 .loc 1 644 0 + 867 003c 7A4C ldr r4, .L82+40 + 868 003e 0223 movs r3, #2 + 869 0040 2370 strb r3, [r4] + 645:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.AdrEnable = LoRaParamInit->AdrEnable; + 870 .loc 1 645 0 + 871 0042 7A4D ldr r5, .L82+44 + 872 0044 2B68 ldr r3, [r5] + 873 0046 5B7A ldrb r3, [r3, #9] + 874 0048 2371 strb r3, [r4, #4] + 646:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 875 .loc 1 646 0 + 876 004a 2000 movs r0, r4 + 877 004c FFF7FEFF bl LoRaMacMibSetRequestConfirm + 878 .LVL61: + 647:./Middlewares/Third_Party/Lora/Core/lora.c **** + 648:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_PUBLIC_NETWORK; + 879 .loc 1 648 0 + 880 0050 0723 movs r3, #7 + 881 0052 2370 strb r3, [r4] + 649:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.EnablePublicNetwork = LoRaParamInit->EnablePublicNetwork; + 882 .loc 1 649 0 + 883 0054 2B68 ldr r3, [r5] + 884 0056 DB7A ldrb r3, [r3, #11] + 885 0058 2371 strb r3, [r4, #4] + 650:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 886 .loc 1 650 0 + 887 005a 2000 movs r0, r4 + 888 005c FFF7FEFF bl LoRaMacMibSetRequestConfirm + 889 .LVL62: + 651:./Middlewares/Third_Party/Lora/Core/lora.c **** + 652:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_DEVICE_CLASS; + 890 .loc 1 652 0 + 891 0060 0023 movs r3, #0 + 892 0062 2370 strb r3, [r4] + 653:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.Class= LoRaParamInit->Class; + 893 .loc 1 653 0 + 894 0064 2B68 ldr r3, [r5] + 895 0066 1B7A ldrb r3, [r3, #8] + 896 0068 2371 strb r3, [r4, #4] + 654:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 897 .loc 1 654 0 + 898 006a 2000 movs r0, r4 + 899 006c FFF7FEFF bl LoRaMacMibSetRequestConfirm + 900 .LVL63: + 655:./Middlewares/Third_Party/Lora/Core/lora.c **** + 656:./Middlewares/Third_Party/Lora/Core/lora.c **** #if defined( REGION_EU868 ) + 657:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacTestSetDutyCycleOn( LORAWAN_DUTYCYCLE_ON ); + 901 .loc 1 657 0 + 902 0070 0120 movs r0, #1 + 903 0072 FFF7FEFF bl LoRaMacTestSetDutyCycleOn + ARM GAS /tmp/ccY05lmV.s page 30 + + + 904 .LVL64: + 658:./Middlewares/Third_Party/Lora/Core/lora.c **** + 659:./Middlewares/Third_Party/Lora/Core/lora.c **** #if( USE_SEMTECH_DEFAULT_CHANNEL_LINEUP == 1 ) + 660:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 3, ( ChannelParams_t )LC4 ); + 661:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 4, ( ChannelParams_t )LC5 ); + 662:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 5, ( ChannelParams_t )LC6 ); + 663:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 6, ( ChannelParams_t )LC7 ); + 664:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 7, ( ChannelParams_t )LC8 ); + 665:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 8, ( ChannelParams_t )LC9 ); + 666:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacChannelAdd( 9, ( ChannelParams_t )LC10 ); + 667:./Middlewares/Third_Party/Lora/Core/lora.c **** + 668:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_RX2_DEFAULT_CHANNEL; + 669:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.Rx2DefaultChannel = ( Rx2ChannelParams_t ){ 869525000, DR_3 }; + 670:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 671:./Middlewares/Third_Party/Lora/Core/lora.c **** + 672:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_RX2_CHANNEL; + 673:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.Rx2Channel = ( Rx2ChannelParams_t ){ 869525000, DR_3 }; + 674:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 675:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 676:./Middlewares/Third_Party/Lora/Core/lora.c **** + 677:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 678:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_JOIN; + 905 .loc 1 678 0 + 906 0076 624B ldr r3, .L82 + 907 0078 0122 movs r2, #1 + 908 007a 1A70 strb r2, [r3] + 909 .L54: + 679:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 680:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 681:./Middlewares/Third_Party/Lora/Core/lora.c **** case DEVICE_STATE_JOIN: + 682:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 683:./Middlewares/Third_Party/Lora/Core/lora.c **** #if( OVER_THE_AIR_ACTIVATION != 0 ) + 684:./Middlewares/Third_Party/Lora/Core/lora.c **** MlmeReq_t mlmeReq; + 685:./Middlewares/Third_Party/Lora/Core/lora.c **** + 686:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Type = MLME_JOIN; + 687:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.DevEui = DevEui; + 688:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppEui = AppEui; + 689:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppKey = AppKey; + 690:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.NbTrials = LoRaParamInit->NbTrials; + 691:./Middlewares/Third_Party/Lora/Core/lora.c **** + 692:./Middlewares/Third_Party/Lora/Core/lora.c **** if( NextTx == true ) + 693:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 694:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMlmeRequest( &mlmeReq ); + 695:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 696:./Middlewares/Third_Party/Lora/Core/lora.c **** + 697:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SLEEP; + 698:./Middlewares/Third_Party/Lora/Core/lora.c **** #else + 699:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_NET_ID; + 700:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.NetID = LORAWAN_NETWORK_ID; + 701:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 702:./Middlewares/Third_Party/Lora/Core/lora.c **** + 703:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_DEV_ADDR; + 704:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.DevAddr = DevAddr; + 705:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 706:./Middlewares/Third_Party/Lora/Core/lora.c **** + 707:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_NWK_SKEY; + 708:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.NwkSKey = NwkSKey; + ARM GAS /tmp/ccY05lmV.s page 31 + + + 709:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 710:./Middlewares/Third_Party/Lora/Core/lora.c **** + 711:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_APP_SKEY; + 712:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.AppSKey = AppSKey; + 713:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 714:./Middlewares/Third_Party/Lora/Core/lora.c **** + 715:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Type = MIB_NETWORK_JOINED; + 716:./Middlewares/Third_Party/Lora/Core/lora.c **** mibReq.Param.IsNetworkJoined = true; + 717:./Middlewares/Third_Party/Lora/Core/lora.c **** LoRaMacMibSetRequestConfirm( &mibReq ); + 718:./Middlewares/Third_Party/Lora/Core/lora.c **** + 719:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SEND; + 720:./Middlewares/Third_Party/Lora/Core/lora.c **** #endif + 721:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 722:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 723:./Middlewares/Third_Party/Lora/Core/lora.c **** case DEVICE_STATE_JOINED: + 724:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 725:./Middlewares/Third_Party/Lora/Core/lora.c **** PRINTF("JOINED\n\r"); + 726:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SEND; + 727:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 728:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 729:./Middlewares/Third_Party/Lora/Core/lora.c **** case DEVICE_STATE_SEND: + 730:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 731:./Middlewares/Third_Party/Lora/Core/lora.c **** if( NextTx == true ) + 732:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 733:./Middlewares/Third_Party/Lora/Core/lora.c **** PrepareTxFrame( ); + 734:./Middlewares/Third_Party/Lora/Core/lora.c **** + 735:./Middlewares/Third_Party/Lora/Core/lora.c **** NextTx = SendFrame( ); + 736:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 737:./Middlewares/Third_Party/Lora/Core/lora.c **** if( ComplianceTest.Running == true ) + 738:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 739:./Middlewares/Third_Party/Lora/Core/lora.c **** // Schedule next packet transmission as soon as possible + 740:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerSetValue( &TxNextPacketTimer, 5000); /* 5s */ + 741:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStart( &TxNextPacketTimer ); + 742:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 743:./Middlewares/Third_Party/Lora/Core/lora.c **** else if (LoRaParamInit->TxEvent == TX_ON_TIMER ) + 744:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 745:./Middlewares/Third_Party/Lora/Core/lora.c **** // Schedule next packet transmission + 746:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerSetValue( &TxNextPacketTimer, LoRaParamInit->TxDutyCycleTime ); + 747:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStart( &TxNextPacketTimer ); + 748:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 749:./Middlewares/Third_Party/Lora/Core/lora.c **** + 750:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SLEEP; + 751:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 752:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 753:./Middlewares/Third_Party/Lora/Core/lora.c **** case DEVICE_STATE_SLEEP: + 754:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 755:./Middlewares/Third_Party/Lora/Core/lora.c **** // Wake up through events + 756:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 757:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 758:./Middlewares/Third_Party/Lora/Core/lora.c **** default: + 759:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 760:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_INIT; + 761:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 762:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 763:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 764:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 910 .loc 1 764 0 + ARM GAS /tmp/ccY05lmV.s page 32 + + + 911 007c 07B0 add sp, sp, #28 + 912 @ sp needed + 913 007e 30BD pop {r4, r5, pc} + 914 .L58: + 915 .LBB17: + 686:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.DevEui = DevEui; + 916 .loc 1 686 0 + 917 0080 01AB add r3, sp, #4 + 918 0082 0022 movs r2, #0 + 919 0084 1A70 strb r2, [r3] + 687:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppEui = AppEui; + 920 .loc 1 687 0 + 921 0086 6A4A ldr r2, .L82+48 + 922 0088 0292 str r2, [sp, #8] + 688:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.AppKey = AppKey; + 923 .loc 1 688 0 + 924 008a 6A4A ldr r2, .L82+52 + 925 008c 0392 str r2, [sp, #12] + 689:./Middlewares/Third_Party/Lora/Core/lora.c **** mlmeReq.Req.Join.NbTrials = LoRaParamInit->NbTrials; + 926 .loc 1 689 0 + 927 008e 6A4A ldr r2, .L82+56 + 928 0090 0492 str r2, [sp, #16] + 690:./Middlewares/Third_Party/Lora/Core/lora.c **** + 929 .loc 1 690 0 + 930 0092 664A ldr r2, .L82+44 + 931 0094 1268 ldr r2, [r2] + 932 0096 127B ldrb r2, [r2, #12] + 933 0098 1A74 strb r2, [r3, #16] + 692:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 934 .loc 1 692 0 + 935 009a 684B ldr r3, .L82+60 + 936 009c 1B78 ldrb r3, [r3] + 937 009e 002B cmp r3, #0 + 938 00a0 03D1 bne .L75 + 939 .L62: + 697:./Middlewares/Third_Party/Lora/Core/lora.c **** #else + 940 .loc 1 697 0 + 941 00a2 574B ldr r3, .L82 + 942 00a4 0522 movs r2, #5 + 943 00a6 1A70 strb r2, [r3] + 944 00a8 E8E7 b .L54 + 945 .L75: + 694:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 946 .loc 1 694 0 + 947 00aa 01A8 add r0, sp, #4 + 948 00ac FFF7FEFF bl LoRaMacMlmeRequest + 949 .LVL65: + 950 00b0 F7E7 b .L62 + 951 .L59: + 952 .LBE17: + 725:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState = DEVICE_STATE_SEND; + 953 .loc 1 725 0 + 954 00b2 6348 ldr r0, .L82+64 + 955 00b4 FFF7FEFF bl vcom_Send + 956 .LVL66: + 726:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 957 .loc 1 726 0 + ARM GAS /tmp/ccY05lmV.s page 33 + + + 958 00b8 514B ldr r3, .L82 + 959 00ba 0322 movs r2, #3 + 960 00bc 1A70 strb r2, [r3] + 727:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 961 .loc 1 727 0 + 962 00be DDE7 b .L54 + 963 .L60: + 731:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 964 .loc 1 731 0 + 965 00c0 5E4B ldr r3, .L82+60 + 966 00c2 1C78 ldrb r4, [r3] + 967 00c4 002C cmp r4, #0 + 968 00c6 0ED1 bne .L76 + 969 .L63: + 737:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 970 .loc 1 737 0 + 971 00c8 5E4B ldr r3, .L82+68 + 972 00ca 1B78 ldrb r3, [r3] + 973 00cc 002B cmp r3, #0 + 974 00ce 00D0 beq .LCB813 + 975 00d0 80E0 b .L77 @long jump + 976 .LCB813: + 743:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 977 .loc 1 743 0 + 978 00d2 564B ldr r3, .L82+44 + 979 00d4 1B68 ldr r3, [r3] + 980 00d6 1A78 ldrb r2, [r3] + 981 00d8 002A cmp r2, #0 + 982 00da 00D1 bne .LCB818 + 983 00dc 83E0 b .L78 @long jump + 984 .LCB818: + 985 .L74: + 750:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 986 .loc 1 750 0 + 987 00de 484B ldr r3, .L82 + 988 00e0 0522 movs r2, #5 + 989 00e2 1A70 strb r2, [r3] + 751:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 990 .loc 1 751 0 + 991 00e4 CAE7 b .L54 + 992 .L76: + 993 .LBB18: + 994 .LBB19: + 184:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 995 .loc 1 184 0 + 996 00e6 574B ldr r3, .L82+68 + 997 00e8 1B78 ldrb r3, [r3] + 998 00ea 002B cmp r3, #0 + 999 00ec 1ED1 bne .L79 + 212:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1000 .loc 1 212 0 + 1001 00ee 4A4B ldr r3, .L82+24 + 1002 00f0 1B68 ldr r3, [r3] + 1003 00f2 DB68 ldr r3, [r3, #12] + 1004 00f4 5449 ldr r1, .L82+72 + 1005 00f6 5548 ldr r0, .L82+76 + 1006 00f8 9847 blx r3 + ARM GAS /tmp/ccY05lmV.s page 34 + + + 1007 .LVL67: + 1008 .L66: + 1009 .LBE19: + 1010 .LBE18: + 1011 .LBB21: + 1012 .LBB22: + 226:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1013 .loc 1 226 0 + 1014 00fa 544B ldr r3, .L82+76 + 1015 00fc 1879 ldrb r0, [r3, #4] + 1016 00fe 6946 mov r1, sp + 1017 0100 FFF7FEFF bl LoRaMacQueryTxPossible + 1018 .LVL68: + 1019 0104 0028 cmp r0, #0 + 1020 0106 3DD0 beq .L69 + 229:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBuffer = NULL; + 1021 .loc 1 229 0 + 1022 0108 01AB add r3, sp, #4 + 1023 010a 0022 movs r2, #0 + 1024 010c 1A70 strb r2, [r3] + 230:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBufferSize = 0; + 1025 .loc 1 230 0 + 1026 010e 0392 str r2, [sp, #12] + 231:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.Datarate = LoRaParamInit->TxDatarate; + 1027 .loc 1 231 0 + 1028 0110 9A81 strh r2, [r3, #12] + 232:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1029 .loc 1 232 0 + 1030 0112 464A ldr r2, .L82+44 + 1031 0114 1268 ldr r2, [r2] + 1032 0116 927A ldrb r2, [r2, #10] + 1033 0118 52B2 sxtb r2, r2 + 1034 011a 9A73 strb r2, [r3, #14] + 1035 .L70: + 254:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1036 .loc 1 254 0 + 1037 011c 01A8 add r0, sp, #4 + 1038 011e FFF7FEFF bl LoRaMacMcpsRequest + 1039 .LVL69: + 1040 0122 0028 cmp r0, #0 + 1041 0124 54D0 beq .L80 + 1042 .L72: + 1043 .LBE22: + 1044 .LBE21: + 735:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1045 .loc 1 735 0 + 1046 0126 454B ldr r3, .L82+60 + 1047 0128 1C70 strb r4, [r3] + 1048 012a CDE7 b .L63 + 1049 .L79: + 1050 .LBB24: + 1051 .LBB20: + 186:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1052 .loc 1 186 0 + 1053 012c 454B ldr r3, .L82+68 + 1054 012e 9B7B ldrb r3, [r3, #14] + 1055 0130 002B cmp r3, #0 + ARM GAS /tmp/ccY05lmV.s page 35 + + + 1056 0132 09D1 bne .L81 + 197:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1057 .loc 1 197 0 + 1058 0134 434B ldr r3, .L82+68 + 1059 0136 5B78 ldrb r3, [r3, #1] + 1060 0138 012B cmp r3, #1 + 1061 013a 17D0 beq .L67 + 1062 013c 042B cmp r3, #4 + 1063 013e DCD1 bne .L66 + 200:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 1064 .loc 1 200 0 + 1065 0140 404B ldr r3, .L82+68 + 1066 0142 0122 movs r2, #1 + 1067 0144 5A70 strb r2, [r3, #1] + 1068 0146 D8E7 b .L66 + 1069 .L81: + 188:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.BuffSize = 3; + 1070 .loc 1 188 0 + 1071 0148 3E4B ldr r3, .L82+68 + 1072 014a 0022 movs r2, #0 + 1073 014c 9A73 strb r2, [r3, #14] + 189:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[0] = 5; + 1074 .loc 1 189 0 + 1075 014e 3F4A ldr r2, .L82+76 + 1076 0150 0321 movs r1, #3 + 1077 0152 1171 strb r1, [r2, #4] + 190:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[1] = ComplianceTest.DemodMargin; + 1078 .loc 1 190 0 + 1079 0154 0231 adds r1, r1, #2 + 1080 0156 1068 ldr r0, [r2] + 1081 0158 0170 strb r1, [r0] + 191:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[2] = ComplianceTest.NbGateways; + 1082 .loc 1 191 0 + 1083 015a D97B ldrb r1, [r3, #15] + 1084 015c 1068 ldr r0, [r2] + 1085 015e 4170 strb r1, [r0, #1] + 192:./Middlewares/Third_Party/Lora/Core/lora.c **** ComplianceTest.State = 1; + 1086 .loc 1 192 0 + 1087 0160 1268 ldr r2, [r2] + 1088 0162 197C ldrb r1, [r3, #16] + 1089 0164 9170 strb r1, [r2, #2] + 193:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1090 .loc 1 193 0 + 1091 0166 0122 movs r2, #1 + 1092 0168 5A70 strb r2, [r3, #1] + 1093 016a C6E7 b .L66 + 1094 .L67: + 203:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[0] = ComplianceTest.DownLinkCounter >> 8; + 1095 .loc 1 203 0 + 1096 016c 374B ldr r3, .L82+76 + 1097 016e 0222 movs r2, #2 + 1098 0170 1A71 strb r2, [r3, #4] + 204:./Middlewares/Third_Party/Lora/Core/lora.c **** AppData.Buff[1] = ComplianceTest.DownLinkCounter; + 1099 .loc 1 204 0 + 1100 0172 3449 ldr r1, .L82+68 + 1101 0174 8A89 ldrh r2, [r1, #12] + 1102 0176 120A lsrs r2, r2, #8 + ARM GAS /tmp/ccY05lmV.s page 36 + + + 1103 0178 1868 ldr r0, [r3] + 1104 017a 0270 strb r2, [r0] + 205:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 1105 .loc 1 205 0 + 1106 017c 8A89 ldrh r2, [r1, #12] + 1107 017e 1B68 ldr r3, [r3] + 1108 0180 5A70 strb r2, [r3, #1] + 1109 0182 BAE7 b .L66 + 1110 .L69: + 1111 .LBE20: + 1112 .LBE24: + 1113 .LBB25: + 1114 .LBB23: + 236:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1115 .loc 1 236 0 + 1116 0184 304B ldr r3, .L82+72 + 1117 0186 1B78 ldrb r3, [r3] + 1118 0188 002B cmp r3, #0 + 1119 018a 0FD1 bne .L71 + 238:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fPort = AppData.Port; + 1120 .loc 1 238 0 + 1121 018c 01AB add r3, sp, #4 + 1122 018e 0022 movs r2, #0 + 1123 0190 1A70 strb r2, [r3] + 239:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBuffer = AppData.Buff; + 1124 .loc 1 239 0 + 1125 0192 2E4A ldr r2, .L82+76 + 1126 0194 5179 ldrb r1, [r2, #5] + 1127 0196 1971 strb r1, [r3, #4] + 240:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.fBufferSize = AppData.BuffSize; + 1128 .loc 1 240 0 + 1129 0198 1168 ldr r1, [r2] + 1130 019a 0391 str r1, [sp, #12] + 241:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Unconfirmed.Datarate = LoRaParamInit->TxDatarate; + 1131 .loc 1 241 0 + 1132 019c 1279 ldrb r2, [r2, #4] + 1133 019e 9A81 strh r2, [r3, #12] + 242:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1134 .loc 1 242 0 + 1135 01a0 224A ldr r2, .L82+44 + 1136 01a2 1268 ldr r2, [r2] + 1137 01a4 927A ldrb r2, [r2, #10] + 1138 01a6 52B2 sxtb r2, r2 + 1139 01a8 9A73 strb r2, [r3, #14] + 1140 01aa B7E7 b .L70 + 1141 .L71: + 246:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fPort = AppData.Port; + 1142 .loc 1 246 0 + 1143 01ac 01AB add r3, sp, #4 + 1144 01ae 0122 movs r2, #1 + 1145 01b0 1A70 strb r2, [r3] + 247:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fBuffer = AppData.Buff; + 1146 .loc 1 247 0 + 1147 01b2 264A ldr r2, .L82+76 + 1148 01b4 5179 ldrb r1, [r2, #5] + 1149 01b6 1971 strb r1, [r3, #4] + 248:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.fBufferSize = AppData.BuffSize; + ARM GAS /tmp/ccY05lmV.s page 37 + + + 1150 .loc 1 248 0 + 1151 01b8 1168 ldr r1, [r2] + 1152 01ba 0391 str r1, [sp, #12] + 249:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.NbTrials = 8; + 1153 .loc 1 249 0 + 1154 01bc 1279 ldrb r2, [r2, #4] + 1155 01be 9A81 strh r2, [r3, #12] + 250:./Middlewares/Third_Party/Lora/Core/lora.c **** mcpsReq.Req.Confirmed.Datarate = LoRaParamInit->TxDatarate; + 1156 .loc 1 250 0 + 1157 01c0 0822 movs r2, #8 + 1158 01c2 DA73 strb r2, [r3, #15] + 251:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1159 .loc 1 251 0 + 1160 01c4 194A ldr r2, .L82+44 + 1161 01c6 1268 ldr r2, [r2] + 1162 01c8 927A ldrb r2, [r2, #10] + 1163 01ca 52B2 sxtb r2, r2 + 1164 01cc 9A73 strb r2, [r3, #14] + 1165 01ce A5E7 b .L70 + 1166 .L80: + 256:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1167 .loc 1 256 0 + 1168 01d0 0024 movs r4, #0 + 1169 01d2 A8E7 b .L72 + 1170 .L77: + 1171 .LBE23: + 1172 .LBE25: + 740:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStart( &TxNextPacketTimer ); + 1173 .loc 1 740 0 + 1174 01d4 134C ldr r4, .L82+36 + 1175 01d6 1E49 ldr r1, .L82+80 + 1176 01d8 2000 movs r0, r4 + 1177 01da FFF7FEFF bl TimerSetValue + 1178 .LVL70: + 741:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1179 .loc 1 741 0 + 1180 01de 2000 movs r0, r4 + 1181 01e0 FFF7FEFF bl TimerStart + 1182 .LVL71: + 1183 01e4 7BE7 b .L74 + 1184 .L78: + 746:./Middlewares/Third_Party/Lora/Core/lora.c **** TimerStart( &TxNextPacketTimer ); + 1185 .loc 1 746 0 + 1186 01e6 5968 ldr r1, [r3, #4] + 1187 01e8 0E4C ldr r4, .L82+36 + 1188 01ea 2000 movs r0, r4 + 1189 01ec FFF7FEFF bl TimerSetValue + 1190 .LVL72: + 747:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1191 .loc 1 747 0 + 1192 01f0 2000 movs r0, r4 + 1193 01f2 FFF7FEFF bl TimerStart + 1194 .LVL73: + 1195 01f6 72E7 b .L74 + 1196 .L55: + 760:./Middlewares/Third_Party/Lora/Core/lora.c **** break; + 1197 .loc 1 760 0 + ARM GAS /tmp/ccY05lmV.s page 38 + + + 1198 01f8 014B ldr r3, .L82 + 1199 01fa 0022 movs r2, #0 + 1200 01fc 1A70 strb r2, [r3] + 1201 .loc 1 764 0 + 1202 01fe 3DE7 b .L54 + 1203 .L83: + 1204 .align 2 + 1205 .L82: + 1206 0200 00000000 .word .LANCHOR1 + 1207 0204 00000000 .word .L57 + 1208 0208 00000000 .word .LANCHOR11 + 1209 020c 00000000 .word McpsConfirm + 1210 0210 00000000 .word McpsIndication + 1211 0214 00000000 .word MlmeConfirm + 1212 0218 00000000 .word .LANCHOR9 + 1213 021c 00000000 .word .LANCHOR12 + 1214 0220 00000000 .word OnTxNextPacketTimerEvent + 1215 0224 00000000 .word .LANCHOR10 + 1216 0228 00000000 .word .LANCHOR13 + 1217 022c 00000000 .word .LANCHOR5 + 1218 0230 00000000 .word .LANCHOR6 + 1219 0234 00000000 .word .LANCHOR7 + 1220 0238 00000000 .word .LANCHOR8 + 1221 023c 00000000 .word .LANCHOR0 + 1222 0240 00000000 .word .LC55 + 1223 0244 00000000 .word .LANCHOR2 + 1224 0248 00000000 .word .LANCHOR3 + 1225 024c 00000000 .word .LANCHOR4 + 1226 0250 88130000 .word 5000 + 1227 .cfi_endproc + 1228 .LFE104: + 1230 .section .text.lora_getDeviceState,"ax",%progbits + 1231 .align 1 + 1232 .global lora_getDeviceState + 1233 .syntax unified + 1234 .code 16 + 1235 .thumb_func + 1236 .fpu softvfp + 1238 lora_getDeviceState: + 1239 .LFB105: + 765:./Middlewares/Third_Party/Lora/Core/lora.c **** + 766:./Middlewares/Third_Party/Lora/Core/lora.c **** + 767:./Middlewares/Third_Party/Lora/Core/lora.c **** DeviceState_t lora_getDeviceState( void ) + 768:./Middlewares/Third_Party/Lora/Core/lora.c **** { + 1240 .loc 1 768 0 + 1241 .cfi_startproc + 1242 @ args = 0, pretend = 0, frame = 0 + 1243 @ frame_needed = 0, uses_anonymous_args = 0 + 1244 @ link register save eliminated. + 769:./Middlewares/Third_Party/Lora/Core/lora.c **** return DeviceState; + 1245 .loc 1 769 0 + 1246 0000 014B ldr r3, .L85 + 1247 0002 1878 ldrb r0, [r3] + 770:./Middlewares/Third_Party/Lora/Core/lora.c **** } + 1248 .loc 1 770 0 + 1249 @ sp needed + 1250 0004 7047 bx lr + ARM GAS /tmp/ccY05lmV.s page 39 + + + 1251 .L86: + 1252 0006 C046 .align 2 + 1253 .L85: + 1254 0008 00000000 .word .LANCHOR1 + 1255 .cfi_endproc + 1256 .LFE105: + 1258 .global ComplianceTest + 1259 .section .bss.AppDataBuff,"aw",%nobits + 1260 .align 2 + 1263 AppDataBuff: + 1264 0000 00000000 .space 64 + 1264 00000000 + 1264 00000000 + 1264 00000000 + 1264 00000000 + 1265 .section .bss.ComplianceTest,"aw",%nobits + 1266 .align 2 + 1267 .set .LANCHOR2,. + 0 + 1270 ComplianceTest: + 1271 0000 00000000 .space 20 + 1271 00000000 + 1271 00000000 + 1271 00000000 + 1271 00000000 + 1272 .section .bss.DeviceState,"aw",%nobits + 1273 .set .LANCHOR1,. + 0 + 1276 DeviceState: + 1277 0000 00 .space 1 + 1278 .section .bss.IsTxConfirmed,"aw",%nobits + 1279 .set .LANCHOR3,. + 0 + 1282 IsTxConfirmed: + 1283 0000 00 .space 1 + 1284 .section .bss.LoRaMacCallbacks,"aw",%nobits + 1285 .align 2 + 1286 .set .LANCHOR12,. + 0 + 1289 LoRaMacCallbacks: + 1290 0000 00000000 .space 4 + 1291 .section .bss.LoRaMacPrimitives,"aw",%nobits + 1292 .align 2 + 1293 .set .LANCHOR11,. + 0 + 1296 LoRaMacPrimitives: + 1297 0000 00000000 .space 12 + 1297 00000000 + 1297 00000000 + 1298 .section .bss.LoRaMainCallbacks,"aw",%nobits + 1299 .align 2 + 1300 .set .LANCHOR9,. + 0 + 1303 LoRaMainCallbacks: + 1304 0000 00000000 .space 4 + 1305 .section .bss.LoRaParamInit,"aw",%nobits + 1306 .align 2 + 1307 .set .LANCHOR5,. + 0 + 1310 LoRaParamInit: + 1311 0000 00000000 .space 4 + 1312 .section .bss.TxNextPacketTimer,"aw",%nobits + 1313 .align 2 + 1314 .set .LANCHOR10,. + 0 + ARM GAS /tmp/ccY05lmV.s page 40 + + + 1317 TxNextPacketTimer: + 1318 0000 00000000 .space 20 + 1318 00000000 + 1318 00000000 + 1318 00000000 + 1318 00000000 + 1319 .section .bss.mibReq,"aw",%nobits + 1320 .align 2 + 1321 .set .LANCHOR13,. + 0 + 1324 mibReq: + 1325 0000 00000000 .space 12 + 1325 00000000 + 1325 00000000 + 1326 .section .data.AppData,"aw",%progbits + 1327 .align 2 + 1328 .set .LANCHOR4,. + 0 + 1331 AppData: + 1332 0000 00000000 .word AppDataBuff + 1333 0004 00 .byte 0 + 1334 0005 00 .byte 0 + 1335 0006 0000 .space 2 + 1336 .section .data.AppEui,"aw",%progbits + 1337 .align 2 + 1338 .set .LANCHOR7,. + 0 + 1341 AppEui: + 1342 0000 70 .byte 112 + 1343 0001 B3 .byte -77 + 1344 0002 D5 .byte -43 + 1345 0003 7E .byte 126 + 1346 0004 D0 .byte -48 + 1347 0005 00 .byte 0 + 1348 0006 7C .byte 124 + 1349 0007 04 .byte 4 + 1350 .section .data.AppKey,"aw",%progbits + 1351 .align 2 + 1352 .set .LANCHOR8,. + 0 + 1355 AppKey: + 1356 0000 4F .byte 79 + 1357 0001 13 .byte 19 + 1358 0002 EF .byte -17 + 1359 0003 E5 .byte -27 + 1360 0004 D9 .byte -39 + 1361 0005 A9 .byte -87 + 1362 0006 44 .byte 68 + 1363 0007 93 .byte -109 + 1364 0008 99 .byte -103 + 1365 0009 25 .byte 37 + 1366 000a D2 .byte -46 + 1367 000b D9 .byte -39 + 1368 000c 79 .byte 121 + 1369 000d 77 .byte 119 + 1370 000e 91 .byte -111 + 1371 000f DC .byte -36 + 1372 .section .data.DevEui,"aw",%progbits + 1373 .align 2 + 1374 .set .LANCHOR6,. + 0 + 1377 DevEui: + ARM GAS /tmp/ccY05lmV.s page 41 + + + 1378 0000 01 .byte 1 + 1379 0001 01 .byte 1 + 1380 0002 01 .byte 1 + 1381 0003 01 .byte 1 + 1382 0004 01 .byte 1 + 1383 0005 01 .byte 1 + 1384 0006 01 .byte 1 + 1385 0007 01 .byte 1 + 1386 .section .data.NextTx,"aw",%progbits + 1387 .set .LANCHOR0,. + 0 + 1390 NextTx: + 1391 0000 01 .byte 1 + 1392 .section .rodata.lora_Init.str1.4,"aMS",%progbits,1 + 1393 .align 2 + 1394 .LC21: + 1395 0000 4F544141 .ascii "OTAA\012\015\000" + 1395 0A0D00 + 1396 0007 00 .space 1 + 1397 .LC23: + 1398 0008 44657645 .ascii "DevEui= %02X\000" + 1398 75693D20 + 1398 25303258 + 1398 00 + 1399 0015 000000 .space 3 + 1400 .LC25: + 1401 0018 2D253032 .ascii "-%02X\000" + 1401 5800 + 1402 001e 0000 .space 2 + 1403 .LC27: + 1404 0020 0A0D00 .ascii "\012\015\000" + 1405 0023 00 .space 1 + 1406 .LC30: + 1407 0024 41707045 .ascii "AppEui= %02X\000" + 1407 75693D20 + 1407 25303258 + 1407 00 + 1408 0031 000000 .space 3 + 1409 .LC33: + 1410 0034 4170704B .ascii "AppKey= %02X\000" + 1410 65793D20 + 1410 25303258 + 1410 00 + 1411 0041 000000 .space 3 + 1412 .LC35: + 1413 0044 20253032 .ascii " %02X\000" + 1413 5800 + 1414 004a 0000 .space 2 + 1415 .LC37: + 1416 004c 0A0A0D00 .ascii "\012\012\015\000" + 1417 .section .rodata.lora_fsm.str1.4,"aMS",%progbits,1 + 1418 .align 2 + 1419 .LC55: + 1420 0000 4A4F494E .ascii "JOINED\012\015\000" + 1420 45440A0D + 1420 00 + 1421 .text + 1422 .Letext0: + ARM GAS /tmp/ccY05lmV.s page 42 + + + 1423 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1424 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 1425 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 1426 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1427 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 1428 .file 7 "/usr/arm-none-eabi/include/math.h" + 1429 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1430 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1431 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1432 .file 11 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 1433 .file 12 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + 1434 .file 13 "Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 1435 .file 14 "./Middlewares/Third_Party/Lora/Core/lora.h" + 1436 .file 15 "Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h" + 1437 .file 16 "Inc/vcom.h" + ARM GAS /tmp/ccY05lmV.s page 43 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 lora.c + /tmp/ccY05lmV.s:16 .text.McpsConfirm:0000000000000000 $t + /tmp/ccY05lmV.s:22 .text.McpsConfirm:0000000000000000 McpsConfirm + /tmp/ccY05lmV.s:41 .text.McpsConfirm:0000000000000008 $d + /tmp/ccY05lmV.s:46 .text.MlmeConfirm:0000000000000000 $t + /tmp/ccY05lmV.s:52 .text.MlmeConfirm:0000000000000000 MlmeConfirm + /tmp/ccY05lmV.s:114 .text.MlmeConfirm:0000000000000048 $d + /tmp/ccY05lmV.s:121 .text.McpsIndication:0000000000000000 $t + /tmp/ccY05lmV.s:127 .text.McpsIndication:0000000000000000 McpsIndication + /tmp/ccY05lmV.s:267 .rodata.McpsIndication:0000000000000000 $d + /tmp/ccY05lmV.s:535 .text.McpsIndication:00000000000001d4 $d + /tmp/ccY05lmV.s:549 .text.OnSendEvent:0000000000000000 $t + /tmp/ccY05lmV.s:556 .text.OnSendEvent:0000000000000000 OnSendEvent + /tmp/ccY05lmV.s:606 .text.OnSendEvent:0000000000000034 $d + /tmp/ccY05lmV.s:612 .text.OnTxNextPacketTimerEvent:0000000000000000 $t + /tmp/ccY05lmV.s:618 .text.OnTxNextPacketTimerEvent:0000000000000000 OnTxNextPacketTimerEvent + /tmp/ccY05lmV.s:642 .text.OnTxNextPacketTimerEvent:0000000000000010 $d + /tmp/ccY05lmV.s:647 .text.lora_Init:0000000000000000 $t + /tmp/ccY05lmV.s:654 .text.lora_Init:0000000000000000 lora_Init + /tmp/ccY05lmV.s:779 .text.lora_Init:000000000000008c $d + /tmp/ccY05lmV.s:797 .text.lora_fsm:0000000000000000 $t + /tmp/ccY05lmV.s:804 .text.lora_fsm:0000000000000000 lora_fsm + /tmp/ccY05lmV.s:831 .rodata.lora_fsm:0000000000000000 $d + /tmp/ccY05lmV.s:1206 .text.lora_fsm:0000000000000200 $d + /tmp/ccY05lmV.s:1231 .text.lora_getDeviceState:0000000000000000 $t + /tmp/ccY05lmV.s:1238 .text.lora_getDeviceState:0000000000000000 lora_getDeviceState + /tmp/ccY05lmV.s:1254 .text.lora_getDeviceState:0000000000000008 $d + /tmp/ccY05lmV.s:1270 .bss.ComplianceTest:0000000000000000 ComplianceTest + /tmp/ccY05lmV.s:1260 .bss.AppDataBuff:0000000000000000 $d + /tmp/ccY05lmV.s:1263 .bss.AppDataBuff:0000000000000000 AppDataBuff + /tmp/ccY05lmV.s:1266 .bss.ComplianceTest:0000000000000000 $d + /tmp/ccY05lmV.s:1276 .bss.DeviceState:0000000000000000 DeviceState + /tmp/ccY05lmV.s:1277 .bss.DeviceState:0000000000000000 $d + /tmp/ccY05lmV.s:1282 .bss.IsTxConfirmed:0000000000000000 IsTxConfirmed + /tmp/ccY05lmV.s:1283 .bss.IsTxConfirmed:0000000000000000 $d + /tmp/ccY05lmV.s:1285 .bss.LoRaMacCallbacks:0000000000000000 $d + /tmp/ccY05lmV.s:1289 .bss.LoRaMacCallbacks:0000000000000000 LoRaMacCallbacks + /tmp/ccY05lmV.s:1292 .bss.LoRaMacPrimitives:0000000000000000 $d + /tmp/ccY05lmV.s:1296 .bss.LoRaMacPrimitives:0000000000000000 LoRaMacPrimitives + /tmp/ccY05lmV.s:1299 .bss.LoRaMainCallbacks:0000000000000000 $d + /tmp/ccY05lmV.s:1303 .bss.LoRaMainCallbacks:0000000000000000 LoRaMainCallbacks + /tmp/ccY05lmV.s:1306 .bss.LoRaParamInit:0000000000000000 $d + /tmp/ccY05lmV.s:1310 .bss.LoRaParamInit:0000000000000000 LoRaParamInit + /tmp/ccY05lmV.s:1313 .bss.TxNextPacketTimer:0000000000000000 $d + /tmp/ccY05lmV.s:1317 .bss.TxNextPacketTimer:0000000000000000 TxNextPacketTimer + /tmp/ccY05lmV.s:1320 .bss.mibReq:0000000000000000 $d + /tmp/ccY05lmV.s:1324 .bss.mibReq:0000000000000000 mibReq + /tmp/ccY05lmV.s:1327 .data.AppData:0000000000000000 $d + /tmp/ccY05lmV.s:1331 .data.AppData:0000000000000000 AppData + /tmp/ccY05lmV.s:1337 .data.AppEui:0000000000000000 $d + /tmp/ccY05lmV.s:1341 .data.AppEui:0000000000000000 AppEui + /tmp/ccY05lmV.s:1351 .data.AppKey:0000000000000000 $d + /tmp/ccY05lmV.s:1355 .data.AppKey:0000000000000000 AppKey + /tmp/ccY05lmV.s:1373 .data.DevEui:0000000000000000 $d + /tmp/ccY05lmV.s:1377 .data.DevEui:0000000000000000 DevEui + /tmp/ccY05lmV.s:1390 .data.NextTx:0000000000000000 NextTx + ARM GAS /tmp/ccY05lmV.s page 44 + + + /tmp/ccY05lmV.s:1393 .rodata.lora_Init.str1.4:0000000000000000 $d + /tmp/ccY05lmV.s:1418 .rodata.lora_fsm.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +LoRaMacMibSetRequestConfirm +LoRaMacTestSetDutyCycleOn +LoRaMacMlmeRequest +memcpy1 +LoRaMacMibGetRequestConfirm +TimerStop +vcom_Send +LoRaMacInitialization +TimerInit +LoRaMacQueryTxPossible +LoRaMacMcpsRequest +TimerSetValue +TimerStart diff --git a/build/low_power.d b/build/low_power.d new file mode 100644 index 0000000..ff40528 --- /dev/null +++ b/build/low_power.d @@ -0,0 +1,138 @@ +build/low_power.d: Middlewares/Third_Party/Lora/Utilities/low_power.c \ + Inc/hw.h Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/low_power.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/low_power.h: diff --git a/build/low_power.lst b/build/low_power.lst new file mode 100644 index 0000000..7395404 --- /dev/null +++ b/build/low_power.lst @@ -0,0 +1,657 @@ +ARM GAS /tmp/ccBl10G9.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "low_power.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LowPower_Disable,"ax",%progbits + 16 .align 1 + 17 .global LowPower_Disable + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LowPower_Disable: + 24 .LFB96: + 25 .file 1 "./Middlewares/Third_Party/Lora/Utilities/low_power.c" + 1:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /******************************************************************************* + 2:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @file low_power.c + 3:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @author MCD Application Team + 4:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @version V1.1.2 + 5:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @date 08-September-2017 + 6:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @brief driver for low power + 7:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** ****************************************************************************** + 8:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @attention + 9:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 10:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 11:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * All rights reserved.

+ 12:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 13:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * Redistribution and use in source and binary forms, with or without + 14:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * modification, are permitted, provided that the following conditions are met: + 15:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 16:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * 1. Redistribution of source code must retain the above copyright notice, + 17:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * this list of conditions and the following disclaimer. + 18:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 19:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * this list of conditions and the following disclaimer in the documentation + 20:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * and/or other materials provided with the distribution. + 21:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 22:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * contributors to this software may be used to endorse or promote products + 23:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * derived from this software without specific written permission. + 24:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * 4. This software, including modifications and/or derivative works of this + 25:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * software, must execute solely and exclusively on microcontroller or + 26:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 27:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * 5. Redistribution and use of this software other than as permitted under + 28:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * this license is void and will automatically terminate your rights under + 29:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * this license. + 30:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 31:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 32:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 33:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + ARM GAS /tmp/ccBl10G9.s page 2 + + + 34:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 35:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 36:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 37:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 38:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 39:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 40:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 41:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 42:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 43:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 44:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** ****************************************************************************** + 45:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 46:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 47:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Includes ------------------------------------------------------------------*/ + 48:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** #include "hw.h" + 49:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** #include "low_power.h" + 50:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 51:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Private typedef -----------------------------------------------------------*/ + 52:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Private define ------------------------------------------------------------*/ + 53:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Private macro -------------------------------------------------------------*/ + 54:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Private variables ---------------------------------------------------------*/ + 55:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 56:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /** + 57:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \brief Flag to indicate if MCU can go to low power mode + 58:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * When 0, MCU is authorized to go in low power mode + 59:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 60:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** static uint32_t LowPower_State = 0; + 61:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 62:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Private function prototypes -----------------------------------------------*/ + 63:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 64:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 65:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 66:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* Exported functions ---------------------------------------------------------*/ + 67:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 68:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /** + 69:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \brief API to set flag allowing power mode + 70:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 71:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \param [IN] enum e_LOW_POWER_State_Id_t + 72:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 73:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** void LowPower_Disable( e_LOW_POWER_State_Id_t state ) + 74:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 26 .loc 1 74 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB14: + 33 .LBB15: + 34 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + ARM GAS /tmp/ccBl10G9.s page 3 + + + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccBl10G9.s page 4 + + + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccBl10G9.s page 5 + + + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccBl10G9.s page 6 + + + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 35 .loc 2 203 0 + 36 .syntax divided + 37 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 38 0000 EFF31083 MRS r3, primask + 39 @ 0 "" 2 + 40 .thumb + 41 .syntax unified + 42 .LBE15: + 43 .LBE14: + 44 .LBB16: + 45 .LBB17: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 46 .loc 2 71 0 + 47 .syntax divided + 48 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 49 0004 72B6 cpsid i + 50 @ 0 "" 2 + 51 .thumb + 52 .syntax unified + 53 .LBE17: + 54 .LBE16: + 75:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** BACKUP_PRIMASK(); + 76:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 77:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DISABLE_IRQ( ); + 78:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 79:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** LowPower_State |= state; + 55 .loc 1 79 0 + 56 0006 034A ldr r2, .L2 + 57 0008 1168 ldr r1, [r2] + 58 000a 0843 orrs r0, r1 + 59 .LVL1: + 60 000c 1060 str r0, [r2] + ARM GAS /tmp/ccBl10G9.s page 7 + + + 61 .LBB18: + 62 .LBB19: + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 63 .loc 2 215 0 + 64 .syntax divided + 65 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 66 000e 83F31088 MSR primask, r3 + 67 @ 0 "" 2 + 68 .thumb + 69 .syntax unified + 70 .LBE19: + 71 .LBE18: + 80:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 81:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** RESTORE_PRIMASK( ); + 82:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 72 .loc 1 82 0 + 73 @ sp needed + 74 0012 7047 bx lr + 75 .L3: + 76 .align 2 + 77 .L2: + 78 0014 00000000 .word .LANCHOR0 + 79 .cfi_endproc + 80 .LFE96: + 82 .section .text.LowPower_Enable,"ax",%progbits + 83 .align 1 + 84 .global LowPower_Enable + 85 .syntax unified + 86 .code 16 + 87 .thumb_func + 88 .fpu softvfp + 90 LowPower_Enable: + 91 .LFB97: + 83:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 84:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /** + 85:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \brief API to reset flag allowing power mode + 86:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * + 87:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \param [IN] enum e_LOW_POWER_State_Id_t + 88:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 89:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** void LowPower_Enable( e_LOW_POWER_State_Id_t state ) + 90:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 92 .loc 1 90 0 + 93 .cfi_startproc + 94 @ args = 0, pretend = 0, frame = 0 + 95 @ frame_needed = 0, uses_anonymous_args = 0 + 96 @ link register save eliminated. + ARM GAS /tmp/ccBl10G9.s page 8 + + + 97 .LVL2: + 98 .LBB20: + 99 .LBB21: + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 100 .loc 2 203 0 + 101 .syntax divided + 102 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 103 0000 EFF31083 MRS r3, primask + 104 @ 0 "" 2 + 105 .thumb + 106 .syntax unified + 107 .LBE21: + 108 .LBE20: + 109 .LBB22: + 110 .LBB23: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 111 .loc 2 71 0 + 112 .syntax divided + 113 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 114 0004 72B6 cpsid i + 115 @ 0 "" 2 + 116 .thumb + 117 .syntax unified + 118 .LBE23: + 119 .LBE22: + 91:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** BACKUP_PRIMASK(); + 92:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 93:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DISABLE_IRQ( ); + 94:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 95:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** LowPower_State &= ~state; + 120 .loc 1 95 0 + 121 0006 0349 ldr r1, .L5 + 122 0008 0A68 ldr r2, [r1] + 123 000a 8243 bics r2, r0 + 124 000c 0A60 str r2, [r1] + 125 .LBB24: + 126 .LBB25: + 127 .loc 2 215 0 + 128 .syntax divided + 129 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 130 000e 83F31088 MSR primask, r3 + 131 @ 0 "" 2 + 132 .thumb + 133 .syntax unified + 134 .LBE25: + 135 .LBE24: + 96:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 97:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** RESTORE_PRIMASK( ); + 98:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 136 .loc 1 98 0 + 137 @ sp needed + 138 0012 7047 bx lr + 139 .L6: + 140 .align 2 + 141 .L5: + 142 0014 00000000 .word .LANCHOR0 + 143 .cfi_endproc + ARM GAS /tmp/ccBl10G9.s page 9 + + + 144 .LFE97: + 146 .section .text.LowPower_GetState,"ax",%progbits + 147 .align 1 + 148 .global LowPower_GetState + 149 .syntax unified + 150 .code 16 + 151 .thumb_func + 152 .fpu softvfp + 154 LowPower_GetState: + 155 .LFB98: + 99:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 100:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /** + 101:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \brief API to get flag allowing power mode + 102:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \note When flag is 0, low power mode is allowed + 103:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \param [IN] state + 104:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * \retval flag state + 105:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 106:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** uint32_t LowPower_GetState( void ) + 107:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 156 .loc 1 107 0 + 157 .cfi_startproc + 158 @ args = 0, pretend = 0, frame = 0 + 159 @ frame_needed = 0, uses_anonymous_args = 0 + 160 @ link register save eliminated. + 108:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** return LowPower_State; + 161 .loc 1 108 0 + 162 0000 014B ldr r3, .L8 + 163 0002 1868 ldr r0, [r3] + 109:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 164 .loc 1 109 0 + 165 @ sp needed + 166 0004 7047 bx lr + 167 .L9: + 168 0006 C046 .align 2 + 169 .L8: + 170 0008 00000000 .word .LANCHOR0 + 171 .cfi_endproc + 172 .LFE98: + 174 .section .text.LowPower_Handler,"ax",%progbits + 175 .align 1 + 176 .global LowPower_Handler + 177 .syntax unified + 178 .code 16 + 179 .thumb_func + 180 .fpu softvfp + 182 LowPower_Handler: + 183 .LFB99: + 110:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 111:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /** + 112:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @brief Handle Low Power + 113:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @param None + 114:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** * @retval None + 115:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** */ + 116:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 117:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** void LowPower_Handler( void ) + 118:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 184 .loc 1 118 0 + ARM GAS /tmp/ccBl10G9.s page 10 + + + 185 .cfi_startproc + 186 @ args = 0, pretend = 0, frame = 0 + 187 @ frame_needed = 0, uses_anonymous_args = 0 + 188 0000 10B5 push {r4, lr} + 189 .LCFI0: + 190 .cfi_def_cfa_offset 8 + 191 .cfi_offset 4, -8 + 192 .cfi_offset 14, -4 + 119:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_GPIO_RST(GPIOB, GPIO_PIN_15); + 120:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 121:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_GPIO_RST(GPIOB, GPIO_PIN_14); + 122:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 123:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** if ( LowPower_State == 0 ) + 193 .loc 1 123 0 + 194 0002 074B ldr r3, .L14 + 195 0004 1B68 ldr r3, [r3] + 196 0006 002B cmp r3, #0 + 197 0008 02D0 beq .L13 + 124:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 125:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 126:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_PRINTF_CRITICAL("dz\n\r"); + 127:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 128:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** HW_EnterStopMode( ); + 129:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 130:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** /* mcu dependent. to be implemented by user*/ + 131:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** HW_ExitStopMode(); + 132:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 133:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_GPIO_SET(GPIOB, GPIO_PIN_15); + 134:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 135:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** HW_RTC_setMcuWakeUpTime( ); + 136:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 137:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** else + 138:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** { + 139:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_PRINTF_CRITICAL("z\n\r"); + 140:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 141:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** HW_EnterSleepMode( ); + 198 .loc 1 141 0 + 199 000a FFF7FEFF bl HW_EnterSleepMode + 200 .LVL3: + 201 .L10: + 142:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 143:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** DBG_GPIO_SET(GPIOB, GPIO_PIN_14); + 144:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 145:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 146:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 202 .loc 1 146 0 + 203 @ sp needed + 204 000e 10BD pop {r4, pc} + 205 .L13: + 128:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 206 .loc 1 128 0 + 207 0010 FFF7FEFF bl HW_EnterStopMode + 208 .LVL4: + 131:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** + 209 .loc 1 131 0 + 210 0014 FFF7FEFF bl HW_ExitStopMode + 211 .LVL5: + ARM GAS /tmp/ccBl10G9.s page 11 + + + 135:./Middlewares/Third_Party/Lora/Utilities/low_power.c **** } + 212 .loc 1 135 0 + 213 0018 FFF7FEFF bl HW_RTC_setMcuWakeUpTime + 214 .LVL6: + 215 001c F7E7 b .L10 + 216 .L15: + 217 001e C046 .align 2 + 218 .L14: + 219 0020 00000000 .word .LANCHOR0 + 220 .cfi_endproc + 221 .LFE99: + 223 .section .bss.LowPower_State,"aw",%nobits + 224 .align 2 + 225 .set .LANCHOR0,. + 0 + 228 LowPower_State: + 229 0000 00000000 .space 4 + 230 .text + 231 .Letext0: + 232 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 233 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 234 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 235 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 236 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + 237 .file 8 "/usr/arm-none-eabi/include/math.h" + 238 .file 9 "/usr/arm-none-eabi/include/sys/_stdint.h" + 239 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 240 .file 11 "Inc/hw_msp.h" + 241 .file 12 "Inc/hw_rtc.h" + ARM GAS /tmp/ccBl10G9.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 low_power.c + /tmp/ccBl10G9.s:16 .text.LowPower_Disable:0000000000000000 $t + /tmp/ccBl10G9.s:23 .text.LowPower_Disable:0000000000000000 LowPower_Disable + /tmp/ccBl10G9.s:78 .text.LowPower_Disable:0000000000000014 $d + /tmp/ccBl10G9.s:83 .text.LowPower_Enable:0000000000000000 $t + /tmp/ccBl10G9.s:90 .text.LowPower_Enable:0000000000000000 LowPower_Enable + /tmp/ccBl10G9.s:142 .text.LowPower_Enable:0000000000000014 $d + /tmp/ccBl10G9.s:147 .text.LowPower_GetState:0000000000000000 $t + /tmp/ccBl10G9.s:154 .text.LowPower_GetState:0000000000000000 LowPower_GetState + /tmp/ccBl10G9.s:170 .text.LowPower_GetState:0000000000000008 $d + /tmp/ccBl10G9.s:175 .text.LowPower_Handler:0000000000000000 $t + /tmp/ccBl10G9.s:182 .text.LowPower_Handler:0000000000000000 LowPower_Handler + /tmp/ccBl10G9.s:219 .text.LowPower_Handler:0000000000000020 $d + /tmp/ccBl10G9.s:224 .bss.LowPower_State:0000000000000000 $d + /tmp/ccBl10G9.s:228 .bss.LowPower_State:0000000000000000 LowPower_State + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HW_EnterSleepMode +HW_EnterStopMode +HW_ExitStopMode +HW_RTC_setMcuWakeUpTime diff --git a/build/main.d b/build/main.d new file mode 100644 index 0000000..012e46e --- /dev/null +++ b/build/main.d @@ -0,0 +1,171 @@ +build/main.d: Src/main.c Inc/hw_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h Inc/main.h \ + Inc/debug.h Inc/hw_conf.h Inc/vcom.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h Inc/hw.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_gpio.h Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Middlewares/Third_Party/Lora/Utilities/low_power.h \ + Middlewares/Third_Party/Lora/Core/lora.h Inc/Commissioning.h \ + Middlewares/Third_Party/Lora/Mac/LoRaMac.h \ + Middlewares/Third_Party/Lora/Mac/region/Region.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/vcom.h \ + Src/voc_sensor.h Src/../Drivers/BME680/bme680.h \ + Src/../Drivers/BME680/bme680_defs.h + +Inc/hw_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/main.h: + +Inc/debug.h: + +Inc/hw_conf.h: + +Inc/vcom.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +Inc/hw.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Middlewares/Third_Party/Lora/Utilities/low_power.h: + +Middlewares/Third_Party/Lora/Core/lora.h: + +Inc/Commissioning.h: + +Middlewares/Third_Party/Lora/Mac/LoRaMac.h: + +Middlewares/Third_Party/Lora/Mac/region/Region.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/vcom.h: + +Src/voc_sensor.h: + +Src/../Drivers/BME680/bme680.h: + +Src/../Drivers/BME680/bme680_defs.h: diff --git a/build/main.lst b/build/main.lst new file mode 100644 index 0000000..92d2a1f --- /dev/null +++ b/build/main.lst @@ -0,0 +1,571 @@ +ARM GAS /tmp/cc3y5xFn.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "main.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HW_GetBatteryLevel,"ax",%progbits + 16 .align 1 + 17 .global HW_GetBatteryLevel + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HW_GetBatteryLevel: + 24 .LFB230: + 25 .file 1 "./Src/main.c" + 1:./Src/main.c **** /* + 2:./Src/main.c **** / _____) _ | | + 3:./Src/main.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/main.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/main.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/main.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/main.c **** (C)2013 Semtech + 8:./Src/main.c **** + 9:./Src/main.c **** Description: Generic lora driver implementation + 10:./Src/main.c **** + 11:./Src/main.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/main.c **** + 13:./Src/main.c **** Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene + 14:./Src/main.c **** */ + 15:./Src/main.c **** /****************************************************************************** + 16:./Src/main.c **** * @file main.c + 17:./Src/main.c **** * @author MCD Application Team + 18:./Src/main.c **** * @version V1.1.2 + 19:./Src/main.c **** * @date 08-September-2017 + 20:./Src/main.c **** * @brief this is the main! + 21:./Src/main.c **** ****************************************************************************** + 22:./Src/main.c **** * @attention + 23:./Src/main.c **** * + 24:./Src/main.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/main.c **** * All rights reserved.

+ 26:./Src/main.c **** * + 27:./Src/main.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/main.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/main.c **** * + 30:./Src/main.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/main.c **** * this list of conditions and the following disclaimer. + 32:./Src/main.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/main.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/cc3y5xFn.s page 2 + + + 34:./Src/main.c **** * and/or other materials provided with the distribution. + 35:./Src/main.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/main.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/main.c **** * derived from this software without specific written permission. + 38:./Src/main.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/main.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/main.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/main.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/main.c **** * this license is void and will automatically terminate your rights under + 43:./Src/main.c **** * this license. + 44:./Src/main.c **** * + 45:./Src/main.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/main.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/main.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/main.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/main.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/main.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/main.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/main.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/main.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/main.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/main.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/main.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/main.c **** * + 58:./Src/main.c **** ****************************************************************************** + 59:./Src/main.c **** */ + 60:./Src/main.c **** + 61:./Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Src/main.c **** #include + 63:./Src/main.c **** #include + 64:./Src/main.c **** #include "stm32l0xx_ll_i2c.h" + 65:./Src/main.c **** #include "hw.h" + 66:./Src/main.c **** #include "low_power.h" + 67:./Src/main.c **** #include "lora.h" + 68:./Src/main.c **** //#include "bsp.h" + 69:./Src/main.c **** #include "timeServer.h" + 70:./Src/main.c **** #include "vcom.h" + 71:./Src/main.c **** #include "voc_sensor.h" + 72:./Src/main.c **** + 73:./Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 74:./Src/main.c **** /* Private define ------------------------------------------------------------*/ + 75:./Src/main.c **** + 76:./Src/main.c **** #define LPP_APP_PORT 99 + 77:./Src/main.c **** + 78:./Src/main.c **** /*! + 79:./Src/main.c **** * Defines the application data transmission duty cycle. 5s, value in [ms]. + 80:./Src/main.c **** */ + 81:./Src/main.c **** #define APP_TX_DUTYCYCLE 10000 + 82:./Src/main.c **** /*! + 83:./Src/main.c **** * LoRaWAN Adaptive Data Rate + 84:./Src/main.c **** * @note Please note that when ADR is enabled the end-device should be static + 85:./Src/main.c **** */ + 86:./Src/main.c **** #define LORAWAN_ADR_ON 1 + 87:./Src/main.c **** /*! + 88:./Src/main.c **** * LoRaWAN confirmed messages + 89:./Src/main.c **** */ + 90:./Src/main.c **** #define LORAWAN_CONFIRMED_MSG DISABLE + ARM GAS /tmp/cc3y5xFn.s page 3 + + + 91:./Src/main.c **** /*! + 92:./Src/main.c **** * LoRaWAN application port + 93:./Src/main.c **** * @note do not use 224. It is reserved for certification + 94:./Src/main.c **** */ + 95:./Src/main.c **** #define LORAWAN_APP_PORT 42 + 96:./Src/main.c **** //2 + 97:./Src/main.c **** /*! + 98:./Src/main.c **** * Number of trials for the join request. + 99:./Src/main.c **** */ + 100:./Src/main.c **** #define JOINREQ_NBTRIALS 3 + 101:./Src/main.c **** + 102:./Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 103:./Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 104:./Src/main.c **** + 105:./Src/main.c **** /* call back when LoRa will transmit a frame*/ + 106:./Src/main.c **** static void LoraTxData(lora_AppData_t *AppData, FunctionalState *IsTxConfirmed); + 107:./Src/main.c **** + 108:./Src/main.c **** /* call back when LoRa has received a frame*/ + 109:./Src/main.c **** static void LoraRxData(lora_AppData_t *AppData); + 110:./Src/main.c **** + 111:./Src/main.c **** uint8_t HW_GetBatteryLevel(void) { + 26 .loc 1 111 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 112:./Src/main.c **** return 254; + 113:./Src/main.c **** } + 31 .loc 1 113 0 + 32 0000 FE20 movs r0, #254 + 33 @ sp needed + 34 0002 7047 bx lr + 35 .cfi_endproc + 36 .LFE230: + 38 .section .text.main,"ax",%progbits + 39 .align 1 + 40 .global main + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 main: + 47 .LFB231: + 114:./Src/main.c **** + 115:./Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 116:./Src/main.c **** /* load call backs*/ + 117:./Src/main.c **** static LoRaMainCallback_t LoRaMainCallbacks = {HW_GetBatteryLevel, + 118:./Src/main.c **** HW_GetUniqueId, + 119:./Src/main.c **** HW_GetRandomSeed, + 120:./Src/main.c **** LoraTxData, + 121:./Src/main.c **** LoraRxData}; + 122:./Src/main.c **** + 123:./Src/main.c **** + 124:./Src/main.c **** #ifdef USE_B_L072Z_LRWAN1 + 125:./Src/main.c **** /*! + 126:./Src/main.c **** * Timer to handle the application Tx Led to toggle + 127:./Src/main.c **** */ + ARM GAS /tmp/cc3y5xFn.s page 4 + + + 128:./Src/main.c **** static TimerEvent_t TxLedTimer; + 129:./Src/main.c **** static void OnTimerLedEvent( void ); + 130:./Src/main.c **** #endif + 131:./Src/main.c **** /* ! + 132:./Src/main.c **** *Initialises the Lora Parameters + 133:./Src/main.c **** */ + 134:./Src/main.c **** static LoRaParam_t LoRaParamInit = {TX_ON_TIMER, + 135:./Src/main.c **** APP_TX_DUTYCYCLE, + 136:./Src/main.c **** CLASS_A, + 137:./Src/main.c **** LORAWAN_ADR_ON, + 138:./Src/main.c **** DR_0, + 139:./Src/main.c **** LORAWAN_PUBLIC_NETWORK, + 140:./Src/main.c **** JOINREQ_NBTRIALS}; + 141:./Src/main.c **** + 142:./Src/main.c **** /* Private functions ---------------------------------------------------------*/ + 143:./Src/main.c **** + 144:./Src/main.c **** #if 0 + 145:./Src/main.c **** typedef enum { + 146:./Src/main.c **** i2cSpeed_std, + 147:./Src/main.c **** i2cSpeed_fast, + 148:./Src/main.c **** i2cSpeed_fastPlus, + 149:./Src/main.c **** i2cSpeed_count, + 150:./Src/main.c **** } i2cSpeed_t; + 151:./Src/main.c **** + 152:./Src/main.c **** void i2cInit(I2C_TypeDef *i2c, i2cSpeed_t spd); + 153:./Src/main.c **** + 154:./Src/main.c **** #define I2C_7BIT_ADDR (0 << 31) + 155:./Src/main.c **** #define I2C_10BIT_ADDR (1 << 31) + 156:./Src/main.c **** + 157:./Src/main.c **** // Returns number of bytes written + 158:./Src/main.c **** uint32_t i2cWrite(I2C_TypeDef *i2c, uint32_t addr, uint8_t *txBuffer, + 159:./Src/main.c **** uint32_t len); + 160:./Src/main.c **** + 161:./Src/main.c **** // Returns number of bytes read + 162:./Src/main.c **** uint32_t i2cRead(I2C_TypeDef *i2c, uint8_t addr, uint8_t *rxBuffer, + 163:./Src/main.c **** uint32_t numBytes); + 164:./Src/main.c **** + 165:./Src/main.c **** #define I2C_READ 0 + 166:./Src/main.c **** #define I2C_WRITE 1 + 167:./Src/main.c **** + 168:./Src/main.c **** static uint32_t setupTiming(i2cSpeed_t spd, uint32_t clockFreq) { + 169:./Src/main.c **** (void) spd; + 170:./Src/main.c **** (void) clockFreq; + 171:./Src/main.c **** uint32_t presc = 0; + 172:./Src/main.c **** uint32_t sdadel = 2; + 173:./Src/main.c **** uint32_t scldel = 2; + 174:./Src/main.c **** uint32_t scll = 6; + 175:./Src/main.c **** uint32_t sclh = 7; + 176:./Src/main.c **** + 177:./Src/main.c **** return presc << 28 | + 178:./Src/main.c **** scldel << 20 | + 179:./Src/main.c **** sdadel << 16 | + 180:./Src/main.c **** sclh << 8 | + 181:./Src/main.c **** scll; + 182:./Src/main.c **** } + 183:./Src/main.c **** + 184:./Src/main.c **** void i2cInit(I2C_TypeDef *i2c, i2cSpeed_t spd) { + ARM GAS /tmp/cc3y5xFn.s page 5 + + + 185:./Src/main.c **** // Setup timing register + 186:./Src/main.c **** i2c->TIMINGR = setupTiming(spd, SystemCoreClock); + 187:./Src/main.c **** + 188:./Src/main.c **** // Reset state + 189:./Src/main.c **** i2c->CR1 &= ~I2C_CR1_PE; + 190:./Src/main.c **** } + 191:./Src/main.c **** + 192:./Src/main.c **** static uint32_t i2cSetup(uint32_t addr, uint8_t direction) { + 193:./Src/main.c **** uint32_t ret = 0; + 194:./Src/main.c **** if (addr & I2C_10BIT_ADDR) { + 195:./Src/main.c **** ret = (addr & 0x000003FF) | I2C_CR2_ADD10; + 196:./Src/main.c **** } else { + 197:./Src/main.c **** // 7 Bit Address + 198:./Src/main.c **** ret = (addr & 0x0000007F) << 1; + 199:./Src/main.c **** } + 200:./Src/main.c **** + 201:./Src/main.c **** if (direction == I2C_READ) { + 202:./Src/main.c **** ret |= I2C_CR2_RD_WRN; + 203:./Src/main.c **** if (addr & I2C_10BIT_ADDR) { + 204:./Src/main.c **** ret |= I2C_CR2_HEAD10R; + 205:./Src/main.c **** } + 206:./Src/main.c **** } + 207:./Src/main.c **** + 208:./Src/main.c **** return ret; + 209:./Src/main.c **** } + 210:./Src/main.c **** + 211:./Src/main.c **** // Will return the number of data bytes written to the device + 212:./Src/main.c **** uint32_t i2cWrite(I2C_TypeDef *i2c, uint32_t addr, uint8_t *txBuffer, + 213:./Src/main.c **** uint32_t len) { + 214:./Src/main.c **** + 215:./Src/main.c **** uint32_t numTxBytes = 0; + 216:./Src/main.c **** + 217:./Src/main.c **** i2c->CR1 &= ~I2C_CR1_PE; + 218:./Src/main.c **** i2c->CR2 = 0; + 219:./Src/main.c **** + 220:./Src/main.c **** i2c->CR2 = i2cSetup(addr, I2C_WRITE); + 221:./Src/main.c **** + 222:./Src/main.c **** if (len > 0xFF) { + 223:./Src/main.c **** i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + 224:./Src/main.c **** } else { + 225:./Src/main.c **** i2c->CR2 |= ((len & 0xFF) << 16) | I2C_CR2_AUTOEND; + 226:./Src/main.c **** } + 227:./Src/main.c **** i2c->CR1 |= I2C_CR1_PE; + 228:./Src/main.c **** i2c->CR2 |= I2C_CR2_START; + 229:./Src/main.c **** while(i2c->CR2 & I2C_CR2_START); + 230:./Src/main.c **** uint8_t done = 0; + 231:./Src/main.c **** uint32_t i = 0; + 232:./Src/main.c **** while (!done && i < 0x0000001F) { + 233:./Src/main.c **** i++; + 234:./Src/main.c **** if (i2c->ISR & I2C_ISR_NACKF) { + 235:./Src/main.c **** // Was not acknowledged, disable device and exit + 236:./Src/main.c **** done = 1; + 237:./Src/main.c **** } + 238:./Src/main.c **** + 239:./Src/main.c **** if (i2c->ISR & I2C_ISR_TXIS) { + 240:./Src/main.c **** // Device acknowledged and we must send the next byte + 241:./Src/main.c **** if (numTxBytes < len){ + ARM GAS /tmp/cc3y5xFn.s page 6 + + + 242:./Src/main.c **** i2c->TXDR = txBuffer[numTxBytes++]; + 243:./Src/main.c **** } + 244:./Src/main.c **** + 245:./Src/main.c **** i = 0; + 246:./Src/main.c **** + 247:./Src/main.c **** } + 248:./Src/main.c **** + 249:./Src/main.c **** if (i2c->ISR & I2C_ISR_TC) { + 250:./Src/main.c **** done = 1; + 251:./Src/main.c **** } + 252:./Src/main.c **** + 253:./Src/main.c **** if (i2c->ISR & I2C_ISR_TCR) { + 254:./Src/main.c **** i = 0; + 255:./Src/main.c **** if ((len - numTxBytes) > 0xFF) { + 256:./Src/main.c **** i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + 257:./Src/main.c **** } else { + 258:./Src/main.c **** i2c->CR2 &= ~(0x00FF0000 | I2C_CR2_RELOAD); + 259:./Src/main.c **** i2c->CR2 |= ((len - numTxBytes) & 0xFF) << 16 | + 260:./Src/main.c **** I2C_CR2_AUTOEND; + 261:./Src/main.c **** } + 262:./Src/main.c **** } + 263:./Src/main.c **** + 264:./Src/main.c **** } + 265:./Src/main.c **** i2c->CR1 &= ~I2C_CR1_PE; + 266:./Src/main.c **** return numTxBytes; + 267:./Src/main.c **** } + 268:./Src/main.c **** + 269:./Src/main.c **** uint32_t i2cRead(I2C_TypeDef *i2c, uint8_t addr, uint8_t *rxBuffer, + 270:./Src/main.c **** uint32_t numBytes) { + 271:./Src/main.c **** + 272:./Src/main.c **** uint32_t numRxBytes = 0; + 273:./Src/main.c **** + 274:./Src/main.c **** i2c->CR1 &= ~I2C_CR1_PE; + 275:./Src/main.c **** i2c->CR2 = 0; + 276:./Src/main.c **** + 277:./Src/main.c **** i2c->CR2 = i2cSetup(addr, I2C_READ); + 278:./Src/main.c **** + 279:./Src/main.c **** if (numBytes > 0xFF) { + 280:./Src/main.c **** i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + 281:./Src/main.c **** } else { + 282:./Src/main.c **** i2c->CR2 |= ((numBytes & 0xFF) << 16) | I2C_CR2_AUTOEND; + 283:./Src/main.c **** } + 284:./Src/main.c **** i2c->CR1 |= I2C_CR1_PE; + 285:./Src/main.c **** i2c->CR2 |= I2C_CR2_START; + 286:./Src/main.c **** + 287:./Src/main.c **** while(i2c->CR2 & I2C_CR2_START); + 288:./Src/main.c **** uint8_t done = 0; + 289:./Src/main.c **** uint32_t i = 0; + 290:./Src/main.c **** while (!done && i < 0x0000001F) { + 291:./Src/main.c **** i++; + 292:./Src/main.c **** + 293:./Src/main.c **** if (i2c->ISR & I2C_ISR_RXNE) { + 294:./Src/main.c **** // Device acknowledged and we must send the next byte + 295:./Src/main.c **** if (numRxBytes < numBytes){ + 296:./Src/main.c **** rxBuffer[numRxBytes++] = i2c->RXDR; + 297:./Src/main.c **** } + 298:./Src/main.c **** + ARM GAS /tmp/cc3y5xFn.s page 7 + + + 299:./Src/main.c **** i = 0; + 300:./Src/main.c **** } + 301:./Src/main.c **** + 302:./Src/main.c **** if (i2c->ISR & I2C_ISR_TC) { + 303:./Src/main.c **** done = 1; + 304:./Src/main.c **** } + 305:./Src/main.c **** + 306:./Src/main.c **** if (i2c->ISR & I2C_ISR_TCR) { + 307:./Src/main.c **** i = 0; + 308:./Src/main.c **** if ((numBytes - numRxBytes) > 0xFF) { + 309:./Src/main.c **** i2c->CR2 |= 0x00FF0000 | I2C_CR2_RELOAD; + 310:./Src/main.c **** } else { + 311:./Src/main.c **** i2c->CR2 &= ~(0x00FF0000 | I2C_CR2_RELOAD); + 312:./Src/main.c **** i2c->CR2 |= ((numBytes - numRxBytes) & 0xFF) << 16 | + 313:./Src/main.c **** I2C_CR2_AUTOEND; + 314:./Src/main.c **** } + 315:./Src/main.c **** } + 316:./Src/main.c **** + 317:./Src/main.c **** } + 318:./Src/main.c **** i2c->CR1 &= ~I2C_CR1_PE; + 319:./Src/main.c **** return numRxBytes; + 320:./Src/main.c **** } + 321:./Src/main.c **** #endif + 322:./Src/main.c **** + 323:./Src/main.c **** + 324:./Src/main.c **** /** + 325:./Src/main.c **** * @brief Main program + 326:./Src/main.c **** * @param None + 327:./Src/main.c **** * @retval None + 328:./Src/main.c **** */ + 329:./Src/main.c **** int main(void) + 330:./Src/main.c **** { + 48 .loc 1 330 0 + 49 .cfi_startproc + 50 @ Volatile: function does not return. + 51 @ args = 0, pretend = 0, frame = 32 + 52 @ frame_needed = 0, uses_anonymous_args = 0 + 53 0000 10B5 push {r4, lr} + 54 .LCFI0: + 55 .cfi_def_cfa_offset 8 + 56 .cfi_offset 4, -8 + 57 .cfi_offset 14, -4 + 58 0002 88B0 sub sp, sp, #32 + 59 .LCFI1: + 60 .cfi_def_cfa_offset 40 + 331:./Src/main.c **** /* STM32 HAL library initialization*/ + 332:./Src/main.c **** HAL_Init(); + 61 .loc 1 332 0 + 62 0004 FFF7FEFF bl HAL_Init + 63 .LVL0: + 333:./Src/main.c **** + 334:./Src/main.c **** /* Configure the system clock*/ + 335:./Src/main.c **** SystemClock_Config(); + 64 .loc 1 335 0 + 65 0008 FFF7FEFF bl SystemClock_Config + 66 .LVL1: + 336:./Src/main.c **** + ARM GAS /tmp/cc3y5xFn.s page 8 + + + 337:./Src/main.c **** /* Configure the debug mode*/ + 338:./Src/main.c **** DBG_Init(); + 67 .loc 1 338 0 + 68 000c FFF7FEFF bl DBG_Init + 69 .LVL2: + 70 .LBB2: + 339:./Src/main.c **** + 340:./Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 71 .loc 1 340 0 + 72 0010 154B ldr r3, .L4 + 73 0012 DA6A ldr r2, [r3, #44] + 74 0014 0124 movs r4, #1 + 75 0016 2243 orrs r2, r4 + 76 0018 DA62 str r2, [r3, #44] + 77 001a DA6A ldr r2, [r3, #44] + 78 001c 2240 ands r2, r4 + 79 001e 0192 str r2, [sp, #4] + 80 0020 019A ldr r2, [sp, #4] + 81 .LBE2: + 82 .LBB3: + 341:./Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 83 .loc 1 341 0 + 84 0022 D96A ldr r1, [r3, #44] + 85 0024 0422 movs r2, #4 + 86 0026 1143 orrs r1, r2 + 87 0028 D962 str r1, [r3, #44] + 88 002a DB6A ldr r3, [r3, #44] + 89 002c 1A40 ands r2, r3 + 90 002e 0292 str r2, [sp, #8] + 91 0030 029B ldr r3, [sp, #8] + 92 .LBE3: + 342:./Src/main.c **** + 343:./Src/main.c **** /* Configure the hardware*/ + 344:./Src/main.c **** HW_Init(); + 93 .loc 1 344 0 + 94 0032 FFF7FEFF bl HW_Init + 95 .LVL3: + 345:./Src/main.c **** MX_I2C1_Init(); + 96 .loc 1 345 0 + 97 0036 FFF7FEFF bl MX_I2C1_Init + 98 .LVL4: + 346:./Src/main.c **** + 347:./Src/main.c **** // BLINKY + 348:./Src/main.c **** GPIO_InitTypeDef initStruct = { 0 }; + 99 .loc 1 348 0 + 100 003a 1422 movs r2, #20 + 101 003c 0021 movs r1, #0 + 102 003e 03A8 add r0, sp, #12 + 103 0040 FFF7FEFF bl memset + 104 .LVL5: + 349:./Src/main.c **** initStruct.Mode =GPIO_MODE_OUTPUT_PP; + 105 .loc 1 349 0 + 106 0044 0494 str r4, [sp, #16] + 350:./Src/main.c **** initStruct.Pull = GPIO_NOPULL; + 351:./Src/main.c **** initStruct.Speed = GPIO_SPEED_HIGH; + 107 .loc 1 351 0 + 108 0046 0323 movs r3, #3 + ARM GAS /tmp/cc3y5xFn.s page 9 + + + 109 0048 0693 str r3, [sp, #24] + 352:./Src/main.c **** HW_GPIO_Init(GPIOC, GPIO_PIN_7, &initStruct); + 110 .loc 1 352 0 + 111 004a 03AA add r2, sp, #12 + 112 004c 8021 movs r1, #128 + 113 004e 0748 ldr r0, .L4+4 + 114 0050 FFF7FEFF bl HW_GPIO_Init + 115 .LVL6: + 353:./Src/main.c **** + 354:./Src/main.c **** /* USER CODE BEGIN 1 */ + 355:./Src/main.c **** /* USER CODE END 1 */ + 356:./Src/main.c **** voc_init(); + 116 .loc 1 356 0 + 117 0054 FFF7FEFF bl voc_init + 118 .LVL7: + 119 .L3: + 357:./Src/main.c **** + 358:./Src/main.c **** while(1) { + 359:./Src/main.c **** GPIOC->ODR ^= 1<<7; + 120 .loc 1 359 0 discriminator 1 + 121 0058 044A ldr r2, .L4+4 + 122 005a 5369 ldr r3, [r2, #20] + 123 005c 8021 movs r1, #128 + 124 005e 4B40 eors r3, r1 + 125 0060 5361 str r3, [r2, #20] + 360:./Src/main.c **** voc_measure(); + 126 .loc 1 360 0 discriminator 1 + 127 0062 FFF7FEFF bl voc_measure + 128 .LVL8: + 129 0066 F7E7 b .L3 + 130 .L5: + 131 .align 2 + 132 .L4: + 133 0068 00100240 .word 1073876992 + 134 006c 00080050 .word 1342179328 + 135 .cfi_endproc + 136 .LFE231: + 138 .text + 139 .Letext0: + 140 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 141 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 142 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 143 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 144 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 145 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 146 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 147 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 148 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 149 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 150 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 151 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 152 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h" + 153 .file 15 "Inc/hw_i2c.h" + 154 .file 16 "/usr/arm-none-eabi/include/math.h" + 155 .file 17 "Middlewares/Third_Party/Lora/Mac/LoRaMac.h" + 156 .file 18 "Middlewares/Third_Party/Lora/Core/lora.h" + 157 .file 19 "./Src/../Drivers/BME680/bme680_defs.h" + ARM GAS /tmp/cc3y5xFn.s page 10 + + + 158 .file 20 "./Src/voc_sensor.h" + 159 .file 21 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 160 .file 22 "Inc/hw_msp.h" + 161 .file 23 "Inc/debug.h" + 162 .file 24 "Inc/hw_gpio.h" + 163 .file 25 "" + ARM GAS /tmp/cc3y5xFn.s page 11 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c + /tmp/cc3y5xFn.s:16 .text.HW_GetBatteryLevel:0000000000000000 $t + /tmp/cc3y5xFn.s:23 .text.HW_GetBatteryLevel:0000000000000000 HW_GetBatteryLevel + /tmp/cc3y5xFn.s:39 .text.main:0000000000000000 $t + /tmp/cc3y5xFn.s:46 .text.main:0000000000000000 main + /tmp/cc3y5xFn.s:133 .text.main:0000000000000068 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_Init +SystemClock_Config +DBG_Init +HW_Init +MX_I2C1_Init +memset +HW_GPIO_Init +voc_init +voc_measure diff --git a/build/startup_stm32l073xx.d b/build/startup_stm32l073xx.d new file mode 100644 index 0000000..188269a --- /dev/null +++ b/build/startup_stm32l073xx.d @@ -0,0 +1 @@ +build/startup_stm32l073xx.d: startup/startup_stm32l073xx.s diff --git a/build/stm32l0xx_hal.d b/build/stm32l0xx_hal.d new file mode 100644 index 0000000..32601d8 --- /dev/null +++ b/build/stm32l0xx_hal.d @@ -0,0 +1,102 @@ +build/stm32l0xx_hal.d: Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal.lst b/build/stm32l0xx_hal.lst new file mode 100644 index 0000000..7c39082 --- /dev/null +++ b/build/stm32l0xx_hal.lst @@ -0,0 +1,1522 @@ +ARM GAS /tmp/ccYJZGyl.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_MspInit,"ax",%progbits + 16 .align 1 + 17 .weak HAL_MspInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_MspInit: + 24 .LFB41: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @file stm32l0xx_hal.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * This is the common part of the HAL initialization + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @verbatim + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ============================================================================== + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ##### How to use this driver ##### + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ============================================================================== + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** [..] + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** The common HAL driver contains a set of generic and common APIs that can be + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** used by the PPP peripheral drivers and the user to start using the HAL. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** [..] + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** The HAL contains two APIs categories: + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Common HAL APIs + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Services HAL APIs + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @endverbatim + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ****************************************************************************** + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @attention + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * Redistribution and use in source and binary forms, with or without modification, + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * are permitted provided that the following conditions are met: + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * 1. Redistributions of source code must retain the above copyright notice, + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * this list of conditions and the following disclaimer. + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * this list of conditions and the following disclaimer in the documentation + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * and/or other materials provided with the distribution. + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + ARM GAS /tmp/ccYJZGyl.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * may be used to endorse or promote products derived from this software + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * without specific prior written permission. + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ****************************************************************************** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Includes ------------------------------------------------------------------*/ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #include "stm32l0xx_hal.h" + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup STM32L0xx_HAL_Driver + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #ifdef HAL_MODULE_ENABLED + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup HAL + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief HAL module driver. + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup HAL_Exported_Constants + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @defgroup SysTick System Tick + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief uwTick_variable uwTick variable + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __IO uint32_t uwTick; + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @} + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @defgroup HAL_Version HAL Version + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief STM32L0xx HAL Driver version number + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define __STM32L0xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ + ARM GAS /tmp/ccYJZGyl.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define __STM32L0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** |(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** |(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** |(__STM32L0xx_HAL_VERSION_RC)) + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU) + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @} + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @} + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @defgroup HAL_Private HAL Private + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @} + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup HAL_Exported_Functions HAL Exported Functions + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group1 + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Initialization and de-initialization functions + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @verbatim + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** =============================================================================== + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ##### Initialization and de-initialization functions ##### + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** =============================================================================== + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** [..] This section provides functions allowing to: + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Initializes the Flash interface, the NVIC allocation and initial clock + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** configuration. It initializes the source of time base also when timeout + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** is needed and the backup domain when enabled. + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) de-Initializes common part of the HAL. + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Configure The time base source to have 1ms time base with a dedicated + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** Tick interrupt priority. + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (++) Systick timer is used by default as source of time base, but user + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** can eventually implement his proper time base source (a general purpose + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** timer for example or other time source), keeping in mind that Time base + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** handled in milliseconds basis. + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (++) Time base configuration function (HAL_InitTick ()) is called automatically + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** at the beginning of the program after reset by HAL_Init() or at any time + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** when clock is configured, by HAL_RCC_ClockConfig(). + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (++) Source of time base is configured to generate interrupts at regular + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** time intervals. Care must be taken if HAL_Delay() is called from a + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** peripheral ISR process, the Tick interrupt line must have higher priority + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (numerically lower) than the peripheral interrupt. Otherwise the caller + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ISR process will be blocked. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (++) functions affecting time base configurations are declared as __weak + ARM GAS /tmp/ccYJZGyl.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** to make override possible in case of other implementations in user file. + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @endverbatim + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief This function configures the Flash prefetch, Flash preread and Buffer cache, + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * Configures time base source, NVIC and Low level hardware + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is called at the beginning of program after reset and before + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * the clock configuration + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note The time base configuration is based on MSI clock when exiting from Reset. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * Once done, time base tick start incrementing. + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * In the default implementation,Systick is used as source of time base. + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * the tick variable is incremented each 1ms in its ISR. + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval HAL status + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_StatusTypeDef HAL_Init(void) + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Configure Buffer cache, Flash prefetch, Flash preread */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #if (BUFFER_CACHE_DISABLE != 0) + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_FLASH_BUFFER_CACHE_DISABLE(); + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #endif /* BUFFER_CACHE_DISABLE */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #if (PREREAD_ENABLE != 0) + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_FLASH_PREREAD_BUFFER_ENABLE(); + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #endif /* PREREAD_ENABLE */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #if (PREFETCH_ENABLE != 0) + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_InitTick(TICK_INT_PRIORITY); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Init the low level hardware */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_MspInit(); + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Return function status */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return HAL_OK; + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief This function de-Initializes common part of the HAL and stops the source + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * of time base. + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is optional. + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval HAL status + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void) + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Reset of all peripherals */ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB1_FORCE_RESET(); + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB2_FORCE_RESET(); + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + ARM GAS /tmp/ccYJZGyl.s page 5 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_AHB_FORCE_RESET(); + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_IOP_FORCE_RESET(); + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_IOP_RELEASE_RESET(); + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* De-Init the low level hardware */ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_MspDeInit(); + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Return function status */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return HAL_OK; + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Initializes the MSP. + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_MspInit(void) + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 26 .loc 1 224 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** the HAL_MspInit could be implemented in the user file + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 31 .loc 1 228 0 + 32 @ sp needed + 33 0000 7047 bx lr + 34 .cfi_endproc + 35 .LFE41: + 37 .section .text.HAL_MspDeInit,"ax",%progbits + 38 .align 1 + 39 .weak HAL_MspDeInit + 40 .syntax unified + 41 .code 16 + 42 .thumb_func + 43 .fpu softvfp + 45 HAL_MspDeInit: + 46 .LFB42: + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief DeInitializes the MSP. + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_MspDeInit(void) + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 47 .loc 1 235 0 + 48 .cfi_startproc + 49 @ args = 0, pretend = 0, frame = 0 + 50 @ frame_needed = 0, uses_anonymous_args = 0 + 51 @ link register save eliminated. + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** the HAL_MspDeInit could be implemented in the user file + ARM GAS /tmp/ccYJZGyl.s page 6 + + + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 52 .loc 1 239 0 + 53 @ sp needed + 54 0000 7047 bx lr + 55 .cfi_endproc + 56 .LFE42: + 58 .section .text.HAL_DeInit,"ax",%progbits + 59 .align 1 + 60 .global HAL_DeInit + 61 .syntax unified + 62 .code 16 + 63 .thumb_func + 64 .fpu softvfp + 66 HAL_DeInit: + 67 .LFB40: + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Reset of all peripherals */ + 68 .loc 1 198 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 0000 10B5 push {r4, lr} + 73 .LCFI0: + 74 .cfi_def_cfa_offset 8 + 75 .cfi_offset 4, -8 + 76 .cfi_offset 14, -4 + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 77 .loc 1 200 0 + 78 0002 084B ldr r3, .L4 + 79 0004 0121 movs r1, #1 + 80 0006 4942 rsbs r1, r1, #0 + 81 0008 9962 str r1, [r3, #40] + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 82 .loc 1 201 0 + 83 000a 0022 movs r2, #0 + 84 000c 9A62 str r2, [r3, #40] + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 85 .loc 1 203 0 + 86 000e 5962 str r1, [r3, #36] + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 87 .loc 1 204 0 + 88 0010 5A62 str r2, [r3, #36] + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 89 .loc 1 206 0 + 90 0012 1962 str r1, [r3, #32] + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 91 .loc 1 207 0 + 92 0014 1A62 str r2, [r3, #32] + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __HAL_RCC_IOP_RELEASE_RESET(); + 93 .loc 1 209 0 + 94 0016 D961 str r1, [r3, #28] + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 95 .loc 1 210 0 + 96 0018 DA61 str r2, [r3, #28] + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 97 .loc 1 213 0 + 98 001a FFF7FEFF bl HAL_MspDeInit + ARM GAS /tmp/ccYJZGyl.s page 7 + + + 99 .LVL0: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 100 .loc 1 217 0 + 101 001e 0020 movs r0, #0 + 102 @ sp needed + 103 0020 10BD pop {r4, pc} + 104 .L5: + 105 0022 C046 .align 2 + 106 .L4: + 107 0024 00100240 .word 1073876992 + 108 .cfi_endproc + 109 .LFE40: + 111 .global __aeabi_uidiv + 112 .section .text.HAL_InitTick,"ax",%progbits + 113 .align 1 + 114 .weak HAL_InitTick + 115 .syntax unified + 116 .code 16 + 117 .thumb_func + 118 .fpu softvfp + 120 HAL_InitTick: + 121 .LFB43: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief This function configures the source of the time base. + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * The time source is configured to have 1ms time base with a dedicated + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * Tick interrupt priority. + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is called automatically at the beginning of program after + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note In the default implementation, SysTick timer is the source of time base. + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * It is used to generate interrupts at regular time intervals. + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * The the SysTick interrupt must have higher priority (numerically lower) + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementation in user file. + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @param TickPriority: Tick interrupt priority. + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval HAL status + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 122 .loc 1 259 0 + 123 .cfi_startproc + 124 @ args = 0, pretend = 0, frame = 0 + 125 @ frame_needed = 0, uses_anonymous_args = 0 + 126 .LVL1: + 127 0000 10B5 push {r4, lr} + 128 .LCFI1: + 129 .cfi_def_cfa_offset 8 + 130 .cfi_offset 4, -8 + 131 .cfi_offset 14, -4 + 132 0002 0400 movs r4, r0 + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /*Configure the SysTick to have interrupt in 1ms time basis*/ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_SYSTICK_Config(SystemCoreClock/1000U); + 133 .loc 1 261 0 + 134 0004 074B ldr r3, .L7 + ARM GAS /tmp/ccYJZGyl.s page 8 + + + 135 0006 1868 ldr r0, [r3] + 136 .LVL2: + 137 0008 FA21 movs r1, #250 + 138 000a 8900 lsls r1, r1, #2 + 139 000c FFF7FEFF bl __aeabi_uidiv + 140 .LVL3: + 141 0010 FFF7FEFF bl HAL_SYSTICK_Config + 142 .LVL4: + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /*Configure the SysTick IRQ priority */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); + 143 .loc 1 264 0 + 144 0014 0120 movs r0, #1 + 145 0016 0022 movs r2, #0 + 146 0018 2100 movs r1, r4 + 147 001a 4042 rsbs r0, r0, #0 + 148 001c FFF7FEFF bl HAL_NVIC_SetPriority + 149 .LVL5: + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Return function status */ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return HAL_OK; + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 150 .loc 1 268 0 + 151 0020 0020 movs r0, #0 + 152 @ sp needed + 153 .LVL6: + 154 0022 10BD pop {r4, pc} + 155 .L8: + 156 .align 2 + 157 .L7: + 158 0024 00000000 .word SystemCoreClock + 159 .cfi_endproc + 160 .LFE43: + 162 .section .text.HAL_Init,"ax",%progbits + 163 .align 1 + 164 .global HAL_Init + 165 .syntax unified + 166 .code 16 + 167 .thumb_func + 168 .fpu softvfp + 170 HAL_Init: + 171 .LFB39: + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Configure Buffer cache, Flash prefetch, Flash preread */ + 172 .loc 1 166 0 + 173 .cfi_startproc + 174 @ args = 0, pretend = 0, frame = 0 + 175 @ frame_needed = 0, uses_anonymous_args = 0 + 176 0000 10B5 push {r4, lr} + 177 .LCFI2: + 178 .cfi_def_cfa_offset 8 + 179 .cfi_offset 4, -8 + 180 .cfi_offset 14, -4 + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 181 .loc 1 177 0 + 182 0002 064A ldr r2, .L10 + 183 0004 1368 ldr r3, [r2] + 184 0006 0221 movs r1, #2 + ARM GAS /tmp/ccYJZGyl.s page 9 + + + 185 0008 0B43 orrs r3, r1 + 186 000a 1360 str r3, [r2] + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 187 .loc 1 182 0 + 188 000c 0320 movs r0, #3 + 189 000e FFF7FEFF bl HAL_InitTick + 190 .LVL7: + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 191 .loc 1 185 0 + 192 0012 FFF7FEFF bl HAL_MspInit + 193 .LVL8: + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 194 .loc 1 189 0 + 195 0016 0020 movs r0, #0 + 196 @ sp needed + 197 0018 10BD pop {r4, pc} + 198 .L11: + 199 001a C046 .align 2 + 200 .L10: + 201 001c 00200240 .word 1073881088 + 202 .cfi_endproc + 203 .LFE39: + 205 .section .text.HAL_IncTick,"ax",%progbits + 206 .align 1 + 207 .weak HAL_IncTick + 208 .syntax unified + 209 .code 16 + 210 .thumb_func + 211 .fpu softvfp + 213 HAL_IncTick: + 214 .LFB44: + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @} + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group2 + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Peripheral Control functions + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @verbatim + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** =============================================================================== + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** ##### HAL Control functions ##### + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** =============================================================================== + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** [..] This section provides functions allowing to: + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Provide a tick value in millisecond + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Provide a blocking delay in millisecond + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Suspend the time base source interrupt + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Resume the time base source interrupt + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Get the HAL API driver version + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Get the device identifier + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Get the device revision identifier + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Configure low power mode behavior when the MCU is in Debug mode + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** (+) Manage the VEREFINT feature (activation, lock, output selection) + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** @endverbatim + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @{ + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + ARM GAS /tmp/ccYJZGyl.s page 10 + + + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * used as application time base. + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * in Systick ISR. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementations in user file. + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_IncTick(void) + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 215 .loc 1 306 0 + 216 .cfi_startproc + 217 @ args = 0, pretend = 0, frame = 0 + 218 @ frame_needed = 0, uses_anonymous_args = 0 + 219 @ link register save eliminated. + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uwTick++; + 220 .loc 1 307 0 + 221 0000 024A ldr r2, .L13 + 222 0002 1368 ldr r3, [r2] + 223 0004 0133 adds r3, r3, #1 + 224 0006 1360 str r3, [r2] + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 225 .loc 1 308 0 + 226 @ sp needed + 227 0008 7047 bx lr + 228 .L14: + 229 000a C046 .align 2 + 230 .L13: + 231 000c 00000000 .word .LANCHOR0 + 232 .cfi_endproc + 233 .LFE44: + 235 .section .text.HAL_GetTick,"ax",%progbits + 236 .align 1 + 237 .weak HAL_GetTick + 238 .syntax unified + 239 .code 16 + 240 .thumb_func + 241 .fpu softvfp + 243 HAL_GetTick: + 244 .LFB45: + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Provides a tick value in millisecond. + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementations in user file. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval tick value + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 245 .loc 1 317 0 + 246 .cfi_startproc + 247 @ args = 0, pretend = 0, frame = 0 + 248 @ frame_needed = 0, uses_anonymous_args = 0 + 249 @ link register save eliminated. + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return uwTick; + ARM GAS /tmp/ccYJZGyl.s page 11 + + + 250 .loc 1 318 0 + 251 0000 014B ldr r3, .L16 + 252 0002 1868 ldr r0, [r3] + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 253 .loc 1 319 0 + 254 @ sp needed + 255 0004 7047 bx lr + 256 .L17: + 257 0006 C046 .align 2 + 258 .L16: + 259 0008 00000000 .word .LANCHOR0 + 260 .cfi_endproc + 261 .LFE45: + 263 .section .text.HAL_Delay,"ax",%progbits + 264 .align 1 + 265 .weak HAL_Delay + 266 .syntax unified + 267 .code 16 + 268 .thumb_func + 269 .fpu softvfp + 271 HAL_Delay: + 272 .LFB46: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief This function provides accurate delay (in ms) based on a variable incremented. + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * is incremented. + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note ThiS function is declared as __weak to be overwritten in case of other + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementations in user file. + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @param Delay: specifies the delay time length, in milliseconds. + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_Delay(__IO uint32_t Delay) + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 273 .loc 1 332 0 + 274 .cfi_startproc + 275 @ args = 0, pretend = 0, frame = 8 + 276 @ frame_needed = 0, uses_anonymous_args = 0 + 277 .LVL9: + 278 0000 10B5 push {r4, lr} + 279 .LCFI3: + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 4, -8 + 282 .cfi_offset 14, -4 + 283 0002 82B0 sub sp, sp, #8 + 284 .LCFI4: + 285 .cfi_def_cfa_offset 16 + 286 0004 0190 str r0, [sp, #4] + 287 .LVL10: + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uint32_t tickstart = 0U; + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** tickstart = HAL_GetTick(); + 288 .loc 1 334 0 + 289 0006 FFF7FEFF bl HAL_GetTick + 290 .LVL11: + 291 000a 0400 movs r4, r0 + 292 .LVL12: + ARM GAS /tmp/ccYJZGyl.s page 12 + + + 293 .L19: + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** while((HAL_GetTick() - tickstart) < Delay) + 294 .loc 1 335 0 discriminator 1 + 295 000c FFF7FEFF bl HAL_GetTick + 296 .LVL13: + 297 0010 001B subs r0, r0, r4 + 298 0012 019B ldr r3, [sp, #4] + 299 0014 9842 cmp r0, r3 + 300 0016 F9D3 bcc .L19 + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 301 .loc 1 338 0 + 302 0018 02B0 add sp, sp, #8 + 303 @ sp needed + 304 .LVL14: + 305 001a 10BD pop {r4, pc} + 306 .cfi_endproc + 307 .LFE46: + 309 .section .text.HAL_SuspendTick,"ax",%progbits + 310 .align 1 + 311 .weak HAL_SuspendTick + 312 .syntax unified + 313 .code 16 + 314 .thumb_func + 315 .fpu softvfp + 317 HAL_SuspendTick: + 318 .LFB47: + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Suspends the Tick increment. + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * is called, the the SysTick interrupt will be disabled and so Tick increment + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * is suspended. + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementations in user file. + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_SuspendTick(void) + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 319 .loc 1 351 0 + 320 .cfi_startproc + 321 @ args = 0, pretend = 0, frame = 0 + 322 @ frame_needed = 0, uses_anonymous_args = 0 + 323 @ link register save eliminated. + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Disable SysTick Interrupt */ + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 324 .loc 1 353 0 + 325 0000 024A ldr r2, .L21 + 326 0002 1368 ldr r3, [r2] + 327 0004 0221 movs r1, #2 + 328 0006 8B43 bics r3, r1 + 329 0008 1360 str r3, [r2] + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 330 .loc 1 354 0 + 331 @ sp needed + ARM GAS /tmp/ccYJZGyl.s page 13 + + + 332 000a 7047 bx lr + 333 .L22: + 334 .align 2 + 335 .L21: + 336 000c 10E000E0 .word -536813552 + 337 .cfi_endproc + 338 .LFE47: + 340 .section .text.HAL_ResumeTick,"ax",%progbits + 341 .align 1 + 342 .weak HAL_ResumeTick + 343 .syntax unified + 344 .code 16 + 345 .thumb_func + 346 .fpu softvfp + 348 HAL_ResumeTick: + 349 .LFB48: + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Resumes the Tick increment. + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * is called, the the SysTick interrupt will be enabled and so Tick increment + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * is resumed. + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * implementations in user file. + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** __weak void HAL_ResumeTick(void) + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 350 .loc 1 367 0 + 351 .cfi_startproc + 352 @ args = 0, pretend = 0, frame = 0 + 353 @ frame_needed = 0, uses_anonymous_args = 0 + 354 @ link register save eliminated. + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Enable SysTick Interrupt */ + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 355 .loc 1 369 0 + 356 0000 024A ldr r2, .L24 + 357 0002 1368 ldr r3, [r2] + 358 0004 0221 movs r1, #2 + 359 0006 0B43 orrs r3, r1 + 360 0008 1360 str r3, [r2] + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 361 .loc 1 370 0 + 362 @ sp needed + 363 000a 7047 bx lr + 364 .L25: + 365 .align 2 + 366 .L24: + 367 000c 10E000E0 .word -536813552 + 368 .cfi_endproc + 369 .LFE48: + 371 .section .text.HAL_GetHalVersion,"ax",%progbits + 372 .align 1 + 373 .global HAL_GetHalVersion + 374 .syntax unified + 375 .code 16 + ARM GAS /tmp/ccYJZGyl.s page 14 + + + 376 .thumb_func + 377 .fpu softvfp + 379 HAL_GetHalVersion: + 380 .LFB49: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Returns the HAL revision + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval version: 0xXYZR (8bits for each decimal, R for RC) + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 381 .loc 1 377 0 + 382 .cfi_startproc + 383 @ args = 0, pretend = 0, frame = 0 + 384 @ frame_needed = 0, uses_anonymous_args = 0 + 385 @ link register save eliminated. + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return __STM32L0xx_HAL_VERSION; + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 386 .loc 1 379 0 + 387 0000 0048 ldr r0, .L27 + 388 @ sp needed + 389 0002 7047 bx lr + 390 .L28: + 391 .align 2 + 392 .L27: + 393 0004 00020801 .word 17302016 + 394 .cfi_endproc + 395 .LFE49: + 397 .section .text.HAL_GetREVID,"ax",%progbits + 398 .align 1 + 399 .global HAL_GetREVID + 400 .syntax unified + 401 .code 16 + 402 .thumb_func + 403 .fpu softvfp + 405 HAL_GetREVID: + 406 .LFB50: + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Returns the device revision identifier. + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval Device revision identifier + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uint32_t HAL_GetREVID(void) + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 407 .loc 1 386 0 + 408 .cfi_startproc + 409 @ args = 0, pretend = 0, frame = 0 + 410 @ frame_needed = 0, uses_anonymous_args = 0 + 411 @ link register save eliminated. + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return((DBGMCU->IDCODE) >> 16U); + 412 .loc 1 387 0 + 413 0000 014B ldr r3, .L30 + 414 0002 1868 ldr r0, [r3] + 415 0004 000C lsrs r0, r0, #16 + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 416 .loc 1 388 0 + 417 @ sp needed + ARM GAS /tmp/ccYJZGyl.s page 15 + + + 418 0006 7047 bx lr + 419 .L31: + 420 .align 2 + 421 .L30: + 422 0008 00580140 .word 1073829888 + 423 .cfi_endproc + 424 .LFE50: + 426 .section .text.HAL_GetDEVID,"ax",%progbits + 427 .align 1 + 428 .global HAL_GetDEVID + 429 .syntax unified + 430 .code 16 + 431 .thumb_func + 432 .fpu softvfp + 434 HAL_GetDEVID: + 435 .LFB51: + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Returns the device identifier. + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval Device identifier + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uint32_t HAL_GetDEVID(void) + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 436 .loc 1 395 0 + 437 .cfi_startproc + 438 @ args = 0, pretend = 0, frame = 0 + 439 @ frame_needed = 0, uses_anonymous_args = 0 + 440 @ link register save eliminated. + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + 441 .loc 1 396 0 + 442 0000 024B ldr r3, .L33 + 443 0002 1868 ldr r0, [r3] + 444 0004 0005 lsls r0, r0, #20 + 445 0006 000D lsrs r0, r0, #20 + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 446 .loc 1 397 0 + 447 @ sp needed + 448 0008 7047 bx lr + 449 .L34: + 450 000a C046 .align 2 + 451 .L33: + 452 000c 00580140 .word 1073829888 + 453 .cfi_endproc + 454 .LFE51: + 456 .section .text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits + 457 .align 1 + 458 .global HAL_DBGMCU_EnableDBGSleepMode + 459 .syntax unified + 460 .code 16 + 461 .thumb_func + 462 .fpu softvfp + 464 HAL_DBGMCU_EnableDBGSleepMode: + 465 .LFB52: + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Enables the Debug Module during SLEEP mode + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + ARM GAS /tmp/ccYJZGyl.s page 16 + + + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void) + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 466 .loc 1 404 0 + 467 .cfi_startproc + 468 @ args = 0, pretend = 0, frame = 0 + 469 @ frame_needed = 0, uses_anonymous_args = 0 + 470 @ link register save eliminated. + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 471 .loc 1 405 0 + 472 0000 024A ldr r2, .L36 + 473 0002 5368 ldr r3, [r2, #4] + 474 0004 0121 movs r1, #1 + 475 0006 0B43 orrs r3, r1 + 476 0008 5360 str r3, [r2, #4] + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 477 .loc 1 406 0 + 478 @ sp needed + 479 000a 7047 bx lr + 480 .L37: + 481 .align 2 + 482 .L36: + 483 000c 00580140 .word 1073829888 + 484 .cfi_endproc + 485 .LFE52: + 487 .section .text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits + 488 .align 1 + 489 .global HAL_DBGMCU_DisableDBGSleepMode + 490 .syntax unified + 491 .code 16 + 492 .thumb_func + 493 .fpu softvfp + 495 HAL_DBGMCU_DisableDBGSleepMode: + 496 .LFB53: + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Disables the Debug Module during SLEEP mode + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void) + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 497 .loc 1 413 0 + 498 .cfi_startproc + 499 @ args = 0, pretend = 0, frame = 0 + 500 @ frame_needed = 0, uses_anonymous_args = 0 + 501 @ link register save eliminated. + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 502 .loc 1 414 0 + 503 0000 024A ldr r2, .L39 + 504 0002 5368 ldr r3, [r2, #4] + 505 0004 0121 movs r1, #1 + 506 0006 8B43 bics r3, r1 + 507 0008 5360 str r3, [r2, #4] + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 508 .loc 1 415 0 + 509 @ sp needed + 510 000a 7047 bx lr + ARM GAS /tmp/ccYJZGyl.s page 17 + + + 511 .L40: + 512 .align 2 + 513 .L39: + 514 000c 00580140 .word 1073829888 + 515 .cfi_endproc + 516 .LFE53: + 518 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 519 .align 1 + 520 .global HAL_DBGMCU_EnableDBGStopMode + 521 .syntax unified + 522 .code 16 + 523 .thumb_func + 524 .fpu softvfp + 526 HAL_DBGMCU_EnableDBGStopMode: + 527 .LFB54: + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Enables the Debug Module during STOP mode + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void) + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 528 .loc 1 422 0 + 529 .cfi_startproc + 530 @ args = 0, pretend = 0, frame = 0 + 531 @ frame_needed = 0, uses_anonymous_args = 0 + 532 @ link register save eliminated. + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 533 .loc 1 423 0 + 534 0000 024A ldr r2, .L42 + 535 0002 5368 ldr r3, [r2, #4] + 536 0004 0221 movs r1, #2 + 537 0006 0B43 orrs r3, r1 + 538 0008 5360 str r3, [r2, #4] + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 539 .loc 1 424 0 + 540 @ sp needed + 541 000a 7047 bx lr + 542 .L43: + 543 .align 2 + 544 .L42: + 545 000c 00580140 .word 1073829888 + 546 .cfi_endproc + 547 .LFE54: + 549 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 550 .align 1 + 551 .global HAL_DBGMCU_DisableDBGStopMode + 552 .syntax unified + 553 .code 16 + 554 .thumb_func + 555 .fpu softvfp + 557 HAL_DBGMCU_DisableDBGStopMode: + 558 .LFB55: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Disables the Debug Module during STOP mode + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + ARM GAS /tmp/ccYJZGyl.s page 18 + + + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void) + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 559 .loc 1 431 0 + 560 .cfi_startproc + 561 @ args = 0, pretend = 0, frame = 0 + 562 @ frame_needed = 0, uses_anonymous_args = 0 + 563 @ link register save eliminated. + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 564 .loc 1 432 0 + 565 0000 024A ldr r2, .L45 + 566 0002 5368 ldr r3, [r2, #4] + 567 0004 0221 movs r1, #2 + 568 0006 8B43 bics r3, r1 + 569 0008 5360 str r3, [r2, #4] + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 570 .loc 1 433 0 + 571 @ sp needed + 572 000a 7047 bx lr + 573 .L46: + 574 .align 2 + 575 .L45: + 576 000c 00580140 .word 1073829888 + 577 .cfi_endproc + 578 .LFE55: + 580 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 581 .align 1 + 582 .global HAL_DBGMCU_EnableDBGStandbyMode + 583 .syntax unified + 584 .code 16 + 585 .thumb_func + 586 .fpu softvfp + 588 HAL_DBGMCU_EnableDBGStandbyMode: + 589 .LFB56: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Enables the Debug Module during STANDBY mode + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void) + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 590 .loc 1 440 0 + 591 .cfi_startproc + 592 @ args = 0, pretend = 0, frame = 0 + 593 @ frame_needed = 0, uses_anonymous_args = 0 + 594 @ link register save eliminated. + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 595 .loc 1 441 0 + 596 0000 024A ldr r2, .L48 + 597 0002 5368 ldr r3, [r2, #4] + 598 0004 0421 movs r1, #4 + 599 0006 0B43 orrs r3, r1 + 600 0008 5360 str r3, [r2, #4] + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 601 .loc 1 442 0 + 602 @ sp needed + 603 000a 7047 bx lr + ARM GAS /tmp/ccYJZGyl.s page 19 + + + 604 .L49: + 605 .align 2 + 606 .L48: + 607 000c 00580140 .word 1073829888 + 608 .cfi_endproc + 609 .LFE56: + 611 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 612 .align 1 + 613 .global HAL_DBGMCU_DisableDBGStandbyMode + 614 .syntax unified + 615 .code 16 + 616 .thumb_func + 617 .fpu softvfp + 619 HAL_DBGMCU_DisableDBGStandbyMode: + 620 .LFB57: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Disables the Debug Module during STANDBY mode + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void) + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 621 .loc 1 449 0 + 622 .cfi_startproc + 623 @ args = 0, pretend = 0, frame = 0 + 624 @ frame_needed = 0, uses_anonymous_args = 0 + 625 @ link register save eliminated. + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 626 .loc 1 450 0 + 627 0000 024A ldr r2, .L51 + 628 0002 5368 ldr r3, [r2, #4] + 629 0004 0421 movs r1, #4 + 630 0006 8B43 bics r3, r1 + 631 0008 5360 str r3, [r2, #4] + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 632 .loc 1 451 0 + 633 @ sp needed + 634 000a 7047 bx lr + 635 .L52: + 636 .align 2 + 637 .L51: + 638 000c 00580140 .word 1073829888 + 639 .cfi_endproc + 640 .LFE57: + 642 .section .text.HAL_DBGMCU_DBG_EnableLowPowerConfig,"ax",%progbits + 643 .align 1 + 644 .global HAL_DBGMCU_DBG_EnableLowPowerConfig + 645 .syntax unified + 646 .code 16 + 647 .thumb_func + 648 .fpu softvfp + 650 HAL_DBGMCU_DBG_EnableLowPowerConfig: + 651 .LFB58: + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Enable low power mode behavior when the MCU is in Debug mode. + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @param Periph: specifies the low power mode. + ARM GAS /tmp/ccYJZGyl.s page 20 + + + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * This parameter can be any combination of the following values: + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph) + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 652 .loc 1 463 0 + 653 .cfi_startproc + 654 @ args = 0, pretend = 0, frame = 0 + 655 @ frame_needed = 0, uses_anonymous_args = 0 + 656 @ link register save eliminated. + 657 .LVL15: + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Check the parameters */ + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** assert_param(IS_DBGMCU_PERIPH(Periph)); + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** DBGMCU->CR |= Periph; + 658 .loc 1 467 0 + 659 0000 024A ldr r2, .L54 + 660 0002 5368 ldr r3, [r2, #4] + 661 0004 1843 orrs r0, r3 + 662 .LVL16: + 663 0006 5060 str r0, [r2, #4] + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 664 .loc 1 469 0 + 665 @ sp needed + 666 0008 7047 bx lr + 667 .L55: + 668 000a C046 .align 2 + 669 .L54: + 670 000c 00580140 .word 1073829888 + 671 .cfi_endproc + 672 .LFE58: + 674 .section .text.HAL_DBGMCU_DBG_DisableLowPowerConfig,"ax",%progbits + 675 .align 1 + 676 .global HAL_DBGMCU_DBG_DisableLowPowerConfig + 677 .syntax unified + 678 .code 16 + 679 .thumb_func + 680 .fpu softvfp + 682 HAL_DBGMCU_DBG_DisableLowPowerConfig: + 683 .LFB59: + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Disable low power mode behavior when the MCU is in Debug mode. + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @param Periph: specifies the low power mode. + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * This parameter can be any combination of the following values: + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph) + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 684 .loc 1 480 0 + 685 .cfi_startproc + ARM GAS /tmp/ccYJZGyl.s page 21 + + + 686 @ args = 0, pretend = 0, frame = 0 + 687 @ frame_needed = 0, uses_anonymous_args = 0 + 688 @ link register save eliminated. + 689 .LVL17: + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Check the parameters */ + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** assert_param(IS_DBGMCU_PERIPH(Periph)); + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** DBGMCU->CR &= ~Periph; + 690 .loc 1 484 0 + 691 0000 024A ldr r2, .L57 + 692 0002 5368 ldr r3, [r2, #4] + 693 0004 8343 bics r3, r0 + 694 0006 5360 str r3, [r2, #4] + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 695 .loc 1 486 0 + 696 @ sp needed + 697 0008 7047 bx lr + 698 .L58: + 699 000a C046 .align 2 + 700 .L57: + 701 000c 00580140 .word 1073829888 + 702 .cfi_endproc + 703 .LFE59: + 705 .section .text.HAL_SYSCFG_GetBootMode,"ax",%progbits + 706 .align 1 + 707 .global HAL_SYSCFG_GetBootMode + 708 .syntax unified + 709 .code 16 + 710 .thumb_func + 711 .fpu softvfp + 713 HAL_SYSCFG_GetBootMode: + 714 .LFB60: + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Returns the boot mode as configured by user. + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval The boot mode as configured by user. The returned value can be one + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * of the following values: + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * - 0x00000000 : Boot is configured in Main Flash memory + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * - 0x00000100 : Boot is configured in System Flash memory + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * - 0x00000300 : Boot is configured in Embedded SRAM memory + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** uint32_t HAL_SYSCFG_GetBootMode(void) + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 715 .loc 1 497 0 + 716 .cfi_startproc + 717 @ args = 0, pretend = 0, frame = 0 + 718 @ frame_needed = 0, uses_anonymous_args = 0 + 719 @ link register save eliminated. + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE); + 720 .loc 1 498 0 + 721 0000 024B ldr r3, .L60 + 722 0002 1868 ldr r0, [r3] + 723 0004 C023 movs r3, #192 + 724 0006 9B00 lsls r3, r3, #2 + 725 0008 1840 ands r0, r3 + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + ARM GAS /tmp/ccYJZGyl.s page 22 + + + 726 .loc 1 499 0 + 727 @ sp needed + 728 000a 7047 bx lr + 729 .L61: + 730 .align 2 + 731 .L60: + 732 000c 00000140 .word 1073807360 + 733 .cfi_endproc + 734 .LFE60: + 736 .section .text.HAL_SYSCFG_VREFINT_OutputSelect,"ax",%progbits + 737 .align 1 + 738 .global HAL_SYSCFG_VREFINT_OutputSelect + 739 .syntax unified + 740 .code 16 + 741 .thumb_func + 742 .fpu softvfp + 744 HAL_SYSCFG_VREFINT_OutputSelect: + 745 .LFB61: + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Selects the output of internal reference voltage (VREFINT). + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * The VREFINT output can be routed to(PB0) or + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * (PB1) or both. + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output. + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * This parameter can be one of the following values: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg SYSCFG_VREFINT_OUT_NONE + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg SYSCFG_VREFINT_OUT_PB0 + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg SYSCFG_VREFINT_OUT_PB1 + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @arg SYSCFG_VREFINT_OUT_PB0_PB1 + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT) + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 746 .loc 1 514 0 + 747 .cfi_startproc + 748 @ args = 0, pretend = 0, frame = 0 + 749 @ frame_needed = 0, uses_anonymous_args = 0 + 750 @ link register save eliminated. + 751 .LVL18: + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Check the parameters */ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** assert_param(IS_SYSCFG_VREFINT_OUT_SELECT(SYSCFG_Vrefint_OUTPUT)); + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Set the output Vrefint pin */ + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SYSCFG->CFGR3 &= ~(SYSCFG_CFGR3_VREF_OUT); + 752 .loc 1 519 0 + 753 0000 044B ldr r3, .L63 + 754 0002 1A6A ldr r2, [r3, #32] + 755 0004 3021 movs r1, #48 + 756 0006 8A43 bics r2, r1 + 757 0008 1A62 str r2, [r3, #32] + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SYSCFG->CFGR3 |= (uint32_t)(SYSCFG_Vrefint_OUTPUT); + 758 .loc 1 520 0 + 759 000a 1A6A ldr r2, [r3, #32] + 760 000c 1043 orrs r0, r2 + 761 .LVL19: + 762 000e 1862 str r0, [r3, #32] + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + ARM GAS /tmp/ccYJZGyl.s page 23 + + + 763 .loc 1 521 0 + 764 @ sp needed + 765 0010 7047 bx lr + 766 .L64: + 767 0012 C046 .align 2 + 768 .L63: + 769 0014 00000140 .word 1073807360 + 770 .cfi_endproc + 771 .LFE61: + 773 .section .text.HAL_SYSCFG_Enable_Lock_VREFINT,"ax",%progbits + 774 .align 1 + 775 .global HAL_SYSCFG_Enable_Lock_VREFINT + 776 .syntax unified + 777 .code 16 + 778 .thumb_func + 779 .fpu softvfp + 781 HAL_SYSCFG_Enable_Lock_VREFINT: + 782 .LFB62: + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Lock the SYSCFG VREF register values + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_SYSCFG_Enable_Lock_VREFINT(void) + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 783 .loc 1 528 0 + 784 .cfi_startproc + 785 @ args = 0, pretend = 0, frame = 0 + 786 @ frame_needed = 0, uses_anonymous_args = 0 + 787 @ link register save eliminated. + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */ + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); + 788 .loc 1 530 0 + 789 0000 034A ldr r2, .L66 + 790 0002 116A ldr r1, [r2, #32] + 791 0004 8023 movs r3, #128 + 792 0006 1B06 lsls r3, r3, #24 + 793 0008 0B43 orrs r3, r1 + 794 000a 1362 str r3, [r2, #32] + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 795 .loc 1 531 0 + 796 @ sp needed + 797 000c 7047 bx lr + 798 .L67: + 799 000e C046 .align 2 + 800 .L66: + 801 0010 00000140 .word 1073807360 + 802 .cfi_endproc + 803 .LFE62: + 805 .section .text.HAL_SYSCFG_Disable_Lock_VREFINT,"ax",%progbits + 806 .align 1 + 807 .global HAL_SYSCFG_Disable_Lock_VREFINT + 808 .syntax unified + 809 .code 16 + 810 .thumb_func + 811 .fpu softvfp + 813 HAL_SYSCFG_Disable_Lock_VREFINT: + ARM GAS /tmp/ccYJZGyl.s page 24 + + + 814 .LFB63: + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @brief Unlock the overall SYSCFG VREF register values + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** * @retval None + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** */ + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** void HAL_SYSCFG_Disable_Lock_VREFINT(void) + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** { + 815 .loc 1 538 0 + 816 .cfi_startproc + 817 @ args = 0, pretend = 0, frame = 0 + 818 @ frame_needed = 0, uses_anonymous_args = 0 + 819 @ link register save eliminated. + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** /* Disable the LOCK by setting REF_LOCK bit in the CFGR3 register */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); + 820 .loc 1 540 0 + 821 0000 024A ldr r2, .L69 + 822 0002 136A ldr r3, [r2, #32] + 823 0004 5B00 lsls r3, r3, #1 + 824 0006 5B08 lsrs r3, r3, #1 + 825 0008 1362 str r3, [r2, #32] + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c **** } + 826 .loc 1 541 0 + 827 @ sp needed + 828 000a 7047 bx lr + 829 .L70: + 830 .align 2 + 831 .L69: + 832 000c 00000140 .word 1073807360 + 833 .cfi_endproc + 834 .LFE63: + 836 .global uwTick + 837 .section .bss.uwTick,"aw",%nobits + 838 .align 2 + 839 .set .LANCHOR0,. + 0 + 842 uwTick: + 843 0000 00000000 .space 4 + 844 .text + 845 .Letext0: + 846 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 847 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 848 .file 4 "Drivers/CMSIS/Include/core_cm0plus.h" + 849 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 850 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 851 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 852 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 853 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 854 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 855 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 856 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + ARM GAS /tmp/ccYJZGyl.s page 25 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal.c + /tmp/ccYJZGyl.s:16 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccYJZGyl.s:23 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccYJZGyl.s:38 .text.HAL_MspDeInit:0000000000000000 $t + /tmp/ccYJZGyl.s:45 .text.HAL_MspDeInit:0000000000000000 HAL_MspDeInit + /tmp/ccYJZGyl.s:59 .text.HAL_DeInit:0000000000000000 $t + /tmp/ccYJZGyl.s:66 .text.HAL_DeInit:0000000000000000 HAL_DeInit + /tmp/ccYJZGyl.s:107 .text.HAL_DeInit:0000000000000024 $d + /tmp/ccYJZGyl.s:113 .text.HAL_InitTick:0000000000000000 $t + /tmp/ccYJZGyl.s:120 .text.HAL_InitTick:0000000000000000 HAL_InitTick + /tmp/ccYJZGyl.s:158 .text.HAL_InitTick:0000000000000024 $d + /tmp/ccYJZGyl.s:163 .text.HAL_Init:0000000000000000 $t + /tmp/ccYJZGyl.s:170 .text.HAL_Init:0000000000000000 HAL_Init + /tmp/ccYJZGyl.s:201 .text.HAL_Init:000000000000001c $d + /tmp/ccYJZGyl.s:206 .text.HAL_IncTick:0000000000000000 $t + /tmp/ccYJZGyl.s:213 .text.HAL_IncTick:0000000000000000 HAL_IncTick + /tmp/ccYJZGyl.s:231 .text.HAL_IncTick:000000000000000c $d + /tmp/ccYJZGyl.s:236 .text.HAL_GetTick:0000000000000000 $t + /tmp/ccYJZGyl.s:243 .text.HAL_GetTick:0000000000000000 HAL_GetTick + /tmp/ccYJZGyl.s:259 .text.HAL_GetTick:0000000000000008 $d + /tmp/ccYJZGyl.s:264 .text.HAL_Delay:0000000000000000 $t + /tmp/ccYJZGyl.s:271 .text.HAL_Delay:0000000000000000 HAL_Delay + /tmp/ccYJZGyl.s:310 .text.HAL_SuspendTick:0000000000000000 $t + /tmp/ccYJZGyl.s:317 .text.HAL_SuspendTick:0000000000000000 HAL_SuspendTick + /tmp/ccYJZGyl.s:336 .text.HAL_SuspendTick:000000000000000c $d + /tmp/ccYJZGyl.s:341 .text.HAL_ResumeTick:0000000000000000 $t + /tmp/ccYJZGyl.s:348 .text.HAL_ResumeTick:0000000000000000 HAL_ResumeTick + /tmp/ccYJZGyl.s:367 .text.HAL_ResumeTick:000000000000000c $d + /tmp/ccYJZGyl.s:372 .text.HAL_GetHalVersion:0000000000000000 $t + /tmp/ccYJZGyl.s:379 .text.HAL_GetHalVersion:0000000000000000 HAL_GetHalVersion + /tmp/ccYJZGyl.s:393 .text.HAL_GetHalVersion:0000000000000004 $d + /tmp/ccYJZGyl.s:398 .text.HAL_GetREVID:0000000000000000 $t + /tmp/ccYJZGyl.s:405 .text.HAL_GetREVID:0000000000000000 HAL_GetREVID + /tmp/ccYJZGyl.s:422 .text.HAL_GetREVID:0000000000000008 $d + /tmp/ccYJZGyl.s:427 .text.HAL_GetDEVID:0000000000000000 $t + /tmp/ccYJZGyl.s:434 .text.HAL_GetDEVID:0000000000000000 HAL_GetDEVID + /tmp/ccYJZGyl.s:452 .text.HAL_GetDEVID:000000000000000c $d + /tmp/ccYJZGyl.s:457 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 $t + /tmp/ccYJZGyl.s:464 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 HAL_DBGMCU_EnableDBGSleepMode + /tmp/ccYJZGyl.s:483 .text.HAL_DBGMCU_EnableDBGSleepMode:000000000000000c $d + /tmp/ccYJZGyl.s:488 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 $t + /tmp/ccYJZGyl.s:495 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 HAL_DBGMCU_DisableDBGSleepMode + /tmp/ccYJZGyl.s:514 .text.HAL_DBGMCU_DisableDBGSleepMode:000000000000000c $d + /tmp/ccYJZGyl.s:519 .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 $t + /tmp/ccYJZGyl.s:526 .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 HAL_DBGMCU_EnableDBGStopMode + /tmp/ccYJZGyl.s:545 .text.HAL_DBGMCU_EnableDBGStopMode:000000000000000c $d + /tmp/ccYJZGyl.s:550 .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 $t + /tmp/ccYJZGyl.s:557 .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 HAL_DBGMCU_DisableDBGStopMode + /tmp/ccYJZGyl.s:576 .text.HAL_DBGMCU_DisableDBGStopMode:000000000000000c $d + /tmp/ccYJZGyl.s:581 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 $t + /tmp/ccYJZGyl.s:588 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 HAL_DBGMCU_EnableDBGStandbyMode + /tmp/ccYJZGyl.s:607 .text.HAL_DBGMCU_EnableDBGStandbyMode:000000000000000c $d + /tmp/ccYJZGyl.s:612 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 $t + /tmp/ccYJZGyl.s:619 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 HAL_DBGMCU_DisableDBGStandbyMode + /tmp/ccYJZGyl.s:638 .text.HAL_DBGMCU_DisableDBGStandbyMode:000000000000000c $d + /tmp/ccYJZGyl.s:643 .text.HAL_DBGMCU_DBG_EnableLowPowerConfig:0000000000000000 $t + ARM GAS /tmp/ccYJZGyl.s page 26 + + + /tmp/ccYJZGyl.s:650 .text.HAL_DBGMCU_DBG_EnableLowPowerConfig:0000000000000000 HAL_DBGMCU_DBG_EnableLowPowerConfig + /tmp/ccYJZGyl.s:670 .text.HAL_DBGMCU_DBG_EnableLowPowerConfig:000000000000000c $d + /tmp/ccYJZGyl.s:675 .text.HAL_DBGMCU_DBG_DisableLowPowerConfig:0000000000000000 $t + /tmp/ccYJZGyl.s:682 .text.HAL_DBGMCU_DBG_DisableLowPowerConfig:0000000000000000 HAL_DBGMCU_DBG_DisableLowPowerConfig + /tmp/ccYJZGyl.s:701 .text.HAL_DBGMCU_DBG_DisableLowPowerConfig:000000000000000c $d + /tmp/ccYJZGyl.s:706 .text.HAL_SYSCFG_GetBootMode:0000000000000000 $t + /tmp/ccYJZGyl.s:713 .text.HAL_SYSCFG_GetBootMode:0000000000000000 HAL_SYSCFG_GetBootMode + /tmp/ccYJZGyl.s:732 .text.HAL_SYSCFG_GetBootMode:000000000000000c $d + /tmp/ccYJZGyl.s:737 .text.HAL_SYSCFG_VREFINT_OutputSelect:0000000000000000 $t + /tmp/ccYJZGyl.s:744 .text.HAL_SYSCFG_VREFINT_OutputSelect:0000000000000000 HAL_SYSCFG_VREFINT_OutputSelect + /tmp/ccYJZGyl.s:769 .text.HAL_SYSCFG_VREFINT_OutputSelect:0000000000000014 $d + /tmp/ccYJZGyl.s:774 .text.HAL_SYSCFG_Enable_Lock_VREFINT:0000000000000000 $t + /tmp/ccYJZGyl.s:781 .text.HAL_SYSCFG_Enable_Lock_VREFINT:0000000000000000 HAL_SYSCFG_Enable_Lock_VREFINT + /tmp/ccYJZGyl.s:801 .text.HAL_SYSCFG_Enable_Lock_VREFINT:0000000000000010 $d + /tmp/ccYJZGyl.s:806 .text.HAL_SYSCFG_Disable_Lock_VREFINT:0000000000000000 $t + /tmp/ccYJZGyl.s:813 .text.HAL_SYSCFG_Disable_Lock_VREFINT:0000000000000000 HAL_SYSCFG_Disable_Lock_VREFINT + /tmp/ccYJZGyl.s:832 .text.HAL_SYSCFG_Disable_Lock_VREFINT:000000000000000c $d + /tmp/ccYJZGyl.s:842 .bss.uwTick:0000000000000000 uwTick + /tmp/ccYJZGyl.s:838 .bss.uwTick:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +HAL_SYSTICK_Config +HAL_NVIC_SetPriority +SystemCoreClock diff --git a/build/stm32l0xx_hal_adc.d b/build/stm32l0xx_hal_adc.d new file mode 100644 index 0000000..29c0d6f --- /dev/null +++ b/build/stm32l0xx_hal_adc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_adc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_adc.lst b/build/stm32l0xx_hal_adc.lst new file mode 100644 index 0000000..1172207 --- /dev/null +++ b/build/stm32l0xx_hal_adc.lst @@ -0,0 +1,5657 @@ +ARM GAS /tmp/ccHnSxqq.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_adc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.ADC_ConversionStop,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 ADC_ConversionStop: + 23 .LFB63: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @file stm32l0xx_hal_adc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief This file provides firmware functions to manage the following + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * functionalities of the Analog to Digital Convertor (ADC) + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ Initialization and Configuration of ADC + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + Operation functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ Start, stop, get result of conversions of regular + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * group, using 3 possible modes: polling, interruption or DMA. + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + Control functions + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ Channels configuration on regular group + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ Analog Watchdog configuration + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + State functions + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ ADC state machine management + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ++ Interrupts and flags management + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Other functions (extended functions) are available in file + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * "stm32l0xx_hal_adc_ex.c". + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @verbatim + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ============================================================================== + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### ADC peripheral features ##### + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ============================================================================== + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Interrupt generation at the end of regular conversion and in case of + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** analog watchdog or overrun events. + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Single and continuous conversion modes. + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Scan mode for conversion of several channels sequentially. + ARM GAS /tmp/ccHnSxqq.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Data alignment with in-built data coherency. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Programmable sampling time (common for all channels) + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) External trigger (timer or EXTI) with configurable polarity + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) DMA request generation for transfer of conversions data of regular group. + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) ADC calibration + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) ADC conversion of regular group. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) ADC supply requirements: 1.62 V to 3.6 V. + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Vdda or to an external voltage reference). + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### How to use this driver ##### + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ============================================================================== + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** *** Configuration of top level parameters related to ADC *** + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ============================================================ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Enable the ADC interface + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) As prerequisite, ADC clock must be configured at RCC top level. + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Caution: On STM32L0, ADC clock frequency max is 16MHz (refer + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** to device datasheet). + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Therefore, ADC clock prescaler must be configured in + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function of ADC clock source frequency to remain below + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** this maximum frequency. + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Two clock settings are mandatory: + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) ADC clock (core clock, also possibly conversion clock). + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) ADC clock (conversions clock). + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Two possible clock sources: synchronous clock derived from APB clock + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** or asynchronous clock derived from ADC dedicated HSI RC oscillator + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** 16MHz. + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** If asynchronous clock is selected, parameter "HSIState" must be set either: + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** always enabled: can be used to supply the main system clock. + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Example: + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Into HAL_ADC_MspInit() (recommended code location) or with + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** other device clock parameters configuration: + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HSI enable (optional: if asynchronous clock + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitTypeDef RCC_OscInitStructure; + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) + ARM GAS /tmp/ccHnSxqq.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC clock source and clock prescaler are configured at ADC level with + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** parameter "ClockPrescaler" using function HAL_ADC_Init(). + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) ADC pins configuration + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Enable the clock for the ADC GPIOs + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using macro __HAL_RCC_GPIOx_CLK_ENABLE() + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Configure these ADC pins in analog mode + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_GPIO_Init() + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, in case of usage of ADC with interruptions: + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Configure the NVIC for ADC + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** into the function of corresponding ADC interruption vector + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADCx_IRQHandler(). + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, in case of usage of DMA: + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Configure the DMA (DMA channel, mode normal or circular, ...) + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_DMA_Init(). + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Configure the NVIC for DMA + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** into the function of corresponding DMA interruption vector + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** DMAx_Channelx_IRQHandler(). + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** *** Configuration of ADC, group regular, channels parameters *** + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ================================================================ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Configure the ADC parameters (resolution, data alignment, ...) + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** and regular group parameters (conversion trigger, sequencer, ...) + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Init(). + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Configure the channels for regular group parameters (channel number, + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** channel rank into sequencer, ..., into regular group) + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_ConfigChannel(). + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, configure the analog watchdog parameters (channels + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** monitored, thresholds, ...) + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_AnalogWDGConfig(). + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) When device is in mode low-power (low-power run, low-power sleep or stop mode), + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init(). + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** In case of internal temperature sensor to be measured: + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** *** Execution of ADC conversions *** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ==================================== + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, perform an automatic ADC calibration to improve the + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** conversion accuracy + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADCEx_Calibration_Start(). + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) ADC driver can be used among three modes: polling, interruption, + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** transfer by DMA. + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC conversion by polling: + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Activate the ADC peripheral and start conversions + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Start() + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Wait for ADC conversion completion + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_PollForConversion() + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Retrieve conversion results + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_GetValue() + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Stop conversion and disable the ADC peripheral + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Stop() + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC conversion by interruption: + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Activate the ADC peripheral and start conversions + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Start_IT() + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Wait for ADC conversion completion by call of function + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ConvCpltCallback() + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (this function must be implemented in user program) + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Retrieve conversion results + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_GetValue() + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Stop conversion and disable the ADC peripheral + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Stop_IT() + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC conversion with transfer by DMA: + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Activate the ADC peripheral and start conversions + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Start_DMA() + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Wait for ADC conversion completion by call of function + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (these functions must be implemented in user program) + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Conversion results are automatically transferred by DMA into + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** destination variable address. + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Stop conversion and disable the ADC peripheral + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_ADC_Stop_DMA() + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (@) Callback functions must be implemented in user program: + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+@) HAL_ADC_ErrorCallback() + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+@) HAL_ADC_ConvCpltCallback() + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+@) HAL_ADC_ConvHalfCpltCallback + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** *** Deinitialization of ADC *** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ============================================================ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Disable the ADC interface + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC clock can be hard reset and disabled at RCC top level. + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Hard reset of ADC peripherals + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) ADC clock disable + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using the equivalent macro/functions as configuration step. + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) Example: + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** Into HAL_ADC_MspDeInit() (recommended code location) or with + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** other device clock parameters configuration: + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + ARM GAS /tmp/ccHnSxqq.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) ADC pins configuration + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Disable the clock for the ADC GPIOs + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using macro __HAL_RCC_GPIOx_CLK_DISABLE() + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, in case of usage of ADC with interruptions: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Disable the NVIC for ADC + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (#) Optionally, in case of usage of DMA: + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Deinitialize the DMA + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_DMA_Init(). + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (++) Disable the NVIC for DMA + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @endverbatim + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ****************************************************************************** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @attention + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Redistribution and use in source and binary forms, with or without modification, + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * are permitted provided that the following conditions are met: + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * this list of conditions and the following disclaimer. + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * this list of conditions and the following disclaimer in the documentation + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * and/or other materials provided with the distribution. + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * may be used to endorse or promote products derived from this software + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * without specific prior written permission. + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ****************************************************************************** + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Includes ------------------------------------------------------------------*/ + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #include "stm32l0xx_hal.h" + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @addtogroup STM32L0xx_HAL_Driver + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC ADC + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief ADC HAL module driver + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #ifdef HAL_ADC_MODULE_ENABLED + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Private typedef -----------------------------------------------------------*/ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Private define ------------------------------------------------------------*/ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Private_Constants ADC Private Constants + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Delay for ADC stabilization time. */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Unit: us */ + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #define ADC_STAB_DELAY_US ((uint32_t) 1U) + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Delay for temperature sensor stabilization time. */ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Unit: us */ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Private macro -------------------------------------------------------------*/ + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Private variables ---------------------------------------------------------*/ + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Private function prototypes -----------------------------------------------*/ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Private_Functions ADC Private Functions + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma); + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DelayMicroSecond(uint32_t microSecond); + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Exported functions ---------------------------------------------------------*/ + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions ADC Exported Functions + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief ADC Initialization and Configuration functions + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @verbatim + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### Initialization and de-initialization functions ##### + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== + ARM GAS /tmp/ccHnSxqq.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] This section provides functions allowing to: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Initialize and configure the ADC. + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) De-initialize the ADC. + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @endverbatim + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Initialize the ADC peripheral and regular group according to + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * parameters specified in structure "ADC_InitTypeDef". + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note As prerequisite, ADC clock must be configured at RCC top level + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * depending on possible clock sources: APB clock of HSI clock. + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * See commented example code below that can be copied and uncommented + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * into HAL_ADC_MspInit(). + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Possibility to update parameters on the fly: + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * coming from ADC state reset. Following calls to this function can + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * be used to reconfigure some parameters of ADC_InitTypeDef + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * structure on the fly, without modifying MSP configuration. If ADC + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * MSP has to be modified again, HAL_ADC_DeInit() must be called + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * before HAL_ADC_Init(). + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * The setting of these parameters is conditioned to ADC state. + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * For parameters constraints, see comments of structure + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * "ADC_InitTypeDef". + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note This function configures the ADC within 2 scopes: scope of entire + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ADC and scope of regular group. For parameters details, see comments + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * of structure "ADC_InitTypeDef". + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note When device is in mode low-power (low-power run, low-power sleep or stop mode), + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init() + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first). + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * In case of internal temperature sensor to be measured: + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly. + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check ADC handle */ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(hadc == NULL) + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + ARM GAS /tmp/ccHnSxqq.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode)); + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime)); + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* at RCC top level depending on both possible clock sources: */ + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* APB clock or HSI clock. */ + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Refer to header of this file for more details on clock enabling procedure*/ + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Actions performed only if ADC is coming from state reset: */ + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Initialization of ADC MSP */ + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - ADC voltage regulator enable */ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(hadc->State == HAL_ADC_STATE_RESET) + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Initialize ADC error code */ + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Allocate lock resource and initialize it */ + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Lock = HAL_UNLOCKED; + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Init the low level hardware */ + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_MspInit(hadc); + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of ADC parameters if previous preliminary actions are */ + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* correctly completed. */ + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* and if there is no conversion on going on regular group (ADC can be */ + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* enabled anyway, in case of call of this function to update a parameter */ + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* on the fly). */ + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) || + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) ) + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL); + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters update conditioned to ADC state: */ + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters that can be updated only when ADC is disabled: */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - ADC clock mode */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - ADC clock prescaler */ + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - ADC Resolution */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_ENABLE(hadc) == RESET) + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Some parameters of this register are not reset, since they are set */ + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by other functions and must be kept in case of usage of this */ + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* function on the fly (update of a parameter of ADC_InitTypeDef */ + ARM GAS /tmp/ccHnSxqq.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* without needing to reconfigure all other ADC groups/channels */ + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* parameters): */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - internal measurement paths: Vbat, temperature sensor, Vref */ + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (set into HAL_ADC_ConfigChannel() ) */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of ADC clock: clock source PCLK or asynchronous with + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** selectable prescaler */ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLOCK_PRESCALER(hadc); + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of ADC: */ + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Resolution */ + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES); + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= hadc->Init.Resolution; + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the Low Frequency mode */ + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode); + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable voltage regulator (if disabled at this step) */ + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADVREGEN bit */ + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR |= ADC_CR_ADVREGEN; + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of ADC: */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Resolution */ + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Data alignment */ + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Scan direction */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - External trigger to start conversion */ + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - External trigger polarity */ + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Continuous conversion mode */ + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - DMA continuous request */ + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Overrun */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - AutoDelay feature */ + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Discontinuous mode */ + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN | + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_SCANDIR | + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_EXTSEL | + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_EXTEN | + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_CONT | + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_DMACFG | + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_OVRMOD | + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_AUTDLY | + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_AUTOFF | + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_DISCEN ); + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= (hadc->Init.DataAlign | + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_SCANDIR(hadc->Init.ScanConvMode) | + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) | + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Overrun | + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable external trigger if trigger selection is different of software */ + ARM GAS /tmp/ccHnSxqq.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* start. */ + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: This configuration keeps the hardware feature of parameter */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* software start. */ + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv | + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.ExternalTrigConvEdge; + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable discontinuous mode only if continuous mode is disabled */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.DiscontinuousConvMode == ENABLE) + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.ContinuousConvMode == DISABLE) + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the selected ADC group regular discontinuous mode */ + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN); + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADC regular group discontinuous was intended to be enabled, */ + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* but ADC regular group modes continuous and sequencer discontinuous */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* cannot be enabled simultaneously. */ + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.OversamplingMode == ENABLE) + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio)); + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift)); + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode)); + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of Oversampler: */ + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Oversampling Ratio */ + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Right bit shift */ + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Triggered mode */ + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR | + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR2_OVSS | + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR2_TOVS ); + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio | + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Oversample.RightBitShift | + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Oversample.TriggeredMode ); + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable OverSampling mode */ + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE; + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE)) + ARM GAS /tmp/ccHnSxqq.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable OverSampling mode if needed */ + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE; + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear the old sampling time */ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR); + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the new sample time */ + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->SMPR |= hadc->Init.SamplingTime; + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear ADC error code */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the ADC state */ + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Deinitialize the ADC peripheral registers to their default reset + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * values, with deinitialization of the ADC MSP. + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note For devices with several ADCs: reset of ADC common registers is done + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * only if all ADCs sharing the same common group are disabled. + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * If this is not the case, reset of these common parameters reset is + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * bypassed without error reporting: it can be the intended behavior in + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * case of reset of a single ADC while the other ADCs sharing the same + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * common group is still running. + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check ADC handle */ + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(hadc == NULL) + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Stop potential conversion on going, on regular group */ + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_ConversionStop(hadc); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC peripheral if conversions are effectively stopped */ + ARM GAS /tmp/ccHnSxqq.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable the ADC peripheral */ + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Disable(hadc); + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if ADC is effectively disabled */ + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status != HAL_ERROR) + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Change ADC state */ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->State = HAL_ADC_STATE_READY; + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of ADC parameters if previous preliminary actions are */ + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* correctly completed. */ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status != HAL_ERROR) + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ========== Reset ADC registers ========== */ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register IER */ + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \ + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP )); + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register ISR */ + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \ + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register CR */ + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable voltage regulator */ + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: Regulator disable useful for power saving */ + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset ADVREGEN bit */ + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR &= ~ADC_CR_ADVREGEN; + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* No action */ + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register CFGR1 */ + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \ + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \ + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \ + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \ + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register CFGR2 */ + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \ + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE ); + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register SMPR */ + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR); + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register TR */ + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT); + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register CALFACT */ + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT); + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register DR */ + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* bits in access mode read only, no direct reset applicable*/ + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset register CALFACT */ + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT); + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ========== Hard reset ADC peripheral ========== */ + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Performs a global reset of the entire ADC peripheral: ADC state is */ + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* forced to a similar state after device power-on. */ + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If needed, copy-paste and uncomment the following reset code into */ + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* */ + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* __HAL_RCC_ADC1_FORCE_RESET() */ + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* __HAL_RCC_ADC1_RELEASE_RESET() */ + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* DeInit the low level hardware */ + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_MspDeInit(hadc); + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to none */ + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->State = HAL_ADC_STATE_RESET; + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Initialize the ADC MSP. + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_MspInit must be implemented in the user file. + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief DeInitialize the ADC MSP. + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + ARM GAS /tmp/ccHnSxqq.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_MspDeInit must be implemented in the user file. + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief ADC IO operation functions + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @verbatim + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### IO operation functions ##### + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] This section provides functions allowing to: + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Start conversion of regular group. + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Stop conversion of regular group. + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Poll for conversion complete on regular group. + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Poll for conversion event. + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Get result of regular channel conversion. + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Start conversion of regular group and enable interruptions. + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Stop conversion of regular group and disable interruptions. + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Handle ADC interrupt request + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Start conversion of regular group and enable DMA transfer. + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Stop conversion of regular group and disable ADC DMA transfer. + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @endverbatim + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Enable ADC, start conversion of regular group. + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Interruptions enabled in this function: None. + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Perform ADC enable and conversion start if no conversion is on going */ + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the ADC peripheral */ + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* performed automatically by hardware. */ + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Enable(hadc); + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Set state bitfield related to regular operation */ + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset ADC all error code fields */ + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC */ + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* operations) */ + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable conversion of regular group. */ + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If software start has been selected, conversion starts immediately. */ + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If external trigger has been selected, conversion will start at next */ + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* trigger event. */ + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR |= ADC_CR_ADSTART; + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = HAL_BUSY; + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Stop ADC conversion of regular group (and injected channels in + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * case of auto_injection mode), disable ADC peripheral. + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 1. Stop potential conversion on going, on ADC group regular */ + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_ConversionStop(hadc); + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC peripheral if conversions are effectively stopped */ + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 2. Disable the ADC peripheral */ + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Disable(hadc); + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if ADC is effectively disabled */ + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Wait for regular group conversion to be completed. + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note ADC conversion flags EOS (end of sequence) and EOC (end of + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * conversion) are cleared by this function, with an exception: + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * if low power feature "LowPowerAutoWait" is enabled, flags are + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * not cleared to not interfere with this feature until data register + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * is read using function HAL_ADC_GetValue(). + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note This function cannot be used in a particular setup: ADC configured + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * in DMA mode and polling for end of each conversion (ADC init + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * In this case, DMA resets the flag EOC and polling cannot be + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * performed on each conversion. Nevertheless, polling can still + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * be performed on the complete sequence (ADC init + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param Timeout: Timeout value in millisecond. + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0; + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tmp_Flag_EOC = 0x00; + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + ARM GAS /tmp/ccHnSxqq.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If end of conversion selected to end of sequence conversions */ + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_Flag_EOC = ADC_FLAG_EOS; + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If end of conversion selected to end of unitary conversion */ + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else /* ADC_EOC_SINGLE_CONV */ + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Verification that ADC configuration is compliant with polling for */ + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* each conversion: */ + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* several ranks and polling for end of each conversion. */ + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* For code simplicity sake, this particular case is generalized to */ + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADC configured in DMA mode and and polling for end of each conversion. */ + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Get tick count */ + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tickstart = HAL_GetTick(); + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Wait until End of unitary conversion or sequence conversions flag is raised */ + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if timeout is disabled (set to infinite wait) */ + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(Timeout != HAL_MAX_DELAY) + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to timeout */ + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_TIMEOUT; + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine */ + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ + ARM GAS /tmp/ccHnSxqq.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If End of Sequence is reached, disable interrupts */ + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADSTART==0 (no conversion on going) */ + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group regular */ + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* HAL_Start_IT(), but is not disabled here because can be used */ + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by overrun IRQ process below. */ + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Change ADC state to error state */ + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear end of conversion flag of regular group if low power feature */ + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* until data register is read using function HAL_ADC_GetValue(). */ + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.LowPowerAutoWait == DISABLE) + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear regular group conversion flag */ + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Poll for ADC event. + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param EventType: the ADC event type. + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * This parameter can be one of the following values: + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @arg ADC_AWD_EVENT: ADC Analog watchdog event + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @arg ADC_OVR_EVENT: ADC Overrun event +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param Timeout: Timeout value in millisecond. +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Indeed, the latter is reset only if hadc->Init.Overrun field is set +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + ARM GAS /tmp/ccHnSxqq.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * by a new converted data as soon as OVR is cleared. +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * To reset OVR flag once the preserved data is retrieved, the user can resort +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeou +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_EVENT_TYPE(EventType)); +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Get tick count */ +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tickstart = HAL_GetTick(); +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check selected event flag */ +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if timeout is disabled (set to infinite wait) */ +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(Timeout != HAL_MAX_DELAY) +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout)) +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to timeout */ +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_TIMEOUT; +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** switch(EventType) +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Analog watchdog (level out of window) event */ +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** case ADC_AWD_EVENT: +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear ADC analog watchdog flag */ +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Overrun event */ +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** default: /* Case ADC_OVR_EVENT */ +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If overrun is set to overwrite previous data, overrun event is not */ +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* considered as an error. */ +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (cf ref manual "Managing conversions without using the DMA and without */ +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* overrun ") */ +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 20 + + +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to overrun */ +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear ADC Overrun flag */ +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Enable ADC, start conversion of regular group with interruption. +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Interruptions enabled in this function according to initialization +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * setting : EOC (end of conversion), EOS (end of sequence), +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * OVR overrun. +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Each of these interruptions has its dedicated callback function. +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note To guarantee a proper reset of all interruptions once all the needed +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * a correct stop of the IT-based conversions. +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * interruption. If required (e.g. in case of oversampling with trigger +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * mode), the user must: +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EO +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * before calling HAL_ADC_Start_IT(). +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Perform ADC enable and conversion start if no conversion is on going */ +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the ADC peripheral */ +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* performed automatically by hardware. */ +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.LowPowerAutoPowerOff != ENABLE) +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Enable(hadc); +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ + ARM GAS /tmp/ccHnSxqq.s page 21 + + +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Set state bitfield related to regular operation */ +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset ADC all error code fields */ +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC */ +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* operations) */ +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable ADC end of conversion interrupt */ +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable ADC overrun interrupt */ +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** switch(hadc->Init.EOCSelection) +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** case ADC_EOC_SEQ_CONV: +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* case ADC_EOC_SINGLE_CONV */ +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** default: +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable conversion of regular group. */ +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If software start has been selected, conversion starts immediately. */ +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If external trigger has been selected, conversion will start at next */ +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* trigger event. */ +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR |= ADC_CR_ADSTART; +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = HAL_BUSY; +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Stop ADC conversion of regular group (and injected group in +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * case of auto_injection mode), disable interrution of +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * end-of-conversion, disable ADC peripheral. +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + ARM GAS /tmp/ccHnSxqq.s page 22 + + +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 1. Stop potential conversion on going, on ADC group regular */ +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_ConversionStop(hadc); +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC peripheral if conversions are effectively stopped */ +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC end of conversion interrupt for regular group */ +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC overrun interrupt */ +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 2. Disable the ADC peripheral */ +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Disable(hadc); +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if ADC is effectively disabled */ +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Interruptions enabled in this function: +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * overrun (if applicable), DMA half transfer, DMA transfer complete. +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Each of these interruptions has its dedicated callback function. +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param pData: Destination Buffer address. +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes) +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Perform ADC enable and conversion start if no conversion is on going */ +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + ARM GAS /tmp/ccHnSxqq.s page 23 + + +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the ADC peripheral */ +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* performed automatically by hardware. */ +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.LowPowerAutoPowerOff != ENABLE) +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Enable(hadc); +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Set state bitfield related to regular operation */ +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset ADC all error code fields */ +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the DMA transfer complete callback */ +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the DMA half transfer complete callback */ +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the DMA error callback */ +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* start (in case of SW start): */ +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC */ +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* operations) */ +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable ADC overrun interrupt */ +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable ADC DMA mode */ +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Start the DMA channel */ +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 24 + + +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable conversion of regular group. */ +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If software start has been selected, conversion starts immediately. */ +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If external trigger has been selected, conversion will start at next */ +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* trigger event. */ +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR |= ADC_CR_ADSTART; +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = HAL_BUSY; +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Stop ADC conversion of regular group (and injected group in +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * case of auto_injection mode), disable ADC DMA transfer, disable +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ADC peripheral. +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Each of these interruptions has its dedicated callback function. +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 1. Stop potential ADC group regular conversion on going */ +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_ConversionStop(hadc); +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC peripheral if conversions are effectively stopped */ +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable the DMA channel (in case of DMA in circular mode or stop */ +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* while DMA transfer is on going) */ +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if DMA channel effectively disabled */ +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status != HAL_OK) +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC overrun interrupt */ +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 25 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* 2. Disable the ADC peripheral */ +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* in memory a potential failing status. */ +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = ADC_Disable(hadc); +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_Disable(hadc); +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if ADC is effectively disabled */ +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (tmp_hal_status == HAL_OK) +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Get ADC regular group conversion result. +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Reading register DR automatically clears ADC flag EOC +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (ADC group regular end of unitary conversion). +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note This function does not clear ADC flag EOS +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (ADC group regular end of sequence conversion). +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Occurrence of flag EOS rising: +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * - If sequencer is composed of 1 rank, flag EOS is equivalent +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * to flag EOC. +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * - If sequencer is composed of several ranks, during the scan +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * sequence flag EOC only is raised, at the end of the scan sequence +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * both flags EOC and EOS are raised. +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * To clear this flag, either use function: +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * model polling: @ref HAL_ADC_PollForConversion() +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval ADC group regular conversion data +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: EOC flag is not cleared here by software because automatically */ +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* cleared by hardware when reading register DR. */ +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 26 + + +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return ADC converted value */ +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return hadc->Instance->DR; +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Handle ADC interrupt request. +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ========== Check End of Conversion flag for regular group ========== */ +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update state machine on conversion status if not in error state */ +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If End of Sequence is reached, disable interrupts */ +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADSTART==0 (no conversion on going) */ +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group regular */ +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* HAL_Start_IT(), but is not disabled here because can be used */ +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by overrun IRQ process below. */ +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Change ADC state to error state */ +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + ARM GAS /tmp/ccHnSxqq.s page 27 + + +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Conversion complete callback */ +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: into callback, to determine if conversion has been triggered */ +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* from EOC or EOS, possibility to use: */ +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ConvCpltCallback(hadc); +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear regular group conversion flag */ +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* conversion flags clear induces the release of the preserved data.*/ +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Therefore, if the preserved data value is needed, it must be */ +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: Management of low power auto-wait enabled: flags must be cleared */ +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by user when fetching ADC conversion data. */ +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* This case is managed in IRQ handler, but this low-power mode */ +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* should not be used with programming model IT or DMA. */ +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Refer to comment of parameter "LowPowerAutoWait". */ +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (hadc->Init.LowPowerAutoWait != ENABLE) +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ========== Check analog watchdog 1 flag ========== */ +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Level out of window 1 callback */ +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_LevelOutOfWindowCallback(hadc); +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear ADC Analog watchdog flag */ +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ========== Check Overrun flag ========== */ +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If overrun is set to overwrite previous data (default setting), */ +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* overrun event is not considered as an error. */ +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* (cf ref manual "Managing conversions without using the DMA and without */ +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* overrun ") */ +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Exception for usage with DMA overrun event always considered as an */ +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* error. */ +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to overrun */ +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear ADC overrun flag */ + ARM GAS /tmp/ccHnSxqq.s page 28 + + +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Error callback */ +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ErrorCallback(hadc); +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear the Overrun flag */ +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Conversion complete callback in non-blocking mode. +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_ConvCpltCallback must be implemented in the user file. +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Conversion DMA half-transfer callback in non-blocking mode. +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Analog watchdog 1 callback in non-blocking mode. +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 29 + + +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief ADC error callback in non-blocking mode +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (ADC conversion with interruption or transfer by DMA). +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note In case of error due to overrun when using ADC with DMA transfer +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * - If needed, restart a new ADC conversion using function +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * "HAL_ADC_Start_DMA()" +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * (this function is also clearing overrun flag) +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** UNUSED(hadc); +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed, +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** function HAL_ADC_ErrorCallback must be implemented in the user file. +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Peripheral Control functions +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @verbatim +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### Peripheral Control functions ##### +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] This section provides functions allowing to: +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Configure channels on regular group +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Configure the analog watchdog +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @endverbatim +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Configure a channel to be assigned to ADC group regular. +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note In case of usage of internal measurement channels: +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * VrefInt/Vlcd(STM32L0x3xx only)/TempSensor. +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Sampling time constraints must be respected (sampling time can be +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * adjusted in function of ADC clock frequency and sampling time +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * setting). +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Refer to device datasheet for timings values, parameters TS_vrefint, +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us). +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * These internal paths can be be disabled using function +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * HAL_ADC_DeInit(). +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Possibility to update parameters on the fly: +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * This function initializes channel into ADC group regular, +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * following calls to this function can be used to reconfigure +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * without resetting the ADC. + ARM GAS /tmp/ccHnSxqq.s page 30 + + +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * The setting of these parameters is conditioned to ADC state: +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Refer to comments of structure "ADC_ChannelConfTypeDef". +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param sConfig: Structure of ADC channel assigned to ADC group regular. +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_CHANNEL(sConfig->Channel)); +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_RANK(sConfig->Rank)); +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters update conditioned to ADC state: */ +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters that can be updated when ADC is disabled or enabled without */ +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* conversion on going on regular group: */ +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Channel number */ +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (sConfig->Rank != ADC_RANK_NONE) +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable selected channels */ +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK); +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */ +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* internal measurement paths enable: If internal channel selected, enable */ +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* dedicated internal buffers and path. */ +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If Temperature sensor channel is selected, then enable the internal */ +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* buffers and path */ +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSO +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR |= ADC_CCR_TSEN; +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Delay for temperature sensor stabilization time */ +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US); +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If VRefInt channel is selected, then enable the internal buffers and path */ +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR |= ADC_CCR_VREFEN; +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If Vlcd channel is selected, then enable the internal buffers and path */ + ARM GAS /tmp/ccHnSxqq.s page 31 + + +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANN +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR |= ADC_CCR_VLCDEN; +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #endif +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Regular sequence configuration */ +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Reset the channel selection register from the selected channel */ +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK)); +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* internal measurement paths disable: If internal channel selected, */ +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* disable dedicated internal buffers and path. */ +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSO +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR &= ~ADC_CCR_TSEN; +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If VRefInt channel is selected, then enable the internal buffers and path */ +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR &= ~ADC_CCR_VREFEN; +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If Vlcd channel is selected, then enable the internal buffers and path */ +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANN +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR &= ~ADC_CCR_VLCDEN; +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** #endif +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Configure the analog watchdog. +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Possibility to update parameters on the fly: +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * This function initializes the selected analog watchdog, successive +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * calls to this function can be used to reconfigure some parameters +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * the ADC. +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * The setting of these parameters is conditioned to ADC state. +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * For parameters constraints, see comments of structure +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * "ADC_AnalogWDGConfTypeDef". +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Analog watchdog thresholds can be modified while ADC conversion +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * is on going. +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * In this case, some constraints must be taken into account: +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * the programmed threshold values are effective from the next +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * ADC EOC (end of unitary conversion). + ARM GAS /tmp/ccHnSxqq.s page 32 + + +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Considering that registers write delay may happen due to +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * bus activity, this might cause an uncertainty on the +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * effective timing of the new programmed threshold values. +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* Analog +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tmpAWDHighThresholdShifted; +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tmpAWDLowThresholdShifted; +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Verify if threshold is within the selected ADC resolution */ +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process locked */ +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_LOCK(hadc); +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters update conditioned to ADC state: */ +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Parameters that can be updated when ADC is disabled or enabled without */ +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* conversion on going on regular group: */ +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Analog watchdog channels */ +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Analog watchdog thresholds */ +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configure ADC Analog watchdog interrupt */ +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(AnalogWDGConfig->ITMode == ENABLE) +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the ADC Analog watchdog interrupt */ +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable the ADC Analog watchdog interrupt */ +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Configuration of analog watchdog: */ +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Set the analog watchdog mode */ +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* - Set the Analog watchdog channel (is not used if watchdog */ +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */ +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_AWDEN | +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_AWDCH); + ARM GAS /tmp/ccHnSxqq.s page 33 + + +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK)); +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Shift the offset in function of the selected ADC resolution: Thresholds */ +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThre +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Clear High & Low high thresholds */ +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT); +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the high threshold */ +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted); +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the low threshold */ +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->TR |= tmpAWDLowThresholdShifted; +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If a conversion is on going on regular group, no update could be done */ +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* on neither of the AWD configuration structure parameters. */ +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmp_hal_status = HAL_ERROR; +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return function status */ +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return tmp_hal_status; +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief ADC Peripheral State functions +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @verbatim +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ##### Peripheral state and errors functions ##### +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** =============================================================================== +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** [..] +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** This subsection provides functions to get in run-time the status of the +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** peripheral. +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Check the ADC state +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (+) Check the ADC error code +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** @endverbatim +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 34 + + +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Return the ADC handle state. +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note ADC state machine is managed by bitfields, ADC status must be +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * compared with states bits. +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * For example: +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval ADC handle state (bitfield on 32 bits) +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return ADC handle state */ +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return hadc->State; +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Return the ADC error code. +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval ADC error code (bitfield on 32 bits) +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return hadc->ErrorCode; +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @} +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** @defgroup ADC_Private_Functions ADC Private Functions +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @{ +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Enable the selected ADC. +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Prerequisite condition to use this function: ADC must be disabled +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * and voltage regulator must be enabled (done into HAL_ADC_Init()). +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note If low power mode AutoPowerOff is enabled, power-on/off phases are +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * performed automatically by hardware. +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * In this mode, this function is useless and must not be called because +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * flag ADC_FLAG_RDY is not usable. +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * Therefore, this function must be called under condition of +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ + ARM GAS /tmp/ccHnSxqq.s page 35 + + +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* enabling phase not yet completed: flag ADC ready not yet set). */ +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* causes: ADC clock not running, ...). */ +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_ENABLE(hadc) == RESET) +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if conditions to enable the ADC are fulfilled */ +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_ENABLING_CONDITIONS(hadc) == RESET) +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Enable the ADC peripheral */ +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE(hadc); +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Delay for ADC stabilization time. */ +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_DelayMicroSecond(ADC_STAB_DELAY_US); +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Get tick count */ +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tickstart = HAL_GetTick(); +1946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Wait for ADC effectively enabled */ +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; +1959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return HAL status */ +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Disable the selected ADC. +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Prerequisite condition to use this function: ADC conversions must be +1970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * stopped. +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. + ARM GAS /tmp/ccHnSxqq.s page 36 + + +1973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Verification if ADC is not already disabled: */ +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* disabled. */ +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_ENABLE(hadc) != RESET) +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check if conditions to disable the ADC are fulfilled */ +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_DISABLING_CONDITIONS(hadc) != RESET) +1985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable the ADC peripheral */ +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE(hadc); +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +1990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; +1998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +1999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Wait for ADC effectively disabled */ +2001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Get tick count */ +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tickstart = HAL_GetTick(); +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) +2007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return HAL status */ +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Stop ADC conversion. +2026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @note Prerequisite condition to use this function: ADC conversions must be +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * stopped to disable the ADC. +2028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hadc: ADC handle +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval HAL status. + ARM GAS /tmp/ccHnSxqq.s page 37 + + +2030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 25 .loc 1 2032 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 70B5 push {r4, r5, r6, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 16 + 33 .cfi_offset 4, -16 + 34 .cfi_offset 5, -12 + 35 .cfi_offset 6, -8 + 36 .cfi_offset 14, -4 + 37 0002 0400 movs r4, r0 + 38 .LVL1: +2033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Verification if ADC is not already stopped on regular group to bypass */ +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* this function if not needed. */ +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + 39 .loc 1 2040 0 + 40 0004 0368 ldr r3, [r0] + 41 0006 9A68 ldr r2, [r3, #8] + 42 0008 5207 lsls r2, r2, #29 + 43 000a 21D5 bpl .L6 +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Stop potential conversion on going on regular group */ +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && + 44 .loc 1 2045 0 + 45 000c 9A68 ldr r2, [r3, #8] + 46 000e 5207 lsls r2, r2, #29 + 47 0010 06D5 bpl .L3 +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + 48 .loc 1 2046 0 discriminator 1 + 49 0012 9A68 ldr r2, [r3, #8] +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + 50 .loc 1 2045 0 discriminator 1 + 51 0014 9207 lsls r2, r2, #30 + 52 0016 03D4 bmi .L3 +2047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Stop conversions on regular group */ +2049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CR |= ADC_CR_ADSTP; + 53 .loc 1 2049 0 + 54 0018 9A68 ldr r2, [r3, #8] + 55 001a 1021 movs r1, #16 + 56 001c 0A43 orrs r2, r1 + 57 001e 9A60 str r2, [r3, #8] + 58 .L3: +2050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 38 + + +2052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Wait for conversion effectively stopped */ +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Get tick count */ +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tickstart = HAL_GetTick(); + 59 .loc 1 2054 0 + 60 0020 FFF7FEFF bl HAL_GetTick + 61 .LVL2: + 62 0024 0500 movs r5, r0 + 63 .LVL3: + 64 .L4: +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) + 65 .loc 1 2056 0 + 66 0026 2368 ldr r3, [r4] + 67 0028 9B68 ldr r3, [r3, #8] + 68 002a 5B07 lsls r3, r3, #29 + 69 002c 0ED5 bpl .L7 +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + 70 .loc 1 2058 0 + 71 002e FFF7FEFF bl HAL_GetTick + 72 .LVL4: + 73 0032 401B subs r0, r0, r5 + 74 0034 0A28 cmp r0, #10 + 75 0036 F6D9 bls .L4 +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update ADC state machine to error */ +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 76 .loc 1 2061 0 + 77 0038 A36D ldr r3, [r4, #88] + 78 003a 1022 movs r2, #16 + 79 003c 1343 orrs r3, r2 + 80 003e A365 str r3, [r4, #88] +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 81 .loc 1 2064 0 + 82 0040 E36D ldr r3, [r4, #92] + 83 0042 0F3A subs r2, r2, #15 + 84 0044 1343 orrs r3, r2 + 85 0046 E365 str r3, [r4, #92] +2065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 86 .loc 1 2066 0 + 87 0048 0120 movs r0, #1 + 88 004a 02E0 b .L2 + 89 .L7: +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Return HAL status */ +2073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_OK; + 90 .loc 1 2073 0 + 91 004c 0020 movs r0, #0 + 92 004e 00E0 b .L2 + 93 .LVL5: + ARM GAS /tmp/ccHnSxqq.s page 39 + + + 94 .L6: + 95 0050 0020 movs r0, #0 + 96 .LVL6: + 97 .L2: +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 98 .loc 1 2074 0 + 99 @ sp needed + 100 .LVL7: + 101 0052 70BD pop {r4, r5, r6, pc} + 102 .cfi_endproc + 103 .LFE63: + 105 .section .text.ADC_Disable,"ax",%progbits + 106 .align 1 + 107 .syntax unified + 108 .code 16 + 109 .thumb_func + 110 .fpu softvfp + 112 ADC_Disable: + 113 .LFB62: +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; + 114 .loc 1 1975 0 + 115 .cfi_startproc + 116 @ args = 0, pretend = 0, frame = 0 + 117 @ frame_needed = 0, uses_anonymous_args = 0 + 118 .LVL8: + 119 0000 70B5 push {r4, r5, r6, lr} + 120 .LCFI1: + 121 .cfi_def_cfa_offset 16 + 122 .cfi_offset 4, -16 + 123 .cfi_offset 5, -12 + 124 .cfi_offset 6, -8 + 125 .cfi_offset 14, -4 + 126 0002 0400 movs r4, r0 + 127 .LVL9: +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 128 .loc 1 1981 0 + 129 0004 0268 ldr r2, [r0] + 130 0006 9168 ldr r1, [r2, #8] + 131 0008 0323 movs r3, #3 + 132 000a 0B40 ands r3, r1 + 133 000c 012B cmp r3, #1 + 134 000e 01D0 beq .L15 +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 135 .loc 1 2020 0 + 136 0010 0020 movs r0, #0 + 137 .LVL10: + 138 .L9: +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 139 .loc 1 2021 0 + 140 @ sp needed + 141 .LVL11: + 142 0012 70BD pop {r4, r5, r6, pc} + 143 .LVL12: + 144 .L15: +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 145 .loc 1 1981 0 discriminator 1 + 146 0014 1368 ldr r3, [r2] + ARM GAS /tmp/ccHnSxqq.s page 40 + + + 147 0016 DB07 lsls r3, r3, #31 + 148 0018 2DD5 bpl .L14 +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 149 .loc 1 1984 0 + 150 001a 9168 ldr r1, [r2, #8] + 151 001c 0523 movs r3, #5 + 152 001e 0B40 ands r3, r1 + 153 0020 012B cmp r3, #1 + 154 0022 09D0 beq .L16 +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 155 .loc 1 1992 0 + 156 0024 836D ldr r3, [r0, #88] + 157 0026 1022 movs r2, #16 + 158 0028 1343 orrs r3, r2 + 159 002a 8365 str r3, [r0, #88] +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 160 .loc 1 1995 0 + 161 002c C36D ldr r3, [r0, #92] + 162 002e 0F3A subs r2, r2, #15 + 163 0030 1343 orrs r3, r2 + 164 0032 C365 str r3, [r0, #92] +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 165 .loc 1 1997 0 + 166 0034 0120 movs r0, #1 + 167 .LVL13: + 168 0036 ECE7 b .L9 + 169 .LVL14: + 170 .L16: +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 171 .loc 1 1987 0 + 172 0038 9368 ldr r3, [r2, #8] + 173 003a 0221 movs r1, #2 + 174 003c 0B43 orrs r3, r1 + 175 003e 9360 str r3, [r2, #8] + 176 0040 0368 ldr r3, [r0] + 177 0042 0322 movs r2, #3 + 178 0044 1A60 str r2, [r3] +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 179 .loc 1 2002 0 + 180 0046 FFF7FEFF bl HAL_GetTick + 181 .LVL15: + 182 004a 0500 movs r5, r0 + 183 .LVL16: + 184 .L11: +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 185 .loc 1 2004 0 + 186 004c 2368 ldr r3, [r4] + 187 004e 9B68 ldr r3, [r3, #8] + 188 0050 DB07 lsls r3, r3, #31 + 189 0052 0ED5 bpl .L17 +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 190 .loc 1 2006 0 + 191 0054 FFF7FEFF bl HAL_GetTick + 192 .LVL17: + 193 0058 401B subs r0, r0, r5 + 194 005a 0A28 cmp r0, #10 + 195 005c F6D9 bls .L11 + ARM GAS /tmp/ccHnSxqq.s page 41 + + +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 196 .loc 1 2009 0 + 197 005e A36D ldr r3, [r4, #88] + 198 0060 1022 movs r2, #16 + 199 0062 1343 orrs r3, r2 + 200 0064 A365 str r3, [r4, #88] +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 201 .loc 1 2012 0 + 202 0066 E36D ldr r3, [r4, #92] + 203 0068 0F3A subs r2, r2, #15 + 204 006a 1343 orrs r3, r2 + 205 006c E365 str r3, [r4, #92] +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 206 .loc 1 2014 0 + 207 006e 0120 movs r0, #1 + 208 0070 CFE7 b .L9 + 209 .L17: +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 210 .loc 1 2020 0 + 211 0072 0020 movs r0, #0 + 212 0074 CDE7 b .L9 + 213 .LVL18: + 214 .L14: + 215 0076 0020 movs r0, #0 + 216 .LVL19: + 217 0078 CBE7 b .L9 + 218 .cfi_endproc + 219 .LFE62: + 221 .global __aeabi_uidiv + 222 .section .text.ADC_Enable,"ax",%progbits + 223 .align 1 + 224 .syntax unified + 225 .code 16 + 226 .thumb_func + 227 .fpu softvfp + 229 ADC_Enable: + 230 .LFB61: +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; + 231 .loc 1 1917 0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 8 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 .LVL20: + 236 0000 30B5 push {r4, r5, lr} + 237 .LCFI2: + 238 .cfi_def_cfa_offset 12 + 239 .cfi_offset 4, -12 + 240 .cfi_offset 5, -8 + 241 .cfi_offset 14, -4 + 242 0002 83B0 sub sp, sp, #12 + 243 .LCFI3: + 244 .cfi_def_cfa_offset 24 + 245 0004 0400 movs r4, r0 + 246 .LVL21: +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 247 .loc 1 1924 0 + 248 0006 0368 ldr r3, [r0] + ARM GAS /tmp/ccHnSxqq.s page 42 + + + 249 0008 9968 ldr r1, [r3, #8] + 250 000a 0322 movs r2, #3 + 251 000c 0A40 ands r2, r1 + 252 000e 012A cmp r2, #1 + 253 0010 0ED0 beq .L27 + 254 .L19: +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 255 .loc 1 1927 0 + 256 0012 9968 ldr r1, [r3, #8] + 257 0014 1D4A ldr r2, .L30 + 258 0016 1142 tst r1, r2 + 259 0018 0FD1 bne .L28 +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 260 .loc 1 1939 0 + 261 001a 9A68 ldr r2, [r3, #8] + 262 001c 0121 movs r1, #1 + 263 001e 0A43 orrs r2, r1 + 264 0020 9A60 str r2, [r3, #8] + 265 .LVL22: + 266 .LBB6: + 267 .LBB7: +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief DMA transfer complete callback. +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hdma: pointer to DMA handle. +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +2081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +2082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Update state machine on conversion status if not in error state */ +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ +2094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* If End of Sequence is reached, disable interrupts */ +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) +2100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ +2102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* ADSTART==0 (no conversion on going) */ +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group regular */ +2106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ +2107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* HAL_Start_IT(), but is not disabled here because can be used */ +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* by overrun IRQ process below. */ +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 43 + + +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, +2114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY); +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +2117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Change ADC state to error state */ +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Conversion complete callback */ +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ConvCpltCallback(hadc); +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** else +2131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Call DMA error callback */ +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->DMA_Handle->XferErrorCallback(hdma); +2134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief DMA half transfer complete callback. +2139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hdma: pointer to DMA handle. +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Half conversion callback */ +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ConvHalfCpltCallback(hadc); +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief DMA error callback. +2153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param hdma: pointer to DMA handle. +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma) +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC state */ +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set ADC error code to DMA error */ +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Error callback */ + ARM GAS /tmp/ccHnSxqq.s page 44 + + +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_ErrorCallback(hadc); +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /** +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @brief Delay micro seconds +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @param microSecond : delay +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** * @retval None +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** */ +2176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** static void ADC_DelayMicroSecond(uint32_t microSecond) +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Compute number of CPU cycles to wait for */ +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U)); + 268 .loc 1 2179 0 + 269 0022 1B4B ldr r3, .L30+4 + 270 0024 1868 ldr r0, [r3] + 271 .LVL23: + 272 0026 1B49 ldr r1, .L30+8 + 273 0028 FFF7FEFF bl __aeabi_uidiv + 274 .LVL24: + 275 002c 0190 str r0, [sp, #4] + 276 002e 12E0 b .L22 + 277 .LVL25: + 278 .L27: + 279 .LBE7: + 280 .LBE6: +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 281 .loc 1 1924 0 discriminator 1 + 282 0030 1A68 ldr r2, [r3] + 283 0032 D207 lsls r2, r2, #31 + 284 0034 EDD5 bpl .L19 +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 285 .loc 1 1964 0 + 286 0036 0020 movs r0, #0 + 287 .LVL26: + 288 0038 08E0 b .L20 + 289 .LVL27: + 290 .L28: +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 291 .loc 1 1930 0 + 292 003a A36D ldr r3, [r4, #88] + 293 003c 1022 movs r2, #16 + 294 003e 1343 orrs r3, r2 + 295 0040 A365 str r3, [r4, #88] +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 296 .loc 1 1933 0 + 297 0042 E36D ldr r3, [r4, #92] + 298 0044 0F3A subs r2, r2, #15 + 299 0046 1343 orrs r3, r2 + 300 0048 E365 str r3, [r4, #92] +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 301 .loc 1 1935 0 + 302 004a 0120 movs r0, #1 + 303 .LVL28: + 304 .L20: +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 305 .loc 1 1965 0 + 306 004c 03B0 add sp, sp, #12 + ARM GAS /tmp/ccHnSxqq.s page 45 + + + 307 @ sp needed + 308 .LVL29: + 309 004e 30BD pop {r4, r5, pc} + 310 .LVL30: + 311 .L23: + 312 .LBB9: + 313 .LBB8: +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** while(waitLoopIndex != 0U) +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** waitLoopIndex--; + 314 .loc 1 2183 0 + 315 0050 019B ldr r3, [sp, #4] + 316 0052 013B subs r3, r3, #1 + 317 0054 0193 str r3, [sp, #4] + 318 .L22: +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 319 .loc 1 2181 0 + 320 0056 019B ldr r3, [sp, #4] + 321 0058 002B cmp r3, #0 + 322 005a F9D1 bne .L23 + 323 .LVL31: + 324 .LBE8: + 325 .LBE9: +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 326 .loc 1 1945 0 + 327 005c FFF7FEFF bl HAL_GetTick + 328 .LVL32: + 329 0060 0500 movs r5, r0 + 330 .LVL33: + 331 .L24: +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 332 .loc 1 1948 0 + 333 0062 2368 ldr r3, [r4] + 334 0064 1B68 ldr r3, [r3] + 335 0066 DB07 lsls r3, r3, #31 + 336 0068 0ED4 bmi .L29 +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 337 .loc 1 1950 0 + 338 006a FFF7FEFF bl HAL_GetTick + 339 .LVL34: + 340 006e 401B subs r0, r0, r5 + 341 0070 0A28 cmp r0, #10 + 342 0072 F6D9 bls .L24 +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 343 .loc 1 1953 0 + 344 0074 A36D ldr r3, [r4, #88] + 345 0076 1022 movs r2, #16 + 346 0078 1343 orrs r3, r2 + 347 007a A365 str r3, [r4, #88] +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 348 .loc 1 1956 0 + 349 007c E36D ldr r3, [r4, #92] + 350 007e 0F3A subs r2, r2, #15 + 351 0080 1343 orrs r3, r2 + 352 0082 E365 str r3, [r4, #92] +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + ARM GAS /tmp/ccHnSxqq.s page 46 + + + 353 .loc 1 1958 0 + 354 0084 0120 movs r0, #1 + 355 0086 E1E7 b .L20 + 356 .L29: +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 357 .loc 1 1964 0 + 358 0088 0020 movs r0, #0 + 359 008a DFE7 b .L20 + 360 .L31: + 361 .align 2 + 362 .L30: + 363 008c 17000080 .word -2147483625 + 364 0090 00000000 .word SystemCoreClock + 365 0094 40420F00 .word 1000000 + 366 .cfi_endproc + 367 .LFE61: + 369 .section .text.HAL_ADC_MspInit,"ax",%progbits + 370 .align 1 + 371 .weak HAL_ADC_MspInit + 372 .syntax unified + 373 .code 16 + 374 .thumb_func + 375 .fpu softvfp + 377 HAL_ADC_MspInit: + 378 .LFB41: + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 379 .loc 1 707 0 + 380 .cfi_startproc + 381 @ args = 0, pretend = 0, frame = 0 + 382 @ frame_needed = 0, uses_anonymous_args = 0 + 383 @ link register save eliminated. + 384 .LVL35: + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 385 .loc 1 714 0 + 386 @ sp needed + 387 0000 7047 bx lr + 388 .cfi_endproc + 389 .LFE41: + 391 .section .text.HAL_ADC_Init,"ax",%progbits + 392 .align 1 + 393 .global HAL_ADC_Init + 394 .syntax unified + 395 .code 16 + 396 .thumb_func + 397 .fpu softvfp + 399 HAL_ADC_Init: + 400 .LFB39: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 401 .loc 1 356 0 + 402 .cfi_startproc + 403 @ args = 0, pretend = 0, frame = 0 + 404 @ frame_needed = 0, uses_anonymous_args = 0 + 405 .LVL36: + 406 0000 70B5 push {r4, r5, r6, lr} + 407 .LCFI4: + 408 .cfi_def_cfa_offset 16 + 409 .cfi_offset 4, -16 + ARM GAS /tmp/ccHnSxqq.s page 47 + + + 410 .cfi_offset 5, -12 + 411 .cfi_offset 6, -8 + 412 .cfi_offset 14, -4 + 413 0002 041E subs r4, r0, #0 + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 414 .loc 1 359 0 + 415 0004 00D1 bne .LCB377 + 416 0006 DCE0 b .L50 @long jump + 417 .LCB377: + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 418 .loc 1 391 0 + 419 0008 836D ldr r3, [r0, #88] + 420 000a 002B cmp r3, #0 + 421 000c 2ED0 beq .L51 + 422 .LVL37: + 423 .L35: + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) ) + 424 .loc 1 408 0 + 425 000e A36D ldr r3, [r4, #88] + 426 0010 DB06 lsls r3, r3, #27 + 427 0012 31D4 bmi .L36 + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 428 .loc 1 409 0 discriminator 1 + 429 0014 2168 ldr r1, [r4] + 430 0016 8B68 ldr r3, [r1, #8] + 431 0018 0422 movs r2, #4 + 432 001a 1A40 ands r2, r3 + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) ) + 433 .loc 1 408 0 discriminator 1 + 434 001c 2CD1 bne .L36 + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 435 .loc 1 420 0 + 436 001e A36D ldr r3, [r4, #88] + 437 0020 6948 ldr r0, .L56 + 438 0022 0340 ands r3, r0 + 439 0024 0630 adds r0, r0, #6 + 440 0026 FF30 adds r0, r0, #255 + 441 0028 0343 orrs r3, r0 + 442 002a A365 str r3, [r4, #88] + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 443 .loc 1 429 0 + 444 002c 8868 ldr r0, [r1, #8] + 445 002e 0323 movs r3, #3 + 446 0030 0340 ands r3, r0 + 447 0032 012B cmp r3, #1 + 448 0034 29D0 beq .L52 + 449 .L38: + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 450 .loc 1 441 0 + 451 0036 6368 ldr r3, [r4, #4] + 452 0038 C020 movs r0, #192 + 453 003a 0006 lsls r0, r0, #24 + 454 003c 8342 cmp r3, r0 + 455 003e 28D0 beq .L40 + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 456 .loc 1 441 0 is_stmt 0 discriminator 2 + 457 0040 8020 movs r0, #128 + ARM GAS /tmp/ccHnSxqq.s page 48 + + + 458 0042 C005 lsls r0, r0, #23 + 459 0044 8342 cmp r3, r0 + 460 0046 24D0 beq .L40 + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 461 .loc 1 441 0 discriminator 4 + 462 0048 8020 movs r0, #128 + 463 004a 0006 lsls r0, r0, #24 + 464 004c 8342 cmp r3, r0 + 465 004e 20D0 beq .L40 + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 466 .loc 1 441 0 discriminator 6 + 467 0050 0B69 ldr r3, [r1, #16] + 468 0052 9B00 lsls r3, r3, #2 + 469 0054 9B08 lsrs r3, r3, #2 + 470 0056 0B61 str r3, [r1, #16] + 471 0058 5C4B ldr r3, .L56+4 + 472 005a 1968 ldr r1, [r3] + 473 005c 5C48 ldr r0, .L56+8 + 474 005e 0140 ands r1, r0 + 475 0060 1960 str r1, [r3] + 476 0062 1968 ldr r1, [r3] + 477 0064 6068 ldr r0, [r4, #4] + 478 0066 0143 orrs r1, r0 + 479 0068 1960 str r1, [r3] + 480 006a 1BE0 b .L42 + 481 .LVL38: + 482 .L51: + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 483 .loc 1 394 0 is_stmt 1 + 484 006c C365 str r3, [r0, #92] + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 485 .loc 1 397 0 + 486 006e 5422 movs r2, #84 + 487 0070 8354 strb r3, [r0, r2] + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 488 .loc 1 400 0 + 489 0072 FFF7FEFF bl HAL_ADC_MspInit + 490 .LVL39: + 491 0076 CAE7 b .L35 + 492 .L36: + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 493 .loc 1 412 0 + 494 0078 A36D ldr r3, [r4, #88] + 495 007a 1022 movs r2, #16 + 496 007c 1343 orrs r3, r2 + 497 007e A365 str r3, [r4, #88] + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 498 .loc 1 415 0 + 499 0080 5423 movs r3, #84 + 500 0082 0022 movs r2, #0 + 501 0084 E254 strb r2, [r4, r3] + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 502 .loc 1 416 0 + 503 0086 0120 movs r0, #1 + 504 .L34: + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 505 .loc 1 571 0 + ARM GAS /tmp/ccHnSxqq.s page 49 + + + 506 @ sp needed + 507 .LVL40: + 508 0088 70BD pop {r4, r5, r6, pc} + 509 .LVL41: + 510 .L52: + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 511 .loc 1 429 0 discriminator 1 + 512 008a 0B68 ldr r3, [r1] + 513 008c DB07 lsls r3, r3, #31 + 514 008e 13D4 bmi .L39 + 515 0090 D1E7 b .L38 + 516 .L40: + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 517 .loc 1 441 0 discriminator 5 + 518 0092 0B69 ldr r3, [r1, #16] + 519 0094 9B00 lsls r3, r3, #2 + 520 0096 9B08 lsrs r3, r3, #2 + 521 0098 0B61 str r3, [r1, #16] + 522 009a 2168 ldr r1, [r4] + 523 009c 0B69 ldr r3, [r1, #16] + 524 009e 6068 ldr r0, [r4, #4] + 525 00a0 0343 orrs r3, r0 + 526 00a2 0B61 str r3, [r1, #16] + 527 .L42: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Instance->CFGR1 |= hadc->Init.Resolution; + 528 .loc 1 445 0 + 529 00a4 2168 ldr r1, [r4] + 530 00a6 CB68 ldr r3, [r1, #12] + 531 00a8 1820 movs r0, #24 + 532 00aa 8343 bics r3, r0 + 533 00ac CB60 str r3, [r1, #12] + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 534 .loc 1 446 0 + 535 00ae 2168 ldr r1, [r4] + 536 00b0 CB68 ldr r3, [r1, #12] + 537 00b2 A068 ldr r0, [r4, #8] + 538 00b4 0343 orrs r3, r0 + 539 00b6 CB60 str r3, [r1, #12] + 540 .L39: + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode); + 541 .loc 1 450 0 + 542 00b8 444B ldr r3, .L56+4 + 543 00ba 1968 ldr r1, [r3] + 544 00bc 4548 ldr r0, .L56+12 + 545 00be 0140 ands r1, r0 + 546 00c0 1960 str r1, [r3] + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 547 .loc 1 451 0 + 548 00c2 1968 ldr r1, [r3] + 549 00c4 A06B ldr r0, [r4, #56] + 550 00c6 4006 lsls r0, r0, #25 + 551 00c8 0143 orrs r1, r0 + 552 00ca 1960 str r1, [r3] + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 553 .loc 1 454 0 + 554 00cc 2368 ldr r3, [r4] + 555 00ce 9968 ldr r1, [r3, #8] + ARM GAS /tmp/ccHnSxqq.s page 50 + + + 556 00d0 C900 lsls r1, r1, #3 + 557 00d2 04D4 bmi .L43 + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 558 .loc 1 457 0 + 559 00d4 9868 ldr r0, [r3, #8] + 560 00d6 8021 movs r1, #128 + 561 00d8 4905 lsls r1, r1, #21 + 562 00da 0143 orrs r1, r0 + 563 00dc 9960 str r1, [r3, #8] + 564 .L43: + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_SCANDIR | + 565 .loc 1 471 0 + 566 00de 2168 ldr r1, [r4] + 567 00e0 CB68 ldr r3, [r1, #12] + 568 00e2 3D48 ldr r0, .L56+16 + 569 00e4 0340 ands r3, r0 + 570 00e6 CB60 str r3, [r1, #12] + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_SCANDIR(hadc->Init.ScanConvMode) | + 571 .loc 1 482 0 + 572 00e8 2068 ldr r0, [r4] + 573 00ea C168 ldr r1, [r0, #12] + 574 00ec E368 ldr r3, [r4, #12] + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | + 575 .loc 1 483 0 + 576 00ee 2569 ldr r5, [r4, #16] + 577 00f0 022D cmp r5, #2 + 578 00f2 2AD0 beq .L53 + 579 .L44: + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_SCANDIR(hadc->Init.ScanConvMode) | + 580 .loc 1 482 0 + 581 00f4 1343 orrs r3, r2 + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) | + 582 .loc 1 484 0 + 583 00f6 226A ldr r2, [r4, #32] + 584 00f8 5203 lsls r2, r2, #13 + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | + 585 .loc 1 483 0 + 586 00fa 1343 orrs r3, r2 + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Overrun | + 587 .loc 1 485 0 + 588 00fc 226B ldr r2, [r4, #48] + 589 00fe 5200 lsls r2, r2, #1 + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) | + 590 .loc 1 484 0 + 591 0100 1343 orrs r3, r2 + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Overrun | + 592 .loc 1 485 0 + 593 0102 626B ldr r2, [r4, #52] + 594 0104 1343 orrs r3, r2 + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); + 595 .loc 1 487 0 + 596 0106 A269 ldr r2, [r4, #24] + 597 0108 9203 lsls r2, r2, #14 + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | + 598 .loc 1 486 0 + 599 010a 1343 orrs r3, r2 + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + ARM GAS /tmp/ccHnSxqq.s page 51 + + + 600 .loc 1 488 0 + 601 010c E269 ldr r2, [r4, #28] + 602 010e D203 lsls r2, r2, #15 + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); + 603 .loc 1 487 0 + 604 0110 1343 orrs r3, r2 + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_SCANDIR(hadc->Init.ScanConvMode) | + 605 .loc 1 482 0 + 606 0112 0B43 orrs r3, r1 + 607 0114 C360 str r3, [r0, #12] + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 608 .loc 1 495 0 + 609 0116 A36A ldr r3, [r4, #40] + 610 0118 C222 movs r2, #194 + 611 011a FF32 adds r2, r2, #255 + 612 011c 9342 cmp r3, r2 + 613 011e 05D0 beq .L45 + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.ExternalTrigConvEdge; + 614 .loc 1 497 0 + 615 0120 2168 ldr r1, [r4] + 616 0122 CA68 ldr r2, [r1, #12] + 617 0124 E06A ldr r0, [r4, #44] + 618 0126 0343 orrs r3, r0 + 619 0128 1343 orrs r3, r2 + 620 012a CB60 str r3, [r1, #12] + 621 .L45: + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 622 .loc 1 502 0 + 623 012c 636A ldr r3, [r4, #36] + 624 012e 012B cmp r3, #1 + 625 0130 0DD0 beq .L54 + 626 .L46: + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 627 .loc 1 523 0 + 628 0132 236C ldr r3, [r4, #64] + 629 0134 012B cmp r3, #1 + 630 0136 1DD0 beq .L55 + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 631 .loc 1 547 0 + 632 0138 2368 ldr r3, [r4] + 633 013a 1A69 ldr r2, [r3, #16] + 634 013c D207 lsls r2, r2, #31 + 635 013e 2CD5 bpl .L49 + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 636 .loc 1 550 0 + 637 0140 1A69 ldr r2, [r3, #16] + 638 0142 0121 movs r1, #1 + 639 0144 8A43 bics r2, r1 + 640 0146 1A61 str r2, [r3, #16] + 641 0148 27E0 b .L49 + 642 .L53: + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | + 643 .loc 1 483 0 + 644 014a 0422 movs r2, #4 + 645 014c D2E7 b .L44 + 646 .L54: + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + ARM GAS /tmp/ccHnSxqq.s page 52 + + + 647 .loc 1 504 0 + 648 014e 236A ldr r3, [r4, #32] + 649 0150 002B cmp r3, #0 + 650 0152 06D1 bne .L47 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 651 .loc 1 507 0 + 652 0154 2268 ldr r2, [r4] + 653 0156 D168 ldr r1, [r2, #12] + 654 0158 8023 movs r3, #128 + 655 015a 5B02 lsls r3, r3, #9 + 656 015c 0B43 orrs r3, r1 + 657 015e D360 str r3, [r2, #12] + 658 0160 E7E7 b .L46 + 659 .L47: + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 660 .loc 1 516 0 + 661 0162 A36D ldr r3, [r4, #88] + 662 0164 2022 movs r2, #32 + 663 0166 1343 orrs r3, r2 + 664 0168 A365 str r3, [r4, #88] + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 665 .loc 1 519 0 + 666 016a E36D ldr r3, [r4, #92] + 667 016c 1F3A subs r2, r2, #31 + 668 016e 1343 orrs r3, r2 + 669 0170 E365 str r3, [r4, #92] + 670 0172 DEE7 b .L46 + 671 .L55: + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR2_OVSS | + 672 .loc 1 534 0 + 673 0174 2268 ldr r2, [r4] + 674 0176 1369 ldr r3, [r2, #16] + 675 0178 1849 ldr r1, .L56+20 + 676 017a 0B40 ands r3, r1 + 677 017c 1361 str r3, [r2, #16] + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Oversample.RightBitShift | + 678 .loc 1 538 0 + 679 017e 2168 ldr r1, [r4] + 680 0180 0A69 ldr r2, [r1, #16] + 681 0182 636C ldr r3, [r4, #68] + 682 0184 A06C ldr r0, [r4, #72] + 683 0186 0343 orrs r3, r0 + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Oversample.TriggeredMode ); + 684 .loc 1 539 0 + 685 0188 E06C ldr r0, [r4, #76] + 686 018a 0343 orrs r3, r0 + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** hadc->Init.Oversample.RightBitShift | + 687 .loc 1 538 0 + 688 018c 1343 orrs r3, r2 + 689 018e 0B61 str r3, [r1, #16] + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 690 .loc 1 543 0 + 691 0190 2268 ldr r2, [r4] + 692 0192 1369 ldr r3, [r2, #16] + 693 0194 0121 movs r1, #1 + 694 0196 0B43 orrs r3, r1 + 695 0198 1361 str r3, [r2, #16] + ARM GAS /tmp/ccHnSxqq.s page 53 + + + 696 .L49: + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 697 .loc 1 555 0 + 698 019a 2268 ldr r2, [r4] + 699 019c 5369 ldr r3, [r2, #20] + 700 019e 0721 movs r1, #7 + 701 01a0 8B43 bics r3, r1 + 702 01a2 5361 str r3, [r2, #20] + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 703 .loc 1 558 0 + 704 01a4 2268 ldr r2, [r4] + 705 01a6 5369 ldr r3, [r2, #20] + 706 01a8 E16B ldr r1, [r4, #60] + 707 01aa 0B43 orrs r3, r1 + 708 01ac 5361 str r3, [r2, #20] + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 709 .loc 1 561 0 + 710 01ae 0023 movs r3, #0 + 711 01b0 E365 str r3, [r4, #92] + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 712 .loc 1 564 0 + 713 01b2 A36D ldr r3, [r4, #88] + 714 01b4 0322 movs r2, #3 + 715 01b6 9343 bics r3, r2 + 716 01b8 023A subs r2, r2, #2 + 717 01ba 1343 orrs r3, r2 + 718 01bc A365 str r3, [r4, #88] + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 719 .loc 1 570 0 + 720 01be 0020 movs r0, #0 + 721 01c0 62E7 b .L34 + 722 .LVL42: + 723 .L50: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 724 .loc 1 361 0 + 725 01c2 0120 movs r0, #1 + 726 .LVL43: + 727 01c4 60E7 b .L34 + 728 .L57: + 729 01c6 C046 .align 2 + 730 .L56: + 731 01c8 FDFEFFFF .word -259 + 732 01cc 08270140 .word 1073817352 + 733 01d0 FFFFC3FF .word -3932161 + 734 01d4 FFFFFFFD .word -33554433 + 735 01d8 1902FEFF .word -130535 + 736 01dc 03FCFFFF .word -1021 + 737 .cfi_endproc + 738 .LFE39: + 740 .section .text.HAL_ADC_MspDeInit,"ax",%progbits + 741 .align 1 + 742 .weak HAL_ADC_MspDeInit + 743 .syntax unified + 744 .code 16 + 745 .thumb_func + 746 .fpu softvfp + 748 HAL_ADC_MspDeInit: + ARM GAS /tmp/ccHnSxqq.s page 54 + + + 749 .LFB42: + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 750 .loc 1 722 0 + 751 .cfi_startproc + 752 @ args = 0, pretend = 0, frame = 0 + 753 @ frame_needed = 0, uses_anonymous_args = 0 + 754 @ link register save eliminated. + 755 .LVL44: + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 756 .loc 1 729 0 + 757 @ sp needed + 758 0000 7047 bx lr + 759 .cfi_endproc + 760 .LFE42: + 762 .section .text.HAL_ADC_DeInit,"ax",%progbits + 763 .align 1 + 764 .global HAL_ADC_DeInit + 765 .syntax unified + 766 .code 16 + 767 .thumb_func + 768 .fpu softvfp + 770 HAL_ADC_DeInit: + 771 .LFB40: + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 772 .loc 1 586 0 + 773 .cfi_startproc + 774 @ args = 0, pretend = 0, frame = 0 + 775 @ frame_needed = 0, uses_anonymous_args = 0 + 776 .LVL45: + 777 0000 70B5 push {r4, r5, r6, lr} + 778 .LCFI5: + 779 .cfi_def_cfa_offset 16 + 780 .cfi_offset 4, -16 + 781 .cfi_offset 5, -12 + 782 .cfi_offset 6, -8 + 783 .cfi_offset 14, -4 + 784 0002 041E subs r4, r0, #0 + 785 .LVL46: + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 786 .loc 1 590 0 + 787 0004 49D0 beq .L63 + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 788 .loc 1 599 0 + 789 0006 836D ldr r3, [r0, #88] + 790 0008 0222 movs r2, #2 + 791 000a 1343 orrs r3, r2 + 792 000c 8365 str r3, [r0, #88] + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 793 .loc 1 602 0 + 794 000e FFF7FEFF bl ADC_ConversionStop + 795 .LVL47: + 796 0012 051E subs r5, r0, #0 + 797 .LVL48: + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 798 .loc 1 605 0 + 799 0014 06D0 beq .L64 + 800 .LVL49: + ARM GAS /tmp/ccHnSxqq.s page 55 + + + 801 .L61: + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 802 .loc 1 621 0 + 803 0016 012D cmp r5, #1 + 804 0018 0DD1 bne .L65 + 805 .L62: + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 806 .loc 1 695 0 + 807 001a 5423 movs r3, #84 + 808 001c 0022 movs r2, #0 + 809 001e E254 strb r2, [r4, r3] + 810 .LVL50: + 811 .L60: + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 812 .loc 1 699 0 + 813 0020 2800 movs r0, r5 + 814 @ sp needed + 815 .LVL51: + 816 0022 70BD pop {r4, r5, r6, pc} + 817 .LVL52: + 818 .L64: + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 819 .loc 1 608 0 + 820 0024 2000 movs r0, r4 + 821 .LVL53: + 822 0026 FFF7FEFF bl ADC_Disable + 823 .LVL54: + 824 002a 0500 movs r5, r0 + 825 .LVL55: + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 826 .loc 1 611 0 + 827 002c 0128 cmp r0, #1 + 828 002e F2D0 beq .L61 + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 829 .loc 1 614 0 + 830 0030 0123 movs r3, #1 + 831 0032 A365 str r3, [r4, #88] + 832 0034 EFE7 b .L61 + 833 .LVL56: + 834 .L65: + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP )); + 835 .loc 1 626 0 + 836 0036 2268 ldr r2, [r4] + 837 0038 5368 ldr r3, [r2, #4] + 838 003a 1949 ldr r1, .L66 + 839 003c 0B40 ands r3, r1 + 840 003e 5360 str r3, [r2, #4] + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + 841 .loc 1 631 0 + 842 0040 2368 ldr r3, [r4] + 843 0042 184A ldr r2, .L66+4 + 844 0044 1A60 str r2, [r3] + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 845 .loc 1 639 0 + 846 0046 2268 ldr r2, [r4] + 847 0048 9368 ldr r3, [r2, #8] + 848 004a 1749 ldr r1, .L66+8 + ARM GAS /tmp/ccHnSxqq.s page 56 + + + 849 004c 0B40 ands r3, r1 + 850 004e 9360 str r3, [r2, #8] + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \ + 851 .loc 1 645 0 + 852 0050 2268 ldr r2, [r4] + 853 0052 D368 ldr r3, [r2, #12] + 854 0054 1549 ldr r1, .L66+12 + 855 0056 0B40 ands r3, r1 + 856 0058 D360 str r3, [r2, #12] + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE ); + 857 .loc 1 652 0 + 858 005a 2268 ldr r2, [r4] + 859 005c 1369 ldr r3, [r2, #16] + 860 005e 1449 ldr r1, .L66+16 + 861 0060 0B40 ands r3, r1 + 862 0062 1361 str r3, [r2, #16] + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 863 .loc 1 657 0 + 864 0064 2268 ldr r2, [r4] + 865 0066 5369 ldr r3, [r2, #20] + 866 0068 0721 movs r1, #7 + 867 006a 8B43 bics r3, r1 + 868 006c 5361 str r3, [r2, #20] + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 869 .loc 1 660 0 + 870 006e 2268 ldr r2, [r4] + 871 0070 136A ldr r3, [r2, #32] + 872 0072 1049 ldr r1, .L66+20 + 873 0074 0B40 ands r3, r1 + 874 0076 1362 str r3, [r2, #32] + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 875 .loc 1 663 0 + 876 0078 2168 ldr r1, [r4] + 877 007a B423 movs r3, #180 + 878 007c CA58 ldr r2, [r1, r3] + 879 007e 7F20 movs r0, #127 + 880 0080 8243 bics r2, r0 + 881 0082 CA50 str r2, [r1, r3] + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 882 .loc 1 673 0 + 883 0084 2168 ldr r1, [r4] + 884 0086 CA58 ldr r2, [r1, r3] + 885 0088 8243 bics r2, r0 + 886 008a CA50 str r2, [r1, r3] + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 887 .loc 1 685 0 + 888 008c 2000 movs r0, r4 + 889 008e FFF7FEFF bl HAL_ADC_MspDeInit + 890 .LVL57: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 891 .loc 1 688 0 + 892 0092 0023 movs r3, #0 + 893 0094 E365 str r3, [r4, #92] + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 894 .loc 1 691 0 + 895 0096 A365 str r3, [r4, #88] + 896 0098 BFE7 b .L62 + ARM GAS /tmp/ccHnSxqq.s page 57 + + + 897 .LVL58: + 898 .L63: + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 899 .loc 1 592 0 + 900 009a 0125 movs r5, #1 + 901 009c C0E7 b .L60 + 902 .L67: + 903 009e C046 .align 2 + 904 .L66: + 905 00a0 60F7FFFF .word -2208 + 906 00a4 9F080000 .word 2207 + 907 00a8 FFFFFFEF .word -268435457 + 908 00ac 00023E83 .word -2093088256 + 909 00b0 02FCFF3F .word 1073740802 + 910 00b4 00F000F0 .word -268374016 + 911 .cfi_endproc + 912 .LFE40: + 914 .section .text.HAL_ADC_Start,"ax",%progbits + 915 .align 1 + 916 .global HAL_ADC_Start + 917 .syntax unified + 918 .code 16 + 919 .thumb_func + 920 .fpu softvfp + 922 HAL_ADC_Start: + 923 .LFB43: + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 924 .loc 1 764 0 + 925 .cfi_startproc + 926 @ args = 0, pretend = 0, frame = 0 + 927 @ frame_needed = 0, uses_anonymous_args = 0 + 928 .LVL59: + 929 0000 10B5 push {r4, lr} + 930 .LCFI6: + 931 .cfi_def_cfa_offset 8 + 932 .cfi_offset 4, -8 + 933 .cfi_offset 14, -4 + 934 0002 0400 movs r4, r0 + 935 .LVL60: + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 936 .loc 1 771 0 + 937 0004 0368 ldr r3, [r0] + 938 0006 9B68 ldr r3, [r3, #8] + 939 0008 5B07 lsls r3, r3, #29 + 940 000a 23D4 bmi .L71 + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 941 .loc 1 774 0 + 942 000c 5423 movs r3, #84 + 943 000e C35C ldrb r3, [r0, r3] + 944 0010 012B cmp r3, #1 + 945 0012 21D0 beq .L72 + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 946 .loc 1 774 0 is_stmt 0 discriminator 2 + 947 0014 5423 movs r3, #84 + 948 0016 0122 movs r2, #1 + 949 0018 C254 strb r2, [r0, r3] + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + ARM GAS /tmp/ccHnSxqq.s page 58 + + + 950 .loc 1 779 0 is_stmt 1 discriminator 2 + 951 001a C369 ldr r3, [r0, #28] + 952 001c 012B cmp r3, #1 + 953 001e 14D1 bne .L74 + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 954 .loc 1 765 0 + 955 0020 0020 movs r0, #0 + 956 .LVL61: + 957 .L70: + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A + 958 .loc 1 790 0 + 959 0022 A36D ldr r3, [r4, #88] + 960 0024 0D4A ldr r2, .L75 + 961 0026 1A40 ands r2, r3 + 962 0028 8023 movs r3, #128 + 963 002a 5B00 lsls r3, r3, #1 + 964 002c 1343 orrs r3, r2 + 965 002e A365 str r3, [r4, #88] + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 966 .loc 1 795 0 + 967 0030 0023 movs r3, #0 + 968 0032 E365 str r3, [r4, #92] + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 969 .loc 1 800 0 + 970 0034 5422 movs r2, #84 + 971 0036 A354 strb r3, [r4, r2] + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 972 .loc 1 805 0 + 973 0038 2368 ldr r3, [r4] + 974 003a 383A subs r2, r2, #56 + 975 003c 1A60 str r2, [r3] + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 976 .loc 1 811 0 + 977 003e 2268 ldr r2, [r4] + 978 0040 9368 ldr r3, [r2, #8] + 979 0042 0421 movs r1, #4 + 980 0044 0B43 orrs r3, r1 + 981 0046 9360 str r3, [r2, #8] + 982 .L69: + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 983 .loc 1 821 0 + 984 @ sp needed + 985 .LVL62: + 986 0048 10BD pop {r4, pc} + 987 .LVL63: + 988 .L74: + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 989 .loc 1 781 0 + 990 004a FFF7FEFF bl ADC_Enable + 991 .LVL64: + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 992 .loc 1 785 0 + 993 004e 0028 cmp r0, #0 + 994 0050 E7D0 beq .L70 + 995 0052 F9E7 b .L69 + 996 .LVL65: + 997 .L71: + ARM GAS /tmp/ccHnSxqq.s page 59 + + + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 998 .loc 1 816 0 + 999 0054 0220 movs r0, #2 + 1000 .LVL66: + 1001 0056 F7E7 b .L69 + 1002 .LVL67: + 1003 .L72: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1004 .loc 1 774 0 + 1005 0058 0220 movs r0, #2 + 1006 .LVL68: + 1007 005a F5E7 b .L69 + 1008 .L76: + 1009 .align 2 + 1010 .L75: + 1011 005c FEF0FFFF .word -3842 + 1012 .cfi_endproc + 1013 .LFE43: + 1015 .section .text.HAL_ADC_Stop,"ax",%progbits + 1016 .align 1 + 1017 .global HAL_ADC_Stop + 1018 .syntax unified + 1019 .code 16 + 1020 .thumb_func + 1021 .fpu softvfp + 1023 HAL_ADC_Stop: + 1024 .LFB44: + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1025 .loc 1 830 0 + 1026 .cfi_startproc + 1027 @ args = 0, pretend = 0, frame = 0 + 1028 @ frame_needed = 0, uses_anonymous_args = 0 + 1029 .LVL69: + 1030 0000 10B5 push {r4, lr} + 1031 .LCFI7: + 1032 .cfi_def_cfa_offset 8 + 1033 .cfi_offset 4, -8 + 1034 .cfi_offset 14, -4 + 1035 0002 0400 movs r4, r0 + 1036 .LVL70: + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1037 .loc 1 837 0 + 1038 0004 5423 movs r3, #84 + 1039 0006 C35C ldrb r3, [r0, r3] + 1040 0008 012B cmp r3, #1 + 1041 000a 17D0 beq .L80 + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1042 .loc 1 837 0 is_stmt 0 discriminator 2 + 1043 000c 5423 movs r3, #84 + 1044 000e 0122 movs r2, #1 + 1045 0010 C254 strb r2, [r0, r3] + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1046 .loc 1 840 0 is_stmt 1 discriminator 2 + 1047 0012 FFF7FEFF bl ADC_ConversionStop + 1048 .LVL71: + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1049 .loc 1 843 0 discriminator 2 + ARM GAS /tmp/ccHnSxqq.s page 60 + + + 1050 0016 0028 cmp r0, #0 + 1051 0018 03D0 beq .L81 + 1052 .LVL72: + 1053 .L79: + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1054 .loc 1 859 0 + 1055 001a 5423 movs r3, #84 + 1056 001c 0022 movs r2, #0 + 1057 001e E254 strb r2, [r4, r3] + 1058 .LVL73: + 1059 .L78: + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1060 .loc 1 863 0 + 1061 @ sp needed + 1062 .LVL74: + 1063 0020 10BD pop {r4, pc} + 1064 .LVL75: + 1065 .L81: + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1066 .loc 1 846 0 + 1067 0022 2000 movs r0, r4 + 1068 .LVL76: + 1069 0024 FFF7FEFF bl ADC_Disable + 1070 .LVL77: + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1071 .loc 1 849 0 + 1072 0028 0028 cmp r0, #0 + 1073 002a F6D1 bne .L79 + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 1074 .loc 1 852 0 + 1075 002c A36D ldr r3, [r4, #88] + 1076 002e 044A ldr r2, .L82 + 1077 0030 1340 ands r3, r2 + 1078 0032 0432 adds r2, r2, #4 + 1079 0034 FF32 adds r2, r2, #255 + 1080 0036 1343 orrs r3, r2 + 1081 0038 A365 str r3, [r4, #88] + 1082 003a EEE7 b .L79 + 1083 .LVL78: + 1084 .L80: + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1085 .loc 1 837 0 + 1086 003c 0220 movs r0, #2 + 1087 .LVL79: + 1088 003e EFE7 b .L78 + 1089 .L83: + 1090 .align 2 + 1091 .L82: + 1092 0040 FEFEFFFF .word -258 + 1093 .cfi_endproc + 1094 .LFE44: + 1096 .section .text.HAL_ADC_PollForConversion,"ax",%progbits + 1097 .align 1 + 1098 .global HAL_ADC_PollForConversion + 1099 .syntax unified + 1100 .code 16 + 1101 .thumb_func + ARM GAS /tmp/ccHnSxqq.s page 61 + + + 1102 .fpu softvfp + 1104 HAL_ADC_PollForConversion: + 1105 .LFB45: + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0; + 1106 .loc 1 884 0 + 1107 .cfi_startproc + 1108 @ args = 0, pretend = 0, frame = 0 + 1109 @ frame_needed = 0, uses_anonymous_args = 0 + 1110 .LVL80: + 1111 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1112 .LCFI8: + 1113 .cfi_def_cfa_offset 24 + 1114 .cfi_offset 3, -24 + 1115 .cfi_offset 4, -20 + 1116 .cfi_offset 5, -16 + 1117 .cfi_offset 6, -12 + 1118 .cfi_offset 7, -8 + 1119 .cfi_offset 14, -4 + 1120 0002 0400 movs r4, r0 + 1121 0004 0E00 movs r6, r1 + 1122 .LVL81: + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1123 .loc 1 892 0 + 1124 0006 4569 ldr r5, [r0, #20] + 1125 0008 082D cmp r5, #8 + 1126 000a 04D0 beq .L85 + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1127 .loc 1 905 0 + 1128 000c 0368 ldr r3, [r0] + 1129 000e DB68 ldr r3, [r3, #12] + 1130 0010 DB07 lsls r3, r3, #31 + 1131 0012 19D4 bmi .L95 + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1132 .loc 1 917 0 + 1133 0014 0C25 movs r5, #12 + 1134 .L85: + 1135 .LVL82: + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1136 .loc 1 922 0 + 1137 0016 FFF7FEFF bl HAL_GetTick + 1138 .LVL83: + 1139 001a 0700 movs r7, r0 + 1140 .LVL84: + 1141 .L88: + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1142 .loc 1 925 0 + 1143 001c 2368 ldr r3, [r4] + 1144 001e 1A68 ldr r2, [r3] + 1145 0020 1542 tst r5, r2 + 1146 0022 1AD1 bne .L96 + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1147 .loc 1 928 0 + 1148 0024 731C adds r3, r6, #1 + 1149 0026 F9D0 beq .L88 + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1150 .loc 1 930 0 + 1151 0028 002E cmp r6, #0 + ARM GAS /tmp/ccHnSxqq.s page 62 + + + 1152 002a 04D0 beq .L89 + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1153 .loc 1 930 0 is_stmt 0 discriminator 1 + 1154 002c FFF7FEFF bl HAL_GetTick + 1155 .LVL85: + 1156 0030 C01B subs r0, r0, r7 + 1157 0032 B042 cmp r0, r6 + 1158 0034 F2D9 bls .L88 + 1159 .L89: + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1160 .loc 1 933 0 is_stmt 1 + 1161 0036 A36D ldr r3, [r4, #88] + 1162 0038 0422 movs r2, #4 + 1163 003a 1343 orrs r3, r2 + 1164 003c A365 str r3, [r4, #88] + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1165 .loc 1 936 0 + 1166 003e 5423 movs r3, #84 + 1167 0040 0022 movs r2, #0 + 1168 0042 E254 strb r2, [r4, r3] + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1169 .loc 1 938 0 + 1170 0044 0320 movs r0, #3 + 1171 0046 07E0 b .L86 + 1172 .LVL86: + 1173 .L95: + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1174 .loc 1 908 0 + 1175 0048 836D ldr r3, [r0, #88] + 1176 004a 2022 movs r2, #32 + 1177 004c 1343 orrs r3, r2 + 1178 004e 8365 str r3, [r0, #88] + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1179 .loc 1 911 0 + 1180 0050 5423 movs r3, #84 + 1181 0052 0022 movs r2, #0 + 1182 0054 C254 strb r2, [r0, r3] + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1183 .loc 1 913 0 + 1184 0056 0120 movs r0, #1 + 1185 .LVL87: + 1186 .L86: + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1187 .loc 1 991 0 + 1188 @ sp needed + 1189 .LVL88: + 1190 .LVL89: + 1191 0058 F8BD pop {r3, r4, r5, r6, r7, pc} + 1192 .LVL90: + 1193 .L96: + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1194 .loc 1 944 0 + 1195 005a A16D ldr r1, [r4, #88] + 1196 005c 8022 movs r2, #128 + 1197 005e 9200 lsls r2, r2, #2 + 1198 0060 0A43 orrs r2, r1 + 1199 0062 A265 str r2, [r4, #88] + ARM GAS /tmp/ccHnSxqq.s page 63 + + + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 1200 .loc 1 948 0 + 1201 0064 D968 ldr r1, [r3, #12] + 1202 0066 C022 movs r2, #192 + 1203 0068 1201 lsls r2, r2, #4 + 1204 006a 1142 tst r1, r2 + 1205 006c 13D1 bne .L91 + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 1206 .loc 1 948 0 is_stmt 0 discriminator 1 + 1207 006e 226A ldr r2, [r4, #32] + 1208 0070 002A cmp r2, #0 + 1209 0072 10D1 bne .L91 + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1210 .loc 1 952 0 is_stmt 1 + 1211 0074 1A68 ldr r2, [r3] + 1212 0076 1207 lsls r2, r2, #28 + 1213 0078 0DD5 bpl .L91 + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1214 .loc 1 956 0 + 1215 007a 9A68 ldr r2, [r3, #8] + 1216 007c 5207 lsls r2, r2, #29 + 1217 007e 12D4 bmi .L92 + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1218 .loc 1 962 0 + 1219 0080 5A68 ldr r2, [r3, #4] + 1220 0082 0C21 movs r1, #12 + 1221 0084 8A43 bics r2, r1 + 1222 0086 5A60 str r2, [r3, #4] + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 1223 .loc 1 965 0 + 1224 0088 A36D ldr r3, [r4, #88] + 1225 008a 0C4A ldr r2, .L97 + 1226 008c 1340 ands r3, r2 + 1227 008e 0432 adds r2, r2, #4 + 1228 0090 FF32 adds r2, r2, #255 + 1229 0092 1343 orrs r3, r2 + 1230 0094 A365 str r3, [r4, #88] + 1231 .L91: + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1232 .loc 1 983 0 + 1233 0096 A369 ldr r3, [r4, #24] + 1234 0098 002B cmp r3, #0 + 1235 009a 0DD1 bne .L94 + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1236 .loc 1 986 0 + 1237 009c 2368 ldr r3, [r4] + 1238 009e 0C22 movs r2, #12 + 1239 00a0 1A60 str r2, [r3] + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1240 .loc 1 990 0 + 1241 00a2 0020 movs r0, #0 + 1242 00a4 D8E7 b .L86 + 1243 .L92: + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1244 .loc 1 972 0 + 1245 00a6 A36D ldr r3, [r4, #88] + 1246 00a8 2022 movs r2, #32 + ARM GAS /tmp/ccHnSxqq.s page 64 + + + 1247 00aa 1343 orrs r3, r2 + 1248 00ac A365 str r3, [r4, #88] + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1249 .loc 1 975 0 + 1250 00ae E36D ldr r3, [r4, #92] + 1251 00b0 1F3A subs r2, r2, #31 + 1252 00b2 1343 orrs r3, r2 + 1253 00b4 E365 str r3, [r4, #92] + 1254 00b6 EEE7 b .L91 + 1255 .L94: + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1256 .loc 1 990 0 + 1257 00b8 0020 movs r0, #0 + 1258 00ba CDE7 b .L86 + 1259 .L98: + 1260 .align 2 + 1261 .L97: + 1262 00bc FEFEFFFF .word -258 + 1263 .cfi_endproc + 1264 .LFE45: + 1266 .section .text.HAL_ADC_PollForEvent,"ax",%progbits + 1267 .align 1 + 1268 .global HAL_ADC_PollForEvent + 1269 .syntax unified + 1270 .code 16 + 1271 .thumb_func + 1272 .fpu softvfp + 1274 HAL_ADC_PollForEvent: + 1275 .LFB46: +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** uint32_t tickstart = 0U; + 1276 .loc 1 1010 0 + 1277 .cfi_startproc + 1278 @ args = 0, pretend = 0, frame = 0 + 1279 @ frame_needed = 0, uses_anonymous_args = 0 + 1280 .LVL91: + 1281 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1282 .LCFI9: + 1283 .cfi_def_cfa_offset 24 + 1284 .cfi_offset 3, -24 + 1285 .cfi_offset 4, -20 + 1286 .cfi_offset 5, -16 + 1287 .cfi_offset 6, -12 + 1288 .cfi_offset 7, -8 + 1289 .cfi_offset 14, -4 + 1290 0002 0500 movs r5, r0 + 1291 0004 0C00 movs r4, r1 + 1292 0006 1600 movs r6, r2 + 1293 .LVL92: +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1294 .loc 1 1018 0 + 1295 0008 FFF7FEFF bl HAL_GetTick + 1296 .LVL93: + 1297 000c 0700 movs r7, r0 + 1298 .LVL94: + 1299 .L101: +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1300 .loc 1 1021 0 + ARM GAS /tmp/ccHnSxqq.s page 65 + + + 1301 000e 2A68 ldr r2, [r5] + 1302 0010 1368 ldr r3, [r2] + 1303 0012 2340 ands r3, r4 + 1304 0014 A342 cmp r3, r4 + 1305 0016 11D0 beq .L109 +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1306 .loc 1 1024 0 + 1307 0018 731C adds r3, r6, #1 + 1308 001a F8D0 beq .L101 +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1309 .loc 1 1026 0 + 1310 001c 002E cmp r6, #0 + 1311 001e 04D0 beq .L102 +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1312 .loc 1 1026 0 is_stmt 0 discriminator 1 + 1313 0020 FFF7FEFF bl HAL_GetTick + 1314 .LVL95: + 1315 0024 C01B subs r0, r0, r7 + 1316 0026 B042 cmp r0, r6 + 1317 0028 F1D9 bls .L101 + 1318 .L102: +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1319 .loc 1 1029 0 is_stmt 1 + 1320 002a AB6D ldr r3, [r5, #88] + 1321 002c 0422 movs r2, #4 + 1322 002e 1343 orrs r3, r2 + 1323 0030 AB65 str r3, [r5, #88] +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1324 .loc 1 1032 0 + 1325 0032 5423 movs r3, #84 + 1326 0034 0022 movs r2, #0 + 1327 0036 EA54 strb r2, [r5, r3] +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1328 .loc 1 1034 0 + 1329 0038 0320 movs r0, #3 + 1330 003a 10E0 b .L103 + 1331 .L109: +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1332 .loc 1 1039 0 + 1333 003c 802C cmp r4, #128 + 1334 003e 0FD0 beq .L110 +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1335 .loc 1 1056 0 + 1336 0040 6B6B ldr r3, [r5, #52] + 1337 0042 002B cmp r3, #0 + 1338 0044 08D1 bne .L107 +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1339 .loc 1 1059 0 + 1340 0046 A96D ldr r1, [r5, #88] + 1341 0048 8023 movs r3, #128 + 1342 004a DB00 lsls r3, r3, #3 + 1343 004c 0B43 orrs r3, r1 + 1344 004e AB65 str r3, [r5, #88] +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1345 .loc 1 1062 0 + 1346 0050 EB6D ldr r3, [r5, #92] + 1347 0052 0221 movs r1, #2 + ARM GAS /tmp/ccHnSxqq.s page 66 + + + 1348 0054 0B43 orrs r3, r1 + 1349 0056 EB65 str r3, [r5, #92] + 1350 .L107: +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; + 1351 .loc 1 1066 0 + 1352 0058 1023 movs r3, #16 + 1353 005a 1360 str r3, [r2] +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1354 .loc 1 1071 0 + 1355 005c 0020 movs r0, #0 + 1356 .L103: +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1357 .loc 1 1072 0 + 1358 @ sp needed + 1359 .LVL96: + 1360 .LVL97: + 1361 .LVL98: + 1362 .LVL99: + 1363 005e F8BD pop {r3, r4, r5, r6, r7, pc} + 1364 .LVL100: + 1365 .L110: +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1366 .loc 1 1044 0 + 1367 0060 A96D ldr r1, [r5, #88] + 1368 0062 8023 movs r3, #128 + 1369 0064 5B02 lsls r3, r3, #9 + 1370 0066 0B43 orrs r3, r1 + 1371 0068 AB65 str r3, [r5, #88] +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; + 1372 .loc 1 1047 0 + 1373 006a 8023 movs r3, #128 + 1374 006c 1360 str r3, [r2] +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1375 .loc 1 1071 0 + 1376 006e 0020 movs r0, #0 +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1377 .loc 1 1048 0 + 1378 0070 F5E7 b .L103 + 1379 .cfi_endproc + 1380 .LFE46: + 1382 .section .text.HAL_ADC_Start_IT,"ax",%progbits + 1383 .align 1 + 1384 .global HAL_ADC_Start_IT + 1385 .syntax unified + 1386 .code 16 + 1387 .thumb_func + 1388 .fpu softvfp + 1390 HAL_ADC_Start_IT: + 1391 .LFB47: +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1392 .loc 1 1093 0 + 1393 .cfi_startproc + 1394 @ args = 0, pretend = 0, frame = 0 + 1395 @ frame_needed = 0, uses_anonymous_args = 0 + 1396 .LVL101: + 1397 0000 10B5 push {r4, lr} + 1398 .LCFI10: + ARM GAS /tmp/ccHnSxqq.s page 67 + + + 1399 .cfi_def_cfa_offset 8 + 1400 .cfi_offset 4, -8 + 1401 .cfi_offset 14, -4 + 1402 0002 0400 movs r4, r0 + 1403 .LVL102: +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1404 .loc 1 1100 0 + 1405 0004 0368 ldr r3, [r0] + 1406 0006 9B68 ldr r3, [r3, #8] + 1407 0008 5B07 lsls r3, r3, #29 + 1408 000a 36D4 bmi .L117 +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1409 .loc 1 1103 0 + 1410 000c 5423 movs r3, #84 + 1411 000e C35C ldrb r3, [r0, r3] + 1412 0010 012B cmp r3, #1 + 1413 0012 34D0 beq .L118 +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1414 .loc 1 1103 0 is_stmt 0 discriminator 2 + 1415 0014 5423 movs r3, #84 + 1416 0016 0122 movs r2, #1 + 1417 0018 C254 strb r2, [r0, r3] +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1418 .loc 1 1108 0 is_stmt 1 discriminator 2 + 1419 001a C369 ldr r3, [r0, #28] + 1420 001c 012B cmp r3, #1 + 1421 001e 21D1 bne .L121 +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1422 .loc 1 1094 0 + 1423 0020 0020 movs r0, #0 + 1424 .LVL103: + 1425 .L113: +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A + 1426 .loc 1 1119 0 + 1427 0022 A36D ldr r3, [r4, #88] + 1428 0024 174A ldr r2, .L122 + 1429 0026 1A40 ands r2, r3 + 1430 0028 8023 movs r3, #128 + 1431 002a 5B00 lsls r3, r3, #1 + 1432 002c 1343 orrs r3, r2 + 1433 002e A365 str r3, [r4, #88] +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1434 .loc 1 1124 0 + 1435 0030 0023 movs r3, #0 + 1436 0032 E365 str r3, [r4, #92] +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1437 .loc 1 1129 0 + 1438 0034 5422 movs r2, #84 + 1439 0036 A354 strb r3, [r4, r2] +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1440 .loc 1 1134 0 + 1441 0038 2368 ldr r3, [r4] + 1442 003a 383A subs r2, r2, #56 + 1443 003c 1A60 str r2, [r3] +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1444 .loc 1 1138 0 + 1445 003e 6369 ldr r3, [r4, #20] + ARM GAS /tmp/ccHnSxqq.s page 68 + + + 1446 0040 082B cmp r3, #8 + 1447 0042 14D1 bne .L120 +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); + 1448 .loc 1 1141 0 + 1449 0044 2268 ldr r2, [r4] + 1450 0046 5368 ldr r3, [r2, #4] + 1451 0048 0421 movs r1, #4 + 1452 004a 8B43 bics r3, r1 + 1453 004c 5360 str r3, [r2, #4] +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; + 1454 .loc 1 1142 0 + 1455 004e 2268 ldr r2, [r4] + 1456 0050 5368 ldr r3, [r2, #4] + 1457 0052 1431 adds r1, r1, #20 + 1458 0054 0B43 orrs r3, r1 + 1459 0056 5360 str r3, [r2, #4] + 1460 .L116: +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1461 .loc 1 1154 0 + 1462 0058 2268 ldr r2, [r4] + 1463 005a 9368 ldr r3, [r2, #8] + 1464 005c 0421 movs r1, #4 + 1465 005e 0B43 orrs r3, r1 + 1466 0060 9360 str r3, [r2, #8] + 1467 .L112: +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1468 .loc 1 1164 0 + 1469 @ sp needed + 1470 .LVL104: + 1471 0062 10BD pop {r4, pc} + 1472 .LVL105: + 1473 .L121: +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1474 .loc 1 1110 0 + 1475 0064 FFF7FEFF bl ADC_Enable + 1476 .LVL106: +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1477 .loc 1 1114 0 + 1478 0068 0028 cmp r0, #0 + 1479 006a DAD0 beq .L113 + 1480 006c F9E7 b .L112 + 1481 .LVL107: + 1482 .L120: +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** break; + 1483 .loc 1 1146 0 + 1484 006e 2268 ldr r2, [r4] + 1485 0070 5368 ldr r3, [r2, #4] + 1486 0072 1C21 movs r1, #28 + 1487 0074 0B43 orrs r3, r1 + 1488 0076 5360 str r3, [r2, #4] +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1489 .loc 1 1147 0 + 1490 0078 EEE7 b .L116 + 1491 .LVL108: + 1492 .L117: +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1493 .loc 1 1159 0 + ARM GAS /tmp/ccHnSxqq.s page 69 + + + 1494 007a 0220 movs r0, #2 + 1495 .LVL109: + 1496 007c F1E7 b .L112 + 1497 .LVL110: + 1498 .L118: +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1499 .loc 1 1103 0 + 1500 007e 0220 movs r0, #2 + 1501 .LVL111: + 1502 0080 EFE7 b .L112 + 1503 .L123: + 1504 0082 C046 .align 2 + 1505 .L122: + 1506 0084 FEF0FFFF .word -3842 + 1507 .cfi_endproc + 1508 .LFE47: + 1510 .section .text.HAL_ADC_Stop_IT,"ax",%progbits + 1511 .align 1 + 1512 .global HAL_ADC_Stop_IT + 1513 .syntax unified + 1514 .code 16 + 1515 .thumb_func + 1516 .fpu softvfp + 1518 HAL_ADC_Stop_IT: + 1519 .LFB48: +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1520 .loc 1 1174 0 + 1521 .cfi_startproc + 1522 @ args = 0, pretend = 0, frame = 0 + 1523 @ frame_needed = 0, uses_anonymous_args = 0 + 1524 .LVL112: + 1525 0000 10B5 push {r4, lr} + 1526 .LCFI11: + 1527 .cfi_def_cfa_offset 8 + 1528 .cfi_offset 4, -8 + 1529 .cfi_offset 14, -4 + 1530 0002 0400 movs r4, r0 + 1531 .LVL113: +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1532 .loc 1 1181 0 + 1533 0004 5423 movs r3, #84 + 1534 0006 C35C ldrb r3, [r0, r3] + 1535 0008 012B cmp r3, #1 + 1536 000a 1CD0 beq .L127 +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1537 .loc 1 1181 0 is_stmt 0 discriminator 2 + 1538 000c 5423 movs r3, #84 + 1539 000e 0122 movs r2, #1 + 1540 0010 C254 strb r2, [r0, r3] +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1541 .loc 1 1184 0 is_stmt 1 discriminator 2 + 1542 0012 FFF7FEFF bl ADC_ConversionStop + 1543 .LVL114: +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1544 .loc 1 1187 0 discriminator 2 + 1545 0016 0028 cmp r0, #0 + 1546 0018 03D0 beq .L128 + ARM GAS /tmp/ccHnSxqq.s page 70 + + + 1547 .LVL115: + 1548 .L126: +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1549 .loc 1 1207 0 + 1550 001a 5423 movs r3, #84 + 1551 001c 0022 movs r2, #0 + 1552 001e E254 strb r2, [r4, r3] + 1553 .LVL116: + 1554 .L125: +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1555 .loc 1 1211 0 + 1556 @ sp needed + 1557 .LVL117: + 1558 0020 10BD pop {r4, pc} + 1559 .LVL118: + 1560 .L128: +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1561 .loc 1 1191 0 + 1562 0022 2268 ldr r2, [r4] + 1563 0024 5368 ldr r3, [r2, #4] + 1564 0026 1C21 movs r1, #28 + 1565 0028 8B43 bics r3, r1 + 1566 002a 5360 str r3, [r2, #4] +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1567 .loc 1 1194 0 + 1568 002c 2000 movs r0, r4 + 1569 .LVL119: + 1570 002e FFF7FEFF bl ADC_Disable + 1571 .LVL120: +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1572 .loc 1 1197 0 + 1573 0032 0028 cmp r0, #0 + 1574 0034 F1D1 bne .L126 +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 1575 .loc 1 1200 0 + 1576 0036 A36D ldr r3, [r4, #88] + 1577 0038 044A ldr r2, .L129 + 1578 003a 1340 ands r3, r2 + 1579 003c 0432 adds r2, r2, #4 + 1580 003e FF32 adds r2, r2, #255 + 1581 0040 1343 orrs r3, r2 + 1582 0042 A365 str r3, [r4, #88] + 1583 0044 E9E7 b .L126 + 1584 .LVL121: + 1585 .L127: +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1586 .loc 1 1181 0 + 1587 0046 0220 movs r0, #2 + 1588 .LVL122: + 1589 0048 EAE7 b .L125 + 1590 .L130: + 1591 004a C046 .align 2 + 1592 .L129: + 1593 004c FEFEFFFF .word -258 + 1594 .cfi_endproc + 1595 .LFE48: + 1597 .section .text.HAL_ADC_Start_DMA,"ax",%progbits + ARM GAS /tmp/ccHnSxqq.s page 71 + + + 1598 .align 1 + 1599 .global HAL_ADC_Start_DMA + 1600 .syntax unified + 1601 .code 16 + 1602 .thumb_func + 1603 .fpu softvfp + 1605 HAL_ADC_Start_DMA: + 1606 .LFB49: +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1607 .loc 1 1224 0 + 1608 .cfi_startproc + 1609 @ args = 0, pretend = 0, frame = 0 + 1610 @ frame_needed = 0, uses_anonymous_args = 0 + 1611 .LVL123: + 1612 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1613 .LCFI12: + 1614 .cfi_def_cfa_offset 24 + 1615 .cfi_offset 3, -24 + 1616 .cfi_offset 4, -20 + 1617 .cfi_offset 5, -16 + 1618 .cfi_offset 6, -12 + 1619 .cfi_offset 7, -8 + 1620 .cfi_offset 14, -4 + 1621 0002 0400 movs r4, r0 + 1622 0004 0E00 movs r6, r1 + 1623 0006 1700 movs r7, r2 + 1624 .LVL124: +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1625 .loc 1 1231 0 + 1626 0008 0368 ldr r3, [r0] + 1627 000a 9B68 ldr r3, [r3, #8] + 1628 000c 5B07 lsls r3, r3, #29 + 1629 000e 3ED4 bmi .L134 +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1630 .loc 1 1234 0 + 1631 0010 5423 movs r3, #84 + 1632 0012 C35C ldrb r3, [r0, r3] + 1633 0014 012B cmp r3, #1 + 1634 0016 3CD0 beq .L135 +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1635 .loc 1 1234 0 is_stmt 0 discriminator 2 + 1636 0018 5423 movs r3, #84 + 1637 001a 0122 movs r2, #1 + 1638 .LVL125: + 1639 001c C254 strb r2, [r0, r3] +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1640 .loc 1 1239 0 is_stmt 1 discriminator 2 + 1641 001e C369 ldr r3, [r0, #28] + 1642 0020 012B cmp r3, #1 + 1643 0022 32D0 beq .L136 +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1644 .loc 1 1241 0 + 1645 0024 FFF7FEFF bl ADC_Enable + 1646 .LVL126: + 1647 0028 051E subs r5, r0, #0 + 1648 .LVL127: +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + ARM GAS /tmp/ccHnSxqq.s page 72 + + + 1649 .loc 1 1245 0 + 1650 002a 2CD1 bne .L132 + 1651 .LVL128: + 1652 .L133: +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A + 1653 .loc 1 1250 0 + 1654 002c A36D ldr r3, [r4, #88] + 1655 002e 1A4A ldr r2, .L137 + 1656 0030 1A40 ands r2, r3 + 1657 0032 8023 movs r3, #128 + 1658 0034 5B00 lsls r3, r3, #1 + 1659 0036 1343 orrs r3, r2 + 1660 0038 A365 str r3, [r4, #88] +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1661 .loc 1 1255 0 + 1662 003a 0023 movs r3, #0 + 1663 003c E365 str r3, [r4, #92] +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1664 .loc 1 1260 0 + 1665 003e 5422 movs r2, #84 + 1666 0040 A354 strb r3, [r4, r2] +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1667 .loc 1 1263 0 + 1668 0042 236D ldr r3, [r4, #80] + 1669 0044 154A ldr r2, .L137+4 + 1670 0046 DA62 str r2, [r3, #44] +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1671 .loc 1 1266 0 + 1672 0048 236D ldr r3, [r4, #80] + 1673 004a 154A ldr r2, .L137+8 + 1674 004c 1A63 str r2, [r3, #48] +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1675 .loc 1 1269 0 + 1676 004e 236D ldr r3, [r4, #80] + 1677 0050 144A ldr r2, .L137+12 + 1678 0052 5A63 str r2, [r3, #52] +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1679 .loc 1 1278 0 + 1680 0054 2368 ldr r3, [r4] + 1681 0056 1C22 movs r2, #28 + 1682 0058 1A60 str r2, [r3] +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1683 .loc 1 1281 0 + 1684 005a 2268 ldr r2, [r4] + 1685 005c 5368 ldr r3, [r2, #4] + 1686 005e 1021 movs r1, #16 + 1687 0060 0B43 orrs r3, r1 + 1688 0062 5360 str r3, [r2, #4] +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1689 .loc 1 1284 0 + 1690 0064 2268 ldr r2, [r4] + 1691 0066 D368 ldr r3, [r2, #12] + 1692 0068 0F39 subs r1, r1, #15 + 1693 006a 0B43 orrs r3, r1 + 1694 006c D360 str r3, [r2, #12] +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1695 .loc 1 1287 0 + ARM GAS /tmp/ccHnSxqq.s page 73 + + + 1696 006e 2168 ldr r1, [r4] + 1697 0070 4031 adds r1, r1, #64 + 1698 0072 3B00 movs r3, r7 + 1699 0074 3200 movs r2, r6 + 1700 0076 206D ldr r0, [r4, #80] + 1701 0078 FFF7FEFF bl HAL_DMA_Start_IT + 1702 .LVL129: +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1703 .loc 1 1293 0 + 1704 007c 2268 ldr r2, [r4] + 1705 007e 9368 ldr r3, [r2, #8] + 1706 0080 0421 movs r1, #4 + 1707 0082 0B43 orrs r3, r1 + 1708 0084 9360 str r3, [r2, #8] + 1709 .L132: +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1710 .loc 1 1303 0 + 1711 0086 2800 movs r0, r5 + 1712 @ sp needed + 1713 .LVL130: + 1714 .LVL131: + 1715 .LVL132: + 1716 0088 F8BD pop {r3, r4, r5, r6, r7, pc} + 1717 .LVL133: + 1718 .L136: +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1719 .loc 1 1225 0 + 1720 008a 0025 movs r5, #0 + 1721 008c CEE7 b .L133 + 1722 .LVL134: + 1723 .L134: +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1724 .loc 1 1298 0 + 1725 008e 0225 movs r5, #2 + 1726 0090 F9E7 b .L132 + 1727 .L135: +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1728 .loc 1 1234 0 + 1729 0092 0225 movs r5, #2 + 1730 0094 F7E7 b .L132 + 1731 .L138: + 1732 0096 C046 .align 2 + 1733 .L137: + 1734 0098 FEF0FFFF .word -3842 + 1735 009c 00000000 .word ADC_DMAConvCplt + 1736 00a0 00000000 .word ADC_DMAHalfConvCplt + 1737 00a4 00000000 .word ADC_DMAError + 1738 .cfi_endproc + 1739 .LFE49: + 1741 .section .text.HAL_ADC_Stop_DMA,"ax",%progbits + 1742 .align 1 + 1743 .global HAL_ADC_Stop_DMA + 1744 .syntax unified + 1745 .code 16 + 1746 .thumb_func + 1747 .fpu softvfp + 1749 HAL_ADC_Stop_DMA: + ARM GAS /tmp/ccHnSxqq.s page 74 + + + 1750 .LFB50: +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1751 .loc 1 1314 0 + 1752 .cfi_startproc + 1753 @ args = 0, pretend = 0, frame = 0 + 1754 @ frame_needed = 0, uses_anonymous_args = 0 + 1755 .LVL135: + 1756 0000 70B5 push {r4, r5, r6, lr} + 1757 .LCFI13: + 1758 .cfi_def_cfa_offset 16 + 1759 .cfi_offset 4, -16 + 1760 .cfi_offset 5, -12 + 1761 .cfi_offset 6, -8 + 1762 .cfi_offset 14, -4 + 1763 0002 0500 movs r5, r0 + 1764 .LVL136: +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1765 .loc 1 1321 0 + 1766 0004 5423 movs r3, #84 + 1767 0006 C35C ldrb r3, [r0, r3] + 1768 0008 012B cmp r3, #1 + 1769 000a 32D0 beq .L145 +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1770 .loc 1 1321 0 is_stmt 0 discriminator 2 + 1771 000c 5423 movs r3, #84 + 1772 000e 0122 movs r2, #1 + 1773 0010 C254 strb r2, [r0, r3] +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1774 .loc 1 1324 0 is_stmt 1 discriminator 2 + 1775 0012 FFF7FEFF bl ADC_ConversionStop + 1776 .LVL137: + 1777 0016 041E subs r4, r0, #0 + 1778 .LVL138: +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1779 .loc 1 1327 0 discriminator 2 + 1780 0018 04D0 beq .L146 + 1781 .LVL139: + 1782 .L141: +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1783 .loc 1 1370 0 + 1784 001a 5423 movs r3, #84 + 1785 001c 0022 movs r2, #0 + 1786 001e EA54 strb r2, [r5, r3] + 1787 .LVL140: + 1788 .L140: +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1789 .loc 1 1374 0 + 1790 0020 2000 movs r0, r4 + 1791 @ sp needed + 1792 .LVL141: + 1793 0022 70BD pop {r4, r5, r6, pc} + 1794 .LVL142: + 1795 .L146: +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1796 .loc 1 1330 0 + 1797 0024 2A68 ldr r2, [r5] + 1798 0026 D368 ldr r3, [r2, #12] + ARM GAS /tmp/ccHnSxqq.s page 75 + + + 1799 0028 0121 movs r1, #1 + 1800 002a 8B43 bics r3, r1 + 1801 002c D360 str r3, [r2, #12] +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1802 .loc 1 1334 0 + 1803 002e 286D ldr r0, [r5, #80] + 1804 .LVL143: + 1805 0030 FFF7FEFF bl HAL_DMA_Abort + 1806 .LVL144: + 1807 0034 041E subs r4, r0, #0 + 1808 .LVL145: +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1809 .loc 1 1337 0 + 1810 0036 03D0 beq .L142 +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1811 .loc 1 1340 0 + 1812 0038 AB6D ldr r3, [r5, #88] + 1813 003a 4022 movs r2, #64 + 1814 003c 1343 orrs r3, r2 + 1815 003e AB65 str r3, [r5, #88] + 1816 .L142: +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1817 .loc 1 1344 0 + 1818 0040 2A68 ldr r2, [r5] + 1819 0042 5368 ldr r3, [r2, #4] + 1820 0044 1021 movs r1, #16 + 1821 0046 8B43 bics r3, r1 + 1822 0048 5360 str r3, [r2, #4] +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1823 .loc 1 1349 0 + 1824 004a 002C cmp r4, #0 + 1825 004c 0DD1 bne .L143 +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1826 .loc 1 1351 0 + 1827 004e 2800 movs r0, r5 + 1828 .LVL146: + 1829 0050 FFF7FEFF bl ADC_Disable + 1830 .LVL147: + 1831 0054 0400 movs r4, r0 + 1832 .LVL148: + 1833 .L144: +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1834 .loc 1 1359 0 + 1835 0056 002C cmp r4, #0 + 1836 0058 DFD1 bne .L141 +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 1837 .loc 1 1362 0 + 1838 005a AB6D ldr r3, [r5, #88] + 1839 005c 064A ldr r2, .L147 + 1840 005e 1340 ands r3, r2 + 1841 0060 0432 adds r2, r2, #4 + 1842 0062 FF32 adds r2, r2, #255 + 1843 0064 1343 orrs r3, r2 + 1844 0066 AB65 str r3, [r5, #88] + 1845 0068 D7E7 b .L141 + 1846 .LVL149: + 1847 .L143: + ARM GAS /tmp/ccHnSxqq.s page 76 + + +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1848 .loc 1 1355 0 + 1849 006a 2800 movs r0, r5 + 1850 .LVL150: + 1851 006c FFF7FEFF bl ADC_Disable + 1852 .LVL151: + 1853 0070 F1E7 b .L144 + 1854 .LVL152: + 1855 .L145: +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1856 .loc 1 1321 0 + 1857 0072 0224 movs r4, #2 + 1858 0074 D4E7 b .L140 + 1859 .L148: + 1860 0076 C046 .align 2 + 1861 .L147: + 1862 0078 FEFEFFFF .word -258 + 1863 .cfi_endproc + 1864 .LFE50: + 1866 .section .text.HAL_ADC_GetValue,"ax",%progbits + 1867 .align 1 + 1868 .global HAL_ADC_GetValue + 1869 .syntax unified + 1870 .code 16 + 1871 .thumb_func + 1872 .fpu softvfp + 1874 HAL_ADC_GetValue: + 1875 .LFB51: +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 1876 .loc 1 1396 0 + 1877 .cfi_startproc + 1878 @ args = 0, pretend = 0, frame = 0 + 1879 @ frame_needed = 0, uses_anonymous_args = 0 + 1880 @ link register save eliminated. + 1881 .LVL153: +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1882 .loc 1 1404 0 + 1883 0000 0368 ldr r3, [r0] + 1884 0002 186C ldr r0, [r3, #64] + 1885 .LVL154: +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1886 .loc 1 1405 0 + 1887 @ sp needed + 1888 0004 7047 bx lr + 1889 .cfi_endproc + 1890 .LFE51: + 1892 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits + 1893 .align 1 + 1894 .weak HAL_ADC_ConvCpltCallback + 1895 .syntax unified + 1896 .code 16 + 1897 .thumb_func + 1898 .fpu softvfp + 1900 HAL_ADC_ConvCpltCallback: + 1901 .LFB53: +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 1902 .loc 1 1535 0 + ARM GAS /tmp/ccHnSxqq.s page 77 + + + 1903 .cfi_startproc + 1904 @ args = 0, pretend = 0, frame = 0 + 1905 @ frame_needed = 0, uses_anonymous_args = 0 + 1906 @ link register save eliminated. + 1907 .LVL155: +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1908 .loc 1 1542 0 + 1909 @ sp needed + 1910 0000 7047 bx lr + 1911 .cfi_endproc + 1912 .LFE53: + 1914 .section .text.ADC_DMAConvCplt,"ax",%progbits + 1915 .align 1 + 1916 .syntax unified + 1917 .code 16 + 1918 .thumb_func + 1919 .fpu softvfp + 1921 ADC_DMAConvCplt: + 1922 .LFB64: +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 1923 .loc 1 2083 0 + 1924 .cfi_startproc + 1925 @ args = 0, pretend = 0, frame = 0 + 1926 @ frame_needed = 0, uses_anonymous_args = 0 + 1927 .LVL156: + 1928 0000 10B5 push {r4, lr} + 1929 .LCFI14: + 1930 .cfi_def_cfa_offset 8 + 1931 .cfi_offset 4, -8 + 1932 .cfi_offset 14, -4 +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1933 .loc 1 2085 0 + 1934 0002 836A ldr r3, [r0, #40] + 1935 .LVL157: +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1936 .loc 1 2088 0 + 1937 0004 9A6D ldr r2, [r3, #88] + 1938 0006 5021 movs r1, #80 + 1939 0008 1142 tst r1, r2 + 1940 000a 03D0 beq .L156 +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1941 .loc 1 2133 0 + 1942 000c 1B6D ldr r3, [r3, #80] + 1943 .LVL158: + 1944 000e 5B6B ldr r3, [r3, #52] + 1945 0010 9847 blx r3 + 1946 .LVL159: + 1947 .L151: +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1948 .loc 1 2135 0 + 1949 @ sp needed + 1950 0012 10BD pop {r4, pc} + 1951 .LVL160: + 1952 .L156: +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1953 .loc 1 2091 0 + 1954 0014 996D ldr r1, [r3, #88] + ARM GAS /tmp/ccHnSxqq.s page 78 + + + 1955 0016 8022 movs r2, #128 + 1956 0018 9200 lsls r2, r2, #2 + 1957 001a 0A43 orrs r2, r1 + 1958 001c 9A65 str r2, [r3, #88] +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 1959 .loc 1 2095 0 + 1960 001e 1A68 ldr r2, [r3] + 1961 0020 D068 ldr r0, [r2, #12] + 1962 .LVL161: + 1963 0022 C021 movs r1, #192 + 1964 0024 0901 lsls r1, r1, #4 + 1965 0026 0842 tst r0, r1 + 1966 0028 13D1 bne .L153 +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 1967 .loc 1 2095 0 is_stmt 0 discriminator 1 + 1968 002a 196A ldr r1, [r3, #32] + 1969 002c 0029 cmp r1, #0 + 1970 002e 10D1 bne .L153 +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1971 .loc 1 2099 0 is_stmt 1 + 1972 0030 1168 ldr r1, [r2] + 1973 0032 0907 lsls r1, r1, #28 + 1974 0034 0DD5 bpl .L153 +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 1975 .loc 1 2103 0 + 1976 0036 9168 ldr r1, [r2, #8] + 1977 0038 4907 lsls r1, r1, #29 + 1978 003a 0ED4 bmi .L154 +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 1979 .loc 1 2109 0 + 1980 003c 5168 ldr r1, [r2, #4] + 1981 003e 0C20 movs r0, #12 + 1982 0040 8143 bics r1, r0 + 1983 0042 5160 str r1, [r2, #4] +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 1984 .loc 1 2112 0 + 1985 0044 9A6D ldr r2, [r3, #88] + 1986 0046 0949 ldr r1, .L157 + 1987 0048 0A40 ands r2, r1 + 1988 004a 0431 adds r1, r1, #4 + 1989 004c FF31 adds r1, r1, #255 + 1990 004e 0A43 orrs r2, r1 + 1991 0050 9A65 str r2, [r3, #88] + 1992 .L153: +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 1993 .loc 1 2128 0 + 1994 0052 1800 movs r0, r3 + 1995 0054 FFF7FEFF bl HAL_ADC_ConvCpltCallback + 1996 .LVL162: + 1997 0058 DBE7 b .L151 + 1998 .LVL163: + 1999 .L154: +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2000 .loc 1 2119 0 + 2001 005a 9A6D ldr r2, [r3, #88] + 2002 005c 2021 movs r1, #32 + 2003 005e 0A43 orrs r2, r1 + ARM GAS /tmp/ccHnSxqq.s page 79 + + + 2004 0060 9A65 str r2, [r3, #88] +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2005 .loc 1 2122 0 + 2006 0062 DA6D ldr r2, [r3, #92] + 2007 0064 1F39 subs r1, r1, #31 + 2008 0066 0A43 orrs r2, r1 + 2009 0068 DA65 str r2, [r3, #92] + 2010 006a F2E7 b .L153 + 2011 .L158: + 2012 .align 2 + 2013 .L157: + 2014 006c FEFEFFFF .word -258 + 2015 .cfi_endproc + 2016 .LFE64: + 2018 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits + 2019 .align 1 + 2020 .weak HAL_ADC_ConvHalfCpltCallback + 2021 .syntax unified + 2022 .code 16 + 2023 .thumb_func + 2024 .fpu softvfp + 2026 HAL_ADC_ConvHalfCpltCallback: + 2027 .LFB54: +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2028 .loc 1 1550 0 + 2029 .cfi_startproc + 2030 @ args = 0, pretend = 0, frame = 0 + 2031 @ frame_needed = 0, uses_anonymous_args = 0 + 2032 @ link register save eliminated. + 2033 .LVL164: +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2034 .loc 1 1557 0 + 2035 @ sp needed + 2036 0000 7047 bx lr + 2037 .cfi_endproc + 2038 .LFE54: + 2040 .section .text.ADC_DMAHalfConvCplt,"ax",%progbits + 2041 .align 1 + 2042 .syntax unified + 2043 .code 16 + 2044 .thumb_func + 2045 .fpu softvfp + 2047 ADC_DMAHalfConvCplt: + 2048 .LFB65: +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 2049 .loc 1 2143 0 + 2050 .cfi_startproc + 2051 @ args = 0, pretend = 0, frame = 0 + 2052 @ frame_needed = 0, uses_anonymous_args = 0 + 2053 .LVL165: + 2054 0000 10B5 push {r4, lr} + 2055 .LCFI15: + 2056 .cfi_def_cfa_offset 8 + 2057 .cfi_offset 4, -8 + 2058 .cfi_offset 14, -4 +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2059 .loc 1 2145 0 + ARM GAS /tmp/ccHnSxqq.s page 80 + + + 2060 0002 806A ldr r0, [r0, #40] + 2061 .LVL166: +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2062 .loc 1 2148 0 + 2063 0004 FFF7FEFF bl HAL_ADC_ConvHalfCpltCallback + 2064 .LVL167: +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2065 .loc 1 2149 0 + 2066 @ sp needed + 2067 0008 10BD pop {r4, pc} + 2068 .cfi_endproc + 2069 .LFE65: + 2071 .section .text.HAL_ADC_LevelOutOfWindowCallback,"ax",%progbits + 2072 .align 1 + 2073 .weak HAL_ADC_LevelOutOfWindowCallback + 2074 .syntax unified + 2075 .code 16 + 2076 .thumb_func + 2077 .fpu softvfp + 2079 HAL_ADC_LevelOutOfWindowCallback: + 2080 .LFB55: +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2081 .loc 1 1565 0 + 2082 .cfi_startproc + 2083 @ args = 0, pretend = 0, frame = 0 + 2084 @ frame_needed = 0, uses_anonymous_args = 0 + 2085 @ link register save eliminated. + 2086 .LVL168: +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2087 .loc 1 1572 0 + 2088 @ sp needed + 2089 0000 7047 bx lr + 2090 .cfi_endproc + 2091 .LFE55: + 2093 .section .text.HAL_ADC_ErrorCallback,"ax",%progbits + 2094 .align 1 + 2095 .weak HAL_ADC_ErrorCallback + 2096 .syntax unified + 2097 .code 16 + 2098 .thumb_func + 2099 .fpu softvfp + 2101 HAL_ADC_ErrorCallback: + 2102 .LFB56: +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2103 .loc 1 1587 0 + 2104 .cfi_startproc + 2105 @ args = 0, pretend = 0, frame = 0 + 2106 @ frame_needed = 0, uses_anonymous_args = 0 + 2107 @ link register save eliminated. + 2108 .LVL169: +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2109 .loc 1 1594 0 + 2110 @ sp needed + 2111 0000 7047 bx lr + 2112 .cfi_endproc + 2113 .LFE56: + 2115 .section .text.ADC_DMAError,"ax",%progbits + ARM GAS /tmp/ccHnSxqq.s page 81 + + + 2116 .align 1 + 2117 .syntax unified + 2118 .code 16 + 2119 .thumb_func + 2120 .fpu softvfp + 2122 ADC_DMAError: + 2123 .LFB66: +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 2124 .loc 1 2157 0 + 2125 .cfi_startproc + 2126 @ args = 0, pretend = 0, frame = 0 + 2127 @ frame_needed = 0, uses_anonymous_args = 0 + 2128 .LVL170: + 2129 0000 10B5 push {r4, lr} + 2130 .LCFI16: + 2131 .cfi_def_cfa_offset 8 + 2132 .cfi_offset 4, -8 + 2133 .cfi_offset 14, -4 +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2134 .loc 1 2159 0 + 2135 0002 806A ldr r0, [r0, #40] + 2136 .LVL171: +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2137 .loc 1 2162 0 + 2138 0004 836D ldr r3, [r0, #88] + 2139 0006 4022 movs r2, #64 + 2140 0008 1343 orrs r3, r2 + 2141 000a 8365 str r3, [r0, #88] +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2142 .loc 1 2165 0 + 2143 000c C36D ldr r3, [r0, #92] + 2144 000e 3C3A subs r2, r2, #60 + 2145 0010 1343 orrs r3, r2 + 2146 0012 C365 str r3, [r0, #92] +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2147 .loc 1 2168 0 + 2148 0014 FFF7FEFF bl HAL_ADC_ErrorCallback + 2149 .LVL172: +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2150 .loc 1 2169 0 + 2151 @ sp needed + 2152 0018 10BD pop {r4, pc} + 2153 .cfi_endproc + 2154 .LFE66: + 2156 .section .text.HAL_ADC_IRQHandler,"ax",%progbits + 2157 .align 1 + 2158 .global HAL_ADC_IRQHandler + 2159 .syntax unified + 2160 .code 16 + 2161 .thumb_func + 2162 .fpu softvfp + 2164 HAL_ADC_IRQHandler: + 2165 .LFB52: +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 2166 .loc 1 1413 0 + 2167 .cfi_startproc + 2168 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccHnSxqq.s page 82 + + + 2169 @ frame_needed = 0, uses_anonymous_args = 0 + 2170 .LVL173: + 2171 0000 10B5 push {r4, lr} + 2172 .LCFI17: + 2173 .cfi_def_cfa_offset 8 + 2174 .cfi_offset 4, -8 + 2175 .cfi_offset 14, -4 + 2176 0002 0400 movs r4, r0 +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + 2177 .loc 1 1420 0 + 2178 0004 0368 ldr r3, [r0] + 2179 0006 1A68 ldr r2, [r3] + 2180 0008 5207 lsls r2, r2, #29 + 2181 000a 02D5 bpl .L165 +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + 2182 .loc 1 1420 0 is_stmt 0 discriminator 1 + 2183 000c 5A68 ldr r2, [r3, #4] + 2184 000e 5207 lsls r2, r2, #29 + 2185 0010 05D4 bmi .L166 + 2186 .L165: +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2187 .loc 1 1421 0 is_stmt 1 discriminator 3 + 2188 0012 1A68 ldr r2, [r3] +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + 2189 .loc 1 1420 0 discriminator 3 + 2190 0014 1207 lsls r2, r2, #28 + 2191 0016 2CD5 bpl .L167 +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2192 .loc 1 1421 0 + 2193 0018 5A68 ldr r2, [r3, #4] + 2194 001a 1207 lsls r2, r2, #28 + 2195 001c 29D5 bpl .L167 + 2196 .L166: +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2197 .loc 1 1424 0 + 2198 001e A26D ldr r2, [r4, #88] + 2199 0020 D206 lsls r2, r2, #27 + 2200 0022 04D4 bmi .L168 +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2201 .loc 1 1427 0 + 2202 0024 A16D ldr r1, [r4, #88] + 2203 0026 8022 movs r2, #128 + 2204 0028 9200 lsls r2, r2, #2 + 2205 002a 0A43 orrs r2, r1 + 2206 002c A265 str r2, [r4, #88] + 2207 .L168: +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 2208 .loc 1 1432 0 + 2209 002e D968 ldr r1, [r3, #12] + 2210 0030 C022 movs r2, #192 + 2211 0032 1201 lsls r2, r2, #4 + 2212 0034 1142 tst r1, r2 + 2213 0036 13D1 bne .L169 +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) + 2214 .loc 1 1432 0 is_stmt 0 discriminator 1 + 2215 0038 226A ldr r2, [r4, #32] + 2216 003a 002A cmp r2, #0 + ARM GAS /tmp/ccHnSxqq.s page 83 + + + 2217 003c 10D1 bne .L169 +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2218 .loc 1 1436 0 is_stmt 1 + 2219 003e 1A68 ldr r2, [r3] + 2220 0040 1207 lsls r2, r2, #28 + 2221 0042 0DD5 bpl .L169 +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2222 .loc 1 1440 0 + 2223 0044 9A68 ldr r2, [r3, #8] + 2224 0046 5207 lsls r2, r2, #29 + 2225 0048 34D4 bmi .L170 +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2226 .loc 1 1446 0 + 2227 004a 5A68 ldr r2, [r3, #4] + 2228 004c 0C21 movs r1, #12 + 2229 004e 8A43 bics r2, r1 + 2230 0050 5A60 str r2, [r3, #4] +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY, + 2231 .loc 1 1449 0 + 2232 0052 A36D ldr r3, [r4, #88] + 2233 0054 224A ldr r2, .L176 + 2234 0056 1340 ands r3, r2 + 2235 0058 0432 adds r2, r2, #4 + 2236 005a FF32 adds r2, r2, #255 + 2237 005c 1343 orrs r3, r2 + 2238 005e A365 str r3, [r4, #88] + 2239 .L169: +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2240 .loc 1 1468 0 + 2241 0060 2000 movs r0, r4 + 2242 .LVL174: + 2243 0062 FFF7FEFF bl HAL_ADC_ConvCpltCallback + 2244 .LVL175: +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2245 .loc 1 1480 0 + 2246 0066 A369 ldr r3, [r4, #24] + 2247 0068 012B cmp r3, #1 + 2248 006a 02D0 beq .L167 +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2249 .loc 1 1482 0 + 2250 006c 2368 ldr r3, [r4] + 2251 006e 0C22 movs r2, #12 + 2252 0070 1A60 str r2, [r3] + 2253 .L167: +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2254 .loc 1 1487 0 + 2255 0072 2368 ldr r3, [r4] + 2256 0074 1A68 ldr r2, [r3] + 2257 0076 1206 lsls r2, r2, #24 + 2258 0078 02D5 bpl .L171 +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2259 .loc 1 1487 0 is_stmt 0 discriminator 1 + 2260 007a 5B68 ldr r3, [r3, #4] + 2261 007c 1B06 lsls r3, r3, #24 + 2262 007e 22D4 bmi .L175 + 2263 .L171: +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + ARM GAS /tmp/ccHnSxqq.s page 84 + + + 2264 .loc 1 1502 0 is_stmt 1 + 2265 0080 2368 ldr r3, [r4] + 2266 0082 1A68 ldr r2, [r3] + 2267 0084 D206 lsls r2, r2, #27 + 2268 0086 14D5 bpl .L164 +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2269 .loc 1 1502 0 is_stmt 0 discriminator 1 + 2270 0088 5A68 ldr r2, [r3, #4] + 2271 008a D206 lsls r2, r2, #27 + 2272 008c 11D5 bpl .L164 +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) + 2273 .loc 1 1510 0 is_stmt 1 + 2274 008e 626B ldr r2, [r4, #52] + 2275 0090 002A cmp r2, #0 + 2276 0092 02D0 beq .L173 +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2277 .loc 1 1511 0 discriminator 1 + 2278 0094 DA68 ldr r2, [r3, #12] +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) + 2279 .loc 1 1510 0 discriminator 1 + 2280 0096 D207 lsls r2, r2, #31 + 2281 0098 08D5 bpl .L174 + 2282 .L173: +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2283 .loc 1 1514 0 + 2284 009a E26D ldr r2, [r4, #92] + 2285 009c 0221 movs r1, #2 + 2286 009e 0A43 orrs r2, r1 + 2287 00a0 E265 str r2, [r4, #92] +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2288 .loc 1 1517 0 + 2289 00a2 1022 movs r2, #16 + 2290 00a4 1A60 str r2, [r3] +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2291 .loc 1 1520 0 + 2292 00a6 2000 movs r0, r4 + 2293 00a8 FFF7FEFF bl HAL_ADC_ErrorCallback + 2294 .LVL176: + 2295 .L174: +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2296 .loc 1 1524 0 + 2297 00ac 2368 ldr r3, [r4] + 2298 00ae 1022 movs r2, #16 + 2299 00b0 1A60 str r2, [r3] + 2300 .L164: +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2301 .loc 1 1527 0 + 2302 @ sp needed + 2303 .LVL177: + 2304 00b2 10BD pop {r4, pc} + 2305 .LVL178: + 2306 .L170: +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2307 .loc 1 1456 0 + 2308 00b4 A36D ldr r3, [r4, #88] + 2309 00b6 2022 movs r2, #32 + 2310 00b8 1343 orrs r3, r2 + ARM GAS /tmp/ccHnSxqq.s page 85 + + + 2311 00ba A365 str r3, [r4, #88] +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2312 .loc 1 1459 0 + 2313 00bc E36D ldr r3, [r4, #92] + 2314 00be 1F3A subs r2, r2, #31 + 2315 00c0 1343 orrs r3, r2 + 2316 00c2 E365 str r3, [r4, #92] + 2317 00c4 CCE7 b .L169 + 2318 .LVL179: + 2319 .L175: +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2320 .loc 1 1490 0 + 2321 00c6 A26D ldr r2, [r4, #88] + 2322 00c8 8023 movs r3, #128 + 2323 00ca 5B02 lsls r3, r3, #9 + 2324 00cc 1343 orrs r3, r2 + 2325 00ce A365 str r3, [r4, #88] +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2326 .loc 1 1493 0 + 2327 00d0 2000 movs r0, r4 + 2328 00d2 FFF7FEFF bl HAL_ADC_LevelOutOfWindowCallback + 2329 .LVL180: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2330 .loc 1 1496 0 + 2331 00d6 2368 ldr r3, [r4] + 2332 00d8 8022 movs r2, #128 + 2333 00da 1A60 str r2, [r3] + 2334 00dc D0E7 b .L171 + 2335 .L177: + 2336 00de C046 .align 2 + 2337 .L176: + 2338 00e0 FEFEFFFF .word -258 + 2339 .cfi_endproc + 2340 .LFE52: + 2342 .section .text.HAL_ADC_ConfigChannel,"ax",%progbits + 2343 .align 1 + 2344 .global HAL_ADC_ConfigChannel + 2345 .syntax unified + 2346 .code 16 + 2347 .thumb_func + 2348 .fpu softvfp + 2350 HAL_ADC_ConfigChannel: + 2351 .LFB57: +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 2352 .loc 1 1638 0 + 2353 .cfi_startproc + 2354 @ args = 0, pretend = 0, frame = 8 + 2355 @ frame_needed = 0, uses_anonymous_args = 0 + 2356 .LVL181: + 2357 0000 30B5 push {r4, r5, lr} + 2358 .LCFI18: + 2359 .cfi_def_cfa_offset 12 + 2360 .cfi_offset 4, -12 + 2361 .cfi_offset 5, -8 + 2362 .cfi_offset 14, -4 + 2363 0002 83B0 sub sp, sp, #12 + 2364 .LCFI19: + ARM GAS /tmp/ccHnSxqq.s page 86 + + + 2365 .cfi_def_cfa_offset 24 + 2366 0004 0400 movs r4, r0 + 2367 0006 0D00 movs r5, r1 +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2368 .loc 1 1645 0 + 2369 0008 5423 movs r3, #84 + 2370 000a C35C ldrb r3, [r0, r3] + 2371 000c 012B cmp r3, #1 + 2372 000e 69D0 beq .L189 +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2373 .loc 1 1645 0 is_stmt 0 discriminator 2 + 2374 0010 5423 movs r3, #84 + 2375 0012 0122 movs r2, #1 + 2376 0014 C254 strb r2, [r0, r3] +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2377 .loc 1 1652 0 is_stmt 1 discriminator 2 + 2378 0016 0368 ldr r3, [r0] + 2379 0018 9A68 ldr r2, [r3, #8] + 2380 001a 5207 lsls r2, r2, #29 + 2381 001c 1CD4 bmi .L190 +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2382 .loc 1 1661 0 + 2383 001e 324A ldr r2, .L191 + 2384 0020 4968 ldr r1, [r1, #4] + 2385 .LVL182: + 2386 0022 9142 cmp r1, r2 + 2387 0024 3FD0 beq .L181 +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2388 .loc 1 1664 0 + 2389 0026 996A ldr r1, [r3, #40] + 2390 0028 2A68 ldr r2, [r5] + 2391 002a 5203 lsls r2, r2, #13 + 2392 002c 520B lsrs r2, r2, #13 + 2393 002e 0A43 orrs r2, r1 + 2394 0030 9A62 str r2, [r3, #40] +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2395 .loc 1 1672 0 + 2396 0032 2B68 ldr r3, [r5] + 2397 0034 5B03 lsls r3, r3, #13 + 2398 0036 1ED5 bpl .L182 +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2399 .loc 1 1674 0 + 2400 0038 2C4A ldr r2, .L191+4 + 2401 003a 1168 ldr r1, [r2] + 2402 003c 8023 movs r3, #128 + 2403 003e 1B04 lsls r3, r3, #16 + 2404 0040 0B43 orrs r3, r1 + 2405 0042 1360 str r3, [r2] + 2406 .LVL183: + 2407 .LBB10: + 2408 .LBB11: +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2409 .loc 1 2179 0 + 2410 0044 2A4B ldr r3, .L191+8 + 2411 0046 1868 ldr r0, [r3] + 2412 .LVL184: + 2413 0048 2A49 ldr r1, .L191+12 + ARM GAS /tmp/ccHnSxqq.s page 87 + + + 2414 004a FFF7FEFF bl __aeabi_uidiv + 2415 .LVL185: + 2416 004e 8300 lsls r3, r0, #2 + 2417 0050 1818 adds r0, r3, r0 + 2418 0052 4300 lsls r3, r0, #1 + 2419 0054 0193 str r3, [sp, #4] + 2420 0056 0BE0 b .L183 + 2421 .LVL186: + 2422 .L190: + 2423 .LBE11: + 2424 .LBE10: +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Process unlocked */ + 2425 .loc 1 1655 0 + 2426 0058 836D ldr r3, [r0, #88] + 2427 005a 2022 movs r2, #32 + 2428 005c 1343 orrs r3, r2 + 2429 005e 8365 str r3, [r0, #88] +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** return HAL_ERROR; + 2430 .loc 1 1657 0 + 2431 0060 5423 movs r3, #84 + 2432 0062 0022 movs r2, #0 + 2433 0064 C254 strb r2, [r0, r3] +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2434 .loc 1 1658 0 + 2435 0066 0120 movs r0, #1 + 2436 .LVL187: + 2437 0068 1BE0 b .L179 + 2438 .LVL188: + 2439 .L184: + 2440 .LBB13: + 2441 .LBB12: + 2442 .loc 1 2183 0 + 2443 006a 019B ldr r3, [sp, #4] + 2444 006c 013B subs r3, r3, #1 + 2445 006e 0193 str r3, [sp, #4] + 2446 .L183: +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2447 .loc 1 2181 0 + 2448 0070 019B ldr r3, [sp, #4] + 2449 0072 002B cmp r3, #0 + 2450 0074 F9D1 bne .L184 + 2451 .LVL189: + 2452 .L182: + 2453 .LBE12: + 2454 .LBE13: +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2455 .loc 1 1681 0 + 2456 0076 2B68 ldr r3, [r5] + 2457 0078 9B03 lsls r3, r3, #14 + 2458 007a 05D5 bpl .L185 +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2459 .loc 1 1683 0 + 2460 007c 1B4A ldr r2, .L191+4 + 2461 007e 1168 ldr r1, [r2] + 2462 0080 8023 movs r3, #128 + 2463 0082 DB03 lsls r3, r3, #15 + 2464 0084 0B43 orrs r3, r1 + ARM GAS /tmp/ccHnSxqq.s page 88 + + + 2465 0086 1360 str r3, [r2] + 2466 .L185: +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2467 .loc 1 1688 0 + 2468 0088 2B68 ldr r3, [r5] + 2469 008a DB03 lsls r3, r3, #15 + 2470 008c 05D5 bpl .L186 +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2471 .loc 1 1690 0 + 2472 008e 174A ldr r2, .L191+4 + 2473 0090 1168 ldr r1, [r2] + 2474 0092 8023 movs r3, #128 + 2475 0094 5B04 lsls r3, r3, #17 + 2476 0096 0B43 orrs r3, r1 + 2477 0098 1360 str r3, [r2] + 2478 .L186: +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2479 .loc 1 1724 0 + 2480 009a 5423 movs r3, #84 + 2481 009c 0022 movs r2, #0 + 2482 009e E254 strb r2, [r4, r3] +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2483 .loc 1 1727 0 + 2484 00a0 0020 movs r0, #0 + 2485 .L179: +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2486 .loc 1 1728 0 + 2487 00a2 03B0 add sp, sp, #12 + 2488 @ sp needed + 2489 .LVL190: + 2490 .LVL191: + 2491 00a4 30BD pop {r4, r5, pc} + 2492 .LVL192: + 2493 .L181: +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2494 .loc 1 1698 0 + 2495 00a6 996A ldr r1, [r3, #40] + 2496 00a8 2A68 ldr r2, [r5] + 2497 00aa 5203 lsls r2, r2, #13 + 2498 00ac 520B lsrs r2, r2, #13 + 2499 00ae 9143 bics r1, r2 + 2500 00b0 9962 str r1, [r3, #40] +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2501 .loc 1 1703 0 + 2502 00b2 2B68 ldr r3, [r5] + 2503 00b4 5B03 lsls r3, r3, #13 + 2504 00b6 04D5 bpl .L187 +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2505 .loc 1 1705 0 + 2506 00b8 0C4A ldr r2, .L191+4 + 2507 00ba 1368 ldr r3, [r2] + 2508 00bc 0E49 ldr r1, .L191+16 + 2509 00be 0B40 ands r3, r1 + 2510 00c0 1360 str r3, [r2] + 2511 .L187: +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2512 .loc 1 1709 0 + ARM GAS /tmp/ccHnSxqq.s page 89 + + + 2513 00c2 2B68 ldr r3, [r5] + 2514 00c4 9B03 lsls r3, r3, #14 + 2515 00c6 04D5 bpl .L188 +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2516 .loc 1 1711 0 + 2517 00c8 084A ldr r2, .L191+4 + 2518 00ca 1368 ldr r3, [r2] + 2519 00cc 0B49 ldr r1, .L191+20 + 2520 00ce 0B40 ands r3, r1 + 2521 00d0 1360 str r3, [r2] + 2522 .L188: +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2523 .loc 1 1716 0 + 2524 00d2 2B68 ldr r3, [r5] + 2525 00d4 DB03 lsls r3, r3, #15 + 2526 00d6 E0D5 bpl .L186 +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2527 .loc 1 1718 0 + 2528 00d8 044A ldr r2, .L191+4 + 2529 00da 1368 ldr r3, [r2] + 2530 00dc 0849 ldr r1, .L191+24 + 2531 00de 0B40 ands r3, r1 + 2532 00e0 1360 str r3, [r2] + 2533 00e2 DAE7 b .L186 + 2534 .LVL193: + 2535 .L189: +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2536 .loc 1 1645 0 + 2537 00e4 0220 movs r0, #2 + 2538 .LVL194: + 2539 00e6 DCE7 b .L179 + 2540 .L192: + 2541 .align 2 + 2542 .L191: + 2543 00e8 01100000 .word 4097 + 2544 00ec 08270140 .word 1073817352 + 2545 00f0 00000000 .word SystemCoreClock + 2546 00f4 40420F00 .word 1000000 + 2547 00f8 FFFF7FFF .word -8388609 + 2548 00fc FFFFBFFF .word -4194305 + 2549 0100 FFFFFFFE .word -16777217 + 2550 .cfi_endproc + 2551 .LFE57: + 2553 .section .text.HAL_ADC_AnalogWDGConfig,"ax",%progbits + 2554 .align 1 + 2555 .global HAL_ADC_AnalogWDGConfig + 2556 .syntax unified + 2557 .code 16 + 2558 .thumb_func + 2559 .fpu softvfp + 2561 HAL_ADC_AnalogWDGConfig: + 2562 .LFB58: +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 2563 .loc 1 1753 0 + 2564 .cfi_startproc + 2565 @ args = 0, pretend = 0, frame = 0 + 2566 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccHnSxqq.s page 90 + + + 2567 .LVL195: + 2568 0000 30B5 push {r4, r5, lr} + 2569 .LCFI20: + 2570 .cfi_def_cfa_offset 12 + 2571 .cfi_offset 4, -12 + 2572 .cfi_offset 5, -8 + 2573 .cfi_offset 14, -4 + 2574 .LVL196: +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2575 .loc 1 1774 0 + 2576 0002 5423 movs r3, #84 + 2577 0004 C35C ldrb r3, [r0, r3] + 2578 0006 012B cmp r3, #1 + 2579 0008 47D0 beq .L199 +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2580 .loc 1 1774 0 is_stmt 0 discriminator 2 + 2581 000a 5423 movs r3, #84 + 2582 000c 0122 movs r2, #1 + 2583 000e C254 strb r2, [r0, r3] +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2584 .loc 1 1781 0 is_stmt 1 discriminator 2 + 2585 0010 0368 ldr r3, [r0] + 2586 0012 9A68 ldr r2, [r3, #8] + 2587 0014 5207 lsls r2, r2, #29 + 2588 0016 3AD4 bmi .L195 +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** { + 2589 .loc 1 1784 0 + 2590 0018 8A68 ldr r2, [r1, #8] + 2591 001a 012A cmp r2, #1 + 2592 001c 32D0 beq .L200 +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2593 .loc 1 1792 0 + 2594 001e 5A68 ldr r2, [r3, #4] + 2595 0020 8024 movs r4, #128 + 2596 0022 A243 bics r2, r4 + 2597 0024 5A60 str r2, [r3, #4] + 2598 .L197: +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** ADC_CFGR1_AWDEN | + 2599 .loc 1 1799 0 + 2600 0026 0268 ldr r2, [r0] + 2601 0028 D368 ldr r3, [r2, #12] + 2602 002a 1D4C ldr r4, .L201 + 2603 002c 2340 ands r3, r4 + 2604 002e D360 str r3, [r2, #12] +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK)); + 2605 .loc 1 1803 0 + 2606 0030 0468 ldr r4, [r0] + 2607 0032 E368 ldr r3, [r4, #12] +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2608 .loc 1 1804 0 + 2609 0034 F822 movs r2, #248 + 2610 0036 D205 lsls r2, r2, #23 + 2611 0038 4D68 ldr r5, [r1, #4] + 2612 003a 2A40 ands r2, r5 +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK)); + 2613 .loc 1 1803 0 + 2614 003c 0D68 ldr r5, [r1] + ARM GAS /tmp/ccHnSxqq.s page 91 + + + 2615 003e 2A43 orrs r2, r5 + 2616 0040 1343 orrs r3, r2 + 2617 0042 E360 str r3, [r4, #12] +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres + 2618 .loc 1 1809 0 + 2619 0044 0568 ldr r5, [r0] + 2620 0046 EB68 ldr r3, [r5, #12] + 2621 0048 DB08 lsrs r3, r3, #3 + 2622 004a 0322 movs r2, #3 + 2623 004c 1340 ands r3, r2 + 2624 004e 5B00 lsls r3, r3, #1 + 2625 0050 CC68 ldr r4, [r1, #12] + 2626 0052 9C40 lsls r4, r4, r3 + 2627 .LVL197: +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2628 .loc 1 1810 0 + 2629 0054 0B69 ldr r3, [r1, #16] + 2630 0056 E968 ldr r1, [r5, #12] + 2631 .LVL198: + 2632 0058 C908 lsrs r1, r1, #3 + 2633 005a 0A40 ands r2, r1 + 2634 005c 5200 lsls r2, r2, #1 + 2635 005e 9340 lsls r3, r3, r2 + 2636 0060 1A00 movs r2, r3 + 2637 .LVL199: +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2638 .loc 1 1813 0 + 2639 0062 2B6A ldr r3, [r5, #32] + 2640 0064 0F49 ldr r1, .L201+4 + 2641 0066 0B40 ands r3, r1 + 2642 0068 2B62 str r3, [r5, #32] +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Set the low threshold */ + 2643 .loc 1 1816 0 + 2644 006a 0168 ldr r1, [r0] + 2645 006c 2404 lsls r4, r4, #16 + 2646 .LVL200: + 2647 006e 0C62 str r4, [r1, #32] +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2648 .loc 1 1818 0 + 2649 0070 0168 ldr r1, [r0] + 2650 0072 0B6A ldr r3, [r1, #32] + 2651 0074 1343 orrs r3, r2 + 2652 0076 0B62 str r3, [r1, #32] +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2653 .loc 1 1754 0 + 2654 0078 0023 movs r3, #0 + 2655 .LVL201: + 2656 .L198: +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2657 .loc 1 1831 0 + 2658 007a 5422 movs r2, #84 + 2659 007c 0021 movs r1, #0 + 2660 007e 8154 strb r1, [r0, r2] + 2661 .LVL202: + 2662 .L194: +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2663 .loc 1 1835 0 + ARM GAS /tmp/ccHnSxqq.s page 92 + + + 2664 0080 1800 movs r0, r3 + 2665 .LVL203: + 2666 @ sp needed + 2667 0082 30BD pop {r4, r5, pc} + 2668 .LVL204: + 2669 .L200: +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2670 .loc 1 1787 0 + 2671 0084 5A68 ldr r2, [r3, #4] + 2672 0086 8024 movs r4, #128 + 2673 0088 2243 orrs r2, r4 + 2674 008a 5A60 str r2, [r3, #4] + 2675 008c CBE7 b .L197 + 2676 .L195: +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2677 .loc 1 1825 0 + 2678 008e 836D ldr r3, [r0, #88] + 2679 0090 2022 movs r2, #32 + 2680 0092 1343 orrs r3, r2 + 2681 0094 8365 str r3, [r0, #88] + 2682 .LVL205: +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2683 .loc 1 1827 0 + 2684 0096 0123 movs r3, #1 + 2685 0098 EFE7 b .L198 + 2686 .LVL206: + 2687 .L199: +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2688 .loc 1 1774 0 + 2689 009a 0223 movs r3, #2 + 2690 009c F0E7 b .L194 + 2691 .L202: + 2692 009e C046 .align 2 + 2693 .L201: + 2694 00a0 FFFF3F83 .word -2092957697 + 2695 00a4 00F000F0 .word -268374016 + 2696 .cfi_endproc + 2697 .LFE58: + 2699 .section .text.HAL_ADC_GetState,"ax",%progbits + 2700 .align 1 + 2701 .global HAL_ADC_GetState + 2702 .syntax unified + 2703 .code 16 + 2704 .thumb_func + 2705 .fpu softvfp + 2707 HAL_ADC_GetState: + 2708 .LFB59: +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 2709 .loc 1 1870 0 + 2710 .cfi_startproc + 2711 @ args = 0, pretend = 0, frame = 0 + 2712 @ frame_needed = 0, uses_anonymous_args = 0 + 2713 @ link register save eliminated. + 2714 .LVL207: +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2715 .loc 1 1875 0 + 2716 0000 806D ldr r0, [r0, #88] + ARM GAS /tmp/ccHnSxqq.s page 93 + + + 2717 .LVL208: +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2718 .loc 1 1876 0 + 2719 @ sp needed + 2720 0002 7047 bx lr + 2721 .cfi_endproc + 2722 .LFE59: + 2724 .section .text.HAL_ADC_GetError,"ax",%progbits + 2725 .align 1 + 2726 .global HAL_ADC_GetError + 2727 .syntax unified + 2728 .code 16 + 2729 .thumb_func + 2730 .fpu softvfp + 2732 HAL_ADC_GetError: + 2733 .LFB60: +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** /* Check the parameters */ + 2734 .loc 1 1884 0 + 2735 .cfi_startproc + 2736 @ args = 0, pretend = 0, frame = 0 + 2737 @ frame_needed = 0, uses_anonymous_args = 0 + 2738 @ link register save eliminated. + 2739 .LVL209: +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** } + 2740 .loc 1 1888 0 + 2741 0000 C06D ldr r0, [r0, #92] + 2742 .LVL210: +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c **** + 2743 .loc 1 1889 0 + 2744 @ sp needed + 2745 0002 7047 bx lr + 2746 .cfi_endproc + 2747 .LFE60: + 2749 .text + 2750 .Letext0: + 2751 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2752 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2753 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 2754 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 2755 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 2756 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 2757 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 2758 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 2759 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 2760 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 2761 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 2762 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h" + 2763 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccHnSxqq.s page 94 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_adc.c + /tmp/ccHnSxqq.s:16 .text.ADC_ConversionStop:0000000000000000 $t + /tmp/ccHnSxqq.s:22 .text.ADC_ConversionStop:0000000000000000 ADC_ConversionStop + /tmp/ccHnSxqq.s:106 .text.ADC_Disable:0000000000000000 $t + /tmp/ccHnSxqq.s:112 .text.ADC_Disable:0000000000000000 ADC_Disable + /tmp/ccHnSxqq.s:223 .text.ADC_Enable:0000000000000000 $t + /tmp/ccHnSxqq.s:229 .text.ADC_Enable:0000000000000000 ADC_Enable + /tmp/ccHnSxqq.s:363 .text.ADC_Enable:000000000000008c $d + /tmp/ccHnSxqq.s:370 .text.HAL_ADC_MspInit:0000000000000000 $t + /tmp/ccHnSxqq.s:377 .text.HAL_ADC_MspInit:0000000000000000 HAL_ADC_MspInit + /tmp/ccHnSxqq.s:392 .text.HAL_ADC_Init:0000000000000000 $t + /tmp/ccHnSxqq.s:399 .text.HAL_ADC_Init:0000000000000000 HAL_ADC_Init + /tmp/ccHnSxqq.s:731 .text.HAL_ADC_Init:00000000000001c8 $d + /tmp/ccHnSxqq.s:741 .text.HAL_ADC_MspDeInit:0000000000000000 $t + /tmp/ccHnSxqq.s:748 .text.HAL_ADC_MspDeInit:0000000000000000 HAL_ADC_MspDeInit + /tmp/ccHnSxqq.s:763 .text.HAL_ADC_DeInit:0000000000000000 $t + /tmp/ccHnSxqq.s:770 .text.HAL_ADC_DeInit:0000000000000000 HAL_ADC_DeInit + /tmp/ccHnSxqq.s:905 .text.HAL_ADC_DeInit:00000000000000a0 $d + /tmp/ccHnSxqq.s:915 .text.HAL_ADC_Start:0000000000000000 $t + /tmp/ccHnSxqq.s:922 .text.HAL_ADC_Start:0000000000000000 HAL_ADC_Start + /tmp/ccHnSxqq.s:1011 .text.HAL_ADC_Start:000000000000005c $d + /tmp/ccHnSxqq.s:1016 .text.HAL_ADC_Stop:0000000000000000 $t + /tmp/ccHnSxqq.s:1023 .text.HAL_ADC_Stop:0000000000000000 HAL_ADC_Stop + /tmp/ccHnSxqq.s:1092 .text.HAL_ADC_Stop:0000000000000040 $d + /tmp/ccHnSxqq.s:1097 .text.HAL_ADC_PollForConversion:0000000000000000 $t + /tmp/ccHnSxqq.s:1104 .text.HAL_ADC_PollForConversion:0000000000000000 HAL_ADC_PollForConversion + /tmp/ccHnSxqq.s:1262 .text.HAL_ADC_PollForConversion:00000000000000bc $d + /tmp/ccHnSxqq.s:1267 .text.HAL_ADC_PollForEvent:0000000000000000 $t + /tmp/ccHnSxqq.s:1274 .text.HAL_ADC_PollForEvent:0000000000000000 HAL_ADC_PollForEvent + /tmp/ccHnSxqq.s:1383 .text.HAL_ADC_Start_IT:0000000000000000 $t + /tmp/ccHnSxqq.s:1390 .text.HAL_ADC_Start_IT:0000000000000000 HAL_ADC_Start_IT + /tmp/ccHnSxqq.s:1506 .text.HAL_ADC_Start_IT:0000000000000084 $d + /tmp/ccHnSxqq.s:1511 .text.HAL_ADC_Stop_IT:0000000000000000 $t + /tmp/ccHnSxqq.s:1518 .text.HAL_ADC_Stop_IT:0000000000000000 HAL_ADC_Stop_IT + /tmp/ccHnSxqq.s:1593 .text.HAL_ADC_Stop_IT:000000000000004c $d + /tmp/ccHnSxqq.s:1598 .text.HAL_ADC_Start_DMA:0000000000000000 $t + /tmp/ccHnSxqq.s:1605 .text.HAL_ADC_Start_DMA:0000000000000000 HAL_ADC_Start_DMA + /tmp/ccHnSxqq.s:1734 .text.HAL_ADC_Start_DMA:0000000000000098 $d + /tmp/ccHnSxqq.s:1921 .text.ADC_DMAConvCplt:0000000000000000 ADC_DMAConvCplt + /tmp/ccHnSxqq.s:2047 .text.ADC_DMAHalfConvCplt:0000000000000000 ADC_DMAHalfConvCplt + /tmp/ccHnSxqq.s:2122 .text.ADC_DMAError:0000000000000000 ADC_DMAError + /tmp/ccHnSxqq.s:1742 .text.HAL_ADC_Stop_DMA:0000000000000000 $t + /tmp/ccHnSxqq.s:1749 .text.HAL_ADC_Stop_DMA:0000000000000000 HAL_ADC_Stop_DMA + /tmp/ccHnSxqq.s:1862 .text.HAL_ADC_Stop_DMA:0000000000000078 $d + /tmp/ccHnSxqq.s:1867 .text.HAL_ADC_GetValue:0000000000000000 $t + /tmp/ccHnSxqq.s:1874 .text.HAL_ADC_GetValue:0000000000000000 HAL_ADC_GetValue + /tmp/ccHnSxqq.s:1893 .text.HAL_ADC_ConvCpltCallback:0000000000000000 $t + /tmp/ccHnSxqq.s:1900 .text.HAL_ADC_ConvCpltCallback:0000000000000000 HAL_ADC_ConvCpltCallback + /tmp/ccHnSxqq.s:1915 .text.ADC_DMAConvCplt:0000000000000000 $t + /tmp/ccHnSxqq.s:2014 .text.ADC_DMAConvCplt:000000000000006c $d + /tmp/ccHnSxqq.s:2019 .text.HAL_ADC_ConvHalfCpltCallback:0000000000000000 $t + /tmp/ccHnSxqq.s:2026 .text.HAL_ADC_ConvHalfCpltCallback:0000000000000000 HAL_ADC_ConvHalfCpltCallback + /tmp/ccHnSxqq.s:2041 .text.ADC_DMAHalfConvCplt:0000000000000000 $t + /tmp/ccHnSxqq.s:2072 .text.HAL_ADC_LevelOutOfWindowCallback:0000000000000000 $t + /tmp/ccHnSxqq.s:2079 .text.HAL_ADC_LevelOutOfWindowCallback:0000000000000000 HAL_ADC_LevelOutOfWindowCallback + /tmp/ccHnSxqq.s:2094 .text.HAL_ADC_ErrorCallback:0000000000000000 $t + ARM GAS /tmp/ccHnSxqq.s page 95 + + + /tmp/ccHnSxqq.s:2101 .text.HAL_ADC_ErrorCallback:0000000000000000 HAL_ADC_ErrorCallback + /tmp/ccHnSxqq.s:2116 .text.ADC_DMAError:0000000000000000 $t + /tmp/ccHnSxqq.s:2157 .text.HAL_ADC_IRQHandler:0000000000000000 $t + /tmp/ccHnSxqq.s:2164 .text.HAL_ADC_IRQHandler:0000000000000000 HAL_ADC_IRQHandler + /tmp/ccHnSxqq.s:2338 .text.HAL_ADC_IRQHandler:00000000000000e0 $d + /tmp/ccHnSxqq.s:2343 .text.HAL_ADC_ConfigChannel:0000000000000000 $t + /tmp/ccHnSxqq.s:2350 .text.HAL_ADC_ConfigChannel:0000000000000000 HAL_ADC_ConfigChannel + /tmp/ccHnSxqq.s:2543 .text.HAL_ADC_ConfigChannel:00000000000000e8 $d + /tmp/ccHnSxqq.s:2554 .text.HAL_ADC_AnalogWDGConfig:0000000000000000 $t + /tmp/ccHnSxqq.s:2561 .text.HAL_ADC_AnalogWDGConfig:0000000000000000 HAL_ADC_AnalogWDGConfig + /tmp/ccHnSxqq.s:2694 .text.HAL_ADC_AnalogWDGConfig:00000000000000a0 $d + /tmp/ccHnSxqq.s:2700 .text.HAL_ADC_GetState:0000000000000000 $t + /tmp/ccHnSxqq.s:2707 .text.HAL_ADC_GetState:0000000000000000 HAL_ADC_GetState + /tmp/ccHnSxqq.s:2725 .text.HAL_ADC_GetError:0000000000000000 $t + /tmp/ccHnSxqq.s:2732 .text.HAL_ADC_GetError:0000000000000000 HAL_ADC_GetError + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GetTick +__aeabi_uidiv +SystemCoreClock +HAL_DMA_Start_IT +HAL_DMA_Abort diff --git a/build/stm32l0xx_hal_adc_ex.d b/build/stm32l0xx_hal_adc_ex.d new file mode 100644 index 0000000..5914f62 --- /dev/null +++ b/build/stm32l0xx_hal_adc_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_adc_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_adc_ex.lst b/build/stm32l0xx_hal_adc_ex.lst new file mode 100644 index 0000000..6e2b2e9 --- /dev/null +++ b/build/stm32l0xx_hal_adc_ex.lst @@ -0,0 +1,924 @@ +ARM GAS /tmp/ccS1GlwB.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_adc_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_ADCEx_Calibration_Start,"ax",%progbits + 16 .align 1 + 17 .global HAL_ADCEx_Calibration_Start + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_ADCEx_Calibration_Start: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @file stm32l0xx_hal_adc_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief This file provides firmware functions to manage the following + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * functionalities of the Analog to Digital Convertor (ADC) + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + Operation functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * ++ Calibration + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * +++ ADC automatic self-calibration + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * +++ Calibration factors get or set + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * Other functions (generic functions) are available in file + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * "stm32l0xx_hal_adc.c". + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** @verbatim + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** [..] + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** (@) Sections "ADC peripheral features" and "How to use this driver" are + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** available in file of generic functions "stm32l0xx_hal_adc.c". + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** [..] + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** @endverbatim + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ****************************************************************************** + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @attention + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * are permitted provided that the following conditions are met: + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * this list of conditions and the following disclaimer. + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * this list of conditions and the following disclaimer in the documentation + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * and/or other materials provided with the distribution. + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + ARM GAS /tmp/ccS1GlwB.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * may be used to endorse or promote products derived from this software + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * without specific prior written permission. + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ****************************************************************************** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** #include "stm32l0xx_hal.h" + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @{ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** @defgroup ADCEx ADCEx + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief ADC Extended HAL module driver + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @{ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** #ifdef HAL_ADC_MODULE_ENABLED + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Private define ------------------------------------------------------------*/ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @{ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Fixed timeout values for ADC calibration, enable settling time, disable */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* settling time. */ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Values defined to be higher than worst cases: low clock frequency, */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* maximum prescaler. */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Unit: ms */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** #define ADC_CALIBRATION_TIMEOUT 10U + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Delay for VREFINT stabilization time. */ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Internal reference startup time max value is 3ms (refer to device datasheet, parameter TVREFINT + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Unit: ms */ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** #define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3U) + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Delay for TEMPSENSOR stabilization time. */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Temperature sensor startup time max value is 10us (refer to device datasheet, parameter tSTART) + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Unit: ms */ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** #define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1U) + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Private variables ---------------------------------------------------------*/ + ARM GAS /tmp/ccS1GlwB.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Exported functions --------------------------------------------------------*/ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @{ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Extended IO operation functions + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** @verbatim + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** =============================================================================== + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ##### IO operation functions ##### + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** =============================================================================== + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** [..] This section provides functions allowing to: + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** (+) Perform the ADC calibration. + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** @endverbatim + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @{ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Perform an ADC automatic self-calibration + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * Calibration prerequisite: ADC must be disabled (execute this + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @note Calibration factor can be read after calibration, using function + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param hadc ADC handle + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param SingleDiff: Selection of single-ended or differential input + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * This parameter can be only of the following values: + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @arg ADC_SINGLE_ENDED: Channel in mode input single ended + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval HAL status + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 26 .loc 1 124 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 0400 movs r4, r0 + 39 .LVL1: + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t tickstart = 0U; + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t backup_setting_adc_dma_transfer = 0U; /* Note: Variable not declared as volatile because + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Check the parameters */ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Process locked */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + ARM GAS /tmp/ccS1GlwB.s page 4 + + + 40 .loc 1 133 0 + 41 0004 5423 movs r3, #84 + 42 0006 C35C ldrb r3, [r0, r3] + 43 0008 012B cmp r3, #1 + 44 000a 49D0 beq .L7 + 45 .loc 1 133 0 is_stmt 0 discriminator 2 + 46 000c 5423 movs r3, #84 + 47 000e 0122 movs r2, #1 + 48 0010 C254 strb r2, [r0, r3] + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Calibration prerequisite: ADC must be disabled. */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** if (ADC_IS_ENABLE(hadc) == RESET) + 49 .loc 1 136 0 is_stmt 1 discriminator 2 + 50 0012 0368 ldr r3, [r0] + 51 0014 9968 ldr r1, [r3, #8] + 52 .LVL2: + 53 0016 0232 adds r2, r2, #2 + 54 0018 0A40 ands r2, r1 + 55 001a 012A cmp r2, #1 + 56 001c 08D1 bne .L3 + 57 .loc 1 136 0 is_stmt 0 discriminator 1 + 58 001e 1A68 ldr r2, [r3] + 59 0020 D207 lsls r2, r2, #31 + 60 0022 05D5 bpl .L3 + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Set ADC state */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY, + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_BUSY_INTERNAL); + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Disable ADC DMA transfer request during calibration */ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Note: Specificity of this STM32 serie: Calibration factor is */ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* available in data register and also transfered by DMA. */ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* To not insert ADC calibration factor among ADC conversion data */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* in array variable, DMA transfer must be disabled during */ + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* calibration. */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_D + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Start ADC calibration */ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** hadc->Instance->CR |= ADC_CR_ADCAL; + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** tickstart = HAL_GetTick(); + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Wait for calibration completion */ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_ERROR_INTERNAL); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Process unlocked */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + ARM GAS /tmp/ccS1GlwB.s page 5 + + + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return HAL_ERROR; + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Restore ADC DMA transfer request after calibration */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Set ADC state */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_READY); + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** else + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 61 .loc 1 185 0 is_stmt 1 + 62 0024 836D ldr r3, [r0, #88] + 63 0026 2022 movs r2, #32 + 64 0028 1343 orrs r3, r2 + 65 002a 8365 str r3, [r0, #88] + 66 .LVL3: + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** tmp_hal_status = HAL_ERROR; + 67 .loc 1 187 0 + 68 002c 0120 movs r0, #1 + 69 .LVL4: + 70 002e 33E0 b .L4 + 71 .LVL5: + 72 .L3: + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY, + 73 .loc 1 139 0 + 74 0030 A26D ldr r2, [r4, #88] + 75 0032 1C49 ldr r1, .L9 + 76 0034 0A40 ands r2, r1 + 77 0036 0631 adds r1, r1, #6 + 78 0038 FF31 adds r1, r1, #255 + 79 003a 0A43 orrs r2, r1 + 80 003c A265 str r2, [r4, #88] + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + 81 .loc 1 149 0 + 82 003e DE68 ldr r6, [r3, #12] + 83 0040 0131 adds r1, r1, #1 + 84 0042 0E40 ands r6, r1 + 85 .LVL6: + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 86 .loc 1 150 0 + 87 0044 DA68 ldr r2, [r3, #12] + 88 0046 8A43 bics r2, r1 + 89 0048 DA60 str r2, [r3, #12] + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 90 .loc 1 153 0 + 91 004a 2268 ldr r2, [r4] + 92 004c 9168 ldr r1, [r2, #8] + 93 004e 8023 movs r3, #128 + 94 0050 1B06 lsls r3, r3, #24 + 95 0052 0B43 orrs r3, r1 + ARM GAS /tmp/ccS1GlwB.s page 6 + + + 96 0054 9360 str r3, [r2, #8] + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 97 .loc 1 155 0 + 98 0056 FFF7FEFF bl HAL_GetTick + 99 .LVL7: + 100 005a 0500 movs r5, r0 + 101 .LVL8: + 102 .L5: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 103 .loc 1 158 0 + 104 005c 2368 ldr r3, [r4] + 105 005e 9A68 ldr r2, [r3, #8] + 106 0060 002A cmp r2, #0 + 107 0062 0FDA bge .L8 + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 108 .loc 1 160 0 + 109 0064 FFF7FEFF bl HAL_GetTick + 110 .LVL9: + 111 0068 401B subs r0, r0, r5 + 112 006a 0A28 cmp r0, #10 + 113 006c F6D9 bls .L5 + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 114 .loc 1 163 0 + 115 006e A36D ldr r3, [r4, #88] + 116 0070 1222 movs r2, #18 + 117 0072 9343 bics r3, r2 + 118 0074 023A subs r2, r2, #2 + 119 0076 1343 orrs r3, r2 + 120 0078 A365 str r3, [r4, #88] + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 121 .loc 1 168 0 + 122 007a 5423 movs r3, #84 + 123 007c 0022 movs r2, #0 + 124 007e E254 strb r2, [r4, r3] + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 125 .loc 1 170 0 + 126 0080 0120 movs r0, #1 + 127 0082 0CE0 b .L2 + 128 .L8: + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 129 .loc 1 175 0 + 130 0084 DA68 ldr r2, [r3, #12] + 131 0086 1643 orrs r6, r2 + 132 .LVL10: + 133 0088 DE60 str r6, [r3, #12] + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 134 .loc 1 178 0 + 135 008a A36D ldr r3, [r4, #88] + 136 008c 0322 movs r2, #3 + 137 008e 9343 bics r3, r2 + 138 0090 023A subs r2, r2, #2 + 139 0092 1343 orrs r3, r2 + 140 0094 A365 str r3, [r4, #88] + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t tickstart = 0U; + 141 .loc 1 125 0 + 142 0096 0020 movs r0, #0 + 143 .LVL11: + ARM GAS /tmp/ccS1GlwB.s page 7 + + + 144 .L4: + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Process unlocked */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 145 .loc 1 191 0 + 146 0098 5423 movs r3, #84 + 147 009a 0022 movs r2, #0 + 148 009c E254 strb r2, [r4, r3] + 149 .LVL12: + 150 .L2: + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Return function status */ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return tmp_hal_status; + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 151 .loc 1 195 0 + 152 @ sp needed + 153 .LVL13: + 154 009e 70BD pop {r4, r5, r6, pc} + 155 .LVL14: + 156 .L7: + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 157 .loc 1 133 0 + 158 00a0 0220 movs r0, #2 + 159 .LVL15: + 160 00a2 FCE7 b .L2 + 161 .L10: + 162 .align 2 + 163 .L9: + 164 00a4 FDFEFFFF .word -259 + 165 .cfi_endproc + 166 .LFE39: + 168 .section .text.HAL_ADCEx_Calibration_GetValue,"ax",%progbits + 169 .align 1 + 170 .global HAL_ADCEx_Calibration_GetValue + 171 .syntax unified + 172 .code 16 + 173 .thumb_func + 174 .fpu softvfp + 176 HAL_ADCEx_Calibration_GetValue: + 177 .LFB40: + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Get the calibration factor. + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param hadc: ADC handle. + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param SingleDiff: This parameter can be only: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @arg ADC_SINGLE_ENDED: Channel in mode input single ended. + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval Calibration value. + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 178 .loc 1 205 0 + 179 .cfi_startproc + 180 @ args = 0, pretend = 0, frame = 0 + 181 @ frame_needed = 0, uses_anonymous_args = 0 + 182 @ link register save eliminated. + 183 .LVL16: + ARM GAS /tmp/ccS1GlwB.s page 8 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Check the parameters */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Return the ADC calibration value */ + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return ((hadc->Instance->CALFACT) & 0x0000007FU); + 184 .loc 1 211 0 + 185 0000 0268 ldr r2, [r0] + 186 0002 B423 movs r3, #180 + 187 0004 D358 ldr r3, [r2, r3] + 188 0006 7F20 movs r0, #127 + 189 .LVL17: + 190 0008 1840 ands r0, r3 + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 191 .loc 1 212 0 + 192 @ sp needed + 193 000a 7047 bx lr + 194 .cfi_endproc + 195 .LFE40: + 197 .section .text.HAL_ADCEx_Calibration_SetValue,"ax",%progbits + 198 .align 1 + 199 .global HAL_ADCEx_Calibration_SetValue + 200 .syntax unified + 201 .code 16 + 202 .thumb_func + 203 .fpu softvfp + 205 HAL_ADCEx_Calibration_SetValue: + 206 .LFB41: + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Set the calibration factor to overwrite automatic conversion result. + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * ADC must be enabled and no conversion is ongoing. + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param hadc: ADC handle + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param SingleDiff: This parameter can be only: + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @arg ADC_SINGLE_ENDED: Channel in mode input single ended. + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum) + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval HAL state + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 207 .loc 1 224 0 + 208 .cfi_startproc + 209 @ args = 0, pretend = 0, frame = 0 + 210 @ frame_needed = 0, uses_anonymous_args = 0 + 211 .LVL18: + 212 0000 30B5 push {r4, r5, lr} + 213 .LCFI1: + 214 .cfi_def_cfa_offset 12 + 215 .cfi_offset 4, -12 + 216 .cfi_offset 5, -8 + 217 .cfi_offset 14, -4 + 218 .LVL19: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Check the parameters */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + ARM GAS /tmp/ccS1GlwB.s page 9 + + + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** assert_param(IS_ADC_CALFACT(CalibrationFactor)); + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Process locked */ + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 219 .loc 1 233 0 + 220 0002 5423 movs r3, #84 + 221 0004 C35C ldrb r3, [r0, r3] + 222 0006 012B cmp r3, #1 + 223 0008 27D0 beq .L16 + 224 .loc 1 233 0 is_stmt 0 discriminator 2 + 225 000a 5423 movs r3, #84 + 226 000c 0121 movs r1, #1 + 227 .LVL20: + 228 000e C154 strb r1, [r0, r3] + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Verification of hardware constraints before modifying the calibration */ + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* factors register: ADC must be enabled, no conversion on going. */ + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** if ( (ADC_IS_ENABLE(hadc) != RESET) && + 229 .loc 1 237 0 is_stmt 1 discriminator 2 + 230 0010 0168 ldr r1, [r0] + 231 0012 8C68 ldr r4, [r1, #8] + 232 0014 513B subs r3, r3, #81 + 233 0016 2340 ands r3, r4 + 234 0018 012B cmp r3, #1 + 235 001a 0DD0 beq .L17 + 236 .L14: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Set the selected ADC calibration value */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** hadc->Instance->CALFACT |= CalibrationFactor; + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** else + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 237 .loc 1 247 0 + 238 001c 836D ldr r3, [r0, #88] + 239 001e 1022 movs r2, #16 + 240 .LVL21: + 241 0020 1343 orrs r3, r2 + 242 0022 8365 str r3, [r0, #88] + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 243 .loc 1 249 0 + 244 0024 C36D ldr r3, [r0, #92] + 245 0026 0F3A subs r2, r2, #15 + 246 0028 1343 orrs r3, r2 + 247 002a C365 str r3, [r0, #92] + 248 .LVL22: + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** tmp_hal_status = HAL_ERROR; + 249 .loc 1 252 0 + 250 002c 0123 movs r3, #1 + 251 .LVL23: + 252 .L15: + ARM GAS /tmp/ccS1GlwB.s page 10 + + + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Process unlocked */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 253 .loc 1 256 0 + 254 002e 5422 movs r2, #84 + 255 0030 0021 movs r1, #0 + 256 0032 8154 strb r1, [r0, r2] + 257 .LVL24: + 258 .L13: + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Return function status */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return tmp_hal_status; + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 259 .loc 1 260 0 + 260 0034 1800 movs r0, r3 + 261 .LVL25: + 262 @ sp needed + 263 0036 30BD pop {r4, r5, pc} + 264 .LVL26: + 265 .L17: + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + 266 .loc 1 237 0 discriminator 1 + 267 0038 0B68 ldr r3, [r1] + 268 003a DB07 lsls r3, r3, #31 + 269 003c EED5 bpl .L14 + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 270 .loc 1 238 0 + 271 003e 8B68 ldr r3, [r1, #8] + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + 272 .loc 1 237 0 + 273 0040 5B07 lsls r3, r3, #29 + 274 0042 EBD4 bmi .L14 + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** hadc->Instance->CALFACT |= CalibrationFactor; + 275 .loc 1 241 0 + 276 0044 B423 movs r3, #180 + 277 0046 CC58 ldr r4, [r1, r3] + 278 0048 7F25 movs r5, #127 + 279 004a AC43 bics r4, r5 + 280 004c CC50 str r4, [r1, r3] + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 281 .loc 1 242 0 + 282 004e 0468 ldr r4, [r0] + 283 0050 E158 ldr r1, [r4, r3] + 284 0052 0A43 orrs r2, r1 + 285 .LVL27: + 286 0054 E250 str r2, [r4, r3] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 287 .loc 1 225 0 + 288 0056 0023 movs r3, #0 + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 289 .loc 1 242 0 + 290 0058 E9E7 b .L15 + 291 .LVL28: + 292 .L16: + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 293 .loc 1 233 0 + ARM GAS /tmp/ccS1GlwB.s page 11 + + + 294 005a 0223 movs r3, #2 + 295 005c EAE7 b .L13 + 296 .cfi_endproc + 297 .LFE41: + 299 .section .text.HAL_ADCEx_EnableVREFINT,"ax",%progbits + 300 .align 1 + 301 .global HAL_ADCEx_EnableVREFINT + 302 .syntax unified + 303 .code 16 + 304 .thumb_func + 305 .fpu softvfp + 307 HAL_ADCEx_EnableVREFINT: + 308 .LFB42: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Enables the buffer of Vrefint for the ADC, required when device is in mode low-power (l + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * This function must be called before function HAL_ADC_Init() + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first) + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * For more details on procedure and buffer current consumption, refer to device reference + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @note This is functional only if the LOCK is not set. + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval None + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void) + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 309 .loc 1 271 0 + 310 .cfi_startproc + 311 @ args = 0, pretend = 0, frame = 0 + 312 @ frame_needed = 0, uses_anonymous_args = 0 + 313 0000 10B5 push {r4, lr} + 314 .LCFI2: + 315 .cfi_def_cfa_offset 8 + 316 .cfi_offset 4, -8 + 317 .cfi_offset 14, -4 + 318 .LVL29: + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t tickstart = 0U; + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); + 319 .loc 1 275 0 + 320 0002 0B4A ldr r2, .L24 + 321 0004 116A ldr r1, [r2, #32] + 322 0006 8023 movs r3, #128 + 323 0008 5B00 lsls r3, r3, #1 + 324 000a 0B43 orrs r3, r1 + 325 000c 1362 str r3, [r2, #32] + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Wait for Vrefint buffer effectively enabled */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Get tick count */ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** tickstart = HAL_GetTick(); + 326 .loc 1 279 0 + 327 000e FFF7FEFF bl HAL_GetTick + 328 .LVL30: + 329 0012 0400 movs r4, r0 + 330 .LVL31: + 331 .L19: + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF)) + ARM GAS /tmp/ccS1GlwB.s page 12 + + + 332 .loc 1 281 0 + 333 0014 064B ldr r3, .L24 + 334 0016 1B6A ldr r3, [r3, #32] + 335 0018 5B00 lsls r3, r3, #1 + 336 001a 06D4 bmi .L23 + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT) + 337 .loc 1 283 0 + 338 001c FFF7FEFF bl HAL_GetTick + 339 .LVL32: + 340 0020 001B subs r0, r0, r4 + 341 0022 0328 cmp r0, #3 + 342 0024 F6D9 bls .L19 + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return HAL_ERROR; + 343 .loc 1 285 0 + 344 0026 0120 movs r0, #1 + 345 0028 00E0 b .L20 + 346 .L23: + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return HAL_OK; + 347 .loc 1 289 0 + 348 002a 0020 movs r0, #0 + 349 .L20: + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 350 .loc 1 290 0 + 351 @ sp needed + 352 .LVL33: + 353 002c 10BD pop {r4, pc} + 354 .L25: + 355 002e C046 .align 2 + 356 .L24: + 357 0030 00000140 .word 1073807360 + 358 .cfi_endproc + 359 .LFE42: + 361 .section .text.HAL_ADCEx_DisableVREFINT,"ax",%progbits + 362 .align 1 + 363 .global HAL_ADCEx_DisableVREFINT + 364 .syntax unified + 365 .code 16 + 366 .thumb_func + 367 .fpu softvfp + 369 HAL_ADCEx_DisableVREFINT: + 370 .LFB43: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Disables the Buffer Vrefint for the ADC. + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @note This is functional only if the LOCK is not set. + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval None + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** void HAL_ADCEx_DisableVREFINT(void) + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 371 .loc 1 298 0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccS1GlwB.s page 13 + + + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 @ link register save eliminated. + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); + 376 .loc 1 300 0 + 377 0000 024A ldr r2, .L27 + 378 0002 136A ldr r3, [r2, #32] + 379 0004 0249 ldr r1, .L27+4 + 380 0006 0B40 ands r3, r1 + 381 0008 1362 str r3, [r2, #32] + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 382 .loc 1 301 0 + 383 @ sp needed + 384 000a 7047 bx lr + 385 .L28: + 386 .align 2 + 387 .L27: + 388 000c 00000140 .word 1073807360 + 389 0010 FFFEFFFF .word -257 + 390 .cfi_endproc + 391 .LFE43: + 393 .section .text.HAL_ADCEx_EnableVREFINTTempSensor,"ax",%progbits + 394 .align 1 + 395 .global HAL_ADCEx_EnableVREFINTTempSensor + 396 .syntax unified + 397 .code 16 + 398 .thumb_func + 399 .fpu softvfp + 401 HAL_ADCEx_EnableVREFINTTempSensor: + 402 .LFB44: + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Enables the buffer of temperature sensor for the ADC, required when device is in mode low + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * This function must be called before function HAL_ADC_Init() + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first) + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * For more details on procedure and buffer current consumption, refer to device reference m + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @note This is functional only if the LOCK is not set. + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval None + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void) + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 403 .loc 1 312 0 + 404 .cfi_startproc + 405 @ args = 0, pretend = 0, frame = 0 + 406 @ frame_needed = 0, uses_anonymous_args = 0 + 407 0000 10B5 push {r4, lr} + 408 .LCFI3: + 409 .cfi_def_cfa_offset 8 + 410 .cfi_offset 4, -8 + 411 .cfi_offset 14, -4 + 412 .LVL34: + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** uint32_t tickstart = 0U; + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); + 413 .loc 1 316 0 + 414 0002 0B4A ldr r2, .L35 + ARM GAS /tmp/ccS1GlwB.s page 14 + + + 415 0004 116A ldr r1, [r2, #32] + 416 0006 8023 movs r3, #128 + 417 0008 9B00 lsls r3, r3, #2 + 418 000a 0B43 orrs r3, r1 + 419 000c 1362 str r3, [r2, #32] + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Wait for Vrefint buffer effectively enabled */ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Get tick count */ + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** tickstart = HAL_GetTick(); + 420 .loc 1 320 0 + 421 000e FFF7FEFF bl HAL_GetTick + 422 .LVL35: + 423 0012 0400 movs r4, r0 + 424 .LVL36: + 425 .L30: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF)) + 426 .loc 1 322 0 + 427 0014 064B ldr r3, .L35 + 428 0016 1B6A ldr r3, [r3, #32] + 429 0018 5B00 lsls r3, r3, #1 + 430 001a 06D4 bmi .L34 + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT) + 431 .loc 1 324 0 + 432 001c FFF7FEFF bl HAL_GetTick + 433 .LVL37: + 434 0020 001B subs r0, r0, r4 + 435 0022 0128 cmp r0, #1 + 436 0024 F6D9 bls .L30 + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return HAL_ERROR; + 437 .loc 1 326 0 + 438 0026 0120 movs r0, #1 + 439 0028 00E0 b .L31 + 440 .L34: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** return HAL_OK; + 441 .loc 1 330 0 + 442 002a 0020 movs r0, #0 + 443 .L31: + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 444 .loc 1 331 0 + 445 @ sp needed + 446 .LVL38: + 447 002c 10BD pop {r4, pc} + 448 .L36: + 449 002e C046 .align 2 + 450 .L35: + 451 0030 00000140 .word 1073807360 + 452 .cfi_endproc + 453 .LFE44: + 455 .section .text.HAL_ADCEx_DisableVREFINTTempSensor,"ax",%progbits + 456 .align 1 + 457 .global HAL_ADCEx_DisableVREFINTTempSensor + ARM GAS /tmp/ccS1GlwB.s page 15 + + + 458 .syntax unified + 459 .code 16 + 460 .thumb_func + 461 .fpu softvfp + 463 HAL_ADCEx_DisableVREFINTTempSensor: + 464 .LFB45: + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /** + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @brief Disables the VREFINT and Sensor for the ADC. + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @note This is functional only if the LOCK is not set. + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** * @retval None + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** */ + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** void HAL_ADCEx_DisableVREFINTTempSensor(void) + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** { + 465 .loc 1 339 0 + 466 .cfi_startproc + 467 @ args = 0, pretend = 0, frame = 0 + 468 @ frame_needed = 0, uses_anonymous_args = 0 + 469 @ link register save eliminated. + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); + 470 .loc 1 341 0 + 471 0000 024A ldr r2, .L38 + 472 0002 136A ldr r3, [r2, #32] + 473 0004 0249 ldr r1, .L38+4 + 474 0006 0B40 ands r3, r1 + 475 0008 1362 str r3, [r2, #32] + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c **** } + 476 .loc 1 342 0 + 477 @ sp needed + 478 000a 7047 bx lr + 479 .L39: + 480 .align 2 + 481 .L38: + 482 000c 00000140 .word 1073807360 + 483 0010 FFFDFFFF .word -513 + 484 .cfi_endproc + 485 .LFE45: + 487 .text + 488 .Letext0: + 489 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 490 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 491 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 492 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 493 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 494 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 495 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 496 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 497 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 498 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 499 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 500 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h" + 501 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccS1GlwB.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_adc_ex.c + /tmp/ccS1GlwB.s:16 .text.HAL_ADCEx_Calibration_Start:0000000000000000 $t + /tmp/ccS1GlwB.s:23 .text.HAL_ADCEx_Calibration_Start:0000000000000000 HAL_ADCEx_Calibration_Start + /tmp/ccS1GlwB.s:164 .text.HAL_ADCEx_Calibration_Start:00000000000000a4 $d + /tmp/ccS1GlwB.s:169 .text.HAL_ADCEx_Calibration_GetValue:0000000000000000 $t + /tmp/ccS1GlwB.s:176 .text.HAL_ADCEx_Calibration_GetValue:0000000000000000 HAL_ADCEx_Calibration_GetValue + /tmp/ccS1GlwB.s:198 .text.HAL_ADCEx_Calibration_SetValue:0000000000000000 $t + /tmp/ccS1GlwB.s:205 .text.HAL_ADCEx_Calibration_SetValue:0000000000000000 HAL_ADCEx_Calibration_SetValue + /tmp/ccS1GlwB.s:300 .text.HAL_ADCEx_EnableVREFINT:0000000000000000 $t + /tmp/ccS1GlwB.s:307 .text.HAL_ADCEx_EnableVREFINT:0000000000000000 HAL_ADCEx_EnableVREFINT + /tmp/ccS1GlwB.s:357 .text.HAL_ADCEx_EnableVREFINT:0000000000000030 $d + /tmp/ccS1GlwB.s:362 .text.HAL_ADCEx_DisableVREFINT:0000000000000000 $t + /tmp/ccS1GlwB.s:369 .text.HAL_ADCEx_DisableVREFINT:0000000000000000 HAL_ADCEx_DisableVREFINT + /tmp/ccS1GlwB.s:388 .text.HAL_ADCEx_DisableVREFINT:000000000000000c $d + /tmp/ccS1GlwB.s:394 .text.HAL_ADCEx_EnableVREFINTTempSensor:0000000000000000 $t + /tmp/ccS1GlwB.s:401 .text.HAL_ADCEx_EnableVREFINTTempSensor:0000000000000000 HAL_ADCEx_EnableVREFINTTempSensor + /tmp/ccS1GlwB.s:451 .text.HAL_ADCEx_EnableVREFINTTempSensor:0000000000000030 $d + /tmp/ccS1GlwB.s:456 .text.HAL_ADCEx_DisableVREFINTTempSensor:0000000000000000 $t + /tmp/ccS1GlwB.s:463 .text.HAL_ADCEx_DisableVREFINTTempSensor:0000000000000000 HAL_ADCEx_DisableVREFINTTempSensor + /tmp/ccS1GlwB.s:482 .text.HAL_ADCEx_DisableVREFINTTempSensor:000000000000000c $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/build/stm32l0xx_hal_comp.d b/build/stm32l0xx_hal_comp.d new file mode 100644 index 0000000..49b6966 --- /dev/null +++ b/build/stm32l0xx_hal_comp.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_comp.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_comp.lst b/build/stm32l0xx_hal_comp.lst new file mode 100644 index 0000000..1e9a007 --- /dev/null +++ b/build/stm32l0xx_hal_comp.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccN7bVXM.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_comp.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccN7bVXM.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_comp.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_comp_ex.d b/build/stm32l0xx_hal_comp_ex.d new file mode 100644 index 0000000..f5353e1 --- /dev/null +++ b/build/stm32l0xx_hal_comp_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_comp_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_comp_ex.lst b/build/stm32l0xx_hal_comp_ex.lst new file mode 100644 index 0000000..4103d13 --- /dev/null +++ b/build/stm32l0xx_hal_comp_ex.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cc5ogqer.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_comp_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc5ogqer.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_comp_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_cortex.d b/build/stm32l0xx_hal_cortex.d new file mode 100644 index 0000000..995cfb0 --- /dev/null +++ b/build/stm32l0xx_hal_cortex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_cortex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_cortex.lst b/build/stm32l0xx_hal_cortex.lst new file mode 100644 index 0000000..264d695 --- /dev/null +++ b/build/stm32l0xx_hal_cortex.lst @@ -0,0 +1,2621 @@ +ARM GAS /tmp/ccd4VzkJ.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_cortex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 16 .align 1 + 17 .global HAL_NVIC_SetPriority + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_NVIC_SetPriority: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @file stm32l0xx_hal_cortex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + Peripheral Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### How to use this driver ##### + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** =========================================================== + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This section provide functions allowing to configure the NVIC interrupts (IRQ). + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** The Cortex-M0+ exceptions are managed by CMSIS functions. + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Enable and Configure the priority of the selected IRQ Channels. + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** The priority can be 0..3. + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** -@- Lower priority values gives higher priority. + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** -@- Priority Order: + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#@) Lowest priority. + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#@) Lowest hardware priority (IRQn position). + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + ARM GAS /tmp/ccd4VzkJ.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ======================================================== + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Setup SysTick Timer for time base + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** is a CMSIS function that: + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x03). + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** inside the stm32l0xx_hal_cortex.c file. + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ****************************************************************************** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @attention + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * Redistribution and use in source and binary forms, with or without modification, + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * are permitted provided that the following conditions are met: + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * this list of conditions and the following disclaimer. + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * this list of conditions and the following disclaimer in the documentation + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * and/or other materials provided with the distribution. + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * may be used to endorse or promote products derived from this software + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * without specific prior written permission. + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ARM GAS /tmp/ccd4VzkJ.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ****************************************************************************** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #include "stm32l0xx_hal.h" + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief CORTEX HAL module driver + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Systick functionalities + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number . + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param PreemptPriority: The pre-emption priority for the IRQn channel. + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be a value between 0 and 3. + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param SubPriority: The subpriority level for the IRQ channel. + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * no subpriority supported in Cortex M0+ based products. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + ARM GAS /tmp/ccd4VzkJ.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 26 .loc 1 150 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 .LVL1: + 39 .LBB26: + 40 .LBB27: + 41 .file 2 "Drivers/CMSIS/Include/core_cm0plus.h" + 1:Drivers/CMSIS/Include/core_cm0plus.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm0plus.h **** * @file core_cm0plus.h + 3:Drivers/CMSIS/Include/core_cm0plus.h **** * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm0plus.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/core_cm0plus.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm0plus.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/core_cm0plus.h **** + 9:Drivers/CMSIS/Include/core_cm0plus.h **** All rights reserved. + 10:Drivers/CMSIS/Include/core_cm0plus.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/core_cm0plus.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/core_cm0plus.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/core_cm0plus.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/core_cm0plus.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/core_cm0plus.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/core_cm0plus.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/core_cm0plus.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/core_cm0plus.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/core_cm0plus.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/core_cm0plus.h **** * + 21:Drivers/CMSIS/Include/core_cm0plus.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/core_cm0plus.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/core_cm0plus.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/core_cm0plus.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/core_cm0plus.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/core_cm0plus.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/core_cm0plus.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/core_cm0plus.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/core_cm0plus.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/core_cm0plus.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/core_cm0plus.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/core_cm0plus.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/core_cm0plus.h **** + 34:Drivers/CMSIS/Include/core_cm0plus.h **** + 35:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __ICCARM__ ) + 36:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 37:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 38:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma clang system_header /* treat file as system include file */ + ARM GAS /tmp/ccd4VzkJ.s page 5 + + + 39:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 40:Drivers/CMSIS/Include/core_cm0plus.h **** + 41:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_GENERIC + 42:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_GENERIC + 43:Drivers/CMSIS/Include/core_cm0plus.h **** + 44:Drivers/CMSIS/Include/core_cm0plus.h **** #include + 45:Drivers/CMSIS/Include/core_cm0plus.h **** + 46:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 47:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" { + 48:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 49:Drivers/CMSIS/Include/core_cm0plus.h **** + 50:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 51:Drivers/CMSIS/Include/core_cm0plus.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 52:Drivers/CMSIS/Include/core_cm0plus.h **** CMSIS violates the following MISRA-C:2004 rules: + 53:Drivers/CMSIS/Include/core_cm0plus.h **** + 54:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 8.5, object/function definition in header file.
+ 55:Drivers/CMSIS/Include/core_cm0plus.h **** Function definitions in header files are used to allow 'inlining'. + 56:Drivers/CMSIS/Include/core_cm0plus.h **** + 57:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 58:Drivers/CMSIS/Include/core_cm0plus.h **** Unions are used for effective representation of core registers. + 59:Drivers/CMSIS/Include/core_cm0plus.h **** + 60:Drivers/CMSIS/Include/core_cm0plus.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 61:Drivers/CMSIS/Include/core_cm0plus.h **** Function-like macros are used to allow more efficient code. + 62:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 63:Drivers/CMSIS/Include/core_cm0plus.h **** + 64:Drivers/CMSIS/Include/core_cm0plus.h **** + 65:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 66:Drivers/CMSIS/Include/core_cm0plus.h **** * CMSIS definitions + 67:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 68:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 69:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup Cortex-M0+ + 70:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 71:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 72:Drivers/CMSIS/Include/core_cm0plus.h **** + 73:Drivers/CMSIS/Include/core_cm0plus.h **** /* CMSIS CM0+ definitions */ + 74:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS H + 75:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS H + 76:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + 77:Drivers/CMSIS/Include/core_cm0plus.h **** __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL versi + 78:Drivers/CMSIS/Include/core_cm0plus.h **** + 79:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORTEX_M (0x00U) /*!< Cortex-M Core * + 80:Drivers/CMSIS/Include/core_cm0plus.h **** + 81:Drivers/CMSIS/Include/core_cm0plus.h **** + 82:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM ) + 83:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for ARM Comp + 84:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE __inline /*!< inline keyword for ARM C + 85:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static __inline + 86:Drivers/CMSIS/Include/core_cm0plus.h **** + 87:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 88:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for ARM Comp + 89:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE __inline /*!< inline keyword for ARM C + 90:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static __inline + 91:Drivers/CMSIS/Include/core_cm0plus.h **** + 92:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ ) + 93:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for GNU Comp + 94:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for GNU C + 95:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline + ARM GAS /tmp/ccd4VzkJ.s page 6 + + + 96:Drivers/CMSIS/Include/core_cm0plus.h **** + 97:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ ) + 98:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for IAR Comp + 99:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for IAR C + 100:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline + 101:Drivers/CMSIS/Include/core_cm0plus.h **** + 102:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TMS470__ ) + 103:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for TI CCS C + 104:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline + 105:Drivers/CMSIS/Include/core_cm0plus.h **** + 106:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ ) + 107:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for TASKING + 108:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for TASKI + 109:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline + 110:Drivers/CMSIS/Include/core_cm0plus.h **** + 111:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ ) + 112:Drivers/CMSIS/Include/core_cm0plus.h **** #define __packed + 113:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM _asm /*!< asm keyword for COSMIC Co + 114:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for COSMIC + 115:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline + 116:Drivers/CMSIS/Include/core_cm0plus.h **** + 117:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 118:Drivers/CMSIS/Include/core_cm0plus.h **** #error Unknown compiler + 119:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 120:Drivers/CMSIS/Include/core_cm0plus.h **** + 121:Drivers/CMSIS/Include/core_cm0plus.h **** /** __FPU_USED indicates whether an FPU is used or not. + 122:Drivers/CMSIS/Include/core_cm0plus.h **** This core does not support an FPU at all + 123:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 124:Drivers/CMSIS/Include/core_cm0plus.h **** #define __FPU_USED 0U + 125:Drivers/CMSIS/Include/core_cm0plus.h **** + 126:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM ) + 127:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TARGET_FPU_VFP + 128:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 129:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 130:Drivers/CMSIS/Include/core_cm0plus.h **** + 131:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 132:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARM_PCS_VFP + 133:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 134:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 135:Drivers/CMSIS/Include/core_cm0plus.h **** + 136:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ ) + 137:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 138:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 139:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 140:Drivers/CMSIS/Include/core_cm0plus.h **** + 141:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ ) + 142:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARMVFP__ + 143:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 144:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 145:Drivers/CMSIS/Include/core_cm0plus.h **** + 146:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TMS470__ ) + 147:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TI_VFP_SUPPORT__ + 148:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 149:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 150:Drivers/CMSIS/Include/core_cm0plus.h **** + 151:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ ) + 152:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __FPU_VFP__ + ARM GAS /tmp/ccd4VzkJ.s page 7 + + + 153:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 154:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 155:Drivers/CMSIS/Include/core_cm0plus.h **** + 156:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ ) + 157:Drivers/CMSIS/Include/core_cm0plus.h **** #if ( __CSMC__ & 0x400U) + 158:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 159:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 160:Drivers/CMSIS/Include/core_cm0plus.h **** + 161:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 162:Drivers/CMSIS/Include/core_cm0plus.h **** + 163:Drivers/CMSIS/Include/core_cm0plus.h **** #include "core_cmInstr.h" /* Core Instruction Access */ + 164:Drivers/CMSIS/Include/core_cm0plus.h **** #include "core_cmFunc.h" /* Core Function Access */ + 165:Drivers/CMSIS/Include/core_cm0plus.h **** + 166:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 167:Drivers/CMSIS/Include/core_cm0plus.h **** } + 168:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 169:Drivers/CMSIS/Include/core_cm0plus.h **** + 170:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* __CORE_CM0PLUS_H_GENERIC */ + 171:Drivers/CMSIS/Include/core_cm0plus.h **** + 172:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CMSIS_GENERIC + 173:Drivers/CMSIS/Include/core_cm0plus.h **** + 174:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_DEPENDANT + 176:Drivers/CMSIS/Include/core_cm0plus.h **** + 177:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 178:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" { + 179:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 180:Drivers/CMSIS/Include/core_cm0plus.h **** + 181:Drivers/CMSIS/Include/core_cm0plus.h **** /* check device defines and use defaults */ + 182:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __CHECK_DEVICE_DEFINES + 183:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CM0PLUS_REV + 184:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_REV 0x0000U + 185:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__CM0PLUS_REV not defined in device header file; using default!" + 186:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 187:Drivers/CMSIS/Include/core_cm0plus.h **** + 188:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __MPU_PRESENT + 189:Drivers/CMSIS/Include/core_cm0plus.h **** #define __MPU_PRESENT 0U + 190:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 191:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 192:Drivers/CMSIS/Include/core_cm0plus.h **** + 193:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __VTOR_PRESENT + 194:Drivers/CMSIS/Include/core_cm0plus.h **** #define __VTOR_PRESENT 0U + 195:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__VTOR_PRESENT not defined in device header file; using default!" + 196:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 197:Drivers/CMSIS/Include/core_cm0plus.h **** + 198:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __NVIC_PRIO_BITS + 199:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_PRIO_BITS 2U + 200:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 201:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 202:Drivers/CMSIS/Include/core_cm0plus.h **** + 203:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __Vendor_SysTickConfig + 204:Drivers/CMSIS/Include/core_cm0plus.h **** #define __Vendor_SysTickConfig 0U + 205:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 206:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 207:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 208:Drivers/CMSIS/Include/core_cm0plus.h **** + 209:Drivers/CMSIS/Include/core_cm0plus.h **** /* IO definitions (access restrictions to peripheral registers) */ + ARM GAS /tmp/ccd4VzkJ.s page 8 + + + 210:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 211:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 212:Drivers/CMSIS/Include/core_cm0plus.h **** + 213:Drivers/CMSIS/Include/core_cm0plus.h **** IO Type Qualifiers are used + 214:Drivers/CMSIS/Include/core_cm0plus.h **** \li to specify the access to peripheral variables. + 215:Drivers/CMSIS/Include/core_cm0plus.h **** \li for automatic generation of peripheral register debug information. + 216:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 217:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 218:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 219:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 220:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 221:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 222:Drivers/CMSIS/Include/core_cm0plus.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 223:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 224:Drivers/CMSIS/Include/core_cm0plus.h **** + 225:Drivers/CMSIS/Include/core_cm0plus.h **** /* following defines should be used for structure members */ + 226:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 227:Drivers/CMSIS/Include/core_cm0plus.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 228:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 229:Drivers/CMSIS/Include/core_cm0plus.h **** + 230:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group Cortex-M0+ */ + 231:Drivers/CMSIS/Include/core_cm0plus.h **** + 232:Drivers/CMSIS/Include/core_cm0plus.h **** + 233:Drivers/CMSIS/Include/core_cm0plus.h **** + 234:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 235:Drivers/CMSIS/Include/core_cm0plus.h **** * Register Abstraction + 236:Drivers/CMSIS/Include/core_cm0plus.h **** Core Register contain: + 237:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register + 238:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Register + 239:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SCB Register + 240:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Register + 241:Drivers/CMSIS/Include/core_cm0plus.h **** - Core MPU Register + 242:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 243:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 244:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 245:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 246:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 247:Drivers/CMSIS/Include/core_cm0plus.h **** + 248:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 249:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 250:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CORE Status and Control Registers + 251:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Core Register type definitions. + 252:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 253:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 254:Drivers/CMSIS/Include/core_cm0plus.h **** + 255:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 256:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Application Program Status Register (APSR). + 257:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 258:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 259:Drivers/CMSIS/Include/core_cm0plus.h **** { + 260:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 261:Drivers/CMSIS/Include/core_cm0plus.h **** { + 262:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + 263:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 264:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 265:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 266:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + ARM GAS /tmp/ccd4VzkJ.s page 9 + + + 267:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 268:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 269:Drivers/CMSIS/Include/core_cm0plus.h **** } APSR_Type; + 270:Drivers/CMSIS/Include/core_cm0plus.h **** + 271:Drivers/CMSIS/Include/core_cm0plus.h **** /* APSR Register Definitions */ + 272:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Pos 31U /*!< APSR + 273:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 274:Drivers/CMSIS/Include/core_cm0plus.h **** + 275:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Pos 30U /*!< APSR + 276:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 277:Drivers/CMSIS/Include/core_cm0plus.h **** + 278:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Pos 29U /*!< APSR + 279:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 280:Drivers/CMSIS/Include/core_cm0plus.h **** + 281:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Pos 28U /*!< APSR + 282:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 283:Drivers/CMSIS/Include/core_cm0plus.h **** + 284:Drivers/CMSIS/Include/core_cm0plus.h **** + 285:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 286:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 287:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 288:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 289:Drivers/CMSIS/Include/core_cm0plus.h **** { + 290:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 291:Drivers/CMSIS/Include/core_cm0plus.h **** { + 292:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 293:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 294:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 295:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 296:Drivers/CMSIS/Include/core_cm0plus.h **** } IPSR_Type; + 297:Drivers/CMSIS/Include/core_cm0plus.h **** + 298:Drivers/CMSIS/Include/core_cm0plus.h **** /* IPSR Register Definitions */ + 299:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 300:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 301:Drivers/CMSIS/Include/core_cm0plus.h **** + 302:Drivers/CMSIS/Include/core_cm0plus.h **** + 303:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 304:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 305:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 306:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 307:Drivers/CMSIS/Include/core_cm0plus.h **** { + 308:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 309:Drivers/CMSIS/Include/core_cm0plus.h **** { + 310:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 311:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + 312:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + 313:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + 314:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 315:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 316:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 317:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 318:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 319:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 320:Drivers/CMSIS/Include/core_cm0plus.h **** } xPSR_Type; + 321:Drivers/CMSIS/Include/core_cm0plus.h **** + 322:Drivers/CMSIS/Include/core_cm0plus.h **** /* xPSR Register Definitions */ + 323:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Pos 31U /*!< xPSR + ARM GAS /tmp/ccd4VzkJ.s page 10 + + + 324:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 325:Drivers/CMSIS/Include/core_cm0plus.h **** + 326:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 327:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 328:Drivers/CMSIS/Include/core_cm0plus.h **** + 329:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Pos 29U /*!< xPSR + 330:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 331:Drivers/CMSIS/Include/core_cm0plus.h **** + 332:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Pos 28U /*!< xPSR + 333:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 334:Drivers/CMSIS/Include/core_cm0plus.h **** + 335:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Pos 24U /*!< xPSR + 336:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 337:Drivers/CMSIS/Include/core_cm0plus.h **** + 338:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 339:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 340:Drivers/CMSIS/Include/core_cm0plus.h **** + 341:Drivers/CMSIS/Include/core_cm0plus.h **** + 342:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 343:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Control Registers (CONTROL). + 344:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 345:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 346:Drivers/CMSIS/Include/core_cm0plus.h **** { + 347:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 348:Drivers/CMSIS/Include/core_cm0plus.h **** { + 349:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 350:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 351:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + 352:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 353:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 354:Drivers/CMSIS/Include/core_cm0plus.h **** } CONTROL_Type; + 355:Drivers/CMSIS/Include/core_cm0plus.h **** + 356:Drivers/CMSIS/Include/core_cm0plus.h **** /* CONTROL Register Definitions */ + 357:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 358:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 359:Drivers/CMSIS/Include/core_cm0plus.h **** + 360:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 361:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 362:Drivers/CMSIS/Include/core_cm0plus.h **** + 363:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CORE */ + 364:Drivers/CMSIS/Include/core_cm0plus.h **** + 365:Drivers/CMSIS/Include/core_cm0plus.h **** + 366:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 367:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 368:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 369:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the NVIC Registers + 370:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 371:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 372:Drivers/CMSIS/Include/core_cm0plus.h **** + 373:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 374:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 375:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 376:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 377:Drivers/CMSIS/Include/core_cm0plus.h **** { + 378:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 379:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0[31U]; + 380:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + ARM GAS /tmp/ccd4VzkJ.s page 11 + + + 381:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RSERVED1[31U]; + 382:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 383:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED2[31U]; + 384:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 385:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED3[31U]; + 386:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED4[64U]; + 387:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + 388:Drivers/CMSIS/Include/core_cm0plus.h **** } NVIC_Type; + 389:Drivers/CMSIS/Include/core_cm0plus.h **** + 390:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_NVIC */ + 391:Drivers/CMSIS/Include/core_cm0plus.h **** + 392:Drivers/CMSIS/Include/core_cm0plus.h **** + 393:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 394:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 395:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 396:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Control Block Registers + 397:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 398:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 399:Drivers/CMSIS/Include/core_cm0plus.h **** + 400:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 401:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Control Block (SCB). + 402:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 403:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 404:Drivers/CMSIS/Include/core_cm0plus.h **** { + 405:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 406:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 407:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__VTOR_PRESENT == 1U) + 408:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 409:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 410:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0; + 411:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 412:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 413:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 414:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 415:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED1; + 416:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registe + 417:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 418:Drivers/CMSIS/Include/core_cm0plus.h **** } SCB_Type; + 419:Drivers/CMSIS/Include/core_cm0plus.h **** + 420:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB CPUID Register Definitions */ + 421:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 422:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 423:Drivers/CMSIS/Include/core_cm0plus.h **** + 424:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 425:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 426:Drivers/CMSIS/Include/core_cm0plus.h **** + 427:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 428:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 429:Drivers/CMSIS/Include/core_cm0plus.h **** + 430:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 431:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 432:Drivers/CMSIS/Include/core_cm0plus.h **** + 433:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 434:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 435:Drivers/CMSIS/Include/core_cm0plus.h **** + 436:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */ + 437:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + ARM GAS /tmp/ccd4VzkJ.s page 12 + + + 438:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 439:Drivers/CMSIS/Include/core_cm0plus.h **** + 440:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 441:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 442:Drivers/CMSIS/Include/core_cm0plus.h **** + 443:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 444:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 445:Drivers/CMSIS/Include/core_cm0plus.h **** + 446:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 447:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 448:Drivers/CMSIS/Include/core_cm0plus.h **** + 449:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 450:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 451:Drivers/CMSIS/Include/core_cm0plus.h **** + 452:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 453:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 454:Drivers/CMSIS/Include/core_cm0plus.h **** + 455:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 456:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 457:Drivers/CMSIS/Include/core_cm0plus.h **** + 458:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 459:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 460:Drivers/CMSIS/Include/core_cm0plus.h **** + 461:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 462:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 463:Drivers/CMSIS/Include/core_cm0plus.h **** + 464:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__VTOR_PRESENT == 1U) + 465:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */ + 466:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB + 467:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 468:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 469:Drivers/CMSIS/Include/core_cm0plus.h **** + 470:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 471:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 472:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 473:Drivers/CMSIS/Include/core_cm0plus.h **** + 474:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 475:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 476:Drivers/CMSIS/Include/core_cm0plus.h **** + 477:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 478:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 479:Drivers/CMSIS/Include/core_cm0plus.h **** + 480:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 481:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 482:Drivers/CMSIS/Include/core_cm0plus.h **** + 483:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 484:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 485:Drivers/CMSIS/Include/core_cm0plus.h **** + 486:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Control Register Definitions */ + 487:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 488:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 489:Drivers/CMSIS/Include/core_cm0plus.h **** + 490:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 491:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 492:Drivers/CMSIS/Include/core_cm0plus.h **** + 493:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 494:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + ARM GAS /tmp/ccd4VzkJ.s page 13 + + + 495:Drivers/CMSIS/Include/core_cm0plus.h **** + 496:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Configuration Control Register Definitions */ + 497:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 498:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 499:Drivers/CMSIS/Include/core_cm0plus.h **** + 500:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 501:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 502:Drivers/CMSIS/Include/core_cm0plus.h **** + 503:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Handler Control and State Register Definitions */ + 504:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 505:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 506:Drivers/CMSIS/Include/core_cm0plus.h **** + 507:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SCB */ + 508:Drivers/CMSIS/Include/core_cm0plus.h **** + 509:Drivers/CMSIS/Include/core_cm0plus.h **** + 510:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 511:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 512:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 513:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Timer Registers. + 514:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 515:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 516:Drivers/CMSIS/Include/core_cm0plus.h **** + 517:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 518:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Timer (SysTick). + 519:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 520:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 521:Drivers/CMSIS/Include/core_cm0plus.h **** { + 522:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 523:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 524:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 525:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 526:Drivers/CMSIS/Include/core_cm0plus.h **** } SysTick_Type; + 527:Drivers/CMSIS/Include/core_cm0plus.h **** + 528:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Control / Status Register Definitions */ + 529:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 530:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 531:Drivers/CMSIS/Include/core_cm0plus.h **** + 532:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 533:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 534:Drivers/CMSIS/Include/core_cm0plus.h **** + 535:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 536:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 537:Drivers/CMSIS/Include/core_cm0plus.h **** + 538:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 539:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 540:Drivers/CMSIS/Include/core_cm0plus.h **** + 541:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Reload Register Definitions */ + 542:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 543:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 544:Drivers/CMSIS/Include/core_cm0plus.h **** + 545:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Current Register Definitions */ + 546:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 547:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 548:Drivers/CMSIS/Include/core_cm0plus.h **** + 549:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Calibration Register Definitions */ + 550:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 551:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + ARM GAS /tmp/ccd4VzkJ.s page 14 + + + 552:Drivers/CMSIS/Include/core_cm0plus.h **** + 553:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 554:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 555:Drivers/CMSIS/Include/core_cm0plus.h **** + 556:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 557:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 558:Drivers/CMSIS/Include/core_cm0plus.h **** + 559:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SysTick */ + 560:Drivers/CMSIS/Include/core_cm0plus.h **** + 561:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__MPU_PRESENT == 1U) + 562:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 563:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 564:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) + 565:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the Memory Protection Unit (MPU) + 566:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 567:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 568:Drivers/CMSIS/Include/core_cm0plus.h **** + 569:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 570:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Memory Protection Unit (MPU). + 571:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 572:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 573:Drivers/CMSIS/Include/core_cm0plus.h **** { + 574:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + 575:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + 576:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + 577:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register + 578:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re + 579:Drivers/CMSIS/Include/core_cm0plus.h **** } MPU_Type; + 580:Drivers/CMSIS/Include/core_cm0plus.h **** + 581:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Type Register Definitions */ + 582:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU + 583:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU + 584:Drivers/CMSIS/Include/core_cm0plus.h **** + 585:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU + 586:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU + 587:Drivers/CMSIS/Include/core_cm0plus.h **** + 588:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU + 589:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU + 590:Drivers/CMSIS/Include/core_cm0plus.h **** + 591:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Control Register Definitions */ + 592:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU + 593:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU + 594:Drivers/CMSIS/Include/core_cm0plus.h **** + 595:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU + 596:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU + 597:Drivers/CMSIS/Include/core_cm0plus.h **** + 598:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU + 599:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU + 600:Drivers/CMSIS/Include/core_cm0plus.h **** + 601:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Number Register Definitions */ + 602:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU + 603:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU + 604:Drivers/CMSIS/Include/core_cm0plus.h **** + 605:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Base Address Register Definitions */ + 606:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Pos 8U /*!< MPU + 607:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU + 608:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/ccd4VzkJ.s page 15 + + + 609:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU + 610:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU + 611:Drivers/CMSIS/Include/core_cm0plus.h **** + 612:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU + 613:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU + 614:Drivers/CMSIS/Include/core_cm0plus.h **** + 615:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Attribute and Size Register Definitions */ + 616:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU + 617:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU + 618:Drivers/CMSIS/Include/core_cm0plus.h **** + 619:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU + 620:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU + 621:Drivers/CMSIS/Include/core_cm0plus.h **** + 622:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU + 623:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU + 624:Drivers/CMSIS/Include/core_cm0plus.h **** + 625:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU + 626:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU + 627:Drivers/CMSIS/Include/core_cm0plus.h **** + 628:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Pos 18U /*!< MPU + 629:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU + 630:Drivers/CMSIS/Include/core_cm0plus.h **** + 631:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Pos 17U /*!< MPU + 632:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU + 633:Drivers/CMSIS/Include/core_cm0plus.h **** + 634:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Pos 16U /*!< MPU + 635:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU + 636:Drivers/CMSIS/Include/core_cm0plus.h **** + 637:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU + 638:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU + 639:Drivers/CMSIS/Include/core_cm0plus.h **** + 640:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU + 641:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU + 642:Drivers/CMSIS/Include/core_cm0plus.h **** + 643:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU + 644:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU + 645:Drivers/CMSIS/Include/core_cm0plus.h **** + 646:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_MPU */ + 647:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 648:Drivers/CMSIS/Include/core_cm0plus.h **** + 649:Drivers/CMSIS/Include/core_cm0plus.h **** + 650:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 651:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 652:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + 653:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ov + 654:Drivers/CMSIS/Include/core_cm0plus.h **** Therefore they are not covered by the Cortex-M0+ header file. + 655:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 656:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 657:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CoreDebug */ + 658:Drivers/CMSIS/Include/core_cm0plus.h **** + 659:Drivers/CMSIS/Include/core_cm0plus.h **** + 660:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 661:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 662:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_bitfield Core register bit field macros + 663:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + 664:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 665:Drivers/CMSIS/Include/core_cm0plus.h **** */ + ARM GAS /tmp/ccd4VzkJ.s page 16 + + + 666:Drivers/CMSIS/Include/core_cm0plus.h **** + 667:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 668:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a bit field value for use in a register bit range. + 669:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field. + 670:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of the bit field. + 671:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted value. + 672:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 673:Drivers/CMSIS/Include/core_cm0plus.h **** #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + 674:Drivers/CMSIS/Include/core_cm0plus.h **** + 675:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 676:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a register value to extract a bit filed value. + 677:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field. + 678:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of register. + 679:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted bit field value. + 680:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 681:Drivers/CMSIS/Include/core_cm0plus.h **** #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + 682:Drivers/CMSIS/Include/core_cm0plus.h **** + 683:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_core_bitfield */ + 684:Drivers/CMSIS/Include/core_cm0plus.h **** + 685:Drivers/CMSIS/Include/core_cm0plus.h **** + 686:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 687:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 688:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_base Core Definitions + 689:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Definitions for base addresses, unions, and structures. + 690:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 691:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 692:Drivers/CMSIS/Include/core_cm0plus.h **** + 693:Drivers/CMSIS/Include/core_cm0plus.h **** /* Memory mapping of Cortex-M0+ Hardware */ + 694:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas + 695:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + 696:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + 697:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas + 698:Drivers/CMSIS/Include/core_cm0plus.h **** + 699:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct + 700:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st + 701:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc + 702:Drivers/CMSIS/Include/core_cm0plus.h **** + 703:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__MPU_PRESENT == 1U) + 704:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * + 705:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * + 706:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 707:Drivers/CMSIS/Include/core_cm0plus.h **** + 708:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} */ + 709:Drivers/CMSIS/Include/core_cm0plus.h **** + 710:Drivers/CMSIS/Include/core_cm0plus.h **** + 711:Drivers/CMSIS/Include/core_cm0plus.h **** + 712:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 713:Drivers/CMSIS/Include/core_cm0plus.h **** * Hardware Abstraction Layer + 714:Drivers/CMSIS/Include/core_cm0plus.h **** Core Function Interface contains: + 715:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Functions + 716:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Functions + 717:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register Access Functions + 718:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 719:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 720:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + 721:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 722:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/ccd4VzkJ.s page 17 + + + 723:Drivers/CMSIS/Include/core_cm0plus.h **** + 724:Drivers/CMSIS/Include/core_cm0plus.h **** + 725:Drivers/CMSIS/Include/core_cm0plus.h **** /* ########################## NVIC functions #################################### */ + 726:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 727:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface + 728:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions + 729:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that manage interrupts and exceptions via the NVIC. + 730:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 731:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 732:Drivers/CMSIS/Include/core_cm0plus.h **** + 733:Drivers/CMSIS/Include/core_cm0plus.h **** /* Interrupt Priorities are WORD accessible only under ARMv6M */ + 734:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following MACROS handle generation of the register offset and byte masks */ + 735:Drivers/CMSIS/Include/core_cm0plus.h **** #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) + 736:Drivers/CMSIS/Include/core_cm0plus.h **** #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) + 737:Drivers/CMSIS/Include/core_cm0plus.h **** #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + 738:Drivers/CMSIS/Include/core_cm0plus.h **** + 739:Drivers/CMSIS/Include/core_cm0plus.h **** + 740:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 741:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Enable External Interrupt + 742:Drivers/CMSIS/Include/core_cm0plus.h **** \details Enables a device-specific interrupt in the NVIC interrupt controller. + 743:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative. + 744:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 745:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + 746:Drivers/CMSIS/Include/core_cm0plus.h **** { + 747:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 748:Drivers/CMSIS/Include/core_cm0plus.h **** } + 749:Drivers/CMSIS/Include/core_cm0plus.h **** + 750:Drivers/CMSIS/Include/core_cm0plus.h **** + 751:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 752:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Disable External Interrupt + 753:Drivers/CMSIS/Include/core_cm0plus.h **** \details Disables a device-specific interrupt in the NVIC interrupt controller. + 754:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative. + 755:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 756:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + 757:Drivers/CMSIS/Include/core_cm0plus.h **** { + 758:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 759:Drivers/CMSIS/Include/core_cm0plus.h **** } + 760:Drivers/CMSIS/Include/core_cm0plus.h **** + 761:Drivers/CMSIS/Include/core_cm0plus.h **** + 762:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 763:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Pending Interrupt + 764:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the pending register in the NVIC and returns the pending bit for the specified int + 765:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + 766:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Interrupt status is not pending. + 767:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Interrupt status is pending. + 768:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 769:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + 770:Drivers/CMSIS/Include/core_cm0plus.h **** { + 771:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL + 772:Drivers/CMSIS/Include/core_cm0plus.h **** } + 773:Drivers/CMSIS/Include/core_cm0plus.h **** + 774:Drivers/CMSIS/Include/core_cm0plus.h **** + 775:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 776:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Pending Interrupt + 777:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the pending bit of an external interrupt. + 778:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. Value cannot be negative. + 779:Drivers/CMSIS/Include/core_cm0plus.h **** */ + ARM GAS /tmp/ccd4VzkJ.s page 18 + + + 780:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + 781:Drivers/CMSIS/Include/core_cm0plus.h **** { + 782:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 783:Drivers/CMSIS/Include/core_cm0plus.h **** } + 784:Drivers/CMSIS/Include/core_cm0plus.h **** + 785:Drivers/CMSIS/Include/core_cm0plus.h **** + 786:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 787:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Clear Pending Interrupt + 788:Drivers/CMSIS/Include/core_cm0plus.h **** \details Clears the pending bit of an external interrupt. + 789:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative. + 790:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 791:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 792:Drivers/CMSIS/Include/core_cm0plus.h **** { + 793:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 794:Drivers/CMSIS/Include/core_cm0plus.h **** } + 795:Drivers/CMSIS/Include/core_cm0plus.h **** + 796:Drivers/CMSIS/Include/core_cm0plus.h **** + 797:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 798:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Interrupt Priority + 799:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the priority of an interrupt. + 800:Drivers/CMSIS/Include/core_cm0plus.h **** \note The priority cannot be set for every core interrupt. + 801:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + 802:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] priority Priority to set. + 803:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 804:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + 805:Drivers/CMSIS/Include/core_cm0plus.h **** { + 806:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) < 0) + 42 .loc 2 806 0 + 43 0002 0028 cmp r0, #0 + 44 0004 11DB blt .L4 + 807:Drivers/CMSIS/Include/core_cm0plus.h **** { + 808:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 809:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 810:Drivers/CMSIS/Include/core_cm0plus.h **** } + 811:Drivers/CMSIS/Include/core_cm0plus.h **** else + 812:Drivers/CMSIS/Include/core_cm0plus.h **** { + 813:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 45 .loc 2 813 0 + 46 0006 8408 lsrs r4, r0, #2 + 47 0008 134D ldr r5, .L5 + 48 000a C034 adds r4, r4, #192 + 49 000c A400 lsls r4, r4, #2 + 50 000e 6259 ldr r2, [r4, r5] + 51 .LVL2: + 52 0010 0323 movs r3, #3 + 53 0012 1840 ands r0, r3 + 54 .LVL3: + 55 0014 C000 lsls r0, r0, #3 + 56 0016 FC33 adds r3, r3, #252 + 57 0018 1E00 movs r6, r3 + 58 001a 8640 lsls r6, r6, r0 + 59 001c B243 bics r2, r6 + 814:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 60 .loc 2 814 0 + 61 001e 8901 lsls r1, r1, #6 + 62 .LVL4: + 63 0020 0B40 ands r3, r1 + ARM GAS /tmp/ccd4VzkJ.s page 19 + + + 64 0022 8340 lsls r3, r3, r0 + 813:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 65 .loc 2 813 0 + 66 0024 1343 orrs r3, r2 + 67 0026 6351 str r3, [r4, r5] + 68 .LVL5: + 69 .L1: + 70 .LBE27: + 71 .LBE26: + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SetPriority(IRQn,PreemptPriority); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 72 .loc 1 154 0 + 73 @ sp needed + 74 0028 70BD pop {r4, r5, r6, pc} + 75 .LVL6: + 76 .L4: + 77 .LBB29: + 78 .LBB28: + 808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 79 .loc 2 808 0 + 80 002a C0B2 uxtb r0, r0 + 81 002c 0F22 movs r2, #15 + 82 .LVL7: + 83 002e 0240 ands r2, r0 + 84 0030 083A subs r2, r2, #8 + 85 0032 9208 lsrs r2, r2, #2 + 86 0034 0632 adds r2, r2, #6 + 87 0036 9200 lsls r2, r2, #2 + 88 0038 084B ldr r3, .L5+4 + 89 003a D318 adds r3, r2, r3 + 90 003c 5D68 ldr r5, [r3, #4] + 91 003e 0324 movs r4, #3 + 92 0040 2040 ands r0, r4 + 93 .LVL8: + 94 0042 C000 lsls r0, r0, #3 + 95 0044 FF22 movs r2, #255 + 96 0046 1400 movs r4, r2 + 97 0048 8440 lsls r4, r4, r0 + 98 004a A543 bics r5, r4 + 809:Drivers/CMSIS/Include/core_cm0plus.h **** } + 99 .loc 2 809 0 + 100 004c 8901 lsls r1, r1, #6 + 101 .LVL9: + 102 004e 0A40 ands r2, r1 + 103 0050 8240 lsls r2, r2, r0 + 808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 104 .loc 2 808 0 + 105 0052 2A43 orrs r2, r5 + 106 0054 5A60 str r2, [r3, #4] + 107 0056 E7E7 b .L1 + 108 .L6: + 109 .align 2 + 110 .L5: + 111 0058 00E100E0 .word -536813312 + 112 005c 00ED00E0 .word -536810240 + ARM GAS /tmp/ccd4VzkJ.s page 20 + + + 113 .LBE28: + 114 .LBE29: + 115 .cfi_endproc + 116 .LFE39: + 118 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 119 .align 1 + 120 .global HAL_NVIC_EnableIRQ + 121 .syntax unified + 122 .code 16 + 123 .thumb_func + 124 .fpu softvfp + 126 HAL_NVIC_EnableIRQ: + 127 .LFB40: + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * function should be called before. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn External interrupt number . + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 128 .loc 1 166 0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 133 .LVL10: + 134 .LBB30: + 135 .LBB31: + 747:Drivers/CMSIS/Include/core_cm0plus.h **** } + 136 .loc 2 747 0 + 137 0000 1F23 movs r3, #31 + 138 0002 1840 ands r0, r3 + 139 .LVL11: + 140 0004 1E3B subs r3, r3, #30 + 141 0006 8340 lsls r3, r3, r0 + 142 0008 014A ldr r2, .L8 + 143 000a 1360 str r3, [r2] + 144 .LVL12: + 145 .LBE31: + 146 .LBE30: + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Enable interrupt */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 147 .loc 1 172 0 + 148 @ sp needed + 149 000c 7047 bx lr + 150 .L9: + 151 000e C046 .align 2 + 152 .L8: + ARM GAS /tmp/ccd4VzkJ.s page 21 + + + 153 0010 00E100E0 .word -536813312 + 154 .cfi_endproc + 155 .LFE40: + 157 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 158 .align 1 + 159 .global HAL_NVIC_DisableIRQ + 160 .syntax unified + 161 .code 16 + 162 .thumb_func + 163 .fpu softvfp + 165 HAL_NVIC_DisableIRQ: + 166 .LFB41: + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn External interrupt number . + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 167 .loc 1 182 0 + 168 .cfi_startproc + 169 @ args = 0, pretend = 0, frame = 0 + 170 @ frame_needed = 0, uses_anonymous_args = 0 + 171 @ link register save eliminated. + 172 .LVL13: + 173 .LBB32: + 174 .LBB33: + 758:Drivers/CMSIS/Include/core_cm0plus.h **** } + 175 .loc 2 758 0 + 176 0000 1F23 movs r3, #31 + 177 0002 1840 ands r0, r3 + 178 .LVL14: + 179 0004 1E3B subs r3, r3, #30 + 180 0006 8340 lsls r3, r3, r0 + 181 0008 0149 ldr r1, .L11 + 182 000a 8022 movs r2, #128 + 183 000c 8B50 str r3, [r1, r2] + 184 .LVL15: + 185 .LBE33: + 186 .LBE32: + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Disable interrupt */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 187 .loc 1 188 0 + 188 @ sp needed + 189 000e 7047 bx lr + 190 .L12: + 191 .align 2 + 192 .L11: + 193 0010 00E100E0 .word -536813312 + 194 .cfi_endproc + ARM GAS /tmp/ccd4VzkJ.s page 22 + + + 195 .LFE41: + 197 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 198 .align 1 + 199 .global HAL_NVIC_SystemReset + 200 .syntax unified + 201 .code 16 + 202 .thumb_func + 203 .fpu softvfp + 205 HAL_NVIC_SystemReset: + 206 .LFB42: + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 207 .loc 1 195 0 + 208 .cfi_startproc + 209 @ Volatile: function does not return. + 210 @ args = 0, pretend = 0, frame = 0 + 211 @ frame_needed = 0, uses_anonymous_args = 0 + 212 @ link register save eliminated. + 213 .LBB42: + 214 .LBB43: + 215 .LBB44: + 216 .LBB45: + 217 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARM GAS /tmp/ccd4VzkJ.s page 23 + + + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccd4VzkJ.s page 24 + + + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccd4VzkJ.s page 25 + + + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccd4VzkJ.s page 26 + + + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccd4VzkJ.s page 27 + + + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */ + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) + ARM GAS /tmp/ccd4VzkJ.s page 28 + + + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0); + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + ARM GAS /tmp/ccd4VzkJ.s page 29 + + + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop"); + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void) + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfi"); + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void) + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfe"); + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void) + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("sev"); + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccd4VzkJ.s page 30 + + + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 218 .loc 3 429 0 + 219 .syntax divided + 220 @ 429 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 221 0000 BFF34F8F dsb 0xF + 222 @ 0 "" 2 + 223 .thumb + 224 .syntax unified + 225 .LBE45: + 226 .LBE44: + 815:Drivers/CMSIS/Include/core_cm0plus.h **** } + 816:Drivers/CMSIS/Include/core_cm0plus.h **** } + 817:Drivers/CMSIS/Include/core_cm0plus.h **** + 818:Drivers/CMSIS/Include/core_cm0plus.h **** + 819:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 820:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Interrupt Priority + 821:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the priority of an interrupt. + 822:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify an external (device specific) interrupt, + 823:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify an internal (core) interrupt. + 824:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + 825:Drivers/CMSIS/Include/core_cm0plus.h **** \return Interrupt Priority. + 826:Drivers/CMSIS/Include/core_cm0plus.h **** Value is aligned automatically to the implemented priority bits of the microc + 827:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 828:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + 829:Drivers/CMSIS/Include/core_cm0plus.h **** { + 830:Drivers/CMSIS/Include/core_cm0plus.h **** + 831:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) < 0) + 832:Drivers/CMSIS/Include/core_cm0plus.h **** { + 833:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - + 834:Drivers/CMSIS/Include/core_cm0plus.h **** } + 835:Drivers/CMSIS/Include/core_cm0plus.h **** else + 836:Drivers/CMSIS/Include/core_cm0plus.h **** { + 837:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - + 838:Drivers/CMSIS/Include/core_cm0plus.h **** } + 839:Drivers/CMSIS/Include/core_cm0plus.h **** } + 840:Drivers/CMSIS/Include/core_cm0plus.h **** + 841:Drivers/CMSIS/Include/core_cm0plus.h **** + 842:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 843:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Reset + 844:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initiates a system reset request to reset the MCU. + 845:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 846:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SystemReset(void) + 847:Drivers/CMSIS/Include/core_cm0plus.h **** { + 848:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure all outstanding memor + 849:Drivers/CMSIS/Include/core_cm0plus.h **** buffered write are completed + 850:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 227 .loc 2 850 0 + 228 0004 034B ldr r3, .L15 + 229 0006 044A ldr r2, .L15+4 + 230 0008 DA60 str r2, [r3, #12] + 231 .LBB46: + 232 .LBB47: + 233 .loc 3 429 0 + 234 .syntax divided + 235 @ 429 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 236 000a BFF34F8F dsb 0xF + 237 @ 0 "" 2 + ARM GAS /tmp/ccd4VzkJ.s page 31 + + + 238 .thumb + 239 .syntax unified + 240 .L14: + 241 .LBE47: + 242 .LBE46: + 243 .LBB48: + 244 .LBB49: + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 245 .loc 3 375 0 + 246 .syntax divided + 247 @ 375 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 248 000e C046 nop + 249 @ 0 "" 2 + 250 .thumb + 251 .syntax unified + 252 0010 FDE7 b .L14 + 253 .L16: + 254 0012 C046 .align 2 + 255 .L15: + 256 0014 00ED00E0 .word -536810240 + 257 0018 0400FA05 .word 100270084 + 258 .LBE49: + 259 .LBE48: + 260 .LBE43: + 261 .LBE42: + 262 .cfi_endproc + 263 .LFE42: + 265 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 266 .align 1 + 267 .global HAL_SYSTICK_Config + 268 .syntax unified + 269 .code 16 + 270 .thumb_func + 271 .fpu softvfp + 273 HAL_SYSTICK_Config: + 274 .LFB43: + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* System Reset */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SystemReset(); + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * - 1 Function failed. + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 275 .loc 1 208 0 + 276 .cfi_startproc + 277 @ args = 0, pretend = 0, frame = 0 + 278 @ frame_needed = 0, uses_anonymous_args = 0 + 279 @ link register save eliminated. + 280 .LVL16: + 281 .LBB50: + 282 .LBB51: + ARM GAS /tmp/ccd4VzkJ.s page 32 + + + 851:Drivers/CMSIS/Include/core_cm0plus.h **** SCB_AIRCR_SYSRESETREQ_Msk); + 852:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure completion of memory + 853:Drivers/CMSIS/Include/core_cm0plus.h **** + 854:Drivers/CMSIS/Include/core_cm0plus.h **** for(;;) /* wait until reset */ + 855:Drivers/CMSIS/Include/core_cm0plus.h **** { + 856:Drivers/CMSIS/Include/core_cm0plus.h **** __NOP(); + 857:Drivers/CMSIS/Include/core_cm0plus.h **** } + 858:Drivers/CMSIS/Include/core_cm0plus.h **** } + 859:Drivers/CMSIS/Include/core_cm0plus.h **** + 860:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_NVICFunctions */ + 861:Drivers/CMSIS/Include/core_cm0plus.h **** + 862:Drivers/CMSIS/Include/core_cm0plus.h **** + 863:Drivers/CMSIS/Include/core_cm0plus.h **** + 864:Drivers/CMSIS/Include/core_cm0plus.h **** /* ################################## SysTick function ######################################## + 865:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 866:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface + 867:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + 868:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that configure the System. + 869:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 870:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 871:Drivers/CMSIS/Include/core_cm0plus.h **** + 872:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__Vendor_SysTickConfig == 0U) + 873:Drivers/CMSIS/Include/core_cm0plus.h **** + 874:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 875:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Tick Configuration + 876:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 877:Drivers/CMSIS/Include/core_cm0plus.h **** Counter is in free running mode to generate periodic interrupts. + 878:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] ticks Number of ticks between two interrupts. + 879:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Function succeeded. + 880:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Function failed. + 881:Drivers/CMSIS/Include/core_cm0plus.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the + 882:Drivers/CMSIS/Include/core_cm0plus.h **** function SysTick_Config is not included. In this case, the file device. + 883:Drivers/CMSIS/Include/core_cm0plus.h **** must contain a vendor-specific implementation of this function. + 884:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 885:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + 886:Drivers/CMSIS/Include/core_cm0plus.h **** { + 887:Drivers/CMSIS/Include/core_cm0plus.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 283 .loc 2 887 0 + 284 0000 0138 subs r0, r0, #1 + 285 .LVL17: + 286 0002 0A4B ldr r3, .L20 + 287 0004 9842 cmp r0, r3 + 288 0006 0FD8 bhi .L19 + 888:Drivers/CMSIS/Include/core_cm0plus.h **** { + 889:Drivers/CMSIS/Include/core_cm0plus.h **** return (1UL); /* Reload value impossible */ + 890:Drivers/CMSIS/Include/core_cm0plus.h **** } + 891:Drivers/CMSIS/Include/core_cm0plus.h **** + 892:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 289 .loc 2 892 0 + 290 0008 094A ldr r2, .L20+4 + 291 000a 5060 str r0, [r2, #4] + 292 .LVL18: + 293 .LBB52: + 294 .LBB53: + 808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 295 .loc 2 808 0 + 296 000c 0948 ldr r0, .L20+8 + ARM GAS /tmp/ccd4VzkJ.s page 33 + + + 297 .LVL19: + 298 000e 036A ldr r3, [r0, #32] + 299 0010 1B02 lsls r3, r3, #8 + 300 0012 1B0A lsrs r3, r3, #8 + 301 0014 C021 movs r1, #192 + 302 0016 0906 lsls r1, r1, #24 + 303 0018 0B43 orrs r3, r1 + 304 001a 0362 str r3, [r0, #32] + 305 .LVL20: + 306 .LBE53: + 307 .LBE52: + 893:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 894:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 308 .loc 2 894 0 + 309 001c 0023 movs r3, #0 + 310 001e 9360 str r3, [r2, #8] + 895:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 311 .loc 2 895 0 + 312 0020 0733 adds r3, r3, #7 + 313 0022 1360 str r3, [r2] + 896:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_TICKINT_Msk | + 897:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi + 898:Drivers/CMSIS/Include/core_cm0plus.h **** return (0UL); /* Function successful */ + 314 .loc 2 898 0 + 315 0024 0020 movs r0, #0 + 316 .LVL21: + 317 .L17: + 318 .LBE51: + 319 .LBE50: + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 320 .loc 1 210 0 + 321 @ sp needed + 322 0026 7047 bx lr + 323 .LVL22: + 324 .L19: + 325 .LBB55: + 326 .LBB54: + 889:Drivers/CMSIS/Include/core_cm0plus.h **** } + 327 .loc 2 889 0 + 328 0028 0120 movs r0, #1 + 329 .LVL23: + 330 .LBE54: + 331 .LBE55: + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 332 .loc 1 209 0 + 333 002a FCE7 b .L17 + 334 .L21: + 335 .align 2 + 336 .L20: + 337 002c FFFFFF00 .word 16777215 + 338 0030 10E000E0 .word -536813552 + 339 0034 00ED00E0 .word -536810240 + 340 .cfi_endproc + 341 .LFE43: + 343 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 344 .align 1 + ARM GAS /tmp/ccd4VzkJ.s page 34 + + + 345 .global HAL_NVIC_GetPriority + 346 .syntax unified + 347 .code 16 + 348 .thumb_func + 349 .fpu softvfp + 351 HAL_NVIC_GetPriority: + 352 .LFB44: + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @} + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Cortex control functions + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ============================================================================== + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..] + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (NVIC, SYSTICK) functionalities. + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number. + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 353 .loc 1 240 0 + 354 .cfi_startproc + 355 @ args = 0, pretend = 0, frame = 0 + 356 @ frame_needed = 0, uses_anonymous_args = 0 + 357 @ link register save eliminated. + 358 .LVL24: + 359 .LBB58: + 360 .LBB59: + 831:Drivers/CMSIS/Include/core_cm0plus.h **** { + 361 .loc 2 831 0 + 362 0000 0028 cmp r0, #0 + 363 0002 0CDB blt .L25 + 837:Drivers/CMSIS/Include/core_cm0plus.h **** } + 364 .loc 2 837 0 + 365 0004 8308 lsrs r3, r0, #2 + 366 0006 C033 adds r3, r3, #192 + 367 0008 9B00 lsls r3, r3, #2 + 368 000a 0E4A ldr r2, .L26 + 369 000c 9B58 ldr r3, [r3, r2] + 370 000e 0322 movs r2, #3 + ARM GAS /tmp/ccd4VzkJ.s page 35 + + + 371 0010 1040 ands r0, r2 + 372 .LVL25: + 373 0012 C000 lsls r0, r0, #3 + 374 0014 C340 lsrs r3, r3, r0 + 375 0016 9809 lsrs r0, r3, #6 + 376 0018 0323 movs r3, #3 + 377 001a 1840 ands r0, r3 + 378 .LVL26: + 379 .L22: + 380 .LBE59: + 381 .LBE58: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return NVIC_GetPriority(IRQn); + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 382 .loc 1 243 0 + 383 @ sp needed + 384 001c 7047 bx lr + 385 .LVL27: + 386 .L25: + 387 .LBB61: + 388 .LBB60: + 833:Drivers/CMSIS/Include/core_cm0plus.h **** } + 389 .loc 2 833 0 + 390 001e C0B2 uxtb r0, r0 + 391 0020 0F23 movs r3, #15 + 392 0022 0340 ands r3, r0 + 393 0024 083B subs r3, r3, #8 + 394 0026 9B08 lsrs r3, r3, #2 + 395 0028 0633 adds r3, r3, #6 + 396 002a 9B00 lsls r3, r3, #2 + 397 002c 064A ldr r2, .L26+4 + 398 002e 9446 mov ip, r2 + 399 0030 6344 add r3, r3, ip + 400 0032 5B68 ldr r3, [r3, #4] + 401 0034 0322 movs r2, #3 + 402 0036 1040 ands r0, r2 + 403 .LVL28: + 404 0038 C000 lsls r0, r0, #3 + 405 003a C340 lsrs r3, r3, r0 + 406 003c 9B09 lsrs r3, r3, #6 + 407 003e 0320 movs r0, #3 + 408 0040 1840 ands r0, r3 + 409 0042 EBE7 b .L22 + 410 .L27: + 411 .align 2 + 412 .L26: + 413 0044 00E100E0 .word -536813312 + 414 0048 00ED00E0 .word -536810240 + 415 .LBE60: + 416 .LBE61: + 417 .cfi_endproc + 418 .LFE44: + 420 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 421 .align 1 + 422 .global HAL_NVIC_SetPendingIRQ + 423 .syntax unified + 424 .code 16 + ARM GAS /tmp/ccd4VzkJ.s page 36 + + + 425 .thumb_func + 426 .fpu softvfp + 428 HAL_NVIC_SetPendingIRQ: + 429 .LFB45: + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 430 .loc 1 253 0 + 431 .cfi_startproc + 432 @ args = 0, pretend = 0, frame = 0 + 433 @ frame_needed = 0, uses_anonymous_args = 0 + 434 @ link register save eliminated. + 435 .LVL29: + 436 .LBB62: + 437 .LBB63: + 782:Drivers/CMSIS/Include/core_cm0plus.h **** } + 438 .loc 2 782 0 + 439 0000 1F23 movs r3, #31 + 440 0002 1840 ands r0, r3 + 441 .LVL30: + 442 0004 1E3B subs r3, r3, #30 + 443 0006 8340 lsls r3, r3, r0 + 444 0008 0249 ldr r1, .L29 + 445 000a 8022 movs r2, #128 + 446 000c 5200 lsls r2, r2, #1 + 447 000e 8B50 str r3, [r1, r2] + 448 .LVL31: + 449 .LBE63: + 450 .LBE62: + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set interrupt pending */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 451 .loc 1 256 0 + 452 @ sp needed + 453 0010 7047 bx lr + 454 .L30: + 455 0012 C046 .align 2 + 456 .L29: + 457 0014 00E100E0 .word -536813312 + 458 .cfi_endproc + 459 .LFE45: + 461 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 462 .align 1 + 463 .global HAL_NVIC_GetPendingIRQ + 464 .syntax unified + 465 .code 16 + 466 .thumb_func + 467 .fpu softvfp + 469 HAL_NVIC_GetPendingIRQ: + 470 .LFB46: + ARM GAS /tmp/ccd4VzkJ.s page 37 + + + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number . + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 471 .loc 1 268 0 + 472 .cfi_startproc + 473 @ args = 0, pretend = 0, frame = 0 + 474 @ frame_needed = 0, uses_anonymous_args = 0 + 475 @ link register save eliminated. + 476 .LVL32: + 477 .LBB64: + 478 .LBB65: + 771:Drivers/CMSIS/Include/core_cm0plus.h **** } + 479 .loc 2 771 0 + 480 0000 044A ldr r2, .L32 + 481 0002 8023 movs r3, #128 + 482 0004 5B00 lsls r3, r3, #1 + 483 0006 D358 ldr r3, [r2, r3] + 484 0008 1F22 movs r2, #31 + 485 000a 1040 ands r0, r2 + 486 .LVL33: + 487 000c C340 lsrs r3, r3, r0 + 488 000e 0120 movs r0, #1 + 489 0010 1840 ands r0, r3 + 490 .LVL34: + 491 .LBE65: + 492 .LBE64: + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Return 1 if pending else 0 */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 493 .loc 1 271 0 + 494 @ sp needed + 495 0012 7047 bx lr + 496 .L33: + 497 .align 2 + 498 .L32: + 499 0014 00E100E0 .word -536813312 + 500 .cfi_endproc + 501 .LFE46: + 503 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 504 .align 1 + 505 .global HAL_NVIC_ClearPendingIRQ + 506 .syntax unified + 507 .code 16 + 508 .thumb_func + 509 .fpu softvfp + 511 HAL_NVIC_ClearPendingIRQ: + 512 .LFB47: + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + ARM GAS /tmp/ccd4VzkJ.s page 38 + + + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number . + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 513 .loc 1 281 0 + 514 .cfi_startproc + 515 @ args = 0, pretend = 0, frame = 0 + 516 @ frame_needed = 0, uses_anonymous_args = 0 + 517 @ link register save eliminated. + 518 .LVL35: + 519 .LBB66: + 520 .LBB67: + 793:Drivers/CMSIS/Include/core_cm0plus.h **** } + 521 .loc 2 793 0 + 522 0000 1F23 movs r3, #31 + 523 0002 1840 ands r0, r3 + 524 .LVL36: + 525 0004 1E3B subs r3, r3, #30 + 526 0006 8340 lsls r3, r3, r0 + 527 0008 0249 ldr r1, .L35 + 528 000a C022 movs r2, #192 + 529 000c 5200 lsls r2, r2, #1 + 530 000e 8B50 str r3, [r1, r2] + 531 .LVL37: + 532 .LBE67: + 533 .LBE66: + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Clear pending interrupt */ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 534 .loc 1 284 0 + 535 @ sp needed + 536 0010 7047 bx lr + 537 .L36: + 538 0012 C046 .align 2 + 539 .L35: + 540 0014 00E100E0 .word -536813312 + 541 .cfi_endproc + 542 .LFE47: + 544 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 545 .align 1 + 546 .global HAL_SYSTICK_CLKSourceConfig + 547 .syntax unified + 548 .code 16 + 549 .thumb_func + 550 .fpu softvfp + 552 HAL_SYSTICK_CLKSourceConfig: + 553 .LFB48: + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Configures the SysTick clock source. + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param CLKSource: specifies the SysTick clock source. + ARM GAS /tmp/ccd4VzkJ.s page 39 + + + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be one of the following values: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 554 .loc 1 296 0 + 555 .cfi_startproc + 556 @ args = 0, pretend = 0, frame = 0 + 557 @ frame_needed = 0, uses_anonymous_args = 0 + 558 @ link register save eliminated. + 559 .LVL38: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 560 .loc 1 299 0 + 561 0000 0428 cmp r0, #4 + 562 0002 05D0 beq .L40 + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** else + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 563 .loc 1 305 0 + 564 0004 054A ldr r2, .L41 + 565 0006 1368 ldr r3, [r2] + 566 0008 0421 movs r1, #4 + 567 000a 8B43 bics r3, r1 + 568 000c 1360 str r3, [r2] + 569 .L37: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 570 .loc 1 307 0 + 571 @ sp needed + 572 000e 7047 bx lr + 573 .L40: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 574 .loc 1 301 0 + 575 0010 024A ldr r2, .L41 + 576 0012 1368 ldr r3, [r2] + 577 0014 0421 movs r1, #4 + 578 0016 0B43 orrs r3, r1 + 579 0018 1360 str r3, [r2] + 580 001a F8E7 b .L37 + 581 .L42: + 582 .align 2 + 583 .L41: + 584 001c 10E000E0 .word -536813552 + 585 .cfi_endproc + 586 .LFE48: + 588 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 589 .align 1 + 590 .weak HAL_SYSTICK_Callback + 591 .syntax unified + 592 .code 16 + ARM GAS /tmp/ccd4VzkJ.s page 40 + + + 593 .thumb_func + 594 .fpu softvfp + 596 HAL_SYSTICK_Callback: + 597 .LFB50: + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief SYSTICK callback. + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 598 .loc 1 323 0 + 599 .cfi_startproc + 600 @ args = 0, pretend = 0, frame = 0 + 601 @ frame_needed = 0, uses_anonymous_args = 0 + 602 @ link register save eliminated. + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 603 .loc 1 327 0 + 604 @ sp needed + 605 0000 7047 bx lr + 606 .cfi_endproc + 607 .LFE50: + 609 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 610 .align 1 + 611 .global HAL_SYSTICK_IRQHandler + 612 .syntax unified + 613 .code 16 + 614 .thumb_func + 615 .fpu softvfp + 617 HAL_SYSTICK_IRQHandler: + 618 .LFB49: + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 619 .loc 1 314 0 + 620 .cfi_startproc + 621 @ args = 0, pretend = 0, frame = 0 + 622 @ frame_needed = 0, uses_anonymous_args = 0 + 623 0000 10B5 push {r4, lr} + 624 .LCFI1: + 625 .cfi_def_cfa_offset 8 + 626 .cfi_offset 4, -8 + 627 .cfi_offset 14, -4 + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 628 .loc 1 315 0 + 629 0002 FFF7FEFF bl HAL_SYSTICK_Callback + 630 .LVL39: + ARM GAS /tmp/ccd4VzkJ.s page 41 + + + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 631 .loc 1 316 0 + 632 @ sp needed + 633 0006 10BD pop {r4, pc} + 634 .cfi_endproc + 635 .LFE49: + 637 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 638 .align 1 + 639 .global HAL_MPU_ConfigRegion + 640 .syntax unified + 641 .code 16 + 642 .thumb_func + 643 .fpu softvfp + 645 HAL_MPU_ConfigRegion: + 646 .LFB51: + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #if (__MPU_PRESENT == 1) + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initialize and configure the Region and the memory to be protected. + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * the initialization and configuration information. + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 647 .loc 1 337 0 + 648 .cfi_startproc + 649 @ args = 0, pretend = 0, frame = 0 + 650 @ frame_needed = 0, uses_anonymous_args = 0 + 651 @ link register save eliminated. + 652 .LVL40: + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set the Region number */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 653 .loc 1 343 0 + 654 0000 4279 ldrb r2, [r0, #5] + 655 0002 134B ldr r3, .L49 + 656 0004 9A60 str r2, [r3, #8] + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** if ((MPU_Init->Enable) == MPU_REGION_ENABLE) + 657 .loc 1 345 0 + 658 0006 0379 ldrb r3, [r0, #4] + 659 0008 012B cmp r3, #1 + 660 000a 04D0 beq .L48 + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */ + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + ARM GAS /tmp/ccd4VzkJ.s page 42 + + + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set the base adsress and set the 4 LSB to 0 */ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U; + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Fill the field RASR */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** else + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** { + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RBAR = 0x00U; + 661 .loc 1 371 0 + 662 000c 104B ldr r3, .L49 + 663 000e 0022 movs r2, #0 + 664 0010 DA60 str r2, [r3, #12] + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RASR = 0x00U; + 665 .loc 1 372 0 + 666 0012 1A61 str r2, [r3, #16] + 667 .L45: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 668 .loc 1 374 0 + 669 @ sp needed + 670 0014 7047 bx lr + 671 .L48: + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** + 672 .loc 1 357 0 + 673 0016 0E33 adds r3, r3, #14 + 674 0018 0268 ldr r2, [r0] + 675 001a 9A43 bics r2, r3 + 676 001c 0C49 ldr r1, .L49 + 677 001e CA60 str r2, [r1, #12] + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 678 .loc 1 360 0 + 679 0020 837A ldrb r3, [r0, #10] + 680 0022 1B07 lsls r3, r3, #28 + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 681 .loc 1 361 0 + 682 0024 427A ldrb r2, [r0, #9] + 683 0026 1206 lsls r2, r2, #24 + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 684 .loc 1 360 0 + 685 0028 1343 orrs r3, r2 + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 686 .loc 1 362 0 + 687 002a C27A ldrb r2, [r0, #11] + 688 002c 9204 lsls r2, r2, #18 + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 689 .loc 1 361 0 + 690 002e 1343 orrs r3, r2 + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 691 .loc 1 363 0 + ARM GAS /tmp/ccd4VzkJ.s page 43 + + + 692 0030 027B ldrb r2, [r0, #12] + 693 0032 5204 lsls r2, r2, #17 + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 694 .loc 1 362 0 + 695 0034 1343 orrs r3, r2 + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 696 .loc 1 364 0 + 697 0036 427B ldrb r2, [r0, #13] + 698 0038 1204 lsls r2, r2, #16 + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 699 .loc 1 363 0 + 700 003a 1343 orrs r3, r2 + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 701 .loc 1 365 0 + 702 003c C279 ldrb r2, [r0, #7] + 703 003e 1202 lsls r2, r2, #8 + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 704 .loc 1 364 0 + 705 0040 1343 orrs r3, r2 + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 706 .loc 1 366 0 + 707 0042 8279 ldrb r2, [r0, #6] + 708 0044 5200 lsls r2, r2, #1 + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 709 .loc 1 365 0 + 710 0046 1343 orrs r3, r2 + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** } + 711 .loc 1 367 0 + 712 0048 0279 ldrb r2, [r0, #4] + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 713 .loc 1 366 0 + 714 004a 1343 orrs r3, r2 + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 715 .loc 1 360 0 + 716 004c 0B61 str r3, [r1, #16] + 717 004e E1E7 b .L45 + 718 .L50: + 719 .align 2 + 720 .L49: + 721 0050 90ED00E0 .word -536810096 + 722 .cfi_endproc + 723 .LFE51: + 725 .text + 726 .Letext0: + 727 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 728 .file 5 "/usr/arm-none-eabi/include/machine/_default_types.h" + 729 .file 6 "/usr/arm-none-eabi/include/sys/_stdint.h" + 730 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 731 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 732 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 733 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 734 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + 735 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + ARM GAS /tmp/ccd4VzkJ.s page 44 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_cortex.c + /tmp/ccd4VzkJ.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t + /tmp/ccd4VzkJ.s:23 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority + /tmp/ccd4VzkJ.s:111 .text.HAL_NVIC_SetPriority:0000000000000058 $d + /tmp/ccd4VzkJ.s:119 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t + /tmp/ccd4VzkJ.s:126 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ + /tmp/ccd4VzkJ.s:153 .text.HAL_NVIC_EnableIRQ:0000000000000010 $d + /tmp/ccd4VzkJ.s:158 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t + /tmp/ccd4VzkJ.s:165 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ + /tmp/ccd4VzkJ.s:193 .text.HAL_NVIC_DisableIRQ:0000000000000010 $d + /tmp/ccd4VzkJ.s:198 .text.HAL_NVIC_SystemReset:0000000000000000 $t + /tmp/ccd4VzkJ.s:205 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset + /tmp/ccd4VzkJ.s:256 .text.HAL_NVIC_SystemReset:0000000000000014 $d + /tmp/ccd4VzkJ.s:266 .text.HAL_SYSTICK_Config:0000000000000000 $t + /tmp/ccd4VzkJ.s:273 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config + /tmp/ccd4VzkJ.s:337 .text.HAL_SYSTICK_Config:000000000000002c $d + /tmp/ccd4VzkJ.s:344 .text.HAL_NVIC_GetPriority:0000000000000000 $t + /tmp/ccd4VzkJ.s:351 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority + /tmp/ccd4VzkJ.s:413 .text.HAL_NVIC_GetPriority:0000000000000044 $d + /tmp/ccd4VzkJ.s:421 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t + /tmp/ccd4VzkJ.s:428 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ + /tmp/ccd4VzkJ.s:457 .text.HAL_NVIC_SetPendingIRQ:0000000000000014 $d + /tmp/ccd4VzkJ.s:462 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t + /tmp/ccd4VzkJ.s:469 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ + /tmp/ccd4VzkJ.s:499 .text.HAL_NVIC_GetPendingIRQ:0000000000000014 $d + /tmp/ccd4VzkJ.s:504 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t + /tmp/ccd4VzkJ.s:511 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccd4VzkJ.s:540 .text.HAL_NVIC_ClearPendingIRQ:0000000000000014 $d + /tmp/ccd4VzkJ.s:545 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t + /tmp/ccd4VzkJ.s:552 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccd4VzkJ.s:584 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d + /tmp/ccd4VzkJ.s:589 .text.HAL_SYSTICK_Callback:0000000000000000 $t + /tmp/ccd4VzkJ.s:596 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback + /tmp/ccd4VzkJ.s:610 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t + /tmp/ccd4VzkJ.s:617 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler + /tmp/ccd4VzkJ.s:638 .text.HAL_MPU_ConfigRegion:0000000000000000 $t + /tmp/ccd4VzkJ.s:645 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion + /tmp/ccd4VzkJ.s:721 .text.HAL_MPU_ConfigRegion:0000000000000050 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_crc.d b/build/stm32l0xx_hal_crc.d new file mode 100644 index 0000000..02eaf8d --- /dev/null +++ b/build/stm32l0xx_hal_crc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_crc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_crc.lst b/build/stm32l0xx_hal_crc.lst new file mode 100644 index 0000000..68170e3 --- /dev/null +++ b/build/stm32l0xx_hal_crc.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccv3vQQT.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_crc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccv3vQQT.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_crc.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_crc_ex.d b/build/stm32l0xx_hal_crc_ex.d new file mode 100644 index 0000000..01d7bfb --- /dev/null +++ b/build/stm32l0xx_hal_crc_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_crc_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_crc_ex.lst b/build/stm32l0xx_hal_crc_ex.lst new file mode 100644 index 0000000..4a9686a --- /dev/null +++ b/build/stm32l0xx_hal_crc_ex.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccbyCQhg.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_crc_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccbyCQhg.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_crc_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_cryp.d b/build/stm32l0xx_hal_cryp.d new file mode 100644 index 0000000..aa4e516 --- /dev/null +++ b/build/stm32l0xx_hal_cryp.d @@ -0,0 +1,2 @@ +build/stm32l0xx_hal_cryp.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c diff --git a/build/stm32l0xx_hal_cryp.lst b/build/stm32l0xx_hal_cryp.lst new file mode 100644 index 0000000..e663b21 --- /dev/null +++ b/build/stm32l0xx_hal_cryp.lst @@ -0,0 +1,25 @@ +ARM GAS /tmp/ccrP1Afq.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_cryp.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + ARM GAS /tmp/ccrP1Afq.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_cryp.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_cryp_ex.d b/build/stm32l0xx_hal_cryp_ex.d new file mode 100644 index 0000000..ec2f911 --- /dev/null +++ b/build/stm32l0xx_hal_cryp_ex.d @@ -0,0 +1,2 @@ +build/stm32l0xx_hal_cryp_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c diff --git a/build/stm32l0xx_hal_cryp_ex.lst b/build/stm32l0xx_hal_cryp_ex.lst new file mode 100644 index 0000000..7af9196 --- /dev/null +++ b/build/stm32l0xx_hal_cryp_ex.lst @@ -0,0 +1,25 @@ +ARM GAS /tmp/ccnSeeEM.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_cryp_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + ARM GAS /tmp/ccnSeeEM.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_cryp_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_dac.d b/build/stm32l0xx_hal_dac.d new file mode 100644 index 0000000..3490d7b --- /dev/null +++ b/build/stm32l0xx_hal_dac.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_dac.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_dac.lst b/build/stm32l0xx_hal_dac.lst new file mode 100644 index 0000000..533f19d --- /dev/null +++ b/build/stm32l0xx_hal_dac.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccDfPbDO.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_dac.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccDfPbDO.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_dac.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_dac_ex.d b/build/stm32l0xx_hal_dac_ex.d new file mode 100644 index 0000000..11ff5c3 --- /dev/null +++ b/build/stm32l0xx_hal_dac_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_dac_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_dac_ex.lst b/build/stm32l0xx_hal_dac_ex.lst new file mode 100644 index 0000000..86cf297 --- /dev/null +++ b/build/stm32l0xx_hal_dac_ex.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cccMEG5F.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_dac_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cccMEG5F.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_dac_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_dma.d b/build/stm32l0xx_hal_dma.d new file mode 100644 index 0000000..e692fe3 --- /dev/null +++ b/build/stm32l0xx_hal_dma.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_dma.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_dma.lst b/build/stm32l0xx_hal_dma.lst new file mode 100644 index 0000000..521add4 --- /dev/null +++ b/build/stm32l0xx_hal_dma.lst @@ -0,0 +1,3299 @@ +ARM GAS /tmp/ccJCJaQH.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_dma.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_DMA_Init,"ax",%progbits + 16 .align 1 + 17 .global HAL_DMA_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_DMA_Init: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @file stm32l0xx_hal_dma.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief DMA HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * This file provides firmware functions to manage the following + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * functionalities of the Direct Memory Access (DMA) peripheral: + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + Initialization/de-initialization functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + I/O operation functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + Peripheral State functions + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @verbatim + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ============================================================================== + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ##### How to use this driver ##### + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ============================================================================== + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (#) Enable and configure the peripheral to be connected to the DMA Channel + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (except for internal SRAM / FLASH memories: no initialization is + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** necessary). + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (#) For a given Channel, program the required configuration through the following parameters: + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** Channel request, Transfer Direction, Source and Destination data formats, + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** Circular, Normal or peripheral flow control mode, Channel Priority level, + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** Source and Destination Increment mode using HAL_DMA_Init() function. + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** *** Polling mode IO operation *** + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ================================= + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** address and destination address and the Length of data to be transferred + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + ARM GAS /tmp/ccJCJaQH.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** case a fixed Timeout can be configured by User depending from his application. + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** *** Interrupt mode IO operation *** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =================================== + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** Source address and destination address and the Length of data to be transferred. In t + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** case the DMA interrupt is configured + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** add his own function by customization of function pointer XferCpltCallback and + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** XferErrorCallback (i.e a member of DMA handle structure). + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of er + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** detection. + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (#) Use HAL_DMA_Abort() function to abort the current transfer + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @endverbatim + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ****************************************************************************** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @attention + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * Redistribution and use in source and binary forms, with or without modification, + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * are permitted provided that the following conditions are met: + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * 1. Redistributions of source code must retain the above copyright notice, + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * this list of conditions and the following disclaimer. + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * this list of conditions and the following disclaimer in the documentation + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * and/or other materials provided with the distribution. + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * may be used to endorse or promote products derived from this software + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * without specific prior written permission. + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ****************************************************************************** + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #include "stm32l0xx_hal.h" + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup STM32L0xx_HAL_Driver + ARM GAS /tmp/ccJCJaQH.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA DMA + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief DMA HAL module driver + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Private typedef -----------------------------------------------------------*/ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Private + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @} + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions DMA Exported Functions + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group1 + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Initialization/de-initialization functions + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @verbatim + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ##### Initialization and de-initialization functions ##### + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] This section provides functions allowing to: + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Initialize and configure the DMA + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) De-Initialize the DMA + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @endverbatim + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Initializes the DMA according to the specified + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * parameters in the DMA_InitTypeDef and create the associated handle. + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 26 .loc 1 140 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 10B5 push {r4, lr} + 32 .LCFI0: + ARM GAS /tmp/ccJCJaQH.s page 4 + + + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 4, -8 + 35 .cfi_offset 14, -4 + 36 .LVL1: + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t tmp = 0U; + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the DMA peripheral state */ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma == NULL) + 37 .loc 1 144 0 + 38 0002 0028 cmp r0, #0 + 39 0004 00D1 bne .LCB12 + 40 0006 82E0 b .L11 @long jump + 41 .LCB12: + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_ERROR; + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the parameters */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma->State == HAL_DMA_STATE_RESET) + 42 .loc 1 160 0 + 43 0008 2523 movs r3, #37 + 44 000a C35C ldrb r3, [r0, r3] + 45 000c 002B cmp r3, #0 + 46 000e 02D1 bne .L3 + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Allocate lock resource and initialize it */ + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Lock = HAL_UNLOCKED; + 47 .loc 1 163 0 + 48 0010 2433 adds r3, r3, #36 + 49 0012 0022 movs r2, #0 + 50 0014 C254 strb r2, [r0, r3] + 51 .L3: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change DMA peripheral state */ + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 52 .loc 1 167 0 + 53 0016 2523 movs r3, #37 + 54 0018 0222 movs r2, #2 + 55 001a C254 strb r2, [r0, r3] + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Get the CR register value */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** tmp = hdma->Instance->CCR; + 56 .loc 1 170 0 + 57 001c 0168 ldr r1, [r0] + 58 001e 0B68 ldr r3, [r1] + 59 .LVL2: + ARM GAS /tmp/ccJCJaQH.s page 5 + + + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 60 .loc 1 173 0 + 61 0020 3C4A ldr r2, .L18 + 62 0022 1A40 ands r2, r3 + 63 .LVL3: + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA_CCR_DIR)); + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Prepare the DMA Channel configuration */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** tmp |= hdma->Init.Direction | + 64 .loc 1 178 0 + 65 0024 8368 ldr r3, [r0, #8] + 66 0026 C468 ldr r4, [r0, #12] + 67 0028 2343 orrs r3, r4 + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 68 .loc 1 179 0 + 69 002a 0469 ldr r4, [r0, #16] + 70 002c 2343 orrs r3, r4 + 71 002e 4469 ldr r4, [r0, #20] + 72 0030 2343 orrs r3, r4 + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 73 .loc 1 180 0 + 74 0032 8469 ldr r4, [r0, #24] + 75 0034 2343 orrs r3, r4 + 76 0036 C469 ldr r4, [r0, #28] + 77 0038 2343 orrs r3, r4 + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 78 .loc 1 181 0 + 79 003a 046A ldr r4, [r0, #32] + 80 003c 2343 orrs r3, r4 + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 81 .loc 1 178 0 + 82 003e 1343 orrs r3, r2 + 83 .LVL4: + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Write to DMA Channel CR register */ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CCR = tmp; + 84 .loc 1 184 0 + 85 0040 0B60 str r3, [r1] + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Write to DMA channel selection register */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if (hdma->Instance == DMA1_Channel1) + 86 .loc 1 187 0 + 87 0042 0368 ldr r3, [r0] + 88 .LVL5: + 89 0044 344A ldr r2, .L18+4 + 90 0046 9342 cmp r3, r2 + 91 0048 1CD0 beq .L12 + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel1*/ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel1 */ + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= hdma->Init.Request; + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + ARM GAS /tmp/ccJCJaQH.s page 6 + + + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel2) + 92 .loc 1 195 0 + 93 004a 344A ldr r2, .L18+8 + 94 004c 9342 cmp r3, r2 + 95 004e 27D0 beq .L13 + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel2*/ + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel2 */ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4U); + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel3) + 96 .loc 1 203 0 + 97 0050 334A ldr r2, .L18+12 + 98 0052 9342 cmp r3, r2 + 99 0054 2FD0 beq .L14 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel3*/ + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel3 */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8U); + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel4) + 100 .loc 1 211 0 + 101 0056 334A ldr r2, .L18+16 + 102 0058 9342 cmp r3, r2 + 103 005a 37D0 beq .L15 + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel4*/ + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel4 */ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12U); + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel5) + 104 .loc 1 219 0 + 105 005c 324A ldr r2, .L18+20 + 106 005e 9342 cmp r3, r2 + 107 0060 3FD0 beq .L16 + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel5*/ + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel5 */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16U); + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #if !defined (STM32L011xx) && !defined (STM32L021xx) + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel6) + 108 .loc 1 228 0 + 109 0062 324A ldr r2, .L18+24 + 110 0064 9342 cmp r3, r2 + 111 0066 47D0 beq .L17 + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel6*/ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; + ARM GAS /tmp/ccJCJaQH.s page 7 + + + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel6 */ + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20U); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel7) + 112 .loc 1 236 0 + 113 0068 314A ldr r2, .L18+28 + 114 006a 9342 cmp r3, r2 + 115 006c 13D1 bne .L5 + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset request selection for DMA1 Channel7*/ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; + 116 .loc 1 239 0 + 117 006e 314B ldr r3, .L18+32 + 118 0070 1A68 ldr r2, [r3] + 119 0072 3149 ldr r1, .L18+36 + 120 .LVL6: + 121 0074 0A40 ands r2, r1 + 122 0076 1A60 str r2, [r3] + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure request selection for DMA1 Channel7 */ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24U); + 123 .loc 1 242 0 + 124 0078 1A68 ldr r2, [r3] + 125 007a 4168 ldr r1, [r0, #4] + 126 007c 0906 lsls r1, r1, #24 + 127 007e 0A43 orrs r2, r1 + 128 0080 1A60 str r2, [r3] + 129 0082 08E0 b .L5 + 130 .LVL7: + 131 .L12: + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 132 .loc 1 190 0 + 133 0084 2B4B ldr r3, .L18+32 + 134 0086 1A68 ldr r2, [r3] + 135 0088 0F21 movs r1, #15 + 136 .LVL8: + 137 008a 8A43 bics r2, r1 + 138 008c 1A60 str r2, [r3] + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 139 .loc 1 193 0 + 140 008e 1A68 ldr r2, [r3] + 141 0090 4168 ldr r1, [r0, #4] + 142 0092 0A43 orrs r2, r1 + 143 0094 1A60 str r2, [r3] + 144 .L5: + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #endif + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Initialize the DMA state*/ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 145 .loc 1 246 0 + 146 0096 2523 movs r3, #37 + 147 0098 0122 movs r2, #1 + 148 009a C254 strb r2, [r0, r3] + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 149 .loc 1 248 0 + ARM GAS /tmp/ccJCJaQH.s page 8 + + + 150 009c 0020 movs r0, #0 + 151 .LVL9: + 152 .L2: + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 153 .loc 1 249 0 + 154 @ sp needed + 155 009e 10BD pop {r4, pc} + 156 .LVL10: + 157 .L13: + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 158 .loc 1 198 0 + 159 00a0 244B ldr r3, .L18+32 + 160 00a2 1A68 ldr r2, [r3] + 161 00a4 F021 movs r1, #240 + 162 .LVL11: + 163 00a6 8A43 bics r2, r1 + 164 00a8 1A60 str r2, [r3] + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 165 .loc 1 201 0 + 166 00aa 1A68 ldr r2, [r3] + 167 00ac 4168 ldr r1, [r0, #4] + 168 00ae 0901 lsls r1, r1, #4 + 169 00b0 0A43 orrs r2, r1 + 170 00b2 1A60 str r2, [r3] + 171 00b4 EFE7 b .L5 + 172 .LVL12: + 173 .L14: + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 174 .loc 1 206 0 + 175 00b6 1F4B ldr r3, .L18+32 + 176 00b8 1A68 ldr r2, [r3] + 177 00ba 2049 ldr r1, .L18+40 + 178 .LVL13: + 179 00bc 0A40 ands r2, r1 + 180 00be 1A60 str r2, [r3] + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 181 .loc 1 209 0 + 182 00c0 1A68 ldr r2, [r3] + 183 00c2 4168 ldr r1, [r0, #4] + 184 00c4 0902 lsls r1, r1, #8 + 185 00c6 0A43 orrs r2, r1 + 186 00c8 1A60 str r2, [r3] + 187 00ca E4E7 b .L5 + 188 .LVL14: + 189 .L15: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 190 .loc 1 214 0 + 191 00cc 194B ldr r3, .L18+32 + 192 00ce 1A68 ldr r2, [r3] + 193 00d0 1B49 ldr r1, .L18+44 + 194 .LVL15: + 195 00d2 0A40 ands r2, r1 + 196 00d4 1A60 str r2, [r3] + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 197 .loc 1 217 0 + 198 00d6 1A68 ldr r2, [r3] + 199 00d8 4168 ldr r1, [r0, #4] + ARM GAS /tmp/ccJCJaQH.s page 9 + + + 200 00da 0903 lsls r1, r1, #12 + 201 00dc 0A43 orrs r2, r1 + 202 00de 1A60 str r2, [r3] + 203 00e0 D9E7 b .L5 + 204 .LVL16: + 205 .L16: + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 206 .loc 1 222 0 + 207 00e2 144B ldr r3, .L18+32 + 208 00e4 1A68 ldr r2, [r3] + 209 00e6 1749 ldr r1, .L18+48 + 210 .LVL17: + 211 00e8 0A40 ands r2, r1 + 212 00ea 1A60 str r2, [r3] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 213 .loc 1 225 0 + 214 00ec 1A68 ldr r2, [r3] + 215 00ee 4168 ldr r1, [r0, #4] + 216 00f0 0904 lsls r1, r1, #16 + 217 00f2 0A43 orrs r2, r1 + 218 00f4 1A60 str r2, [r3] + 219 00f6 CEE7 b .L5 + 220 .LVL18: + 221 .L17: + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 222 .loc 1 231 0 + 223 00f8 0E4B ldr r3, .L18+32 + 224 00fa 1A68 ldr r2, [r3] + 225 00fc 1249 ldr r1, .L18+52 + 226 .LVL19: + 227 00fe 0A40 ands r2, r1 + 228 0100 1A60 str r2, [r3] + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 229 .loc 1 234 0 + 230 0102 1A68 ldr r2, [r3] + 231 0104 4168 ldr r1, [r0, #4] + 232 0106 0905 lsls r1, r1, #20 + 233 0108 0A43 orrs r2, r1 + 234 010a 1A60 str r2, [r3] + 235 010c C3E7 b .L5 + 236 .LVL20: + 237 .L11: + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 238 .loc 1 146 0 + 239 010e 0120 movs r0, #1 + 240 .LVL21: + 241 0110 C5E7 b .L2 + 242 .L19: + 243 0112 C046 .align 2 + 244 .L18: + 245 0114 0FC0FFFF .word -16369 + 246 0118 08000240 .word 1073872904 + 247 011c 1C000240 .word 1073872924 + 248 0120 30000240 .word 1073872944 + 249 0124 44000240 .word 1073872964 + 250 0128 58000240 .word 1073872984 + 251 012c 6C000240 .word 1073873004 + ARM GAS /tmp/ccJCJaQH.s page 10 + + + 252 0130 80000240 .word 1073873024 + 253 0134 A8000240 .word 1073873064 + 254 0138 FFFFFFF0 .word -251658241 + 255 013c FFF0FFFF .word -3841 + 256 0140 FF0FFFFF .word -61441 + 257 0144 FFFFF0FF .word -983041 + 258 0148 FFFF0FFF .word -15728641 + 259 .cfi_endproc + 260 .LFE39: + 262 .section .text.HAL_DMA_DeInit,"ax",%progbits + 263 .align 1 + 264 .global HAL_DMA_DeInit + 265 .syntax unified + 266 .code 16 + 267 .thumb_func + 268 .fpu softvfp + 270 HAL_DMA_DeInit: + 271 .LFB40: + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief DeInitializes the DMA peripheral + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 272 .loc 1 258 0 + 273 .cfi_startproc + 274 @ args = 0, pretend = 0, frame = 0 + 275 @ frame_needed = 0, uses_anonymous_args = 0 + 276 .LVL22: + 277 0000 00B5 push {lr} + 278 .LCFI1: + 279 .cfi_def_cfa_offset 4 + 280 .cfi_offset 14, -4 + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the DMA peripheral state */ + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma == NULL) + 281 .loc 1 260 0 + 282 0002 0028 cmp r0, #0 + 283 0004 00D1 bne .LCB261 + 284 0006 F5E0 b .L33 @long jump + 285 .LCB261: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_ERROR; + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the DMA peripheral state */ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma->State == HAL_DMA_STATE_BUSY) + 286 .loc 1 266 0 + 287 0008 2523 movs r3, #37 + 288 000a C35C ldrb r3, [r0, r3] + 289 000c 022B cmp r3, #2 + 290 000e 00D1 bne .LCB266 + 291 0010 F2E0 b .L34 @long jump + 292 .LCB266: + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + ARM GAS /tmp/ccJCJaQH.s page 11 + + + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_ERROR; + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the selected DMA Channelx */ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 293 .loc 1 272 0 + 294 0012 0268 ldr r2, [r0] + 295 0014 1368 ldr r3, [r2] + 296 0016 0121 movs r1, #1 + 297 0018 8B43 bics r3, r1 + 298 001a 1360 str r3, [r2] + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Reset DMA Channel control register */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CCR = 0U; + 299 .loc 1 275 0 + 300 001c 0268 ldr r2, [r0] + 301 001e 0023 movs r3, #0 + 302 0020 1360 str r3, [r2] + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Reset DMA Channel Number of Data to Transfer register */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CNDTR = 0U; + 303 .loc 1 278 0 + 304 0022 0268 ldr r2, [r0] + 305 0024 5360 str r3, [r2, #4] + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Reset DMA Channel peripheral address register */ + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CPAR = 0U; + 306 .loc 1 281 0 + 307 0026 0268 ldr r2, [r0] + 308 0028 9360 str r3, [r2, #8] + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Reset DMA Channel memory address register */ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CMAR = 0U; + 309 .loc 1 284 0 + 310 002a 0268 ldr r2, [r0] + 311 002c D360 str r3, [r2, #12] + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear all flags */ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + 312 .loc 1 287 0 + 313 002e 0368 ldr r3, [r0] + 314 0030 724A ldr r2, .L69 + 315 0032 9342 cmp r3, r2 + 316 0034 14D0 beq .L35 + 317 .loc 1 287 0 is_stmt 0 discriminator 1 + 318 0036 724A ldr r2, .L69+4 + 319 0038 9342 cmp r3, r2 + 320 003a 2AD0 beq .L36 + 321 .loc 1 287 0 discriminator 3 + 322 003c 714A ldr r2, .L69+8 + 323 003e 9342 cmp r3, r2 + 324 0040 29D0 beq .L37 + 325 .loc 1 287 0 discriminator 5 + 326 0042 714A ldr r2, .L69+12 + 327 0044 9342 cmp r3, r2 + 328 0046 29D0 beq .L38 + 329 .loc 1 287 0 discriminator 7 + ARM GAS /tmp/ccJCJaQH.s page 12 + + + 330 0048 704A ldr r2, .L69+16 + 331 004a 9342 cmp r3, r2 + 332 004c 29D0 beq .L39 + 333 .loc 1 287 0 discriminator 9 + 334 004e 704A ldr r2, .L69+20 + 335 0050 9342 cmp r3, r2 + 336 0052 02D0 beq .L59 + 337 .loc 1 287 0 + 338 0054 8022 movs r2, #128 + 339 0056 5204 lsls r2, r2, #17 + 340 0058 03E0 b .L22 + 341 .L59: + 342 005a 8022 movs r2, #128 + 343 005c 5203 lsls r2, r2, #13 + 344 005e 00E0 b .L22 + 345 .L35: + 346 0060 0122 movs r2, #1 + 347 .L22: + 348 .loc 1 287 0 discriminator 24 + 349 0062 6C4B ldr r3, .L69+24 + 350 0064 5A60 str r2, [r3, #4] + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 351 .loc 1 288 0 is_stmt 1 discriminator 24 + 352 0066 0368 ldr r3, [r0] + 353 0068 644A ldr r2, .L69 + 354 006a 9342 cmp r3, r2 + 355 006c 1FD0 beq .L41 + 356 .loc 1 288 0 is_stmt 0 discriminator 1 + 357 006e 644A ldr r2, .L69+4 + 358 0070 9342 cmp r3, r2 + 359 0072 35D0 beq .L42 + 360 .loc 1 288 0 discriminator 3 + 361 0074 634A ldr r2, .L69+8 + 362 0076 9342 cmp r3, r2 + 363 0078 34D0 beq .L43 + 364 .loc 1 288 0 discriminator 5 + 365 007a 634A ldr r2, .L69+12 + 366 007c 9342 cmp r3, r2 + 367 007e 34D0 beq .L44 + 368 .loc 1 288 0 discriminator 7 + 369 0080 624A ldr r2, .L69+16 + 370 0082 9342 cmp r3, r2 + 371 0084 34D0 beq .L45 + 372 .loc 1 288 0 discriminator 9 + 373 0086 624A ldr r2, .L69+20 + 374 0088 9342 cmp r3, r2 + 375 008a 0DD0 beq .L60 + 376 .loc 1 288 0 + 377 008c 8022 movs r2, #128 + 378 008e 9204 lsls r2, r2, #18 + 379 0090 0EE0 b .L23 + 380 .L36: + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 381 .loc 1 287 0 is_stmt 1 + 382 0092 1022 movs r2, #16 + 383 0094 E5E7 b .L22 + 384 .L37: + ARM GAS /tmp/ccJCJaQH.s page 13 + + + 385 0096 8022 movs r2, #128 + 386 0098 5200 lsls r2, r2, #1 + 387 009a E2E7 b .L22 + 388 .L38: + 389 009c 8022 movs r2, #128 + 390 009e 5201 lsls r2, r2, #5 + 391 00a0 DFE7 b .L22 + 392 .L39: + 393 00a2 8022 movs r2, #128 + 394 00a4 5202 lsls r2, r2, #9 + 395 00a6 DCE7 b .L22 + 396 .L60: + 397 .loc 1 288 0 + 398 00a8 8022 movs r2, #128 + 399 00aa 9203 lsls r2, r2, #14 + 400 00ac 00E0 b .L23 + 401 .L41: + 402 00ae 0222 movs r2, #2 + 403 .L23: + 404 .loc 1 288 0 is_stmt 0 discriminator 24 + 405 00b0 584B ldr r3, .L69+24 + 406 00b2 5A60 str r2, [r3, #4] + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 407 .loc 1 289 0 is_stmt 1 discriminator 24 + 408 00b4 0368 ldr r3, [r0] + 409 00b6 514A ldr r2, .L69 + 410 00b8 9342 cmp r3, r2 + 411 00ba 1FD0 beq .L47 + 412 .loc 1 289 0 is_stmt 0 discriminator 1 + 413 00bc 504A ldr r2, .L69+4 + 414 00be 9342 cmp r3, r2 + 415 00c0 35D0 beq .L48 + 416 .loc 1 289 0 discriminator 3 + 417 00c2 504A ldr r2, .L69+8 + 418 00c4 9342 cmp r3, r2 + 419 00c6 34D0 beq .L49 + 420 .loc 1 289 0 discriminator 5 + 421 00c8 4F4A ldr r2, .L69+12 + 422 00ca 9342 cmp r3, r2 + 423 00cc 34D0 beq .L50 + 424 .loc 1 289 0 discriminator 7 + 425 00ce 4F4A ldr r2, .L69+16 + 426 00d0 9342 cmp r3, r2 + 427 00d2 34D0 beq .L51 + 428 .loc 1 289 0 discriminator 9 + 429 00d4 4E4A ldr r2, .L69+20 + 430 00d6 9342 cmp r3, r2 + 431 00d8 0DD0 beq .L61 + 432 .loc 1 289 0 + 433 00da 8022 movs r2, #128 + 434 00dc 1205 lsls r2, r2, #20 + 435 00de 0EE0 b .L24 + 436 .L42: + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 437 .loc 1 288 0 is_stmt 1 + 438 00e0 2022 movs r2, #32 + 439 00e2 E5E7 b .L23 + ARM GAS /tmp/ccJCJaQH.s page 14 + + + 440 .L43: + 441 00e4 8022 movs r2, #128 + 442 00e6 9200 lsls r2, r2, #2 + 443 00e8 E2E7 b .L23 + 444 .L44: + 445 00ea 8022 movs r2, #128 + 446 00ec 9201 lsls r2, r2, #6 + 447 00ee DFE7 b .L23 + 448 .L45: + 449 00f0 8022 movs r2, #128 + 450 00f2 9202 lsls r2, r2, #10 + 451 00f4 DCE7 b .L23 + 452 .L61: + 453 .loc 1 289 0 + 454 00f6 8022 movs r2, #128 + 455 00f8 1204 lsls r2, r2, #16 + 456 00fa 00E0 b .L24 + 457 .L47: + 458 00fc 0822 movs r2, #8 + 459 .L24: + 460 .loc 1 289 0 is_stmt 0 discriminator 24 + 461 00fe 454B ldr r3, .L69+24 + 462 0100 5A60 str r2, [r3, #4] + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 463 .loc 1 290 0 is_stmt 1 discriminator 24 + 464 0102 0368 ldr r3, [r0] + 465 0104 3D4A ldr r2, .L69 + 466 0106 9342 cmp r3, r2 + 467 0108 1FD0 beq .L53 + 468 .loc 1 290 0 is_stmt 0 discriminator 1 + 469 010a 3D4A ldr r2, .L69+4 + 470 010c 9342 cmp r3, r2 + 471 010e 3BD0 beq .L54 + 472 .loc 1 290 0 discriminator 3 + 473 0110 3C4A ldr r2, .L69+8 + 474 0112 9342 cmp r3, r2 + 475 0114 3AD0 beq .L55 + 476 .loc 1 290 0 discriminator 5 + 477 0116 3C4A ldr r2, .L69+12 + 478 0118 9342 cmp r3, r2 + 479 011a 3AD0 beq .L56 + 480 .loc 1 290 0 discriminator 7 + 481 011c 3B4A ldr r2, .L69+16 + 482 011e 9342 cmp r3, r2 + 483 0120 3AD0 beq .L57 + 484 .loc 1 290 0 discriminator 9 + 485 0122 3B4A ldr r2, .L69+20 + 486 0124 9342 cmp r3, r2 + 487 0126 0DD0 beq .L62 + 488 .loc 1 290 0 + 489 0128 8022 movs r2, #128 + 490 012a D204 lsls r2, r2, #19 + 491 012c 0EE0 b .L25 + 492 .L48: + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 493 .loc 1 289 0 is_stmt 1 + 494 012e 8022 movs r2, #128 + ARM GAS /tmp/ccJCJaQH.s page 15 + + + 495 0130 E5E7 b .L24 + 496 .L49: + 497 0132 8022 movs r2, #128 + 498 0134 1201 lsls r2, r2, #4 + 499 0136 E2E7 b .L24 + 500 .L50: + 501 0138 8022 movs r2, #128 + 502 013a 1202 lsls r2, r2, #8 + 503 013c DFE7 b .L24 + 504 .L51: + 505 013e 8022 movs r2, #128 + 506 0140 1203 lsls r2, r2, #12 + 507 0142 DCE7 b .L24 + 508 .L62: + 509 .loc 1 290 0 + 510 0144 8022 movs r2, #128 + 511 0146 D203 lsls r2, r2, #15 + 512 0148 00E0 b .L25 + 513 .L53: + 514 014a 0422 movs r2, #4 + 515 .L25: + 516 .loc 1 290 0 is_stmt 0 discriminator 24 + 517 014c 314B ldr r3, .L69+24 + 518 014e 5A60 str r2, [r3, #4] + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Reset DMA channel selection register */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if (hdma->Instance == DMA1_Channel1) + 519 .loc 1 293 0 is_stmt 1 discriminator 24 + 520 0150 0368 ldr r3, [r0] + 521 0152 2A4A ldr r2, .L69 + 522 0154 9342 cmp r3, r2 + 523 0156 22D0 beq .L63 + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel2) + 524 .loc 1 298 0 + 525 0158 294A ldr r2, .L69+4 + 526 015a 9342 cmp r3, r2 + 527 015c 2CD0 beq .L64 + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel3) + 528 .loc 1 303 0 + 529 015e 294A ldr r2, .L69+8 + 530 0160 9342 cmp r3, r2 + 531 0162 2FD0 beq .L65 + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel4) + 532 .loc 1 308 0 + 533 0164 284A ldr r2, .L69+12 + ARM GAS /tmp/ccJCJaQH.s page 16 + + + 534 0166 9342 cmp r3, r2 + 535 0168 32D0 beq .L66 + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel5) + 536 .loc 1 313 0 + 537 016a 284A ldr r2, .L69+16 + 538 016c 9342 cmp r3, r2 + 539 016e 35D0 beq .L67 + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #if !defined (STM32L011xx) && !defined (STM32L021xx) + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel6) + 540 .loc 1 319 0 + 541 0170 274A ldr r2, .L69+20 + 542 0172 9342 cmp r3, r2 + 543 0174 38D0 beq .L68 + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else if (hdma->Instance == DMA1_Channel7) + 544 .loc 1 324 0 + 545 0176 284A ldr r2, .L69+28 + 546 0178 9342 cmp r3, r2 + 547 017a 15D1 bne .L27 + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /*Reset DMA request*/ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; + 548 .loc 1 327 0 + 549 017c 274A ldr r2, .L69+32 + 550 017e 1368 ldr r3, [r2] + 551 0180 2749 ldr r1, .L69+36 + 552 0182 0B40 ands r3, r1 + 553 0184 1360 str r3, [r2] + 554 0186 0FE0 b .L27 + 555 .L54: + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 556 .loc 1 290 0 + 557 0188 4022 movs r2, #64 + 558 018a DFE7 b .L25 + 559 .L55: + 560 018c 8022 movs r2, #128 + 561 018e D200 lsls r2, r2, #3 + 562 0190 DCE7 b .L25 + 563 .L56: + 564 0192 8022 movs r2, #128 + 565 0194 D201 lsls r2, r2, #7 + 566 0196 D9E7 b .L25 + 567 .L57: + 568 0198 8022 movs r2, #128 + 569 019a D202 lsls r2, r2, #11 + 570 019c D6E7 b .L25 + ARM GAS /tmp/ccJCJaQH.s page 17 + + + 571 .L63: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 572 .loc 1 296 0 + 573 019e 1F4A ldr r2, .L69+32 + 574 01a0 1368 ldr r3, [r2] + 575 01a2 0F21 movs r1, #15 + 576 01a4 8B43 bics r3, r1 + 577 01a6 1360 str r3, [r2] + 578 .L27: + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** #endif + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Initialise the error code */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 579 .loc 1 331 0 + 580 01a8 0023 movs r3, #0 + 581 01aa C363 str r3, [r0, #60] + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Initialize the DMA state */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 582 .loc 1 334 0 + 583 01ac 2522 movs r2, #37 + 584 01ae 8354 strb r3, [r0, r2] + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Release Lock */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 585 .loc 1 337 0 + 586 01b0 013A subs r2, r2, #1 + 587 01b2 8354 strb r3, [r0, r2] + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 588 .loc 1 339 0 + 589 01b4 0020 movs r0, #0 + 590 .LVL23: + 591 .L21: + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 592 .loc 1 340 0 + 593 @ sp needed + 594 01b6 00BD pop {pc} + 595 .LVL24: + 596 .L64: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 597 .loc 1 301 0 + 598 01b8 184A ldr r2, .L69+32 + 599 01ba 1368 ldr r3, [r2] + 600 01bc F021 movs r1, #240 + 601 01be 8B43 bics r3, r1 + 602 01c0 1360 str r3, [r2] + 603 01c2 F1E7 b .L27 + 604 .L65: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 605 .loc 1 306 0 + 606 01c4 154A ldr r2, .L69+32 + 607 01c6 1368 ldr r3, [r2] + 608 01c8 1649 ldr r1, .L69+40 + 609 01ca 0B40 ands r3, r1 + 610 01cc 1360 str r3, [r2] + 611 01ce EBE7 b .L27 + ARM GAS /tmp/ccJCJaQH.s page 18 + + + 612 .L66: + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 613 .loc 1 311 0 + 614 01d0 124A ldr r2, .L69+32 + 615 01d2 1368 ldr r3, [r2] + 616 01d4 1449 ldr r1, .L69+44 + 617 01d6 0B40 ands r3, r1 + 618 01d8 1360 str r3, [r2] + 619 01da E5E7 b .L27 + 620 .L67: + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 621 .loc 1 316 0 + 622 01dc 0F4A ldr r2, .L69+32 + 623 01de 1368 ldr r3, [r2] + 624 01e0 1249 ldr r1, .L69+48 + 625 01e2 0B40 ands r3, r1 + 626 01e4 1360 str r3, [r2] + 627 01e6 DFE7 b .L27 + 628 .L68: + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 629 .loc 1 322 0 + 630 01e8 0C4A ldr r2, .L69+32 + 631 01ea 1368 ldr r3, [r2] + 632 01ec 1049 ldr r1, .L69+52 + 633 01ee 0B40 ands r3, r1 + 634 01f0 1360 str r3, [r2] + 635 01f2 D9E7 b .L27 + 636 .L33: + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 637 .loc 1 262 0 + 638 01f4 0120 movs r0, #1 + 639 .LVL25: + 640 01f6 DEE7 b .L21 + 641 .LVL26: + 642 .L34: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 643 .loc 1 268 0 + 644 01f8 0120 movs r0, #1 + 645 .LVL27: + 646 01fa DCE7 b .L21 + 647 .L70: + 648 .align 2 + 649 .L69: + 650 01fc 08000240 .word 1073872904 + 651 0200 1C000240 .word 1073872924 + 652 0204 30000240 .word 1073872944 + 653 0208 44000240 .word 1073872964 + 654 020c 58000240 .word 1073872984 + 655 0210 6C000240 .word 1073873004 + 656 0214 00000240 .word 1073872896 + 657 0218 80000240 .word 1073873024 + 658 021c A8000240 .word 1073873064 + 659 0220 FFFFFFF0 .word -251658241 + 660 0224 FFF0FFFF .word -3841 + 661 0228 FF0FFFFF .word -61441 + 662 022c FFFFF0FF .word -983041 + 663 0230 FFFF0FFF .word -15728641 + ARM GAS /tmp/ccJCJaQH.s page 19 + + + 664 .cfi_endproc + 665 .LFE40: + 667 .section .text.HAL_DMA_Start,"ax",%progbits + 668 .align 1 + 669 .global HAL_DMA_Start + 670 .syntax unified + 671 .code 16 + 672 .thumb_func + 673 .fpu softvfp + 675 HAL_DMA_Start: + 676 .LFB41: + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @} + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group2 + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief I/O operation functions + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @verbatim + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ##### IO operation functions ##### + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] This section provides functions allowing to: + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** Start DMA transfer with interrupt + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Abort DMA transfer + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Poll for transfer complete + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Handle DMA interrupt request + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @endverbatim + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Starts the DMA Transfer. + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 677 .loc 1 375 0 + 678 .cfi_startproc + 679 @ args = 0, pretend = 0, frame = 0 + 680 @ frame_needed = 0, uses_anonymous_args = 0 + 681 .LVL28: + 682 0000 70B5 push {r4, r5, r6, lr} + 683 .LCFI2: + 684 .cfi_def_cfa_offset 16 + 685 .cfi_offset 4, -16 + 686 .cfi_offset 5, -12 + 687 .cfi_offset 6, -8 + ARM GAS /tmp/ccJCJaQH.s page 20 + + + 688 .cfi_offset 14, -4 + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process locked */ + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_LOCK(hdma); + 689 .loc 1 377 0 + 690 0002 2424 movs r4, #36 + 691 0004 045D ldrb r4, [r0, r4] + 692 0006 012C cmp r4, #1 + 693 0008 1ED0 beq .L75 + 694 .loc 1 377 0 is_stmt 0 discriminator 2 + 695 000a 0126 movs r6, #1 + 696 000c 2424 movs r4, #36 + 697 000e 0655 strb r6, [r0, r4] + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change DMA peripheral state */ + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 698 .loc 1 380 0 is_stmt 1 discriminator 2 + 699 0010 0134 adds r4, r4, #1 + 700 0012 0225 movs r5, #2 + 701 0014 0555 strb r5, [r0, r4] + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the parameters */ + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the peripheral */ + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 702 .loc 1 386 0 discriminator 2 + 703 0016 0568 ldr r5, [r0] + 704 0018 2C68 ldr r4, [r5] + 705 001a B443 bics r4, r6 + 706 001c 2C60 str r4, [r5] + 707 .LVL29: + 708 .LBB6: + 709 .LBB7: + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Enable the Peripheral */ + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process locked */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_LOCK(hdma); + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 21 + + + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change DMA peripheral state */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check the parameters */ + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the peripheral */ + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Enable the transfer complete interrupt */ + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Enable the Half transfer complete interrupt */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Enable the transfer Error interrupt */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Enable the Peripheral */ + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Aborts the DMA Transfer. + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t tickstart = 0U; + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the channel */ + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Get timeout */ + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** tickstart = HAL_GetTick(); + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check if the DMA Channel is effectively disabled */ + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** while((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check for the Timeout */ + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Update error code */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_TIMEOUT; + ARM GAS /tmp/ccJCJaQH.s page 22 + + + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_TIMEOUT; + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state*/ + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Aborts the DMA Transfer in Interrupt mode. + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* no transfer ongoing */ + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** status = HAL_ERROR; + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable DMA IT */ + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the channel */ + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear all flags */ + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Call User Abort callback */ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return status; + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + ARM GAS /tmp/ccJCJaQH.s page 23 + + + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Polling for transfer complete. + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param CompleteLevel: Specifies the DMA level complete. + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param Timeout: Timeout duration. + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t temp; + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t tickstart = 0U; + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Get the level transfer complete flag */ + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer Complete flag */ + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Half Transfer Complete flag */ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Get timeout */ + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** tickstart = HAL_GetTick(); + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the transfer error flags */ + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Update error code */ + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State= HAL_DMA_STATE_ERROR; + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_ERROR; + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Check for the Timeout */ + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(Timeout != HAL_MAX_DELAY) + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Update error code */ + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State= HAL_DMA_STATE_TIMEOUT; + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + ARM GAS /tmp/ccJCJaQH.s page 24 + + + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_TIMEOUT; + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the transfer complete flag */ + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* The selected Channelx EN bit is cleared (DMA is disabled and + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** all transfers are complete) */ + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process unlocked */ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* The selected Channelx EN bit is cleared (DMA is disabled and + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** all transfers are complete) */ + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY_HALF; + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process unlocked */ + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return HAL_OK; + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Handles DMA interrupt request. + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval None + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the transfer error interrupt */ + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the transfer error flag */ + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Update error code */ + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TE; + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + ARM GAS /tmp/ccJCJaQH.s page 25 + + + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if (hdma->XferErrorCallback != NULL) + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer error callback */ + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->XferErrorCallback(hdma); + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the half transfer interrupt */ + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change DMA peripheral state */ + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY_HALF; + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Half transfer callback */ + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Disable the transfer complete interrupt */ + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Clear the transfer complete flag */ + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Update error code */ + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_NONE; + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Change the DMA state */ + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 26 + + + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process Unlocked */ + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer complete callback */ + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @} + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group3 + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Peripheral State functions + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @verbatim + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** ##### Peripheral State functions ##### + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** =============================================================================== + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** [..] + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** This subsection provides functions allowing to + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Check the DMA state + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** (+) Get error code + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** @endverbatim + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Returns the DMA state. + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL state + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return hdma->State; + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Return the DMA error code + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval DMA Error Code + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return hdma->ErrorCode; + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @} + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + ARM GAS /tmp/ccJCJaQH.s page 27 + + + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @} + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Private macro -------------------------------------------------------------*/ + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** @addtogroup DMA_Private + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @{ + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @brief Sets the DMA Transfer parameter. + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** * @retval HAL status + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** */ + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure DMA Channel data length */ + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CNDTR = DataLength; + 710 .loc 1 778 0 discriminator 2 + 711 001e 0468 ldr r4, [r0] + 712 0020 6360 str r3, [r4, #4] + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Peripheral to Memory */ + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 713 .loc 1 781 0 discriminator 2 + 714 0022 8368 ldr r3, [r0, #8] + 715 .LVL30: + 716 0024 102B cmp r3, #16 + 717 0026 0AD0 beq .L76 + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CPAR = DstAddress; + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure DMA Channel source address */ + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CMAR = SrcAddress; + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Memory to Peripheral */ + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** else + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure DMA Channel source address */ + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CPAR = SrcAddress; + 718 .loc 1 793 0 + 719 0028 0368 ldr r3, [r0] + 720 002a 9960 str r1, [r3, #8] + 721 .LVL31: + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** hdma->Instance->CMAR = DstAddress; + 722 .loc 1 796 0 + ARM GAS /tmp/ccJCJaQH.s page 28 + + + 723 002c 0368 ldr r3, [r0] + 724 002e DA60 str r2, [r3, #12] + 725 .L74: + 726 .LVL32: + 727 .LBE7: + 728 .LBE6: + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 729 .loc 1 392 0 discriminator 2 + 730 0030 0268 ldr r2, [r0] + 731 .LVL33: + 732 0032 1368 ldr r3, [r2] + 733 0034 0121 movs r1, #1 + 734 .LVL34: + 735 0036 0B43 orrs r3, r1 + 736 0038 1360 str r3, [r2] + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 737 .loc 1 394 0 discriminator 2 + 738 003a 0020 movs r0, #0 + 739 .LVL35: + 740 .L72: + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 741 .loc 1 395 0 + 742 @ sp needed + 743 003c 70BD pop {r4, r5, r6, pc} + 744 .LVL36: + 745 .L76: + 746 .LBB9: + 747 .LBB8: + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 748 .loc 1 784 0 + 749 003e 0368 ldr r3, [r0] + 750 0040 9A60 str r2, [r3, #8] + 751 .LVL37: + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 752 .loc 1 787 0 + 753 0042 0368 ldr r3, [r0] + 754 0044 D960 str r1, [r3, #12] + 755 0046 F3E7 b .L74 + 756 .LVL38: + 757 .L75: + 758 .LBE8: + 759 .LBE9: + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 760 .loc 1 377 0 + 761 0048 0220 movs r0, #2 + 762 .LVL39: + 763 004a F7E7 b .L72 + 764 .cfi_endproc + 765 .LFE41: + 767 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 768 .align 1 + 769 .global HAL_DMA_Start_IT + 770 .syntax unified + 771 .code 16 + 772 .thumb_func + 773 .fpu softvfp + 775 HAL_DMA_Start_IT: + ARM GAS /tmp/ccJCJaQH.s page 29 + + + 776 .LFB42: + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Process locked */ + 777 .loc 1 407 0 + 778 .cfi_startproc + 779 @ args = 0, pretend = 0, frame = 0 + 780 @ frame_needed = 0, uses_anonymous_args = 0 + 781 .LVL40: + 782 0000 70B5 push {r4, r5, r6, lr} + 783 .LCFI3: + 784 .cfi_def_cfa_offset 16 + 785 .cfi_offset 4, -16 + 786 .cfi_offset 5, -12 + 787 .cfi_offset 6, -8 + 788 .cfi_offset 14, -4 + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 789 .loc 1 409 0 + 790 0002 2424 movs r4, #36 + 791 0004 045D ldrb r4, [r0, r4] + 792 0006 012C cmp r4, #1 + 793 0008 2DD0 beq .L81 + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 794 .loc 1 409 0 is_stmt 0 discriminator 2 + 795 000a 0126 movs r6, #1 + 796 000c 2424 movs r4, #36 + 797 000e 0655 strb r6, [r0, r4] + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 798 .loc 1 412 0 is_stmt 1 discriminator 2 + 799 0010 0134 adds r4, r4, #1 + 800 0012 0225 movs r5, #2 + 801 0014 0555 strb r5, [r0, r4] + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 802 .loc 1 418 0 discriminator 2 + 803 0016 0568 ldr r5, [r0] + 804 0018 2C68 ldr r4, [r5] + 805 001a B443 bics r4, r6 + 806 001c 2C60 str r4, [r5] + 807 .LVL41: + 808 .LBB10: + 809 .LBB11: + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 810 .loc 1 778 0 discriminator 2 + 811 001e 0468 ldr r4, [r0] + 812 0020 6360 str r3, [r4, #4] + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 813 .loc 1 781 0 discriminator 2 + 814 0022 8368 ldr r3, [r0, #8] + 815 .LVL42: + 816 0024 102B cmp r3, #16 + 817 0026 19D0 beq .L82 + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 818 .loc 1 793 0 + 819 0028 0368 ldr r3, [r0] + 820 002a 9960 str r1, [r3, #8] + 821 .LVL43: + 822 .loc 1 796 0 + 823 002c 0368 ldr r3, [r0] + 824 002e DA60 str r2, [r3, #12] + ARM GAS /tmp/ccJCJaQH.s page 30 + + + 825 .L80: + 826 .LVL44: + 827 .LBE11: + 828 .LBE10: + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 829 .loc 1 424 0 discriminator 2 + 830 0030 0268 ldr r2, [r0] + 831 .LVL45: + 832 0032 1368 ldr r3, [r2] + 833 0034 0221 movs r1, #2 + 834 .LVL46: + 835 0036 0B43 orrs r3, r1 + 836 0038 1360 str r3, [r2] + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 837 .loc 1 427 0 discriminator 2 + 838 003a 0268 ldr r2, [r0] + 839 003c 1368 ldr r3, [r2] + 840 003e 0231 adds r1, r1, #2 + 841 0040 0B43 orrs r3, r1 + 842 0042 1360 str r3, [r2] + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 843 .loc 1 430 0 discriminator 2 + 844 0044 0268 ldr r2, [r0] + 845 0046 1368 ldr r3, [r2] + 846 0048 0431 adds r1, r1, #4 + 847 004a 0B43 orrs r3, r1 + 848 004c 1360 str r3, [r2] + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 849 .loc 1 433 0 discriminator 2 + 850 004e 0268 ldr r2, [r0] + 851 0050 1368 ldr r3, [r2] + 852 0052 0739 subs r1, r1, #7 + 853 0054 0B43 orrs r3, r1 + 854 0056 1360 str r3, [r2] + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 855 .loc 1 435 0 discriminator 2 + 856 0058 0020 movs r0, #0 + 857 .LVL47: + 858 .L78: + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 859 .loc 1 436 0 + 860 @ sp needed + 861 005a 70BD pop {r4, r5, r6, pc} + 862 .LVL48: + 863 .L82: + 864 .LBB13: + 865 .LBB12: + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 866 .loc 1 784 0 + 867 005c 0368 ldr r3, [r0] + 868 005e 9A60 str r2, [r3, #8] + 869 .LVL49: + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 870 .loc 1 787 0 + 871 0060 0368 ldr r3, [r0] + 872 0062 D960 str r1, [r3, #12] + 873 0064 E4E7 b .L80 + ARM GAS /tmp/ccJCJaQH.s page 31 + + + 874 .LVL50: + 875 .L81: + 876 .LBE12: + 877 .LBE13: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 878 .loc 1 409 0 + 879 0066 0220 movs r0, #2 + 880 .LVL51: + 881 0068 F7E7 b .L78 + 882 .cfi_endproc + 883 .LFE42: + 885 .section .text.HAL_DMA_Abort,"ax",%progbits + 886 .align 1 + 887 .global HAL_DMA_Abort + 888 .syntax unified + 889 .code 16 + 890 .thumb_func + 891 .fpu softvfp + 893 HAL_DMA_Abort: + 894 .LFB43: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t tickstart = 0U; + 895 .loc 1 445 0 + 896 .cfi_startproc + 897 @ args = 0, pretend = 0, frame = 0 + 898 @ frame_needed = 0, uses_anonymous_args = 0 + 899 .LVL52: + 900 0000 70B5 push {r4, r5, r6, lr} + 901 .LCFI4: + 902 .cfi_def_cfa_offset 16 + 903 .cfi_offset 4, -16 + 904 .cfi_offset 5, -12 + 905 .cfi_offset 6, -8 + 906 .cfi_offset 14, -4 + 907 0002 0400 movs r4, r0 + 908 .LVL53: + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 909 .loc 1 449 0 + 910 0004 0268 ldr r2, [r0] + 911 0006 1368 ldr r3, [r2] + 912 0008 0121 movs r1, #1 + 913 000a 8B43 bics r3, r1 + 914 000c 1360 str r3, [r2] + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 915 .loc 1 452 0 + 916 000e FFF7FEFF bl HAL_GetTick + 917 .LVL54: + 918 0012 0500 movs r5, r0 + 919 .LVL55: + 920 .L84: + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 921 .loc 1 455 0 + 922 0014 2368 ldr r3, [r4] + 923 0016 1B68 ldr r3, [r3] + 924 0018 DB07 lsls r3, r3, #31 + 925 001a 12D5 bpl .L87 + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 926 .loc 1 458 0 + ARM GAS /tmp/ccJCJaQH.s page 32 + + + 927 001c FFF7FEFF bl HAL_GetTick + 928 .LVL56: + 929 0020 401B subs r0, r0, r5 + 930 0022 FA23 movs r3, #250 + 931 0024 9B00 lsls r3, r3, #2 + 932 0026 9842 cmp r0, r3 + 933 0028 F4D9 bls .L84 + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 934 .loc 1 461 0 + 935 002a E36B ldr r3, [r4, #60] + 936 002c 2022 movs r2, #32 + 937 002e 1343 orrs r3, r2 + 938 0030 E363 str r3, [r4, #60] + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 939 .loc 1 464 0 + 940 0032 2423 movs r3, #36 + 941 0034 0022 movs r2, #0 + 942 0036 E254 strb r2, [r4, r3] + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 943 .loc 1 467 0 + 944 0038 0133 adds r3, r3, #1 + 945 003a 0332 adds r2, r2, #3 + 946 003c E254 strb r2, [r4, r3] + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 947 .loc 1 469 0 + 948 003e 0320 movs r0, #3 + 949 0040 06E0 b .L85 + 950 .L87: + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 951 .loc 1 473 0 + 952 0042 2423 movs r3, #36 + 953 0044 0022 movs r2, #0 + 954 0046 E254 strb r2, [r4, r3] + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 955 .loc 1 476 0 + 956 0048 0133 adds r3, r3, #1 + 957 004a 0132 adds r2, r2, #1 + 958 004c E254 strb r2, [r4, r3] + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 959 .loc 1 478 0 + 960 004e 0020 movs r0, #0 + 961 .L85: + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 962 .loc 1 479 0 + 963 @ sp needed + 964 .LVL57: + 965 .LVL58: + 966 0050 70BD pop {r4, r5, r6, pc} + 967 .cfi_endproc + 968 .LFE43: + 970 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 971 .align 1 + 972 .global HAL_DMA_Abort_IT + 973 .syntax unified + 974 .code 16 + 975 .thumb_func + 976 .fpu softvfp + ARM GAS /tmp/ccJCJaQH.s page 33 + + + 978 HAL_DMA_Abort_IT: + 979 .LFB44: + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 980 .loc 1 488 0 + 981 .cfi_startproc + 982 @ args = 0, pretend = 0, frame = 0 + 983 @ frame_needed = 0, uses_anonymous_args = 0 + 984 .LVL59: + 985 0000 10B5 push {r4, lr} + 986 .LCFI5: + 987 .cfi_def_cfa_offset 8 + 988 .cfi_offset 4, -8 + 989 .cfi_offset 14, -4 + 990 .LVL60: + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 991 .loc 1 491 0 + 992 0002 2523 movs r3, #37 + 993 0004 C35C ldrb r3, [r0, r3] + 994 0006 022B cmp r3, #2 + 995 0008 03D0 beq .L89 + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 996 .loc 1 494 0 + 997 000a 0423 movs r3, #4 + 998 000c C363 str r3, [r0, #60] + 999 .LVL61: + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1000 .loc 1 496 0 + 1001 000e 0120 movs r0, #1 + 1002 .LVL62: + 1003 .L90: + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1004 .loc 1 522 0 + 1005 @ sp needed + 1006 0010 10BD pop {r4, pc} + 1007 .LVL63: + 1008 .L89: + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1009 .loc 1 501 0 + 1010 0012 0268 ldr r2, [r0] + 1011 0014 1368 ldr r3, [r2] + 1012 0016 0E21 movs r1, #14 + 1013 0018 8B43 bics r3, r1 + 1014 001a 1360 str r3, [r2] + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1015 .loc 1 504 0 + 1016 001c 0268 ldr r2, [r0] + 1017 001e 1368 ldr r3, [r2] + 1018 0020 0D39 subs r1, r1, #13 + 1019 0022 8B43 bics r3, r1 + 1020 0024 1360 str r3, [r2] + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1021 .loc 1 507 0 + 1022 0026 0368 ldr r3, [r0] + 1023 0028 194A ldr r2, .L100 + 1024 002a 9342 cmp r3, r2 + 1025 002c 14D0 beq .L92 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 34 + + + 1026 .loc 1 507 0 is_stmt 0 discriminator 1 + 1027 002e 194A ldr r2, .L100+4 + 1028 0030 9342 cmp r3, r2 + 1029 0032 20D0 beq .L93 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1030 .loc 1 507 0 discriminator 3 + 1031 0034 184A ldr r2, .L100+8 + 1032 0036 9342 cmp r3, r2 + 1033 0038 1FD0 beq .L94 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1034 .loc 1 507 0 discriminator 5 + 1035 003a 184A ldr r2, .L100+12 + 1036 003c 9342 cmp r3, r2 + 1037 003e 1FD0 beq .L95 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1038 .loc 1 507 0 discriminator 7 + 1039 0040 174A ldr r2, .L100+16 + 1040 0042 9342 cmp r3, r2 + 1041 0044 1FD0 beq .L96 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1042 .loc 1 507 0 discriminator 9 + 1043 0046 174A ldr r2, .L100+20 + 1044 0048 9342 cmp r3, r2 + 1045 004a 02D0 beq .L99 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1046 .loc 1 507 0 + 1047 004c 8022 movs r2, #128 + 1048 004e 5204 lsls r2, r2, #17 + 1049 0050 03E0 b .L91 + 1050 .L99: + 1051 0052 8022 movs r2, #128 + 1052 0054 5203 lsls r2, r2, #13 + 1053 0056 00E0 b .L91 + 1054 .L92: + 1055 0058 0122 movs r2, #1 + 1056 .L91: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1057 .loc 1 507 0 discriminator 24 + 1058 005a 134B ldr r3, .L100+24 + 1059 005c 5A60 str r2, [r3, #4] + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1060 .loc 1 510 0 is_stmt 1 discriminator 24 + 1061 005e 2523 movs r3, #37 + 1062 0060 0122 movs r2, #1 + 1063 0062 C254 strb r2, [r0, r3] + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1064 .loc 1 513 0 discriminator 24 + 1065 0064 013B subs r3, r3, #1 + 1066 0066 0022 movs r2, #0 + 1067 0068 C254 strb r2, [r0, r3] + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1068 .loc 1 516 0 discriminator 24 + 1069 006a 836B ldr r3, [r0, #56] + 1070 006c 002B cmp r3, #0 + 1071 006e 0DD0 beq .L98 + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1072 .loc 1 518 0 + ARM GAS /tmp/ccJCJaQH.s page 35 + + + 1073 0070 9847 blx r3 + 1074 .LVL64: + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1075 .loc 1 489 0 + 1076 0072 0020 movs r0, #0 + 1077 0074 CCE7 b .L90 + 1078 .LVL65: + 1079 .L93: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1080 .loc 1 507 0 + 1081 0076 1022 movs r2, #16 + 1082 0078 EFE7 b .L91 + 1083 .L94: + 1084 007a 8022 movs r2, #128 + 1085 007c 5200 lsls r2, r2, #1 + 1086 007e ECE7 b .L91 + 1087 .L95: + 1088 0080 8022 movs r2, #128 + 1089 0082 5201 lsls r2, r2, #5 + 1090 0084 E9E7 b .L91 + 1091 .L96: + 1092 0086 8022 movs r2, #128 + 1093 0088 5202 lsls r2, r2, #9 + 1094 008a E6E7 b .L91 + 1095 .L98: + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1096 .loc 1 489 0 + 1097 008c 0020 movs r0, #0 + 1098 .LVL66: + 1099 008e BFE7 b .L90 + 1100 .L101: + 1101 .align 2 + 1102 .L100: + 1103 0090 08000240 .word 1073872904 + 1104 0094 1C000240 .word 1073872924 + 1105 0098 30000240 .word 1073872944 + 1106 009c 44000240 .word 1073872964 + 1107 00a0 58000240 .word 1073872984 + 1108 00a4 6C000240 .word 1073873004 + 1109 00a8 00000240 .word 1073872896 + 1110 .cfi_endproc + 1111 .LFE44: + 1113 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 1114 .align 1 + 1115 .global HAL_DMA_PollForTransfer + 1116 .syntax unified + 1117 .code 16 + 1118 .thumb_func + 1119 .fpu softvfp + 1121 HAL_DMA_PollForTransfer: + 1122 .LFB45: + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** uint32_t temp; + 1123 .loc 1 533 0 + 1124 .cfi_startproc + 1125 @ args = 0, pretend = 0, frame = 8 + 1126 @ frame_needed = 0, uses_anonymous_args = 0 + 1127 .LVL67: + ARM GAS /tmp/ccJCJaQH.s page 36 + + + 1128 0000 F0B5 push {r4, r5, r6, r7, lr} + 1129 .LCFI6: + 1130 .cfi_def_cfa_offset 20 + 1131 .cfi_offset 4, -20 + 1132 .cfi_offset 5, -16 + 1133 .cfi_offset 6, -12 + 1134 .cfi_offset 7, -8 + 1135 .cfi_offset 14, -4 + 1136 0002 83B0 sub sp, sp, #12 + 1137 .LCFI7: + 1138 .cfi_def_cfa_offset 32 + 1139 0004 0500 movs r5, r0 + 1140 0006 0C00 movs r4, r1 + 1141 0008 1700 movs r7, r2 + 1142 .LVL68: + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1143 .loc 1 538 0 + 1144 000a 0029 cmp r1, #0 + 1145 000c 18D1 bne .L103 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1146 .loc 1 541 0 + 1147 000e 0368 ldr r3, [r0] + 1148 0010 7F4A ldr r2, .L153 + 1149 .LVL69: + 1150 0012 9342 cmp r3, r2 + 1151 0014 2DD0 beq .L115 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1152 .loc 1 541 0 is_stmt 0 discriminator 1 + 1153 0016 7F4A ldr r2, .L153+4 + 1154 0018 9342 cmp r3, r2 + 1155 001a 2FD0 beq .L116 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1156 .loc 1 541 0 discriminator 3 + 1157 001c 7E4A ldr r2, .L153+8 + 1158 001e 9342 cmp r3, r2 + 1159 0020 2ED0 beq .L117 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1160 .loc 1 541 0 discriminator 5 + 1161 0022 7E4A ldr r2, .L153+12 + 1162 0024 9342 cmp r3, r2 + 1163 0026 2ED0 beq .L118 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1164 .loc 1 541 0 discriminator 7 + 1165 0028 7D4A ldr r2, .L153+16 + 1166 002a 9342 cmp r3, r2 + 1167 002c 2ED0 beq .L119 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1168 .loc 1 541 0 discriminator 9 + 1169 002e 7D4A ldr r2, .L153+20 + 1170 0030 9342 cmp r3, r2 + 1171 0032 02D0 beq .L145 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1172 .loc 1 541 0 + 1173 0034 8026 movs r6, #128 + 1174 0036 B604 lsls r6, r6, #18 + 1175 0038 1CE0 b .L104 + 1176 .L145: + ARM GAS /tmp/ccJCJaQH.s page 37 + + + 1177 003a 8026 movs r6, #128 + 1178 003c B603 lsls r6, r6, #14 + 1179 003e 19E0 b .L104 + 1180 .LVL70: + 1181 .L103: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1182 .loc 1 546 0 is_stmt 1 + 1183 0040 0368 ldr r3, [r0] + 1184 0042 734A ldr r2, .L153 + 1185 .LVL71: + 1186 0044 9342 cmp r3, r2 + 1187 0046 24D0 beq .L121 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1188 .loc 1 546 0 is_stmt 0 discriminator 1 + 1189 0048 724A ldr r2, .L153+4 + 1190 004a 9342 cmp r3, r2 + 1191 004c 23D0 beq .L122 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1192 .loc 1 546 0 discriminator 3 + 1193 004e 724A ldr r2, .L153+8 + 1194 0050 9342 cmp r3, r2 + 1195 0052 22D0 beq .L123 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1196 .loc 1 546 0 discriminator 5 + 1197 0054 714A ldr r2, .L153+12 + 1198 0056 9342 cmp r3, r2 + 1199 0058 22D0 beq .L124 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1200 .loc 1 546 0 discriminator 7 + 1201 005a 714A ldr r2, .L153+16 + 1202 005c 9342 cmp r3, r2 + 1203 005e 22D0 beq .L125 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1204 .loc 1 546 0 discriminator 9 + 1205 0060 704A ldr r2, .L153+20 + 1206 0062 9342 cmp r3, r2 + 1207 0064 02D0 beq .L146 + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1208 .loc 1 546 0 + 1209 0066 8026 movs r6, #128 + 1210 0068 F604 lsls r6, r6, #19 + 1211 006a 03E0 b .L104 + 1212 .L146: + 1213 006c 8026 movs r6, #128 + 1214 006e F603 lsls r6, r6, #15 + 1215 0070 00E0 b .L104 + 1216 .L115: + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1217 .loc 1 541 0 is_stmt 1 + 1218 0072 0226 movs r6, #2 + 1219 .L104: + 1220 .LVL72: + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1221 .loc 1 550 0 + 1222 0074 FFF7FEFF bl HAL_GetTick + 1223 .LVL73: + 1224 0078 0190 str r0, [sp, #4] + ARM GAS /tmp/ccJCJaQH.s page 38 + + + 1225 .LVL74: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1226 .loc 1 552 0 + 1227 007a 1FE0 b .L109 + 1228 .LVL75: + 1229 .L116: + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1230 .loc 1 541 0 + 1231 007c 2026 movs r6, #32 + 1232 007e F9E7 b .L104 + 1233 .L117: + 1234 0080 8026 movs r6, #128 + 1235 0082 B600 lsls r6, r6, #2 + 1236 0084 F6E7 b .L104 + 1237 .L118: + 1238 0086 8026 movs r6, #128 + 1239 0088 B601 lsls r6, r6, #6 + 1240 008a F3E7 b .L104 + 1241 .L119: + 1242 008c 8026 movs r6, #128 + 1243 008e B602 lsls r6, r6, #10 + 1244 0090 F0E7 b .L104 + 1245 .L121: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1246 .loc 1 546 0 + 1247 0092 0426 movs r6, #4 + 1248 0094 EEE7 b .L104 + 1249 .L122: + 1250 0096 4026 movs r6, #64 + 1251 0098 ECE7 b .L104 + 1252 .L123: + 1253 009a 8026 movs r6, #128 + 1254 009c F600 lsls r6, r6, #3 + 1255 009e E9E7 b .L104 + 1256 .L124: + 1257 00a0 8026 movs r6, #128 + 1258 00a2 F601 lsls r6, r6, #7 + 1259 00a4 E6E7 b .L104 + 1260 .L125: + 1261 00a6 8026 movs r6, #128 + 1262 00a8 F602 lsls r6, r6, #11 + 1263 00aa E3E7 b .L104 + 1264 .LVL76: + 1265 .L150: + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1266 .loc 1 554 0 + 1267 00ac 8023 movs r3, #128 + 1268 00ae 1B04 lsls r3, r3, #16 + 1269 00b0 00E0 b .L106 + 1270 .L127: + 1271 00b2 0823 movs r3, #8 + 1272 .L106: + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1273 .loc 1 554 0 is_stmt 0 discriminator 24 + 1274 00b4 1342 tst r3, r2 + 1275 00b6 28D1 bne .L147 + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + ARM GAS /tmp/ccJCJaQH.s page 39 + + + 1276 .loc 1 571 0 is_stmt 1 + 1277 00b8 7B1C adds r3, r7, #1 + 1278 00ba 35D1 bne .L148 + 1279 .L109: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1280 .loc 1 552 0 + 1281 00bc 5A4B ldr r3, .L153+24 + 1282 00be 1B68 ldr r3, [r3] + 1283 00c0 1E42 tst r6, r3 + 1284 00c2 45D1 bne .L149 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1285 .loc 1 554 0 + 1286 00c4 584B ldr r3, .L153+24 + 1287 00c6 1A68 ldr r2, [r3] + 1288 00c8 2B68 ldr r3, [r5] + 1289 00ca 5149 ldr r1, .L153 + 1290 00cc 8B42 cmp r3, r1 + 1291 00ce F0D0 beq .L127 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1292 .loc 1 554 0 is_stmt 0 discriminator 1 + 1293 00d0 5049 ldr r1, .L153+4 + 1294 00d2 8B42 cmp r3, r1 + 1295 00d4 0ED0 beq .L128 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1296 .loc 1 554 0 discriminator 3 + 1297 00d6 5049 ldr r1, .L153+8 + 1298 00d8 8B42 cmp r3, r1 + 1299 00da 0DD0 beq .L129 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1300 .loc 1 554 0 discriminator 5 + 1301 00dc 4F49 ldr r1, .L153+12 + 1302 00de 8B42 cmp r3, r1 + 1303 00e0 0DD0 beq .L130 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1304 .loc 1 554 0 discriminator 7 + 1305 00e2 4F49 ldr r1, .L153+16 + 1306 00e4 8B42 cmp r3, r1 + 1307 00e6 0DD0 beq .L131 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1308 .loc 1 554 0 discriminator 9 + 1309 00e8 4E49 ldr r1, .L153+20 + 1310 00ea 8B42 cmp r3, r1 + 1311 00ec DED0 beq .L150 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1312 .loc 1 554 0 + 1313 00ee 8023 movs r3, #128 + 1314 00f0 1B05 lsls r3, r3, #20 + 1315 00f2 DFE7 b .L106 + 1316 .L128: + 1317 00f4 8023 movs r3, #128 + 1318 00f6 DDE7 b .L106 + 1319 .L129: + 1320 00f8 8023 movs r3, #128 + 1321 00fa 1B01 lsls r3, r3, #4 + 1322 00fc DAE7 b .L106 + 1323 .L130: + 1324 00fe 8023 movs r3, #128 + ARM GAS /tmp/ccJCJaQH.s page 40 + + + 1325 0100 1B02 lsls r3, r3, #8 + 1326 0102 D7E7 b .L106 + 1327 .L131: + 1328 0104 8023 movs r3, #128 + 1329 0106 1B03 lsls r3, r3, #12 + 1330 0108 D4E7 b .L106 + 1331 .L147: + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1332 .loc 1 557 0 is_stmt 1 discriminator 24 + 1333 010a 474A ldr r2, .L153+24 + 1334 010c 5360 str r3, [r2, #4] + 1335 .LVL77: + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1336 .loc 1 560 0 discriminator 24 + 1337 010e EB6B ldr r3, [r5, #60] + 1338 0110 0122 movs r2, #1 + 1339 0112 1343 orrs r3, r2 + 1340 0114 EB63 str r3, [r5, #60] + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1341 .loc 1 563 0 discriminator 24 + 1342 0116 2523 movs r3, #37 + 1343 0118 0332 adds r2, r2, #3 + 1344 011a EA54 strb r2, [r5, r3] + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1345 .loc 1 566 0 discriminator 24 + 1346 011c 013B subs r3, r3, #1 + 1347 011e 0022 movs r2, #0 + 1348 0120 EA54 strb r2, [r5, r3] + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1349 .loc 1 568 0 discriminator 24 + 1350 0122 0120 movs r0, #1 + 1351 .L108: + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /** + 1352 .loc 1 615 0 + 1353 0124 03B0 add sp, sp, #12 + 1354 @ sp needed + 1355 .LVL78: + 1356 .LVL79: + 1357 .LVL80: + 1358 .LVL81: + 1359 0126 F0BD pop {r4, r5, r6, r7, pc} + 1360 .LVL82: + 1361 .L148: + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1362 .loc 1 573 0 + 1363 0128 002F cmp r7, #0 + 1364 012a 05D0 beq .L110 + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1365 .loc 1 573 0 is_stmt 0 discriminator 1 + 1366 012c FFF7FEFF bl HAL_GetTick + 1367 .LVL83: + 1368 0130 019B ldr r3, [sp, #4] + 1369 0132 C01A subs r0, r0, r3 + 1370 0134 B842 cmp r0, r7 + 1371 0136 C1D9 bls .L109 + 1372 .L110: + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 41 + + + 1373 .loc 1 576 0 is_stmt 1 + 1374 0138 EB6B ldr r3, [r5, #60] + 1375 013a 2022 movs r2, #32 + 1376 013c 1343 orrs r3, r2 + 1377 013e EB63 str r3, [r5, #60] + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1378 .loc 1 579 0 + 1379 0140 2523 movs r3, #37 + 1380 0142 1D3A subs r2, r2, #29 + 1381 0144 EA54 strb r2, [r5, r3] + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1382 .loc 1 582 0 + 1383 0146 013B subs r3, r3, #1 + 1384 0148 0022 movs r2, #0 + 1385 014a EA54 strb r2, [r5, r3] + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1386 .loc 1 584 0 + 1387 014c 0320 movs r0, #3 + 1388 014e E9E7 b .L108 + 1389 .L149: + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1390 .loc 1 589 0 + 1391 0150 002C cmp r4, #0 + 1392 0152 2ED1 bne .L112 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1393 .loc 1 592 0 + 1394 0154 2B68 ldr r3, [r5] + 1395 0156 2E4A ldr r2, .L153 + 1396 0158 9342 cmp r3, r2 + 1397 015a 14D0 beq .L133 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1398 .loc 1 592 0 is_stmt 0 discriminator 1 + 1399 015c 2D4A ldr r2, .L153+4 + 1400 015e 9342 cmp r3, r2 + 1401 0160 1CD0 beq .L134 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1402 .loc 1 592 0 discriminator 3 + 1403 0162 2D4A ldr r2, .L153+8 + 1404 0164 9342 cmp r3, r2 + 1405 0166 1BD0 beq .L135 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1406 .loc 1 592 0 discriminator 5 + 1407 0168 2C4A ldr r2, .L153+12 + 1408 016a 9342 cmp r3, r2 + 1409 016c 1BD0 beq .L136 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1410 .loc 1 592 0 discriminator 7 + 1411 016e 2C4A ldr r2, .L153+16 + 1412 0170 9342 cmp r3, r2 + 1413 0172 1BD0 beq .L137 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1414 .loc 1 592 0 discriminator 9 + 1415 0174 2B4A ldr r2, .L153+20 + 1416 0176 9342 cmp r3, r2 + 1417 0178 02D0 beq .L151 + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1418 .loc 1 592 0 + ARM GAS /tmp/ccJCJaQH.s page 42 + + + 1419 017a 8022 movs r2, #128 + 1420 017c 9204 lsls r2, r2, #18 + 1421 017e 03E0 b .L113 + 1422 .L151: + 1423 0180 8022 movs r2, #128 + 1424 0182 9203 lsls r2, r2, #14 + 1425 0184 00E0 b .L113 + 1426 .L133: + 1427 0186 0222 movs r2, #2 + 1428 .L113: + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1429 .loc 1 592 0 discriminator 24 + 1430 0188 274B ldr r3, .L153+24 + 1431 018a 5A60 str r2, [r3, #4] + 1432 .LVL84: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1433 .loc 1 596 0 is_stmt 1 discriminator 24 + 1434 018c 2523 movs r3, #37 + 1435 018e 0122 movs r2, #1 + 1436 0190 EA54 strb r2, [r5, r3] + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1437 .loc 1 599 0 discriminator 24 + 1438 0192 013B subs r3, r3, #1 + 1439 0194 0022 movs r2, #0 + 1440 0196 EA54 strb r2, [r5, r3] + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1441 .loc 1 614 0 discriminator 24 + 1442 0198 0020 movs r0, #0 + 1443 019a C3E7 b .L108 + 1444 .LVL85: + 1445 .L134: + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1446 .loc 1 592 0 + 1447 019c 2022 movs r2, #32 + 1448 019e F3E7 b .L113 + 1449 .L135: + 1450 01a0 8022 movs r2, #128 + 1451 01a2 9200 lsls r2, r2, #2 + 1452 01a4 F0E7 b .L113 + 1453 .L136: + 1454 01a6 8022 movs r2, #128 + 1455 01a8 9201 lsls r2, r2, #6 + 1456 01aa EDE7 b .L113 + 1457 .L137: + 1458 01ac 8022 movs r2, #128 + 1459 01ae 9202 lsls r2, r2, #10 + 1460 01b0 EAE7 b .L113 + 1461 .L112: + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1462 .loc 1 604 0 + 1463 01b2 2B68 ldr r3, [r5] + 1464 01b4 164A ldr r2, .L153 + 1465 01b6 9342 cmp r3, r2 + 1466 01b8 14D0 beq .L139 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1467 .loc 1 604 0 is_stmt 0 discriminator 1 + 1468 01ba 164A ldr r2, .L153+4 + ARM GAS /tmp/ccJCJaQH.s page 43 + + + 1469 01bc 9342 cmp r3, r2 + 1470 01be 1CD0 beq .L140 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1471 .loc 1 604 0 discriminator 3 + 1472 01c0 154A ldr r2, .L153+8 + 1473 01c2 9342 cmp r3, r2 + 1474 01c4 1BD0 beq .L141 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1475 .loc 1 604 0 discriminator 5 + 1476 01c6 154A ldr r2, .L153+12 + 1477 01c8 9342 cmp r3, r2 + 1478 01ca 1BD0 beq .L142 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1479 .loc 1 604 0 discriminator 7 + 1480 01cc 144A ldr r2, .L153+16 + 1481 01ce 9342 cmp r3, r2 + 1482 01d0 1BD0 beq .L143 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1483 .loc 1 604 0 discriminator 9 + 1484 01d2 144A ldr r2, .L153+20 + 1485 01d4 9342 cmp r3, r2 + 1486 01d6 02D0 beq .L152 + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1487 .loc 1 604 0 + 1488 01d8 8022 movs r2, #128 + 1489 01da D204 lsls r2, r2, #19 + 1490 01dc 03E0 b .L114 + 1491 .L152: + 1492 01de 8022 movs r2, #128 + 1493 01e0 D203 lsls r2, r2, #15 + 1494 01e2 00E0 b .L114 + 1495 .L139: + 1496 01e4 0422 movs r2, #4 + 1497 .L114: + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1498 .loc 1 604 0 discriminator 24 + 1499 01e6 104B ldr r3, .L153+24 + 1500 01e8 5A60 str r2, [r3, #4] + 1501 .LVL86: + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1502 .loc 1 608 0 is_stmt 1 discriminator 24 + 1503 01ea 2523 movs r3, #37 + 1504 01ec 0522 movs r2, #5 + 1505 01ee EA54 strb r2, [r5, r3] + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1506 .loc 1 611 0 discriminator 24 + 1507 01f0 013B subs r3, r3, #1 + 1508 01f2 0022 movs r2, #0 + 1509 01f4 EA54 strb r2, [r5, r3] + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1510 .loc 1 614 0 discriminator 24 + 1511 01f6 0020 movs r0, #0 + 1512 01f8 94E7 b .L108 + 1513 .LVL87: + 1514 .L140: + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1515 .loc 1 604 0 + ARM GAS /tmp/ccJCJaQH.s page 44 + + + 1516 01fa 4022 movs r2, #64 + 1517 01fc F3E7 b .L114 + 1518 .L141: + 1519 01fe 8022 movs r2, #128 + 1520 0200 D200 lsls r2, r2, #3 + 1521 0202 F0E7 b .L114 + 1522 .L142: + 1523 0204 8022 movs r2, #128 + 1524 0206 D201 lsls r2, r2, #7 + 1525 0208 EDE7 b .L114 + 1526 .L143: + 1527 020a 8022 movs r2, #128 + 1528 020c D202 lsls r2, r2, #11 + 1529 020e EAE7 b .L114 + 1530 .L154: + 1531 .align 2 + 1532 .L153: + 1533 0210 08000240 .word 1073872904 + 1534 0214 1C000240 .word 1073872924 + 1535 0218 30000240 .word 1073872944 + 1536 021c 44000240 .word 1073872964 + 1537 0220 58000240 .word 1073872984 + 1538 0224 6C000240 .word 1073873004 + 1539 0228 00000240 .word 1073872896 + 1540 .cfi_endproc + 1541 .LFE45: + 1543 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 1544 .align 1 + 1545 .global HAL_DMA_IRQHandler + 1546 .syntax unified + 1547 .code 16 + 1548 .thumb_func + 1549 .fpu softvfp + 1551 HAL_DMA_IRQHandler: + 1552 .LFB46: + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ + 1553 .loc 1 623 0 + 1554 .cfi_startproc + 1555 @ args = 0, pretend = 0, frame = 0 + 1556 @ frame_needed = 0, uses_anonymous_args = 0 + 1557 .LVL88: + 1558 0000 10B5 push {r4, lr} + 1559 .LCFI8: + 1560 .cfi_def_cfa_offset 8 + 1561 .cfi_offset 4, -8 + 1562 .cfi_offset 14, -4 + 1563 0002 0400 movs r4, r0 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1564 .loc 1 625 0 + 1565 0004 974B ldr r3, .L209 + 1566 0006 1A68 ldr r2, [r3] + 1567 0008 0368 ldr r3, [r0] + 1568 000a 9749 ldr r1, .L209+4 + 1569 000c 8B42 cmp r3, r1 + 1570 000e 14D0 beq .L167 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1571 .loc 1 625 0 is_stmt 0 discriminator 1 + ARM GAS /tmp/ccJCJaQH.s page 45 + + + 1572 0010 9649 ldr r1, .L209+8 + 1573 0012 8B42 cmp r3, r1 + 1574 0014 31D0 beq .L168 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1575 .loc 1 625 0 discriminator 3 + 1576 0016 9649 ldr r1, .L209+12 + 1577 0018 8B42 cmp r3, r1 + 1578 001a 30D0 beq .L169 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1579 .loc 1 625 0 discriminator 5 + 1580 001c 9549 ldr r1, .L209+16 + 1581 001e 8B42 cmp r3, r1 + 1582 0020 30D0 beq .L170 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1583 .loc 1 625 0 discriminator 7 + 1584 0022 9549 ldr r1, .L209+20 + 1585 0024 8B42 cmp r3, r1 + 1586 0026 30D0 beq .L171 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1587 .loc 1 625 0 discriminator 9 + 1588 0028 9449 ldr r1, .L209+24 + 1589 002a 8B42 cmp r3, r1 + 1590 002c 02D0 beq .L203 + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1591 .loc 1 625 0 + 1592 002e 8021 movs r1, #128 + 1593 0030 0905 lsls r1, r1, #20 + 1594 0032 03E0 b .L156 + 1595 .L203: + 1596 0034 8021 movs r1, #128 + 1597 0036 0904 lsls r1, r1, #16 + 1598 0038 00E0 b .L156 + 1599 .L167: + 1600 003a 0821 movs r1, #8 + 1601 .L156: + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1602 .loc 1 625 0 discriminator 24 + 1603 003c 1142 tst r1, r2 + 1604 003e 3CD0 beq .L157 + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1605 .loc 1 627 0 is_stmt 1 + 1606 0040 1A68 ldr r2, [r3] + 1607 0042 1207 lsls r2, r2, #28 + 1608 0044 39D5 bpl .L157 + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1609 .loc 1 630 0 + 1610 0046 1A68 ldr r2, [r3] + 1611 0048 0821 movs r1, #8 + 1612 004a 8A43 bics r2, r1 + 1613 004c 1A60 str r2, [r3] + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1614 .loc 1 633 0 + 1615 004e 2368 ldr r3, [r4] + 1616 0050 854A ldr r2, .L209+4 + 1617 0052 9342 cmp r3, r2 + 1618 0054 1FD0 beq .L173 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 46 + + + 1619 .loc 1 633 0 is_stmt 0 discriminator 1 + 1620 0056 854A ldr r2, .L209+8 + 1621 0058 9342 cmp r3, r2 + 1622 005a 46D0 beq .L174 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1623 .loc 1 633 0 discriminator 3 + 1624 005c 844A ldr r2, .L209+12 + 1625 005e 9342 cmp r3, r2 + 1626 0060 45D0 beq .L175 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1627 .loc 1 633 0 discriminator 5 + 1628 0062 844A ldr r2, .L209+16 + 1629 0064 9342 cmp r3, r2 + 1630 0066 45D0 beq .L176 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1631 .loc 1 633 0 discriminator 7 + 1632 0068 834A ldr r2, .L209+20 + 1633 006a 9342 cmp r3, r2 + 1634 006c 45D0 beq .L177 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1635 .loc 1 633 0 discriminator 9 + 1636 006e 834A ldr r2, .L209+24 + 1637 0070 9342 cmp r3, r2 + 1638 0072 0DD0 beq .L204 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1639 .loc 1 633 0 + 1640 0074 8022 movs r2, #128 + 1641 0076 1205 lsls r2, r2, #20 + 1642 0078 0EE0 b .L158 + 1643 .L168: + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1644 .loc 1 625 0 is_stmt 1 + 1645 007a 8021 movs r1, #128 + 1646 007c DEE7 b .L156 + 1647 .L169: + 1648 007e 8021 movs r1, #128 + 1649 0080 0901 lsls r1, r1, #4 + 1650 0082 DBE7 b .L156 + 1651 .L170: + 1652 0084 8021 movs r1, #128 + 1653 0086 0902 lsls r1, r1, #8 + 1654 0088 D8E7 b .L156 + 1655 .L171: + 1656 008a 8021 movs r1, #128 + 1657 008c 0903 lsls r1, r1, #12 + 1658 008e D5E7 b .L156 + 1659 .L204: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1660 .loc 1 633 0 + 1661 0090 8022 movs r2, #128 + 1662 0092 1204 lsls r2, r2, #16 + 1663 0094 00E0 b .L158 + 1664 .L173: + 1665 0096 0822 movs r2, #8 + 1666 .L158: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1667 .loc 1 633 0 is_stmt 0 discriminator 24 + ARM GAS /tmp/ccJCJaQH.s page 47 + + + 1668 0098 724B ldr r3, .L209 + 1669 009a 5A60 str r2, [r3, #4] + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1670 .loc 1 636 0 is_stmt 1 discriminator 24 + 1671 009c E36B ldr r3, [r4, #60] + 1672 009e 0122 movs r2, #1 + 1673 00a0 1343 orrs r3, r2 + 1674 00a2 E363 str r3, [r4, #60] + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1675 .loc 1 639 0 discriminator 24 + 1676 00a4 2523 movs r3, #37 + 1677 00a6 0332 adds r2, r2, #3 + 1678 00a8 E254 strb r2, [r4, r3] + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1679 .loc 1 642 0 discriminator 24 + 1680 00aa 013B subs r3, r3, #1 + 1681 00ac 0022 movs r2, #0 + 1682 00ae E254 strb r2, [r4, r3] + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1683 .loc 1 644 0 discriminator 24 + 1684 00b0 636B ldr r3, [r4, #52] + 1685 00b2 002B cmp r3, #0 + 1686 00b4 01D0 beq .L157 + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1687 .loc 1 647 0 + 1688 00b6 2000 movs r0, r4 + 1689 .LVL89: + 1690 00b8 9847 blx r3 + 1691 .LVL90: + 1692 .L157: + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1693 .loc 1 653 0 + 1694 00ba 6A4B ldr r3, .L209 + 1695 00bc 1A68 ldr r2, [r3] + 1696 00be 2368 ldr r3, [r4] + 1697 00c0 6949 ldr r1, .L209+4 + 1698 00c2 8B42 cmp r3, r1 + 1699 00c4 1FD0 beq .L179 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1700 .loc 1 653 0 is_stmt 0 discriminator 1 + 1701 00c6 6949 ldr r1, .L209+8 + 1702 00c8 8B42 cmp r3, r1 + 1703 00ca 3FD0 beq .L180 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1704 .loc 1 653 0 discriminator 3 + 1705 00cc 6849 ldr r1, .L209+12 + 1706 00ce 8B42 cmp r3, r1 + 1707 00d0 3ED0 beq .L181 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1708 .loc 1 653 0 discriminator 5 + 1709 00d2 6849 ldr r1, .L209+16 + 1710 00d4 8B42 cmp r3, r1 + 1711 00d6 3ED0 beq .L182 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1712 .loc 1 653 0 discriminator 7 + 1713 00d8 6749 ldr r1, .L209+20 + 1714 00da 8B42 cmp r3, r1 + ARM GAS /tmp/ccJCJaQH.s page 48 + + + 1715 00dc 3ED0 beq .L183 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1716 .loc 1 653 0 discriminator 9 + 1717 00de 6749 ldr r1, .L209+24 + 1718 00e0 8B42 cmp r3, r1 + 1719 00e2 0DD0 beq .L205 + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1720 .loc 1 653 0 + 1721 00e4 8021 movs r1, #128 + 1722 00e6 C904 lsls r1, r1, #19 + 1723 00e8 0EE0 b .L159 + 1724 .LVL91: + 1725 .L174: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1726 .loc 1 633 0 is_stmt 1 + 1727 00ea 8022 movs r2, #128 + 1728 00ec D4E7 b .L158 + 1729 .L175: + 1730 00ee 8022 movs r2, #128 + 1731 00f0 1201 lsls r2, r2, #4 + 1732 00f2 D1E7 b .L158 + 1733 .L176: + 1734 00f4 8022 movs r2, #128 + 1735 00f6 1202 lsls r2, r2, #8 + 1736 00f8 CEE7 b .L158 + 1737 .L177: + 1738 00fa 8022 movs r2, #128 + 1739 00fc 1203 lsls r2, r2, #12 + 1740 00fe CBE7 b .L158 + 1741 .LVL92: + 1742 .L205: + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1743 .loc 1 653 0 + 1744 0100 8021 movs r1, #128 + 1745 0102 C903 lsls r1, r1, #15 + 1746 0104 00E0 b .L159 + 1747 .L179: + 1748 0106 0421 movs r1, #4 + 1749 .L159: + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1750 .loc 1 653 0 is_stmt 0 discriminator 24 + 1751 0108 1142 tst r1, r2 + 1752 010a 38D0 beq .L160 + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1753 .loc 1 655 0 is_stmt 1 + 1754 010c 1A68 ldr r2, [r3] + 1755 010e 5207 lsls r2, r2, #29 + 1756 0110 35D5 bpl .L160 + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1757 .loc 1 658 0 + 1758 0112 1A68 ldr r2, [r3] + 1759 0114 9206 lsls r2, r2, #26 + 1760 0116 03D4 bmi .L161 + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1761 .loc 1 661 0 + 1762 0118 1A68 ldr r2, [r3] + 1763 011a 0421 movs r1, #4 + ARM GAS /tmp/ccJCJaQH.s page 49 + + + 1764 011c 8A43 bics r2, r1 + 1765 011e 1A60 str r2, [r3] + 1766 .L161: + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1767 .loc 1 664 0 + 1768 0120 2368 ldr r3, [r4] + 1769 0122 514A ldr r2, .L209+4 + 1770 0124 9342 cmp r3, r2 + 1771 0126 1FD0 beq .L185 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1772 .loc 1 664 0 is_stmt 0 discriminator 1 + 1773 0128 504A ldr r2, .L209+8 + 1774 012a 9342 cmp r3, r2 + 1775 012c 3FD0 beq .L186 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1776 .loc 1 664 0 discriminator 3 + 1777 012e 504A ldr r2, .L209+12 + 1778 0130 9342 cmp r3, r2 + 1779 0132 3ED0 beq .L187 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1780 .loc 1 664 0 discriminator 5 + 1781 0134 4F4A ldr r2, .L209+16 + 1782 0136 9342 cmp r3, r2 + 1783 0138 3ED0 beq .L188 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1784 .loc 1 664 0 discriminator 7 + 1785 013a 4F4A ldr r2, .L209+20 + 1786 013c 9342 cmp r3, r2 + 1787 013e 3ED0 beq .L189 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1788 .loc 1 664 0 discriminator 9 + 1789 0140 4E4A ldr r2, .L209+24 + 1790 0142 9342 cmp r3, r2 + 1791 0144 0DD0 beq .L206 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1792 .loc 1 664 0 + 1793 0146 8022 movs r2, #128 + 1794 0148 D204 lsls r2, r2, #19 + 1795 014a 0EE0 b .L162 + 1796 .L180: + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1797 .loc 1 653 0 is_stmt 1 + 1798 014c 4021 movs r1, #64 + 1799 014e DBE7 b .L159 + 1800 .L181: + 1801 0150 8021 movs r1, #128 + 1802 0152 C900 lsls r1, r1, #3 + 1803 0154 D8E7 b .L159 + 1804 .L182: + 1805 0156 8021 movs r1, #128 + 1806 0158 C901 lsls r1, r1, #7 + 1807 015a D5E7 b .L159 + 1808 .L183: + 1809 015c 8021 movs r1, #128 + 1810 015e C902 lsls r1, r1, #11 + 1811 0160 D2E7 b .L159 + 1812 .L206: + ARM GAS /tmp/ccJCJaQH.s page 50 + + + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1813 .loc 1 664 0 + 1814 0162 8022 movs r2, #128 + 1815 0164 D203 lsls r2, r2, #15 + 1816 0166 00E0 b .L162 + 1817 .L185: + 1818 0168 0422 movs r2, #4 + 1819 .L162: + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1820 .loc 1 664 0 is_stmt 0 discriminator 24 + 1821 016a 3E4B ldr r3, .L209 + 1822 016c 5A60 str r2, [r3, #4] + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1823 .loc 1 667 0 is_stmt 1 discriminator 24 + 1824 016e 2523 movs r3, #37 + 1825 0170 0522 movs r2, #5 + 1826 0172 E254 strb r2, [r4, r3] + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1827 .loc 1 669 0 discriminator 24 + 1828 0174 236B ldr r3, [r4, #48] + 1829 0176 002B cmp r3, #0 + 1830 0178 01D0 beq .L160 + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1831 .loc 1 672 0 + 1832 017a 2000 movs r0, r4 + 1833 017c 9847 blx r3 + 1834 .LVL93: + 1835 .L160: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1836 .loc 1 678 0 + 1837 017e 394B ldr r3, .L209 + 1838 0180 1A68 ldr r2, [r3] + 1839 0182 2368 ldr r3, [r4] + 1840 0184 3849 ldr r1, .L209+4 + 1841 0186 8B42 cmp r3, r1 + 1842 0188 1FD0 beq .L191 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1843 .loc 1 678 0 is_stmt 0 discriminator 1 + 1844 018a 3849 ldr r1, .L209+8 + 1845 018c 8B42 cmp r3, r1 + 1846 018e 3FD0 beq .L192 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1847 .loc 1 678 0 discriminator 3 + 1848 0190 3749 ldr r1, .L209+12 + 1849 0192 8B42 cmp r3, r1 + 1850 0194 3ED0 beq .L193 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1851 .loc 1 678 0 discriminator 5 + 1852 0196 3749 ldr r1, .L209+16 + 1853 0198 8B42 cmp r3, r1 + 1854 019a 3ED0 beq .L194 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1855 .loc 1 678 0 discriminator 7 + 1856 019c 3649 ldr r1, .L209+20 + 1857 019e 8B42 cmp r3, r1 + 1858 01a0 3ED0 beq .L195 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + ARM GAS /tmp/ccJCJaQH.s page 51 + + + 1859 .loc 1 678 0 discriminator 9 + 1860 01a2 3649 ldr r1, .L209+24 + 1861 01a4 8B42 cmp r3, r1 + 1862 01a6 0DD0 beq .L207 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1863 .loc 1 678 0 + 1864 01a8 8021 movs r1, #128 + 1865 01aa 8904 lsls r1, r1, #18 + 1866 01ac 0EE0 b .L163 + 1867 .L186: + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1868 .loc 1 664 0 is_stmt 1 + 1869 01ae 4022 movs r2, #64 + 1870 01b0 DBE7 b .L162 + 1871 .L187: + 1872 01b2 8022 movs r2, #128 + 1873 01b4 D200 lsls r2, r2, #3 + 1874 01b6 D8E7 b .L162 + 1875 .L188: + 1876 01b8 8022 movs r2, #128 + 1877 01ba D201 lsls r2, r2, #7 + 1878 01bc D5E7 b .L162 + 1879 .L189: + 1880 01be 8022 movs r2, #128 + 1881 01c0 D202 lsls r2, r2, #11 + 1882 01c2 D2E7 b .L162 + 1883 .L207: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1884 .loc 1 678 0 + 1885 01c4 8021 movs r1, #128 + 1886 01c6 8903 lsls r1, r1, #14 + 1887 01c8 00E0 b .L163 + 1888 .L191: + 1889 01ca 0221 movs r1, #2 + 1890 .L163: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1891 .loc 1 678 0 is_stmt 0 discriminator 24 + 1892 01cc 1142 tst r1, r2 + 1893 01ce 3DD0 beq .L155 + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1894 .loc 1 680 0 is_stmt 1 + 1895 01d0 1A68 ldr r2, [r3] + 1896 01d2 9207 lsls r2, r2, #30 + 1897 01d4 3AD5 bpl .L155 + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1898 .loc 1 682 0 + 1899 01d6 1A68 ldr r2, [r3] + 1900 01d8 9206 lsls r2, r2, #26 + 1901 01da 03D4 bmi .L165 + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1902 .loc 1 685 0 + 1903 01dc 1A68 ldr r2, [r3] + 1904 01de 0221 movs r1, #2 + 1905 01e0 8A43 bics r2, r1 + 1906 01e2 1A60 str r2, [r3] + 1907 .L165: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + ARM GAS /tmp/ccJCJaQH.s page 52 + + + 1908 .loc 1 688 0 + 1909 01e4 2368 ldr r3, [r4] + 1910 01e6 204A ldr r2, .L209+4 + 1911 01e8 9342 cmp r3, r2 + 1912 01ea 1FD0 beq .L197 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1913 .loc 1 688 0 is_stmt 0 discriminator 1 + 1914 01ec 1F4A ldr r2, .L209+8 + 1915 01ee 9342 cmp r3, r2 + 1916 01f0 2DD0 beq .L198 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1917 .loc 1 688 0 discriminator 3 + 1918 01f2 1F4A ldr r2, .L209+12 + 1919 01f4 9342 cmp r3, r2 + 1920 01f6 2CD0 beq .L199 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1921 .loc 1 688 0 discriminator 5 + 1922 01f8 1E4A ldr r2, .L209+16 + 1923 01fa 9342 cmp r3, r2 + 1924 01fc 2CD0 beq .L200 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1925 .loc 1 688 0 discriminator 7 + 1926 01fe 1E4A ldr r2, .L209+20 + 1927 0200 9342 cmp r3, r2 + 1928 0202 2CD0 beq .L201 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1929 .loc 1 688 0 discriminator 9 + 1930 0204 1D4A ldr r2, .L209+24 + 1931 0206 9342 cmp r3, r2 + 1932 0208 0DD0 beq .L208 + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1933 .loc 1 688 0 + 1934 020a 8022 movs r2, #128 + 1935 020c 9204 lsls r2, r2, #18 + 1936 020e 0EE0 b .L166 + 1937 .L192: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1938 .loc 1 678 0 is_stmt 1 + 1939 0210 2021 movs r1, #32 + 1940 0212 DBE7 b .L163 + 1941 .L193: + 1942 0214 8021 movs r1, #128 + 1943 0216 8900 lsls r1, r1, #2 + 1944 0218 D8E7 b .L163 + 1945 .L194: + 1946 021a 8021 movs r1, #128 + 1947 021c 8901 lsls r1, r1, #6 + 1948 021e D5E7 b .L163 + 1949 .L195: + 1950 0220 8021 movs r1, #128 + 1951 0222 8902 lsls r1, r1, #10 + 1952 0224 D2E7 b .L163 + 1953 .L208: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1954 .loc 1 688 0 + 1955 0226 8022 movs r2, #128 + 1956 0228 9203 lsls r2, r2, #14 + ARM GAS /tmp/ccJCJaQH.s page 53 + + + 1957 022a 00E0 b .L166 + 1958 .L197: + 1959 022c 0222 movs r2, #2 + 1960 .L166: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1961 .loc 1 688 0 is_stmt 0 discriminator 24 + 1962 022e 0D4B ldr r3, .L209 + 1963 0230 5A60 str r2, [r3, #4] + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1964 .loc 1 691 0 is_stmt 1 discriminator 24 + 1965 0232 E36B ldr r3, [r4, #60] + 1966 0234 E363 str r3, [r4, #60] + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1967 .loc 1 694 0 discriminator 24 + 1968 0236 2523 movs r3, #37 + 1969 0238 0122 movs r2, #1 + 1970 023a E254 strb r2, [r4, r3] + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1971 .loc 1 697 0 discriminator 24 + 1972 023c 013B subs r3, r3, #1 + 1973 023e 0022 movs r2, #0 + 1974 0240 E254 strb r2, [r4, r3] + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** { + 1975 .loc 1 699 0 discriminator 24 + 1976 0242 E36A ldr r3, [r4, #44] + 1977 0244 002B cmp r3, #0 + 1978 0246 01D0 beq .L155 + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 1979 .loc 1 702 0 + 1980 0248 2000 movs r0, r4 + 1981 024a 9847 blx r3 + 1982 .LVL94: + 1983 .L155: + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1984 .loc 1 706 0 + 1985 @ sp needed + 1986 .LVL95: + 1987 024c 10BD pop {r4, pc} + 1988 .LVL96: + 1989 .L198: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 1990 .loc 1 688 0 + 1991 024e 2022 movs r2, #32 + 1992 0250 EDE7 b .L166 + 1993 .L199: + 1994 0252 8022 movs r2, #128 + 1995 0254 9200 lsls r2, r2, #2 + 1996 0256 EAE7 b .L166 + 1997 .L200: + 1998 0258 8022 movs r2, #128 + 1999 025a 9201 lsls r2, r2, #6 + 2000 025c E7E7 b .L166 + 2001 .L201: + 2002 025e 8022 movs r2, #128 + 2003 0260 9202 lsls r2, r2, #10 + 2004 0262 E4E7 b .L166 + 2005 .L210: + ARM GAS /tmp/ccJCJaQH.s page 54 + + + 2006 .align 2 + 2007 .L209: + 2008 0264 00000240 .word 1073872896 + 2009 0268 08000240 .word 1073872904 + 2010 026c 1C000240 .word 1073872924 + 2011 0270 30000240 .word 1073872944 + 2012 0274 44000240 .word 1073872964 + 2013 0278 58000240 .word 1073872984 + 2014 027c 6C000240 .word 1073873004 + 2015 .cfi_endproc + 2016 .LFE46: + 2018 .section .text.HAL_DMA_GetState,"ax",%progbits + 2019 .align 1 + 2020 .global HAL_DMA_GetState + 2021 .syntax unified + 2022 .code 16 + 2023 .thumb_func + 2024 .fpu softvfp + 2026 HAL_DMA_GetState: + 2027 .LFB47: + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return hdma->State; + 2028 .loc 1 735 0 + 2029 .cfi_startproc + 2030 @ args = 0, pretend = 0, frame = 0 + 2031 @ frame_needed = 0, uses_anonymous_args = 0 + 2032 @ link register save eliminated. + 2033 .LVL97: + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 2034 .loc 1 736 0 + 2035 0000 2523 movs r3, #37 + 2036 0002 C05C ldrb r0, [r0, r3] + 2037 .LVL98: + 2038 0004 C0B2 uxtb r0, r0 + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 2039 .loc 1 737 0 + 2040 @ sp needed + 2041 0006 7047 bx lr + 2042 .cfi_endproc + 2043 .LFE47: + 2045 .section .text.HAL_DMA_GetError,"ax",%progbits + 2046 .align 1 + 2047 .global HAL_DMA_GetError + 2048 .syntax unified + 2049 .code 16 + 2050 .thumb_func + 2051 .fpu softvfp + 2053 HAL_DMA_GetError: + 2054 .LFB48: + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** return hdma->ErrorCode; + 2055 .loc 1 746 0 + 2056 .cfi_startproc + 2057 @ args = 0, pretend = 0, frame = 0 + 2058 @ frame_needed = 0, uses_anonymous_args = 0 + 2059 @ link register save eliminated. + 2060 .LVL99: + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** } + 2061 .loc 1 747 0 + ARM GAS /tmp/ccJCJaQH.s page 55 + + + 2062 0000 C06B ldr r0, [r0, #60] + 2063 .LVL100: + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c **** + 2064 .loc 1 748 0 + 2065 @ sp needed + 2066 0002 7047 bx lr + 2067 .cfi_endproc + 2068 .LFE48: + 2070 .text + 2071 .Letext0: + 2072 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2073 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2074 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 2075 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 2076 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 2077 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 2078 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 2079 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 2080 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 2081 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 2082 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 2083 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccJCJaQH.s page 56 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_dma.c + /tmp/ccJCJaQH.s:16 .text.HAL_DMA_Init:0000000000000000 $t + /tmp/ccJCJaQH.s:23 .text.HAL_DMA_Init:0000000000000000 HAL_DMA_Init + /tmp/ccJCJaQH.s:245 .text.HAL_DMA_Init:0000000000000114 $d + /tmp/ccJCJaQH.s:263 .text.HAL_DMA_DeInit:0000000000000000 $t + /tmp/ccJCJaQH.s:270 .text.HAL_DMA_DeInit:0000000000000000 HAL_DMA_DeInit + /tmp/ccJCJaQH.s:650 .text.HAL_DMA_DeInit:00000000000001fc $d + /tmp/ccJCJaQH.s:668 .text.HAL_DMA_Start:0000000000000000 $t + /tmp/ccJCJaQH.s:675 .text.HAL_DMA_Start:0000000000000000 HAL_DMA_Start + /tmp/ccJCJaQH.s:768 .text.HAL_DMA_Start_IT:0000000000000000 $t + /tmp/ccJCJaQH.s:775 .text.HAL_DMA_Start_IT:0000000000000000 HAL_DMA_Start_IT + /tmp/ccJCJaQH.s:886 .text.HAL_DMA_Abort:0000000000000000 $t + /tmp/ccJCJaQH.s:893 .text.HAL_DMA_Abort:0000000000000000 HAL_DMA_Abort + /tmp/ccJCJaQH.s:971 .text.HAL_DMA_Abort_IT:0000000000000000 $t + /tmp/ccJCJaQH.s:978 .text.HAL_DMA_Abort_IT:0000000000000000 HAL_DMA_Abort_IT + /tmp/ccJCJaQH.s:1103 .text.HAL_DMA_Abort_IT:0000000000000090 $d + /tmp/ccJCJaQH.s:1114 .text.HAL_DMA_PollForTransfer:0000000000000000 $t + /tmp/ccJCJaQH.s:1121 .text.HAL_DMA_PollForTransfer:0000000000000000 HAL_DMA_PollForTransfer + /tmp/ccJCJaQH.s:1533 .text.HAL_DMA_PollForTransfer:0000000000000210 $d + /tmp/ccJCJaQH.s:1544 .text.HAL_DMA_IRQHandler:0000000000000000 $t + /tmp/ccJCJaQH.s:1551 .text.HAL_DMA_IRQHandler:0000000000000000 HAL_DMA_IRQHandler + /tmp/ccJCJaQH.s:2008 .text.HAL_DMA_IRQHandler:0000000000000264 $d + /tmp/ccJCJaQH.s:2019 .text.HAL_DMA_GetState:0000000000000000 $t + /tmp/ccJCJaQH.s:2026 .text.HAL_DMA_GetState:0000000000000000 HAL_DMA_GetState + /tmp/ccJCJaQH.s:2046 .text.HAL_DMA_GetError:0000000000000000 $t + /tmp/ccJCJaQH.s:2053 .text.HAL_DMA_GetError:0000000000000000 HAL_DMA_GetError + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/build/stm32l0xx_hal_firewall.d b/build/stm32l0xx_hal_firewall.d new file mode 100644 index 0000000..b9368ed --- /dev/null +++ b/build/stm32l0xx_hal_firewall.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_firewall.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_firewall.lst b/build/stm32l0xx_hal_firewall.lst new file mode 100644 index 0000000..9cb36d1 --- /dev/null +++ b/build/stm32l0xx_hal_firewall.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccviRKHs.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_firewall.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccviRKHs.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_firewall.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_flash.d b/build/stm32l0xx_hal_flash.d new file mode 100644 index 0000000..b728878 --- /dev/null +++ b/build/stm32l0xx_hal_flash.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_flash.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_flash.lst b/build/stm32l0xx_hal_flash.lst new file mode 100644 index 0000000..4e43c4c --- /dev/null +++ b/build/stm32l0xx_hal_flash.lst @@ -0,0 +1,1990 @@ +ARM GAS /tmp/ccqRvrNg.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_flash.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.FLASH_SetErrorCode,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 FLASH_SetErrorCode: + 23 .LFB51: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @file stm32l0xx_hal_flash.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief FLASH HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * functionalities of the internal FLASH memory: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + Program operations functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + Memory Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + Peripheral State functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @verbatim + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ============================================================================== + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### FLASH peripheral features ##### + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ============================================================================== + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** to the Flash memory. It implements the erase and program Flash memory operations + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** and the read and write protection mechanisms. + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] The Flash memory interface accelerates code execution with a system of instruction + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** prefetch. + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] The FLASH main features are: + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Flash memory read operations + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Flash memory program/erase operations + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Read / write protections + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Prefetch on I-Code + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Option Bytes programming + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### How to use this driver ##### + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ============================================================================== + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** This driver provides functions and macros to configure and program the FLASH + ARM GAS /tmp/ccqRvrNg.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** memory of all STM32L0xx devices. + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) FLASH Memory I/O Programming functions: this group includes all needed + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** functions to erase and program the main memory: + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Lock and Unlock the FLASH interface + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Erase function: Erase page + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Program functions: Fast Word and Half Page(should be + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** executed from internal SRAM). + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) DATA EEPROM Programming functions: this group includes all + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** needed functions to erase and program the DATA EEPROM memory: + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Lock and Unlock the DATA EEPROM interface. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** Double Word (should be executed from internal SRAM). + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Program functions: Fast Program Byte, Fast Program Half-Word, + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** FastProgramWord, Program Byte, Program Half-Word, + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** Program Word and Program Double-Word (should be executed + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** from internal SRAM). + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) FLASH Option Bytes Programming functions: this group includes all needed + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** functions to manage the Option Bytes: + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Lock and Unlock the Option Bytes + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Set/Reset the write protection + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Set the Read protection Level + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Program the user Option Bytes + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Launch the Option Bytes loader + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Set/Get the Read protection Level. + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Set/Get the BOR level. + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Get the Write protection. + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Get the user option bytes. + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Interrupts and flags management functions : this group + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** includes all needed functions to: + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Handle FLASH interrupts + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Wait for last FLASH operation according to its status + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Get error flag status + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) FLASH Interface configuration functions: this group includes + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** the management of following features: + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Enable/Disable the RUN PowerDown mode. + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Enable/Disable the SLEEP PowerDown mode. + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) FLASH Peripheral State methods: this group includes + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** the management of following features: + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Wait for the FLASH operation + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Get the specific FLASH error flag + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] In addition to these function, this driver includes a set of macros allowing + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** to handle the following operations: + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Set/Get the latency + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Enable/Disable the prefetch buffer + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Enable/Disable the preread buffer + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Enable/Disable the Flash power-down + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Enable/Disable the FLASH interrupts + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) Monitor the FLASH flags status + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + ARM GAS /tmp/ccqRvrNg.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### Programming operation functions ##### + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** =============================================================================== + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** This subsection provides a set of functions allowing to manage the FLASH + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** program operations. + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] The FLASH Memory Programming functions, includes the following functions: + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_Unlock(void); + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_Lock(void); + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] Any operation of erase or program should follow these steps: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** program memory access. + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the desired function to erase page or program data. + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (recommended to protect the FLASH memory against possible unwanted operation). + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### Option Bytes Programming functions ##### + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ============================================================================== + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] The FLASH_Option Bytes Programming_functions, includes the following functions: + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_OB_Unlock(void); + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_OB_Lock(void); + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASH_OB_Launch(void); + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] Any operation of erase or program should follow these steps: + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** register access. + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the following functions to program the desired option bytes. + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Once all needed option bytes to be programmed are correctly written, call the + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommen + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** to protect the option Bytes against possible unwanted operations). + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] Proprietary code Read Out Protection (PcROP): + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) The PcROP sector is selected by using the same option bytes as the Write + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** protection. As a result, these 2 options are exclusive each other. + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @endverbatim + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ****************************************************************************** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @attention + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * Redistribution and use in source and binary forms, with or without modification, + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * are permitted provided that the following conditions are met: + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * 1. Redistributions of source code must retain the above copyright notice, + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * this list of conditions and the following disclaimer. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/ccqRvrNg.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * and/or other materials provided with the distribution. + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * may be used to endorse or promote products derived from this software + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * without specific prior written permission. + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ****************************************************************************** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** #include "stm32l0xx_hal.h" + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @addtogroup STM32L0xx_HAL_Driver + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH FLASH + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief FLASH HAL module driver + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Private_Constants FLASH Private Constants + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Private macro ---------------------------- ---------------------------------*/ + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Private_Macros FLASH Private Macros + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Private_Variables FLASH Private Variables + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Variables used for Erase pages under interruption*/ + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash; + ARM GAS /tmp/ccqRvrNg.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Private_Functions FLASH Private Functions + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** static void FLASH_SetErrorCode(void); + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** extern void FLASH_PageErase(uint32_t PageAddress); + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Exported functions ---------------------------------------------------------*/ + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Programming operation functions + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @verbatim + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @endverbatim + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Program word at a specified address + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @note To correctly run this function, the HAL_FLASH_Unlock() function + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * must be called before. + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * Call the HAL_FLASH_Lock() to disable the flash memory access + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * (recommended to protect the FLASH memory against possible unwanted operation). + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Process Locked */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check the parameters */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(status == HAL_OK) + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + ARM GAS /tmp/ccqRvrNg.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clean the error context */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /*Program word (32-bit) at a specified address.*/ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** *(__IO uint32_t *)Address = Data; + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Process Unlocked */ + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return status; + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Program word at a specified address with interrupt enabled. + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Process Locked */ + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check the parameters */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Address = Address; + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clean the error context */ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Program word (32-bit) at a specified address. */ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** *(__IO uint32_t *)Address = Data; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return status; + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief This function handles FLASH interrupt request. + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval None + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + ARM GAS /tmp/ccqRvrNg.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** uint32_t addresstmp = 0; + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check FLASH operation error flags */ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * as expected. If the user run an application using the first + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * cut of the STM32L031xx device or the first cut of the STM32L041xx + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * device, the check on the FLASH_FLAG_OPTVERR bit should be ignored. + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * Note :The revId of the device can be retrieved via the HAL_GetREVID() + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * function. + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Return the faulty sector */ + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** addresstmp = pFlash.Page; + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Page = 0xFFFFFFFFU; + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** else + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Return the faulty address */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** addresstmp = pFlash.Address; + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Save the Error code */ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** FLASH_SetErrorCode(); + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(addresstmp); + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Stop the procedure ongoing */ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Process can continue only if no error detected */ + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + ARM GAS /tmp/ccqRvrNg.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Nb of pages to erased can be decreased */ + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.NbPagesToErase--; + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check if there are still pages to erase */ + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(pFlash.NbPagesToErase != 0U) + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** addresstmp = pFlash.Page; + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /*Increment sector number*/ + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** addresstmp = pFlash.Page + FLASH_PAGE_SIZE; + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Page = addresstmp; + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* If the erase operation is completed, disable the ERASE Bit */ + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** FLASH_PageErase(addresstmp); + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** else + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* No more pages to Erase, user callback can be called. */ + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Reset Sector and stop Erase pages procedure */ + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Page = addresstmp = 0xFFFFFFFFU; + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** else + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* If the program operation is completed, disable the PROG Bit */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Program ended. Return the selected address */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Reset Address and stop Program procedure */ + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Address = 0xFFFFFFFFU; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Operation is completed, disable the PROG and ERASE */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG)); + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Disable End of FLASH Operation and Error source interrupts */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Process Unlocked */ + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + ARM GAS /tmp/ccqRvrNg.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * - Pages Erase: Address of the page which has been erased + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * - Program: Address which was selected for data program + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval none + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** UNUSED(ReturnValue); + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief FLASH operation error interrupt callback + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * - Pages Erase: Address of the page which returned an error + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * - Program: Address which was selected for data program + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval none + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** UNUSED(ReturnValue); + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief management functions + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @verbatim + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** =============================================================================== + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### Peripheral Control functions ##### + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** =============================================================================== + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** memory operations. + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @endverbatim + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + ARM GAS /tmp/ccqRvrNg.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Unlock the FLASH control register access + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Unlocking FLASH_PECR register access*/ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Unlocking the program memory access */ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** else + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_ERROR; + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_OK; + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Locks the FLASH control register access + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the PRGLOCK Bit to lock the FLASH Registers access */ + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_OK; + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Unlock the FLASH Option Control Registers access. + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Unlocking FLASH_PECR register access*/ + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Unlocking FLASH_PECR register access*/ + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Unlocking the option bytes block access */ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + ARM GAS /tmp/ccqRvrNg.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** else + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_ERROR; + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_OK; + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Lock the FLASH Option Control Registers access. + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the option bytes block access */ + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_OK; + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Launch the option byte loading. + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @note This function will reset automatically the MCU. + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the OBL_Launch bit to launch the option byte loading */ + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Peripheral errors functions + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @verbatim + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** =============================================================================== + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** =============================================================================== + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** [..] + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** This subsection permit to get in run-time errors of the FLASH peripheral. + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** @endverbatim + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval FLASH_ErrorCode The returned value can be: + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @ref FLASH_Error_Codes + ARM GAS /tmp/ccqRvrNg.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return pFlash.ErrorCode; + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @} + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @{ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval HAL Status + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flag will be set */ + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if (Timeout != HAL_MAX_DELAY) + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_TIMEOUT; + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + ARM GAS /tmp/ccqRvrNg.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /*Save the error code*/ + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * as expected. If the user run an application using the first + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * cut of the STM32L031xx device or the first cut of the STM32L041xx + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * device, this error should be ignored. The revId of the device + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * can be retrieved via the HAL_GetREVID() function. + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** FLASH_SetErrorCode(); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_ERROR; + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* There is no error flag set */ + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_OK; + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /** + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @brief Set the specific FLASH error flag. + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * @retval None + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** static void FLASH_SetErrorCode(void) + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 25 .loc 1 686 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** uint32_t flags = 0; + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + 31 .loc 1 689 0 + 32 0000 2A4B ldr r3, .L10 + 33 0002 9B69 ldr r3, [r3, #24] + 34 0004 DB05 lsls r3, r3, #23 + 35 0006 4FD5 bpl .L9 + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 36 .loc 1 691 0 + 37 0008 294A ldr r2, .L10+4 + 38 000a 5369 ldr r3, [r2, #20] + 39 000c 0221 movs r1, #2 + 40 000e 0B43 orrs r3, r1 + 41 0010 5361 str r3, [r2, #20] + 42 .LVL1: + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_WRPERR; + 43 .loc 1 692 0 + 44 0012 8023 movs r3, #128 + 45 0014 5B00 lsls r3, r3, #1 + 46 .LVL2: + 47 .L2: + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + 48 .loc 1 694 0 + ARM GAS /tmp/ccqRvrNg.s page 14 + + + 49 0016 254A ldr r2, .L10 + 50 0018 9269 ldr r2, [r2, #24] + 51 001a 9205 lsls r2, r2, #22 + 52 001c 07D5 bpl .L3 + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + 53 .loc 1 696 0 + 54 001e 2449 ldr r1, .L10+4 + 55 0020 4A69 ldr r2, [r1, #20] + 56 0022 0120 movs r0, #1 + 57 0024 0243 orrs r2, r0 + 58 0026 4A61 str r2, [r1, #20] + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_PGAERR; + 59 .loc 1 697 0 + 60 0028 8022 movs r2, #128 + 61 002a 9200 lsls r2, r2, #2 + 62 002c 1343 orrs r3, r2 + 63 .LVL3: + 64 .L3: + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) + 65 .loc 1 699 0 + 66 002e 1F4A ldr r2, .L10 + 67 0030 9269 ldr r2, [r2, #24] + 68 0032 5205 lsls r2, r2, #21 + 69 0034 07D5 bpl .L4 + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; + 70 .loc 1 701 0 + 71 0036 1E49 ldr r1, .L10+4 + 72 0038 4A69 ldr r2, [r1, #20] + 73 003a 0820 movs r0, #8 + 74 003c 0243 orrs r2, r0 + 75 003e 4A61 str r2, [r1, #20] + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_SIZERR; + 76 .loc 1 702 0 + 77 0040 8022 movs r2, #128 + 78 0042 D200 lsls r2, r2, #3 + 79 0044 1343 orrs r3, r2 + 80 .LVL4: + 81 .L4: + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + 82 .loc 1 704 0 + 83 0046 194A ldr r2, .L10 + 84 0048 9269 ldr r2, [r2, #24] + 85 004a 1205 lsls r2, r2, #20 + 86 004c 07D5 bpl .L5 + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * as expected. If the user run an application using the first + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * cut of the STM32L031xx device or the first cut of the STM32L041xx + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * device, this error should be ignored. The revId of the device + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * can be retrieved via the HAL_GetREVID() function. + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** * + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** */ + ARM GAS /tmp/ccqRvrNg.s page 15 + + + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + 87 .loc 1 714 0 + 88 004e 1849 ldr r1, .L10+4 + 89 0050 4A69 ldr r2, [r1, #20] + 90 0052 0420 movs r0, #4 + 91 0054 0243 orrs r2, r0 + 92 0056 4A61 str r2, [r1, #20] + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_OPTVERR; + 93 .loc 1 715 0 + 94 0058 8022 movs r2, #128 + 95 005a 1201 lsls r2, r2, #4 + 96 005c 1343 orrs r3, r2 + 97 .LVL5: + 98 .L5: + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + 99 .loc 1 718 0 + 100 005e 134A ldr r2, .L10 + 101 0060 9269 ldr r2, [r2, #24] + 102 0062 9204 lsls r2, r2, #18 + 103 0064 07D5 bpl .L6 + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + 104 .loc 1 720 0 + 105 0066 1249 ldr r1, .L10+4 + 106 0068 4A69 ldr r2, [r1, #20] + 107 006a 1020 movs r0, #16 + 108 006c 0243 orrs r2, r0 + 109 006e 4A61 str r2, [r1, #20] + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_RDERR; + 110 .loc 1 721 0 + 111 0070 8022 movs r2, #128 + 112 0072 9201 lsls r2, r2, #6 + 113 0074 1343 orrs r3, r2 + 114 .LVL6: + 115 .L6: + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) + 116 .loc 1 723 0 + 117 0076 0D4A ldr r2, .L10 + 118 0078 9269 ldr r2, [r2, #24] + 119 007a 9203 lsls r2, r2, #14 + 120 007c 05D5 bpl .L7 + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; + 121 .loc 1 725 0 + 122 007e 0C48 ldr r0, .L10+4 + 123 0080 4269 ldr r2, [r0, #20] + 124 0082 2021 movs r1, #32 + 125 0084 0A43 orrs r2, r1 + 126 0086 4261 str r2, [r0, #20] + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= HAL_FLASH_ERROR_FWWERR; + 127 .loc 1 726 0 + 128 0088 0B43 orrs r3, r1 + 129 .LVL7: + 130 .L7: + ARM GAS /tmp/ccqRvrNg.s page 16 + + + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) + 131 .loc 1 728 0 + 132 008a 084A ldr r2, .L10 + 133 008c 9269 ldr r2, [r2, #24] + 134 008e D203 lsls r2, r2, #15 + 135 0090 07D5 bpl .L8 + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; + 136 .loc 1 730 0 + 137 0092 0749 ldr r1, .L10+4 + 138 0094 4A69 ldr r2, [r1, #20] + 139 0096 4020 movs r0, #64 + 140 0098 0243 orrs r2, r0 + 141 009a 4A61 str r2, [r1, #20] + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** flags |= FLASH_FLAG_NOTZEROERR; + 142 .loc 1 731 0 + 143 009c 8022 movs r2, #128 + 144 009e 5202 lsls r2, r2, #9 + 145 00a0 1343 orrs r3, r2 + 146 .LVL8: + 147 .L8: + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clear FLASH error pending bits */ + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(flags); + 148 .loc 1 735 0 + 149 00a2 024A ldr r2, .L10 + 150 00a4 9361 str r3, [r2, #24] + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 151 .loc 1 736 0 + 152 @ sp needed + 153 00a6 7047 bx lr + 154 .LVL9: + 155 .L9: + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 156 .loc 1 687 0 + 157 00a8 0023 movs r3, #0 + 158 00aa B4E7 b .L2 + 159 .L11: + 160 .align 2 + 161 .L10: + 162 00ac 00200240 .word 1073881088 + 163 00b0 00000000 .word .LANCHOR0 + 164 .cfi_endproc + 165 .LFE51: + 167 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 168 .align 1 + 169 .global HAL_FLASH_Program_IT + 170 .syntax unified + 171 .code 16 + 172 .thumb_func + 173 .fpu softvfp + 175 HAL_FLASH_Program_IT: + 176 .LFB40: + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 177 .loc 1 290 0 + ARM GAS /tmp/ccqRvrNg.s page 17 + + + 178 .cfi_startproc + 179 @ args = 0, pretend = 0, frame = 0 + 180 @ frame_needed = 0, uses_anonymous_args = 0 + 181 .LVL10: + 182 0000 70B5 push {r4, r5, r6, lr} + 183 .LCFI0: + 184 .cfi_def_cfa_offset 16 + 185 .cfi_offset 4, -16 + 186 .cfi_offset 5, -12 + 187 .cfi_offset 6, -8 + 188 .cfi_offset 14, -4 + 189 .LVL11: + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 190 .loc 1 294 0 + 191 0002 0D4B ldr r3, .L17 + 192 0004 1B7C ldrb r3, [r3, #16] + 193 0006 012B cmp r3, #1 + 194 0008 14D0 beq .L14 + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 195 .loc 1 294 0 is_stmt 0 discriminator 2 + 196 000a 0B4B ldr r3, .L17 + 197 000c 0124 movs r4, #1 + 198 000e 1C74 strb r4, [r3, #16] + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 199 .loc 1 301 0 is_stmt 1 discriminator 2 + 200 0010 0A4D ldr r5, .L17+4 + 201 0012 6E68 ldr r6, [r5, #4] + 202 0014 C024 movs r4, #192 + 203 0016 A402 lsls r4, r4, #10 + 204 0018 3443 orrs r4, r6 + 205 001a 6C60 str r4, [r5, #4] + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + 206 .loc 1 303 0 discriminator 2 + 207 001c 9960 str r1, [r3, #8] + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Clean the error context */ + 208 .loc 1 304 0 discriminator 2 + 209 001e 0224 movs r4, #2 + 210 0020 1C70 strb r4, [r3] + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 211 .loc 1 306 0 discriminator 2 + 212 0022 0024 movs r4, #0 + 213 0024 5C61 str r4, [r3, #20] + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 214 .loc 1 308 0 discriminator 2 + 215 0026 0228 cmp r0, #2 + 216 0028 01D0 beq .L16 + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 217 .loc 1 313 0 + 218 002a 0020 movs r0, #0 + 219 .LVL12: + 220 .L13: + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 221 .loc 1 314 0 + 222 @ sp needed + 223 002c 70BD pop {r4, r5, r6, pc} + 224 .LVL13: + 225 .L16: + ARM GAS /tmp/ccqRvrNg.s page 18 + + + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 226 .loc 1 311 0 + 227 002e 0A60 str r2, [r1] + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 228 .loc 1 313 0 + 229 0030 0020 movs r0, #0 + 230 .LVL14: + 231 0032 FBE7 b .L13 + 232 .LVL15: + 233 .L14: + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 234 .loc 1 294 0 + 235 0034 0220 movs r0, #2 + 236 .LVL16: + 237 0036 F9E7 b .L13 + 238 .L18: + 239 .align 2 + 240 .L17: + 241 0038 00000000 .word .LANCHOR0 + 242 003c 00200240 .word 1073881088 + 243 .cfi_endproc + 244 .LFE40: + 246 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 247 .align 1 + 248 .weak HAL_FLASH_EndOfOperationCallback + 249 .syntax unified + 250 .code 16 + 251 .thumb_func + 252 .fpu softvfp + 254 HAL_FLASH_EndOfOperationCallback: + 255 .LFB42: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 256 .loc 1 445 0 + 257 .cfi_startproc + 258 @ args = 0, pretend = 0, frame = 0 + 259 @ frame_needed = 0, uses_anonymous_args = 0 + 260 @ link register save eliminated. + 261 .LVL17: + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 262 .loc 1 452 0 + 263 @ sp needed + 264 0000 7047 bx lr + 265 .cfi_endproc + 266 .LFE42: + 268 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 269 .align 1 + 270 .weak HAL_FLASH_OperationErrorCallback + 271 .syntax unified + 272 .code 16 + 273 .thumb_func + 274 .fpu softvfp + 276 HAL_FLASH_OperationErrorCallback: + 277 .LFB43: + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 278 .loc 1 462 0 + 279 .cfi_startproc + 280 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccqRvrNg.s page 19 + + + 281 @ frame_needed = 0, uses_anonymous_args = 0 + 282 @ link register save eliminated. + 283 .LVL18: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 284 .loc 1 469 0 + 285 @ sp needed + 286 0000 7047 bx lr + 287 .cfi_endproc + 288 .LFE43: + 290 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 291 .align 1 + 292 .global HAL_FLASH_IRQHandler + 293 .syntax unified + 294 .code 16 + 295 .thumb_func + 296 .fpu softvfp + 298 HAL_FLASH_IRQHandler: + 299 .LFB41: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** uint32_t addresstmp = 0; + 300 .loc 1 321 0 + 301 .cfi_startproc + 302 @ args = 0, pretend = 0, frame = 0 + 303 @ frame_needed = 0, uses_anonymous_args = 0 + 304 0000 10B5 push {r4, lr} + 305 .LCFI1: + 306 .cfi_def_cfa_offset 8 + 307 .cfi_offset 4, -8 + 308 .cfi_offset 14, -4 + 309 .LVL19: + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 310 .loc 1 337 0 + 311 0002 3E4B ldr r3, .L31 + 312 0004 9B69 ldr r3, [r3, #24] + 313 0006 DB05 lsls r3, r3, #23 + 314 0008 17D4 bmi .L22 + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 315 .loc 1 338 0 discriminator 1 + 316 000a 3C4B ldr r3, .L31 + 317 000c 9B69 ldr r3, [r3, #24] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 318 .loc 1 337 0 discriminator 1 + 319 000e 9B05 lsls r3, r3, #22 + 320 0010 13D4 bmi .L22 + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 321 .loc 1 339 0 + 322 0012 3A4B ldr r3, .L31 + 323 0014 9B69 ldr r3, [r3, #24] + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 324 .loc 1 338 0 + 325 0016 5B05 lsls r3, r3, #21 + 326 0018 0FD4 bmi .L22 + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 327 .loc 1 340 0 + 328 001a 384B ldr r3, .L31 + 329 001c 9B69 ldr r3, [r3, #24] + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 330 .loc 1 339 0 + ARM GAS /tmp/ccqRvrNg.s page 20 + + + 331 001e 1B05 lsls r3, r3, #20 + 332 0020 0BD4 bmi .L22 + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 333 .loc 1 341 0 + 334 0022 364B ldr r3, .L31 + 335 0024 9B69 ldr r3, [r3, #24] + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 336 .loc 1 340 0 + 337 0026 9B04 lsls r3, r3, #18 + 338 0028 07D4 bmi .L22 + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 339 .loc 1 342 0 + 340 002a 344B ldr r3, .L31 + 341 002c 9B69 ldr r3, [r3, #24] + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 342 .loc 1 341 0 + 343 002e 9B03 lsls r3, r3, #14 + 344 0030 03D4 bmi .L22 + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 345 .loc 1 343 0 + 346 0032 324B ldr r3, .L31 + 347 0034 9B69 ldr r3, [r3, #24] + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 348 .loc 1 342 0 + 349 0036 DB03 lsls r3, r3, #15 + 350 0038 0DD5 bpl .L23 + 351 .L22: + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 352 .loc 1 345 0 + 353 003a 314B ldr r3, .L31+4 + 354 003c 1B78 ldrb r3, [r3] + 355 003e 012B cmp r3, #1 + 356 0040 2ED0 beq .L30 + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 357 .loc 1 354 0 + 358 0042 2F4B ldr r3, .L31+4 + 359 0044 9C68 ldr r4, [r3, #8] + 360 .LVL20: + 361 .L25: + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 362 .loc 1 357 0 + 363 0046 FFF7FEFF bl FLASH_SetErrorCode + 364 .LVL21: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 365 .loc 1 360 0 + 366 004a 2000 movs r0, r4 + 367 004c FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 368 .LVL22: + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 369 .loc 1 363 0 + 370 0050 2B4B ldr r3, .L31+4 + 371 0052 0022 movs r2, #0 + 372 0054 1A70 strb r2, [r3] + 373 .LVL23: + 374 .L23: + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 375 .loc 1 367 0 + ARM GAS /tmp/ccqRvrNg.s page 21 + + + 376 0056 294B ldr r3, .L31 + 377 0058 9B69 ldr r3, [r3, #24] + 378 005a 9B07 lsls r3, r3, #30 + 379 005c 3DD5 bpl .L26 + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 380 .loc 1 370 0 + 381 005e 274B ldr r3, .L31 + 382 0060 0222 movs r2, #2 + 383 0062 9A61 str r2, [r3, #24] + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 384 .loc 1 373 0 + 385 0064 264B ldr r3, .L31+4 + 386 0066 1B78 ldrb r3, [r3] + 387 0068 002B cmp r3, #0 + 388 006a 36D0 beq .L26 + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 389 .loc 1 375 0 + 390 006c 244B ldr r3, .L31+4 + 391 006e 1B78 ldrb r3, [r3] + 392 0070 012B cmp r3, #1 + 393 0072 24D1 bne .L27 + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 394 .loc 1 378 0 + 395 0074 224B ldr r3, .L31+4 + 396 0076 5A68 ldr r2, [r3, #4] + 397 0078 013A subs r2, r2, #1 + 398 007a 5A60 str r2, [r3, #4] + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 399 .loc 1 381 0 + 400 007c 5B68 ldr r3, [r3, #4] + 401 007e 002B cmp r3, #0 + 402 0080 14D0 beq .L28 + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 403 .loc 1 383 0 + 404 0082 1F4C ldr r4, .L31+4 + 405 0084 E068 ldr r0, [r4, #12] + 406 .LVL24: + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 407 .loc 1 385 0 + 408 0086 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 409 .LVL25: + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Page = addresstmp; + 410 .loc 1 388 0 + 411 008a E068 ldr r0, [r4, #12] + 412 008c 8030 adds r0, r0, #128 + 413 .LVL26: + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 414 .loc 1 389 0 + 415 008e E060 str r0, [r4, #12] + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 416 .loc 1 392 0 + 417 0090 1A4A ldr r2, .L31 + 418 0092 5368 ldr r3, [r2, #4] + 419 0094 1B49 ldr r1, .L31+8 + 420 0096 0B40 ands r3, r1 + 421 0098 5360 str r3, [r2, #4] + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + ARM GAS /tmp/ccqRvrNg.s page 22 + + + 422 .loc 1 394 0 + 423 009a FFF7FEFF bl FLASH_PageErase + 424 .LVL27: + 425 009e 1CE0 b .L26 + 426 .LVL28: + 427 .L30: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.Page = 0xFFFFFFFFU; + 428 .loc 1 348 0 + 429 00a0 174B ldr r3, .L31+4 + 430 00a2 DC68 ldr r4, [r3, #12] + 431 .LVL29: + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 432 .loc 1 349 0 + 433 00a4 0122 movs r2, #1 + 434 00a6 5242 rsbs r2, r2, #0 + 435 00a8 DA60 str r2, [r3, #12] + 436 00aa CCE7 b .L25 + 437 .LVL30: + 438 .L28: + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 439 .loc 1 400 0 + 440 00ac 144B ldr r3, .L31+4 + 441 00ae 0120 movs r0, #1 + 442 00b0 4042 rsbs r0, r0, #0 + 443 00b2 D860 str r0, [r3, #12] + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 444 .loc 1 401 0 + 445 00b4 0022 movs r2, #0 + 446 00b6 1A70 strb r2, [r3] + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 447 .loc 1 403 0 + 448 00b8 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 449 .LVL31: + 450 00bc 0DE0 b .L26 + 451 .LVL32: + 452 .L27: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 453 .loc 1 409 0 + 454 00be 0F4A ldr r2, .L31 + 455 00c0 5368 ldr r3, [r2, #4] + 456 00c2 0821 movs r1, #8 + 457 00c4 8B43 bics r3, r1 + 458 00c6 5360 str r3, [r2, #4] + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 459 .loc 1 413 0 + 460 00c8 0D4C ldr r4, .L31+4 + 461 00ca A068 ldr r0, [r4, #8] + 462 00cc FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 463 .LVL33: + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 464 .loc 1 416 0 + 465 00d0 0123 movs r3, #1 + 466 00d2 5B42 rsbs r3, r3, #0 + 467 00d4 A360 str r3, [r4, #8] + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 468 .loc 1 417 0 + 469 00d6 0023 movs r3, #0 + ARM GAS /tmp/ccqRvrNg.s page 23 + + + 470 00d8 2370 strb r3, [r4] + 471 .L26: + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 472 .loc 1 423 0 + 473 00da 094B ldr r3, .L31+4 + 474 00dc 1B78 ldrb r3, [r3] + 475 00de 002B cmp r3, #0 + 476 00e0 0BD1 bne .L21 + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 477 .loc 1 426 0 + 478 00e2 064B ldr r3, .L31 + 479 00e4 5A68 ldr r2, [r3, #4] + 480 00e6 0849 ldr r1, .L31+12 + 481 00e8 0A40 ands r2, r1 + 482 00ea 5A60 str r2, [r3, #4] + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 483 .loc 1 429 0 + 484 00ec 5A68 ldr r2, [r3, #4] + 485 00ee 0749 ldr r1, .L31+16 + 486 00f0 0A40 ands r2, r1 + 487 00f2 5A60 str r2, [r3, #4] + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 488 .loc 1 432 0 + 489 00f4 024B ldr r3, .L31+4 + 490 00f6 0022 movs r2, #0 + 491 00f8 1A74 strb r2, [r3, #16] + 492 .L21: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 493 .loc 1 434 0 + 494 @ sp needed + 495 00fa 10BD pop {r4, pc} + 496 .L32: + 497 .align 2 + 498 .L31: + 499 00fc 00200240 .word 1073881088 + 500 0100 00000000 .word .LANCHOR0 + 501 0104 FFFDFFFF .word -513 + 502 0108 F7FDFFFF .word -521 + 503 010c FFFFFCFF .word -196609 + 504 .cfi_endproc + 505 .LFE41: + 507 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 508 .align 1 + 509 .global HAL_FLASH_Unlock + 510 .syntax unified + 511 .code 16 + 512 .thumb_func + 513 .fpu softvfp + 515 HAL_FLASH_Unlock: + 516 .LFB44: + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) + 517 .loc 1 495 0 + 518 .cfi_startproc + 519 @ args = 0, pretend = 0, frame = 0 + 520 @ frame_needed = 0, uses_anonymous_args = 0 + 521 @ link register save eliminated. + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + ARM GAS /tmp/ccqRvrNg.s page 24 + + + 522 .loc 1 496 0 + 523 0000 0A4B ldr r3, .L37 + 524 0002 5B68 ldr r3, [r3, #4] + 525 0004 9B07 lsls r3, r3, #30 + 526 0006 0FD5 bpl .L36 + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 527 .loc 1 499 0 + 528 0008 084B ldr r3, .L37 + 529 000a 5B68 ldr r3, [r3, #4] + 530 000c DB07 lsls r3, r3, #31 + 531 000e 04D5 bpl .L35 + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + 532 .loc 1 501 0 + 533 0010 064B ldr r3, .L37 + 534 0012 074A ldr r2, .L37+4 + 535 0014 DA60 str r2, [r3, #12] + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 536 .loc 1 502 0 + 537 0016 074A ldr r2, .L37+8 + 538 0018 DA60 str r2, [r3, #12] + 539 .L35: + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); + 540 .loc 1 506 0 + 541 001a 044B ldr r3, .L37 + 542 001c 064A ldr r2, .L37+12 + 543 001e 1A61 str r2, [r3, #16] + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 544 .loc 1 507 0 + 545 0020 064A ldr r2, .L37+16 + 546 0022 1A61 str r2, [r3, #16] + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 547 .loc 1 514 0 + 548 0024 0020 movs r0, #0 + 549 .L34: + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 550 .loc 1 515 0 + 551 @ sp needed + 552 0026 7047 bx lr + 553 .L36: + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 554 .loc 1 511 0 + 555 0028 0120 movs r0, #1 + 556 002a FCE7 b .L34 + 557 .L38: + 558 .align 2 + 559 .L37: + 560 002c 00200240 .word 1073881088 + 561 0030 EFCDAB89 .word -1985229329 + 562 0034 05040302 .word 33752069 + 563 0038 BFAE9D8C .word -1935823169 + 564 003c 16151413 .word 320083222 + 565 .cfi_endproc + 566 .LFE44: + 568 .section .text.HAL_FLASH_Lock,"ax",%progbits + 569 .align 1 + 570 .global HAL_FLASH_Lock + 571 .syntax unified + ARM GAS /tmp/ccqRvrNg.s page 25 + + + 572 .code 16 + 573 .thumb_func + 574 .fpu softvfp + 576 HAL_FLASH_Lock: + 577 .LFB45: + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the PRGLOCK Bit to lock the FLASH Registers access */ + 578 .loc 1 522 0 + 579 .cfi_startproc + 580 @ args = 0, pretend = 0, frame = 0 + 581 @ frame_needed = 0, uses_anonymous_args = 0 + 582 @ link register save eliminated. + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 583 .loc 1 524 0 + 584 0000 034A ldr r2, .L40 + 585 0002 5368 ldr r3, [r2, #4] + 586 0004 0221 movs r1, #2 + 587 0006 0B43 orrs r3, r1 + 588 0008 5360 str r3, [r2, #4] + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 589 .loc 1 527 0 + 590 000a 0020 movs r0, #0 + 591 @ sp needed + 592 000c 7047 bx lr + 593 .L41: + 594 000e C046 .align 2 + 595 .L40: + 596 0010 00200240 .word 1073881088 + 597 .cfi_endproc + 598 .LFE45: + 600 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 601 .align 1 + 602 .global HAL_FLASH_OB_Unlock + 603 .syntax unified + 604 .code 16 + 605 .thumb_func + 606 .fpu softvfp + 608 HAL_FLASH_OB_Unlock: + 609 .LFB46: + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) + 610 .loc 1 534 0 + 611 .cfi_startproc + 612 @ args = 0, pretend = 0, frame = 0 + 613 @ frame_needed = 0, uses_anonymous_args = 0 + 614 @ link register save eliminated. + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 615 .loc 1 535 0 + 616 0000 0A4B ldr r3, .L46 + 617 0002 5B68 ldr r3, [r3, #4] + 618 0004 5B07 lsls r3, r3, #29 + 619 0006 0FD5 bpl .L45 + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 620 .loc 1 538 0 + 621 0008 084B ldr r3, .L46 + 622 000a 5B68 ldr r3, [r3, #4] + 623 000c DB07 lsls r3, r3, #31 + 624 000e 04D5 bpl .L44 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + ARM GAS /tmp/ccqRvrNg.s page 26 + + + 625 .loc 1 541 0 + 626 0010 064B ldr r3, .L46 + 627 0012 074A ldr r2, .L46+4 + 628 0014 DA60 str r2, [r3, #12] + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 629 .loc 1 542 0 + 630 0016 074A ldr r2, .L46+8 + 631 0018 DA60 str r2, [r3, #12] + 632 .L44: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 633 .loc 1 546 0 + 634 001a 044B ldr r3, .L46 + 635 001c 064A ldr r2, .L46+12 + 636 001e 5A61 str r2, [r3, #20] + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 637 .loc 1 547 0 + 638 0020 064A ldr r2, .L46+16 + 639 0022 5A61 str r2, [r3, #20] + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 640 .loc 1 554 0 + 641 0024 0020 movs r0, #0 + 642 .L43: + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 643 .loc 1 555 0 + 644 @ sp needed + 645 0026 7047 bx lr + 646 .L45: + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 647 .loc 1 551 0 + 648 0028 0120 movs r0, #1 + 649 002a FCE7 b .L43 + 650 .L47: + 651 .align 2 + 652 .L46: + 653 002c 00200240 .word 1073881088 + 654 0030 EFCDAB89 .word -1985229329 + 655 0034 05040302 .word 33752069 + 656 0038 C8D9EAFB .word -68494904 + 657 003c 27262524 .word 606414375 + 658 .cfi_endproc + 659 .LFE46: + 661 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 662 .align 1 + 663 .global HAL_FLASH_OB_Lock + 664 .syntax unified + 665 .code 16 + 666 .thumb_func + 667 .fpu softvfp + 669 HAL_FLASH_OB_Lock: + 670 .LFB47: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the option bytes block access */ + 671 .loc 1 562 0 + 672 .cfi_startproc + 673 @ args = 0, pretend = 0, frame = 0 + 674 @ frame_needed = 0, uses_anonymous_args = 0 + 675 @ link register save eliminated. + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + ARM GAS /tmp/ccqRvrNg.s page 27 + + + 676 .loc 1 564 0 + 677 0000 034A ldr r2, .L49 + 678 0002 5368 ldr r3, [r2, #4] + 679 0004 0421 movs r1, #4 + 680 0006 0B43 orrs r3, r1 + 681 0008 5360 str r3, [r2, #4] + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 682 .loc 1 567 0 + 683 000a 0020 movs r0, #0 + 684 @ sp needed + 685 000c 7047 bx lr + 686 .L50: + 687 000e C046 .align 2 + 688 .L49: + 689 0010 00200240 .word 1073881088 + 690 .cfi_endproc + 691 .LFE47: + 693 .section .text.HAL_FLASH_GetError,"ax",%progbits + 694 .align 1 + 695 .global HAL_FLASH_GetError + 696 .syntax unified + 697 .code 16 + 698 .thumb_func + 699 .fpu softvfp + 701 HAL_FLASH_GetError: + 702 .LFB49: + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return pFlash.ErrorCode; + 703 .loc 1 607 0 + 704 .cfi_startproc + 705 @ args = 0, pretend = 0, frame = 0 + 706 @ frame_needed = 0, uses_anonymous_args = 0 + 707 @ link register save eliminated. + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 708 .loc 1 608 0 + 709 0000 014B ldr r3, .L52 + 710 0002 5869 ldr r0, [r3, #20] + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 711 .loc 1 609 0 + 712 @ sp needed + 713 0004 7047 bx lr + 714 .L53: + 715 0006 C046 .align 2 + 716 .L52: + 717 0008 00000000 .word .LANCHOR0 + 718 .cfi_endproc + 719 .LFE49: + 721 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 722 .align 1 + 723 .global FLASH_WaitForLastOperation + 724 .syntax unified + 725 .code 16 + 726 .thumb_func + 727 .fpu softvfp + 729 FLASH_WaitForLastOperation: + 730 .LFB50: + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 731 .loc 1 629 0 + ARM GAS /tmp/ccqRvrNg.s page 28 + + + 732 .cfi_startproc + 733 @ args = 0, pretend = 0, frame = 0 + 734 @ frame_needed = 0, uses_anonymous_args = 0 + 735 .LVL34: + 736 0000 70B5 push {r4, r5, r6, lr} + 737 .LCFI2: + 738 .cfi_def_cfa_offset 16 + 739 .cfi_offset 4, -16 + 740 .cfi_offset 5, -12 + 741 .cfi_offset 6, -8 + 742 .cfi_offset 14, -4 + 743 0002 0400 movs r4, r0 + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 744 .loc 1 634 0 + 745 0004 FFF7FEFF bl HAL_GetTick + 746 .LVL35: + 747 0008 0500 movs r5, r0 + 748 .LVL36: + 749 .L56: + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 750 .loc 1 636 0 + 751 000a 1D4B ldr r3, .L65 + 752 000c 9B69 ldr r3, [r3, #24] + 753 000e DB07 lsls r3, r3, #31 + 754 0010 0AD5 bpl .L64 + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 755 .loc 1 638 0 + 756 0012 631C adds r3, r4, #1 + 757 0014 F9D0 beq .L56 + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 758 .loc 1 640 0 + 759 0016 002C cmp r4, #0 + 760 0018 2DD0 beq .L61 + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 761 .loc 1 640 0 is_stmt 0 discriminator 1 + 762 001a FFF7FEFF bl HAL_GetTick + 763 .LVL37: + 764 001e 401B subs r0, r0, r5 + 765 0020 A042 cmp r0, r4 + 766 0022 F2D9 bls .L56 + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 767 .loc 1 642 0 is_stmt 1 + 768 0024 0320 movs r0, #3 + 769 0026 25E0 b .L57 + 770 .L64: + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 771 .loc 1 648 0 + 772 0028 154B ldr r3, .L65 + 773 002a 9B69 ldr r3, [r3, #24] + 774 002c 9B07 lsls r3, r3, #30 + 775 002e 02D5 bpl .L59 + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 776 .loc 1 651 0 + 777 0030 134B ldr r3, .L65 + 778 0032 0222 movs r2, #2 + 779 0034 9A61 str r2, [r3, #24] + 780 .L59: + ARM GAS /tmp/ccqRvrNg.s page 29 + + + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 781 .loc 1 654 0 + 782 0036 124B ldr r3, .L65 + 783 0038 9B69 ldr r3, [r3, #24] + 784 003a DB05 lsls r3, r3, #23 + 785 003c 17D4 bmi .L60 + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 786 .loc 1 655 0 discriminator 1 + 787 003e 104B ldr r3, .L65 + 788 0040 9B69 ldr r3, [r3, #24] + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 789 .loc 1 654 0 discriminator 1 + 790 0042 9B05 lsls r3, r3, #22 + 791 0044 13D4 bmi .L60 + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 792 .loc 1 656 0 + 793 0046 0E4B ldr r3, .L65 + 794 0048 9B69 ldr r3, [r3, #24] + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 795 .loc 1 655 0 + 796 004a 5B05 lsls r3, r3, #21 + 797 004c 0FD4 bmi .L60 + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 798 .loc 1 657 0 + 799 004e 0C4B ldr r3, .L65 + 800 0050 9B69 ldr r3, [r3, #24] + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 801 .loc 1 656 0 + 802 0052 1B05 lsls r3, r3, #20 + 803 0054 0BD4 bmi .L60 + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 804 .loc 1 658 0 + 805 0056 0A4B ldr r3, .L65 + 806 0058 9B69 ldr r3, [r3, #24] + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 807 .loc 1 657 0 + 808 005a 9B04 lsls r3, r3, #18 + 809 005c 07D4 bmi .L60 + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 810 .loc 1 659 0 + 811 005e 084B ldr r3, .L65 + 812 0060 9B69 ldr r3, [r3, #24] + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 813 .loc 1 658 0 + 814 0062 9B03 lsls r3, r3, #14 + 815 0064 03D4 bmi .L60 + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 816 .loc 1 660 0 + 817 0066 064B ldr r3, .L65 + 818 0068 9B69 ldr r3, [r3, #24] + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 819 .loc 1 659 0 + 820 006a DB03 lsls r3, r3, #15 + 821 006c 05D5 bpl .L63 + 822 .L60: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** return HAL_ERROR; + 823 .loc 1 672 0 + ARM GAS /tmp/ccqRvrNg.s page 30 + + + 824 006e FFF7FEFF bl FLASH_SetErrorCode + 825 .LVL38: + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 826 .loc 1 673 0 + 827 0072 0120 movs r0, #1 + 828 .L57: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 829 .loc 1 678 0 + 830 @ sp needed + 831 .LVL39: + 832 .LVL40: + 833 0074 70BD pop {r4, r5, r6, pc} + 834 .LVL41: + 835 .L61: + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 836 .loc 1 642 0 + 837 0076 0320 movs r0, #3 + 838 0078 FCE7 b .L57 + 839 .L63: + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 840 .loc 1 677 0 + 841 007a 0020 movs r0, #0 + 842 007c FAE7 b .L57 + 843 .L66: + 844 007e C046 .align 2 + 845 .L65: + 846 0080 00200240 .word 1073881088 + 847 .cfi_endproc + 848 .LFE50: + 850 .section .text.HAL_FLASH_Program,"ax",%progbits + 851 .align 1 + 852 .global HAL_FLASH_Program + 853 .syntax unified + 854 .code 16 + 855 .thumb_func + 856 .fpu softvfp + 858 HAL_FLASH_Program: + 859 .LFB39: + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 860 .loc 1 248 0 + 861 .cfi_startproc + 862 @ args = 0, pretend = 0, frame = 0 + 863 @ frame_needed = 0, uses_anonymous_args = 0 + 864 .LVL42: + 865 0000 70B5 push {r4, r5, r6, lr} + 866 .LCFI3: + 867 .cfi_def_cfa_offset 16 + 868 .cfi_offset 4, -16 + 869 .cfi_offset 5, -12 + 870 .cfi_offset 6, -8 + 871 .cfi_offset 14, -4 + 872 0002 0C00 movs r4, r1 + 873 0004 1500 movs r5, r2 + 874 .LVL43: + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 875 .loc 1 252 0 + 876 0006 0D4B ldr r3, .L72 + ARM GAS /tmp/ccqRvrNg.s page 31 + + + 877 0008 1B7C ldrb r3, [r3, #16] + 878 000a 012B cmp r3, #1 + 879 000c 13D0 beq .L70 + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 880 .loc 1 252 0 is_stmt 0 discriminator 2 + 881 000e 0B4B ldr r3, .L72 + 882 0010 0122 movs r2, #1 + 883 .LVL44: + 884 0012 1A74 strb r2, [r3, #16] + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 885 .loc 1 259 0 is_stmt 1 discriminator 2 + 886 0014 0A48 ldr r0, .L72+4 + 887 .LVL45: + 888 0016 FFF7FEFF bl FLASH_WaitForLastOperation + 889 .LVL46: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** { + 890 .loc 1 261 0 discriminator 2 + 891 001a 0028 cmp r0, #0 + 892 001c 03D0 beq .L71 + 893 .LVL47: + 894 .L69: + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 895 .loc 1 274 0 + 896 001e 074B ldr r3, .L72 + 897 0020 0022 movs r2, #0 + 898 0022 1A74 strb r2, [r3, #16] + 899 .LVL48: + 900 .L68: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 901 .loc 1 277 0 + 902 @ sp needed + 903 .LVL49: + 904 .LVL50: + 905 0024 70BD pop {r4, r5, r6, pc} + 906 .LVL51: + 907 .L71: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 908 .loc 1 264 0 + 909 0026 054B ldr r3, .L72 + 910 0028 0022 movs r2, #0 + 911 002a 5A61 str r2, [r3, #20] + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 912 .loc 1 267 0 + 913 002c 2560 str r5, [r4] + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 914 .loc 1 270 0 + 915 002e 0448 ldr r0, .L72+4 + 916 .LVL52: + 917 0030 FFF7FEFF bl FLASH_WaitForLastOperation + 918 .LVL53: + 919 0034 F3E7 b .L69 + 920 .LVL54: + 921 .L70: + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 922 .loc 1 252 0 + 923 0036 0220 movs r0, #2 + 924 .LVL55: + ARM GAS /tmp/ccqRvrNg.s page 32 + + + 925 0038 F4E7 b .L68 + 926 .L73: + 927 003a C046 .align 2 + 928 .L72: + 929 003c 00000000 .word .LANCHOR0 + 930 0040 50C30000 .word 50000 + 931 .cfi_endproc + 932 .LFE39: + 934 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 935 .align 1 + 936 .global HAL_FLASH_OB_Launch + 937 .syntax unified + 938 .code 16 + 939 .thumb_func + 940 .fpu softvfp + 942 HAL_FLASH_OB_Launch: + 943 .LFB48: + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** /* Set the OBL_Launch bit to launch the option byte loading */ + 944 .loc 1 575 0 + 945 .cfi_startproc + 946 @ args = 0, pretend = 0, frame = 0 + 947 @ frame_needed = 0, uses_anonymous_args = 0 + 948 0000 10B5 push {r4, lr} + 949 .LCFI4: + 950 .cfi_def_cfa_offset 8 + 951 .cfi_offset 4, -8 + 952 .cfi_offset 14, -4 + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 953 .loc 1 577 0 + 954 0002 054A ldr r2, .L75 + 955 0004 5168 ldr r1, [r2, #4] + 956 0006 8023 movs r3, #128 + 957 0008 DB02 lsls r3, r3, #11 + 958 000a 0B43 orrs r3, r1 + 959 000c 5360 str r3, [r2, #4] + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** } + 960 .loc 1 580 0 + 961 000e 0348 ldr r0, .L75+4 + 962 0010 FFF7FEFF bl FLASH_WaitForLastOperation + 963 .LVL56: + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c **** + 964 .loc 1 581 0 + 965 @ sp needed + 966 0014 10BD pop {r4, pc} + 967 .L76: + 968 0016 C046 .align 2 + 969 .L75: + 970 0018 00200240 .word 1073881088 + 971 001c 50C30000 .word 50000 + 972 .cfi_endproc + 973 .LFE48: + 975 .global pFlash + 976 .section .bss.pFlash,"aw",%nobits + 977 .align 2 + 978 .set .LANCHOR0,. + 0 + 981 pFlash: + 982 0000 00000000 .space 24 + ARM GAS /tmp/ccqRvrNg.s page 33 + + + 982 00000000 + 982 00000000 + 982 00000000 + 982 00000000 + 983 .text + 984 .Letext0: + 985 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 986 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 987 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 988 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 989 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 990 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 991 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 992 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 993 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 994 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 995 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h" + 996 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccqRvrNg.s page 34 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_flash.c + /tmp/ccqRvrNg.s:16 .text.FLASH_SetErrorCode:0000000000000000 $t + /tmp/ccqRvrNg.s:22 .text.FLASH_SetErrorCode:0000000000000000 FLASH_SetErrorCode + /tmp/ccqRvrNg.s:162 .text.FLASH_SetErrorCode:00000000000000ac $d + /tmp/ccqRvrNg.s:168 .text.HAL_FLASH_Program_IT:0000000000000000 $t + /tmp/ccqRvrNg.s:175 .text.HAL_FLASH_Program_IT:0000000000000000 HAL_FLASH_Program_IT + /tmp/ccqRvrNg.s:241 .text.HAL_FLASH_Program_IT:0000000000000038 $d + /tmp/ccqRvrNg.s:247 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 $t + /tmp/ccqRvrNg.s:254 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 HAL_FLASH_EndOfOperationCallback + /tmp/ccqRvrNg.s:269 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 $t + /tmp/ccqRvrNg.s:276 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 HAL_FLASH_OperationErrorCallback + /tmp/ccqRvrNg.s:291 .text.HAL_FLASH_IRQHandler:0000000000000000 $t + /tmp/ccqRvrNg.s:298 .text.HAL_FLASH_IRQHandler:0000000000000000 HAL_FLASH_IRQHandler + /tmp/ccqRvrNg.s:499 .text.HAL_FLASH_IRQHandler:00000000000000fc $d + /tmp/ccqRvrNg.s:508 .text.HAL_FLASH_Unlock:0000000000000000 $t + /tmp/ccqRvrNg.s:515 .text.HAL_FLASH_Unlock:0000000000000000 HAL_FLASH_Unlock + /tmp/ccqRvrNg.s:560 .text.HAL_FLASH_Unlock:000000000000002c $d + /tmp/ccqRvrNg.s:569 .text.HAL_FLASH_Lock:0000000000000000 $t + /tmp/ccqRvrNg.s:576 .text.HAL_FLASH_Lock:0000000000000000 HAL_FLASH_Lock + /tmp/ccqRvrNg.s:596 .text.HAL_FLASH_Lock:0000000000000010 $d + /tmp/ccqRvrNg.s:601 .text.HAL_FLASH_OB_Unlock:0000000000000000 $t + /tmp/ccqRvrNg.s:608 .text.HAL_FLASH_OB_Unlock:0000000000000000 HAL_FLASH_OB_Unlock + /tmp/ccqRvrNg.s:653 .text.HAL_FLASH_OB_Unlock:000000000000002c $d + /tmp/ccqRvrNg.s:662 .text.HAL_FLASH_OB_Lock:0000000000000000 $t + /tmp/ccqRvrNg.s:669 .text.HAL_FLASH_OB_Lock:0000000000000000 HAL_FLASH_OB_Lock + /tmp/ccqRvrNg.s:689 .text.HAL_FLASH_OB_Lock:0000000000000010 $d + /tmp/ccqRvrNg.s:694 .text.HAL_FLASH_GetError:0000000000000000 $t + /tmp/ccqRvrNg.s:701 .text.HAL_FLASH_GetError:0000000000000000 HAL_FLASH_GetError + /tmp/ccqRvrNg.s:717 .text.HAL_FLASH_GetError:0000000000000008 $d + /tmp/ccqRvrNg.s:722 .text.FLASH_WaitForLastOperation:0000000000000000 $t + /tmp/ccqRvrNg.s:729 .text.FLASH_WaitForLastOperation:0000000000000000 FLASH_WaitForLastOperation + /tmp/ccqRvrNg.s:846 .text.FLASH_WaitForLastOperation:0000000000000080 $d + /tmp/ccqRvrNg.s:851 .text.HAL_FLASH_Program:0000000000000000 $t + /tmp/ccqRvrNg.s:858 .text.HAL_FLASH_Program:0000000000000000 HAL_FLASH_Program + /tmp/ccqRvrNg.s:929 .text.HAL_FLASH_Program:000000000000003c $d + /tmp/ccqRvrNg.s:935 .text.HAL_FLASH_OB_Launch:0000000000000000 $t + /tmp/ccqRvrNg.s:942 .text.HAL_FLASH_OB_Launch:0000000000000000 HAL_FLASH_OB_Launch + /tmp/ccqRvrNg.s:970 .text.HAL_FLASH_OB_Launch:0000000000000018 $d + /tmp/ccqRvrNg.s:981 .bss.pFlash:0000000000000000 pFlash + /tmp/ccqRvrNg.s:977 .bss.pFlash:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +FLASH_PageErase +HAL_GetTick diff --git a/build/stm32l0xx_hal_flash_ex.d b/build/stm32l0xx_hal_flash_ex.d new file mode 100644 index 0000000..1029895 --- /dev/null +++ b/build/stm32l0xx_hal_flash_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_flash_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_flash_ex.lst b/build/stm32l0xx_hal_flash_ex.lst new file mode 100644 index 0000000..9789dd7 --- /dev/null +++ b/build/stm32l0xx_hal_flash_ex.lst @@ -0,0 +1,3227 @@ +ARM GAS /tmp/cc9alhJF.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_flash_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.FLASH_OB_ProtectedSectorsConfig,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 FLASH_OB_ProtectedSectorsConfig: + 23 .LFB62: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @file stm32l0xx_hal_flash_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Extended FLASH HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This file provides firmware functions to manage the following + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * functionalities of the internal FLASH memory: + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + FLASH Interface configuration + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + FLASH Memory Erasing + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + DATA EEPROM Programming/Erasing + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + Option Bytes Programming + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + Interrupts management + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @verbatim + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ##### Flash peripheral Extended features ##### + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] Comparing to other products, the FLASH interface for STM32L0xx + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** devices contains the following additional features + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) Erase functions + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) DATA_EEPROM memory management + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) BOOT option bit configuration + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) PCROP protection for all sectors + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ##### How to use this driver ##### + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] This driver provides functions to configure and program the FLASH memory + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** of all STM32L0xx. It includes: + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) Full DATA_EEPROM erase and program management + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) Boot activation + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) PCROP protection configuration and control for all pages + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9alhJF.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @endverbatim + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ****************************************************************************** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @attention + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * are permitted provided that the following conditions are met: + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * this list of conditions and the following disclaimer. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * this list of conditions and the following disclaimer in the documentation + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * and/or other materials provided with the distribution. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * may be used to endorse or promote products derived from this software + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * without specific prior written permission. + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ****************************************************************************** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #include "stm32l0xx_hal.h" + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup FLASH + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Variables + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Variables used for Erase pages under interruption*/ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** extern FLASH_ProcessTypeDef pFlash; + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief FLASH HAL Extension module driver + ARM GAS /tmp/cc9alhJF.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress); + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_BFB2) + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_BFB2 */ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetRDP(void); + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void); + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetBOR(void); + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetBOOTBit1(void); + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BootBit1); + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32 + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState); + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void); + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP2(void); + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + ARM GAS /tmp/cc9alhJF.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief FLASH Memory Erasing functions + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @verbatim + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ##### FLASH Erasing Programming functions ##### + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] The FLASH Memory Erasing functions, includes the following functions: + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** is called with parameter 0xFFFFFFFF + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] Any operation of erase should follow these steps: + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** program memory access. + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the desired function to erase page. + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (recommended to protect the FLASH memory against possible unwanted operation). + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @endverbatim + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory Pages + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * must be called before. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param[out] PageError pointer to variable that + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information on faulty page in case of error + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * (0xFFFFFFFF means that all the pages have been correctly erased) + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t address = 0U; + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Locked */ + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status == HAL_OK) + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Initialization of PageError variable*/ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *PageError = 0xFFFFFFFFU; + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_NBPAGES(pEraseInit->NbPages)); + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + ARM GAS /tmp/cc9alhJF.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEr + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Erase page by page to be done*/ + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** for(address = pEraseInit->PageAddress; + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** FLASH_PageErase(address); + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the ERASE Bit */ + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty address */ + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *PageError = address; + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** break; + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * must be called before. + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with paramet + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * 0xFFFFFFFF + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* If procedure already ongoing, reject the next one */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return HAL_ERROR; + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_NBPAGES(pEraseInit->NbPages)); + ARM GAS /tmp/cc9alhJF.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pErase + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Locked */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status == HAL_OK) + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.NbPagesToErase = pEraseInit->NbPages; + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.Page = pEraseInit->PageAddress; + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Erase 1st page and wait for IT*/ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** FLASH_PageErase(pEraseInit->PageAddress); + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Option Bytes Programming functions + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @verbatim + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ##### Option Bytes Programming functions ##### + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] Any operation of erase or program should follow these steps: + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASH_OB_Unlock() function to enable the Flash option control + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** register access. + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call following function to program the desired option bytes. + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (++) @ref HAL_FLASHEx_OBProgram: + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** - To Enable/Disable the desired sector write protection. + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** - To set the desired read Protection Level. + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** - To configure the user option Bytes: IWDG, STOP and the Standby. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** - To Set the BOR level. + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Once all needed option bytes to be programmed are correctly written, call the + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @ref HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASH_OB_Lock() to disable the Flash option control register access (reco + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** to protect the option Bytes against possible unwanted operations). + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9alhJF.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] Proprietary code Read Out Protection (PcROP): + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) The PcROP sector is selected by using the same option bytes as the Write + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** protection (nWRPi bits). As a result, these 2 options are exclusive each other. + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) In order to activate the PcROP (change the function of the nWRPi option bits), + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** the WPRMOD option bit must be activated. + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) The active value of nWRPi bits is inverted when PCROP mode is active, this + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** means: if WPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** is read/write protected. + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) To activate PCROP mode for Flash sector(s), you need to call the following function: + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (++) @ref HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (++) @ref HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @endverbatim + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Program option bytes + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Locked */ + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Write protection configuration*/ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState)); + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPSector2, pOBInit->WRPS + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPState); + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Read protection configuration*/ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + ARM GAS /tmp/cc9alhJF.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* USER configuration*/ + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STOP_NORST, + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STDBY_NORST); + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* BOR Level configuration*/ + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_BORConfig(pOBInit->BORLevel); + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program BOOT Bit1 config option byte */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((pOBInit->OptionType & OPTIONBYTE_BOOT_BIT1) == OPTIONBYTE_BOOT_BIT1) + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_BOOTBit1Config(pOBInit->BOOTBit1Config); + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Get the Option byte configuration + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval None + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get WRP sector */ + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->WRPSector = FLASH_OB_GetWRP(); + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + ARM GAS /tmp/cc9alhJF.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->WRPSector2 = FLASH_OB_GetWRP2(); + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Get RDP Level*/ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Get USER*/ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /*Get BOR Level*/ + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->BORLevel = FLASH_OB_GetBOR(); + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get BOOT bit 1 config OB */ + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->BOOTBit1Config = FLASH_OB_GetBOOTBit1(); + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2) + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Program option bytes + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OBEX(pAdvOBInit->OptionType)); + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_WPRMOD) + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program PCROP option byte*/ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPSector2, pAd + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPState); + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_WPRMOD */ + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_BFB2) + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program BOOT config option byte */ + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_BFB2 */ + ARM GAS /tmp/cc9alhJF.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Get the OBEX byte configuration + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval None + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->OptionType = 0; + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_WPRMOD) + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->OptionType |= OPTIONBYTE_PCROP; + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get PCROP state */ + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> FLASH_OPTR_WPRMOD_Pos; + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get PCROP protected sector */ + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->PCROPSector = FLASH->WRPR; + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get PCROP protected sector */ + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->PCROPSector2 = FLASH->WRPR2; + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_WPRMOD */ + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_BFB2) + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG; + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get Boot config OB */ + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 16U; + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_BFB2 */ + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */ + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_WPRMOD) + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Select the Protection Mode (WPRMOD). + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note Once WPRMOD bit is active, unprotection of a protected sector is not possible + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPER + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint16_t tmp1 = 0; + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp2 = 0; + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint8_t optiontmp = 0; + ARM GAS /tmp/cc9alhJF.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint16_t optiontmp2 = 0; + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Mask RDP Byte */ + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Update Option Byte */ + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* calculate the option byte to write */ + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = (uint16_t)(~(optiontmp2 )); + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* program PCRop */ + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->RDP = tmp2; + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Read protection operation Status */ + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Deselect the Protection Mode (WPRMOD). + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note Once WPRMOD bit is active, unprotection of a protected sector is not possible + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPER + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint16_t tmp1 = 0; + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp2 = 0; + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint8_t optiontmp = 0; + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint16_t optiontmp2 = 0; + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Mask RDP Byte */ + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Update Option Byte */ + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* calculate the option byte to write */ + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = (uint16_t)(~(optiontmp2 )); + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + ARM GAS /tmp/cc9alhJF.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* program PCRop */ + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->RDP = tmp2; + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Read protection operation Status */ + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_WPRMOD */ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief DATA EEPROM Programming functions + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @verbatim + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** =============================================================================== + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ##### DATA EEPROM Programming functions ##### + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** =============================================================================== + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** [..] Any operation of erase or program should follow these steps: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** and Flash program erase control register access. + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the desired function to erase or program data. + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** and Flash program erase control register access(recommended + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** to protect the DATA_EEPROM against possible unwanted operation). + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** @endverbatim + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Unlocks the data memory and FLASH_PECR register access. + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Unlocking the Data memory and FLASH_PECR register access*/ + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** FLASH->PEKEYR = FLASH_PEKEY1; + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** FLASH->PEKEYR = FLASH_PEKEY2; + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return HAL_ERROR; + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + ARM GAS /tmp/cc9alhJF.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return HAL_OK; + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Locks the Data memory and FLASH_PECR register access. + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return HAL_OK; + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Erase a word in data memory. + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Address specifies the address to be erased. + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * must be called before. + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * and Flash program erase control register access(recommended to protect + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * the DATA_EEPROM against possible unwanted operation). + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address) + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_DATA_ADDRESS(Address)); + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Write 00000000h to valid address in the data memory */ + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *(__IO uint32_t *) Address = 0x00000000U; + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the erase status */ + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Program word at a specified address + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * must be called before. + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * and Flash program erase control register access(recommended to protect + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * the DATA_EEPROM against possible unwanted operation). + ARM GAS /tmp/cc9alhJF.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * this function to configure the Fixed Time Programming. + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param TypeProgram Indicate the way to program at a specified address. + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be a value of @ref FLASHEx_Type_Program_Data + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Address specifie the address to be programmed. + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Data specifie the data to be programmed + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Locked */ + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_FLASH_DATA_ADDRESS(Address)); + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD) + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program word (32-bit) at a specified address.*/ + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *(__IO uint32_t *)Address = Data; + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD) + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program halfword (16-bit) at a specified address.*/ + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *(__IO uint16_t *)Address = (uint16_t) Data; + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE) + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program byte (8-bit) at a specified address.*/ + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *(__IO uint8_t *)Address = (uint8_t) Data; + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = HAL_ERROR; + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Process Unlocked */ + ARM GAS /tmp/cc9alhJF.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval None + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** SET_BIT(FLASH->PECR, FLASH_PECR_FIX); + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval None + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FIX); + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OPTIONS BYTES + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** ============================================================================== + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Enables or disables the read out protection. + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * must be called before. + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_RDP specifies the read protection level. + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be: + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Chip protection + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0 + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/cc9alhJF.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_RDP(OB_RDP)); + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = (uint32_t)(OB->RDP & FLASH_OPTR_RDPROT); + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_WPRMOD) + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Mask WPRMOD bit */ + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp3 = (uint32_t)(OB->RDP & FLASH_OPTR_WPRMOD); + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* calculate the option byte to write */ + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = (~((uint32_t)(OB_RDP | tmp3))); + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3))); + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* program read protection level */ + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->RDP = tmp2; + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Read protection operation Status */ + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Programs the FLASH brownout reset threshold level Option Byte. + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_BOR Selects the brownout reset threshold level. + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * power supply reaches the PDR(Power Down Reset) threshold (1.5V) + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp = 0, tmp1 = 0; + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_BOR_LEVEL(OB_BOR)); + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get the User Option byte register */ + ARM GAS /tmp/cc9alhJF.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16U); + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/ + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U; + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= (OB_BOR | tmp1); + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Write the BOR Option Byte */ + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->USER = tmp; + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Option Byte BOR programmation Status */ + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Sets or resets the BOOT bit1 option bit. + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_BootBit1 Set or Reset the BOOT bit1 option bit. + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_BIT1_RESET BOOT1 option bit reset + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_BIT1_SET BOOT1 option bit set + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BootBit1) + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BootBit1) << 15; + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT1(OB_BootBit1)); + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get the User Option byte register */ + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16U); + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Calculate the user option byte to write */ + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp = (~(OB_Bits | tmp1)) << 16U; + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= OB_Bits | tmp1; + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program OB */ + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->USER = tmp; + ARM GAS /tmp/cc9alhJF.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH User Option Bytes values. + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes. + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void) + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the User Option Byte */ + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16U); + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH Read Protection level. + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval FLASH RDP level + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetRDP(void) + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (uint8_t)(FLASH->OPTR & FLASH_OPTR_RDPROT); + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH BOR level. + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval The BOR level Option Bytes. + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetBOR(void) + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the BOR level */ + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16U); + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH BOOT bit1 value. + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval The BOOT bit 1 value Option Bytes. + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetBOOTBit1(void) + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the BOR level */ + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> FLASH_OPTR_BOOT1_Pos; + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH Write Protection Option Bytes value. +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval The FLASH Write Protection Option Bytes value. +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void) +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + ARM GAS /tmp/cc9alhJF.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (uint32_t)(FLASH->WRPR); +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Returns the FLASH Write Protection Option Bytes value. +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval The FLASH Write Protection Option Bytes value. +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP2(void) +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return (uint32_t)(FLASH->WRPR2); +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Write Option Byte of the desired pages of the Flash. +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Sector specifies the sectors to be write protected. +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Sector2 specifies the sectors to be write protected (only stm32l07xxx and stm32l08xxx d +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param NewState new state of the specified FLASH Pages Write protection. +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be: +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_WRPSTATE_ENABLE +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_WRPSTATE_DISABLE +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_ +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Write Option Byte of the desired pages of the Flash. +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param Sector specifies the sectors to be write protected. +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param NewState new state of the specified FLASH Pages Write protection. +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be: +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_WRPSTATE_ENABLE +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_WRPSTATE_DISABLE +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState) +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 25 .loc 1 1044 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 70B5 push {r4, r5, r6, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 16 + 33 .cfi_offset 4, -16 + 34 .cfi_offset 5, -12 + 35 .cfi_offset 6, -8 + 36 .cfi_offset 14, -4 + 37 0002 0400 movs r4, r0 + 38 0004 0E00 movs r6, r1 + 39 0006 1500 movs r5, r2 + 40 .LVL1: + ARM GAS /tmp/cc9alhJF.s page 20 + + +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t WRP_Data = 0; +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t OB_WRP = Sector; +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 41 .loc 1 1050 0 + 42 0008 2948 ldr r0, .L9 + 43 .LVL2: + 44 000a FFF7FEFF bl FLASH_WaitForLastOperation + 45 .LVL3: +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) + 46 .loc 1 1052 0 + 47 000e 0028 cmp r0, #0 + 48 0010 2DD1 bne .L2 +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 49 .loc 1 1055 0 + 50 0012 284B ldr r3, .L9+4 + 51 0014 0022 movs r2, #0 + 52 0016 5A61 str r2, [r3, #20] +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Update WRP only if at least 1 selected sector */ +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (OB_WRP != 0x00000000U) + 53 .loc 1 1058 0 + 54 0018 002C cmp r4, #0 + 55 001a 0BD0 beq .L3 +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((OB_WRP & WRP_MASK_LOW) != 0x00000000U) + 56 .loc 1 1060 0 + 57 001c 2304 lsls r3, r4, #16 + 58 001e 09D0 beq .L3 +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (NewState != OB_WRPSTATE_DISABLE) + 59 .loc 1 1062 0 + 60 0020 002D cmp r5, #0 + 61 0022 28D0 beq .L4 +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP01)); + 62 .loc 1 1064 0 + 63 0024 2449 ldr r1, .L9+8 + 64 0026 8B68 ldr r3, [r1, #8] + 65 0028 2343 orrs r3, r4 + 66 002a 9BB2 uxth r3, r3 + 67 .LVL4: +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP01 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); + 68 .loc 1 1065 0 + 69 002c DA43 mvns r2, r3 + 70 002e 1204 lsls r2, r2, #16 + 71 0030 1343 orrs r3, r2 + 72 .LVL5: + 73 0032 8B60 str r3, [r1, #8] + 74 .L3: +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else + ARM GAS /tmp/cc9alhJF.s page 21 + + +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP01)); +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP01 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Update WRP only if at least 1 selected sector */ +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (OB_WRP != 0x00000000U) + 75 .loc 1 1076 0 + 76 0034 002C cmp r4, #0 + 77 0036 0CD0 beq .L5 +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((OB_WRP & WRP_MASK_HIGH) != 0x00000000U) + 78 .loc 1 1078 0 + 79 0038 230C lsrs r3, r4, #16 + 80 003a 0AD0 beq .L5 +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (NewState != OB_WRPSTATE_DISABLE) + 81 .loc 1 1080 0 + 82 003c 002D cmp r5, #0 + 83 003e 23D0 beq .L6 +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16U | OB->WRP23))); + 84 .loc 1 1082 0 + 85 0040 1C00 movs r4, r3 + 86 .LVL6: + 87 0042 1D4A ldr r2, .L9+8 + 88 0044 D368 ldr r3, [r2, #12] + 89 0046 1C43 orrs r4, r3 + 90 0048 A4B2 uxth r4, r4 + 91 .LVL7: +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP23 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); + 92 .loc 1 1083 0 + 93 004a E343 mvns r3, r4 + 94 004c 1B04 lsls r3, r3, #16 + 95 004e 1C43 orrs r4, r3 + 96 .LVL8: + 97 0050 D460 str r4, [r2, #12] + 98 .L5: + 99 .LVL9: +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16U & OB->WRP23))); +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP23 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB_WRP = Sector2; +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Update WRP only if at least 1 selected sector */ +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (OB_WRP != 0x00000000U) + 100 .loc 1 1095 0 + 101 0052 002E cmp r6, #0 + 102 0054 0BD0 beq .L2 +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + ARM GAS /tmp/cc9alhJF.s page 22 + + +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if ((OB_WRP & WRP_MASK_LOW) != 0x00000000U) + 103 .loc 1 1097 0 + 104 0056 3304 lsls r3, r6, #16 + 105 0058 09D0 beq .L2 +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (NewState != OB_WRPSTATE_DISABLE) + 106 .loc 1 1099 0 + 107 005a 002D cmp r5, #0 + 108 005c 1ED1 bne .L8 +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP45)); +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP45 =(uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** else +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP45)); + 109 .loc 1 1106 0 + 110 005e 1649 ldr r1, .L9+8 + 111 0060 0B69 ldr r3, [r1, #16] + 112 0062 B343 bics r3, r6 + 113 0064 9BB2 uxth r3, r3 + 114 .LVL10: +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP45 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); + 115 .loc 1 1107 0 + 116 0066 DA43 mvns r2, r3 + 117 0068 1204 lsls r2, r2, #16 + 118 006a 1343 orrs r3, r2 + 119 .LVL11: + 120 006c 0B61 str r3, [r1, #16] + 121 .LVL12: + 122 .L2: +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 123 .loc 1 1114 0 + 124 006e 1048 ldr r0, .L9 + 125 .LVL13: + 126 0070 FFF7FEFF bl FLASH_WaitForLastOperation + 127 .LVL14: +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the write protection operation Status */ +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 128 .loc 1 1118 0 + 129 @ sp needed + 130 .LVL15: + 131 0074 70BD pop {r4, r5, r6, pc} + 132 .LVL16: + 133 .L4: +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP01 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); + 134 .loc 1 1069 0 + 135 0076 1049 ldr r1, .L9+8 + 136 0078 8B68 ldr r3, [r1, #8] + ARM GAS /tmp/cc9alhJF.s page 23 + + + 137 007a A343 bics r3, r4 + 138 007c 9BB2 uxth r3, r3 + 139 .LVL17: +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 140 .loc 1 1070 0 + 141 007e DA43 mvns r2, r3 + 142 0080 1204 lsls r2, r2, #16 + 143 0082 1343 orrs r3, r2 + 144 .LVL18: + 145 0084 8B60 str r3, [r1, #8] + 146 0086 D5E7 b .L3 + 147 .L6: +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP23 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); + 148 .loc 1 1087 0 + 149 0088 E443 mvns r4, r4 + 150 .LVL19: + 151 008a 240C lsrs r4, r4, #16 + 152 .LVL20: + 153 008c 0A4A ldr r2, .L9+8 + 154 008e D368 ldr r3, [r2, #12] + 155 0090 2340 ands r3, r4 + 156 .LVL21: +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 157 .loc 1 1088 0 + 158 0092 DC43 mvns r4, r3 + 159 0094 2404 lsls r4, r4, #16 + 160 0096 1C43 orrs r4, r3 + 161 0098 D460 str r4, [r2, #12] + 162 009a DAE7 b .L5 + 163 .LVL22: + 164 .L8: +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->WRP45 =(uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); + 165 .loc 1 1101 0 + 166 009c 064A ldr r2, .L9+8 + 167 009e 1369 ldr r3, [r2, #16] + 168 00a0 1E43 orrs r6, r3 + 169 .LVL23: + 170 00a2 B6B2 uxth r6, r6 + 171 .LVL24: +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 172 .loc 1 1102 0 + 173 00a4 F343 mvns r3, r6 + 174 00a6 1B04 lsls r3, r3, #16 + 175 00a8 1E43 orrs r6, r3 + 176 .LVL25: + 177 00aa 1661 str r6, [r2, #16] + 178 00ac DFE7 b .L2 + 179 .L10: + 180 00ae C046 .align 2 + 181 .L9: + 182 00b0 50C30000 .word 50000 + 183 00b4 00000000 .word pFlash + 184 00b8 0000F81F .word 536346624 + 185 .cfi_endproc + 186 .LFE62: + 188 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 189 .align 1 + ARM GAS /tmp/cc9alhJF.s page 24 + + + 190 .global HAL_FLASHEx_Erase + 191 .syntax unified + 192 .code 16 + 193 .thumb_func + 194 .fpu softvfp + 196 HAL_FLASHEx_Erase: + 197 .LFB39: + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 198 .loc 1 188 0 + 199 .cfi_startproc + 200 @ args = 0, pretend = 0, frame = 0 + 201 @ frame_needed = 0, uses_anonymous_args = 0 + 202 .LVL26: + 203 0000 F0B5 push {r4, r5, r6, r7, lr} + 204 .LCFI1: + 205 .cfi_def_cfa_offset 20 + 206 .cfi_offset 4, -20 + 207 .cfi_offset 5, -16 + 208 .cfi_offset 6, -12 + 209 .cfi_offset 7, -8 + 210 .cfi_offset 14, -4 + 211 0002 C646 mov lr, r8 + 212 0004 00B5 push {lr} + 213 .LCFI2: + 214 .cfi_def_cfa_offset 24 + 215 .cfi_offset 8, -24 + 216 0006 0600 movs r6, r0 + 217 0008 8846 mov r8, r1 + 218 .LVL27: + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 219 .loc 1 193 0 + 220 000a 204B ldr r3, .L19 + 221 000c 1B7C ldrb r3, [r3, #16] + 222 000e 012B cmp r3, #1 + 223 0010 3AD0 beq .L17 + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 224 .loc 1 193 0 is_stmt 0 discriminator 2 + 225 0012 1E4B ldr r3, .L19 + 226 0014 0122 movs r2, #1 + 227 0016 1A74 strb r2, [r3, #16] + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 228 .loc 1 196 0 is_stmt 1 discriminator 2 + 229 0018 1D48 ldr r0, .L19+4 + 230 .LVL28: + 231 001a FFF7FEFF bl FLASH_WaitForLastOperation + 232 .LVL29: + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 233 .loc 1 198 0 discriminator 2 + 234 001e 0028 cmp r0, #0 + 235 0020 2CD1 bne .L13 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 236 .loc 1 201 0 + 237 0022 0123 movs r3, #1 + 238 0024 5B42 rsbs r3, r3, #0 + 239 0026 4246 mov r2, r8 + 240 0028 1360 str r3, [r2] + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + ARM GAS /tmp/cc9alhJF.s page 25 + + + 241 .loc 1 210 0 + 242 002a 7568 ldr r5, [r6, #4] + 243 .LVL30: + 244 .L14: + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 245 .loc 1 211 0 discriminator 1 + 246 002c B368 ldr r3, [r6, #8] + 247 002e DB01 lsls r3, r3, #7 + 248 0030 7268 ldr r2, [r6, #4] + 249 0032 9446 mov ip, r2 + 250 0034 6344 add r3, r3, ip + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 251 .loc 1 210 0 discriminator 1 + 252 0036 AB42 cmp r3, r5 + 253 0038 20D9 bls .L13 + 254 .LVL31: + 255 .LBB18: + 256 .LBB19: +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_IWDG Selects the WDG mode. +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_IWDG_SW Software WDG selected +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_IWDG_HW Hardware WDG selected +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_STOP Reset event when entering STOP mode. +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_STOP_NORST No reset generated when entering in STOP +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_STOP_RST Reset generated when entering in STOP +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_STDBY Reset event when entering Standby mode. +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp = 0, tmp1 = 0; +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE(OB_STOP)); +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get the User Option byte register */ +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16U); +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Calculate the user option byte to write */ +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(O +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + ARM GAS /tmp/cc9alhJF.s page 26 + + +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Write the User Option Byte */ +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->USER = tmp; +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Option Byte program Status */ +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #if defined(FLASH_OPTR_BFB2) +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Configures to boot from Bank1 or Bank2. +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param OB_BOOT select the FLASH Bank to boot from. +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_BANK1 BFB2 option bit reset +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_BANK2 BFB2 option bit set +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval HAL status +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** uint32_t tmp = 0U, tmp1 = 0U; +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Check the parameters */ +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT_BANK(OB_BOOT)); +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get the User Option byte register and BOR Level*/ +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16U); +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Calculate the option byte to write */ +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U; +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= (OB_BOOT | tmp1); +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if(status == HAL_OK) +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Write the BOOT Option Byte */ +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** OB->USER = tmp; +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Return the Option Byte program Status */ +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + ARM GAS /tmp/cc9alhJF.s page 27 + + +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif /* FLASH_OPTR_BFB2 */ +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @} +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup FLASH +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Functions +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @{ +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /** +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @brief Erases a specified page in program memory. +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @param PageAddress The page address in program memory to be erased. +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @note A Page is erased in the Program memory only if the address to load +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** * @retval None +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** */ +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress) +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 257 .loc 1 1245 0 + 258 003a 0022 movs r2, #0 + 259 003c 134B ldr r3, .L19 + 260 003e 5A61 str r2, [r3, #20] +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Set the ERASE bit */ +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 261 .loc 1 1248 0 + 262 0040 144C ldr r4, .L19+8 + 263 0042 6168 ldr r1, [r4, #4] + 264 0044 8023 movs r3, #128 + 265 0046 9B00 lsls r3, r3, #2 + 266 0048 0B43 orrs r3, r1 + 267 004a 6360 str r3, [r4, #4] +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Set PROG bit */ +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 268 .loc 1 1251 0 + 269 004c 6368 ldr r3, [r4, #4] + 270 004e 0827 movs r7, #8 + 271 0050 3B43 orrs r3, r7 + 272 0052 6360 str r3, [r4, #4] +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Write 00000000h to the first word of the program page to erase */ +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000; + 273 .loc 1 1254 0 + ARM GAS /tmp/cc9alhJF.s page 28 + + + 274 0054 7F23 movs r3, #127 + 275 0056 2900 movs r1, r5 + 276 0058 9943 bics r1, r3 + 277 005a 0A60 str r2, [r1] + 278 .LVL32: + 279 .LBE19: + 280 .LBE18: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 281 .loc 1 217 0 + 282 005c 0C48 ldr r0, .L19+4 + 283 .LVL33: + 284 005e FFF7FEFF bl FLASH_WaitForLastOperation + 285 .LVL34: + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 286 .loc 1 220 0 + 287 0062 6368 ldr r3, [r4, #4] + 288 0064 BB43 bics r3, r7 + 289 0066 6360 str r3, [r4, #4] + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 290 .loc 1 221 0 + 291 0068 6368 ldr r3, [r4, #4] + 292 006a 0B4A ldr r2, .L19+12 + 293 006c 1340 ands r3, r2 + 294 006e 6360 str r3, [r4, #4] + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 295 .loc 1 223 0 + 296 0070 0028 cmp r0, #0 + 297 0072 01D1 bne .L18 + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 298 .loc 1 212 0 + 299 0074 8035 adds r5, r5, #128 + 300 .LVL35: + 301 0076 D9E7 b .L14 + 302 .L18: + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** break; + 303 .loc 1 226 0 + 304 0078 4346 mov r3, r8 + 305 007a 1D60 str r5, [r3] + 306 .LVL36: + 307 .L13: + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 308 .loc 1 233 0 + 309 007c 034B ldr r3, .L19 + 310 007e 0022 movs r2, #0 + 311 0080 1A74 strb r2, [r3, #16] + 312 .LVL37: + 313 .L12: + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 314 .loc 1 236 0 + 315 @ sp needed + 316 .LVL38: + 317 .LVL39: + 318 0082 04BC pop {r2} + 319 0084 9046 mov r8, r2 + 320 0086 F0BD pop {r4, r5, r6, r7, pc} + 321 .LVL40: + 322 .L17: + ARM GAS /tmp/cc9alhJF.s page 29 + + + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 323 .loc 1 193 0 + 324 0088 0220 movs r0, #2 + 325 .LVL41: + 326 008a FAE7 b .L12 + 327 .L20: + 328 .align 2 + 329 .L19: + 330 008c 00000000 .word pFlash + 331 0090 50C30000 .word 50000 + 332 0094 00200240 .word 1073881088 + 333 0098 FFFDFFFF .word -513 + 334 .cfi_endproc + 335 .LFE39: + 337 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 338 .align 1 + 339 .global HAL_FLASHEx_Erase_IT + 340 .syntax unified + 341 .code 16 + 342 .thumb_func + 343 .fpu softvfp + 345 HAL_FLASHEx_Erase_IT: + 346 .LFB40: + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 347 .loc 1 252 0 + 348 .cfi_startproc + 349 @ args = 0, pretend = 0, frame = 0 + 350 @ frame_needed = 0, uses_anonymous_args = 0 + 351 .LVL42: + 352 0000 70B5 push {r4, r5, r6, lr} + 353 .LCFI3: + 354 .cfi_def_cfa_offset 16 + 355 .cfi_offset 4, -16 + 356 .cfi_offset 5, -12 + 357 .cfi_offset 6, -8 + 358 .cfi_offset 14, -4 + 359 0002 0400 movs r4, r0 + 360 .LVL43: + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 361 .loc 1 256 0 + 362 0004 1A4B ldr r3, .L27 + 363 0006 1B78 ldrb r3, [r3] + 364 0008 002B cmp r3, #0 + 365 000a 2CD1 bne .L24 + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 366 .loc 1 268 0 + 367 000c 184B ldr r3, .L27 + 368 000e 1B7C ldrb r3, [r3, #16] + 369 0010 012B cmp r3, #1 + 370 0012 2AD0 beq .L25 + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 371 .loc 1 268 0 is_stmt 0 discriminator 2 + 372 0014 164B ldr r3, .L27 + 373 0016 0122 movs r2, #1 + 374 0018 1A74 strb r2, [r3, #16] + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 375 .loc 1 271 0 is_stmt 1 discriminator 2 + ARM GAS /tmp/cc9alhJF.s page 30 + + + 376 001a 1648 ldr r0, .L27+4 + 377 .LVL44: + 378 001c FFF7FEFF bl FLASH_WaitForLastOperation + 379 .LVL45: + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 380 .loc 1 273 0 discriminator 2 + 381 0020 0028 cmp r0, #0 + 382 0022 03D0 beq .L26 + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 383 .loc 1 288 0 + 384 0024 124B ldr r3, .L27 + 385 0026 0022 movs r2, #0 + 386 0028 1A74 strb r2, [r3, #16] + 387 002a 1DE0 b .L22 + 388 .L26: + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 389 .loc 1 276 0 + 390 002c 124B ldr r3, .L27+8 + 391 002e 5968 ldr r1, [r3, #4] + 392 0030 C022 movs r2, #192 + 393 0032 9202 lsls r2, r2, #10 + 394 0034 0A43 orrs r2, r1 + 395 0036 5A60 str r2, [r3, #4] + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.NbPagesToErase = pEraseInit->NbPages; + 396 .loc 1 278 0 + 397 0038 0D4A ldr r2, .L27 + 398 003a 0121 movs r1, #1 + 399 003c 1170 strb r1, [r2] + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pFlash.Page = pEraseInit->PageAddress; + 400 .loc 1 279 0 + 401 003e A168 ldr r1, [r4, #8] + 402 0040 5160 str r1, [r2, #4] + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 403 .loc 1 280 0 + 404 0042 6168 ldr r1, [r4, #4] + 405 0044 D160 str r1, [r2, #12] + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 406 .loc 1 283 0 + 407 0046 6168 ldr r1, [r4, #4] + 408 .LVL46: + 409 .LBB20: + 410 .LBB21: +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 411 .loc 1 1245 0 + 412 0048 0024 movs r4, #0 + 413 .LVL47: + 414 004a 5461 str r4, [r2, #20] +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 415 .loc 1 1248 0 + 416 004c 5D68 ldr r5, [r3, #4] + 417 004e 8022 movs r2, #128 + 418 0050 9200 lsls r2, r2, #2 + 419 0052 2A43 orrs r2, r5 + 420 0054 5A60 str r2, [r3, #4] +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 421 .loc 1 1251 0 + 422 0056 5A68 ldr r2, [r3, #4] + ARM GAS /tmp/cc9alhJF.s page 31 + + + 423 0058 0825 movs r5, #8 + 424 005a 2A43 orrs r2, r5 + 425 005c 5A60 str r2, [r3, #4] + 426 .loc 1 1254 0 + 427 005e 7F23 movs r3, #127 + 428 0060 9943 bics r1, r3 + 429 .LVL48: + 430 0062 0C60 str r4, [r1] + 431 0064 00E0 b .L22 + 432 .LVL49: + 433 .L24: + 434 .LBE21: + 435 .LBE20: + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 436 .loc 1 258 0 + 437 0066 0120 movs r0, #1 + 438 .LVL50: + 439 .L22: + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 440 .loc 1 292 0 + 441 @ sp needed + 442 0068 70BD pop {r4, r5, r6, pc} + 443 .LVL51: + 444 .L25: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 445 .loc 1 268 0 + 446 006a 0220 movs r0, #2 + 447 .LVL52: + 448 006c FCE7 b .L22 + 449 .L28: + 450 006e C046 .align 2 + 451 .L27: + 452 0070 00000000 .word pFlash + 453 0074 50C30000 .word 50000 + 454 0078 00200240 .word 1073881088 + 455 .cfi_endproc + 456 .LFE40: + 458 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 459 .align 1 + 460 .global HAL_FLASHEx_OBProgram + 461 .syntax unified + 462 .code 16 + 463 .thumb_func + 464 .fpu softvfp + 466 HAL_FLASHEx_OBProgram: + 467 .LFB41: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 468 .loc 1 344 0 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 0 + 471 @ frame_needed = 0, uses_anonymous_args = 0 + 472 .LVL53: + 473 0000 70B5 push {r4, r5, r6, lr} + 474 .LCFI4: + 475 .cfi_def_cfa_offset 16 + 476 .cfi_offset 4, -16 + 477 .cfi_offset 5, -12 + ARM GAS /tmp/cc9alhJF.s page 32 + + + 478 .cfi_offset 6, -8 + 479 .cfi_offset 14, -4 + 480 0002 0400 movs r4, r0 + 481 .LVL54: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 482 .loc 1 348 0 + 483 0004 514B ldr r3, .L50 + 484 0006 1B7C ldrb r3, [r3, #16] + 485 0008 012B cmp r3, #1 + 486 000a 00D1 bne .LCB475 + 487 000c 9CE0 b .L40 @long jump + 488 .LCB475: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 489 .loc 1 348 0 is_stmt 0 discriminator 2 + 490 000e 0123 movs r3, #1 + 491 0010 4E4A ldr r2, .L50 + 492 0012 1374 strb r3, [r2, #16] + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 493 .loc 1 354 0 is_stmt 1 discriminator 2 + 494 0014 0268 ldr r2, [r0] + 495 0016 1342 tst r3, r2 + 496 0018 11D1 bne .L42 + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 497 .loc 1 345 0 + 498 001a 0120 movs r0, #1 + 499 .LVL55: + 500 .L31: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 501 .loc 1 371 0 + 502 001c 2368 ldr r3, [r4] + 503 001e 9B07 lsls r3, r3, #30 + 504 0020 18D4 bmi .L43 + 505 .LVL56: + 506 .L32: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 507 .loc 1 383 0 + 508 0022 2368 ldr r3, [r4] + 509 0024 5B07 lsls r3, r3, #29 + 510 0026 34D4 bmi .L44 + 511 .LVL57: + 512 .L34: + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 513 .loc 1 397 0 + 514 0028 2368 ldr r3, [r4] + 515 002a 1B07 lsls r3, r3, #28 + 516 002c 56D4 bmi .L45 + 517 .LVL58: + 518 .L36: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 519 .loc 1 409 0 + 520 002e 2368 ldr r3, [r4] + 521 0030 DB06 lsls r3, r3, #27 + 522 0032 00D5 bpl .LCB522 + 523 0034 6FE0 b .L46 @long jump + 524 .LCB522: + 525 .LVL59: + 526 .L38: + ARM GAS /tmp/cc9alhJF.s page 33 + + + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 527 .loc 1 414 0 + 528 0036 454B ldr r3, .L50 + 529 0038 0022 movs r2, #0 + 530 003a 1A74 strb r2, [r3, #16] + 531 .LVL60: + 532 .L30: + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 533 .loc 1 417 0 + 534 @ sp needed + 535 003c 70BD pop {r4, r5, r6, pc} + 536 .LVL61: + 537 .L42: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else + 538 .loc 1 358 0 + 539 003e 4268 ldr r2, [r0, #4] + 540 0040 C168 ldr r1, [r0, #12] + 541 0042 8068 ldr r0, [r0, #8] + 542 .LVL62: + 543 0044 FFF7FEFF bl FLASH_OB_ProtectedSectorsConfig + 544 .LVL63: + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 545 .loc 1 362 0 + 546 0048 0028 cmp r0, #0 + 547 004a E7D0 beq .L31 + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 548 .loc 1 365 0 + 549 004c 3F4B ldr r3, .L50 + 550 004e 0022 movs r2, #0 + 551 0050 1A74 strb r2, [r3, #16] + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 552 .loc 1 366 0 + 553 0052 F3E7 b .L30 + 554 .L43: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 555 .loc 1 373 0 + 556 0054 237C ldrb r3, [r4, #16] + 557 .LVL64: + 558 .LBB30: + 559 .LBB31: + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 560 .loc 1 838 0 + 561 0056 3E4A ldr r2, .L50+4 + 562 0058 1168 ldr r1, [r2] + 563 .LVL65: + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 564 .loc 1 842 0 + 565 005a 1268 ldr r2, [r2] + 566 005c 8021 movs r1, #128 + 567 005e 4900 lsls r1, r1, #1 + 568 0060 0A40 ands r2, r1 + 569 .LVL66: + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3))); + 570 .loc 1 846 0 + 571 0062 1343 orrs r3, r2 + 572 .LVL67: + 573 0064 DD43 mvns r5, r3 + ARM GAS /tmp/cc9alhJF.s page 34 + + + 574 .LVL68: + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 575 .loc 1 847 0 + 576 0066 2D04 lsls r5, r5, #16 + 577 .LVL69: + 578 0068 1D43 orrs r5, r3 + 579 .LVL70: + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 580 .loc 1 850 0 + 581 006a 3A48 ldr r0, .L50+8 + 582 .LVL71: + 583 006c FFF7FEFF bl FLASH_WaitForLastOperation + 584 .LVL72: + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 585 .loc 1 852 0 + 586 0070 0028 cmp r0, #0 + 587 0072 05D0 beq .L47 + 588 .LVL73: + 589 .L33: + 590 .LBE31: + 591 .LBE30: + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 592 .loc 1 374 0 + 593 0074 0028 cmp r0, #0 + 594 0076 D4D0 beq .L32 + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 595 .loc 1 377 0 + 596 0078 344B ldr r3, .L50 + 597 007a 0022 movs r2, #0 + 598 007c 1A74 strb r2, [r3, #16] + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 599 .loc 1 378 0 + 600 007e DDE7 b .L30 + 601 .LVL74: + 602 .L47: + 603 .LBB33: + 604 .LBB32: + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 605 .loc 1 855 0 + 606 0080 324B ldr r3, .L50 + 607 0082 0022 movs r2, #0 + 608 0084 5A61 str r2, [r3, #20] + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 609 .loc 1 858 0 + 610 0086 324B ldr r3, .L50+4 + 611 0088 1D60 str r5, [r3] + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 612 .loc 1 861 0 + 613 008a 3248 ldr r0, .L50+8 + 614 .LVL75: + 615 008c FFF7FEFF bl FLASH_WaitForLastOperation + 616 .LVL76: + 617 0090 F0E7 b .L33 + 618 .LVL77: + 619 .L44: + 620 .LBE32: + 621 .LBE33: + ARM GAS /tmp/cc9alhJF.s page 35 + + + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STOP_NORST, + 622 .loc 1 385 0 + 623 0092 A37C ldrb r3, [r4, #18] + 624 0094 1021 movs r1, #16 + 625 0096 1940 ands r1, r3 + 626 0098 2020 movs r0, #32 + 627 .LVL78: + 628 009a 1840 ands r0, r3 + 629 009c 4022 movs r2, #64 + 630 009e 1A40 ands r2, r3 + 631 .LVL79: + 632 .LBB34: + 633 .LBB35: +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 634 .loc 1 1147 0 + 635 00a0 2B4B ldr r3, .L50+4 + 636 00a2 5B68 ldr r3, [r3, #4] + 637 00a4 2C4D ldr r5, .L50+12 + 638 00a6 2B40 ands r3, r5 + 639 .LVL80: +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); + 640 .loc 1 1150 0 + 641 00a8 0143 orrs r1, r0 + 642 .LVL81: + 643 00aa 0A43 orrs r2, r1 + 644 .LVL82: + 645 00ac 1343 orrs r3, r2 + 646 .LVL83: + 647 00ae DD43 mvns r5, r3 + 648 00b0 2D04 lsls r5, r5, #16 + 649 .LVL84: +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 650 .loc 1 1151 0 + 651 00b2 1D43 orrs r5, r3 + 652 .LVL85: +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 653 .loc 1 1154 0 + 654 00b4 2748 ldr r0, .L50+8 + 655 .LVL86: + 656 00b6 FFF7FEFF bl FLASH_WaitForLastOperation + 657 .LVL87: +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 658 .loc 1 1156 0 + 659 00ba 0028 cmp r0, #0 + 660 00bc 05D0 beq .L48 + 661 .LVL88: + 662 .L35: + 663 .LBE35: + 664 .LBE34: + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 665 .loc 1 388 0 + 666 00be 0028 cmp r0, #0 + 667 00c0 B2D0 beq .L34 + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 668 .loc 1 391 0 + 669 00c2 224B ldr r3, .L50 + 670 00c4 0022 movs r2, #0 + ARM GAS /tmp/cc9alhJF.s page 36 + + + 671 00c6 1A74 strb r2, [r3, #16] + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 672 .loc 1 392 0 + 673 00c8 B8E7 b .L30 + 674 .LVL89: + 675 .L48: + 676 .LBB37: + 677 .LBB36: +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 678 .loc 1 1159 0 + 679 00ca 204B ldr r3, .L50 + 680 00cc 0022 movs r2, #0 + 681 00ce 5A61 str r2, [r3, #20] +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 682 .loc 1 1162 0 + 683 00d0 1F4B ldr r3, .L50+4 + 684 00d2 5D60 str r5, [r3, #4] +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 685 .loc 1 1165 0 + 686 00d4 1F48 ldr r0, .L50+8 + 687 .LVL90: + 688 00d6 FFF7FEFF bl FLASH_WaitForLastOperation + 689 .LVL91: + 690 00da F0E7 b .L35 + 691 .LVL92: + 692 .L45: + 693 .LBE36: + 694 .LBE37: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if (status != HAL_OK) + 695 .loc 1 399 0 + 696 00dc 637C ldrb r3, [r4, #17] + 697 .LVL93: + 698 .LBB38: + 699 .LBB39: + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 700 .loc 1 890 0 + 701 00de 1C4A ldr r2, .L50+4 + 702 00e0 5268 ldr r2, [r2, #4] + 703 00e2 1E49 ldr r1, .L50+16 + 704 00e4 0A40 ands r2, r1 + 705 .LVL94: + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= (OB_BOR | tmp1); + 706 .loc 1 893 0 + 707 00e6 1343 orrs r3, r2 + 708 .LVL95: + 709 00e8 DD43 mvns r5, r3 + 710 00ea 2D04 lsls r5, r5, #16 + 711 .LVL96: + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 712 .loc 1 894 0 + 713 00ec 1D43 orrs r5, r3 + 714 .LVL97: + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 715 .loc 1 897 0 + 716 00ee 1948 ldr r0, .L50+8 + 717 .LVL98: + 718 00f0 FFF7FEFF bl FLASH_WaitForLastOperation + ARM GAS /tmp/cc9alhJF.s page 37 + + + 719 .LVL99: + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 720 .loc 1 899 0 + 721 00f4 0028 cmp r0, #0 + 722 00f6 05D0 beq .L49 + 723 .LVL100: + 724 .L37: + 725 .LBE39: + 726 .LBE38: + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 727 .loc 1 400 0 + 728 00f8 0028 cmp r0, #0 + 729 00fa 98D0 beq .L36 + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** return status; + 730 .loc 1 403 0 + 731 00fc 134B ldr r3, .L50 + 732 00fe 0022 movs r2, #0 + 733 0100 1A74 strb r2, [r3, #16] + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 734 .loc 1 404 0 + 735 0102 9BE7 b .L30 + 736 .LVL101: + 737 .L49: + 738 .LBB41: + 739 .LBB40: + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 740 .loc 1 902 0 + 741 0104 114B ldr r3, .L50 + 742 0106 0022 movs r2, #0 + 743 0108 5A61 str r2, [r3, #20] + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 744 .loc 1 905 0 + 745 010a 114B ldr r3, .L50+4 + 746 010c 5D60 str r5, [r3, #4] + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 747 .loc 1 908 0 + 748 010e 1148 ldr r0, .L50+8 + 749 .LVL102: + 750 0110 FFF7FEFF bl FLASH_WaitForLastOperation + 751 .LVL103: + 752 0114 F0E7 b .L37 + 753 .LVL104: + 754 .L46: + 755 .LBE40: + 756 .LBE41: + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 757 .loc 1 411 0 + 758 0116 E37C ldrb r3, [r4, #19] + 759 .LVL105: + 760 .LBB42: + 761 .LBB43: + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 762 .loc 1 926 0 + 763 0118 DB03 lsls r3, r3, #15 + 764 .LVL106: + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 765 .loc 1 932 0 + ARM GAS /tmp/cc9alhJF.s page 38 + + + 766 011a 0D4A ldr r2, .L50+4 + 767 011c 5268 ldr r2, [r2, #4] + 768 011e 5204 lsls r2, r2, #17 + 769 0120 520C lsrs r2, r2, #17 + 770 .LVL107: + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= OB_Bits | tmp1; + 771 .loc 1 935 0 + 772 0122 1343 orrs r3, r2 + 773 .LVL108: + 774 0124 DC43 mvns r4, r3 + 775 .LVL109: + 776 0126 2404 lsls r4, r4, #16 + 777 .LVL110: + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 778 .loc 1 936 0 + 779 0128 1C43 orrs r4, r3 + 780 .LVL111: + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 781 .loc 1 939 0 + 782 012a 0A48 ldr r0, .L50+8 + 783 .LVL112: + 784 012c FFF7FEFF bl FLASH_WaitForLastOperation + 785 .LVL113: + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 786 .loc 1 941 0 + 787 0130 0028 cmp r0, #0 + 788 0132 00D0 beq .LCB858 + 789 0134 7FE7 b .L38 @long jump + 790 .LCB858: + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Program OB */ + 791 .loc 1 944 0 + 792 0136 054B ldr r3, .L50 + 793 0138 0022 movs r2, #0 + 794 013a 5A61 str r2, [r3, #20] + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 795 .loc 1 946 0 + 796 013c 044B ldr r3, .L50+4 + 797 013e 5C60 str r4, [r3, #4] + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 798 .loc 1 948 0 + 799 0140 0448 ldr r0, .L50+8 + 800 .LVL114: + 801 0142 FFF7FEFF bl FLASH_WaitForLastOperation + 802 .LVL115: + 803 0146 76E7 b .L38 + 804 .LVL116: + 805 .L40: + 806 .LBE43: + 807 .LBE42: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 808 .loc 1 348 0 + 809 0148 0220 movs r0, #2 + 810 .LVL117: + 811 014a 77E7 b .L30 + 812 .L51: + 813 .align 2 + 814 .L50: + ARM GAS /tmp/cc9alhJF.s page 39 + + + 815 014c 00000000 .word pFlash + 816 0150 0000F81F .word 536346624 + 817 0154 50C30000 .word 50000 + 818 0158 8FFF0000 .word 65423 + 819 015c F0FF0000 .word 65520 + 820 .cfi_endproc + 821 .LFE41: + 823 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 824 .align 1 + 825 .global HAL_FLASHEx_OBGetConfig + 826 .syntax unified + 827 .code 16 + 828 .thumb_func + 829 .fpu softvfp + 831 HAL_FLASHEx_OBGetConfig: + 832 .LFB42: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + 833 .loc 1 427 0 + 834 .cfi_startproc + 835 @ args = 0, pretend = 0, frame = 0 + 836 @ frame_needed = 0, uses_anonymous_args = 0 + 837 @ link register save eliminated. + 838 .LVL118: + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 839 .loc 1 428 0 + 840 0000 0F23 movs r3, #15 + 841 0002 0360 str r3, [r0] + 842 .LBB44: + 843 .LBB45: +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 844 .loc 1 1005 0 + 845 0004 0A4B ldr r3, .L53 + 846 0006 1A6A ldr r2, [r3, #32] + 847 .LBE45: + 848 .LBE44: + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 849 .loc 1 431 0 + 850 0008 8260 str r2, [r0, #8] + 851 .LBB46: + 852 .LBB47: +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 853 .loc 1 1016 0 + 854 000a 8022 movs r2, #128 + 855 000c 9A58 ldr r2, [r3, r2] + 856 .LBE47: + 857 .LBE46: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 858 .loc 1 434 0 + 859 000e C260 str r2, [r0, #12] + 860 .LBB48: + 861 .LBB49: + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 862 .loc 1 974 0 + 863 0010 DA69 ldr r2, [r3, #28] + 864 .LBE49: + 865 .LBE48: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9alhJF.s page 40 + + + 866 .loc 1 438 0 + 867 0012 0274 strb r2, [r0, #16] + 868 .LBB50: + 869 .LBB51: + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 870 .loc 1 961 0 + 871 0014 D969 ldr r1, [r3, #28] + 872 0016 090C lsrs r1, r1, #16 + 873 0018 7022 movs r2, #112 + 874 001a 0A40 ands r2, r1 + 875 .LBE51: + 876 .LBE50: + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 877 .loc 1 441 0 + 878 001c 8274 strb r2, [r0, #18] + 879 .LBB52: + 880 .LBB53: + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 881 .loc 1 984 0 + 882 001e D969 ldr r1, [r3, #28] + 883 0020 090C lsrs r1, r1, #16 + 884 0022 0F22 movs r2, #15 + 885 0024 0A40 ands r2, r1 + 886 .LBE53: + 887 .LBE52: + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 888 .loc 1 444 0 + 889 0026 4274 strb r2, [r0, #17] + 890 .LBB54: + 891 .LBB55: + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 892 .loc 1 994 0 + 893 0028 DB69 ldr r3, [r3, #28] + 894 002a DB0F lsrs r3, r3, #31 + 895 .LBE55: + 896 .LBE54: + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 897 .loc 1 447 0 + 898 002c C374 strb r3, [r0, #19] + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 899 .loc 1 448 0 + 900 @ sp needed + 901 002e 7047 bx lr + 902 .L54: + 903 .align 2 + 904 .L53: + 905 0030 00200240 .word 1073881088 + 906 .cfi_endproc + 907 .LFE42: + 909 .section .text.HAL_FLASHEx_AdvOBProgram,"ax",%progbits + 910 .align 1 + 911 .global HAL_FLASHEx_AdvOBProgram + 912 .syntax unified + 913 .code 16 + 914 .thumb_func + 915 .fpu softvfp + 917 HAL_FLASHEx_AdvOBProgram: + ARM GAS /tmp/cc9alhJF.s page 41 + + + 918 .LFB43: + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 919 .loc 1 460 0 + 920 .cfi_startproc + 921 @ args = 0, pretend = 0, frame = 0 + 922 @ frame_needed = 0, uses_anonymous_args = 0 + 923 .LVL119: + 924 0000 10B5 push {r4, lr} + 925 .LCFI5: + 926 .cfi_def_cfa_offset 8 + 927 .cfi_offset 4, -8 + 928 .cfi_offset 14, -4 + 929 0002 0400 movs r4, r0 + 930 .LVL120: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 931 .loc 1 469 0 + 932 0004 0368 ldr r3, [r0] + 933 0006 DB07 lsls r3, r3, #31 + 934 0008 04D4 bmi .L60 + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 935 .loc 1 461 0 + 936 000a 0120 movs r0, #1 + 937 .LVL121: + 938 .L56: + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 939 .loc 1 485 0 + 940 000c 2368 ldr r3, [r4] + 941 000e 9B07 lsls r3, r3, #30 + 942 0010 06D4 bmi .L61 + 943 .LVL122: + 944 .L57: + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 945 .loc 1 493 0 + 946 @ sp needed + 947 0012 10BD pop {r4, pc} + 948 .LVL123: + 949 .L60: + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #else + 950 .loc 1 474 0 + 951 0014 4268 ldr r2, [r0, #4] + 952 0016 C168 ldr r1, [r0, #12] + 953 0018 8068 ldr r0, [r0, #8] + 954 .LVL124: + 955 001a FFF7FEFF bl FLASH_OB_ProtectedSectorsConfig + 956 .LVL125: + 957 001e F5E7 b .L56 + 958 .L61: + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 959 .loc 1 487 0 + 960 0020 237C ldrb r3, [r4, #16] + 961 .LVL126: + 962 .LBB58: + 963 .LBB59: +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 964 .loc 1 1191 0 + 965 0022 0B4A ldr r2, .L62 + 966 0024 5268 ldr r2, [r2, #4] + ARM GAS /tmp/cc9alhJF.s page 42 + + + 967 0026 0B49 ldr r1, .L62+4 + 968 0028 0A40 ands r2, r1 + 969 .LVL127: +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp |= (OB_BOOT | tmp1); + 970 .loc 1 1194 0 + 971 002a 1343 orrs r3, r2 + 972 .LVL128: + 973 002c DC43 mvns r4, r3 + 974 .LVL129: + 975 002e 2404 lsls r4, r4, #16 + 976 .LVL130: +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 977 .loc 1 1195 0 + 978 0030 1C43 orrs r4, r3 + 979 .LVL131: +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 980 .loc 1 1198 0 + 981 0032 0948 ldr r0, .L62+8 + 982 .LVL132: + 983 0034 FFF7FEFF bl FLASH_WaitForLastOperation + 984 .LVL133: +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 985 .loc 1 1200 0 + 986 0038 0028 cmp r0, #0 + 987 003a EAD1 bne .L57 +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 988 .loc 1 1203 0 + 989 003c 074B ldr r3, .L62+12 + 990 003e 0022 movs r2, #0 + 991 0040 5A61 str r2, [r3, #20] +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 992 .loc 1 1206 0 + 993 0042 034B ldr r3, .L62 + 994 0044 5C60 str r4, [r3, #4] +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 995 .loc 1 1209 0 + 996 0046 0448 ldr r0, .L62+8 + 997 .LVL134: + 998 0048 FFF7FEFF bl FLASH_WaitForLastOperation + 999 .LVL135: + 1000 004c E1E7 b .L57 + 1001 .L63: + 1002 004e C046 .align 2 + 1003 .L62: + 1004 0050 0000F81F .word 536346624 + 1005 0054 7FFF0000 .word 65407 + 1006 0058 50C30000 .word 50000 + 1007 005c 00000000 .word pFlash + 1008 .LBE59: + 1009 .LBE58: + 1010 .cfi_endproc + 1011 .LFE43: + 1013 .section .text.HAL_FLASHEx_AdvOBGetConfig,"ax",%progbits + 1014 .align 1 + 1015 .global HAL_FLASHEx_AdvOBGetConfig + 1016 .syntax unified + 1017 .code 16 + ARM GAS /tmp/cc9alhJF.s page 43 + + + 1018 .thumb_func + 1019 .fpu softvfp + 1021 HAL_FLASHEx_AdvOBGetConfig: + 1022 .LFB44: + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** pAdvOBInit->OptionType = 0; + 1023 .loc 1 503 0 + 1024 .cfi_startproc + 1025 @ args = 0, pretend = 0, frame = 0 + 1026 @ frame_needed = 0, uses_anonymous_args = 0 + 1027 @ link register save eliminated. + 1028 .LVL136: + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1029 .loc 1 508 0 + 1030 0000 0122 movs r2, #1 + 1031 0002 0260 str r2, [r0] + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Get PCROP protected sector */ + 1032 .loc 1 512 0 + 1033 0004 084B ldr r3, .L65 + 1034 0006 D969 ldr r1, [r3, #28] + 1035 0008 090A lsrs r1, r1, #8 + 1036 000a 0A40 ands r2, r1 + 1037 000c 4260 str r2, [r0, #4] + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1038 .loc 1 514 0 + 1039 000e 1A6A ldr r2, [r3, #32] + 1040 0010 8260 str r2, [r0, #8] + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** #endif + 1041 .loc 1 518 0 + 1042 0012 8022 movs r2, #128 + 1043 0014 9A58 ldr r2, [r3, r2] + 1044 0016 C260 str r2, [r0, #12] + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1045 .loc 1 524 0 + 1046 0018 0322 movs r2, #3 + 1047 001a 0260 str r2, [r0] + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1048 .loc 1 527 0 + 1049 001c DA69 ldr r2, [r3, #28] + 1050 001e 120C lsrs r2, r2, #16 + 1051 0020 8023 movs r3, #128 + 1052 0022 1340 ands r3, r2 + 1053 0024 0382 strh r3, [r0, #16] + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1054 .loc 1 530 0 + 1055 @ sp needed + 1056 0026 7047 bx lr + 1057 .L66: + 1058 .align 2 + 1059 .L65: + 1060 0028 00200240 .word 1073881088 + 1061 .cfi_endproc + 1062 .LFE44: + 1064 .section .text.HAL_FLASHEx_OB_SelectPCROP,"ax",%progbits + 1065 .align 1 + 1066 .global HAL_FLASHEx_OB_SelectPCROP + 1067 .syntax unified + 1068 .code 16 + ARM GAS /tmp/cc9alhJF.s page 44 + + + 1069 .thumb_func + 1070 .fpu softvfp + 1072 HAL_FLASHEx_OB_SelectPCROP: + 1073 .LFB45: + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1074 .loc 1 543 0 + 1075 .cfi_startproc + 1076 @ args = 0, pretend = 0, frame = 0 + 1077 @ frame_needed = 0, uses_anonymous_args = 0 + 1078 0000 10B5 push {r4, lr} + 1079 .LCFI6: + 1080 .cfi_def_cfa_offset 8 + 1081 .cfi_offset 4, -8 + 1082 .cfi_offset 14, -4 + 1083 .LVL137: + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1084 .loc 1 550 0 + 1085 0002 0B48 ldr r0, .L70 + 1086 0004 FFF7FEFF bl FLASH_WaitForLastOperation + 1087 .LVL138: + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1088 .loc 1 553 0 + 1089 0008 0A4B ldr r3, .L70+4 + 1090 000a 1B78 ldrb r3, [r3] + 1091 .LVL139: + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1092 .loc 1 556 0 + 1093 000c 8022 movs r2, #128 + 1094 000e 5200 lsls r2, r2, #1 + 1095 0010 1A43 orrs r2, r3 + 1096 .LVL140: + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + 1097 .loc 1 559 0 + 1098 0012 D343 mvns r3, r2 + 1099 .LVL141: + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1100 .loc 1 560 0 + 1101 0014 1B04 lsls r3, r3, #16 + 1102 .LVL142: + 1103 0016 1343 orrs r3, r2 + 1104 .LVL143: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1105 .loc 1 562 0 + 1106 0018 0028 cmp r0, #0 + 1107 001a 00D0 beq .L69 + 1108 .LVL144: + 1109 .L68: + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1110 .loc 1 576 0 + 1111 @ sp needed + 1112 001c 10BD pop {r4, pc} + 1113 .LVL145: + 1114 .L69: + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1115 .loc 1 565 0 + 1116 001e 064A ldr r2, .L70+8 + 1117 .LVL146: + ARM GAS /tmp/cc9alhJF.s page 45 + + + 1118 0020 0021 movs r1, #0 + 1119 0022 5161 str r1, [r2, #20] + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1120 .loc 1 568 0 + 1121 0024 034A ldr r2, .L70+4 + 1122 0026 1360 str r3, [r2] + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1123 .loc 1 571 0 + 1124 0028 0148 ldr r0, .L70 + 1125 .LVL147: + 1126 002a FFF7FEFF bl FLASH_WaitForLastOperation + 1127 .LVL148: + 1128 002e F5E7 b .L68 + 1129 .L71: + 1130 .align 2 + 1131 .L70: + 1132 0030 50C30000 .word 50000 + 1133 0034 0000F81F .word 536346624 + 1134 0038 00000000 .word pFlash + 1135 .cfi_endproc + 1136 .LFE45: + 1138 .section .text.HAL_FLASHEx_OB_DeSelectPCROP,"ax",%progbits + 1139 .align 1 + 1140 .global HAL_FLASHEx_OB_DeSelectPCROP + 1141 .syntax unified + 1142 .code 16 + 1143 .thumb_func + 1144 .fpu softvfp + 1146 HAL_FLASHEx_OB_DeSelectPCROP: + 1147 .LFB46: + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1148 .loc 1 585 0 + 1149 .cfi_startproc + 1150 @ args = 0, pretend = 0, frame = 0 + 1151 @ frame_needed = 0, uses_anonymous_args = 0 + 1152 0000 10B5 push {r4, lr} + 1153 .LCFI7: + 1154 .cfi_def_cfa_offset 8 + 1155 .cfi_offset 4, -8 + 1156 .cfi_offset 14, -4 + 1157 .LVL149: + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1158 .loc 1 592 0 + 1159 0002 0A48 ldr r0, .L75 + 1160 0004 FFF7FEFF bl FLASH_WaitForLastOperation + 1161 .LVL150: + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1162 .loc 1 595 0 + 1163 0008 094B ldr r3, .L75+4 + 1164 000a 1A78 ldrb r2, [r3] + 1165 000c D2B2 uxtb r2, r2 + 1166 .LVL151: + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + 1167 .loc 1 601 0 + 1168 000e D343 mvns r3, r2 + 1169 .LVL152: + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9alhJF.s page 46 + + + 1170 .loc 1 602 0 + 1171 0010 1B04 lsls r3, r3, #16 + 1172 .LVL153: + 1173 0012 1343 orrs r3, r2 + 1174 .LVL154: + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1175 .loc 1 604 0 + 1176 0014 0028 cmp r0, #0 + 1177 0016 00D0 beq .L74 + 1178 .LVL155: + 1179 .L73: + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1180 .loc 1 618 0 + 1181 @ sp needed + 1182 0018 10BD pop {r4, pc} + 1183 .LVL156: + 1184 .L74: + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1185 .loc 1 607 0 + 1186 001a 064A ldr r2, .L75+8 + 1187 .LVL157: + 1188 001c 0021 movs r1, #0 + 1189 001e 5161 str r1, [r2, #20] + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1190 .loc 1 610 0 + 1191 0020 034A ldr r2, .L75+4 + 1192 0022 1360 str r3, [r2] + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1193 .loc 1 613 0 + 1194 0024 0148 ldr r0, .L75 + 1195 .LVL158: + 1196 0026 FFF7FEFF bl FLASH_WaitForLastOperation + 1197 .LVL159: + 1198 002a F5E7 b .L73 + 1199 .L76: + 1200 .align 2 + 1201 .L75: + 1202 002c 50C30000 .word 50000 + 1203 0030 0000F81F .word 536346624 + 1204 0034 00000000 .word pFlash + 1205 .cfi_endproc + 1206 .LFE46: + 1208 .section .text.HAL_FLASHEx_DATAEEPROM_Unlock,"ax",%progbits + 1209 .align 1 + 1210 .global HAL_FLASHEx_DATAEEPROM_Unlock + 1211 .syntax unified + 1212 .code 16 + 1213 .thumb_func + 1214 .fpu softvfp + 1216 HAL_FLASHEx_DATAEEPROM_Unlock: + 1217 .LFB47: + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + 1218 .loc 1 651 0 + 1219 .cfi_startproc + 1220 @ args = 0, pretend = 0, frame = 0 + 1221 @ frame_needed = 0, uses_anonymous_args = 0 + 1222 @ link register save eliminated. + ARM GAS /tmp/cc9alhJF.s page 47 + + + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1223 .loc 1 652 0 + 1224 0000 064B ldr r3, .L80 + 1225 0002 5B68 ldr r3, [r3, #4] + 1226 0004 DB07 lsls r3, r3, #31 + 1227 0006 06D5 bpl .L79 + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** FLASH->PEKEYR = FLASH_PEKEY2; + 1228 .loc 1 655 0 + 1229 0008 044B ldr r3, .L80 + 1230 000a 054A ldr r2, .L80+4 + 1231 000c DA60 str r2, [r3, #12] + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1232 .loc 1 656 0 + 1233 000e 054A ldr r2, .L80+8 + 1234 0010 DA60 str r2, [r3, #12] + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1235 .loc 1 662 0 + 1236 0012 0020 movs r0, #0 + 1237 .L78: + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1238 .loc 1 663 0 + 1239 @ sp needed + 1240 0014 7047 bx lr + 1241 .L79: + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1242 .loc 1 660 0 + 1243 0016 0120 movs r0, #1 + 1244 0018 FCE7 b .L78 + 1245 .L81: + 1246 001a C046 .align 2 + 1247 .L80: + 1248 001c 00200240 .word 1073881088 + 1249 0020 EFCDAB89 .word -1985229329 + 1250 0024 05040302 .word 33752069 + 1251 .cfi_endproc + 1252 .LFE47: + 1254 .section .text.HAL_FLASHEx_DATAEEPROM_Lock,"ax",%progbits + 1255 .align 1 + 1256 .global HAL_FLASHEx_DATAEEPROM_Lock + 1257 .syntax unified + 1258 .code 16 + 1259 .thumb_func + 1260 .fpu softvfp + 1262 HAL_FLASHEx_DATAEEPROM_Lock: + 1263 .LFB48: + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ + 1264 .loc 1 670 0 + 1265 .cfi_startproc + 1266 @ args = 0, pretend = 0, frame = 0 + 1267 @ frame_needed = 0, uses_anonymous_args = 0 + 1268 @ link register save eliminated. + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1269 .loc 1 672 0 + 1270 0000 034A ldr r2, .L83 + 1271 0002 5368 ldr r3, [r2, #4] + 1272 0004 0121 movs r1, #1 + 1273 0006 0B43 orrs r3, r1 + ARM GAS /tmp/cc9alhJF.s page 48 + + + 1274 0008 5360 str r3, [r2, #4] + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1275 .loc 1 675 0 + 1276 000a 0020 movs r0, #0 + 1277 @ sp needed + 1278 000c 7047 bx lr + 1279 .L84: + 1280 000e C046 .align 2 + 1281 .L83: + 1282 0010 00200240 .word 1073881088 + 1283 .cfi_endproc + 1284 .LFE48: + 1286 .section .text.HAL_FLASHEx_DATAEEPROM_Erase,"ax",%progbits + 1287 .align 1 + 1288 .global HAL_FLASHEx_DATAEEPROM_Erase + 1289 .syntax unified + 1290 .code 16 + 1291 .thumb_func + 1292 .fpu softvfp + 1294 HAL_FLASHEx_DATAEEPROM_Erase: + 1295 .LFB49: + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1296 .loc 1 688 0 + 1297 .cfi_startproc + 1298 @ args = 0, pretend = 0, frame = 0 + 1299 @ frame_needed = 0, uses_anonymous_args = 0 + 1300 .LVL160: + 1301 0000 10B5 push {r4, lr} + 1302 .LCFI8: + 1303 .cfi_def_cfa_offset 8 + 1304 .cfi_offset 4, -8 + 1305 .cfi_offset 14, -4 + 1306 0002 0400 movs r4, r0 + 1307 .LVL161: + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1308 .loc 1 695 0 + 1309 0004 0648 ldr r0, .L88 + 1310 .LVL162: + 1311 0006 FFF7FEFF bl FLASH_WaitForLastOperation + 1312 .LVL163: + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1313 .loc 1 697 0 + 1314 000a 0028 cmp r0, #0 + 1315 000c 00D0 beq .L87 + 1316 .LVL164: + 1317 .L86: + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1318 .loc 1 710 0 + 1319 @ sp needed + 1320 .LVL165: + 1321 000e 10BD pop {r4, pc} + 1322 .LVL166: + 1323 .L87: + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1324 .loc 1 700 0 + 1325 0010 0023 movs r3, #0 + 1326 0012 044A ldr r2, .L88+4 + ARM GAS /tmp/cc9alhJF.s page 49 + + + 1327 0014 5361 str r3, [r2, #20] + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1328 .loc 1 703 0 + 1329 0016 2360 str r3, [r4] + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1330 .loc 1 705 0 + 1331 0018 0148 ldr r0, .L88 + 1332 .LVL167: + 1333 001a FFF7FEFF bl FLASH_WaitForLastOperation + 1334 .LVL168: + 1335 001e F6E7 b .L86 + 1336 .L89: + 1337 .align 2 + 1338 .L88: + 1339 0020 50C30000 .word 50000 + 1340 0024 00000000 .word pFlash + 1341 .cfi_endproc + 1342 .LFE49: + 1344 .section .text.HAL_FLASHEx_DATAEEPROM_Program,"ax",%progbits + 1345 .align 1 + 1346 .global HAL_FLASHEx_DATAEEPROM_Program + 1347 .syntax unified + 1348 .code 16 + 1349 .thumb_func + 1350 .fpu softvfp + 1352 HAL_FLASHEx_DATAEEPROM_Program: + 1353 .LFB50: + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1354 .loc 1 730 0 + 1355 .cfi_startproc + 1356 @ args = 0, pretend = 0, frame = 0 + 1357 @ frame_needed = 0, uses_anonymous_args = 0 + 1358 .LVL169: + 1359 0000 70B5 push {r4, r5, r6, lr} + 1360 .LCFI9: + 1361 .cfi_def_cfa_offset 16 + 1362 .cfi_offset 4, -16 + 1363 .cfi_offset 5, -12 + 1364 .cfi_offset 6, -8 + 1365 .cfi_offset 14, -4 + 1366 0002 0400 movs r4, r0 + 1367 0004 0E00 movs r6, r1 + 1368 0006 1500 movs r5, r2 + 1369 .LVL170: + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1370 .loc 1 734 0 + 1371 0008 124B ldr r3, .L100 + 1372 000a 1B7C ldrb r3, [r3, #16] + 1373 000c 012B cmp r3, #1 + 1374 000e 1FD0 beq .L96 + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1375 .loc 1 734 0 is_stmt 0 discriminator 2 + 1376 0010 104B ldr r3, .L100 + 1377 0012 0122 movs r2, #1 + 1378 .LVL171: + 1379 0014 1A74 strb r2, [r3, #16] + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9alhJF.s page 50 + + + 1380 .loc 1 741 0 is_stmt 1 discriminator 2 + 1381 0016 1048 ldr r0, .L100+4 + 1382 .LVL172: + 1383 0018 FFF7FEFF bl FLASH_WaitForLastOperation + 1384 .LVL173: + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1385 .loc 1 743 0 discriminator 2 + 1386 001c 0028 cmp r0, #0 + 1387 001e 0CD1 bne .L92 + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1388 .loc 1 746 0 + 1389 0020 0C4B ldr r3, .L100 + 1390 0022 0022 movs r2, #0 + 1391 0024 5A61 str r2, [r3, #20] + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1392 .loc 1 748 0 + 1393 0026 022C cmp r4, #2 + 1394 0028 06D0 beq .L97 + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1395 .loc 1 753 0 + 1396 002a 012C cmp r4, #1 + 1397 002c 09D0 beq .L98 + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** { + 1398 .loc 1 758 0 + 1399 002e 002C cmp r4, #0 + 1400 0030 0AD1 bne .L99 + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1401 .loc 1 761 0 + 1402 0032 EDB2 uxtb r5, r5 + 1403 .LVL174: + 1404 0034 3570 strb r5, [r6] + 1405 0036 00E0 b .L92 + 1406 .LVL175: + 1407 .L97: + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1408 .loc 1 751 0 + 1409 0038 3560 str r5, [r6] + 1410 .LVL176: + 1411 .L92: + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1412 .loc 1 776 0 + 1413 003a 064B ldr r3, .L100 + 1414 003c 0022 movs r2, #0 + 1415 003e 1A74 strb r2, [r3, #16] + 1416 .LVL177: + 1417 .L91: + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1418 .loc 1 779 0 + 1419 @ sp needed + 1420 .LVL178: + 1421 .LVL179: + 1422 0040 70BD pop {r4, r5, r6, pc} + 1423 .LVL180: + 1424 .L98: + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1425 .loc 1 756 0 + 1426 0042 ADB2 uxth r5, r5 + ARM GAS /tmp/cc9alhJF.s page 51 + + + 1427 .LVL181: + 1428 0044 3580 strh r5, [r6] + 1429 0046 F8E7 b .L92 + 1430 .LVL182: + 1431 .L99: + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1432 .loc 1 771 0 + 1433 0048 0348 ldr r0, .L100+4 + 1434 004a FFF7FEFF bl FLASH_WaitForLastOperation + 1435 .LVL183: + 1436 004e F4E7 b .L92 + 1437 .LVL184: + 1438 .L96: + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1439 .loc 1 734 0 + 1440 0050 0220 movs r0, #2 + 1441 .LVL185: + 1442 0052 F5E7 b .L91 + 1443 .L101: + 1444 .align 2 + 1445 .L100: + 1446 0054 00000000 .word pFlash + 1447 0058 50C30000 .word 50000 + 1448 .cfi_endproc + 1449 .LFE50: + 1451 .section .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram,"ax",%progbits + 1452 .align 1 + 1453 .global HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram + 1454 .syntax unified + 1455 .code 16 + 1456 .thumb_func + 1457 .fpu softvfp + 1459 HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram: + 1460 .LFB51: + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** SET_BIT(FLASH->PECR, FLASH_PECR_FIX); + 1461 .loc 1 786 0 + 1462 .cfi_startproc + 1463 @ args = 0, pretend = 0, frame = 0 + 1464 @ frame_needed = 0, uses_anonymous_args = 0 + 1465 @ link register save eliminated. + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1466 .loc 1 787 0 + 1467 0000 034A ldr r2, .L103 + 1468 0002 5168 ldr r1, [r2, #4] + 1469 0004 8023 movs r3, #128 + 1470 0006 5B00 lsls r3, r3, #1 + 1471 0008 0B43 orrs r3, r1 + 1472 000a 5360 str r3, [r2, #4] + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1473 .loc 1 788 0 + 1474 @ sp needed + 1475 000c 7047 bx lr + 1476 .L104: + 1477 000e C046 .align 2 + 1478 .L103: + 1479 0010 00200240 .word 1073881088 + 1480 .cfi_endproc + ARM GAS /tmp/cc9alhJF.s page 52 + + + 1481 .LFE51: + 1483 .section .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram,"ax",%progbits + 1484 .align 1 + 1485 .global HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram + 1486 .syntax unified + 1487 .code 16 + 1488 .thumb_func + 1489 .fpu softvfp + 1491 HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram: + 1492 .LFB52: + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FIX); + 1493 .loc 1 795 0 + 1494 .cfi_startproc + 1495 @ args = 0, pretend = 0, frame = 0 + 1496 @ frame_needed = 0, uses_anonymous_args = 0 + 1497 @ link register save eliminated. + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1498 .loc 1 796 0 + 1499 0000 024A ldr r2, .L106 + 1500 0002 5368 ldr r3, [r2, #4] + 1501 0004 0249 ldr r1, .L106+4 + 1502 0006 0B40 ands r3, r1 + 1503 0008 5360 str r3, [r2, #4] + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1504 .loc 1 797 0 + 1505 @ sp needed + 1506 000a 7047 bx lr + 1507 .L107: + 1508 .align 2 + 1509 .L106: + 1510 000c 00200240 .word 1073881088 + 1511 0010 FFFEFFFF .word -257 + 1512 .cfi_endproc + 1513 .LFE52: + 1515 .section .text.FLASH_PageErase,"ax",%progbits + 1516 .align 1 + 1517 .global FLASH_PageErase + 1518 .syntax unified + 1519 .code 16 + 1520 .thumb_func + 1521 .fpu softvfp + 1523 FLASH_PageErase: + 1524 .LFB65: +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** /* Clean the error context */ + 1525 .loc 1 1243 0 + 1526 .cfi_startproc + 1527 @ args = 0, pretend = 0, frame = 0 + 1528 @ frame_needed = 0, uses_anonymous_args = 0 + 1529 .LVL186: + 1530 0000 10B5 push {r4, lr} + 1531 .LCFI10: + 1532 .cfi_def_cfa_offset 8 + 1533 .cfi_offset 4, -8 + 1534 .cfi_offset 14, -4 +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1535 .loc 1 1245 0 + 1536 0002 0021 movs r1, #0 + ARM GAS /tmp/cc9alhJF.s page 53 + + + 1537 0004 074B ldr r3, .L109 + 1538 0006 5961 str r1, [r3, #20] +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1539 .loc 1 1248 0 + 1540 0008 074B ldr r3, .L109+4 + 1541 000a 5C68 ldr r4, [r3, #4] + 1542 000c 8022 movs r2, #128 + 1543 000e 9200 lsls r2, r2, #2 + 1544 0010 2243 orrs r2, r4 + 1545 0012 5A60 str r2, [r3, #4] +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** + 1546 .loc 1 1251 0 + 1547 0014 5A68 ldr r2, [r3, #4] + 1548 0016 0824 movs r4, #8 + 1549 0018 2243 orrs r2, r4 + 1550 001a 5A60 str r2, [r3, #4] + 1551 .loc 1 1254 0 + 1552 001c 7F23 movs r3, #127 + 1553 001e 9843 bics r0, r3 + 1554 .LVL187: + 1555 0020 0160 str r1, [r0] +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c **** } + 1556 .loc 1 1255 0 + 1557 @ sp needed + 1558 0022 10BD pop {r4, pc} + 1559 .L110: + 1560 .align 2 + 1561 .L109: + 1562 0024 00000000 .word pFlash + 1563 0028 00200240 .word 1073881088 + 1564 .cfi_endproc + 1565 .LFE65: + 1567 .text + 1568 .Letext0: + 1569 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1570 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1571 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1572 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1573 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 1574 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 1575 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1576 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 1577 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1578 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 1579 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h" + 1580 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h" + ARM GAS /tmp/cc9alhJF.s page 54 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_flash_ex.c + /tmp/cc9alhJF.s:16 .text.FLASH_OB_ProtectedSectorsConfig:0000000000000000 $t + /tmp/cc9alhJF.s:22 .text.FLASH_OB_ProtectedSectorsConfig:0000000000000000 FLASH_OB_ProtectedSectorsConfig + /tmp/cc9alhJF.s:182 .text.FLASH_OB_ProtectedSectorsConfig:00000000000000b0 $d + /tmp/cc9alhJF.s:189 .text.HAL_FLASHEx_Erase:0000000000000000 $t + /tmp/cc9alhJF.s:196 .text.HAL_FLASHEx_Erase:0000000000000000 HAL_FLASHEx_Erase + /tmp/cc9alhJF.s:330 .text.HAL_FLASHEx_Erase:000000000000008c $d + /tmp/cc9alhJF.s:338 .text.HAL_FLASHEx_Erase_IT:0000000000000000 $t + /tmp/cc9alhJF.s:345 .text.HAL_FLASHEx_Erase_IT:0000000000000000 HAL_FLASHEx_Erase_IT + /tmp/cc9alhJF.s:452 .text.HAL_FLASHEx_Erase_IT:0000000000000070 $d + /tmp/cc9alhJF.s:459 .text.HAL_FLASHEx_OBProgram:0000000000000000 $t + /tmp/cc9alhJF.s:466 .text.HAL_FLASHEx_OBProgram:0000000000000000 HAL_FLASHEx_OBProgram + /tmp/cc9alhJF.s:815 .text.HAL_FLASHEx_OBProgram:000000000000014c $d + /tmp/cc9alhJF.s:824 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 $t + /tmp/cc9alhJF.s:831 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 HAL_FLASHEx_OBGetConfig + /tmp/cc9alhJF.s:905 .text.HAL_FLASHEx_OBGetConfig:0000000000000030 $d + /tmp/cc9alhJF.s:910 .text.HAL_FLASHEx_AdvOBProgram:0000000000000000 $t + /tmp/cc9alhJF.s:917 .text.HAL_FLASHEx_AdvOBProgram:0000000000000000 HAL_FLASHEx_AdvOBProgram + /tmp/cc9alhJF.s:1004 .text.HAL_FLASHEx_AdvOBProgram:0000000000000050 $d + /tmp/cc9alhJF.s:1014 .text.HAL_FLASHEx_AdvOBGetConfig:0000000000000000 $t + /tmp/cc9alhJF.s:1021 .text.HAL_FLASHEx_AdvOBGetConfig:0000000000000000 HAL_FLASHEx_AdvOBGetConfig + /tmp/cc9alhJF.s:1060 .text.HAL_FLASHEx_AdvOBGetConfig:0000000000000028 $d + /tmp/cc9alhJF.s:1065 .text.HAL_FLASHEx_OB_SelectPCROP:0000000000000000 $t + /tmp/cc9alhJF.s:1072 .text.HAL_FLASHEx_OB_SelectPCROP:0000000000000000 HAL_FLASHEx_OB_SelectPCROP + /tmp/cc9alhJF.s:1132 .text.HAL_FLASHEx_OB_SelectPCROP:0000000000000030 $d + /tmp/cc9alhJF.s:1139 .text.HAL_FLASHEx_OB_DeSelectPCROP:0000000000000000 $t + /tmp/cc9alhJF.s:1146 .text.HAL_FLASHEx_OB_DeSelectPCROP:0000000000000000 HAL_FLASHEx_OB_DeSelectPCROP + /tmp/cc9alhJF.s:1202 .text.HAL_FLASHEx_OB_DeSelectPCROP:000000000000002c $d + /tmp/cc9alhJF.s:1209 .text.HAL_FLASHEx_DATAEEPROM_Unlock:0000000000000000 $t + /tmp/cc9alhJF.s:1216 .text.HAL_FLASHEx_DATAEEPROM_Unlock:0000000000000000 HAL_FLASHEx_DATAEEPROM_Unlock + /tmp/cc9alhJF.s:1248 .text.HAL_FLASHEx_DATAEEPROM_Unlock:000000000000001c $d + /tmp/cc9alhJF.s:1255 .text.HAL_FLASHEx_DATAEEPROM_Lock:0000000000000000 $t + /tmp/cc9alhJF.s:1262 .text.HAL_FLASHEx_DATAEEPROM_Lock:0000000000000000 HAL_FLASHEx_DATAEEPROM_Lock + /tmp/cc9alhJF.s:1282 .text.HAL_FLASHEx_DATAEEPROM_Lock:0000000000000010 $d + /tmp/cc9alhJF.s:1287 .text.HAL_FLASHEx_DATAEEPROM_Erase:0000000000000000 $t + /tmp/cc9alhJF.s:1294 .text.HAL_FLASHEx_DATAEEPROM_Erase:0000000000000000 HAL_FLASHEx_DATAEEPROM_Erase + /tmp/cc9alhJF.s:1339 .text.HAL_FLASHEx_DATAEEPROM_Erase:0000000000000020 $d + /tmp/cc9alhJF.s:1345 .text.HAL_FLASHEx_DATAEEPROM_Program:0000000000000000 $t + /tmp/cc9alhJF.s:1352 .text.HAL_FLASHEx_DATAEEPROM_Program:0000000000000000 HAL_FLASHEx_DATAEEPROM_Program + /tmp/cc9alhJF.s:1446 .text.HAL_FLASHEx_DATAEEPROM_Program:0000000000000054 $d + /tmp/cc9alhJF.s:1452 .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram:0000000000000000 $t + /tmp/cc9alhJF.s:1459 .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram:0000000000000000 HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram + /tmp/cc9alhJF.s:1479 .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram:0000000000000010 $d + /tmp/cc9alhJF.s:1484 .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram:0000000000000000 $t + /tmp/cc9alhJF.s:1491 .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram:0000000000000000 HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram + /tmp/cc9alhJF.s:1510 .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram:000000000000000c $d + /tmp/cc9alhJF.s:1516 .text.FLASH_PageErase:0000000000000000 $t + /tmp/cc9alhJF.s:1523 .text.FLASH_PageErase:0000000000000000 FLASH_PageErase + /tmp/cc9alhJF.s:1562 .text.FLASH_PageErase:0000000000000024 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +FLASH_WaitForLastOperation +pFlash diff --git a/build/stm32l0xx_hal_flash_ramfunc.d b/build/stm32l0xx_hal_flash_ramfunc.d new file mode 100644 index 0000000..cb2e20b --- /dev/null +++ b/build/stm32l0xx_hal_flash_ramfunc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_flash_ramfunc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_flash_ramfunc.lst b/build/stm32l0xx_hal_flash_ramfunc.lst new file mode 100644 index 0000000..7e2f3b5 --- /dev/null +++ b/build/stm32l0xx_hal_flash_ramfunc.lst @@ -0,0 +1,1527 @@ +ARM GAS /tmp/ccviJFHV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_flash_ramfunc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .RamFunc,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 FLASHRAM_WaitForLastOperation: + 23 .LFB46: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @file stm32l0xx_hal_flash_ramfunc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief FLASH RAMFUNC driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * This file provides a Flash firmware functions which should be + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * executed from internal SRAM + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @verbatim + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *** ARM Compiler *** + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** -------------------- + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** [..] RAM functions are defined using the toolchain options. + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** Functions that are be executed in RAM should reside in a separate + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** source module. Using the 'Options for File' dialog you can simply change + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** the 'Code / Const' area of a module to a memory space in physical RAM. + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** Available memory areas are declared in the 'Target' tab of the + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** Options for Target' dialog. + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *** ICCARM Compiler *** + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ----------------------- + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *** GNU Compiler *** + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** -------------------- + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** [..] RAM functions are defined using a specific toolchain attribute + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** "__attribute__((section(".RamFunc")))". + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @endverbatim + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ****************************************************************************** + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @attention + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + ARM GAS /tmp/ccviJFHV.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * Redistribution and use in source and binary forms, with or without modification, + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * are permitted provided that the following conditions are met: + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * this list of conditions and the following disclaimer. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * this list of conditions and the following disclaimer in the documentation + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * and/or other materials provided with the distribution. + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * may be used to endorse or promote products derived from this software + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * without specific prior written permission. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ****************************************************************************** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Includes ------------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** #include "stm32l0xx_hal.h" + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @addtogroup STM32L0xx_HAL_Driver + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @addtogroup FLASH + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @addtogroup FLASH_Private_Variables + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** extern FLASH_ProcessTypeDef pFlash; + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief FLASH functions executed from RAM + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private typedef -----------------------------------------------------------*/ + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private define ------------------------------------------------------------*/ + ARM GAS /tmp/ccviJFHV.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private macro -------------------------------------------------------------*/ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private variables ---------------------------------------------------------*/ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private function prototypes -----------------------------------------------*/ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** static __RAM_FUNC FLASHRAM_SetErrorCode(void); + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Private functions ---------------------------------------------------------*/ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @verbatim + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** =============================================================================== + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ##### ramfunc functions ##### + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** =============================================================================== + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** [..] + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** This subsection provides a set of functions that should be executed from RAM + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** transfers. + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @endverbatim + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Enable the power down mode during RUN mode. + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note This function can be used only when the user code is running from Internal SRAM. + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Enable the Power Down in Run mode*/ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_POWER_DOWN_ENABLE(); + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Disable the power down mode during RUN mode. + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note This function can be used only when the user code is running from Internal SRAM. + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Disable the Power Down in Run mode*/ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_POWER_DOWN_DISABLE(); + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + ARM GAS /tmp/ccviJFHV.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @verbatim + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @endverbatim + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** #if defined(FLASH_PECR_PARALLBANK) + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Erases a specified 2 pages in program memory in parallel. + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note This function can be used only for STM32L07xxx/STM32L08xxx devices. + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * To correctly run this function, the @ref HAL_FLASH_Unlock() function + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * must be called before. + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (recommended to protect the FLASH memory against possible unwanted operation). + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Page_Address1: The page address in program memory to be erased in + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * the first Bank (BANK1). This parameter should be between FLASH_BASE + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * and FLASH_BANK1_END. + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Page_Address2: The page address in program memory to be erased in + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * and FLASH_BANK2_END. + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note A Page is erased in the Program memory only if the address to load + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(status == HAL_OK) + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Proceed to erase the page */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write 00000000h to the first word of the first program page to erase */ + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *(__IO uint32_t *)Page_Address1 = 0x00000000U; + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write 00000000h to the first word of the second program page to erase */ + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *(__IO uint32_t *)Page_Address2 = 0x00000000U; + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + ARM GAS /tmp/ccviJFHV.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Return the Erase Status */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return status; + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Program 2 half pages in program memory in parallel (half page size is 16 Words). + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note This function can be used only for STM32L07xxx/STM32L08xxx devices. + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Address1: specifies the first address to be written in the first bank + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_S + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param pBuffer1: pointer to the buffer containing the data to be written + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * to the first half page in the first bank. + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Address2: specifies the second address to be written in the second bank + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_ + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param pBuffer2: pointer to the buffer containing the data to be written + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * to the second half page in the second bank. + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * must be called before. + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (recommended to protect the FLASH memory against possible unwanted operation). + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note Half page write is possible only from SRAM. + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note A half page is written to the program memory only if the first + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * address to load is the start address of a half page (multiple of 64 + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * bytes) and the 15 remaining words to load are in the same half page. + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note During the Program memory half page write all read operations are + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * forbidden (this includes DMA read operations and debugger read + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * operations such as breakpoints, periodic updates, etc.). + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note If a PGAERR is set during a Program memory half page write, the + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * complete write operation is aborted. Software should then reset the + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * FPRG and PROG/DATA bits and restart the write operation from the + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * beginning. + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Addr + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** uint32_t count = 0U; + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(status == HAL_OK) + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Proceed to program the new half page */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(status == HAL_OK) + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Disable all IRQs */ + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __disable_irq(); + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write the first half page directly with 16 different words */ + ARM GAS /tmp/ccviJFHV.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** while(count < 16U) + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Address1 doesn't need to be increased */ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *(__IO uint32_t*) Address1 = *pBuffer1; + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer1++; + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** count ++; + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write the second half page directly with 16 different words */ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** count = 0U; + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** while(count < 16U) + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Address2 doesn't need to be increased */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *(__IO uint32_t*) Address2 = *pBuffer2; + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer2++; + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** count ++; + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Enable IRQs */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __enable_irq(); + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Return the Write Status */ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return status; + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** #endif /* FLASH_PECR_PARALLBANK */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Program a half page in program memory. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Address: specifies the address to be written. + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param pBuffer: pointer to the buffer containing the data to be written to + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * the half page. + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * must be called before. + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note Half page write is possible only from SRAM. + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note A half page is written to the program memory only if the first + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * address to load is the start address of a half page (multiple of 64 + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * bytes) and the 15 remaining words to load are in the same half page. + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note During the Program memory half page write all read operations are + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * forbidden (this includes DMA read operations and debugger read + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * operations such as breakpoints, periodic updates, etc.). + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @note If a PGAERR is set during a Program memory half page write, the + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * complete write operation is aborted. Software should then reset the + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * FPRG and PROG/DATA bits and restart the write operation from the + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * beginning. + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + ARM GAS /tmp/ccviJFHV.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** uint32_t count = 0U; + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(status == HAL_OK) + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Proceed to program the new half page */ + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Disable all IRQs */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __disable_irq(); + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write one half page directly with 16 different words */ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** while(count < 16U) + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Address doesn't need to be increased */ + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *(__IO uint32_t*) Address = *pBuffer; + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer++; + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** count ++; + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Enable IRQs */ + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __enable_irq(); + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for last operation to be completed */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* If the write operation is completed, disable the PROG and FPRG bits */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Return the Write Status */ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return status; + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Peripheral errors functions + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @verbatim + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** =============================================================================== + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** ##### Peripheral errors functions ##### + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** =============================================================================== + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** [..] + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** This subsection permit to get in run-time errors of the FLASH peripheral. + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** @endverbatim + ARM GAS /tmp/ccviJFHV.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Get the specific FLASH errors flag. + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Error pointer is the error value. It can be a mixed of: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_SIZE FLASH Programming Parallelism error flag + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_FWWERR FLASH Write or Erase operation aborted + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @arg @ref HAL_FLASH_ERROR_NOTZERO FLASH Write operation is done in a not-erased regi + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL Status + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error) + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *Error = pFlash.ErrorCode; + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @} + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** @addtogroup FLASH_RAMFUNC_Private_Functions + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @{ + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Set the specific FLASH error flag. + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL Status + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** static __RAM_FUNC FLASHRAM_SetErrorCode(void) + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** uint32_t flags = 0; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_WRPERR; + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_PGAERR; + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_SIZERR; + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + ARM GAS /tmp/ccviJFHV.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * as expected. If the user run an application using the first + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * cut of the STM32L031xx device or the first cut of the STM32L041xx + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * device, this error should be ignored. The revId of the device + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * can be retrieved via the HAL_GetREVID() function. + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_OPTVERR; + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_RDERR; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= HAL_FLASH_ERROR_FWWERR; + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_NOTZEROERR; + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Clear FLASH error pending bits */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_CLEAR_FLAG(flags); + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /** + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @brief Wait for a FLASH operation to complete. + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @param Timeout: maximum flash operationtimeout + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * @retval HAL status + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 25 .loc 1 475 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flag will be set */ + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) + 31 .loc 1 480 0 + 32 0000 00E0 b .L2 + 33 .L4: + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + ARM GAS /tmp/ccviJFHV.s page 10 + + + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** Timeout--; + 34 .loc 1 482 0 + 35 0002 0138 subs r0, r0, #1 + 36 .LVL1: + 37 .L2: + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 38 .loc 1 480 0 + 39 0004 434B ldr r3, .L18 + 40 0006 9B69 ldr r3, [r3, #24] + 41 0008 DB07 lsls r3, r3, #31 + 42 000a 01D5 bpl .L3 + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 43 .loc 1 480 0 is_stmt 0 discriminator 1 + 44 000c 0028 cmp r0, #0 + 45 000e F8D1 bne .L4 + 46 .L3: + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(Timeout == 0x00U) + 47 .loc 1 485 0 is_stmt 1 + 48 0010 0028 cmp r0, #0 + 49 0012 00D1 bne .LCB28 + 50 0014 79E0 b .L15 @long jump + 51 .LCB28: + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_TIMEOUT; + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Check FLASH End of Operation flag */ + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 52 .loc 1 491 0 + 53 0016 3F4B ldr r3, .L18 + 54 0018 9B69 ldr r3, [r3, #24] + 55 001a 9B07 lsls r3, r3, #30 + 56 001c 02D5 bpl .L6 + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Clear FLASH End of Operation pending bit */ + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 57 .loc 1 494 0 + 58 001e 3D4B ldr r3, .L18 + 59 0020 0222 movs r2, #2 + 60 0022 9A61 str r2, [r3, #24] + 61 .L6: + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 62 .loc 1 497 0 + 63 0024 3B4B ldr r3, .L18 + 64 0026 9B69 ldr r3, [r3, #24] + 65 0028 DB05 lsls r3, r3, #23 + 66 002a 17D4 bmi .L7 + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 67 .loc 1 498 0 discriminator 1 + 68 002c 394B ldr r3, .L18 + 69 002e 9B69 ldr r3, [r3, #24] + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 70 .loc 1 497 0 discriminator 1 + ARM GAS /tmp/ccviJFHV.s page 11 + + + 71 0030 9B05 lsls r3, r3, #22 + 72 0032 13D4 bmi .L7 + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 73 .loc 1 499 0 + 74 0034 374B ldr r3, .L18 + 75 0036 9B69 ldr r3, [r3, #24] + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + 76 .loc 1 498 0 + 77 0038 5B05 lsls r3, r3, #21 + 78 003a 0FD4 bmi .L7 + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 79 .loc 1 500 0 + 80 003c 354B ldr r3, .L18 + 81 003e 9B69 ldr r3, [r3, #24] + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + 82 .loc 1 499 0 + 83 0040 1B05 lsls r3, r3, #20 + 84 0042 0BD4 bmi .L7 + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 85 .loc 1 501 0 + 86 0044 334B ldr r3, .L18 + 87 0046 9B69 ldr r3, [r3, #24] + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + 88 .loc 1 500 0 + 89 0048 9B04 lsls r3, r3, #18 + 90 004a 07D4 bmi .L7 + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 91 .loc 1 502 0 + 92 004c 314B ldr r3, .L18 + 93 004e 9B69 ldr r3, [r3, #24] + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + 94 .loc 1 501 0 + 95 0050 9B03 lsls r3, r3, #14 + 96 0052 03D4 bmi .L7 + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + 97 .loc 1 503 0 + 98 0054 2F4B ldr r3, .L18 + 99 0056 9B69 ldr r3, [r3, #24] + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + 100 .loc 1 502 0 + 101 0058 DB03 lsls r3, r3, #15 + 102 005a 58D5 bpl .L16 + 103 .L7: + 104 .LVL2: + 105 .LBB12: + 106 .LBB13: + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 107 .loc 1 418 0 + 108 005c 2D4B ldr r3, .L18 + 109 005e 9B69 ldr r3, [r3, #24] + 110 0060 DB05 lsls r3, r3, #23 + 111 0062 07D5 bpl .L17 + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_WRPERR; + 112 .loc 1 420 0 + 113 0064 2C4A ldr r2, .L18+4 + 114 0066 5369 ldr r3, [r2, #20] + 115 0068 0221 movs r1, #2 + ARM GAS /tmp/ccviJFHV.s page 12 + + + 116 006a 0B43 orrs r3, r1 + 117 006c 5361 str r3, [r2, #20] + 118 .LVL3: + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 119 .loc 1 421 0 + 120 006e 8023 movs r3, #128 + 121 0070 5B00 lsls r3, r3, #1 + 122 0072 00E0 b .L8 + 123 .LVL4: + 124 .L17: + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 125 .loc 1 416 0 + 126 0074 0023 movs r3, #0 + 127 .LVL5: + 128 .L8: + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 129 .loc 1 423 0 + 130 0076 274A ldr r2, .L18 + 131 0078 9269 ldr r2, [r2, #24] + 132 007a 9205 lsls r2, r2, #22 + 133 007c 07D5 bpl .L9 + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_PGAERR; + 134 .loc 1 425 0 + 135 007e 2649 ldr r1, .L18+4 + 136 0080 4A69 ldr r2, [r1, #20] + 137 0082 0120 movs r0, #1 + 138 .LVL6: + 139 0084 0243 orrs r2, r0 + 140 0086 4A61 str r2, [r1, #20] + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 141 .loc 1 426 0 + 142 0088 8022 movs r2, #128 + 143 008a 9200 lsls r2, r2, #2 + 144 008c 1343 orrs r3, r2 + 145 .LVL7: + 146 .L9: + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 147 .loc 1 428 0 + 148 008e 214A ldr r2, .L18 + 149 0090 9269 ldr r2, [r2, #24] + 150 0092 5205 lsls r2, r2, #21 + 151 0094 07D5 bpl .L10 + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_SIZERR; + 152 .loc 1 430 0 + 153 0096 2049 ldr r1, .L18+4 + 154 0098 4A69 ldr r2, [r1, #20] + 155 009a 0820 movs r0, #8 + 156 009c 0243 orrs r2, r0 + 157 009e 4A61 str r2, [r1, #20] + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 158 .loc 1 431 0 + 159 00a0 8022 movs r2, #128 + 160 00a2 D200 lsls r2, r2, #3 + 161 00a4 1343 orrs r3, r2 + 162 .LVL8: + 163 .L10: + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + ARM GAS /tmp/ccviJFHV.s page 13 + + + 164 .loc 1 433 0 + 165 00a6 1B4A ldr r2, .L18 + 166 00a8 9269 ldr r2, [r2, #24] + 167 00aa 1205 lsls r2, r2, #20 + 168 00ac 07D5 bpl .L11 + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_OPTVERR; + 169 .loc 1 443 0 + 170 00ae 1A49 ldr r1, .L18+4 + 171 00b0 4A69 ldr r2, [r1, #20] + 172 00b2 0420 movs r0, #4 + 173 00b4 0243 orrs r2, r0 + 174 00b6 4A61 str r2, [r1, #20] + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 175 .loc 1 444 0 + 176 00b8 8022 movs r2, #128 + 177 00ba 1201 lsls r2, r2, #4 + 178 00bc 1343 orrs r3, r2 + 179 .LVL9: + 180 .L11: + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 181 .loc 1 447 0 + 182 00be 154A ldr r2, .L18 + 183 00c0 9269 ldr r2, [r2, #24] + 184 00c2 9204 lsls r2, r2, #18 + 185 00c4 07D5 bpl .L12 + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_RDERR; + 186 .loc 1 449 0 + 187 00c6 1449 ldr r1, .L18+4 + 188 00c8 4A69 ldr r2, [r1, #20] + 189 00ca 1020 movs r0, #16 + 190 00cc 0243 orrs r2, r0 + 191 00ce 4A61 str r2, [r1, #20] + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 192 .loc 1 450 0 + 193 00d0 8022 movs r2, #128 + 194 00d2 9201 lsls r2, r2, #6 + 195 00d4 1343 orrs r3, r2 + 196 .LVL10: + 197 .L12: + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 198 .loc 1 452 0 + 199 00d6 0F4A ldr r2, .L18 + 200 00d8 9269 ldr r2, [r2, #24] + 201 00da 9203 lsls r2, r2, #14 + 202 00dc 05D5 bpl .L13 + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= HAL_FLASH_ERROR_FWWERR; + 203 .loc 1 454 0 + 204 00de 0E48 ldr r0, .L18+4 + 205 00e0 4269 ldr r2, [r0, #20] + 206 00e2 2021 movs r1, #32 + 207 00e4 0A43 orrs r2, r1 + 208 00e6 4261 str r2, [r0, #20] + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 209 .loc 1 455 0 + 210 00e8 0B43 orrs r3, r1 + 211 .LVL11: + 212 .L13: + ARM GAS /tmp/ccviJFHV.s page 14 + + + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 213 .loc 1 457 0 + 214 00ea 0A4A ldr r2, .L18 + 215 00ec 9269 ldr r2, [r2, #24] + 216 00ee D203 lsls r2, r2, #15 + 217 00f0 07D5 bpl .L14 + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** flags |= FLASH_FLAG_NOTZEROERR; + 218 .loc 1 459 0 + 219 00f2 0949 ldr r1, .L18+4 + 220 00f4 4A69 ldr r2, [r1, #20] + 221 00f6 4020 movs r0, #64 + 222 00f8 0243 orrs r2, r0 + 223 00fa 4A61 str r2, [r1, #20] + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 224 .loc 1 460 0 + 225 00fc 8022 movs r2, #128 + 226 00fe 5202 lsls r2, r2, #9 + 227 0100 1343 orrs r3, r2 + 228 .LVL12: + 229 .L14: + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 230 .loc 1 464 0 + 231 0102 044A ldr r2, .L18 + 232 0104 9361 str r3, [r2, #24] + 233 .LBE13: + 234 .LBE12: + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /*Save the error code*/ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * as expected. If the user run an application using the first + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * cut of the STM32L031xx device or the first cut of the STM32L041xx + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * device, this error should be ignored. The revId of the device + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * can be retrieved via the HAL_GetREVID() function. + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** * + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** */ + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** FLASHRAM_SetErrorCode(); + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_ERROR; + 235 .loc 1 516 0 + 236 0106 0120 movs r0, #1 + 237 .LVL13: + 238 .L5: + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* There is no error flag set */ + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 239 .loc 1 521 0 + 240 @ sp needed + 241 0108 7047 bx lr + 242 .LVL14: + 243 .L15: + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 244 .loc 1 487 0 + 245 010a 0320 movs r0, #3 + 246 .LVL15: + ARM GAS /tmp/ccviJFHV.s page 15 + + + 247 010c FCE7 b .L5 + 248 .LVL16: + 249 .L16: + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 250 .loc 1 520 0 + 251 010e 0020 movs r0, #0 + 252 .LVL17: + 253 0110 FAE7 b .L5 + 254 .L19: + 255 0112 C046 .align 2 + 256 .L18: + 257 0114 00200240 .word 1073881088 + 258 0118 00000000 .word pFlash + 259 .cfi_endproc + 260 .LFE46: + 262 .align 1 + 263 .global HAL_FLASHEx_EnableRunPowerDown + 264 .syntax unified + 265 .code 16 + 266 .thumb_func + 267 .fpu softvfp + 269 HAL_FLASHEx_EnableRunPowerDown: + 270 .LFB39: + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Enable the Power Down in Run mode*/ + 271 .loc 1 132 0 + 272 .cfi_startproc + 273 @ args = 0, pretend = 0, frame = 0 + 274 @ frame_needed = 0, uses_anonymous_args = 0 + 275 @ link register save eliminated. + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 276 .loc 1 134 0 + 277 011c 054B ldr r3, .L21 + 278 011e 064A ldr r2, .L21+4 + 279 0120 9A60 str r2, [r3, #8] + 280 0122 064A ldr r2, .L21+8 + 281 0124 9A60 str r2, [r3, #8] + 282 0126 1A68 ldr r2, [r3] + 283 0128 1021 movs r1, #16 + 284 012a 0A43 orrs r2, r1 + 285 012c 1A60 str r2, [r3] + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 286 .loc 1 137 0 + 287 012e 0020 movs r0, #0 + 288 @ sp needed + 289 0130 7047 bx lr + 290 .L22: + 291 0132 C046 .align 2 + 292 .L21: + 293 0134 00200240 .word 1073881088 + 294 0138 37261504 .word 68494903 + 295 013c FDFCFBFA .word -84148995 + 296 .cfi_endproc + 297 .LFE39: + 299 .align 1 + 300 .global HAL_FLASHEx_DisableRunPowerDown + 301 .syntax unified + 302 .code 16 + ARM GAS /tmp/ccviJFHV.s page 16 + + + 303 .thumb_func + 304 .fpu softvfp + 306 HAL_FLASHEx_DisableRunPowerDown: + 307 .LFB40: + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Disable the Power Down in Run mode*/ + 308 .loc 1 145 0 + 309 .cfi_startproc + 310 @ args = 0, pretend = 0, frame = 0 + 311 @ frame_needed = 0, uses_anonymous_args = 0 + 312 @ link register save eliminated. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 313 .loc 1 147 0 + 314 0140 054B ldr r3, .L24 + 315 0142 064A ldr r2, .L24+4 + 316 0144 9A60 str r2, [r3, #8] + 317 0146 064A ldr r2, .L24+8 + 318 0148 9A60 str r2, [r3, #8] + 319 014a 1A68 ldr r2, [r3] + 320 014c 1021 movs r1, #16 + 321 014e 8A43 bics r2, r1 + 322 0150 1A60 str r2, [r3] + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 323 .loc 1 150 0 + 324 0152 0020 movs r0, #0 + 325 @ sp needed + 326 0154 7047 bx lr + 327 .L25: + 328 0156 C046 .align 2 + 329 .L24: + 330 0158 00200240 .word 1073881088 + 331 015c 37261504 .word 68494903 + 332 0160 FDFCFBFA .word -84148995 + 333 .cfi_endproc + 334 .LFE40: + 336 .align 1 + 337 .global HAL_FLASHEx_EraseParallelPage + 338 .syntax unified + 339 .code 16 + 340 .thumb_func + 341 .fpu softvfp + 343 HAL_FLASHEx_EraseParallelPage: + 344 .LFB41: + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + 345 .loc 1 182 0 + 346 .cfi_startproc + 347 @ args = 0, pretend = 0, frame = 0 + 348 @ frame_needed = 0, uses_anonymous_args = 0 + 349 .LVL18: + 350 0164 F8B5 push {r3, r4, r5, r6, r7, lr} + 351 .LCFI0: + 352 .cfi_def_cfa_offset 24 + 353 .cfi_offset 3, -24 + 354 .cfi_offset 4, -20 + 355 .cfi_offset 5, -16 + 356 .cfi_offset 6, -12 + 357 .cfi_offset 7, -8 + 358 .cfi_offset 14, -4 + ARM GAS /tmp/ccviJFHV.s page 17 + + + 359 0166 0600 movs r6, r0 + 360 0168 0D00 movs r5, r1 + 361 .LVL19: + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 362 .loc 1 186 0 + 363 016a 1348 ldr r0, .L29 + 364 .LVL20: + 365 016c FFF748FF bl FLASHRAM_WaitForLastOperation + 366 .LVL21: + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 367 .loc 1 188 0 + 368 0170 0028 cmp r0, #0 + 369 0172 00D0 beq .L28 + 370 .LVL22: + 371 .L27: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 372 .loc 1 210 0 + 373 @ sp needed + 374 .LVL23: + 375 .LVL24: + 376 0174 F8BD pop {r3, r4, r5, r6, r7, pc} + 377 .LVL25: + 378 .L28: + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 379 .loc 1 191 0 + 380 0176 114C ldr r4, .L29+4 + 381 0178 6268 ldr r2, [r4, #4] + 382 017a 8023 movs r3, #128 + 383 017c 1B02 lsls r3, r3, #8 + 384 017e 1343 orrs r3, r2 + 385 0180 6360 str r3, [r4, #4] + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 386 .loc 1 192 0 + 387 0182 6268 ldr r2, [r4, #4] + 388 0184 8023 movs r3, #128 + 389 0186 9B00 lsls r3, r3, #2 + 390 0188 1343 orrs r3, r2 + 391 018a 6360 str r3, [r4, #4] + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 392 .loc 1 193 0 + 393 018c 6368 ldr r3, [r4, #4] + 394 018e 0827 movs r7, #8 + 395 0190 3B43 orrs r3, r7 + 396 0192 6360 str r3, [r4, #4] + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** /* Write 00000000h to the first word of the second program page to erase */ + 397 .loc 1 196 0 + 398 0194 0023 movs r3, #0 + 399 0196 3360 str r3, [r6] + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 400 .loc 1 198 0 + 401 0198 2B60 str r3, [r5] + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 402 .loc 1 201 0 + 403 019a 0748 ldr r0, .L29 + 404 .LVL26: + 405 019c FFF730FF bl FLASHRAM_WaitForLastOperation + 406 .LVL27: + ARM GAS /tmp/ccviJFHV.s page 18 + + + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + 407 .loc 1 204 0 + 408 01a0 6368 ldr r3, [r4, #4] + 409 01a2 BB43 bics r3, r7 + 410 01a4 6360 str r3, [r4, #4] + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 411 .loc 1 205 0 + 412 01a6 6368 ldr r3, [r4, #4] + 413 01a8 054A ldr r2, .L29+8 + 414 01aa 1340 ands r3, r2 + 415 01ac 6360 str r3, [r4, #4] + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 416 .loc 1 206 0 + 417 01ae 6368 ldr r3, [r4, #4] + 418 01b0 044A ldr r2, .L29+12 + 419 01b2 1340 ands r3, r2 + 420 01b4 6360 str r3, [r4, #4] + 421 01b6 DDE7 b .L27 + 422 .L30: + 423 .align 2 + 424 .L29: + 425 01b8 50C30000 .word 50000 + 426 01bc 00200240 .word 1073881088 + 427 01c0 FFFDFFFF .word -513 + 428 01c4 FF7FFFFF .word -32769 + 429 .cfi_endproc + 430 .LFE41: + 432 .align 1 + 433 .global HAL_FLASHEx_ProgramParallelHalfPage + 434 .syntax unified + 435 .code 16 + 436 .thumb_func + 437 .fpu softvfp + 439 HAL_FLASHEx_ProgramParallelHalfPage: + 440 .LFB42: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** uint32_t count = 0U; + 441 .loc 1 241 0 + 442 .cfi_startproc + 443 @ args = 0, pretend = 0, frame = 0 + 444 @ frame_needed = 0, uses_anonymous_args = 0 + 445 .LVL28: + 446 01c8 F8B5 push {r3, r4, r5, r6, r7, lr} + 447 .LCFI1: + 448 .cfi_def_cfa_offset 24 + 449 .cfi_offset 3, -24 + 450 .cfi_offset 4, -20 + 451 .cfi_offset 5, -16 + 452 .cfi_offset 6, -12 + 453 .cfi_offset 7, -8 + 454 .cfi_offset 14, -4 + 455 01ca 0700 movs r7, r0 + 456 01cc 0D00 movs r5, r1 + 457 01ce 1600 movs r6, r2 + 458 01d0 1C00 movs r4, r3 + 459 .LVL29: + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 460 .loc 1 246 0 + ARM GAS /tmp/ccviJFHV.s page 19 + + + 461 01d2 1D48 ldr r0, .L39 + 462 .LVL30: + 463 01d4 FFF714FF bl FLASHRAM_WaitForLastOperation + 464 .LVL31: + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 465 .loc 1 248 0 + 466 01d8 0028 cmp r0, #0 + 467 01da 00D0 beq .L38 + 468 .LVL32: + 469 .L32: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** #endif /* FLASH_PECR_PARALLBANK */ + 470 .loc 1 296 0 + 471 @ sp needed + 472 .LVL33: + 473 .LVL34: + 474 .LVL35: + 475 .LVL36: + 476 01dc F8BD pop {r3, r4, r5, r6, r7, pc} + 477 .LVL37: + 478 .L38: + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 479 .loc 1 251 0 + 480 01de 1B4B ldr r3, .L39+4 + 481 01e0 5968 ldr r1, [r3, #4] + 482 01e2 8022 movs r2, #128 + 483 01e4 1202 lsls r2, r2, #8 + 484 01e6 0A43 orrs r2, r1 + 485 01e8 5A60 str r2, [r3, #4] + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 486 .loc 1 252 0 + 487 01ea 5968 ldr r1, [r3, #4] + 488 01ec 8022 movs r2, #128 + 489 01ee D200 lsls r2, r2, #3 + 490 01f0 0A43 orrs r2, r1 + 491 01f2 5A60 str r2, [r3, #4] + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 492 .loc 1 253 0 + 493 01f4 5A68 ldr r2, [r3, #4] + 494 01f6 0821 movs r1, #8 + 495 01f8 0A43 orrs r2, r1 + 496 01fa 5A60 str r2, [r3, #4] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** if(status == HAL_OK) + 497 .loc 1 256 0 + 498 01fc 1248 ldr r0, .L39 + 499 .LVL38: + 500 01fe FFF7FFFE bl FLASHRAM_WaitForLastOperation + 501 .LVL39: + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 502 .loc 1 257 0 + 503 0202 0028 cmp r0, #0 + 504 0204 12D1 bne .L33 + 505 .LBB14: + 506 .LBB15: + 507 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + ARM GAS /tmp/ccviJFHV.s page 20 + + + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + ARM GAS /tmp/ccviJFHV.s page 21 + + + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 508 .loc 2 71 0 + 509 .syntax divided + 510 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 511 0206 72B6 cpsid i + 512 @ 0 "" 2 + 513 .thumb + 514 .syntax unified + 515 .LBE15: + 516 .LBE14: + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + 517 .loc 1 242 0 + 518 0208 0023 movs r3, #0 + 519 020a 02E0 b .L34 + 520 .LVL40: + 521 .L35: + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer1++; + 522 .loc 1 266 0 + 523 020c 04CD ldmia r5!, {r2} + 524 .LVL41: + 525 020e 3A60 str r2, [r7] + 526 .LVL42: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 527 .loc 1 268 0 + 528 0210 0133 adds r3, r3, #1 + 529 .LVL43: + 530 .L34: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 531 .loc 1 263 0 + 532 0212 0F2B cmp r3, #15 + 533 0214 FAD9 bls .L35 + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** while(count < 16U) + 534 .loc 1 272 0 + 535 0216 0023 movs r3, #0 + 536 .LVL44: + 537 0218 02E0 b .L36 + 538 .LVL45: + 539 .L37: + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer2++; + 540 .loc 1 276 0 + 541 021a 04CC ldmia r4!, {r2} + 542 .LVL46: + 543 021c 3260 str r2, [r6] + 544 .LVL47: + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 545 .loc 1 278 0 + 546 021e 0133 adds r3, r3, #1 + ARM GAS /tmp/ccviJFHV.s page 22 + + + 547 .LVL48: + 548 .L36: + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 549 .loc 1 273 0 + 550 0220 0F2B cmp r3, #15 + 551 0222 FAD9 bls .L37 + 552 .LBB16: + 553 .LBB17: + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 554 .loc 2 60 0 + 555 .syntax divided + 556 @ 60 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 557 0224 62B6 cpsie i + 558 @ 0 "" 2 + 559 .thumb + 560 .syntax unified + 561 .LBE17: + 562 .LBE16: + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 563 .loc 1 285 0 + 564 0226 0848 ldr r0, .L39 + 565 .LVL49: + 566 0228 FFF7EAFE bl FLASHRAM_WaitForLastOperation + 567 .LVL50: + 568 .L33: + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 569 .loc 1 289 0 + 570 022c 074B ldr r3, .L39+4 + 571 022e 5A68 ldr r2, [r3, #4] + 572 0230 0821 movs r1, #8 + 573 0232 8A43 bics r2, r1 + 574 0234 5A60 str r2, [r3, #4] + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + 575 .loc 1 290 0 + 576 0236 5A68 ldr r2, [r3, #4] + 577 0238 0549 ldr r1, .L39+8 + 578 023a 0A40 ands r2, r1 + 579 023c 5A60 str r2, [r3, #4] + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 580 .loc 1 291 0 + 581 023e 5A68 ldr r2, [r3, #4] + 582 0240 0449 ldr r1, .L39+12 + 583 0242 0A40 ands r2, r1 + 584 0244 5A60 str r2, [r3, #4] + 585 0246 C9E7 b .L32 + 586 .L40: + 587 .align 2 + 588 .L39: + 589 0248 50C30000 .word 50000 + 590 024c 00200240 .word 1073881088 + 591 0250 FFFBFFFF .word -1025 + 592 0254 FF7FFFFF .word -32769 + 593 .cfi_endproc + 594 .LFE42: + 596 .align 1 + 597 .global HAL_FLASHEx_HalfPageProgram + 598 .syntax unified + ARM GAS /tmp/ccviJFHV.s page 23 + + + 599 .code 16 + 600 .thumb_func + 601 .fpu softvfp + 603 HAL_FLASHEx_HalfPageProgram: + 604 .LFB43: + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** uint32_t count = 0U; + 605 .loc 1 322 0 + 606 .cfi_startproc + 607 @ args = 0, pretend = 0, frame = 0 + 608 @ frame_needed = 0, uses_anonymous_args = 0 + 609 .LVL51: + 610 0258 70B5 push {r4, r5, r6, lr} + 611 .LCFI2: + 612 .cfi_def_cfa_offset 16 + 613 .cfi_offset 4, -16 + 614 .cfi_offset 5, -12 + 615 .cfi_offset 6, -8 + 616 .cfi_offset 14, -4 + 617 025a 0500 movs r5, r0 + 618 025c 0C00 movs r4, r1 + 619 .LVL52: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 620 .loc 1 327 0 + 621 025e 1248 ldr r0, .L45 + 622 .LVL53: + 623 0260 FFF7CEFE bl FLASHRAM_WaitForLastOperation + 624 .LVL54: + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 625 .loc 1 329 0 + 626 0264 0028 cmp r0, #0 + 627 0266 1ED1 bne .L42 + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + 628 .loc 1 332 0 + 629 0268 104B ldr r3, .L45+4 + 630 026a 5968 ldr r1, [r3, #4] + 631 026c 8022 movs r2, #128 + 632 026e D200 lsls r2, r2, #3 + 633 0270 0A43 orrs r2, r1 + 634 0272 5A60 str r2, [r3, #4] + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 635 .loc 1 333 0 + 636 0274 5A68 ldr r2, [r3, #4] + 637 0276 0821 movs r1, #8 + 638 0278 0A43 orrs r2, r1 + 639 027a 5A60 str r2, [r3, #4] + 640 .LBB18: + 641 .LBB19: + 642 .loc 2 71 0 + 643 .syntax divided + 644 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 645 027c 72B6 cpsid i + 646 @ 0 "" 2 + 647 .thumb + 648 .syntax unified + 649 .LBE19: + 650 .LBE18: + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccviJFHV.s page 24 + + + 651 .loc 1 323 0 + 652 027e 0023 movs r3, #0 + 653 0280 02E0 b .L43 + 654 .LVL55: + 655 .L44: + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** pBuffer++; + 656 .loc 1 342 0 + 657 0282 04CC ldmia r4!, {r2} + 658 .LVL56: + 659 0284 2A60 str r2, [r5] + 660 .LVL57: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 661 .loc 1 344 0 + 662 0286 0133 adds r3, r3, #1 + 663 .LVL58: + 664 .L43: + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** { + 665 .loc 1 339 0 + 666 0288 0F2B cmp r3, #15 + 667 028a FAD9 bls .L44 + 668 .LBB20: + 669 .LBB21: + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 670 .loc 2 60 0 + 671 .syntax divided + 672 @ 60 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 673 028c 62B6 cpsie i + 674 @ 0 "" 2 + 675 .thumb + 676 .syntax unified + 677 .LBE21: + 678 .LBE20: + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 679 .loc 1 351 0 + 680 028e 0648 ldr r0, .L45 + 681 .LVL59: + 682 0290 FFF7B6FE bl FLASHRAM_WaitForLastOperation + 683 .LVL60: + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + 684 .loc 1 354 0 + 685 0294 054B ldr r3, .L45+4 + 686 0296 5A68 ldr r2, [r3, #4] + 687 0298 0821 movs r1, #8 + 688 029a 8A43 bics r2, r1 + 689 029c 5A60 str r2, [r3, #4] + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** } + 690 .loc 1 355 0 + 691 029e 5A68 ldr r2, [r3, #4] + 692 02a0 0349 ldr r1, .L45+8 + 693 02a2 0A40 ands r2, r1 + 694 02a4 5A60 str r2, [r3, #4] + 695 .LVL61: + 696 .L42: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 697 .loc 1 360 0 + 698 @ sp needed + 699 .LVL62: + ARM GAS /tmp/ccviJFHV.s page 25 + + + 700 .LVL63: + 701 02a6 70BD pop {r4, r5, r6, pc} + 702 .L46: + 703 .align 2 + 704 .L45: + 705 02a8 50C30000 .word 50000 + 706 02ac 00200240 .word 1073881088 + 707 02b0 FFFBFFFF .word -1025 + 708 .cfi_endproc + 709 .LFE43: + 711 .align 1 + 712 .global HAL_FLASHEx_GetError + 713 .syntax unified + 714 .code 16 + 715 .thumb_func + 716 .fpu softvfp + 718 HAL_FLASHEx_GetError: + 719 .LFB44: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** *Error = pFlash.ErrorCode; + 720 .loc 1 393 0 + 721 .cfi_startproc + 722 @ args = 0, pretend = 0, frame = 0 + 723 @ frame_needed = 0, uses_anonymous_args = 0 + 724 @ link register save eliminated. + 725 .LVL64: + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** return HAL_OK; + 726 .loc 1 394 0 + 727 02b4 024B ldr r3, .L48 + 728 02b6 5B69 ldr r3, [r3, #20] + 729 02b8 0360 str r3, [r0] + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c **** + 730 .loc 1 396 0 + 731 02ba 0020 movs r0, #0 + 732 .LVL65: + 733 @ sp needed + 734 02bc 7047 bx lr + 735 .L49: + 736 02be C046 .align 2 + 737 .L48: + 738 02c0 00000000 .word pFlash + 739 .cfi_endproc + 740 .LFE44: + 742 .text + 743 .Letext0: + 744 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 745 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 746 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 747 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 748 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 749 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 750 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 751 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 752 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 753 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h" + ARM GAS /tmp/ccviJFHV.s page 26 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_flash_ramfunc.c + /tmp/ccviJFHV.s:16 .RamFunc:0000000000000000 $t + /tmp/ccviJFHV.s:22 .RamFunc:0000000000000000 FLASHRAM_WaitForLastOperation + /tmp/ccviJFHV.s:257 .RamFunc:0000000000000114 $d + /tmp/ccviJFHV.s:262 .RamFunc:000000000000011c $t + /tmp/ccviJFHV.s:269 .RamFunc:000000000000011c HAL_FLASHEx_EnableRunPowerDown + /tmp/ccviJFHV.s:293 .RamFunc:0000000000000134 $d + /tmp/ccviJFHV.s:299 .RamFunc:0000000000000140 $t + /tmp/ccviJFHV.s:306 .RamFunc:0000000000000140 HAL_FLASHEx_DisableRunPowerDown + /tmp/ccviJFHV.s:330 .RamFunc:0000000000000158 $d + /tmp/ccviJFHV.s:336 .RamFunc:0000000000000164 $t + /tmp/ccviJFHV.s:343 .RamFunc:0000000000000164 HAL_FLASHEx_EraseParallelPage + /tmp/ccviJFHV.s:425 .RamFunc:00000000000001b8 $d + /tmp/ccviJFHV.s:432 .RamFunc:00000000000001c8 $t + /tmp/ccviJFHV.s:439 .RamFunc:00000000000001c8 HAL_FLASHEx_ProgramParallelHalfPage + /tmp/ccviJFHV.s:589 .RamFunc:0000000000000248 $d + /tmp/ccviJFHV.s:596 .RamFunc:0000000000000258 $t + /tmp/ccviJFHV.s:603 .RamFunc:0000000000000258 HAL_FLASHEx_HalfPageProgram + /tmp/ccviJFHV.s:705 .RamFunc:00000000000002a8 $d + /tmp/ccviJFHV.s:711 .RamFunc:00000000000002b4 $t + /tmp/ccviJFHV.s:718 .RamFunc:00000000000002b4 HAL_FLASHEx_GetError + /tmp/ccviJFHV.s:738 .RamFunc:00000000000002c0 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +pFlash diff --git a/build/stm32l0xx_hal_gpio.d b/build/stm32l0xx_hal_gpio.d new file mode 100644 index 0000000..2ac70d2 --- /dev/null +++ b/build/stm32l0xx_hal_gpio.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_gpio.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_gpio.lst b/build/stm32l0xx_hal_gpio.lst new file mode 100644 index 0000000..fef8baa --- /dev/null +++ b/build/stm32l0xx_hal_gpio.lst @@ -0,0 +1,1503 @@ +ARM GAS /tmp/ccJYgg6T.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_gpio.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_GPIO_Init,"ax",%progbits + 16 .align 1 + 17 .global HAL_GPIO_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_GPIO_Init: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @file stm32l0xx_hal_gpio.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief GPIO HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * functionalities of the General Purpose Input/Output (GPIO) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + IO operation functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @verbatim + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ============================================================================== + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ##### GPIO Peripheral features ##### + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** [..] + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** configured by software in several modes: + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Input mode + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Analog mode + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Output mode + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Alternate function mode + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) External interrupt/event lines + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) During and just after reset, the alternate functions and external interrupt + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** lines are not active and the I/O ports are configured in input floating mode. + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** activated or not. + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** type and the IO speed can be selected depending on the VDD value. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + ARM GAS /tmp/ccJYgg6T.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** multiplexer that allows only one peripheral alternate function (AF) connected + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** to an IO pin at a time. In this way, there can be no conflict between peripherals + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** sharing the same IO pin. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) All ports have external interrupt/event capability. To use external interrupt + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** lines, the port must be configured in input mode. All available GPIO pins are + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (+) The external interrupt/event controller consists of up to 28 edge detectors + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (16 lines are connected to GPIO) for generating event/interrupt requests (each + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** input line can be independently configured to select the type (interrupt or event) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** and the corresponding trigger event (rising or falling or both). Each line can + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** also be masked independently. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ##### How to use this driver ##### + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ============================================================================== + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** [..] + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** structure. + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) In case of Output or alternate function mode selection: the speed is + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** configured through "Speed" member from GPIO_InitTypeDef structure. + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) In alternate mode is selection, the alternate function connected to the IO + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** is configured through "Alternate" member from GPIO_InitTypeDef structure. + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) Analog mode is required when a pin is to be used as ADC channel + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** or DAC output. + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (++) In case of external interrupt/event selection the "Mode" member from + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIO_InitTypeDef structure select the type (interrupt or event) and + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** the corresponding trigger event (rising or falling or both). + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** HAL_NVIC_EnableIRQ(). + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) HAL_GPIO_DeInit allows to set register values to their reset value. This function + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** is also to be used when unconfiguring pin which was used as an external interrupt + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** or in event mode. That is the only way to reset the corresponding bit in + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI & SYSCFG registers. + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) During and just after reset, the alternate functions are not + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** active and the GPIO pins are configured in input floating mode (except JTAG + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** pins). + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** priority over the GPIO function. + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + ARM GAS /tmp/ccJYgg6T.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** The HSE has priority over the GPIO function. + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @endverbatim + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ****************************************************************************** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @attention + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Redistribution and use in source and binary forms, with or without modification, + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * are permitted provided that the following conditions are met: + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * 1. Redistributions of source code must retain the above copyright notice, + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * this list of conditions and the following disclaimer. + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * this list of conditions and the following disclaimer in the documentation + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * and/or other materials provided with the distribution. + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * may be used to endorse or promote products derived from this software + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * without specific prior written permission. + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ****************************************************************************** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #include "stm32l0xx_hal.h" + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup STM32L0xx_HAL_Driver + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup GPIO + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief GPIO HAL module driver + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup GPIO_Private + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Private define ------------------------------------------------------------*/ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define GPIO_MODE ((uint32_t)0x00000003U) + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define EXTI_MODE ((uint32_t)0x10000000U) + ARM GAS /tmp/ccJYgg6T.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define GPIO_MODE_IT ((uint32_t)0x00010000U) + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define GPIO_MODE_EVT ((uint32_t)0x00020000U) + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define RISING_EDGE ((uint32_t)0x00100000U) + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define FALLING_EDGE ((uint32_t)0x00200000U) + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** #define GPIO_NUMBER ((uint32_t)16U) + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @} + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions_Group1 + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Initialization and de-initialization functions + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @verbatim + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** =============================================================================== + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** =============================================================================== + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @endverbatim + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family d + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 26 .loc 1 184 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F0B5 push {r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 20 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + 36 .cfi_offset 6, -12 + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 39 0002 C646 mov lr, r8 + 40 0004 00B5 push {lr} + 41 .LCFI1: + 42 .cfi_def_cfa_offset 24 + 43 .cfi_offset 8, -24 + 44 .LVL1: + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t position = 0x00U; + ARM GAS /tmp/ccJYgg6T.s page 5 + + + 45 .loc 1 185 0 + 46 0006 0023 movs r3, #0 + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t iocurrent = 0x00U; + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t temp = 0x00U; + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin))); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the port pins */ + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** while (((GPIO_Init->Pin) >> position) != 0) + 47 .loc 1 195 0 + 48 0008 38E0 b .L2 + 49 .LVL2: + 50 .L21: + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Get the IO position */ + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** iocurrent = (GPIO_Init->Pin) & (1U << position); + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(iocurrent) + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check if the Alternate function is compliant with the GPIO in use */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate))); + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3U]; + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)) + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the Speed parameter */ + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the IO Speed */ + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the IO Output Type */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp= GPIOx->OTYPER; + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = GPIOx->MODER; + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + ARM GAS /tmp/ccJYgg6T.s page 6 + + + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->MODER = temp; + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Enable SYSCFG Clock */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = SYSCFG->EXTICR[position >> 2U]; + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** CLEAR_BIT(temp, ((uint32_t)0x0FU) << (4U * (position & 0x03U))); + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U))); + 51 .loc 1 255 0 + 52 000a 0526 movs r6, #5 + 53 000c 00E0 b .L8 + 54 .L14: + 55 000e 0026 movs r6, #0 + 56 .L8: + 57 .loc 1 255 0 is_stmt 0 discriminator 24 + 58 0010 AE40 lsls r6, r6, r5 + 59 0012 3500 movs r5, r6 + 60 0014 3D43 orrs r5, r7 + 61 .LVL3: + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 62 .loc 1 256 0 is_stmt 1 discriminator 24 + 63 0016 0234 adds r4, r4, #2 + 64 0018 A400 lsls r4, r4, #2 + 65 001a 584E ldr r6, .L22 + 66 001c A551 str r5, [r4, r6] + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = EXTI->IMR; + 67 .loc 1 259 0 discriminator 24 + 68 001e 584C ldr r4, .L22+4 + 69 0020 2568 ldr r5, [r4] + 70 .LVL4: + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 71 .loc 1 260 0 discriminator 24 + 72 0022 4246 mov r2, r8 + 73 0024 D443 mvns r4, r2 + 74 0026 2E00 movs r6, r5 + 75 0028 2640 ands r6, r4 + 76 .LVL5: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 77 .loc 1 261 0 discriminator 24 + 78 002a 4A68 ldr r2, [r1, #4] + 79 002c D203 lsls r2, r2, #15 + 80 002e 02D5 bpl .L9 + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= iocurrent; + ARM GAS /tmp/ccJYgg6T.s page 7 + + + 81 .loc 1 263 0 + 82 0030 4246 mov r2, r8 + 83 0032 1543 orrs r5, r2 + 84 0034 2E00 movs r6, r5 + 85 .LVL6: + 86 .L9: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->IMR = temp; + 87 .loc 1 265 0 + 88 0036 524D ldr r5, .L22+4 + 89 0038 2E60 str r6, [r5] + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = EXTI->EMR; + 90 .loc 1 267 0 + 91 003a 6D68 ldr r5, [r5, #4] + 92 .LVL7: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 93 .loc 1 268 0 + 94 003c 2E00 movs r6, r5 + 95 003e 2640 ands r6, r4 + 96 .LVL8: + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 97 .loc 1 269 0 + 98 0040 4A68 ldr r2, [r1, #4] + 99 0042 9203 lsls r2, r2, #14 + 100 0044 02D5 bpl .L10 + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= iocurrent; + 101 .loc 1 271 0 + 102 0046 4246 mov r2, r8 + 103 0048 1543 orrs r5, r2 + 104 004a 2E00 movs r6, r5 + 105 .LVL9: + 106 .L10: + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->EMR = temp; + 107 .loc 1 273 0 + 108 004c 4C4D ldr r5, .L22+4 + 109 004e 6E60 str r6, [r5, #4] + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = EXTI->RTSR; + 110 .loc 1 276 0 + 111 0050 AD68 ldr r5, [r5, #8] + 112 .LVL10: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 113 .loc 1 277 0 + 114 0052 2E00 movs r6, r5 + 115 0054 2640 ands r6, r4 + 116 .LVL11: + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 117 .loc 1 278 0 + 118 0056 4A68 ldr r2, [r1, #4] + 119 0058 D202 lsls r2, r2, #11 + 120 005a 02D5 bpl .L11 + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= iocurrent; + ARM GAS /tmp/ccJYgg6T.s page 8 + + + 121 .loc 1 280 0 + 122 005c 4246 mov r2, r8 + 123 005e 1543 orrs r5, r2 + 124 0060 2E00 movs r6, r5 + 125 .LVL12: + 126 .L11: + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->RTSR = temp; + 127 .loc 1 282 0 + 128 0062 474D ldr r5, .L22+4 + 129 0064 AE60 str r6, [r5, #8] + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp = EXTI->FTSR; + 130 .loc 1 284 0 + 131 0066 ED68 ldr r5, [r5, #12] + 132 .LVL13: + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 133 .loc 1 285 0 + 134 0068 2C40 ands r4, r5 + 135 .LVL14: + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 136 .loc 1 286 0 + 137 006a 4A68 ldr r2, [r1, #4] + 138 006c 9202 lsls r2, r2, #10 + 139 006e 02D5 bpl .L12 + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= iocurrent; + 140 .loc 1 288 0 + 141 0070 4246 mov r2, r8 + 142 0072 2A43 orrs r2, r5 + 143 0074 1400 movs r4, r2 + 144 .LVL15: + 145 .L12: + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->FTSR = temp; + 146 .loc 1 290 0 + 147 0076 424A ldr r2, .L22+4 + 148 0078 D460 str r4, [r2, #12] + 149 .LVL16: + 150 .L3: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** position++; + 151 .loc 1 293 0 + 152 007a 0133 adds r3, r3, #1 + 153 .LVL17: + 154 .L2: + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 155 .loc 1 195 0 + 156 007c 0A68 ldr r2, [r1] + 157 007e 1400 movs r4, r2 + 158 0080 DC40 lsrs r4, r4, r3 + 159 0082 77D0 beq .L20 + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 160 .loc 1 198 0 + 161 0084 0124 movs r4, #1 + 162 0086 9C40 lsls r4, r4, r3 + ARM GAS /tmp/ccJYgg6T.s page 9 + + + 163 0088 2240 ands r2, r4 + 164 008a 9046 mov r8, r2 + 165 .LVL18: + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 166 .loc 1 200 0 + 167 008c F5D0 beq .L3 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 168 .loc 1 204 0 + 169 008e 4D68 ldr r5, [r1, #4] + 170 0090 022D cmp r5, #2 + 171 0092 01D0 beq .L4 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 172 .loc 1 204 0 is_stmt 0 discriminator 1 + 173 0094 122D cmp r5, #18 + 174 0096 0ED1 bne .L5 + 175 .L4: + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; + 176 .loc 1 209 0 is_stmt 1 + 177 0098 DD08 lsrs r5, r3, #3 + 178 009a 0835 adds r5, r5, #8 + 179 009c AD00 lsls r5, r5, #2 + 180 009e 2F58 ldr r7, [r5, r0] + 181 .LVL19: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)) + 182 .loc 1 210 0 + 183 00a0 0726 movs r6, #7 + 184 00a2 1E40 ands r6, r3 + 185 00a4 B600 lsls r6, r6, #2 + 186 00a6 0F22 movs r2, #15 + 187 .LVL20: + 188 00a8 B240 lsls r2, r2, r6 + 189 00aa 9743 bics r7, r2 + 190 .LVL21: + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 191 .loc 1 211 0 + 192 00ac 0A69 ldr r2, [r1, #16] + 193 00ae B240 lsls r2, r2, r6 + 194 00b0 1600 movs r6, r2 + 195 00b2 3E43 orrs r6, r7 + 196 .LVL22: + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 197 .loc 1 212 0 + 198 00b4 2E50 str r6, [r5, r0] + 199 .LVL23: + 200 .L5: + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 201 .loc 1 216 0 + 202 00b6 4D68 ldr r5, [r1, #4] + 203 00b8 6E1E subs r6, r5, #1 + 204 00ba 012E cmp r6, #1 + 205 00bc 03D9 bls .L6 + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 206 .loc 1 216 0 is_stmt 0 discriminator 1 + 207 00be 112D cmp r5, #17 + 208 00c0 01D0 beq .L6 + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 209 .loc 1 217 0 is_stmt 1 + ARM GAS /tmp/ccJYgg6T.s page 10 + + + 210 00c2 122D cmp r5, #18 + 211 00c4 12D1 bne .L7 + 212 .L6: + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); + 213 .loc 1 222 0 + 214 00c6 8568 ldr r5, [r0, #8] + 215 .LVL24: + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 216 .loc 1 223 0 + 217 00c8 5F00 lsls r7, r3, #1 + 218 00ca 0326 movs r6, #3 + 219 00cc BE40 lsls r6, r6, r7 + 220 00ce B543 bics r5, r6 + 221 .LVL25: + 222 00d0 2E00 movs r6, r5 + 223 .LVL26: + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 224 .loc 1 224 0 + 225 00d2 CD68 ldr r5, [r1, #12] + 226 .LVL27: + 227 00d4 BD40 lsls r5, r5, r7 + 228 00d6 3543 orrs r5, r6 + 229 .LVL28: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 230 .loc 1 225 0 + 231 00d8 8560 str r5, [r0, #8] + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 232 .loc 1 228 0 + 233 00da 4568 ldr r5, [r0, #4] + 234 .LVL29: + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 235 .loc 1 229 0 + 236 00dc A543 bics r5, r4 + 237 .LVL30: + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 238 .loc 1 230 0 + 239 00de 4A68 ldr r2, [r1, #4] + 240 00e0 1609 lsrs r6, r2, #4 + 241 00e2 0124 movs r4, #1 + 242 00e4 3440 ands r4, r6 + 243 00e6 9C40 lsls r4, r4, r3 + 244 00e8 2C43 orrs r4, r5 + 245 .LVL31: + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 246 .loc 1 231 0 + 247 00ea 4460 str r4, [r0, #4] + 248 .LVL32: + 249 .L7: + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 250 .loc 1 235 0 + 251 00ec 0768 ldr r7, [r0] + 252 .LVL33: + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 253 .loc 1 236 0 + 254 00ee 5E00 lsls r6, r3, #1 + 255 00f0 0324 movs r4, #3 + 256 00f2 2500 movs r5, r4 + ARM GAS /tmp/ccJYgg6T.s page 11 + + + 257 00f4 B540 lsls r5, r5, r6 + 258 00f6 ED43 mvns r5, r5 + 259 00f8 2F40 ands r7, r5 + 260 .LVL34: + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->MODER = temp; + 261 .loc 1 237 0 + 262 00fa 4A68 ldr r2, [r1, #4] + 263 00fc 1440 ands r4, r2 + 264 00fe B440 lsls r4, r4, r6 + 265 0100 3C43 orrs r4, r7 + 266 .LVL35: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 267 .loc 1 238 0 + 268 0102 0460 str r4, [r0] + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 269 .loc 1 241 0 + 270 0104 C468 ldr r4, [r0, #12] + 271 .LVL36: + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 272 .loc 1 242 0 + 273 0106 2540 ands r5, r4 + 274 .LVL37: + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 275 .loc 1 243 0 + 276 0108 8C68 ldr r4, [r1, #8] + 277 010a B440 lsls r4, r4, r6 + 278 010c 2C43 orrs r4, r5 + 279 .LVL38: + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 280 .loc 1 244 0 + 281 010e C460 str r4, [r0, #12] + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 282 .loc 1 248 0 + 283 0110 4A68 ldr r2, [r1, #4] + 284 0112 D200 lsls r2, r2, #3 + 285 0114 B1D5 bpl .L3 + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 286 .loc 1 251 0 + 287 0116 1B4D ldr r5, .L22+8 + 288 0118 6C6B ldr r4, [r5, #52] + 289 .LVL39: + 290 011a 0126 movs r6, #1 + 291 011c 3443 orrs r4, r6 + 292 011e 6C63 str r4, [r5, #52] + 293 .LVL40: + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** CLEAR_BIT(temp, ((uint32_t)0x0FU) << (4U * (position & 0x03U))); + 294 .loc 1 253 0 + 295 0120 9C08 lsrs r4, r3, #2 + 296 0122 A51C adds r5, r4, #2 + 297 0124 AD00 lsls r5, r5, #2 + 298 0126 154E ldr r6, .L22 + 299 0128 AF59 ldr r7, [r5, r6] + 300 .LVL41: + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U))); + 301 .loc 1 254 0 + 302 012a 0326 movs r6, #3 + 303 012c 1E40 ands r6, r3 + ARM GAS /tmp/ccJYgg6T.s page 12 + + + 304 012e B500 lsls r5, r6, #2 + 305 0130 0F26 movs r6, #15 + 306 0132 AE40 lsls r6, r6, r5 + 307 0134 B743 bics r7, r6 + 308 .LVL42: + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 309 .loc 1 255 0 + 310 0136 A026 movs r6, #160 + 311 0138 F605 lsls r6, r6, #23 + 312 013a B042 cmp r0, r6 + 313 013c 00D1 bne .LCB317 + 314 013e 66E7 b .L14 @long jump + 315 .LCB317: + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 316 .loc 1 255 0 is_stmt 0 discriminator 1 + 317 0140 114E ldr r6, .L22+12 + 318 0142 B042 cmp r0, r6 + 319 0144 0ED0 beq .L15 + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 320 .loc 1 255 0 discriminator 3 + 321 0146 114E ldr r6, .L22+16 + 322 0148 B042 cmp r0, r6 + 323 014a 0DD0 beq .L16 + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 324 .loc 1 255 0 discriminator 5 + 325 014c 104E ldr r6, .L22+20 + 326 014e B042 cmp r0, r6 + 327 0150 0CD0 beq .L17 + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 328 .loc 1 255 0 discriminator 7 + 329 0152 104E ldr r6, .L22+24 + 330 0154 B042 cmp r0, r6 + 331 0156 0BD0 beq .L18 + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 332 .loc 1 255 0 discriminator 9 + 333 0158 0F4E ldr r6, .L22+28 + 334 015a B042 cmp r0, r6 + 335 015c 00D1 bne .LCB332 + 336 015e 54E7 b .L21 @long jump + 337 .LCB332: + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 338 .loc 1 255 0 + 339 0160 0626 movs r6, #6 + 340 0162 55E7 b .L8 + 341 .L15: + 342 0164 0126 movs r6, #1 + 343 0166 53E7 b .L8 + 344 .L16: + 345 0168 0226 movs r6, #2 + 346 016a 51E7 b .L8 + 347 .L17: + 348 016c 0326 movs r6, #3 + 349 016e 4FE7 b .L8 + 350 .L18: + 351 0170 0426 movs r6, #4 + 352 0172 4DE7 b .L8 + 353 .LVL43: + ARM GAS /tmp/ccJYgg6T.s page 13 + + + 354 .L20: + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 355 .loc 1 295 0 is_stmt 1 + 356 @ sp needed + 357 0174 04BC pop {r2} + 358 0176 9046 mov r8, r2 + 359 0178 F0BD pop {r4, r5, r6, r7, pc} + 360 .L23: + 361 017a C046 .align 2 + 362 .L22: + 363 017c 00000140 .word 1073807360 + 364 0180 00040140 .word 1073808384 + 365 0184 00100240 .word 1073876992 + 366 0188 00040050 .word 1342178304 + 367 018c 00080050 .word 1342179328 + 368 0190 000C0050 .word 1342180352 + 369 0194 00100050 .word 1342181376 + 370 0198 001C0050 .word 1342184448 + 371 .cfi_endproc + 372 .LFE39: + 374 .section .text.HAL_GPIO_DeInit,"ax",%progbits + 375 .align 1 + 376 .global HAL_GPIO_DeInit + 377 .syntax unified + 378 .code 16 + 379 .thumb_func + 380 .fpu softvfp + 382 HAL_GPIO_DeInit: + 383 .LFB40: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief De-initializes the GPIOx peripheral registers to their default reset values. + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family d + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 384 .loc 1 307 0 + 385 .cfi_startproc + 386 @ args = 0, pretend = 0, frame = 0 + 387 @ frame_needed = 0, uses_anonymous_args = 0 + 388 .LVL44: + 389 0000 F0B5 push {r4, r5, r6, r7, lr} + 390 .LCFI2: + 391 .cfi_def_cfa_offset 20 + 392 .cfi_offset 4, -20 + 393 .cfi_offset 5, -16 + 394 .cfi_offset 6, -12 + 395 .cfi_offset 7, -8 + 396 .cfi_offset 14, -4 + 397 0002 D646 mov lr, r10 + 398 0004 4F46 mov r7, r9 + ARM GAS /tmp/ccJYgg6T.s page 14 + + + 399 0006 4646 mov r6, r8 + 400 0008 C0B5 push {r6, r7, lr} + 401 .LCFI3: + 402 .cfi_def_cfa_offset 32 + 403 .cfi_offset 8, -32 + 404 .cfi_offset 9, -28 + 405 .cfi_offset 10, -24 + 406 .LVL45: + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t position = 0x00U; + 407 .loc 1 308 0 + 408 000a 0023 movs r3, #0 + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t iocurrent = 0x00U; + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** uint32_t tmp = 0x00U; + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the port pins */ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** while ((GPIO_Pin >> position) != 0) + 409 .loc 1 316 0 + 410 000c 06E0 b .L25 + 411 .LVL46: + 412 .L37: + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Get the IO position */ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** iocurrent = (GPIO_Pin) & (1U << position); + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(iocurrent) + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure IO Direction in Input Floting Mode */ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4 + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Clear the External Interrupt or Event for the current IO */ + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp = SYSCFG->EXTICR[position >> 2U]; + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U))); + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 413 .loc 1 344 0 + 414 000e 0525 movs r5, #5 + 415 0010 00E0 b .L27 + 416 .L29: + 417 0012 0025 movs r5, #0 + 418 .L27: + ARM GAS /tmp/ccJYgg6T.s page 15 + + + 419 .loc 1 344 0 is_stmt 0 discriminator 24 + 420 0014 9540 lsls r5, r5, r2 + 421 0016 A542 cmp r5, r4 + 422 0018 54D0 beq .L35 + 423 .LVL47: + 424 .L26: + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U)); + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] &= ~tmp; + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->IMR &= ~((uint32_t)iocurrent); + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** position++; + 425 .loc 1 358 0 is_stmt 1 + 426 001a 0133 adds r3, r3, #1 + 427 .LVL48: + 428 .L25: + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 429 .loc 1 316 0 + 430 001c 0A00 movs r2, r1 + 431 001e DA40 lsrs r2, r2, r3 + 432 0020 66D0 beq .L36 + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 433 .loc 1 319 0 + 434 0022 0122 movs r2, #1 + 435 0024 9A40 lsls r2, r2, r3 + 436 0026 0C00 movs r4, r1 + 437 0028 1440 ands r4, r2 + 438 002a A446 mov ip, r4 + 439 .LVL49: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 440 .loc 1 321 0 + 441 002c F5D0 beq .L26 + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 442 .loc 1 325 0 + 443 002e 0668 ldr r6, [r0] + 444 0030 5D00 lsls r5, r3, #1 + 445 0032 0324 movs r4, #3 + 446 .LVL50: + 447 0034 A246 mov r10, r4 + 448 0036 2700 movs r7, r4 + 449 0038 AF40 lsls r7, r7, r5 + 450 003a 3D00 movs r5, r7 + 451 003c 3E43 orrs r6, r7 + 452 003e 0660 str r6, [r0] + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 453 .loc 1 328 0 + 454 0040 DF08 lsrs r7, r3, #3 + 455 0042 0837 adds r7, r7, #8 + 456 0044 BF00 lsls r7, r7, #2 + ARM GAS /tmp/ccJYgg6T.s page 16 + + + 457 0046 3C58 ldr r4, [r7, r0] + 458 0048 A146 mov r9, r4 + 459 004a 0726 movs r6, #7 + 460 004c 1E40 ands r6, r3 + 461 004e B600 lsls r6, r6, #2 + 462 0050 0F24 movs r4, #15 + 463 0052 A046 mov r8, r4 + 464 0054 B440 lsls r4, r4, r6 + 465 0056 2600 movs r6, r4 + 466 0058 4C46 mov r4, r9 + 467 005a B443 bics r4, r6 + 468 005c 3C50 str r4, [r7, r0] + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 469 .loc 1 331 0 + 470 005e 8668 ldr r6, [r0, #8] + 471 0060 ED43 mvns r5, r5 + 472 0062 2E40 ands r6, r5 + 473 0064 8660 str r6, [r0, #8] + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 474 .loc 1 334 0 + 475 0066 4668 ldr r6, [r0, #4] + 476 0068 9643 bics r6, r2 + 477 006a 4660 str r6, [r0, #4] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 478 .loc 1 337 0 + 479 006c C268 ldr r2, [r0, #12] + 480 006e 1540 ands r5, r2 + 481 0070 C560 str r5, [r0, #12] + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U))); + 482 .loc 1 342 0 + 483 0072 9E08 lsrs r6, r3, #2 + 484 0074 B51C adds r5, r6, #2 + 485 0076 AD00 lsls r5, r5, #2 + 486 0078 204A ldr r2, .L38 + 487 007a AD58 ldr r5, [r5, r2] + 488 .LVL51: + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 489 .loc 1 343 0 + 490 007c 5246 mov r2, r10 + 491 007e 1A40 ands r2, r3 + 492 0080 9200 lsls r2, r2, #2 + 493 0082 4746 mov r7, r8 + 494 0084 9740 lsls r7, r7, r2 + 495 0086 2C00 movs r4, r5 + 496 0088 3C40 ands r4, r7 + 497 .LVL52: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 498 .loc 1 344 0 + 499 008a A025 movs r5, #160 + 500 008c ED05 lsls r5, r5, #23 + 501 008e A842 cmp r0, r5 + 502 0090 BFD0 beq .L29 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 503 .loc 1 344 0 is_stmt 0 discriminator 1 + 504 0092 1B4D ldr r5, .L38+4 + 505 0094 A842 cmp r0, r5 + 506 0096 0DD0 beq .L30 + ARM GAS /tmp/ccJYgg6T.s page 17 + + + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 507 .loc 1 344 0 discriminator 3 + 508 0098 1A4D ldr r5, .L38+8 + 509 009a A842 cmp r0, r5 + 510 009c 0CD0 beq .L31 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 511 .loc 1 344 0 discriminator 5 + 512 009e 1A4D ldr r5, .L38+12 + 513 00a0 A842 cmp r0, r5 + 514 00a2 0BD0 beq .L32 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 515 .loc 1 344 0 discriminator 7 + 516 00a4 194D ldr r5, .L38+16 + 517 00a6 A842 cmp r0, r5 + 518 00a8 0AD0 beq .L33 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 519 .loc 1 344 0 discriminator 9 + 520 00aa 194D ldr r5, .L38+20 + 521 00ac A842 cmp r0, r5 + 522 00ae AED0 beq .L37 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 523 .loc 1 344 0 + 524 00b0 0625 movs r5, #6 + 525 00b2 AFE7 b .L27 + 526 .L30: + 527 00b4 0125 movs r5, #1 + 528 00b6 ADE7 b .L27 + 529 .L31: + 530 00b8 0225 movs r5, #2 + 531 00ba ABE7 b .L27 + 532 .L32: + 533 00bc 0325 movs r5, #3 + 534 00be A9E7 b .L27 + 535 .L33: + 536 00c0 0425 movs r5, #4 + 537 00c2 A7E7 b .L27 + 538 .L35: + 539 .LVL53: + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 540 .loc 1 347 0 is_stmt 1 + 541 00c4 0D4D ldr r5, .L38 + 542 00c6 B21C adds r2, r6, #2 + 543 00c8 9200 lsls r2, r2, #2 + 544 00ca 5459 ldr r4, [r2, r5] + 545 00cc BC43 bics r4, r7 + 546 00ce 5451 str r4, [r2, r5] + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 547 .loc 1 350 0 + 548 00d0 104C ldr r4, .L38+24 + 549 00d2 2568 ldr r5, [r4] + 550 00d4 6246 mov r2, ip + 551 00d6 D243 mvns r2, r2 + 552 00d8 1540 ands r5, r2 + 553 00da 2560 str r5, [r4] + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 554 .loc 1 351 0 + 555 00dc 6568 ldr r5, [r4, #4] + ARM GAS /tmp/ccJYgg6T.s page 18 + + + 556 00de 1540 ands r5, r2 + 557 00e0 6560 str r5, [r4, #4] + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 558 .loc 1 354 0 + 559 00e2 A568 ldr r5, [r4, #8] + 560 00e4 1540 ands r5, r2 + 561 00e6 A560 str r5, [r4, #8] + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 562 .loc 1 355 0 + 563 00e8 E568 ldr r5, [r4, #12] + 564 00ea 2A40 ands r2, r5 + 565 00ec E260 str r2, [r4, #12] + 566 00ee 94E7 b .L26 + 567 .LVL54: + 568 .L36: + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 569 .loc 1 360 0 + 570 @ sp needed + 571 00f0 1CBC pop {r2, r3, r4} + 572 00f2 9046 mov r8, r2 + 573 00f4 9946 mov r9, r3 + 574 00f6 A246 mov r10, r4 + 575 00f8 F0BD pop {r4, r5, r6, r7, pc} + 576 .L39: + 577 00fa C046 .align 2 + 578 .L38: + 579 00fc 00000140 .word 1073807360 + 580 0100 00040050 .word 1342178304 + 581 0104 00080050 .word 1342179328 + 582 0108 000C0050 .word 1342180352 + 583 010c 00100050 .word 1342181376 + 584 0110 001C0050 .word 1342184448 + 585 0114 00040140 .word 1073808384 + 586 .cfi_endproc + 587 .LFE40: + 589 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 590 .align 1 + 591 .global HAL_GPIO_ReadPin + 592 .syntax unified + 593 .code 16 + 594 .thumb_func + 595 .fpu softvfp + 597 HAL_GPIO_ReadPin: + 598 .LFB41: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @} + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions_Group2 + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief GPIO Read and Write + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @verbatim + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** =============================================================================== + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** ##### IO operation functions ##### + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** =============================================================================== + ARM GAS /tmp/ccJYgg6T.s page 19 + + + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** @endverbatim + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @{ + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Reads the specified input port pin. + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family d + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to read. + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This parameter can be GPIO_PIN_x where x can be (0..15). + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval The input port pin value. + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 599 .loc 1 388 0 + 600 .cfi_startproc + 601 @ args = 0, pretend = 0, frame = 0 + 602 @ frame_needed = 0, uses_anonymous_args = 0 + 603 @ link register save eliminated. + 604 .LVL55: + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIO_PinState bitstatus; + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 605 .loc 1 394 0 + 606 0000 0369 ldr r3, [r0, #16] + 607 0002 0B42 tst r3, r1 + 608 0004 01D1 bne .L43 + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** else + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 609 .loc 1 400 0 + 610 0006 0020 movs r0, #0 + 611 .LVL56: + 612 .L41: + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** return bitstatus; + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 613 .loc 1 403 0 + 614 @ sp needed + 615 0008 7047 bx lr + 616 .LVL57: + 617 .L43: + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 618 .loc 1 396 0 + 619 000a 0120 movs r0, #1 + 620 .LVL58: + 621 000c FCE7 b .L41 + 622 .cfi_endproc + 623 .LFE41: + ARM GAS /tmp/ccJYgg6T.s page 20 + + + 625 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 626 .align 1 + 627 .global HAL_GPIO_WritePin + 628 .syntax unified + 629 .code 16 + 630 .thumb_func + 631 .fpu softvfp + 633 HAL_GPIO_WritePin: + 634 .LFB42: + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Sets or clears the selected data port bit. + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR register to allow atomic read/modify + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * the read and the modify access. + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family d + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param PinState: specifies the value to be written to the selected bit. + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * GPIO_PIN_RESET: to clear the port pin + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * GPIO_PIN_SET: to set the port pin + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 635 .loc 1 424 0 + 636 .cfi_startproc + 637 @ args = 0, pretend = 0, frame = 0 + 638 @ frame_needed = 0, uses_anonymous_args = 0 + 639 @ link register save eliminated. + 640 .LVL59: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(PinState != GPIO_PIN_RESET) + 641 .loc 1 429 0 + 642 0000 002A cmp r2, #0 + 643 0002 01D1 bne .L47 + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->BSRR = GPIO_Pin; + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** else + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->BRR = GPIO_Pin ; + 644 .loc 1 435 0 + 645 0004 8162 str r1, [r0, #40] + 646 .L44: + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 647 .loc 1 437 0 + 648 @ sp needed + ARM GAS /tmp/ccJYgg6T.s page 21 + + + 649 0006 7047 bx lr + 650 .L47: + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 651 .loc 1 431 0 + 652 0008 8161 str r1, [r0, #24] + 653 000a FCE7 b .L44 + 654 .cfi_endproc + 655 .LFE42: + 657 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 658 .align 1 + 659 .global HAL_GPIO_TogglePin + 660 .syntax unified + 661 .code 16 + 662 .thumb_func + 663 .fpu softvfp + 665 HAL_GPIO_TogglePin: + 666 .LFB43: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Toggles the specified GPIO pins. + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family d + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the pins to be toggled. + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 667 .loc 1 448 0 + 668 .cfi_startproc + 669 @ args = 0, pretend = 0, frame = 0 + 670 @ frame_needed = 0, uses_anonymous_args = 0 + 671 @ link register save eliminated. + 672 .LVL60: + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->ODR ^= GPIO_Pin; + 673 .loc 1 452 0 + 674 0000 4369 ldr r3, [r0, #20] + 675 0002 5940 eors r1, r3 + 676 .LVL61: + 677 0004 4161 str r1, [r0, #20] + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 678 .loc 1 453 0 + 679 @ sp needed + 680 0006 7047 bx lr + 681 .cfi_endproc + 682 .LFE43: + 684 .section .text.HAL_GPIO_LockPin,"ax",%progbits + 685 .align 1 + 686 .global HAL_GPIO_LockPin + 687 .syntax unified + 688 .code 16 + 689 .thumb_func + 690 .fpu softvfp + 692 HAL_GPIO_LockPin: + ARM GAS /tmp/ccJYgg6T.s page 22 + + + 693 .LFB44: + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief Locks GPIO Pins configuration registers. + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * until the next reset. + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family. + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * Note that GPIOE is not available on all devices. + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be locked. + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * All port bits are not necessarily available on all GPIOs. + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 694 .loc 1 469 0 + 695 .cfi_startproc + 696 @ args = 0, pretend = 0, frame = 8 + 697 @ frame_needed = 0, uses_anonymous_args = 0 + 698 @ link register save eliminated. + 699 .LVL62: + 700 0000 82B0 sub sp, sp, #8 + 701 .LCFI4: + 702 .cfi_def_cfa_offset 8 + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 703 .loc 1 470 0 + 704 0002 8022 movs r2, #128 + 705 0004 5202 lsls r2, r2, #9 + 706 0006 0192 str r2, [sp, #4] + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Check the parameters */ + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Apply lock key write sequence */ + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp |= GPIO_Pin; + 707 .loc 1 476 0 + 708 0008 019B ldr r3, [sp, #4] + 709 000a 0B43 orrs r3, r1 + 710 000c 0193 str r3, [sp, #4] + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 711 .loc 1 478 0 + 712 000e 019B ldr r3, [sp, #4] + 713 0010 C361 str r3, [r0, #28] + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 714 .loc 1 480 0 + 715 0012 C161 str r1, [r0, #28] + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 716 .loc 1 482 0 + 717 0014 019B ldr r3, [sp, #4] + 718 0016 C361 str r3, [r0, #28] + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Read LCKK bit*/ + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** tmp = GPIOx->LCKR; + ARM GAS /tmp/ccJYgg6T.s page 23 + + + 719 .loc 1 484 0 + 720 0018 C369 ldr r3, [r0, #28] + 721 001a 0193 str r3, [sp, #4] + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + 722 .loc 1 486 0 + 723 001c C369 ldr r3, [r0, #28] + 724 001e 1342 tst r3, r2 + 725 0020 02D1 bne .L52 + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** return HAL_OK; + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** else + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** return HAL_ERROR; + 726 .loc 1 492 0 + 727 0022 0120 movs r0, #1 + 728 .LVL63: + 729 .L50: + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 730 .loc 1 494 0 + 731 0024 02B0 add sp, sp, #8 + 732 @ sp needed + 733 0026 7047 bx lr + 734 .LVL64: + 735 .L52: + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 736 .loc 1 488 0 + 737 0028 0020 movs r0, #0 + 738 .LVL65: + 739 002a FBE7 b .L50 + 740 .cfi_endproc + 741 .LFE44: + 743 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 744 .align 1 + 745 .weak HAL_GPIO_EXTI_Callback + 746 .syntax unified + 747 .code 16 + 748 .thumb_func + 749 .fpu softvfp + 751 HAL_GPIO_EXTI_Callback: + 752 .LFB46: + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief This function handles EXTI interrupt request. + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the pins connected to the EXTI line. + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + ARM GAS /tmp/ccJYgg6T.s page 24 + + + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /** + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @brief EXTI line detection callbacks. + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the pins connected to the EXTI line. + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** * @retval None + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 753 .loc 1 516 0 + 754 .cfi_startproc + 755 @ args = 0, pretend = 0, frame = 0 + 756 @ frame_needed = 0, uses_anonymous_args = 0 + 757 @ link register save eliminated. + 758 .LVL66: + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* NOTE: This function Should not be modified, when the callback is needed, + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** the HAL_GPIO_EXTI_Callback could be implemented in the user file + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** */ + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 759 .loc 1 523 0 + 760 @ sp needed + 761 0000 7047 bx lr + 762 .cfi_endproc + 763 .LFE46: + 765 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 766 .align 1 + 767 .global HAL_GPIO_EXTI_IRQHandler + 768 .syntax unified + 769 .code 16 + 770 .thumb_func + 771 .fpu softvfp + 773 HAL_GPIO_EXTI_IRQHandler: + 774 .LFB45: + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 775 .loc 1 501 0 + 776 .cfi_startproc + 777 @ args = 0, pretend = 0, frame = 0 + 778 @ frame_needed = 0, uses_anonymous_args = 0 + 779 .LVL67: + 780 0000 10B5 push {r4, lr} + 781 .LCFI5: + 782 .cfi_def_cfa_offset 8 + 783 .cfi_offset 4, -8 + 784 .cfi_offset 14, -4 + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** { + 785 .loc 1 503 0 + 786 0002 054B ldr r3, .L57 + 787 0004 5B69 ldr r3, [r3, #20] + 788 0006 1842 tst r0, r3 + 789 0008 00D1 bne .L56 + 790 .LVL68: + 791 .L54: + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 792 .loc 1 508 0 + 793 @ sp needed + ARM GAS /tmp/ccJYgg6T.s page 25 + + + 794 000a 10BD pop {r4, pc} + 795 .LVL69: + 796 .L56: + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 797 .loc 1 505 0 + 798 000c 024B ldr r3, .L57 + 799 000e 5861 str r0, [r3, #20] + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** } + 800 .loc 1 506 0 + 801 0010 FFF7FEFF bl HAL_GPIO_EXTI_Callback + 802 .LVL70: + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c **** + 803 .loc 1 508 0 + 804 0014 F9E7 b .L54 + 805 .L58: + 806 0016 C046 .align 2 + 807 .L57: + 808 0018 00040140 .word 1073808384 + 809 .cfi_endproc + 810 .LFE45: + 812 .text + 813 .Letext0: + 814 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 815 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 816 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 817 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 818 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 819 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 820 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 821 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 822 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 823 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 824 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + ARM GAS /tmp/ccJYgg6T.s page 26 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_gpio.c + /tmp/ccJYgg6T.s:16 .text.HAL_GPIO_Init:0000000000000000 $t + /tmp/ccJYgg6T.s:23 .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init + /tmp/ccJYgg6T.s:363 .text.HAL_GPIO_Init:000000000000017c $d + /tmp/ccJYgg6T.s:375 .text.HAL_GPIO_DeInit:0000000000000000 $t + /tmp/ccJYgg6T.s:382 .text.HAL_GPIO_DeInit:0000000000000000 HAL_GPIO_DeInit + /tmp/ccJYgg6T.s:579 .text.HAL_GPIO_DeInit:00000000000000fc $d + /tmp/ccJYgg6T.s:590 .text.HAL_GPIO_ReadPin:0000000000000000 $t + /tmp/ccJYgg6T.s:597 .text.HAL_GPIO_ReadPin:0000000000000000 HAL_GPIO_ReadPin + /tmp/ccJYgg6T.s:626 .text.HAL_GPIO_WritePin:0000000000000000 $t + /tmp/ccJYgg6T.s:633 .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin + /tmp/ccJYgg6T.s:658 .text.HAL_GPIO_TogglePin:0000000000000000 $t + /tmp/ccJYgg6T.s:665 .text.HAL_GPIO_TogglePin:0000000000000000 HAL_GPIO_TogglePin + /tmp/ccJYgg6T.s:685 .text.HAL_GPIO_LockPin:0000000000000000 $t + /tmp/ccJYgg6T.s:692 .text.HAL_GPIO_LockPin:0000000000000000 HAL_GPIO_LockPin + /tmp/ccJYgg6T.s:744 .text.HAL_GPIO_EXTI_Callback:0000000000000000 $t + /tmp/ccJYgg6T.s:751 .text.HAL_GPIO_EXTI_Callback:0000000000000000 HAL_GPIO_EXTI_Callback + /tmp/ccJYgg6T.s:766 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccJYgg6T.s:773 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 HAL_GPIO_EXTI_IRQHandler + /tmp/ccJYgg6T.s:808 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000018 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_i2c.d b/build/stm32l0xx_hal_i2c.d new file mode 100644 index 0000000..488c77d --- /dev/null +++ b/build/stm32l0xx_hal_i2c.d @@ -0,0 +1,105 @@ +build/stm32l0xx_hal_i2c.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c Inc/vcom.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Inc/vcom.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_i2c.lst b/build/stm32l0xx_hal_i2c.lst new file mode 100644 index 0000000..31eebb5 --- /dev/null +++ b/build/stm32l0xx_hal_i2c.lst @@ -0,0 +1,17938 @@ +ARM GAS /tmp/ccpuPECZ.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_i2c.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 I2C_DMASlaveTransmitCplt: + 23 .LFB99: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @file stm32l0xx_hal_i2c.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + IO operation functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @verbatim + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ============================================================================== + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ##### How to use this driver ##### + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ============================================================================== + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (##) I2C pins configuration + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx channel + ARM GAS /tmp/ccpuPECZ.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the DMA Tx or Rx channel + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** Polling mode IO operation *** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ================================= + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit( + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ===================================== + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =================================== + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ErrorCallback() + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** Interrupt mode IO sequential operation *** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ============================================== + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + ARM GAS /tmp/ccpuPECZ.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** when a direction change during transfer + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfa + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** and data to transfer without a final stop condition + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** and data to transfer without a final stop condition, an then permit a c + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2 + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Differents sequential I2C interfaces are listed below: + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code to check the Address Match Code and the transmission direction request + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2 + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ErrorCallback() + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ======================================= + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Mem_Write_IT() + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Mem_Read_IT() + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + ARM GAS /tmp/ccpuPECZ.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ErrorCallback() + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** DMA mode IO operation *** + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ============================== + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Master_Transmit_DMA() + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Master_Receive_DMA() + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Slave_Transmit_DMA() + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Slave_Receive_DMA() + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ErrorCallback() + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ================================= + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Mem_Write_DMA() + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_Mem_Read_DMA() + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** add his own code by customization of function pointer HAL_I2C_ErrorCallback() + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ================================== + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + ARM GAS /tmp/ccpuPECZ.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @endverbatim + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ****************************************************************************** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @attention + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * Redistribution and use in source and binary forms, with or without modification, + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * are permitted provided that the following conditions are met: + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * 1. Redistributions of source code must retain the above copyright notice, + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * this list of conditions and the following disclaimer. + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * this list of conditions and the following disclaimer in the documentation + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * and/or other materials provided with the distribution. + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * may be used to endorse or promote products derived from this software + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * without specific prior written permission. + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ****************************************************************************** + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #include + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #include "stm32l0xx_hal.h" + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @addtogroup STM32L0xx_HAL_Driver + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C I2C + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C HAL module driver + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + ARM GAS /tmp/ccpuPECZ.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define SlaveAddr_SHIFT 7U + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define SlaveAddr_MSK 0x06U + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~( + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MOD + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MOD + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MOD + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MOD + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MOD + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MOD + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_TX_IT (0x00000001U) + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_RX_IT (0x00000002U) + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (0x00000004U) + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (0x00000011U) + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (0x00000012U) + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (0x00000012U) + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private macro -------------------------------------------------------------*/ + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + ARM GAS /tmp/ccpuPECZ.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint1 + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16 + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint3 + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uin + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to flush TXDR register */ + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Private functions to handle start, restart or stop a transfer */ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @verbatim + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the selected configuration: + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Clock Timing + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Own Address 1 + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Dual Addressing mode + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Own Address 2 + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Own Address 2 Mask + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) General call mode + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Nostretch mode + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** of the selected I2Cx peripheral. + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @endverbatim + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c == NULL) + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddr + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccpuPECZ.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c == NULL) + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Release Lock */ + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); + ARM GAS /tmp/ccpuPECZ.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Data transfers functions + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @verbatim + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ##### IO operation functions ##### + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** transfers. + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) There are two modes of transfer: + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** The status of all data processing is returned by the same function + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** after finishing transfer. + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** The end of the data processing will be indicated through the + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** using DMA mode. + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) Blocking mode functions are : + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + ARM GAS /tmp/ccpuPECZ.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @endverbatim + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRIT + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + ARM GAS /tmp/ccpuPECZ.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRI + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR */ + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TCR flag is set */ + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is set */ + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + ARM GAS /tmp/ccpuPECZ.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_REA + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TCR flag is set */ + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + ARM GAS /tmp/ccpuPECZ.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is set */ + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, ui + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); + ARM GAS /tmp/ccpuPECZ.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR */ + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOP flag is set */ + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Normal use case for Transmitter mode */ + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* A NACK is generated to confirm the end of transfer */ + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP flag */ + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uin +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 20 + + +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Store Last receive data if any */ +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP flag */ +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccpuPECZ.s page 21 + + +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccpuPECZ.s page 22 + + +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + ARM GAS /tmp/ccpuPECZ.s page 23 + + +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + ARM GAS /tmp/ccpuPECZ.s page 24 + + +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 25 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + ARM GAS /tmp/ccpuPECZ.s page 26 + + +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSi +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update XferCount value */ +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRI + ARM GAS /tmp/ccpuPECZ.s page 27 + + +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 28 + + +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSi +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update XferCount value */ +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_REA +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current + ARM GAS /tmp/ccpuPECZ.s page 29 + + +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 30 + + +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ + ARM GAS /tmp/ccpuPECZ.s page 31 + + +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 32 + + +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** do +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 33 + + +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR */ +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U); +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccpuPECZ.s page 34 + + +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("Bad pData or Size=0\r\n"); +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("Timeout\r\n"); +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 35 + + +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("Error in memory read - %d\r\n", hi2c->ErrorCode); +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_REA +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** do +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("waiting for flag timeout1\r\n"); +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +1959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("waiting for flag timeout2\r\n"); +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccpuPECZ.s page 36 + + +1973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (hi2c->XferCount > 0U); +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("waiting for stop error %d\r\n", hi2c->ErrorCode); +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +1998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +1999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("busy!!\r\n"); +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface + ARM GAS /tmp/ccpuPECZ.s page 37 + + +2030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + ARM GAS /tmp/ccpuPECZ.s page 38 + + +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + ARM GAS /tmp/ccpuPECZ.s page 39 + + +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +2186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + ARM GAS /tmp/ccpuPECZ.s page 40 + + +2201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* possible to enable all of these */ +2211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA +2234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +2236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); + ARM GAS /tmp/ccpuPECZ.s page 41 + + +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +2284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +2299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ +2301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize +2309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address */ +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update XferCount value */ + ARM GAS /tmp/ccpuPECZ.s page 42 + + +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +2327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +2339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be read +2347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +2352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 43 + + +2372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +2400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +2415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the DMA error callback */ +2417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +2424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize +2425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); +2428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 44 + + +2429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update XferCount value */ +2430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +2436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +2454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @note This function is used with Memory devices +2455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Trials Number of trials +2460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +2461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +2464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; +2466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0U; +2468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** do +2483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Generate Start */ +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + ARM GAS /tmp/ccpuPECZ.s page 45 + + +2486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +2489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_F +2491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +2493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) +2495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Device is ready */ +2497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +2506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) +2507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +2510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +2515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Device is ready */ +2518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +2529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +2534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +2535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +2537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if the maximum allowed number of trials has been reached */ +2541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_Trials++ == Trials) +2542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 46 + + +2543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Generate Stop */ +2544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +2545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +2548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +2553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (I2C_Trials < Trials); +2557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +2564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +2573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +2574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +2581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddres +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +2587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +2590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +2598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 47 + + +2600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +2604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If size > MAX_NBYTE_SIZE, use reload mode */ +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +2616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If transfer direction not change, do not generate Restart Condition */ +2619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +2620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) +2621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +2623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +2626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); +2627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter +2646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +2647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +2654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress + ARM GAS /tmp/ccpuPECZ.s page 48 + + +2657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +2659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +2660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +2663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +2671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +2677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +2680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +2689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If transfer direction not change, do not generate Restart Condition */ +2692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +2693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) +2694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +2696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +2699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); +2700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccpuPECZ.s page 49 + + +2714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +2719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +2720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +2725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uin +2728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +2731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) +2733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +2740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +2741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +2746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +2747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +2748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable associated Interrupts */ +2750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +2751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +2754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +2766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +2768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +2770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ + ARM GAS /tmp/ccpuPECZ.s page 50 + + +2771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +2772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* REnable ADDR interrupt */ +2781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +2782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +2793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +2794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +2799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint +2802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +2804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +2805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) +2807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +2814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +2815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +2820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +2821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +2822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable associated Interrupts */ +2824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +2825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + ARM GAS /tmp/ccpuPECZ.s page 51 + + +2828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; +2837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +2839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +2840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +2842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +2844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +2845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +2846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* REnable ADDR interrupt */ +2855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +2856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +2867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +2872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +2877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +2879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 52 + + +2885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +2891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C +2893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +2896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +2898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tmp; +2899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +2901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +2902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); +2905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +2908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +2910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; +2917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Abort a master I2C IT or DMA process communication with Interrupt. +2922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +2926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +2927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +2929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) +2931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +2936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +2937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +2938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +2940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; +2941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 53 + + +2942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +2943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +2944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); +2945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +2947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** process unlock */ +2952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +2953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +2955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +2957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wrong usage of abort function */ +2959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +2960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +2961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} +2966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +2969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ +2970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +2974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +2977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +2979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +2981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +2982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +2983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +2985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferISR != NULL) +2986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +2987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); +2988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +2990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +2991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +2992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +2993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +2996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +2997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +2998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 54 + + +2999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +3000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +3001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) +3004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; +3006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear BERR flag */ +3008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +3009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +3012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) +3013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; +3015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear OVR flag */ +3017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +3018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +3021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) +3022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; +3024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ARLO flag */ +3026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +3027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +3030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C +3031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +3033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +3038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +3043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +3049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +3054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccpuPECZ.s page 55 + + +3056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +3059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +3065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +3069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +3074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +3080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +3085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +3090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file +3096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Slave Address Match callback. +3101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +3104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +3105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +3108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(TransferDirection); +3112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(AddrMatchCode); + ARM GAS /tmp/ccpuPECZ.s page 56 + + +3113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +3116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Listen Complete callback. +3121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +3126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +3132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +3137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +3142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +3148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. +3153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +3158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +3164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C error callback. +3169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccpuPECZ.s page 57 + + +3170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +3174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +3180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C abort callback. +3185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +3190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hi2c); +3193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +3195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +3196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} +3201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +3204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +3205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * +3206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @verbatim +3207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== +3208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +3209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** =============================================================================== +3210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** [..] +3211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +3212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** and the data flow. +3213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** @endverbatim +3215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ +3216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Return the I2C handle state. +3220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL state +3223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +3225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Return I2C handle state */ + ARM GAS /tmp/ccpuPECZ.s page 58 + + +3227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return hi2c->State; +3228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +3232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for I2C module +3234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL mode +3235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +3237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return hi2c->Mode; +3239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Return the I2C error code. +3243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval I2C Error Code +3246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +3248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return hi2c->ErrorCode; +3250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} +3254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @} +3258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +3261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @{ +3262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +3266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +3270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint +3273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t devaddress = 0U; +3275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) +3280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 59 + + +3284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set corresponding Error Code */ +3285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +3286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +3287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +3288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +3290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +3291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) +3293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +3295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +3296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +3297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +3298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) +3300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR */ +3302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); +3303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +3304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +3305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) +3307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) +3309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); +3311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +3316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +3321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP) +3323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +3327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +3333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +3334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +3336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITMasterSequentialCplt(hi2c); +3337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ + ARM GAS /tmp/ccpuPECZ.s page 60 + + +3341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +3343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) +3347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +3349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +3351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +3353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +3354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Generate Stop */ +3356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +3357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +3361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITMasterSequentialCplt(hi2c); +3362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +3368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +3370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) +3374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Master complete process */ +3376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +3377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +3387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +3391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint3 +3394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process locked */ +3396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 61 + + +3398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) +3399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check that I2C transfer finished */ +3401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +3402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean XferCount == 0*/ +3403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* So clear Flag NACKF only */ +3404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +3405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME) +3407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_LISTEN)) +3408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Listen complete process */ +3410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +3411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_ +3413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +3418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +3419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +3421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +3422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITSlaveSequentialCplt(hi2c); +3423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +3433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +3437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +3438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) +3441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +3443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +3445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +3446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +3447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +3448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ +3451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) +3452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +3454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITSlaveSequentialCplt(hi2c); + ARM GAS /tmp/ccpuPECZ.s page 62 + + +3455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) +3458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); +3460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) +3462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +3464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +3465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if all Datas have already been sent */ +3466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +3467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +3468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write data to TXDR */ +3470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); +3471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +3472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +3473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) +3477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +3479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +3480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITSlaveSequentialCplt(hi2c); +3481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if STOPF is set */ +3486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) +3487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Slave complete process */ +3489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +3490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +3500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +3504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uin +3507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t devaddress = 0U; +3509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; +3510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/ccpuPECZ.s page 63 + + +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) +3515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set corresponding Error Code */ +3520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +3521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +3523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +3524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +3525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +3526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +3528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +3529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) +3531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable TC interrupt */ +3533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); +3534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +3536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Recover Slave address */ +3538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); +3539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +3541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +3550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ +3553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +3554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update XferCount value */ +3556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable DMA Request */ +3559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +3560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +3566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else + ARM GAS /tmp/ccpuPECZ.s page 64 + + +3569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +3571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +3573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) +3576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Master complete process */ +3578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +3579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +3589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +3593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint +3596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process locked */ +3598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) +3601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check that I2C transfer finished */ +3603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +3604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean XferCount == 0 */ +3605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* So clear Flag NACKF only */ +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) +3607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +3614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +3618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +3619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) +3622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ +3624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 65 + + +3626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) +3627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Slave complete process */ +3629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +3630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques +3640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +3644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +3645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +3646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +3647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +3648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint1 +3651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); +3653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +3656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +3658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +3660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +3668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +3669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Memory Address */ +3671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +3672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +3674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send MSB of Memory Address */ +3677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +3678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +3680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +3681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + ARM GAS /tmp/ccpuPECZ.s page 66 + + +3683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +3685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send LSB of Memory Address */ +3693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +3694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +3697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) +3698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +3707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * in datasheet must be shift at right before call interface +3711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddress Internal memory address +3712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +3713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +3714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +3715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +3716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16 +3718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); +3720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +3722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +3723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("I2C_RequestMemoryRead error %d\r\n", hi2c->ErrorCode); +3725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +3726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +3728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +3736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +3737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send Memory Address */ +3739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + ARM GAS /tmp/ccpuPECZ.s page 67 + + +3740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +3742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send MSB of Memory Address */ +3745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +3746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +3748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +3749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("I2C_RequestMemoryRead error2 %d\r\n", hi2c->ErrorCode); +3751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +3752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +3754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Send LSB of Memory Address */ +3762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +3763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until TC flag is set */ +3766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("I2C_RequestMemoryRead TIMEOUT\r\n"); +3769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +3770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +3773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Address complete process callback. +3777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +3778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +3782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint8_t transferdirection = 0U; +3784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t slaveaddrcode = 0U; +3785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t ownadd1code = 0U; +3786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t ownadd2code = 0U; +3787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +3789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(ITFlags); +3790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ +3792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) +3793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); +3795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); +3796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ARM GAS /tmp/ccpuPECZ.s page 68 + + +3797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); +3798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +3800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +3801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) +3803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** slaveaddrcode = ownadd1code; +3805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->AddrEventCount++; +3806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) +3807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset Address Event counter */ +3809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; +3810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ +3812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call Slave Addr callback */ +3818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +3819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +3824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +3826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +3827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call Slave Addr callback */ +3832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +3833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +3836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +3839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +3840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call Slave Addr callback */ +3845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +3846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Else clear address flag only */ +3849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ +3852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 69 + + +3854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +3861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +3862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +3865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset I2C handle mode */ +3867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +3870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +3871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +3872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +3875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +3876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +3878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +3879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +3885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +3887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +3888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +3891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +3892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +3894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +3901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +3906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +3907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +3910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 70 + + +3911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset I2C handle mode */ +3912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +3915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ +3917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +3919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +3921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +3922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Tx complete callback to inform upper layer of the end of transmit process */ +3927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +3928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +3933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +3935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +3937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Rx complete callback to inform upper layer of the end of receive process */ +3943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +3944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +3948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Master complete process. +3949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +3950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +3951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +3952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +3953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +3954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +3956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +3959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +3960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset handle parameters */ +3962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +3963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +3964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +3965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((ITFlags & I2C_FLAG_AF) != RESET) +3967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 71 + + +3968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +3969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set acknowledge error code */ +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +3973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +3976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +3977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +3979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); +3980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) +3983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +3985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +3986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +3987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +3988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +3989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +3993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +3994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +3997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +3999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +4001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +4011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +4014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +4019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 72 + + +4025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +4026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +4035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Slave complete process. +4041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +4042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +4046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +4048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +4049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear ADDR flag */ +4051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable all interrupts */ +4054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); +4055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +4057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +4058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +4060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +4061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +4063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +4066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || +4067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) +4068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); +4070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +4073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +4074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Store Last receive data if any */ +4080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_RXNE) != RESET)) +4081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 73 + + +4082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +4083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +4084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +4086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +4088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +4089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +4096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +4098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) +4100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +4103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +4105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +4106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call I2C Listen complete process */ +4108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +4109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +4112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +4114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +4120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +4121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Slave Rx Complete callback */ +4131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +4132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/ccpuPECZ.s page 74 + + +4139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Slave Tx Complete callback */ +4141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +4142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Listen complete process. +4147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +4148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +4152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset handle parameters */ +4154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +4155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +4156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +4159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Store Last receive data if any */ +4161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (((ITFlags & I2C_FLAG_RXNE) != RESET)) +4162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Read data from RXDR */ +4164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; +4165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +4167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; +4169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; +4170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable all Interrupts*/ +4177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +4178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACK Flag */ +4180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +4186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +4187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C interrupts error process. +4191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +4192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param ErrorCode Error code to handle. +4193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) + ARM GAS /tmp/ccpuPECZ.s page 75 + + +4196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset handle parameters */ +4198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +4200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = 0U; +4201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set new error code */ +4203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; +4204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Interrupts */ +4206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) || +4207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || +4208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) +4209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +4211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); +4212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +4214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +4216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable all interrupts */ +4221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +4222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If state is an abort treatment on goind, don't change state */ +4224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* This change will be do later */ +4225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) +4226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +4228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +4231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; +4232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +4235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Abort DMA TX */ +4247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 76 + + +4253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +4254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Abort DMA RX */ +4266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ +4269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_ABORT) +4273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +4281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +4289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +4294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +4295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +4298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +4300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) +4302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; +4304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register if not empty */ +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) +4308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + ARM GAS /tmp/ccpuPECZ.s page 77 + + +4310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +4315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle +4316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +4319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +4321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable DMA Request */ +4323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +4326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable STOP interrupt */ +4329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +4332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update Buffer pointer */ +4335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +4336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the XferSize to transfer */ +4338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ +4348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c- +4349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable TC interrupts */ +4351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +4352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +4357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle +4358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +4361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 25 .loc 1 4361 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + ARM GAS /tmp/ccpuPECZ.s page 78 + + + 30 .LVL0: +4362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hdma); +4364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +4366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +4367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +4368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 31 .loc 1 4368 0 + 32 @ sp needed + 33 0000 7047 bx lr + 34 .cfi_endproc + 35 .LFE99: + 37 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 38 .align 1 + 39 .syntax unified + 40 .code 16 + 41 .thumb_func + 42 .fpu softvfp + 44 I2C_DMASlaveReceiveCplt: + 45 .LFB101: +4369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +4372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle +4373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +4376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +4378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable DMA Request */ +4380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +4383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable STOP interrupt */ +4386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +4389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Update Buffer pointer */ +4392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +4393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Set the XferSize to transfer */ +4395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccpuPECZ.s page 79 + + +4405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c- +4406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable TC interrupts */ +4408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +4409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +4414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle +4415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +4418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 46 .loc 1 4418 0 + 47 .cfi_startproc + 48 @ args = 0, pretend = 0, frame = 0 + 49 @ frame_needed = 0, uses_anonymous_args = 0 + 50 @ link register save eliminated. + 51 .LVL1: +4419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** UNUSED(hdma); +4421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +4423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +4424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +4425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 52 .loc 1 4425 0 + 53 @ sp needed + 54 0000 7047 bx lr + 55 .cfi_endproc + 56 .LFE101: + 58 .section .text.I2C_Disable_IRQ,"ax",%progbits + 59 .align 1 + 60 .syntax unified + 61 .code 16 + 62 .thumb_func + 63 .fpu softvfp + 65 I2C_Disable_IRQ: + 66 .LFB111: +4426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +4429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle +4430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +4435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Acknowledge */ +4437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +4438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +4441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 80 + + +4443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +4445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +4446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hdma DMA handle. +4447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +4450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +4452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable Acknowledge */ +4454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +4455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +4457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +4459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if come from abort from user */ +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) +4462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +4467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +4472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. +4477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +4480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Status The new Flag status (SET or RESET). +4481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +4482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +4483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +4486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) +4488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check for the Timeout */ +4490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +4491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) +4493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccpuPECZ.s page 81 + + +4500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +4508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +4511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +4512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +4515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) +4517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if a NACK is detected */ +4519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +4520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("I2C_WaitOnTXISFlagUntilTimeout ->I2C_IsAcknowledgeFailed error\r\n"); +4522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +4523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check for the Timeout */ +4526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +4527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) +4529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +4531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** PRINTF("I2C_WaitOnTXISFlagUntilTimeout timeout\r\n"); +4538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +4539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +4547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +4550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +4551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +4554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +4556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 82 + + +4557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if a NACK is detected */ +4558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +4559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +4561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check for the Timeout */ +4564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) +4565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +4567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +4574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +4581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +4584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +4585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +4588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) +4590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if a NACK is detected */ +4592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +4593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +4595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check if a STOPF is detected */ +4598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) +4599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +4601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +4602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +4604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +4605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccpuPECZ.s page 83 + + +4614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check for the Timeout */ +4617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) +4618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +4620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +4626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief This function handles Acknowledge failed detection during an I2C Communication. +4633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Timeout Timeout duration +4636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Tickstart Tick start value +4637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ +4640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +4642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Wait until STOP Flag is reset */ +4644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +4645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +4646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check for the Timeout */ +4648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +4649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) +4651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; +4658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear NACKF Flag */ +4663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ +4666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +4667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Flush TX register */ +4669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 84 + + +4671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +4672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +4673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_AF; +4675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; +4682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +4688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c I2C handle. +4689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +4690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. +4691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +4692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +4693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * This parameter can be one of the following values: +4694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . +4695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +4696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +4697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +4698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * This parameter can be one of the following values: +4699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +4700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +4701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +4702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +4703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval None +4704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_ +4706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ +4708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); +4709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); +4710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); +4711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* update CR2 register */ +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEN +4714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ +4715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +4719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +4722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +4725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tmpisr = 0U; +4727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 85 + + +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ +4729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) +4730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) +4732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +4734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +4735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) +4738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +4740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +4741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) +4744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable STOP interrupts */ +4746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +4747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) +4750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable TC interrupts */ +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +4753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** else +4756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) +4758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, and ADDR interrupts */ +4760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +4761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) +4764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +4766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; +4767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) +4770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +4772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; +4773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) +4776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable STOP interrupts */ +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +4779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable interrupts only at the end */ +4783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +4784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* all interrupts requested done */ + ARM GAS /tmp/ccpuPECZ.s page 86 + + +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +4786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** +4791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +4792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +4795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** * @retval HAL status +4796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** */ +4797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +4798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 67 .loc 1 4798 0 + 68 .cfi_startproc + 69 @ args = 0, pretend = 0, frame = 0 + 70 @ frame_needed = 0, uses_anonymous_args = 0 + 71 .LVL2: + 72 0000 30B5 push {r4, r5, lr} + 73 .LCFI0: + 74 .cfi_def_cfa_offset 12 + 75 .cfi_offset 4, -12 + 76 .cfi_offset 5, -8 + 77 .cfi_offset 14, -4 + 78 .LVL3: +4799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tmpisr = 0U; +4800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 79 .loc 1 4801 0 + 80 0002 CB07 lsls r3, r1, #31 + 81 0004 09D5 bpl .L10 + 82 .LVL4: +4802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +4804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; +4805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + 83 .loc 1 4806 0 + 84 0006 4123 movs r3, #65 + 85 0008 C35C ldrb r3, [r0, r3] + 86 000a 2822 movs r2, #40 + 87 000c 1340 ands r3, r2 + 88 000e 282B cmp r3, #40 + 89 0010 01D0 beq .L13 +4807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +4809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 90 .loc 1 4809 0 + 91 0012 F223 movs r3, #242 + 92 0014 02E0 b .L4 + 93 .L13: +4804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 94 .loc 1 4804 0 + 95 0016 1A33 adds r3, r3, #26 + 96 0018 00E0 b .L4 + 97 .LVL5: + ARM GAS /tmp/ccpuPECZ.s page 87 + + + 98 .L10: +4799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 99 .loc 1 4799 0 + 100 001a 0023 movs r3, #0 + 101 .LVL6: + 102 .L4: +4810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 103 .loc 1 4813 0 + 104 001c 8A07 lsls r2, r1, #30 + 105 001e 09D5 bpl .L5 +4814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +4816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 106 .loc 1 4816 0 + 107 0020 4424 movs r4, #68 + 108 0022 1C43 orrs r4, r3 + 109 .LVL7: +4817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + 110 .loc 1 4818 0 + 111 0024 4122 movs r2, #65 + 112 0026 825C ldrb r2, [r0, r2] + 113 0028 2825 movs r5, #40 + 114 002a 2A40 ands r2, r5 + 115 002c 282A cmp r2, #40 + 116 002e 15D0 beq .L12 +4819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +4821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 117 .loc 1 4821 0 + 118 0030 F422 movs r2, #244 + 119 0032 1343 orrs r3, r2 + 120 .LVL8: + 121 .L5: +4822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 122 .loc 1 4825 0 + 123 0034 4A07 lsls r2, r1, #29 + 124 0036 01D5 bpl .L6 +4826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +4828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 125 .loc 1 4828 0 + 126 0038 B822 movs r2, #184 + 127 003a 1343 orrs r3, r2 + 128 .LVL9: + 129 .L6: +4829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + 130 .loc 1 4831 0 + 131 003c 1122 movs r2, #17 + ARM GAS /tmp/ccpuPECZ.s page 88 + + + 132 003e 0A40 ands r2, r1 + 133 0040 112A cmp r2, #17 + 134 0042 0DD0 beq .L14 + 135 .L7: + 136 0044 1222 movs r2, #18 + 137 0046 1140 ands r1, r2 + 138 .LVL10: +4832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +4834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +4835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + 139 .loc 1 4837 0 + 140 0048 1229 cmp r1, #18 + 141 004a 0CD0 beq .L15 + 142 .L8: +4838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable STOP interrupts */ +4840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +4841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + 143 .loc 1 4843 0 + 144 004c 1229 cmp r1, #18 + 145 004e 0DD0 beq .L16 + 146 .L9: +4844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { +4845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Enable TC interrupts */ +4846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +4847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } +4848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Disable interrupts only at the end */ +4850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +4851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* all disable interrupts request are not done */ +4852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 147 .loc 1 4852 0 + 148 0050 0168 ldr r1, [r0] + 149 0052 0A68 ldr r2, [r1] + 150 0054 9A43 bics r2, r3 + 151 0056 0A60 str r2, [r1] +4853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** +4854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_OK; +4855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 152 .loc 1 4855 0 + 153 0058 0020 movs r0, #0 + 154 .LVL11: + 155 @ sp needed + 156 005a 30BD pop {r4, r5, pc} + 157 .LVL12: + 158 .L12: +4816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 159 .loc 1 4816 0 + 160 005c 2300 movs r3, r4 + 161 005e E9E7 b .L5 + 162 .LVL13: + 163 .L14: + ARM GAS /tmp/ccpuPECZ.s page 89 + + +4834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 164 .loc 1 4834 0 + 165 0060 7F32 adds r2, r2, #127 + 166 0062 1343 orrs r3, r2 + 167 .LVL14: + 168 0064 EEE7 b .L7 + 169 .LVL15: + 170 .L15: +4840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 171 .loc 1 4840 0 + 172 0066 0E32 adds r2, r2, #14 + 173 0068 1343 orrs r3, r2 + 174 .LVL16: + 175 006a EFE7 b .L8 + 176 .L16: +4846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 177 .loc 1 4846 0 + 178 006c 4022 movs r2, #64 + 179 006e 1343 orrs r3, r2 + 180 .LVL17: + 181 0070 EEE7 b .L9 + 182 .cfi_endproc + 183 .LFE111: + 185 .section .text.I2C_IsAcknowledgeFailed,"ax",%progbits + 186 .align 1 + 187 .syntax unified + 188 .code 16 + 189 .thumb_func + 190 .fpu softvfp + 192 I2C_IsAcknowledgeFailed: + 193 .LFB108: +4640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 194 .loc 1 4640 0 + 195 .cfi_startproc + 196 @ args = 0, pretend = 0, frame = 0 + 197 @ frame_needed = 0, uses_anonymous_args = 0 + 198 .LVL18: + 199 0000 70B5 push {r4, r5, r6, lr} + 200 .LCFI1: + 201 .cfi_def_cfa_offset 16 + 202 .cfi_offset 4, -16 + 203 .cfi_offset 5, -12 + 204 .cfi_offset 6, -8 + 205 .cfi_offset 14, -4 + 206 0002 0400 movs r4, r0 + 207 0004 0E00 movs r6, r1 + 208 0006 1500 movs r5, r2 +4641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 209 .loc 1 4641 0 + 210 0008 0368 ldr r3, [r0] + 211 000a 9B69 ldr r3, [r3, #24] + 212 000c DB06 lsls r3, r3, #27 + 213 000e 16D5 bpl .L25 + 214 .LVL19: + 215 .L20: +4645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 216 .loc 1 4645 0 + ARM GAS /tmp/ccpuPECZ.s page 90 + + + 217 0010 2368 ldr r3, [r4] + 218 0012 9A69 ldr r2, [r3, #24] + 219 0014 9206 lsls r2, r2, #26 + 220 0016 14D4 bmi .L26 +4648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 221 .loc 1 4648 0 + 222 0018 731C adds r3, r6, #1 + 223 001a F9D0 beq .L20 +4650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 224 .loc 1 4650 0 + 225 001c 002E cmp r6, #0 + 226 001e 04D0 beq .L21 +4650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 227 .loc 1 4650 0 is_stmt 0 discriminator 1 + 228 0020 FFF7FEFF bl HAL_GetTick + 229 .LVL20: + 230 0024 401B subs r0, r0, r5 + 231 0026 B042 cmp r0, r6 + 232 0028 F2D9 bls .L20 + 233 .L21: +4652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 234 .loc 1 4652 0 is_stmt 1 + 235 002a 4123 movs r3, #65 + 236 002c 2022 movs r2, #32 + 237 002e E254 strb r2, [r4, r3] +4653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 238 .loc 1 4653 0 + 239 0030 0023 movs r3, #0 + 240 0032 2232 adds r2, r2, #34 + 241 0034 A354 strb r3, [r4, r2] +4656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 242 .loc 1 4656 0 + 243 0036 023A subs r2, r2, #2 + 244 0038 A354 strb r3, [r4, r2] +4657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 245 .loc 1 4657 0 + 246 003a 0320 movs r0, #3 + 247 003c 24E0 b .L19 + 248 .LVL21: + 249 .L25: +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 250 .loc 1 4683 0 + 251 003e 0020 movs r0, #0 + 252 .LVL22: + 253 0040 22E0 b .L19 + 254 .LVL23: + 255 .L26: +4663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 256 .loc 1 4663 0 + 257 0042 1022 movs r2, #16 + 258 0044 DA61 str r2, [r3, #28] +4666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 259 .loc 1 4666 0 + 260 0046 2368 ldr r3, [r4] + 261 0048 1032 adds r2, r2, #16 + 262 004a DA61 str r2, [r3, #28] + 263 .LVL24: + ARM GAS /tmp/ccpuPECZ.s page 91 + + + 264 .LBB142: + 265 .LBB143: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 266 .loc 1 4301 0 + 267 004c 2368 ldr r3, [r4] + 268 004e 9A69 ldr r2, [r3, #24] + 269 0050 9207 lsls r2, r2, #30 + 270 0052 01D5 bpl .L23 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 271 .loc 1 4303 0 + 272 0054 0022 movs r2, #0 + 273 0056 9A62 str r2, [r3, #40] + 274 .L23: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 275 .loc 1 4307 0 + 276 0058 2368 ldr r3, [r4] + 277 005a 9A69 ldr r2, [r3, #24] + 278 005c D207 lsls r2, r2, #31 + 279 005e 03D4 bmi .L24 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 280 .loc 1 4309 0 + 281 0060 9A69 ldr r2, [r3, #24] + 282 0062 0121 movs r1, #1 + 283 0064 0A43 orrs r2, r1 + 284 0066 9A61 str r2, [r3, #24] + 285 .L24: + 286 .LVL25: + 287 .LBE143: + 288 .LBE142: +4672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 289 .loc 1 4672 0 + 290 0068 2268 ldr r2, [r4] + 291 006a 5368 ldr r3, [r2, #4] + 292 006c 0749 ldr r1, .L27 + 293 006e 0B40 ands r3, r1 + 294 0070 5360 str r3, [r2, #4] +4674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 295 .loc 1 4674 0 + 296 0072 0423 movs r3, #4 + 297 0074 6364 str r3, [r4, #68] +4675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 298 .loc 1 4675 0 + 299 0076 3D33 adds r3, r3, #61 + 300 0078 2022 movs r2, #32 + 301 007a E254 strb r2, [r4, r3] +4676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 302 .loc 1 4676 0 + 303 007c 0023 movs r3, #0 + 304 007e 2232 adds r2, r2, #34 + 305 0080 A354 strb r3, [r4, r2] +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 306 .loc 1 4679 0 + 307 0082 023A subs r2, r2, #2 + 308 0084 A354 strb r3, [r4, r2] +4681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 309 .loc 1 4681 0 + 310 0086 0120 movs r0, #1 + ARM GAS /tmp/ccpuPECZ.s page 92 + + + 311 .L19: +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 312 .loc 1 4684 0 + 313 @ sp needed + 314 .LVL26: + 315 .LVL27: + 316 .LVL28: + 317 0088 70BD pop {r4, r5, r6, pc} + 318 .L28: + 319 008a C046 .align 2 + 320 .L27: + 321 008c 00E800FE .word -33495040 + 322 .cfi_endproc + 323 .LFE108: + 325 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 326 .align 1 + 327 .syntax unified + 328 .code 16 + 329 .thumb_func + 330 .fpu softvfp + 332 I2C_WaitOnFlagUntilTimeout: + 333 .LFB104: +4486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 334 .loc 1 4486 0 + 335 .cfi_startproc + 336 @ args = 4, pretend = 0, frame = 0 + 337 @ frame_needed = 0, uses_anonymous_args = 0 + 338 .LVL29: + 339 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 340 .LCFI2: + 341 .cfi_def_cfa_offset 24 + 342 .cfi_offset 3, -24 + 343 .cfi_offset 4, -20 + 344 .cfi_offset 5, -16 + 345 .cfi_offset 6, -12 + 346 .cfi_offset 7, -8 + 347 .cfi_offset 14, -4 + 348 0002 0600 movs r6, r0 + 349 0004 0C00 movs r4, r1 + 350 0006 1700 movs r7, r2 + 351 0008 1D00 movs r5, r3 + 352 .LVL30: + 353 .L31: +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 354 .loc 1 4487 0 + 355 000a 3368 ldr r3, [r6] + 356 000c 9B69 ldr r3, [r3, #24] + 357 000e 2340 ands r3, r4 + 358 0010 1B1B subs r3, r3, r4 + 359 0012 5A42 rsbs r2, r3, #0 + 360 0014 5341 adcs r3, r3, r2 + 361 0016 BB42 cmp r3, r7 + 362 0018 13D1 bne .L35 +4490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 363 .loc 1 4490 0 + 364 001a 6B1C adds r3, r5, #1 + 365 001c F5D0 beq .L31 + ARM GAS /tmp/ccpuPECZ.s page 93 + + +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 366 .loc 1 4492 0 + 367 001e 002D cmp r5, #0 + 368 0020 05D0 beq .L32 +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 369 .loc 1 4492 0 is_stmt 0 discriminator 1 + 370 0022 FFF7FEFF bl HAL_GetTick + 371 .LVL31: + 372 0026 069B ldr r3, [sp, #24] + 373 0028 C01A subs r0, r0, r3 + 374 002a A842 cmp r0, r5 + 375 002c EDD9 bls .L31 + 376 .L32: +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 377 .loc 1 4494 0 is_stmt 1 + 378 002e 4123 movs r3, #65 + 379 0030 2022 movs r2, #32 + 380 0032 F254 strb r2, [r6, r3] +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 381 .loc 1 4495 0 + 382 0034 0023 movs r3, #0 + 383 0036 2232 adds r2, r2, #34 + 384 0038 B354 strb r3, [r6, r2] +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 385 .loc 1 4498 0 + 386 003a 023A subs r2, r2, #2 + 387 003c B354 strb r3, [r6, r2] +4499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 388 .loc 1 4499 0 + 389 003e 0320 movs r0, #3 + 390 0040 00E0 b .L33 + 391 .L35: +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 392 .loc 1 4503 0 + 393 0042 0020 movs r0, #0 + 394 .L33: +4504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 395 .loc 1 4504 0 + 396 @ sp needed + 397 .LVL32: + 398 .LVL33: + 399 .LVL34: + 400 0044 F8BD pop {r3, r4, r5, r6, r7, pc} + 401 .cfi_endproc + 402 .LFE104: + 404 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 405 .align 1 + 406 .syntax unified + 407 .code 16 + 408 .thumb_func + 409 .fpu softvfp + 411 I2C_WaitOnSTOPFlagUntilTimeout: + 412 .LFB106: +4554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 413 .loc 1 4554 0 + 414 .cfi_startproc + 415 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccpuPECZ.s page 94 + + + 416 @ frame_needed = 0, uses_anonymous_args = 0 + 417 .LVL35: + 418 0000 70B5 push {r4, r5, r6, lr} + 419 .LCFI3: + 420 .cfi_def_cfa_offset 16 + 421 .cfi_offset 4, -16 + 422 .cfi_offset 5, -12 + 423 .cfi_offset 6, -8 + 424 .cfi_offset 14, -4 + 425 0002 0500 movs r5, r0 + 426 0004 0C00 movs r4, r1 + 427 0006 1600 movs r6, r2 + 428 .LVL36: + 429 .L37: +4555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 430 .loc 1 4555 0 + 431 0008 2B68 ldr r3, [r5] + 432 000a 9B69 ldr r3, [r3, #24] + 433 000c 9B06 lsls r3, r3, #26 + 434 000e 1AD4 bmi .L42 +4558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 435 .loc 1 4558 0 + 436 0010 3200 movs r2, r6 + 437 0012 2100 movs r1, r4 + 438 0014 2800 movs r0, r5 + 439 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 440 .LVL37: + 441 001a 0028 cmp r0, #0 + 442 001c 15D1 bne .L41 +4564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 443 .loc 1 4564 0 + 444 001e 002C cmp r4, #0 + 445 0020 04D0 beq .L39 +4564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 446 .loc 1 4564 0 is_stmt 0 discriminator 1 + 447 0022 FFF7FEFF bl HAL_GetTick + 448 .LVL38: + 449 0026 801B subs r0, r0, r6 + 450 0028 A042 cmp r0, r4 + 451 002a EDD9 bls .L37 + 452 .L39: +4566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 453 .loc 1 4566 0 is_stmt 1 + 454 002c 6B6C ldr r3, [r5, #68] + 455 002e 2022 movs r2, #32 + 456 0030 1343 orrs r3, r2 + 457 0032 6B64 str r3, [r5, #68] +4567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 458 .loc 1 4567 0 + 459 0034 4123 movs r3, #65 + 460 0036 EA54 strb r2, [r5, r3] +4568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 461 .loc 1 4568 0 + 462 0038 0023 movs r3, #0 + 463 003a 2232 adds r2, r2, #34 + 464 003c AB54 strb r3, [r5, r2] +4571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 95 + + + 465 .loc 1 4571 0 + 466 003e 023A subs r2, r2, #2 + 467 0040 AB54 strb r3, [r5, r2] +4573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 468 .loc 1 4573 0 + 469 0042 0320 movs r0, #3 + 470 .L38: +4577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 471 .loc 1 4577 0 + 472 @ sp needed + 473 .LVL39: + 474 .LVL40: + 475 .LVL41: + 476 0044 70BD pop {r4, r5, r6, pc} + 477 .LVL42: + 478 .L42: +4576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 479 .loc 1 4576 0 + 480 0046 0020 movs r0, #0 + 481 0048 FCE7 b .L38 + 482 .L41: +4560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 483 .loc 1 4560 0 + 484 004a 0120 movs r0, #1 + 485 004c FAE7 b .L38 + 486 .cfi_endproc + 487 .LFE106: + 489 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 490 .align 1 + 491 .syntax unified + 492 .code 16 + 493 .thumb_func + 494 .fpu softvfp + 496 I2C_WaitOnRXNEFlagUntilTimeout: + 497 .LFB107: +4588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 498 .loc 1 4588 0 + 499 .cfi_startproc + 500 @ args = 0, pretend = 0, frame = 0 + 501 @ frame_needed = 0, uses_anonymous_args = 0 + 502 .LVL43: + 503 0000 70B5 push {r4, r5, r6, lr} + 504 .LCFI4: + 505 .cfi_def_cfa_offset 16 + 506 .cfi_offset 4, -16 + 507 .cfi_offset 5, -12 + 508 .cfi_offset 6, -8 + 509 .cfi_offset 14, -4 + 510 0002 0400 movs r4, r0 + 511 0004 0D00 movs r5, r1 + 512 0006 1600 movs r6, r2 + 513 .LVL44: + 514 .L44: +4589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 515 .loc 1 4589 0 + 516 0008 2368 ldr r3, [r4] + 517 000a 9B69 ldr r3, [r3, #24] + ARM GAS /tmp/ccpuPECZ.s page 96 + + + 518 000c 5B07 lsls r3, r3, #29 + 519 000e 2DD4 bmi .L50 +4592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 520 .loc 1 4592 0 + 521 0010 3200 movs r2, r6 + 522 0012 2900 movs r1, r5 + 523 0014 2000 movs r0, r4 + 524 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 525 .LVL45: + 526 001a 0028 cmp r0, #0 + 527 001c 28D1 bne .L49 +4598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 528 .loc 1 4598 0 + 529 001e 2368 ldr r3, [r4] + 530 0020 9A69 ldr r2, [r3, #24] + 531 0022 9206 lsls r2, r2, #26 + 532 0024 11D4 bmi .L51 +4617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 533 .loc 1 4617 0 + 534 0026 002D cmp r5, #0 + 535 0028 04D0 beq .L47 +4617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 536 .loc 1 4617 0 is_stmt 0 discriminator 1 + 537 002a FFF7FEFF bl HAL_GetTick + 538 .LVL46: + 539 002e 801B subs r0, r0, r6 + 540 0030 A842 cmp r0, r5 + 541 0032 E9D9 bls .L44 + 542 .L47: +4619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 543 .loc 1 4619 0 is_stmt 1 + 544 0034 636C ldr r3, [r4, #68] + 545 0036 2022 movs r2, #32 + 546 0038 1343 orrs r3, r2 + 547 003a 6364 str r3, [r4, #68] +4620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 548 .loc 1 4620 0 + 549 003c 4123 movs r3, #65 + 550 003e E254 strb r2, [r4, r3] +4623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 551 .loc 1 4623 0 + 552 0040 013B subs r3, r3, #1 + 553 0042 0022 movs r2, #0 + 554 0044 E254 strb r2, [r4, r3] +4625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 555 .loc 1 4625 0 + 556 0046 0320 movs r0, #3 + 557 .L45: +4629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 558 .loc 1 4629 0 + 559 @ sp needed + 560 .LVL47: + 561 .LVL48: + 562 .LVL49: + 563 0048 70BD pop {r4, r5, r6, pc} + 564 .LVL50: + 565 .L51: + ARM GAS /tmp/ccpuPECZ.s page 97 + + +4601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 566 .loc 1 4601 0 + 567 004a 2022 movs r2, #32 + 568 004c DA61 str r2, [r3, #28] +4604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 569 .loc 1 4604 0 + 570 004e 2168 ldr r1, [r4] + 571 0050 4B68 ldr r3, [r1, #4] + 572 0052 0848 ldr r0, .L52 + 573 0054 0340 ands r3, r0 + 574 0056 4B60 str r3, [r1, #4] +4606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 575 .loc 1 4606 0 + 576 0058 0023 movs r3, #0 + 577 005a 6364 str r3, [r4, #68] +4607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 578 .loc 1 4607 0 + 579 005c 4121 movs r1, #65 + 580 005e 6254 strb r2, [r4, r1] +4608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 581 .loc 1 4608 0 + 582 0060 2232 adds r2, r2, #34 + 583 0062 A354 strb r3, [r4, r2] +4611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 584 .loc 1 4611 0 + 585 0064 023A subs r2, r2, #2 + 586 0066 A354 strb r3, [r4, r2] +4613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 587 .loc 1 4613 0 + 588 0068 0120 movs r0, #1 + 589 006a EDE7 b .L45 + 590 .L50: +4628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 591 .loc 1 4628 0 + 592 006c 0020 movs r0, #0 + 593 006e EBE7 b .L45 + 594 .L49: +4594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 595 .loc 1 4594 0 + 596 0070 0120 movs r0, #1 + 597 0072 E9E7 b .L45 + 598 .L53: + 599 .align 2 + 600 .L52: + 601 0074 00E800FE .word -33495040 + 602 .cfi_endproc + 603 .LFE107: + 605 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 606 .align 1 + 607 .syntax unified + 608 .code 16 + 609 .thumb_func + 610 .fpu softvfp + 612 I2C_WaitOnTXISFlagUntilTimeout: + 613 .LFB105: +4515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 614 .loc 1 4515 0 + ARM GAS /tmp/ccpuPECZ.s page 98 + + + 615 .cfi_startproc + 616 @ args = 0, pretend = 0, frame = 0 + 617 @ frame_needed = 0, uses_anonymous_args = 0 + 618 .LVL51: + 619 0000 70B5 push {r4, r5, r6, lr} + 620 .LCFI5: + 621 .cfi_def_cfa_offset 16 + 622 .cfi_offset 4, -16 + 623 .cfi_offset 5, -12 + 624 .cfi_offset 6, -8 + 625 .cfi_offset 14, -4 + 626 0002 0400 movs r4, r0 + 627 0004 0D00 movs r5, r1 + 628 0006 1600 movs r6, r2 + 629 .LVL52: + 630 .L58: +4516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 631 .loc 1 4516 0 + 632 0008 2368 ldr r3, [r4] + 633 000a 9B69 ldr r3, [r3, #24] + 634 000c 9B07 lsls r3, r3, #30 + 635 000e 24D4 bmi .L61 +4519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 636 .loc 1 4519 0 + 637 0010 3200 movs r2, r6 + 638 0012 2900 movs r1, r5 + 639 0014 2000 movs r0, r4 + 640 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 641 .LVL53: + 642 001a 0028 cmp r0, #0 + 643 001c 18D1 bne .L62 +4526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 644 .loc 1 4526 0 + 645 001e 6B1C adds r3, r5, #1 + 646 0020 F2D0 beq .L58 +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 647 .loc 1 4528 0 + 648 0022 002D cmp r5, #0 + 649 0024 04D0 beq .L59 +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 650 .loc 1 4528 0 is_stmt 0 discriminator 1 + 651 0026 FFF7FEFF bl HAL_GetTick + 652 .LVL54: + 653 002a 801B subs r0, r0, r6 + 654 002c A842 cmp r0, r5 + 655 002e EBD9 bls .L58 + 656 .L59: +4530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 657 .loc 1 4530 0 is_stmt 1 + 658 0030 636C ldr r3, [r4, #68] + 659 0032 2022 movs r2, #32 + 660 0034 1343 orrs r3, r2 + 661 0036 6364 str r3, [r4, #68] +4531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 662 .loc 1 4531 0 + 663 0038 4123 movs r3, #65 + 664 003a E254 strb r2, [r4, r3] + ARM GAS /tmp/ccpuPECZ.s page 99 + + +4532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 665 .loc 1 4532 0 + 666 003c 0023 movs r3, #0 + 667 003e 2232 adds r2, r2, #34 + 668 0040 A354 strb r3, [r4, r2] +4535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 669 .loc 1 4535 0 + 670 0042 023A subs r2, r2, #2 + 671 0044 A354 strb r3, [r4, r2] +4537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 672 .loc 1 4537 0 + 673 0046 0648 ldr r0, .L63 + 674 0048 FFF7FEFF bl vcom_Send + 675 .LVL55: +4538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 676 .loc 1 4538 0 + 677 004c 0320 movs r0, #3 + 678 004e 05E0 b .L57 + 679 .L62: +4521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 680 .loc 1 4521 0 + 681 0050 0448 ldr r0, .L63+4 + 682 0052 FFF7FEFF bl vcom_Send + 683 .LVL56: +4522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 684 .loc 1 4522 0 + 685 0056 0120 movs r0, #1 + 686 0058 00E0 b .L57 + 687 .L61: +4542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 688 .loc 1 4542 0 + 689 005a 0020 movs r0, #0 + 690 .L57: +4543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 691 .loc 1 4543 0 + 692 @ sp needed + 693 .LVL57: + 694 .LVL58: + 695 .LVL59: + 696 005c 70BD pop {r4, r5, r6, pc} + 697 .L64: + 698 005e C046 .align 2 + 699 .L63: + 700 0060 44000000 .word .LC2 + 701 0064 00000000 .word .LC0 + 702 .cfi_endproc + 703 .LFE105: + 705 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 706 .align 1 + 707 .syntax unified + 708 .code 16 + 709 .thumb_func + 710 .fpu softvfp + 712 I2C_RequestMemoryWrite: + 713 .LFB88: +3651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + 714 .loc 1 3651 0 + ARM GAS /tmp/ccpuPECZ.s page 100 + + + 715 .cfi_startproc + 716 @ args = 8, pretend = 0, frame = 0 + 717 @ frame_needed = 0, uses_anonymous_args = 0 + 718 .LVL60: + 719 0000 F0B5 push {r4, r5, r6, r7, lr} + 720 .LCFI6: + 721 .cfi_def_cfa_offset 20 + 722 .cfi_offset 4, -20 + 723 .cfi_offset 5, -16 + 724 .cfi_offset 6, -12 + 725 .cfi_offset 7, -8 + 726 .cfi_offset 14, -4 + 727 0002 83B0 sub sp, sp, #12 + 728 .LCFI7: + 729 .cfi_def_cfa_offset 32 + 730 0004 0600 movs r6, r0 + 731 0006 1500 movs r5, r2 + 732 0008 1C00 movs r4, r3 +3652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 733 .loc 1 3652 0 + 734 000a DAB2 uxtb r2, r3 + 735 .LVL61: + 736 .LBB144: + 737 .LBB145: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 738 .loc 1 4713 0 + 739 000c 0068 ldr r0, [r0] + 740 .LVL62: + 741 000e 4368 ldr r3, [r0, #4] + 742 .LVL63: + 743 0010 1F4F ldr r7, .L73 + 744 0012 3B40 ands r3, r7 + 745 0014 8905 lsls r1, r1, #22 + 746 .LVL64: + 747 0016 890D lsrs r1, r1, #22 + 748 0018 1204 lsls r2, r2, #16 + 749 .LVL65: + 750 001a 1143 orrs r1, r2 + 751 001c 1D4A ldr r2, .L73+4 + 752 001e 1143 orrs r1, r2 + 753 0020 1943 orrs r1, r3 + 754 0022 4160 str r1, [r0, #4] + 755 .LVL66: + 756 .LBE145: + 757 .LBE144: +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 758 .loc 1 3655 0 + 759 0024 099A ldr r2, [sp, #36] + 760 0026 0899 ldr r1, [sp, #32] + 761 0028 3000 movs r0, r6 + 762 002a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 763 .LVL67: + 764 002e 0028 cmp r0, #0 + 765 0030 05D0 beq .L66 +3657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 766 .loc 1 3657 0 + 767 0032 736C ldr r3, [r6, #68] + ARM GAS /tmp/ccpuPECZ.s page 101 + + + 768 0034 042B cmp r3, #4 + 769 0036 26D1 bne .L71 +3659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 770 .loc 1 3659 0 + 771 0038 0120 movs r0, #1 + 772 .L67: +3703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 773 .loc 1 3703 0 + 774 003a 03B0 add sp, sp, #12 + 775 @ sp needed + 776 .LVL68: + 777 003c F0BD pop {r4, r5, r6, r7, pc} + 778 .LVL69: + 779 .L66: +3668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 780 .loc 1 3668 0 + 781 003e 012C cmp r4, #1 + 782 0040 0ED1 bne .L68 +3671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 783 .loc 1 3671 0 + 784 0042 3368 ldr r3, [r6] + 785 0044 EDB2 uxtb r5, r5 + 786 0046 9D62 str r5, [r3, #40] + 787 .L69: +3697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 788 .loc 1 3697 0 + 789 0048 099B ldr r3, [sp, #36] + 790 004a 0093 str r3, [sp] + 791 004c 089B ldr r3, [sp, #32] + 792 004e 0022 movs r2, #0 + 793 0050 8021 movs r1, #128 + 794 0052 3000 movs r0, r6 + 795 0054 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 796 .LVL70: + 797 0058 0028 cmp r0, #0 + 798 005a EED0 beq .L67 +3699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 799 .loc 1 3699 0 + 800 005c 0320 movs r0, #3 + 801 005e ECE7 b .L67 + 802 .L68: +3677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 803 .loc 1 3677 0 + 804 0060 3368 ldr r3, [r6] + 805 0062 2A0A lsrs r2, r5, #8 + 806 0064 9A62 str r2, [r3, #40] +3680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 807 .loc 1 3680 0 + 808 0066 099A ldr r2, [sp, #36] + 809 0068 0899 ldr r1, [sp, #32] + 810 006a 3000 movs r0, r6 + 811 006c FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 812 .LVL71: + 813 0070 0028 cmp r0, #0 + 814 0072 04D0 beq .L70 +3682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 815 .loc 1 3682 0 + ARM GAS /tmp/ccpuPECZ.s page 102 + + + 816 0074 736C ldr r3, [r6, #68] + 817 0076 042B cmp r3, #4 + 818 0078 07D1 bne .L72 +3684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 819 .loc 1 3684 0 + 820 007a 0120 movs r0, #1 + 821 007c DDE7 b .L67 + 822 .L70: +3693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 823 .loc 1 3693 0 + 824 007e 3368 ldr r3, [r6] + 825 0080 EDB2 uxtb r5, r5 + 826 0082 9D62 str r5, [r3, #40] + 827 0084 E0E7 b .L69 + 828 .L71: +3663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 829 .loc 1 3663 0 + 830 0086 0320 movs r0, #3 + 831 0088 D7E7 b .L67 + 832 .L72: +3688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 833 .loc 1 3688 0 + 834 008a 0320 movs r0, #3 + 835 008c D5E7 b .L67 + 836 .L74: + 837 008e C046 .align 2 + 838 .L73: + 839 0090 009800FC .word -67069952 + 840 0094 00200081 .word -2130698240 + 841 .cfi_endproc + 842 .LFE88: + 844 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 845 .align 1 + 846 .syntax unified + 847 .code 16 + 848 .thumb_func + 849 .fpu softvfp + 851 I2C_RequestMemoryRead: + 852 .LFB89: +3718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + 853 .loc 1 3718 0 + 854 .cfi_startproc + 855 @ args = 8, pretend = 0, frame = 0 + 856 @ frame_needed = 0, uses_anonymous_args = 0 + 857 .LVL72: + 858 0000 F0B5 push {r4, r5, r6, r7, lr} + 859 .LCFI8: + 860 .cfi_def_cfa_offset 20 + 861 .cfi_offset 4, -20 + 862 .cfi_offset 5, -16 + 863 .cfi_offset 6, -12 + 864 .cfi_offset 7, -8 + 865 .cfi_offset 14, -4 + 866 0002 83B0 sub sp, sp, #12 + 867 .LCFI9: + 868 .cfi_def_cfa_offset 32 + 869 0004 0600 movs r6, r0 + ARM GAS /tmp/ccpuPECZ.s page 103 + + + 870 0006 1400 movs r4, r2 + 871 0008 1D00 movs r5, r3 +3719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 872 .loc 1 3719 0 + 873 000a DAB2 uxtb r2, r3 + 874 .LVL73: + 875 .LBB146: + 876 .LBB147: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 877 .loc 1 4713 0 + 878 000c 0068 ldr r0, [r0] + 879 .LVL74: + 880 000e 4368 ldr r3, [r0, #4] + 881 .LVL75: + 882 0010 254F ldr r7, .L86 + 883 0012 3B40 ands r3, r7 + 884 0014 8905 lsls r1, r1, #22 + 885 .LVL76: + 886 0016 890D lsrs r1, r1, #22 + 887 0018 1204 lsls r2, r2, #16 + 888 .LVL77: + 889 001a 1143 orrs r1, r2 + 890 001c 234A ldr r2, .L86+4 + 891 001e 1143 orrs r1, r2 + 892 0020 1943 orrs r1, r3 + 893 0022 4160 str r1, [r0, #4] + 894 .LVL78: + 895 .LBE147: + 896 .LBE146: +3722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 897 .loc 1 3722 0 + 898 0024 099A ldr r2, [sp, #36] + 899 0026 0899 ldr r1, [sp, #32] + 900 0028 3000 movs r0, r6 + 901 002a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 902 .LVL79: + 903 002e 0028 cmp r0, #0 + 904 0030 10D1 bne .L83 +3736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 905 .loc 1 3736 0 + 906 0032 012D cmp r5, #1 + 907 0034 17D1 bne .L78 +3739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 908 .loc 1 3739 0 + 909 0036 3368 ldr r3, [r6] + 910 0038 E4B2 uxtb r4, r4 + 911 003a 9C62 str r4, [r3, #40] + 912 .L79: +3766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 913 .loc 1 3766 0 + 914 003c 099B ldr r3, [sp, #36] + 915 003e 0093 str r3, [sp] + 916 0040 089B ldr r3, [sp, #32] + 917 0042 0022 movs r2, #0 + 918 0044 4021 movs r1, #64 + 919 0046 3000 movs r0, r6 + 920 0048 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + ARM GAS /tmp/ccpuPECZ.s page 104 + + + 921 .LVL80: + 922 004c 0028 cmp r0, #0 + 923 004e 21D1 bne .L84 + 924 .L77: +3773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 925 .loc 1 3773 0 + 926 0050 03B0 add sp, sp, #12 + 927 @ sp needed + 928 .LVL81: + 929 0052 F0BD pop {r4, r5, r6, r7, pc} + 930 .LVL82: + 931 .L83: +3724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 932 .loc 1 3724 0 + 933 0054 716C ldr r1, [r6, #68] + 934 0056 1648 ldr r0, .L86+8 + 935 0058 FFF7FEFF bl vcom_Send + 936 .LVL83: +3725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 937 .loc 1 3725 0 + 938 005c 736C ldr r3, [r6, #68] + 939 005e 042B cmp r3, #4 + 940 0060 1DD1 bne .L81 +3727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 941 .loc 1 3727 0 + 942 0062 0120 movs r0, #1 + 943 0064 F4E7 b .L77 + 944 .L78: +3745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 945 .loc 1 3745 0 + 946 0066 3368 ldr r3, [r6] + 947 0068 220A lsrs r2, r4, #8 + 948 006a 9A62 str r2, [r3, #40] +3748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 949 .loc 1 3748 0 + 950 006c 099A ldr r2, [sp, #36] + 951 006e 0899 ldr r1, [sp, #32] + 952 0070 3000 movs r0, r6 + 953 0072 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 954 .LVL84: + 955 0076 0028 cmp r0, #0 + 956 0078 03D1 bne .L85 +3762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 957 .loc 1 3762 0 + 958 007a 3368 ldr r3, [r6] + 959 007c E4B2 uxtb r4, r4 + 960 007e 9C62 str r4, [r3, #40] + 961 0080 DCE7 b .L79 + 962 .L85: +3750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 963 .loc 1 3750 0 + 964 0082 716C ldr r1, [r6, #68] + 965 0084 0B48 ldr r0, .L86+12 + 966 0086 FFF7FEFF bl vcom_Send + 967 .LVL85: +3751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 968 .loc 1 3751 0 + ARM GAS /tmp/ccpuPECZ.s page 105 + + + 969 008a 736C ldr r3, [r6, #68] + 970 008c 042B cmp r3, #4 + 971 008e 08D1 bne .L82 +3753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 972 .loc 1 3753 0 + 973 0090 0120 movs r0, #1 + 974 0092 DDE7 b .L77 + 975 .L84: +3768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 976 .loc 1 3768 0 + 977 0094 0848 ldr r0, .L86+16 + 978 0096 FFF7FEFF bl vcom_Send + 979 .LVL86: +3769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 980 .loc 1 3769 0 + 981 009a 0320 movs r0, #3 + 982 009c D8E7 b .L77 + 983 .L81: +3731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 984 .loc 1 3731 0 + 985 009e 0320 movs r0, #3 + 986 00a0 D6E7 b .L77 + 987 .L82: +3757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 988 .loc 1 3757 0 + 989 00a2 0320 movs r0, #3 + 990 00a4 D4E7 b .L77 + 991 .L87: + 992 00a6 C046 .align 2 + 993 .L86: + 994 00a8 009800FC .word -67069952 + 995 00ac 00200080 .word -2147475456 + 996 00b0 00000000 .word .LC4 + 997 00b4 24000000 .word .LC6 + 998 00b8 48000000 .word .LC8 + 999 .cfi_endproc + 1000 .LFE89: + 1002 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 1003 .align 1 + 1004 .syntax unified + 1005 .code 16 + 1006 .thumb_func + 1007 .fpu softvfp + 1009 I2C_DMAMasterTransmitCplt: + 1010 .LFB98: +4319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 1011 .loc 1 4319 0 + 1012 .cfi_startproc + 1013 @ args = 0, pretend = 0, frame = 0 + 1014 @ frame_needed = 0, uses_anonymous_args = 0 + 1015 .LVL87: + 1016 0000 10B5 push {r4, lr} + 1017 .LCFI10: + 1018 .cfi_def_cfa_offset 8 + 1019 .cfi_offset 4, -8 + 1020 .cfi_offset 14, -4 +4320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 106 + + + 1021 .loc 1 4320 0 + 1022 0002 846A ldr r4, [r0, #40] + 1023 .LVL88: +4323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1024 .loc 1 4323 0 + 1025 0004 2268 ldr r2, [r4] + 1026 0006 1368 ldr r3, [r2] + 1027 0008 1E49 ldr r1, .L101 + 1028 000a 0B40 ands r3, r1 + 1029 000c 1360 str r3, [r2] +4326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1030 .loc 1 4326 0 + 1031 000e 638D ldrh r3, [r4, #42] + 1032 0010 9BB2 uxth r3, r3 + 1033 0012 002B cmp r3, #0 + 1034 0014 10D1 bne .L89 + 1035 .LVL89: + 1036 .LBB148: + 1037 .LBB149: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 1038 .loc 1 4728 0 + 1039 0016 636B ldr r3, [r4, #52] + 1040 0018 1B4A ldr r2, .L101+4 + 1041 001a 9342 cmp r3, r2 + 1042 001c 0AD0 beq .L95 + 1043 001e 1B4A ldr r2, .L101+8 + 1044 0020 9342 cmp r3, r2 + 1045 0022 05D0 beq .L99 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1046 .loc 1 4778 0 + 1047 0024 F421 movs r1, #244 + 1048 .L90: + 1049 .LVL90: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1050 .loc 1 4785 0 + 1051 0026 2268 ldr r2, [r4] + 1052 0028 1368 ldr r3, [r2] + 1053 002a 0B43 orrs r3, r1 + 1054 002c 1360 str r3, [r2] + 1055 .LVL91: + 1056 .L88: + 1057 .LBE149: + 1058 .LBE148: +4353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1059 .loc 1 4353 0 + 1060 @ sp needed + 1061 .LVL92: + 1062 002e 10BD pop {r4, pc} + 1063 .LVL93: + 1064 .L99: + 1065 .LBB151: + 1066 .LBB150: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1067 .loc 1 4752 0 + 1068 0030 6021 movs r1, #96 + 1069 0032 F8E7 b .L90 + 1070 .L95: + ARM GAS /tmp/ccpuPECZ.s page 107 + + + 1071 0034 6021 movs r1, #96 + 1072 0036 F6E7 b .L90 + 1073 .LVL94: + 1074 .L89: + 1075 .LBE150: + 1076 .LBE151: +4335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1077 .loc 1 4335 0 + 1078 0038 218D ldrh r1, [r4, #40] + 1079 003a 636A ldr r3, [r4, #36] + 1080 003c 9C46 mov ip, r3 + 1081 003e 6144 add r1, r1, ip + 1082 0040 6162 str r1, [r4, #36] +4338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1083 .loc 1 4338 0 + 1084 0042 638D ldrh r3, [r4, #42] + 1085 0044 9BB2 uxth r3, r3 + 1086 0046 FF2B cmp r3, #255 + 1087 0048 14D9 bls .L92 +4340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1088 .loc 1 4340 0 + 1089 004a FF23 movs r3, #255 + 1090 004c 2385 strh r3, [r4, #40] + 1091 .L93: +4348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1092 .loc 1 4348 0 + 1093 004e 2268 ldr r2, [r4] + 1094 0050 2832 adds r2, r2, #40 + 1095 0052 238D ldrh r3, [r4, #40] + 1096 0054 A06B ldr r0, [r4, #56] + 1097 .LVL95: + 1098 0056 FFF7FEFF bl HAL_DMA_Start_IT + 1099 .LVL96: + 1100 .LBB152: + 1101 .LBB153: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 1102 .loc 1 4728 0 + 1103 005a 636B ldr r3, [r4, #52] + 1104 005c 0A4A ldr r2, .L101+4 + 1105 005e 9342 cmp r3, r2 + 1106 0060 0DD0 beq .L97 + 1107 0062 0A4A ldr r2, .L101+8 + 1108 0064 9342 cmp r3, r2 + 1109 0066 08D0 beq .L100 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1110 .loc 1 4778 0 + 1111 0068 F421 movs r1, #244 + 1112 .L94: + 1113 .LVL97: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1114 .loc 1 4785 0 + 1115 006a 2268 ldr r2, [r4] + 1116 006c 1368 ldr r3, [r2] + 1117 006e 0B43 orrs r3, r1 + 1118 0070 1360 str r3, [r2] + 1119 .LBE153: + 1120 .LBE152: + ARM GAS /tmp/ccpuPECZ.s page 108 + + +4353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1121 .loc 1 4353 0 + 1122 0072 DCE7 b .L88 + 1123 .LVL98: + 1124 .L92: +4344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1125 .loc 1 4344 0 + 1126 0074 638D ldrh r3, [r4, #42] + 1127 0076 2385 strh r3, [r4, #40] + 1128 0078 E9E7 b .L93 + 1129 .LVL99: + 1130 .L100: + 1131 .LBB155: + 1132 .LBB154: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1133 .loc 1 4752 0 + 1134 007a 6021 movs r1, #96 + 1135 007c F5E7 b .L94 + 1136 .L97: + 1137 007e 6021 movs r1, #96 + 1138 0080 F3E7 b .L94 + 1139 .L102: + 1140 0082 C046 .align 2 + 1141 .L101: + 1142 0084 FFBFFFFF .word -16385 + 1143 0088 00000000 .word I2C_Master_ISR_DMA + 1144 008c 00000000 .word I2C_Slave_ISR_DMA + 1145 .LBE154: + 1146 .LBE155: + 1147 .cfi_endproc + 1148 .LFE98: + 1150 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + 1151 .align 1 + 1152 .syntax unified + 1153 .code 16 + 1154 .thumb_func + 1155 .fpu softvfp + 1157 I2C_DMAMasterReceiveCplt: + 1158 .LFB100: +4376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 1159 .loc 1 4376 0 + 1160 .cfi_startproc + 1161 @ args = 0, pretend = 0, frame = 0 + 1162 @ frame_needed = 0, uses_anonymous_args = 0 + 1163 .LVL100: + 1164 0000 10B5 push {r4, lr} + 1165 .LCFI11: + 1166 .cfi_def_cfa_offset 8 + 1167 .cfi_offset 4, -8 + 1168 .cfi_offset 14, -4 +4377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1169 .loc 1 4377 0 + 1170 0002 846A ldr r4, [r0, #40] + 1171 .LVL101: +4380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1172 .loc 1 4380 0 + 1173 0004 2268 ldr r2, [r4] + ARM GAS /tmp/ccpuPECZ.s page 109 + + + 1174 0006 1368 ldr r3, [r2] + 1175 0008 1E49 ldr r1, .L116 + 1176 000a 0B40 ands r3, r1 + 1177 000c 1360 str r3, [r2] +4383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1178 .loc 1 4383 0 + 1179 000e 638D ldrh r3, [r4, #42] + 1180 0010 9BB2 uxth r3, r3 + 1181 0012 002B cmp r3, #0 + 1182 0014 10D1 bne .L104 + 1183 .LVL102: + 1184 .LBB156: + 1185 .LBB157: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 1186 .loc 1 4728 0 + 1187 0016 636B ldr r3, [r4, #52] + 1188 0018 1B4A ldr r2, .L116+4 + 1189 001a 9342 cmp r3, r2 + 1190 001c 0AD0 beq .L110 + 1191 001e 1B4A ldr r2, .L116+8 + 1192 0020 9342 cmp r3, r2 + 1193 0022 05D0 beq .L114 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1194 .loc 1 4778 0 + 1195 0024 F421 movs r1, #244 + 1196 .L105: + 1197 .LVL103: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1198 .loc 1 4785 0 + 1199 0026 2268 ldr r2, [r4] + 1200 0028 1368 ldr r3, [r2] + 1201 002a 0B43 orrs r3, r1 + 1202 002c 1360 str r3, [r2] + 1203 .LVL104: + 1204 .L103: + 1205 .LBE157: + 1206 .LBE156: +4410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1207 .loc 1 4410 0 + 1208 @ sp needed + 1209 .LVL105: + 1210 002e 10BD pop {r4, pc} + 1211 .LVL106: + 1212 .L114: + 1213 .LBB159: + 1214 .LBB158: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1215 .loc 1 4752 0 + 1216 0030 6021 movs r1, #96 + 1217 0032 F8E7 b .L105 + 1218 .L110: + 1219 0034 6021 movs r1, #96 + 1220 0036 F6E7 b .L105 + 1221 .LVL107: + 1222 .L104: + 1223 .LBE158: + 1224 .LBE159: + ARM GAS /tmp/ccpuPECZ.s page 110 + + +4392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1225 .loc 1 4392 0 + 1226 0038 228D ldrh r2, [r4, #40] + 1227 003a 636A ldr r3, [r4, #36] + 1228 003c 9C46 mov ip, r3 + 1229 003e 6244 add r2, r2, ip + 1230 0040 6262 str r2, [r4, #36] +4395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1231 .loc 1 4395 0 + 1232 0042 638D ldrh r3, [r4, #42] + 1233 0044 9BB2 uxth r3, r3 + 1234 0046 FF2B cmp r3, #255 + 1235 0048 14D9 bls .L107 +4397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1236 .loc 1 4397 0 + 1237 004a FF23 movs r3, #255 + 1238 004c 2385 strh r3, [r4, #40] + 1239 .L108: +4405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1240 .loc 1 4405 0 + 1241 004e 2168 ldr r1, [r4] + 1242 0050 2431 adds r1, r1, #36 + 1243 0052 238D ldrh r3, [r4, #40] + 1244 0054 E06B ldr r0, [r4, #60] + 1245 .LVL108: + 1246 0056 FFF7FEFF bl HAL_DMA_Start_IT + 1247 .LVL109: + 1248 .LBB160: + 1249 .LBB161: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 1250 .loc 1 4728 0 + 1251 005a 636B ldr r3, [r4, #52] + 1252 005c 0A4A ldr r2, .L116+4 + 1253 005e 9342 cmp r3, r2 + 1254 0060 0DD0 beq .L112 + 1255 0062 0A4A ldr r2, .L116+8 + 1256 0064 9342 cmp r3, r2 + 1257 0066 08D0 beq .L115 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1258 .loc 1 4778 0 + 1259 0068 F421 movs r1, #244 + 1260 .L109: + 1261 .LVL110: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1262 .loc 1 4785 0 + 1263 006a 2268 ldr r2, [r4] + 1264 006c 1368 ldr r3, [r2] + 1265 006e 0B43 orrs r3, r1 + 1266 0070 1360 str r3, [r2] + 1267 .LBE161: + 1268 .LBE160: +4410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1269 .loc 1 4410 0 + 1270 0072 DCE7 b .L103 + 1271 .LVL111: + 1272 .L107: +4401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 111 + + + 1273 .loc 1 4401 0 + 1274 0074 638D ldrh r3, [r4, #42] + 1275 0076 2385 strh r3, [r4, #40] + 1276 0078 E9E7 b .L108 + 1277 .LVL112: + 1278 .L115: + 1279 .LBB163: + 1280 .LBB162: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1281 .loc 1 4752 0 + 1282 007a 6021 movs r1, #96 + 1283 007c F5E7 b .L109 + 1284 .L112: + 1285 007e 6021 movs r1, #96 + 1286 0080 F3E7 b .L109 + 1287 .L117: + 1288 0082 C046 .align 2 + 1289 .L116: + 1290 0084 FF7FFFFF .word -32769 + 1291 0088 00000000 .word I2C_Master_ISR_DMA + 1292 008c 00000000 .word I2C_Slave_ISR_DMA + 1293 .LBE162: + 1294 .LBE163: + 1295 .cfi_endproc + 1296 .LFE100: + 1298 .section .text.HAL_I2C_MspInit,"ax",%progbits + 1299 .align 1 + 1300 .weak HAL_I2C_MspInit + 1301 .syntax unified + 1302 .code 16 + 1303 .thumb_func + 1304 .fpu softvfp + 1306 HAL_I2C_MspInit: + 1307 .LFB41: + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1308 .loc 1 529 0 + 1309 .cfi_startproc + 1310 @ args = 0, pretend = 0, frame = 0 + 1311 @ frame_needed = 0, uses_anonymous_args = 0 + 1312 @ link register save eliminated. + 1313 .LVL113: + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1314 .loc 1 536 0 + 1315 @ sp needed + 1316 0000 7047 bx lr + 1317 .cfi_endproc + 1318 .LFE41: + 1320 .section .text.HAL_I2C_Init,"ax",%progbits + 1321 .align 1 + 1322 .global HAL_I2C_Init + 1323 .syntax unified + 1324 .code 16 + 1325 .thumb_func + 1326 .fpu softvfp + 1328 HAL_I2C_Init: + 1329 .LFB39: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + ARM GAS /tmp/ccpuPECZ.s page 112 + + + 1330 .loc 1 406 0 + 1331 .cfi_startproc + 1332 @ args = 0, pretend = 0, frame = 0 + 1333 @ frame_needed = 0, uses_anonymous_args = 0 + 1334 .LVL114: + 1335 0000 10B5 push {r4, lr} + 1336 .LCFI12: + 1337 .cfi_def_cfa_offset 8 + 1338 .cfi_offset 4, -8 + 1339 .cfi_offset 14, -4 + 1340 0002 041E subs r4, r0, #0 + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1341 .loc 1 408 0 + 1342 0004 59D0 beq .L125 + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1343 .loc 1 423 0 + 1344 0006 4123 movs r3, #65 + 1345 0008 C35C ldrb r3, [r0, r3] + 1346 000a 002B cmp r3, #0 + 1347 000c 43D0 beq .L126 + 1348 .LVL115: + 1349 .L121: + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1350 .loc 1 432 0 + 1351 000e 4123 movs r3, #65 + 1352 0010 2422 movs r2, #36 + 1353 0012 E254 strb r2, [r4, r3] + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1354 .loc 1 435 0 + 1355 0014 2268 ldr r2, [r4] + 1356 0016 1368 ldr r3, [r2] + 1357 0018 0121 movs r1, #1 + 1358 001a 8B43 bics r3, r1 + 1359 001c 1360 str r3, [r2] + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1360 .loc 1 439 0 + 1361 001e 2268 ldr r2, [r4] + 1362 0020 274B ldr r3, .L129 + 1363 0022 6168 ldr r1, [r4, #4] + 1364 0024 0B40 ands r3, r1 + 1365 0026 1361 str r3, [r2, #16] + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1366 .loc 1 443 0 + 1367 0028 2268 ldr r2, [r4] + 1368 002a 9368 ldr r3, [r2, #8] + 1369 002c 2549 ldr r1, .L129+4 + 1370 002e 0B40 ands r3, r1 + 1371 0030 9360 str r3, [r2, #8] + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1372 .loc 1 446 0 + 1373 0032 E368 ldr r3, [r4, #12] + 1374 0034 012B cmp r3, #1 + 1375 0036 34D0 beq .L127 + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1376 .loc 1 452 0 + 1377 0038 2268 ldr r2, [r4] + 1378 003a 8423 movs r3, #132 + ARM GAS /tmp/ccpuPECZ.s page 113 + + + 1379 003c 1B02 lsls r3, r3, #8 + 1380 003e A168 ldr r1, [r4, #8] + 1381 0040 0B43 orrs r3, r1 + 1382 0042 9360 str r3, [r2, #8] + 1383 .L123: + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1384 .loc 1 457 0 + 1385 0044 E368 ldr r3, [r4, #12] + 1386 0046 022B cmp r3, #2 + 1387 0048 32D0 beq .L128 + 1388 .L124: + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1389 .loc 1 462 0 + 1390 004a 2268 ldr r2, [r4] + 1391 004c 5168 ldr r1, [r2, #4] + 1392 004e 1E4B ldr r3, .L129+8 + 1393 0050 0B43 orrs r3, r1 + 1394 0052 5360 str r3, [r2, #4] + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1395 .loc 1 466 0 + 1396 0054 2268 ldr r2, [r4] + 1397 0056 D368 ldr r3, [r2, #12] + 1398 0058 1A49 ldr r1, .L129+4 + 1399 005a 0B40 ands r3, r1 + 1400 005c D360 str r3, [r2, #12] + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1401 .loc 1 469 0 + 1402 005e 2369 ldr r3, [r4, #16] + 1403 0060 6269 ldr r2, [r4, #20] + 1404 0062 1343 orrs r3, r2 + 1405 0064 A269 ldr r2, [r4, #24] + 1406 0066 1202 lsls r2, r2, #8 + 1407 0068 2168 ldr r1, [r4] + 1408 006a 1343 orrs r3, r2 + 1409 006c CB60 str r3, [r1, #12] + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1410 .loc 1 473 0 + 1411 006e 2268 ldr r2, [r4] + 1412 0070 E369 ldr r3, [r4, #28] + 1413 0072 216A ldr r1, [r4, #32] + 1414 0074 0B43 orrs r3, r1 + 1415 0076 1360 str r3, [r2] + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1416 .loc 1 476 0 + 1417 0078 2268 ldr r2, [r4] + 1418 007a 1368 ldr r3, [r2] + 1419 007c 0121 movs r1, #1 + 1420 007e 0B43 orrs r3, r1 + 1421 0080 1360 str r3, [r2] + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1422 .loc 1 478 0 + 1423 0082 0023 movs r3, #0 + 1424 0084 6364 str r3, [r4, #68] + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1425 .loc 1 479 0 + 1426 0086 4122 movs r2, #65 + 1427 0088 1F31 adds r1, r1, #31 + ARM GAS /tmp/ccpuPECZ.s page 114 + + + 1428 008a A154 strb r1, [r4, r2] + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1429 .loc 1 480 0 + 1430 008c 2363 str r3, [r4, #48] + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1431 .loc 1 481 0 + 1432 008e 0132 adds r2, r2, #1 + 1433 0090 A354 strb r3, [r4, r2] + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1434 .loc 1 483 0 + 1435 0092 0020 movs r0, #0 + 1436 .L120: + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1437 .loc 1 484 0 + 1438 @ sp needed + 1439 .LVL116: + 1440 0094 10BD pop {r4, pc} + 1441 .LVL117: + 1442 .L126: + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1443 .loc 1 426 0 + 1444 0096 4033 adds r3, r3, #64 + 1445 0098 0022 movs r2, #0 + 1446 009a C254 strb r2, [r0, r3] + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1447 .loc 1 429 0 + 1448 009c FFF7FEFF bl HAL_I2C_MspInit + 1449 .LVL118: + 1450 00a0 B5E7 b .L121 + 1451 .L127: + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1452 .loc 1 448 0 + 1453 00a2 2268 ldr r2, [r4] + 1454 00a4 8023 movs r3, #128 + 1455 00a6 1B02 lsls r3, r3, #8 + 1456 00a8 A168 ldr r1, [r4, #8] + 1457 00aa 0B43 orrs r3, r1 + 1458 00ac 9360 str r3, [r2, #8] + 1459 00ae C9E7 b .L123 + 1460 .L128: + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1461 .loc 1 459 0 + 1462 00b0 2368 ldr r3, [r4] + 1463 00b2 8022 movs r2, #128 + 1464 00b4 1201 lsls r2, r2, #4 + 1465 00b6 5A60 str r2, [r3, #4] + 1466 00b8 C7E7 b .L124 + 1467 .LVL119: + 1468 .L125: + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1469 .loc 1 410 0 + 1470 00ba 0120 movs r0, #1 + 1471 .LVL120: + 1472 00bc EAE7 b .L120 + 1473 .L130: + 1474 00be C046 .align 2 + 1475 .L129: + ARM GAS /tmp/ccpuPECZ.s page 115 + + + 1476 00c0 FFFFFFF0 .word -251658241 + 1477 00c4 FF7FFFFF .word -32769 + 1478 00c8 00800002 .word 33587200 + 1479 .cfi_endproc + 1480 .LFE39: + 1482 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 1483 .align 1 + 1484 .weak HAL_I2C_MspDeInit + 1485 .syntax unified + 1486 .code 16 + 1487 .thumb_func + 1488 .fpu softvfp + 1490 HAL_I2C_MspDeInit: + 1491 .LFB42: + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1492 .loc 1 545 0 + 1493 .cfi_startproc + 1494 @ args = 0, pretend = 0, frame = 0 + 1495 @ frame_needed = 0, uses_anonymous_args = 0 + 1496 @ link register save eliminated. + 1497 .LVL121: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1498 .loc 1 552 0 + 1499 @ sp needed + 1500 0000 7047 bx lr + 1501 .cfi_endproc + 1502 .LFE42: + 1504 .section .text.HAL_I2C_DeInit,"ax",%progbits + 1505 .align 1 + 1506 .global HAL_I2C_DeInit + 1507 .syntax unified + 1508 .code 16 + 1509 .thumb_func + 1510 .fpu softvfp + 1512 HAL_I2C_DeInit: + 1513 .LFB40: + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1514 .loc 1 493 0 + 1515 .cfi_startproc + 1516 @ args = 0, pretend = 0, frame = 0 + 1517 @ frame_needed = 0, uses_anonymous_args = 0 + 1518 .LVL122: + 1519 0000 70B5 push {r4, r5, r6, lr} + 1520 .LCFI13: + 1521 .cfi_def_cfa_offset 16 + 1522 .cfi_offset 4, -16 + 1523 .cfi_offset 5, -12 + 1524 .cfi_offset 6, -8 + 1525 .cfi_offset 14, -4 + 1526 0002 041E subs r4, r0, #0 + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1527 .loc 1 495 0 + 1528 0004 13D0 beq .L134 + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1529 .loc 1 503 0 + 1530 0006 4125 movs r5, #65 + 1531 0008 2423 movs r3, #36 + ARM GAS /tmp/ccpuPECZ.s page 116 + + + 1532 000a 4355 strb r3, [r0, r5] + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1533 .loc 1 506 0 + 1534 000c 0268 ldr r2, [r0] + 1535 000e 1368 ldr r3, [r2] + 1536 0010 0121 movs r1, #1 + 1537 0012 8B43 bics r3, r1 + 1538 0014 1360 str r3, [r2] + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1539 .loc 1 509 0 + 1540 0016 FFF7FEFF bl HAL_I2C_MspDeInit + 1541 .LVL123: + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1542 .loc 1 511 0 + 1543 001a 0023 movs r3, #0 + 1544 001c 6364 str r3, [r4, #68] + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1545 .loc 1 512 0 + 1546 001e 6355 strb r3, [r4, r5] + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1547 .loc 1 513 0 + 1548 0020 2363 str r3, [r4, #48] + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1549 .loc 1 514 0 + 1550 0022 4222 movs r2, #66 + 1551 0024 A354 strb r3, [r4, r2] + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1552 .loc 1 517 0 + 1553 0026 023A subs r2, r2, #2 + 1554 0028 A354 strb r3, [r4, r2] + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1555 .loc 1 519 0 + 1556 002a 0020 movs r0, #0 + 1557 .L133: + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1558 .loc 1 520 0 + 1559 @ sp needed + 1560 .LVL124: + 1561 002c 70BD pop {r4, r5, r6, pc} + 1562 .LVL125: + 1563 .L134: + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1564 .loc 1 497 0 + 1565 002e 0120 movs r0, #1 + 1566 .LVL126: + 1567 0030 FCE7 b .L133 + 1568 .cfi_endproc + 1569 .LFE40: + 1571 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 1572 .align 1 + 1573 .global HAL_I2C_Master_Transmit + 1574 .syntax unified + 1575 .code 16 + 1576 .thumb_func + 1577 .fpu softvfp + 1579 HAL_I2C_Master_Transmit: + 1580 .LFB43: + ARM GAS /tmp/ccpuPECZ.s page 117 + + + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 1581 .loc 1 629 0 + 1582 .cfi_startproc + 1583 @ args = 4, pretend = 0, frame = 8 + 1584 @ frame_needed = 0, uses_anonymous_args = 0 + 1585 .LVL127: + 1586 0000 F0B5 push {r4, r5, r6, r7, lr} + 1587 .LCFI14: + 1588 .cfi_def_cfa_offset 20 + 1589 .cfi_offset 4, -20 + 1590 .cfi_offset 5, -16 + 1591 .cfi_offset 6, -12 + 1592 .cfi_offset 7, -8 + 1593 .cfi_offset 14, -4 + 1594 0002 85B0 sub sp, sp, #20 + 1595 .LCFI15: + 1596 .cfi_def_cfa_offset 40 + 1597 0004 0400 movs r4, r0 + 1598 0006 0D00 movs r5, r1 + 1599 0008 1700 movs r7, r2 + 1600 000a 0393 str r3, [sp, #12] + 1601 .LVL128: + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1602 .loc 1 632 0 + 1603 000c 4123 movs r3, #65 + 1604 .LVL129: + 1605 000e C35C ldrb r3, [r0, r3] + 1606 0010 202B cmp r3, #32 + 1607 0012 00D0 beq .LCB1634 + 1608 0014 BDE0 b .L147 @long jump + 1609 .LCB1634: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1610 .loc 1 635 0 + 1611 0016 2033 adds r3, r3, #32 + 1612 0018 C35C ldrb r3, [r0, r3] + 1613 001a 012B cmp r3, #1 + 1614 001c 00D1 bne .LCB1638 + 1615 001e BBE0 b .L148 @long jump + 1616 .LCB1638: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1617 .loc 1 635 0 is_stmt 0 discriminator 2 + 1618 0020 4023 movs r3, #64 + 1619 0022 0122 movs r2, #1 + 1620 .LVL130: + 1621 0024 C254 strb r2, [r0, r3] + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1622 .loc 1 638 0 is_stmt 1 discriminator 2 + 1623 0026 FFF7FEFF bl HAL_GetTick + 1624 .LVL131: + 1625 002a 0600 movs r6, r0 + 1626 .LVL132: + 1627 .L137: + 1628 .LBB164: + 1629 .LBB165: +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1630 .loc 1 4487 0 + 1631 002c 2368 ldr r3, [r4] + ARM GAS /tmp/ccpuPECZ.s page 118 + + + 1632 002e 9A69 ldr r2, [r3, #24] + 1633 0030 1204 lsls r2, r2, #16 + 1634 0032 0ED5 bpl .L152 +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1635 .loc 1 4492 0 + 1636 0034 FFF7FEFF bl HAL_GetTick + 1637 .LVL133: + 1638 0038 801B subs r0, r0, r6 + 1639 003a 1928 cmp r0, #25 + 1640 003c F6D9 bls .L137 +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1641 .loc 1 4494 0 + 1642 003e 4123 movs r3, #65 + 1643 0040 2022 movs r2, #32 + 1644 0042 E254 strb r2, [r4, r3] +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1645 .loc 1 4495 0 + 1646 0044 0023 movs r3, #0 + 1647 0046 2232 adds r2, r2, #34 + 1648 0048 A354 strb r3, [r4, r2] +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 1649 .loc 1 4498 0 + 1650 004a 023A subs r2, r2, #2 + 1651 004c A354 strb r3, [r4, r2] + 1652 .LVL134: + 1653 .LBE165: + 1654 .LBE164: + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1655 .loc 1 642 0 + 1656 004e 0320 movs r0, #3 + 1657 0050 A0E0 b .L136 + 1658 .LVL135: + 1659 .L152: + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1660 .loc 1 645 0 + 1661 0052 4122 movs r2, #65 + 1662 0054 2121 movs r1, #33 + 1663 0056 A154 strb r1, [r4, r2] + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1664 .loc 1 646 0 + 1665 0058 0132 adds r2, r2, #1 + 1666 005a 1139 subs r1, r1, #17 + 1667 005c A154 strb r1, [r4, r2] + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1668 .loc 1 647 0 + 1669 005e 0022 movs r2, #0 + 1670 0060 6264 str r2, [r4, #68] + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 1671 .loc 1 650 0 + 1672 0062 6762 str r7, [r4, #36] + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1673 .loc 1 651 0 + 1674 0064 6946 mov r1, sp + 1675 0066 8989 ldrh r1, [r1, #12] + 1676 0068 6185 strh r1, [r4, #42] + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1677 .loc 1 652 0 + ARM GAS /tmp/ccpuPECZ.s page 119 + + + 1678 006a 6263 str r2, [r4, #52] + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1679 .loc 1 656 0 + 1680 006c 628D ldrh r2, [r4, #42] + 1681 006e 92B2 uxth r2, r2 + 1682 0070 FF2A cmp r2, #255 + 1683 0072 0ED9 bls .L139 + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRIT + 1684 .loc 1 658 0 + 1685 0074 FF22 movs r2, #255 + 1686 0076 2285 strh r2, [r4, #40] + 1687 .LVL136: + 1688 .LBB166: + 1689 .LBB167: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 1690 .loc 1 4713 0 + 1691 0078 5A68 ldr r2, [r3, #4] + 1692 007a 4B49 ldr r1, .L155 + 1693 007c 0A40 ands r2, r1 + 1694 007e A805 lsls r0, r5, #22 + 1695 0080 800D lsrs r0, r0, #22 + 1696 0082 FF21 movs r1, #255 + 1697 0084 0904 lsls r1, r1, #16 + 1698 0086 0843 orrs r0, r1 + 1699 0088 4849 ldr r1, .L155+4 + 1700 008a 0143 orrs r1, r0 + 1701 008c 0A43 orrs r2, r1 + 1702 008e 5A60 str r2, [r3, #4] + 1703 0090 26E0 b .L144 + 1704 .LVL137: + 1705 .L139: + 1706 .LBE167: + 1707 .LBE166: + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRI + 1708 .loc 1 663 0 + 1709 0092 628D ldrh r2, [r4, #42] + 1710 0094 92B2 uxth r2, r2 + 1711 0096 2285 strh r2, [r4, #40] + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1712 .loc 1 664 0 + 1713 0098 D2B2 uxtb r2, r2 + 1714 .LVL138: + 1715 .LBB168: + 1716 .LBB169: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 1717 .loc 1 4713 0 + 1718 009a 5968 ldr r1, [r3, #4] + 1719 009c 4248 ldr r0, .L155 + 1720 009e 0140 ands r1, r0 + 1721 00a0 A805 lsls r0, r5, #22 + 1722 00a2 800D lsrs r0, r0, #22 + 1723 00a4 1204 lsls r2, r2, #16 + 1724 .LVL139: + 1725 00a6 0243 orrs r2, r0 + 1726 00a8 4148 ldr r0, .L155+8 + 1727 00aa 0243 orrs r2, r0 + 1728 00ac 0A43 orrs r2, r1 + ARM GAS /tmp/ccpuPECZ.s page 120 + + + 1729 00ae 5A60 str r2, [r3, #4] + 1730 .LVL140: + 1731 00b0 16E0 b .L144 + 1732 .LVL141: + 1733 .L154: + 1734 .LBE169: + 1735 .LBE168: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1736 .loc 1 672 0 + 1737 00b2 636C ldr r3, [r4, #68] + 1738 00b4 042B cmp r3, #4 + 1739 00b6 00D0 beq .LCB1796 + 1740 00b8 70E0 b .L149 @long jump + 1741 .LCB1796: + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1742 .loc 1 674 0 + 1743 00ba 0120 movs r0, #1 + 1744 00bc 6AE0 b .L136 + 1745 .L143: + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 1746 .loc 1 701 0 + 1747 00be 638D ldrh r3, [r4, #42] + 1748 00c0 9BB2 uxth r3, r3 + 1749 00c2 2385 strh r3, [r4, #40] + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1750 .loc 1 702 0 + 1751 00c4 DBB2 uxtb r3, r3 + 1752 .LVL142: + 1753 .LBB170: + 1754 .LBB171: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 1755 .loc 1 4713 0 + 1756 00c6 2068 ldr r0, [r4] + 1757 00c8 4268 ldr r2, [r0, #4] + 1758 00ca 3A49 ldr r1, .L155+12 + 1759 00cc 0A40 ands r2, r1 + 1760 00ce A905 lsls r1, r5, #22 + 1761 00d0 890D lsrs r1, r1, #22 + 1762 00d2 1B04 lsls r3, r3, #16 + 1763 .LVL143: + 1764 00d4 0B43 orrs r3, r1 + 1765 00d6 8021 movs r1, #128 + 1766 00d8 8904 lsls r1, r1, #18 + 1767 00da 0B43 orrs r3, r1 + 1768 00dc 1343 orrs r3, r2 + 1769 00de 4360 str r3, [r0, #4] + 1770 .LVL144: + 1771 .L144: + 1772 .LBE171: + 1773 .LBE170: + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1774 .loc 1 667 0 + 1775 00e0 638D ldrh r3, [r4, #42] + 1776 00e2 9BB2 uxth r3, r3 + 1777 00e4 002B cmp r3, #0 + 1778 00e6 38D0 beq .L153 + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 121 + + + 1779 .loc 1 670 0 + 1780 00e8 3200 movs r2, r6 + 1781 00ea 0A99 ldr r1, [sp, #40] + 1782 00ec 2000 movs r0, r4 + 1783 00ee FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1784 .LVL145: + 1785 00f2 0028 cmp r0, #0 + 1786 00f4 DDD1 bne .L154 + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 1787 .loc 1 682 0 + 1788 00f6 636A ldr r3, [r4, #36] + 1789 00f8 5A1C adds r2, r3, #1 + 1790 00fa 6262 str r2, [r4, #36] + 1791 00fc 2268 ldr r2, [r4] + 1792 00fe 1B78 ldrb r3, [r3] + 1793 0100 9362 str r3, [r2, #40] + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 1794 .loc 1 683 0 + 1795 0102 638D ldrh r3, [r4, #42] + 1796 0104 013B subs r3, r3, #1 + 1797 0106 9BB2 uxth r3, r3 + 1798 0108 6385 strh r3, [r4, #42] + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1799 .loc 1 684 0 + 1800 010a 238D ldrh r3, [r4, #40] + 1801 010c 013B subs r3, r3, #1 + 1802 010e 9BB2 uxth r3, r3 + 1803 0110 2385 strh r3, [r4, #40] + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1804 .loc 1 686 0 + 1805 0112 002B cmp r3, #0 + 1806 0114 E4D1 bne .L144 + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1807 .loc 1 686 0 is_stmt 0 discriminator 1 + 1808 0116 638D ldrh r3, [r4, #42] + 1809 0118 9BB2 uxth r3, r3 + 1810 011a 002B cmp r3, #0 + 1811 011c E0D0 beq .L144 + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1812 .loc 1 689 0 is_stmt 1 + 1813 011e 0096 str r6, [sp] + 1814 0120 0A9B ldr r3, [sp, #40] + 1815 0122 0022 movs r2, #0 + 1816 0124 8021 movs r1, #128 + 1817 0126 2000 movs r0, r4 + 1818 0128 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1819 .LVL146: + 1820 012c 0028 cmp r0, #0 + 1821 012e 37D1 bne .L150 + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1822 .loc 1 694 0 + 1823 0130 638D ldrh r3, [r4, #42] + 1824 0132 9BB2 uxth r3, r3 + 1825 0134 FF2B cmp r3, #255 + 1826 0136 C2D9 bls .L143 + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 1827 .loc 1 696 0 + ARM GAS /tmp/ccpuPECZ.s page 122 + + + 1828 0138 FF23 movs r3, #255 + 1829 013a 2385 strh r3, [r4, #40] + 1830 .LVL147: + 1831 .LBB172: + 1832 .LBB173: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 1833 .loc 1 4713 0 + 1834 013c 2068 ldr r0, [r4] + 1835 013e 4368 ldr r3, [r0, #4] + 1836 0140 1C4A ldr r2, .L155+12 + 1837 0142 1340 ands r3, r2 + 1838 0144 A905 lsls r1, r5, #22 + 1839 0146 890D lsrs r1, r1, #22 + 1840 0148 FF22 movs r2, #255 + 1841 014a 1204 lsls r2, r2, #16 + 1842 014c 1143 orrs r1, r2 + 1843 014e 8022 movs r2, #128 + 1844 0150 5204 lsls r2, r2, #17 + 1845 0152 0A43 orrs r2, r1 + 1846 0154 1343 orrs r3, r2 + 1847 0156 4360 str r3, [r0, #4] + 1848 0158 C2E7 b .L144 + 1849 .LVL148: + 1850 .L153: + 1851 .LBE173: + 1852 .LBE172: + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1853 .loc 1 709 0 + 1854 015a 3200 movs r2, r6 + 1855 015c 0A99 ldr r1, [sp, #40] + 1856 015e 2000 movs r0, r4 + 1857 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1858 .LVL149: + 1859 0164 0028 cmp r0, #0 + 1860 0166 04D0 beq .L146 + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1861 .loc 1 711 0 + 1862 0168 636C ldr r3, [r4, #68] + 1863 016a 042B cmp r3, #4 + 1864 016c 1AD1 bne .L151 + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1865 .loc 1 713 0 + 1866 016e 0120 movs r0, #1 + 1867 0170 10E0 b .L136 + 1868 .L146: + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1869 .loc 1 722 0 + 1870 0172 2368 ldr r3, [r4] + 1871 0174 2022 movs r2, #32 + 1872 0176 DA61 str r2, [r3, #28] + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1873 .loc 1 725 0 + 1874 0178 2168 ldr r1, [r4] + 1875 017a 4B68 ldr r3, [r1, #4] + 1876 017c 0E4D ldr r5, .L155+16 + 1877 017e 2B40 ands r3, r5 + 1878 0180 4B60 str r3, [r1, #4] + ARM GAS /tmp/ccpuPECZ.s page 123 + + + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1879 .loc 1 727 0 + 1880 0182 4123 movs r3, #65 + 1881 0184 E254 strb r2, [r4, r3] + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1882 .loc 1 728 0 + 1883 0186 0023 movs r3, #0 + 1884 0188 2232 adds r2, r2, #34 + 1885 018a A354 strb r3, [r4, r2] + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1886 .loc 1 731 0 + 1887 018c 023A subs r2, r2, #2 + 1888 018e A354 strb r3, [r4, r2] + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1889 .loc 1 733 0 + 1890 0190 00E0 b .L136 + 1891 .LVL150: + 1892 .L147: + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1893 .loc 1 737 0 + 1894 0192 0220 movs r0, #2 + 1895 .LVL151: + 1896 .L136: + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1897 .loc 1 739 0 + 1898 0194 05B0 add sp, sp, #20 + 1899 @ sp needed + 1900 .LVL152: + 1901 .LVL153: + 1902 0196 F0BD pop {r4, r5, r6, r7, pc} + 1903 .LVL154: + 1904 .L148: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1905 .loc 1 635 0 + 1906 0198 0220 movs r0, #2 + 1907 .LVL155: + 1908 019a FBE7 b .L136 + 1909 .LVL156: + 1910 .L149: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1911 .loc 1 678 0 + 1912 019c 0320 movs r0, #3 + 1913 019e F9E7 b .L136 + 1914 .L150: + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1915 .loc 1 691 0 + 1916 01a0 0320 movs r0, #3 + 1917 01a2 F7E7 b .L136 + 1918 .L151: + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 1919 .loc 1 717 0 + 1920 01a4 0320 movs r0, #3 + 1921 01a6 F5E7 b .L136 + 1922 .L156: + 1923 .align 2 + 1924 .L155: + 1925 01a8 009800FC .word -67069952 + ARM GAS /tmp/ccpuPECZ.s page 124 + + + 1926 01ac 00200081 .word -2130698240 + 1927 01b0 00200082 .word -2113921024 + 1928 01b4 009C00FC .word -67068928 + 1929 01b8 00E800FE .word -33495040 + 1930 .cfi_endproc + 1931 .LFE43: + 1933 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 1934 .align 1 + 1935 .global HAL_I2C_Master_Receive + 1936 .syntax unified + 1937 .code 16 + 1938 .thumb_func + 1939 .fpu softvfp + 1941 HAL_I2C_Master_Receive: + 1942 .LFB44: + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 1943 .loc 1 753 0 + 1944 .cfi_startproc + 1945 @ args = 4, pretend = 0, frame = 8 + 1946 @ frame_needed = 0, uses_anonymous_args = 0 + 1947 .LVL157: + 1948 0000 F0B5 push {r4, r5, r6, r7, lr} + 1949 .LCFI16: + 1950 .cfi_def_cfa_offset 20 + 1951 .cfi_offset 4, -20 + 1952 .cfi_offset 5, -16 + 1953 .cfi_offset 6, -12 + 1954 .cfi_offset 7, -8 + 1955 .cfi_offset 14, -4 + 1956 0002 85B0 sub sp, sp, #20 + 1957 .LCFI17: + 1958 .cfi_def_cfa_offset 40 + 1959 0004 0400 movs r4, r0 + 1960 0006 0D00 movs r5, r1 + 1961 0008 1700 movs r7, r2 + 1962 000a 0393 str r3, [sp, #12] + 1963 .LVL158: + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1964 .loc 1 756 0 + 1965 000c 4123 movs r3, #65 + 1966 .LVL159: + 1967 000e C35C ldrb r3, [r0, r3] + 1968 0010 202B cmp r3, #32 + 1969 0012 00D0 beq .LCB2059 + 1970 0014 BDE0 b .L169 @long jump + 1971 .LCB2059: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1972 .loc 1 759 0 + 1973 0016 2033 adds r3, r3, #32 + 1974 0018 C35C ldrb r3, [r0, r3] + 1975 001a 012B cmp r3, #1 + 1976 001c 00D1 bne .LCB2063 + 1977 001e BBE0 b .L170 @long jump + 1978 .LCB2063: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1979 .loc 1 759 0 is_stmt 0 discriminator 2 + 1980 0020 4023 movs r3, #64 + ARM GAS /tmp/ccpuPECZ.s page 125 + + + 1981 0022 0122 movs r2, #1 + 1982 .LVL160: + 1983 0024 C254 strb r2, [r0, r3] + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 1984 .loc 1 762 0 is_stmt 1 discriminator 2 + 1985 0026 FFF7FEFF bl HAL_GetTick + 1986 .LVL161: + 1987 002a 0600 movs r6, r0 + 1988 .LVL162: + 1989 .L159: + 1990 .LBB174: + 1991 .LBB175: +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1992 .loc 1 4487 0 + 1993 002c 2368 ldr r3, [r4] + 1994 002e 9A69 ldr r2, [r3, #24] + 1995 0030 1204 lsls r2, r2, #16 + 1996 0032 0ED5 bpl .L174 +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 1997 .loc 1 4492 0 + 1998 0034 FFF7FEFF bl HAL_GetTick + 1999 .LVL163: + 2000 0038 801B subs r0, r0, r6 + 2001 003a 1928 cmp r0, #25 + 2002 003c F6D9 bls .L159 +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2003 .loc 1 4494 0 + 2004 003e 4123 movs r3, #65 + 2005 0040 2022 movs r2, #32 + 2006 0042 E254 strb r2, [r4, r3] +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2007 .loc 1 4495 0 + 2008 0044 0023 movs r3, #0 + 2009 0046 2232 adds r2, r2, #34 + 2010 0048 A354 strb r3, [r4, r2] +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2011 .loc 1 4498 0 + 2012 004a 023A subs r2, r2, #2 + 2013 004c A354 strb r3, [r4, r2] + 2014 .LVL164: + 2015 .LBE175: + 2016 .LBE174: + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2017 .loc 1 766 0 + 2018 004e 0320 movs r0, #3 + 2019 0050 A0E0 b .L158 + 2020 .LVL165: + 2021 .L174: + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2022 .loc 1 769 0 + 2023 0052 4122 movs r2, #65 + 2024 0054 2221 movs r1, #34 + 2025 0056 A154 strb r1, [r4, r2] + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2026 .loc 1 770 0 + 2027 0058 0132 adds r2, r2, #1 + 2028 005a 1239 subs r1, r1, #18 + ARM GAS /tmp/ccpuPECZ.s page 126 + + + 2029 005c A154 strb r1, [r4, r2] + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2030 .loc 1 771 0 + 2031 005e 0022 movs r2, #0 + 2032 0060 6264 str r2, [r4, #68] + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2033 .loc 1 774 0 + 2034 0062 6762 str r7, [r4, #36] + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2035 .loc 1 775 0 + 2036 0064 6946 mov r1, sp + 2037 0066 8989 ldrh r1, [r1, #12] + 2038 0068 6185 strh r1, [r4, #42] + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2039 .loc 1 776 0 + 2040 006a 6263 str r2, [r4, #52] + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2041 .loc 1 780 0 + 2042 006c 628D ldrh r2, [r4, #42] + 2043 006e 92B2 uxth r2, r2 + 2044 0070 FF2A cmp r2, #255 + 2045 0072 0ED9 bls .L161 + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ + 2046 .loc 1 782 0 + 2047 0074 FF22 movs r2, #255 + 2048 0076 2285 strh r2, [r4, #40] + 2049 .LVL166: + 2050 .LBB176: + 2051 .LBB177: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 2052 .loc 1 4713 0 + 2053 0078 5A68 ldr r2, [r3, #4] + 2054 007a 4B49 ldr r1, .L177 + 2055 007c 0A40 ands r2, r1 + 2056 007e A805 lsls r0, r5, #22 + 2057 0080 800D lsrs r0, r0, #22 + 2058 0082 FF21 movs r1, #255 + 2059 0084 0904 lsls r1, r1, #16 + 2060 0086 0843 orrs r0, r1 + 2061 0088 4849 ldr r1, .L177+4 + 2062 008a 0143 orrs r1, r0 + 2063 008c 0A43 orrs r2, r1 + 2064 008e 5A60 str r2, [r3, #4] + 2065 0090 26E0 b .L166 + 2066 .LVL167: + 2067 .L161: + 2068 .LBE177: + 2069 .LBE176: + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_REA + 2070 .loc 1 787 0 + 2071 0092 628D ldrh r2, [r4, #42] + 2072 0094 92B2 uxth r2, r2 + 2073 0096 2285 strh r2, [r4, #40] + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2074 .loc 1 788 0 + 2075 0098 D2B2 uxtb r2, r2 + 2076 .LVL168: + ARM GAS /tmp/ccpuPECZ.s page 127 + + + 2077 .LBB178: + 2078 .LBB179: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 2079 .loc 1 4713 0 + 2080 009a 5968 ldr r1, [r3, #4] + 2081 009c 4248 ldr r0, .L177 + 2082 009e 0140 ands r1, r0 + 2083 00a0 A805 lsls r0, r5, #22 + 2084 00a2 800D lsrs r0, r0, #22 + 2085 00a4 1204 lsls r2, r2, #16 + 2086 .LVL169: + 2087 00a6 0243 orrs r2, r0 + 2088 00a8 4148 ldr r0, .L177+8 + 2089 00aa 0243 orrs r2, r0 + 2090 00ac 0A43 orrs r2, r1 + 2091 00ae 5A60 str r2, [r3, #4] + 2092 .LVL170: + 2093 00b0 16E0 b .L166 + 2094 .LVL171: + 2095 .L176: + 2096 .LBE179: + 2097 .LBE178: + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2098 .loc 1 796 0 + 2099 00b2 636C ldr r3, [r4, #68] + 2100 00b4 042B cmp r3, #4 + 2101 00b6 00D0 beq .LCB2221 + 2102 00b8 70E0 b .L171 @long jump + 2103 .LCB2221: + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2104 .loc 1 798 0 + 2105 00ba 0120 movs r0, #1 + 2106 00bc 6AE0 b .L158 + 2107 .L165: + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 2108 .loc 1 826 0 + 2109 00be 638D ldrh r3, [r4, #42] + 2110 00c0 9BB2 uxth r3, r3 + 2111 00c2 2385 strh r3, [r4, #40] + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2112 .loc 1 827 0 + 2113 00c4 DBB2 uxtb r3, r3 + 2114 .LVL172: + 2115 .LBB180: + 2116 .LBB181: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 2117 .loc 1 4713 0 + 2118 00c6 2068 ldr r0, [r4] + 2119 00c8 4268 ldr r2, [r0, #4] + 2120 00ca 3A49 ldr r1, .L177+12 + 2121 00cc 0A40 ands r2, r1 + 2122 00ce A905 lsls r1, r5, #22 + 2123 00d0 890D lsrs r1, r1, #22 + 2124 00d2 1B04 lsls r3, r3, #16 + 2125 .LVL173: + 2126 00d4 0B43 orrs r3, r1 + 2127 00d6 8021 movs r1, #128 + ARM GAS /tmp/ccpuPECZ.s page 128 + + + 2128 00d8 8904 lsls r1, r1, #18 + 2129 00da 0B43 orrs r3, r1 + 2130 00dc 1343 orrs r3, r2 + 2131 00de 4360 str r3, [r0, #4] + 2132 .LVL174: + 2133 .L166: + 2134 .LBE181: + 2135 .LBE180: + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2136 .loc 1 791 0 + 2137 00e0 638D ldrh r3, [r4, #42] + 2138 00e2 9BB2 uxth r3, r3 + 2139 00e4 002B cmp r3, #0 + 2140 00e6 38D0 beq .L175 + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2141 .loc 1 794 0 + 2142 00e8 3200 movs r2, r6 + 2143 00ea 0A99 ldr r1, [sp, #40] + 2144 00ec 2000 movs r0, r4 + 2145 00ee FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2146 .LVL175: + 2147 00f2 0028 cmp r0, #0 + 2148 00f4 DDD1 bne .L176 + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 2149 .loc 1 807 0 + 2150 00f6 2368 ldr r3, [r4] + 2151 00f8 5A6A ldr r2, [r3, #36] + 2152 00fa 636A ldr r3, [r4, #36] + 2153 00fc 591C adds r1, r3, #1 + 2154 00fe 6162 str r1, [r4, #36] + 2155 0100 1A70 strb r2, [r3] + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 2156 .loc 1 808 0 + 2157 0102 238D ldrh r3, [r4, #40] + 2158 0104 013B subs r3, r3, #1 + 2159 0106 9BB2 uxth r3, r3 + 2160 0108 2385 strh r3, [r4, #40] + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2161 .loc 1 809 0 + 2162 010a 628D ldrh r2, [r4, #42] + 2163 010c 013A subs r2, r2, #1 + 2164 010e 92B2 uxth r2, r2 + 2165 0110 6285 strh r2, [r4, #42] + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2166 .loc 1 811 0 + 2167 0112 002B cmp r3, #0 + 2168 0114 E4D1 bne .L166 + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2169 .loc 1 811 0 is_stmt 0 discriminator 1 + 2170 0116 638D ldrh r3, [r4, #42] + 2171 0118 9BB2 uxth r3, r3 + 2172 011a 002B cmp r3, #0 + 2173 011c E0D0 beq .L166 + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2174 .loc 1 814 0 is_stmt 1 + 2175 011e 0096 str r6, [sp] + 2176 0120 0A9B ldr r3, [sp, #40] + ARM GAS /tmp/ccpuPECZ.s page 129 + + + 2177 0122 0022 movs r2, #0 + 2178 0124 8021 movs r1, #128 + 2179 0126 2000 movs r0, r4 + 2180 0128 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2181 .LVL176: + 2182 012c 0028 cmp r0, #0 + 2183 012e 37D1 bne .L172 + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2184 .loc 1 819 0 + 2185 0130 638D ldrh r3, [r4, #42] + 2186 0132 9BB2 uxth r3, r3 + 2187 0134 FF2B cmp r3, #255 + 2188 0136 C2D9 bls .L165 + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 2189 .loc 1 821 0 + 2190 0138 FF23 movs r3, #255 + 2191 013a 2385 strh r3, [r4, #40] + 2192 .LVL177: + 2193 .LBB182: + 2194 .LBB183: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 2195 .loc 1 4713 0 + 2196 013c 2068 ldr r0, [r4] + 2197 013e 4368 ldr r3, [r0, #4] + 2198 0140 1C4A ldr r2, .L177+12 + 2199 0142 1340 ands r3, r2 + 2200 0144 A905 lsls r1, r5, #22 + 2201 0146 890D lsrs r1, r1, #22 + 2202 0148 FF22 movs r2, #255 + 2203 014a 1204 lsls r2, r2, #16 + 2204 014c 1143 orrs r1, r2 + 2205 014e 8022 movs r2, #128 + 2206 0150 5204 lsls r2, r2, #17 + 2207 0152 0A43 orrs r2, r1 + 2208 0154 1343 orrs r3, r2 + 2209 0156 4360 str r3, [r0, #4] + 2210 0158 C2E7 b .L166 + 2211 .LVL178: + 2212 .L175: + 2213 .LBE183: + 2214 .LBE182: + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2215 .loc 1 834 0 + 2216 015a 3200 movs r2, r6 + 2217 015c 0A99 ldr r1, [sp, #40] + 2218 015e 2000 movs r0, r4 + 2219 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2220 .LVL179: + 2221 0164 0028 cmp r0, #0 + 2222 0166 04D0 beq .L168 + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2223 .loc 1 836 0 + 2224 0168 636C ldr r3, [r4, #68] + 2225 016a 042B cmp r3, #4 + 2226 016c 1AD1 bne .L173 + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2227 .loc 1 838 0 + ARM GAS /tmp/ccpuPECZ.s page 130 + + + 2228 016e 0120 movs r0, #1 + 2229 0170 10E0 b .L158 + 2230 .L168: + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2231 .loc 1 847 0 + 2232 0172 2368 ldr r3, [r4] + 2233 0174 2022 movs r2, #32 + 2234 0176 DA61 str r2, [r3, #28] + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2235 .loc 1 850 0 + 2236 0178 2168 ldr r1, [r4] + 2237 017a 4B68 ldr r3, [r1, #4] + 2238 017c 0E4D ldr r5, .L177+16 + 2239 017e 2B40 ands r3, r5 + 2240 0180 4B60 str r3, [r1, #4] + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2241 .loc 1 852 0 + 2242 0182 4123 movs r3, #65 + 2243 0184 E254 strb r2, [r4, r3] + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2244 .loc 1 853 0 + 2245 0186 0023 movs r3, #0 + 2246 0188 2232 adds r2, r2, #34 + 2247 018a A354 strb r3, [r4, r2] + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2248 .loc 1 856 0 + 2249 018c 023A subs r2, r2, #2 + 2250 018e A354 strb r3, [r4, r2] + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2251 .loc 1 858 0 + 2252 0190 00E0 b .L158 + 2253 .LVL180: + 2254 .L169: + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2255 .loc 1 862 0 + 2256 0192 0220 movs r0, #2 + 2257 .LVL181: + 2258 .L158: + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2259 .loc 1 864 0 + 2260 0194 05B0 add sp, sp, #20 + 2261 @ sp needed + 2262 .LVL182: + 2263 .LVL183: + 2264 0196 F0BD pop {r4, r5, r6, r7, pc} + 2265 .LVL184: + 2266 .L170: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2267 .loc 1 759 0 + 2268 0198 0220 movs r0, #2 + 2269 .LVL185: + 2270 019a FBE7 b .L158 + 2271 .LVL186: + 2272 .L171: + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2273 .loc 1 802 0 + 2274 019c 0320 movs r0, #3 + ARM GAS /tmp/ccpuPECZ.s page 131 + + + 2275 019e F9E7 b .L158 + 2276 .L172: + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2277 .loc 1 816 0 + 2278 01a0 0320 movs r0, #3 + 2279 01a2 F7E7 b .L158 + 2280 .L173: + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2281 .loc 1 842 0 + 2282 01a4 0320 movs r0, #3 + 2283 01a6 F5E7 b .L158 + 2284 .L178: + 2285 .align 2 + 2286 .L177: + 2287 01a8 009800FC .word -67069952 + 2288 01ac 00240081 .word -2130697216 + 2289 01b0 00240082 .word -2113920000 + 2290 01b4 009C00FC .word -67068928 + 2291 01b8 00E800FE .word -33495040 + 2292 .cfi_endproc + 2293 .LFE44: + 2295 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 2296 .align 1 + 2297 .global HAL_I2C_Slave_Transmit + 2298 .syntax unified + 2299 .code 16 + 2300 .thumb_func + 2301 .fpu softvfp + 2303 HAL_I2C_Slave_Transmit: + 2304 .LFB45: + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 2305 .loc 1 876 0 + 2306 .cfi_startproc + 2307 @ args = 0, pretend = 0, frame = 8 + 2308 @ frame_needed = 0, uses_anonymous_args = 0 + 2309 .LVL187: + 2310 0000 F0B5 push {r4, r5, r6, r7, lr} + 2311 .LCFI18: + 2312 .cfi_def_cfa_offset 20 + 2313 .cfi_offset 4, -20 + 2314 .cfi_offset 5, -16 + 2315 .cfi_offset 6, -12 + 2316 .cfi_offset 7, -8 + 2317 .cfi_offset 14, -4 + 2318 0002 85B0 sub sp, sp, #20 + 2319 .LCFI19: + 2320 .cfi_def_cfa_offset 40 + 2321 0004 0400 movs r4, r0 + 2322 0006 0D00 movs r5, r1 + 2323 0008 1600 movs r6, r2 + 2324 000a 0393 str r3, [sp, #12] + 2325 .LVL188: + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2326 .loc 1 879 0 + 2327 000c 4123 movs r3, #65 + 2328 .LVL189: + 2329 000e C35C ldrb r3, [r0, r3] + ARM GAS /tmp/ccpuPECZ.s page 132 + + + 2330 0010 202B cmp r3, #32 + 2331 0012 00D0 beq .LCB2483 + 2332 0014 B5E0 b .L189 @long jump + 2333 .LCB2483: + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2334 .loc 1 881 0 + 2335 0016 0029 cmp r1, #0 + 2336 0018 00D1 bne .LCB2485 + 2337 001a B5E0 b .L190 @long jump + 2338 .LCB2485: + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2339 .loc 1 881 0 is_stmt 0 discriminator 1 + 2340 001c 002A cmp r2, #0 + 2341 001e 00D1 bne .LCB2487 + 2342 0020 B4E0 b .L191 @long jump + 2343 .LCB2487: + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2344 .loc 1 886 0 is_stmt 1 + 2345 0022 2033 adds r3, r3, #32 + 2346 0024 C35C ldrb r3, [r0, r3] + 2347 0026 012B cmp r3, #1 + 2348 0028 00D1 bne .LCB2491 + 2349 002a B1E0 b .L192 @long jump + 2350 .LCB2491: + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2351 .loc 1 886 0 is_stmt 0 discriminator 2 + 2352 002c 4023 movs r3, #64 + 2353 002e 0122 movs r2, #1 + 2354 .LVL190: + 2355 0030 C254 strb r2, [r0, r3] + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2356 .loc 1 889 0 is_stmt 1 discriminator 2 + 2357 0032 FFF7FEFF bl HAL_GetTick + 2358 .LVL191: + 2359 0036 0700 movs r7, r0 + 2360 .LVL192: + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2361 .loc 1 891 0 discriminator 2 + 2362 0038 4123 movs r3, #65 + 2363 003a 2122 movs r2, #33 + 2364 003c E254 strb r2, [r4, r3] + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2365 .loc 1 892 0 discriminator 2 + 2366 003e 0133 adds r3, r3, #1 + 2367 0040 013A subs r2, r2, #1 + 2368 0042 E254 strb r2, [r4, r3] + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2369 .loc 1 893 0 discriminator 2 + 2370 0044 0023 movs r3, #0 + 2371 0046 6364 str r3, [r4, #68] + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2372 .loc 1 896 0 discriminator 2 + 2373 0048 6562 str r5, [r4, #36] + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2374 .loc 1 897 0 discriminator 2 + 2375 004a 6685 strh r6, [r4, #42] + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 133 + + + 2376 .loc 1 898 0 discriminator 2 + 2377 004c 6363 str r3, [r4, #52] + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2378 .loc 1 901 0 discriminator 2 + 2379 004e 2268 ldr r2, [r4] + 2380 0050 5368 ldr r3, [r2, #4] + 2381 0052 5249 ldr r1, .L202 + 2382 0054 0B40 ands r3, r1 + 2383 0056 5360 str r3, [r2, #4] + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2384 .loc 1 904 0 discriminator 2 + 2385 0058 0090 str r0, [sp] + 2386 005a 039B ldr r3, [sp, #12] + 2387 005c 0022 movs r2, #0 + 2388 005e 0821 movs r1, #8 + 2389 0060 2000 movs r0, r4 + 2390 .LVL193: + 2391 0062 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2392 .LVL194: + 2393 0066 0028 cmp r0, #0 + 2394 0068 25D1 bne .L195 + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2395 .loc 1 912 0 + 2396 006a 2368 ldr r3, [r4] + 2397 006c 0822 movs r2, #8 + 2398 006e DA61 str r2, [r3, #28] + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2399 .loc 1 915 0 + 2400 0070 E368 ldr r3, [r4, #12] + 2401 0072 022B cmp r3, #2 + 2402 0074 27D0 beq .L196 + 2403 .L182: + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2404 .loc 1 930 0 + 2405 0076 8021 movs r1, #128 + 2406 0078 0097 str r7, [sp] + 2407 007a 039B ldr r3, [sp, #12] + 2408 007c 0022 movs r2, #0 + 2409 007e 4902 lsls r1, r1, #9 + 2410 0080 2000 movs r0, r4 + 2411 0082 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2412 .LVL195: + 2413 0086 0028 cmp r0, #0 + 2414 0088 32D1 bne .L197 + 2415 .L184: + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2416 .loc 1 937 0 + 2417 008a 638D ldrh r3, [r4, #42] + 2418 008c 9BB2 uxth r3, r3 + 2419 008e 002B cmp r3, #0 + 2420 0090 41D0 beq .L198 + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2421 .loc 1 940 0 + 2422 0092 3A00 movs r2, r7 + 2423 0094 0399 ldr r1, [sp, #12] + 2424 0096 2000 movs r0, r4 + 2425 0098 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + ARM GAS /tmp/ccpuPECZ.s page 134 + + + 2426 .LVL196: + 2427 009c 0028 cmp r0, #0 + 2428 009e 2FD1 bne .L199 + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 2429 .loc 1 956 0 + 2430 00a0 636A ldr r3, [r4, #36] + 2431 00a2 5A1C adds r2, r3, #1 + 2432 00a4 6262 str r2, [r4, #36] + 2433 00a6 2268 ldr r2, [r4] + 2434 00a8 1B78 ldrb r3, [r3] + 2435 00aa 9362 str r3, [r2, #40] + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2436 .loc 1 957 0 + 2437 00ac 638D ldrh r3, [r4, #42] + 2438 00ae 013B subs r3, r3, #1 + 2439 00b0 9BB2 uxth r3, r3 + 2440 00b2 6385 strh r3, [r4, #42] + 2441 00b4 E9E7 b .L184 + 2442 .L195: + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2443 .loc 1 907 0 + 2444 00b6 2268 ldr r2, [r4] + 2445 00b8 5168 ldr r1, [r2, #4] + 2446 00ba 8023 movs r3, #128 + 2447 00bc 1B02 lsls r3, r3, #8 + 2448 00be 0B43 orrs r3, r1 + 2449 00c0 5360 str r3, [r2, #4] + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2450 .loc 1 908 0 + 2451 00c2 0320 movs r0, #3 + 2452 00c4 5EE0 b .L180 + 2453 .L196: + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2454 .loc 1 918 0 + 2455 00c6 0097 str r7, [sp] + 2456 00c8 039B ldr r3, [sp, #12] + 2457 00ca 0022 movs r2, #0 + 2458 00cc 0821 movs r1, #8 + 2459 00ce 2000 movs r0, r4 + 2460 00d0 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2461 .LVL197: + 2462 00d4 0028 cmp r0, #0 + 2463 00d6 03D1 bne .L200 + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2464 .loc 1 926 0 + 2465 00d8 2368 ldr r3, [r4] + 2466 00da 0822 movs r2, #8 + 2467 00dc DA61 str r2, [r3, #28] + 2468 00de CAE7 b .L182 + 2469 .L200: + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2470 .loc 1 921 0 + 2471 00e0 2268 ldr r2, [r4] + 2472 00e2 5168 ldr r1, [r2, #4] + 2473 00e4 8023 movs r3, #128 + 2474 00e6 1B02 lsls r3, r3, #8 + 2475 00e8 0B43 orrs r3, r1 + ARM GAS /tmp/ccpuPECZ.s page 135 + + + 2476 00ea 5360 str r3, [r2, #4] + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2477 .loc 1 922 0 + 2478 00ec 0320 movs r0, #3 + 2479 00ee 49E0 b .L180 + 2480 .L197: + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2481 .loc 1 933 0 + 2482 00f0 2268 ldr r2, [r4] + 2483 00f2 5168 ldr r1, [r2, #4] + 2484 00f4 8023 movs r3, #128 + 2485 00f6 1B02 lsls r3, r3, #8 + 2486 00f8 0B43 orrs r3, r1 + 2487 00fa 5360 str r3, [r2, #4] + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2488 .loc 1 934 0 + 2489 00fc 0320 movs r0, #3 + 2490 00fe 41E0 b .L180 + 2491 .L199: + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2492 .loc 1 943 0 + 2493 0100 2268 ldr r2, [r4] + 2494 0102 5168 ldr r1, [r2, #4] + 2495 0104 8023 movs r3, #128 + 2496 0106 1B02 lsls r3, r3, #8 + 2497 0108 0B43 orrs r3, r1 + 2498 010a 5360 str r3, [r2, #4] + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2499 .loc 1 945 0 + 2500 010c 636C ldr r3, [r4, #68] + 2501 010e 042B cmp r3, #4 + 2502 0110 40D1 bne .L193 + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2503 .loc 1 947 0 + 2504 0112 0120 movs r0, #1 + 2505 0114 36E0 b .L180 + 2506 .L198: + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2507 .loc 1 961 0 + 2508 0116 3A00 movs r2, r7 + 2509 0118 0399 ldr r1, [sp, #12] + 2510 011a 2000 movs r0, r4 + 2511 011c FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2512 .LVL198: + 2513 0120 0028 cmp r0, #0 + 2514 0122 0AD0 beq .L187 + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2515 .loc 1 964 0 + 2516 0124 2268 ldr r2, [r4] + 2517 0126 5168 ldr r1, [r2, #4] + 2518 0128 8023 movs r3, #128 + 2519 012a 1B02 lsls r3, r3, #8 + 2520 012c 0B43 orrs r3, r1 + 2521 012e 5360 str r3, [r2, #4] + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2522 .loc 1 966 0 + 2523 0130 636C ldr r3, [r4, #68] + ARM GAS /tmp/ccpuPECZ.s page 136 + + + 2524 0132 042B cmp r3, #4 + 2525 0134 30D1 bne .L194 + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2526 .loc 1 970 0 + 2527 0136 0023 movs r3, #0 + 2528 0138 6364 str r3, [r4, #68] + 2529 .L187: + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2530 .loc 1 979 0 + 2531 013a 2368 ldr r3, [r4] + 2532 013c 2022 movs r2, #32 + 2533 013e DA61 str r2, [r3, #28] + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2534 .loc 1 982 0 + 2535 0140 8021 movs r1, #128 + 2536 0142 0097 str r7, [sp] + 2537 0144 039B ldr r3, [sp, #12] + 2538 0146 1F3A subs r2, r2, #31 + 2539 0148 0902 lsls r1, r1, #8 + 2540 014a 2000 movs r0, r4 + 2541 014c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2542 .LVL199: + 2543 0150 0028 cmp r0, #0 + 2544 0152 0ED1 bne .L201 + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2545 .loc 1 990 0 + 2546 0154 2268 ldr r2, [r4] + 2547 0156 5168 ldr r1, [r2, #4] + 2548 0158 8023 movs r3, #128 + 2549 015a 1B02 lsls r3, r3, #8 + 2550 015c 0B43 orrs r3, r1 + 2551 015e 5360 str r3, [r2, #4] + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2552 .loc 1 992 0 + 2553 0160 4123 movs r3, #65 + 2554 0162 2022 movs r2, #32 + 2555 0164 E254 strb r2, [r4, r3] + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2556 .loc 1 993 0 + 2557 0166 0023 movs r3, #0 + 2558 0168 2232 adds r2, r2, #34 + 2559 016a A354 strb r3, [r4, r2] + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2560 .loc 1 996 0 + 2561 016c 023A subs r2, r2, #2 + 2562 016e A354 strb r3, [r4, r2] + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2563 .loc 1 998 0 + 2564 0170 08E0 b .L180 + 2565 .L201: + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2566 .loc 1 985 0 + 2567 0172 2268 ldr r2, [r4] + 2568 0174 5168 ldr r1, [r2, #4] + 2569 0176 8023 movs r3, #128 + 2570 0178 1B02 lsls r3, r3, #8 + 2571 017a 0B43 orrs r3, r1 + ARM GAS /tmp/ccpuPECZ.s page 137 + + + 2572 017c 5360 str r3, [r2, #4] + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2573 .loc 1 986 0 + 2574 017e 0320 movs r0, #3 + 2575 0180 00E0 b .L180 + 2576 .LVL200: + 2577 .L189: +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2578 .loc 1 1002 0 + 2579 0182 0220 movs r0, #2 + 2580 .LVL201: + 2581 .L180: +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2582 .loc 1 1004 0 + 2583 0184 05B0 add sp, sp, #20 + 2584 @ sp needed + 2585 .LVL202: + 2586 .LVL203: + 2587 0186 F0BD pop {r4, r5, r6, r7, pc} + 2588 .LVL204: + 2589 .L190: + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2590 .loc 1 883 0 + 2591 0188 0120 movs r0, #1 + 2592 .LVL205: + 2593 018a FBE7 b .L180 + 2594 .LVL206: + 2595 .L191: + 2596 018c 0120 movs r0, #1 + 2597 .LVL207: + 2598 018e F9E7 b .L180 + 2599 .LVL208: + 2600 .L192: + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2601 .loc 1 886 0 + 2602 0190 0220 movs r0, #2 + 2603 .LVL209: + 2604 0192 F7E7 b .L180 + 2605 .LVL210: + 2606 .L193: + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2607 .loc 1 951 0 + 2608 0194 0320 movs r0, #3 + 2609 0196 F5E7 b .L180 + 2610 .L194: + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2611 .loc 1 974 0 + 2612 0198 0320 movs r0, #3 + 2613 019a F3E7 b .L180 + 2614 .L203: + 2615 .align 2 + 2616 .L202: + 2617 019c FF7FFFFF .word -32769 + 2618 .cfi_endproc + 2619 .LFE45: + 2621 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 2622 .align 1 + ARM GAS /tmp/ccpuPECZ.s page 138 + + + 2623 .global HAL_I2C_Slave_Receive + 2624 .syntax unified + 2625 .code 16 + 2626 .thumb_func + 2627 .fpu softvfp + 2629 HAL_I2C_Slave_Receive: + 2630 .LFB46: +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 2631 .loc 1 1016 0 + 2632 .cfi_startproc + 2633 @ args = 0, pretend = 0, frame = 8 + 2634 @ frame_needed = 0, uses_anonymous_args = 0 + 2635 .LVL211: + 2636 0000 F0B5 push {r4, r5, r6, r7, lr} + 2637 .LCFI20: + 2638 .cfi_def_cfa_offset 20 + 2639 .cfi_offset 4, -20 + 2640 .cfi_offset 5, -16 + 2641 .cfi_offset 6, -12 + 2642 .cfi_offset 7, -8 + 2643 .cfi_offset 14, -4 + 2644 0002 85B0 sub sp, sp, #20 + 2645 .LCFI21: + 2646 .cfi_def_cfa_offset 40 + 2647 0004 0500 movs r5, r0 + 2648 0006 0C00 movs r4, r1 + 2649 0008 1600 movs r6, r2 + 2650 000a 0393 str r3, [sp, #12] + 2651 .LVL212: +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2652 .loc 1 1019 0 + 2653 000c 4123 movs r3, #65 + 2654 .LVL213: + 2655 000e C35C ldrb r3, [r0, r3] + 2656 0010 202B cmp r3, #32 + 2657 0012 00D0 beq .LCB2808 + 2658 0014 ACE0 b .L213 @long jump + 2659 .LCB2808: +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2660 .loc 1 1021 0 + 2661 0016 0029 cmp r1, #0 + 2662 0018 00D1 bne .LCB2810 + 2663 001a ACE0 b .L214 @long jump + 2664 .LCB2810: +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2665 .loc 1 1021 0 is_stmt 0 discriminator 1 + 2666 001c 002A cmp r2, #0 + 2667 001e 00D1 bne .LCB2812 + 2668 0020 ABE0 b .L215 @long jump + 2669 .LCB2812: +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2670 .loc 1 1026 0 is_stmt 1 + 2671 0022 2033 adds r3, r3, #32 + 2672 0024 C35C ldrb r3, [r0, r3] + 2673 0026 012B cmp r3, #1 + 2674 0028 00D1 bne .LCB2816 + 2675 002a A8E0 b .L216 @long jump + ARM GAS /tmp/ccpuPECZ.s page 139 + + + 2676 .LCB2816: +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2677 .loc 1 1026 0 is_stmt 0 discriminator 2 + 2678 002c 4023 movs r3, #64 + 2679 002e 0122 movs r2, #1 + 2680 .LVL214: + 2681 0030 C254 strb r2, [r0, r3] +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2682 .loc 1 1029 0 is_stmt 1 discriminator 2 + 2683 0032 FFF7FEFF bl HAL_GetTick + 2684 .LVL215: + 2685 0036 0700 movs r7, r0 + 2686 .LVL216: +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2687 .loc 1 1031 0 discriminator 2 + 2688 0038 4123 movs r3, #65 + 2689 003a 2222 movs r2, #34 + 2690 003c EA54 strb r2, [r5, r3] +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2691 .loc 1 1032 0 discriminator 2 + 2692 003e 0133 adds r3, r3, #1 + 2693 0040 023A subs r2, r2, #2 + 2694 0042 EA54 strb r2, [r5, r3] +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2695 .loc 1 1033 0 discriminator 2 + 2696 0044 0023 movs r3, #0 + 2697 0046 6B64 str r3, [r5, #68] +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2698 .loc 1 1036 0 discriminator 2 + 2699 0048 6C62 str r4, [r5, #36] +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2700 .loc 1 1037 0 discriminator 2 + 2701 004a 6E85 strh r6, [r5, #42] +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2702 .loc 1 1038 0 discriminator 2 + 2703 004c 6B63 str r3, [r5, #52] +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2704 .loc 1 1041 0 discriminator 2 + 2705 004e 2A68 ldr r2, [r5] + 2706 0050 5368 ldr r3, [r2, #4] + 2707 0052 4D49 ldr r1, .L225 + 2708 0054 0B40 ands r3, r1 + 2709 0056 5360 str r3, [r2, #4] +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2710 .loc 1 1044 0 discriminator 2 + 2711 0058 0090 str r0, [sp] + 2712 005a 039B ldr r3, [sp, #12] + 2713 005c 0022 movs r2, #0 + 2714 005e 0821 movs r1, #8 + 2715 0060 2800 movs r0, r5 + 2716 .LVL217: + 2717 0062 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2718 .LVL218: + 2719 0066 0028 cmp r0, #0 + 2720 0068 22D1 bne .L219 +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2721 .loc 1 1052 0 + ARM GAS /tmp/ccpuPECZ.s page 140 + + + 2722 006a 2B68 ldr r3, [r5] + 2723 006c 0822 movs r2, #8 + 2724 006e DA61 str r2, [r3, #28] +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2725 .loc 1 1055 0 + 2726 0070 8021 movs r1, #128 + 2727 0072 0097 str r7, [sp] + 2728 0074 039B ldr r3, [sp, #12] + 2729 0076 073A subs r2, r2, #7 + 2730 0078 4902 lsls r1, r1, #9 + 2731 007a 2800 movs r0, r5 + 2732 007c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2733 .LVL219: + 2734 0080 0028 cmp r0, #0 + 2735 0082 1DD1 bne .L220 + 2736 .L207: +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2737 .loc 1 1062 0 + 2738 0084 6B8D ldrh r3, [r5, #42] + 2739 0086 9BB2 uxth r3, r3 + 2740 0088 002B cmp r3, #0 + 2741 008a 3BD0 beq .L221 +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2742 .loc 1 1065 0 + 2743 008c 3A00 movs r2, r7 + 2744 008e 0399 ldr r1, [sp, #12] + 2745 0090 2800 movs r0, r5 + 2746 0092 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2747 .LVL220: + 2748 0096 0028 cmp r0, #0 + 2749 0098 1AD1 bne .L222 +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 2750 .loc 1 1089 0 + 2751 009a 2B68 ldr r3, [r5] + 2752 009c 5A6A ldr r2, [r3, #36] + 2753 009e 6B6A ldr r3, [r5, #36] + 2754 00a0 591C adds r1, r3, #1 + 2755 00a2 6962 str r1, [r5, #36] + 2756 00a4 1A70 strb r2, [r3] +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2757 .loc 1 1090 0 + 2758 00a6 6B8D ldrh r3, [r5, #42] + 2759 00a8 013B subs r3, r3, #1 + 2760 00aa 9BB2 uxth r3, r3 + 2761 00ac 6B85 strh r3, [r5, #42] + 2762 00ae E9E7 b .L207 + 2763 .L219: +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2764 .loc 1 1047 0 + 2765 00b0 2A68 ldr r2, [r5] + 2766 00b2 5168 ldr r1, [r2, #4] + 2767 00b4 8023 movs r3, #128 + 2768 00b6 1B02 lsls r3, r3, #8 + 2769 00b8 0B43 orrs r3, r1 + 2770 00ba 5360 str r3, [r2, #4] +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2771 .loc 1 1048 0 + ARM GAS /tmp/ccpuPECZ.s page 141 + + + 2772 00bc 0320 movs r0, #3 + 2773 00be 58E0 b .L205 + 2774 .L220: +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2775 .loc 1 1058 0 + 2776 00c0 2A68 ldr r2, [r5] + 2777 00c2 5168 ldr r1, [r2, #4] + 2778 00c4 8023 movs r3, #128 + 2779 00c6 1B02 lsls r3, r3, #8 + 2780 00c8 0B43 orrs r3, r1 + 2781 00ca 5360 str r3, [r2, #4] +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2782 .loc 1 1059 0 + 2783 00cc 0320 movs r0, #3 + 2784 00ce 50E0 b .L205 + 2785 .L222: +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2786 .loc 1 1068 0 + 2787 00d0 2A68 ldr r2, [r5] + 2788 00d2 5168 ldr r1, [r2, #4] + 2789 00d4 8023 movs r3, #128 + 2790 00d6 1B02 lsls r3, r3, #8 + 2791 00d8 0B43 orrs r3, r1 + 2792 00da 5360 str r3, [r2, #4] +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2793 .loc 1 1071 0 + 2794 00dc 2B68 ldr r3, [r5] + 2795 00de 9A69 ldr r2, [r3, #24] + 2796 00e0 5207 lsls r2, r2, #29 + 2797 00e2 08D5 bpl .L209 +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 2798 .loc 1 1074 0 + 2799 00e4 5A6A ldr r2, [r3, #36] + 2800 00e6 6B6A ldr r3, [r5, #36] + 2801 00e8 591C adds r1, r3, #1 + 2802 00ea 6962 str r1, [r5, #36] + 2803 00ec 1A70 strb r2, [r3] +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2804 .loc 1 1075 0 + 2805 00ee 6B8D ldrh r3, [r5, #42] + 2806 00f0 013B subs r3, r3, #1 + 2807 00f2 9BB2 uxth r3, r3 + 2808 00f4 6B85 strh r3, [r5, #42] + 2809 .L209: +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2810 .loc 1 1078 0 + 2811 00f6 6B6C ldr r3, [r5, #68] + 2812 00f8 202B cmp r3, #32 + 2813 00fa 01D0 beq .L223 +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2814 .loc 1 1084 0 + 2815 00fc 0120 movs r0, #1 + 2816 00fe 38E0 b .L205 + 2817 .L223: +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2818 .loc 1 1080 0 + 2819 0100 0320 movs r0, #3 + ARM GAS /tmp/ccpuPECZ.s page 142 + + + 2820 0102 36E0 b .L205 + 2821 .L221: +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2822 .loc 1 1094 0 + 2823 0104 3A00 movs r2, r7 + 2824 0106 0399 ldr r1, [sp, #12] + 2825 0108 2800 movs r0, r5 + 2826 010a FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2827 .LVL221: + 2828 010e 0028 cmp r0, #0 + 2829 0110 0AD0 beq .L211 +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2830 .loc 1 1097 0 + 2831 0112 2A68 ldr r2, [r5] + 2832 0114 5168 ldr r1, [r2, #4] + 2833 0116 8023 movs r3, #128 + 2834 0118 1B02 lsls r3, r3, #8 + 2835 011a 0B43 orrs r3, r1 + 2836 011c 5360 str r3, [r2, #4] +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2837 .loc 1 1099 0 + 2838 011e 6B6C ldr r3, [r5, #68] + 2839 0120 042B cmp r3, #4 + 2840 0122 2ED1 bne .L218 +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2841 .loc 1 1101 0 + 2842 0124 0120 movs r0, #1 + 2843 0126 24E0 b .L205 + 2844 .L211: +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2845 .loc 1 1110 0 + 2846 0128 2B68 ldr r3, [r5] + 2847 012a 2022 movs r2, #32 + 2848 012c DA61 str r2, [r3, #28] +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2849 .loc 1 1113 0 + 2850 012e 8021 movs r1, #128 + 2851 0130 0097 str r7, [sp] + 2852 0132 039B ldr r3, [sp, #12] + 2853 0134 1F3A subs r2, r2, #31 + 2854 0136 0902 lsls r1, r1, #8 + 2855 0138 2800 movs r0, r5 + 2856 013a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2857 .LVL222: + 2858 013e 0028 cmp r0, #0 + 2859 0140 0ED1 bne .L224 +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2860 .loc 1 1121 0 + 2861 0142 2A68 ldr r2, [r5] + 2862 0144 5168 ldr r1, [r2, #4] + 2863 0146 8023 movs r3, #128 + 2864 0148 1B02 lsls r3, r3, #8 + 2865 014a 0B43 orrs r3, r1 + 2866 014c 5360 str r3, [r2, #4] +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2867 .loc 1 1123 0 + 2868 014e 4123 movs r3, #65 + ARM GAS /tmp/ccpuPECZ.s page 143 + + + 2869 0150 2022 movs r2, #32 + 2870 0152 EA54 strb r2, [r5, r3] +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2871 .loc 1 1124 0 + 2872 0154 0023 movs r3, #0 + 2873 0156 2232 adds r2, r2, #34 + 2874 0158 AB54 strb r3, [r5, r2] +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2875 .loc 1 1127 0 + 2876 015a 023A subs r2, r2, #2 + 2877 015c AB54 strb r3, [r5, r2] +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2878 .loc 1 1129 0 + 2879 015e 08E0 b .L205 + 2880 .L224: +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 2881 .loc 1 1116 0 + 2882 0160 2A68 ldr r2, [r5] + 2883 0162 5168 ldr r1, [r2, #4] + 2884 0164 8023 movs r3, #128 + 2885 0166 1B02 lsls r3, r3, #8 + 2886 0168 0B43 orrs r3, r1 + 2887 016a 5360 str r3, [r2, #4] +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2888 .loc 1 1117 0 + 2889 016c 0320 movs r0, #3 + 2890 016e 00E0 b .L205 + 2891 .LVL223: + 2892 .L213: +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2893 .loc 1 1133 0 + 2894 0170 0220 movs r0, #2 + 2895 .LVL224: + 2896 .L205: +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2897 .loc 1 1135 0 + 2898 0172 05B0 add sp, sp, #20 + 2899 @ sp needed + 2900 .LVL225: + 2901 .LVL226: + 2902 0174 F0BD pop {r4, r5, r6, r7, pc} + 2903 .LVL227: + 2904 .L214: +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2905 .loc 1 1023 0 + 2906 0176 0120 movs r0, #1 + 2907 .LVL228: + 2908 0178 FBE7 b .L205 + 2909 .LVL229: + 2910 .L215: + 2911 017a 0120 movs r0, #1 + 2912 .LVL230: + 2913 017c F9E7 b .L205 + 2914 .LVL231: + 2915 .L216: +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2916 .loc 1 1026 0 + ARM GAS /tmp/ccpuPECZ.s page 144 + + + 2917 017e 0220 movs r0, #2 + 2918 .LVL232: + 2919 0180 F7E7 b .L205 + 2920 .LVL233: + 2921 .L218: +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 2922 .loc 1 1105 0 + 2923 0182 0320 movs r0, #3 + 2924 0184 F5E7 b .L205 + 2925 .L226: + 2926 0186 C046 .align 2 + 2927 .L225: + 2928 0188 FF7FFFFF .word -32769 + 2929 .cfi_endproc + 2930 .LFE46: + 2932 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 2933 .align 1 + 2934 .global HAL_I2C_Master_Transmit_IT + 2935 .syntax unified + 2936 .code 16 + 2937 .thumb_func + 2938 .fpu softvfp + 2940 HAL_I2C_Master_Transmit_IT: + 2941 .LFB47: +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 2942 .loc 1 1148 0 + 2943 .cfi_startproc + 2944 @ args = 0, pretend = 0, frame = 0 + 2945 @ frame_needed = 0, uses_anonymous_args = 0 + 2946 .LVL234: + 2947 0000 70B5 push {r4, r5, r6, lr} + 2948 .LCFI22: + 2949 .cfi_def_cfa_offset 16 + 2950 .cfi_offset 4, -16 + 2951 .cfi_offset 5, -12 + 2952 .cfi_offset 6, -8 + 2953 .cfi_offset 14, -4 + 2954 .LVL235: +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2955 .loc 1 1151 0 + 2956 0002 4124 movs r4, #65 + 2957 0004 045D ldrb r4, [r0, r4] + 2958 0006 202C cmp r4, #32 + 2959 0008 48D1 bne .L232 +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2960 .loc 1 1153 0 + 2961 000a 0468 ldr r4, [r0] + 2962 000c A569 ldr r5, [r4, #24] + 2963 000e 2D04 lsls r5, r5, #16 + 2964 0010 46D4 bmi .L233 +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2965 .loc 1 1159 0 + 2966 0012 4025 movs r5, #64 + 2967 0014 455D ldrb r5, [r0, r5] + 2968 0016 012D cmp r5, #1 + 2969 0018 44D0 beq .L234 +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 145 + + + 2970 .loc 1 1159 0 is_stmt 0 discriminator 2 + 2971 001a 4025 movs r5, #64 + 2972 001c 0126 movs r6, #1 + 2973 001e 4655 strb r6, [r0, r5] +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2974 .loc 1 1161 0 is_stmt 1 discriminator 2 + 2975 0020 0135 adds r5, r5, #1 + 2976 0022 2036 adds r6, r6, #32 + 2977 0024 4655 strb r6, [r0, r5] +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2978 .loc 1 1162 0 discriminator 2 + 2979 0026 0135 adds r5, r5, #1 + 2980 0028 113E subs r6, r6, #17 + 2981 002a 4655 strb r6, [r0, r5] +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2982 .loc 1 1163 0 discriminator 2 + 2983 002c 0025 movs r5, #0 + 2984 002e 4564 str r5, [r0, #68] +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2985 .loc 1 1166 0 discriminator 2 + 2986 0030 4262 str r2, [r0, #36] +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2987 .loc 1 1167 0 discriminator 2 + 2988 0032 4385 strh r3, [r0, #42] +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2989 .loc 1 1168 0 discriminator 2 + 2990 0034 1C4B ldr r3, .L238 + 2991 .LVL236: + 2992 0036 C362 str r3, [r0, #44] + 2993 .LVL237: +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 2994 .loc 1 1169 0 discriminator 2 + 2995 0038 1C4B ldr r3, .L238+4 + 2996 003a 4363 str r3, [r0, #52] +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 2997 .loc 1 1171 0 discriminator 2 + 2998 003c 438D ldrh r3, [r0, #42] + 2999 003e 9BB2 uxth r3, r3 + 3000 0040 FF2B cmp r3, #255 + 3001 0042 22D9 bls .L229 +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3002 .loc 1 1173 0 + 3003 0044 FF23 movs r3, #255 + 3004 0046 0385 strh r3, [r0, #40] + 3005 .LVL238: +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3006 .loc 1 1174 0 + 3007 0048 8025 movs r5, #128 + 3008 004a 6D04 lsls r5, r5, #17 + 3009 .LVL239: + 3010 .L230: +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3011 .loc 1 1184 0 + 3012 004c 028D ldrh r2, [r0, #40] + 3013 .LVL240: + 3014 004e D2B2 uxtb r2, r2 + 3015 .LVL241: + ARM GAS /tmp/ccpuPECZ.s page 146 + + + 3016 .LBB184: + 3017 .LBB185: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 3018 .loc 1 4713 0 + 3019 0050 6368 ldr r3, [r4, #4] + 3020 0052 174E ldr r6, .L238+8 + 3021 0054 3340 ands r3, r6 + 3022 0056 8905 lsls r1, r1, #22 + 3023 .LVL242: + 3024 0058 890D lsrs r1, r1, #22 + 3025 005a 1204 lsls r2, r2, #16 + 3026 .LVL243: + 3027 005c 1143 orrs r1, r2 + 3028 005e 0D43 orrs r5, r1 + 3029 .LVL244: + 3030 0060 1449 ldr r1, .L238+12 + 3031 0062 2943 orrs r1, r5 + 3032 0064 1943 orrs r1, r3 + 3033 0066 6160 str r1, [r4, #4] + 3034 .LVL245: + 3035 .LBE185: + 3036 .LBE184: +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3037 .loc 1 1187 0 + 3038 0068 4023 movs r3, #64 + 3039 006a 0022 movs r2, #0 + 3040 006c C254 strb r2, [r0, r3] + 3041 .LVL246: + 3042 .LBB186: + 3043 .LBB187: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3044 .loc 1 4728 0 + 3045 006e 436B ldr r3, [r0, #52] + 3046 0070 114A ldr r2, .L238+16 + 3047 0072 9342 cmp r3, r2 + 3048 0074 10D0 beq .L235 + 3049 0076 114A ldr r2, .L238+20 + 3050 0078 9342 cmp r3, r2 + 3051 007a 0BD0 beq .L237 + 3052 007c F221 movs r1, #242 + 3053 .L231: + 3054 .LVL247: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3055 .loc 1 4785 0 + 3056 007e 0268 ldr r2, [r0] + 3057 0080 1368 ldr r3, [r2] + 3058 0082 0B43 orrs r3, r1 + 3059 0084 1360 str r3, [r2] + 3060 .LVL248: + 3061 .LBE187: + 3062 .LBE186: +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3063 .loc 1 1198 0 + 3064 0086 0020 movs r0, #0 + 3065 .LVL249: + 3066 0088 09E0 b .L228 + 3067 .LVL250: + ARM GAS /tmp/ccpuPECZ.s page 147 + + + 3068 .L229: +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3069 .loc 1 1178 0 + 3070 008a 438D ldrh r3, [r0, #42] + 3071 008c 0385 strh r3, [r0, #40] + 3072 .LVL251: +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3073 .loc 1 1179 0 + 3074 008e 8025 movs r5, #128 + 3075 0090 AD04 lsls r5, r5, #18 + 3076 0092 DBE7 b .L230 + 3077 .LVL252: + 3078 .L237: + 3079 .LBB189: + 3080 .LBB188: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3081 .loc 1 4728 0 + 3082 0094 0021 movs r1, #0 + 3083 0096 F2E7 b .L231 + 3084 .L235: + 3085 0098 0021 movs r1, #0 + 3086 009a F0E7 b .L231 + 3087 .LVL253: + 3088 .L232: + 3089 .LBE188: + 3090 .LBE189: +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3091 .loc 1 1202 0 + 3092 009c 0220 movs r0, #2 + 3093 .LVL254: + 3094 .L228: +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3095 .loc 1 1204 0 + 3096 @ sp needed + 3097 009e 70BD pop {r4, r5, r6, pc} + 3098 .LVL255: + 3099 .L233: +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3100 .loc 1 1155 0 + 3101 00a0 0220 movs r0, #2 + 3102 .LVL256: + 3103 00a2 FCE7 b .L228 + 3104 .LVL257: + 3105 .L234: +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3106 .loc 1 1159 0 + 3107 00a4 0220 movs r0, #2 + 3108 .LVL258: + 3109 00a6 FAE7 b .L228 + 3110 .L239: + 3111 .align 2 + 3112 .L238: + 3113 00a8 0000FFFF .word -65536 + 3114 00ac 00000000 .word I2C_Master_ISR_IT + 3115 00b0 009800FC .word -67069952 + 3116 00b4 00200080 .word -2147475456 + 3117 00b8 00000000 .word I2C_Master_ISR_DMA + ARM GAS /tmp/ccpuPECZ.s page 148 + + + 3118 00bc 00000000 .word I2C_Slave_ISR_DMA + 3119 .cfi_endproc + 3120 .LFE47: + 3122 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 3123 .align 1 + 3124 .global HAL_I2C_Master_Receive_IT + 3125 .syntax unified + 3126 .code 16 + 3127 .thumb_func + 3128 .fpu softvfp + 3130 HAL_I2C_Master_Receive_IT: + 3131 .LFB48: +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 3132 .loc 1 1217 0 + 3133 .cfi_startproc + 3134 @ args = 0, pretend = 0, frame = 0 + 3135 @ frame_needed = 0, uses_anonymous_args = 0 + 3136 .LVL259: + 3137 0000 70B5 push {r4, r5, r6, lr} + 3138 .LCFI23: + 3139 .cfi_def_cfa_offset 16 + 3140 .cfi_offset 4, -16 + 3141 .cfi_offset 5, -12 + 3142 .cfi_offset 6, -8 + 3143 .cfi_offset 14, -4 + 3144 .LVL260: +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3145 .loc 1 1220 0 + 3146 0002 4124 movs r4, #65 + 3147 0004 045D ldrb r4, [r0, r4] + 3148 0006 202C cmp r4, #32 + 3149 0008 48D1 bne .L245 +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3150 .loc 1 1222 0 + 3151 000a 0468 ldr r4, [r0] + 3152 000c A569 ldr r5, [r4, #24] + 3153 000e 2D04 lsls r5, r5, #16 + 3154 0010 46D4 bmi .L246 +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3155 .loc 1 1228 0 + 3156 0012 4025 movs r5, #64 + 3157 0014 455D ldrb r5, [r0, r5] + 3158 0016 012D cmp r5, #1 + 3159 0018 44D0 beq .L247 +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3160 .loc 1 1228 0 is_stmt 0 discriminator 2 + 3161 001a 4025 movs r5, #64 + 3162 001c 0126 movs r6, #1 + 3163 001e 4655 strb r6, [r0, r5] +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3164 .loc 1 1230 0 is_stmt 1 discriminator 2 + 3165 0020 0135 adds r5, r5, #1 + 3166 0022 2136 adds r6, r6, #33 + 3167 0024 4655 strb r6, [r0, r5] +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3168 .loc 1 1231 0 discriminator 2 + 3169 0026 0135 adds r5, r5, #1 + ARM GAS /tmp/ccpuPECZ.s page 149 + + + 3170 0028 123E subs r6, r6, #18 + 3171 002a 4655 strb r6, [r0, r5] +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3172 .loc 1 1232 0 discriminator 2 + 3173 002c 0025 movs r5, #0 + 3174 002e 4564 str r5, [r0, #68] +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3175 .loc 1 1235 0 discriminator 2 + 3176 0030 4262 str r2, [r0, #36] +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3177 .loc 1 1236 0 discriminator 2 + 3178 0032 4385 strh r3, [r0, #42] +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3179 .loc 1 1237 0 discriminator 2 + 3180 0034 1C4B ldr r3, .L251 + 3181 .LVL261: + 3182 0036 C362 str r3, [r0, #44] + 3183 .LVL262: +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3184 .loc 1 1238 0 discriminator 2 + 3185 0038 1C4B ldr r3, .L251+4 + 3186 003a 4363 str r3, [r0, #52] +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3187 .loc 1 1240 0 discriminator 2 + 3188 003c 438D ldrh r3, [r0, #42] + 3189 003e 9BB2 uxth r3, r3 + 3190 0040 FF2B cmp r3, #255 + 3191 0042 22D9 bls .L242 +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3192 .loc 1 1242 0 + 3193 0044 FF23 movs r3, #255 + 3194 0046 0385 strh r3, [r0, #40] + 3195 .LVL263: +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3196 .loc 1 1243 0 + 3197 0048 8025 movs r5, #128 + 3198 004a 6D04 lsls r5, r5, #17 + 3199 .LVL264: + 3200 .L243: +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3201 .loc 1 1253 0 + 3202 004c 028D ldrh r2, [r0, #40] + 3203 .LVL265: + 3204 004e D2B2 uxtb r2, r2 + 3205 .LVL266: + 3206 .LBB190: + 3207 .LBB191: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 3208 .loc 1 4713 0 + 3209 0050 6368 ldr r3, [r4, #4] + 3210 0052 174E ldr r6, .L251+8 + 3211 0054 3340 ands r3, r6 + 3212 0056 8905 lsls r1, r1, #22 + 3213 .LVL267: + 3214 0058 890D lsrs r1, r1, #22 + 3215 005a 1204 lsls r2, r2, #16 + 3216 .LVL268: + ARM GAS /tmp/ccpuPECZ.s page 150 + + + 3217 005c 1143 orrs r1, r2 + 3218 005e 0D43 orrs r5, r1 + 3219 .LVL269: + 3220 0060 1449 ldr r1, .L251+12 + 3221 0062 2943 orrs r1, r5 + 3222 0064 1943 orrs r1, r3 + 3223 0066 6160 str r1, [r4, #4] + 3224 .LVL270: + 3225 .LBE191: + 3226 .LBE190: +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3227 .loc 1 1256 0 + 3228 0068 4023 movs r3, #64 + 3229 006a 0022 movs r2, #0 + 3230 006c C254 strb r2, [r0, r3] + 3231 .LVL271: + 3232 .LBB192: + 3233 .LBB193: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3234 .loc 1 4728 0 + 3235 006e 436B ldr r3, [r0, #52] + 3236 0070 114A ldr r2, .L251+16 + 3237 0072 9342 cmp r3, r2 + 3238 0074 10D0 beq .L248 + 3239 0076 114A ldr r2, .L251+20 + 3240 0078 9342 cmp r3, r2 + 3241 007a 0BD0 beq .L250 + 3242 007c F421 movs r1, #244 + 3243 .L244: + 3244 .LVL272: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3245 .loc 1 4785 0 + 3246 007e 0268 ldr r2, [r0] + 3247 0080 1368 ldr r3, [r2] + 3248 0082 0B43 orrs r3, r1 + 3249 0084 1360 str r3, [r2] + 3250 .LVL273: + 3251 .LBE193: + 3252 .LBE192: +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3253 .loc 1 1267 0 + 3254 0086 0020 movs r0, #0 + 3255 .LVL274: + 3256 0088 09E0 b .L241 + 3257 .LVL275: + 3258 .L242: +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3259 .loc 1 1247 0 + 3260 008a 438D ldrh r3, [r0, #42] + 3261 008c 0385 strh r3, [r0, #40] + 3262 .LVL276: +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3263 .loc 1 1248 0 + 3264 008e 8025 movs r5, #128 + 3265 0090 AD04 lsls r5, r5, #18 + 3266 0092 DBE7 b .L243 + 3267 .LVL277: + ARM GAS /tmp/ccpuPECZ.s page 151 + + + 3268 .L250: + 3269 .LBB195: + 3270 .LBB194: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3271 .loc 1 4728 0 + 3272 0094 0021 movs r1, #0 + 3273 0096 F2E7 b .L244 + 3274 .L248: + 3275 0098 0021 movs r1, #0 + 3276 009a F0E7 b .L244 + 3277 .LVL278: + 3278 .L245: + 3279 .LBE194: + 3280 .LBE195: +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3281 .loc 1 1271 0 + 3282 009c 0220 movs r0, #2 + 3283 .LVL279: + 3284 .L241: +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3285 .loc 1 1273 0 + 3286 @ sp needed + 3287 009e 70BD pop {r4, r5, r6, pc} + 3288 .LVL280: + 3289 .L246: +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3290 .loc 1 1224 0 + 3291 00a0 0220 movs r0, #2 + 3292 .LVL281: + 3293 00a2 FCE7 b .L241 + 3294 .LVL282: + 3295 .L247: +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3296 .loc 1 1228 0 + 3297 00a4 0220 movs r0, #2 + 3298 .LVL283: + 3299 00a6 FAE7 b .L241 + 3300 .L252: + 3301 .align 2 + 3302 .L251: + 3303 00a8 0000FFFF .word -65536 + 3304 00ac 00000000 .word I2C_Master_ISR_IT + 3305 00b0 009800FC .word -67069952 + 3306 00b4 00240080 .word -2147474432 + 3307 00b8 00000000 .word I2C_Master_ISR_DMA + 3308 00bc 00000000 .word I2C_Slave_ISR_DMA + 3309 .cfi_endproc + 3310 .LFE48: + 3312 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 3313 .align 1 + 3314 .global HAL_I2C_Slave_Transmit_IT + 3315 .syntax unified + 3316 .code 16 + 3317 .thumb_func + 3318 .fpu softvfp + 3320 HAL_I2C_Slave_Transmit_IT: + 3321 .LFB49: + ARM GAS /tmp/ccpuPECZ.s page 152 + + +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3322 .loc 1 1284 0 + 3323 .cfi_startproc + 3324 @ args = 0, pretend = 0, frame = 0 + 3325 @ frame_needed = 0, uses_anonymous_args = 0 + 3326 .LVL284: + 3327 0000 F0B5 push {r4, r5, r6, r7, lr} + 3328 .LCFI24: + 3329 .cfi_def_cfa_offset 20 + 3330 .cfi_offset 4, -20 + 3331 .cfi_offset 5, -16 + 3332 .cfi_offset 6, -12 + 3333 .cfi_offset 7, -8 + 3334 .cfi_offset 14, -4 +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3335 .loc 1 1285 0 + 3336 0002 4123 movs r3, #65 + 3337 0004 C35C ldrb r3, [r0, r3] + 3338 0006 202B cmp r3, #32 + 3339 0008 23D1 bne .L255 +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3340 .loc 1 1288 0 + 3341 000a 2033 adds r3, r3, #32 + 3342 000c C35C ldrb r3, [r0, r3] + 3343 000e 012B cmp r3, #1 + 3344 0010 21D0 beq .L256 +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3345 .loc 1 1288 0 is_stmt 0 discriminator 2 + 3346 0012 4024 movs r4, #64 + 3347 0014 0123 movs r3, #1 + 3348 0016 0355 strb r3, [r0, r4] +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3349 .loc 1 1290 0 is_stmt 1 discriminator 2 + 3350 0018 4033 adds r3, r3, #64 + 3351 001a 2125 movs r5, #33 + 3352 001c C554 strb r5, [r0, r3] +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3353 .loc 1 1291 0 discriminator 2 + 3354 001e 0133 adds r3, r3, #1 + 3355 0020 013D subs r5, r5, #1 + 3356 0022 C554 strb r5, [r0, r3] +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3357 .loc 1 1292 0 discriminator 2 + 3358 0024 0025 movs r5, #0 + 3359 0026 4564 str r5, [r0, #68] +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3360 .loc 1 1295 0 discriminator 2 + 3361 0028 0668 ldr r6, [r0] + 3362 002a 7368 ldr r3, [r6, #4] + 3363 002c 0B4F ldr r7, .L257 + 3364 002e 3B40 ands r3, r7 + 3365 0030 7360 str r3, [r6, #4] +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3366 .loc 1 1298 0 discriminator 2 + 3367 0032 4162 str r1, [r0, #36] +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3368 .loc 1 1299 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 153 + + + 3369 0034 4285 strh r2, [r0, #42] +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3370 .loc 1 1300 0 discriminator 2 + 3371 0036 438D ldrh r3, [r0, #42] + 3372 0038 0385 strh r3, [r0, #40] +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3373 .loc 1 1301 0 discriminator 2 + 3374 003a 094B ldr r3, .L257+4 + 3375 003c C362 str r3, [r0, #44] +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3376 .loc 1 1302 0 discriminator 2 + 3377 003e 094B ldr r3, .L257+8 + 3378 0040 4363 str r3, [r0, #52] +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3379 .loc 1 1305 0 discriminator 2 + 3380 0042 0555 strb r5, [r0, r4] + 3381 .LVL285: + 3382 .LBB196: + 3383 .LBB197: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3384 .loc 1 4785 0 discriminator 2 + 3385 0044 0268 ldr r2, [r0] + 3386 .LVL286: + 3387 0046 1368 ldr r3, [r2] + 3388 0048 FA21 movs r1, #250 + 3389 .LVL287: + 3390 004a 0B43 orrs r3, r1 + 3391 004c 1360 str r3, [r2] + 3392 .LVL288: + 3393 .LBE197: + 3394 .LBE196: +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3395 .loc 1 1316 0 discriminator 2 + 3396 004e 0020 movs r0, #0 + 3397 .LVL289: + 3398 0050 00E0 b .L254 + 3399 .LVL290: + 3400 .L255: +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3401 .loc 1 1320 0 + 3402 0052 0220 movs r0, #2 + 3403 .LVL291: + 3404 .L254: +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3405 .loc 1 1322 0 + 3406 @ sp needed + 3407 0054 F0BD pop {r4, r5, r6, r7, pc} + 3408 .LVL292: + 3409 .L256: +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3410 .loc 1 1288 0 + 3411 0056 0220 movs r0, #2 + 3412 .LVL293: + 3413 0058 FCE7 b .L254 + 3414 .L258: + 3415 005a C046 .align 2 + 3416 .L257: + ARM GAS /tmp/ccpuPECZ.s page 154 + + + 3417 005c FF7FFFFF .word -32769 + 3418 0060 0000FFFF .word -65536 + 3419 0064 00000000 .word I2C_Slave_ISR_IT + 3420 .cfi_endproc + 3421 .LFE49: + 3423 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 3424 .align 1 + 3425 .global HAL_I2C_Slave_Receive_IT + 3426 .syntax unified + 3427 .code 16 + 3428 .thumb_func + 3429 .fpu softvfp + 3431 HAL_I2C_Slave_Receive_IT: + 3432 .LFB50: +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3433 .loc 1 1333 0 + 3434 .cfi_startproc + 3435 @ args = 0, pretend = 0, frame = 0 + 3436 @ frame_needed = 0, uses_anonymous_args = 0 + 3437 .LVL294: + 3438 0000 F0B5 push {r4, r5, r6, r7, lr} + 3439 .LCFI25: + 3440 .cfi_def_cfa_offset 20 + 3441 .cfi_offset 4, -20 + 3442 .cfi_offset 5, -16 + 3443 .cfi_offset 6, -12 + 3444 .cfi_offset 7, -8 + 3445 .cfi_offset 14, -4 +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3446 .loc 1 1334 0 + 3447 0002 4123 movs r3, #65 + 3448 0004 C35C ldrb r3, [r0, r3] + 3449 0006 202B cmp r3, #32 + 3450 0008 23D1 bne .L261 +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3451 .loc 1 1337 0 + 3452 000a 2033 adds r3, r3, #32 + 3453 000c C35C ldrb r3, [r0, r3] + 3454 000e 012B cmp r3, #1 + 3455 0010 21D0 beq .L262 +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3456 .loc 1 1337 0 is_stmt 0 discriminator 2 + 3457 0012 4024 movs r4, #64 + 3458 0014 0123 movs r3, #1 + 3459 0016 0355 strb r3, [r0, r4] +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3460 .loc 1 1339 0 is_stmt 1 discriminator 2 + 3461 0018 4033 adds r3, r3, #64 + 3462 001a 2225 movs r5, #34 + 3463 001c C554 strb r5, [r0, r3] +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3464 .loc 1 1340 0 discriminator 2 + 3465 001e 0133 adds r3, r3, #1 + 3466 0020 023D subs r5, r5, #2 + 3467 0022 C554 strb r5, [r0, r3] +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3468 .loc 1 1341 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 155 + + + 3469 0024 0025 movs r5, #0 + 3470 0026 4564 str r5, [r0, #68] +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3471 .loc 1 1344 0 discriminator 2 + 3472 0028 0668 ldr r6, [r0] + 3473 002a 7368 ldr r3, [r6, #4] + 3474 002c 0B4F ldr r7, .L263 + 3475 002e 3B40 ands r3, r7 + 3476 0030 7360 str r3, [r6, #4] +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3477 .loc 1 1347 0 discriminator 2 + 3478 0032 4162 str r1, [r0, #36] +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3479 .loc 1 1348 0 discriminator 2 + 3480 0034 4285 strh r2, [r0, #42] +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3481 .loc 1 1349 0 discriminator 2 + 3482 0036 438D ldrh r3, [r0, #42] + 3483 0038 0385 strh r3, [r0, #40] +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3484 .loc 1 1350 0 discriminator 2 + 3485 003a 094B ldr r3, .L263+4 + 3486 003c C362 str r3, [r0, #44] +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3487 .loc 1 1351 0 discriminator 2 + 3488 003e 094B ldr r3, .L263+8 + 3489 0040 4363 str r3, [r0, #52] +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3490 .loc 1 1354 0 discriminator 2 + 3491 0042 0555 strb r5, [r0, r4] + 3492 .LVL295: + 3493 .LBB198: + 3494 .LBB199: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3495 .loc 1 4785 0 discriminator 2 + 3496 0044 0268 ldr r2, [r0] + 3497 .LVL296: + 3498 0046 1368 ldr r3, [r2] + 3499 0048 FC21 movs r1, #252 + 3500 .LVL297: + 3501 004a 0B43 orrs r3, r1 + 3502 004c 1360 str r3, [r2] + 3503 .LVL298: + 3504 .LBE199: + 3505 .LBE198: +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3506 .loc 1 1365 0 discriminator 2 + 3507 004e 0020 movs r0, #0 + 3508 .LVL299: + 3509 0050 00E0 b .L260 + 3510 .LVL300: + 3511 .L261: +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3512 .loc 1 1369 0 + 3513 0052 0220 movs r0, #2 + 3514 .LVL301: + 3515 .L260: + ARM GAS /tmp/ccpuPECZ.s page 156 + + +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3516 .loc 1 1371 0 + 3517 @ sp needed + 3518 0054 F0BD pop {r4, r5, r6, r7, pc} + 3519 .LVL302: + 3520 .L262: +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3521 .loc 1 1337 0 + 3522 0056 0220 movs r0, #2 + 3523 .LVL303: + 3524 0058 FCE7 b .L260 + 3525 .L264: + 3526 005a C046 .align 2 + 3527 .L263: + 3528 005c FF7FFFFF .word -32769 + 3529 0060 0000FFFF .word -65536 + 3530 0064 00000000 .word I2C_Slave_ISR_IT + 3531 .cfi_endproc + 3532 .LFE50: + 3534 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 3535 .align 1 + 3536 .global HAL_I2C_Master_Transmit_DMA + 3537 .syntax unified + 3538 .code 16 + 3539 .thumb_func + 3540 .fpu softvfp + 3542 HAL_I2C_Master_Transmit_DMA: + 3543 .LFB51: +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 3544 .loc 1 1384 0 + 3545 .cfi_startproc + 3546 @ args = 0, pretend = 0, frame = 0 + 3547 @ frame_needed = 0, uses_anonymous_args = 0 + 3548 .LVL304: + 3549 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3550 .LCFI26: + 3551 .cfi_def_cfa_offset 24 + 3552 .cfi_offset 3, -24 + 3553 .cfi_offset 4, -20 + 3554 .cfi_offset 5, -16 + 3555 .cfi_offset 6, -12 + 3556 .cfi_offset 7, -8 + 3557 .cfi_offset 14, -4 + 3558 0002 0400 movs r4, r0 + 3559 0004 0D00 movs r5, r1 + 3560 0006 1100 movs r1, r2 + 3561 .LVL305: +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3562 .loc 1 1387 0 + 3563 0008 4122 movs r2, #65 + 3564 .LVL306: + 3565 000a 825C ldrb r2, [r0, r2] + 3566 000c 202A cmp r2, #32 + 3567 000e 00D0 beq .LCB3787 + 3568 0010 8CE0 b .L272 @long jump + 3569 .LCB3787: +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 157 + + + 3570 .loc 1 1389 0 + 3571 0012 0268 ldr r2, [r0] + 3572 0014 9069 ldr r0, [r2, #24] + 3573 .LVL307: + 3574 0016 0004 lsls r0, r0, #16 + 3575 0018 00D5 bpl .LCB3794 + 3576 001a 89E0 b .L273 @long jump + 3577 .LCB3794: +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3578 .loc 1 1395 0 + 3579 001c 4020 movs r0, #64 + 3580 001e 205C ldrb r0, [r4, r0] + 3581 0020 0128 cmp r0, #1 + 3582 0022 00D1 bne .LCB3798 + 3583 0024 86E0 b .L274 @long jump + 3584 .LCB3798: +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3585 .loc 1 1395 0 is_stmt 0 discriminator 2 + 3586 0026 4020 movs r0, #64 + 3587 0028 0126 movs r6, #1 + 3588 002a 2654 strb r6, [r4, r0] +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3589 .loc 1 1397 0 is_stmt 1 discriminator 2 + 3590 002c 0130 adds r0, r0, #1 + 3591 002e 2036 adds r6, r6, #32 + 3592 0030 2654 strb r6, [r4, r0] +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3593 .loc 1 1398 0 discriminator 2 + 3594 0032 0130 adds r0, r0, #1 + 3595 0034 113E subs r6, r6, #17 + 3596 0036 2654 strb r6, [r4, r0] +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3597 .loc 1 1399 0 discriminator 2 + 3598 0038 0020 movs r0, #0 + 3599 003a 6064 str r0, [r4, #68] +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3600 .loc 1 1402 0 discriminator 2 + 3601 003c 6162 str r1, [r4, #36] +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3602 .loc 1 1403 0 discriminator 2 + 3603 003e 6385 strh r3, [r4, #42] +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3604 .loc 1 1404 0 discriminator 2 + 3605 0040 3D4B ldr r3, .L282 + 3606 .LVL308: + 3607 0042 E362 str r3, [r4, #44] + 3608 .LVL309: +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3609 .loc 1 1405 0 discriminator 2 + 3610 0044 3D4B ldr r3, .L282+4 + 3611 0046 6363 str r3, [r4, #52] +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3612 .loc 1 1407 0 discriminator 2 + 3613 0048 638D ldrh r3, [r4, #42] + 3614 004a 9BB2 uxth r3, r3 + 3615 004c FF2B cmp r3, #255 + 3616 004e 25D9 bls .L267 + ARM GAS /tmp/ccpuPECZ.s page 158 + + +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3617 .loc 1 1409 0 + 3618 0050 FF23 movs r3, #255 + 3619 0052 2385 strh r3, [r4, #40] + 3620 .LVL310: +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3621 .loc 1 1410 0 + 3622 0054 8026 movs r6, #128 + 3623 0056 7604 lsls r6, r6, #17 + 3624 .LVL311: + 3625 .L268: +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3626 .loc 1 1418 0 + 3627 0058 238D ldrh r3, [r4, #40] + 3628 005a 002B cmp r3, #0 + 3629 005c 23D1 bne .L279 +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3630 .loc 1 1455 0 + 3631 005e 3849 ldr r1, .L282+8 + 3632 .LVL312: + 3633 0060 6163 str r1, [r4, #52] +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3634 .loc 1 1459 0 + 3635 0062 DBB2 uxtb r3, r3 + 3636 .LVL313: + 3637 .LBB200: + 3638 .LBB201: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 3639 .loc 1 4713 0 + 3640 0064 5168 ldr r1, [r2, #4] + 3641 0066 3748 ldr r0, .L282+12 + 3642 0068 0140 ands r1, r0 + 3643 006a AD05 lsls r5, r5, #22 + 3644 .LVL314: + 3645 006c AD0D lsrs r5, r5, #22 + 3646 006e 1B04 lsls r3, r3, #16 + 3647 .LVL315: + 3648 0070 1D43 orrs r5, r3 + 3649 0072 354B ldr r3, .L282+16 + 3650 0074 1D43 orrs r5, r3 + 3651 0076 0D43 orrs r5, r1 + 3652 0078 5560 str r5, [r2, #4] + 3653 .LVL316: + 3654 .LBE201: + 3655 .LBE200: +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3656 .loc 1 1462 0 + 3657 007a 4023 movs r3, #64 + 3658 007c 0022 movs r2, #0 + 3659 007e E254 strb r2, [r4, r3] + 3660 .LVL317: + 3661 .LBB202: + 3662 .LBB203: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3663 .loc 1 4728 0 + 3664 0080 636B ldr r3, [r4, #52] + 3665 0082 2E4A ldr r2, .L282+4 + ARM GAS /tmp/ccpuPECZ.s page 159 + + + 3666 0084 9342 cmp r3, r2 + 3667 0086 4FD0 beq .L277 + 3668 0088 304A ldr r2, .L282+20 + 3669 008a 9342 cmp r3, r2 + 3670 008c 4AD0 beq .L280 + 3671 008e F221 movs r1, #242 + 3672 .L271: + 3673 .LVL318: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3674 .loc 1 4785 0 + 3675 0090 2268 ldr r2, [r4] + 3676 0092 1368 ldr r3, [r2] + 3677 0094 0B43 orrs r3, r1 + 3678 0096 1360 str r3, [r2] + 3679 .LBE203: + 3680 .LBE202: +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3681 .loc 1 1473 0 + 3682 0098 0020 movs r0, #0 + 3683 009a 48E0 b .L266 + 3684 .LVL319: + 3685 .L267: +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3686 .loc 1 1414 0 + 3687 009c 638D ldrh r3, [r4, #42] + 3688 009e 2385 strh r3, [r4, #40] + 3689 .LVL320: +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3690 .loc 1 1415 0 + 3691 00a0 8026 movs r6, #128 + 3692 00a2 B604 lsls r6, r6, #18 + 3693 00a4 D8E7 b .L268 + 3694 .LVL321: + 3695 .L279: +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3696 .loc 1 1421 0 + 3697 00a6 A36B ldr r3, [r4, #56] + 3698 00a8 294A ldr r2, .L282+24 + 3699 00aa DA62 str r2, [r3, #44] +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3700 .loc 1 1424 0 + 3701 00ac A36B ldr r3, [r4, #56] + 3702 00ae 294A ldr r2, .L282+28 + 3703 00b0 5A63 str r2, [r3, #52] +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3704 .loc 1 1427 0 + 3705 00b2 A36B ldr r3, [r4, #56] + 3706 00b4 0027 movs r7, #0 + 3707 00b6 1F63 str r7, [r3, #48] +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3708 .loc 1 1428 0 + 3709 00b8 A36B ldr r3, [r4, #56] + 3710 00ba 9F63 str r7, [r3, #56] +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3711 .loc 1 1431 0 + 3712 00bc 2268 ldr r2, [r4] + 3713 00be 2832 adds r2, r2, #40 + ARM GAS /tmp/ccpuPECZ.s page 160 + + + 3714 00c0 238D ldrh r3, [r4, #40] + 3715 00c2 A06B ldr r0, [r4, #56] + 3716 00c4 FFF7FEFF bl HAL_DMA_Start_IT + 3717 .LVL322: +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3718 .loc 1 1435 0 + 3719 00c8 238D ldrh r3, [r4, #40] + 3720 00ca DBB2 uxtb r3, r3 + 3721 .LVL323: + 3722 .LBB205: + 3723 .LBB206: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 3724 .loc 1 4713 0 + 3725 00cc 2168 ldr r1, [r4] + 3726 00ce 4868 ldr r0, [r1, #4] + 3727 00d0 1C4A ldr r2, .L282+12 + 3728 00d2 0240 ands r2, r0 + 3729 00d4 AD05 lsls r5, r5, #22 + 3730 .LVL324: + 3731 00d6 AD0D lsrs r5, r5, #22 + 3732 00d8 1B04 lsls r3, r3, #16 + 3733 .LVL325: + 3734 00da 1D43 orrs r5, r3 + 3735 00dc 2E43 orrs r6, r5 + 3736 .LVL326: + 3737 00de 1E4D ldr r5, .L282+32 + 3738 00e0 2E43 orrs r6, r5 + 3739 00e2 1643 orrs r6, r2 + 3740 00e4 4E60 str r6, [r1, #4] + 3741 .LVL327: + 3742 .LBE206: + 3743 .LBE205: +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3744 .loc 1 1438 0 + 3745 00e6 638D ldrh r3, [r4, #42] + 3746 00e8 228D ldrh r2, [r4, #40] + 3747 00ea 9B1A subs r3, r3, r2 + 3748 00ec 9BB2 uxth r3, r3 + 3749 00ee 6385 strh r3, [r4, #42] +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3750 .loc 1 1441 0 + 3751 00f0 4023 movs r3, #64 + 3752 00f2 E754 strb r7, [r4, r3] + 3753 .LVL328: + 3754 .LBB207: + 3755 .LBB208: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3756 .loc 1 4728 0 + 3757 00f4 636B ldr r3, [r4, #52] + 3758 00f6 114A ldr r2, .L282+4 + 3759 00f8 9342 cmp r3, r2 + 3760 00fa 11D0 beq .L275 + 3761 00fc 134A ldr r2, .L282+20 + 3762 00fe 9342 cmp r3, r2 + 3763 0100 0CD0 beq .L281 + 3764 0102 F221 movs r1, #242 + 3765 .L270: + ARM GAS /tmp/ccpuPECZ.s page 161 + + + 3766 .LVL329: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3767 .loc 1 4785 0 + 3768 0104 2268 ldr r2, [r4] + 3769 0106 1368 ldr r3, [r2] + 3770 0108 0B43 orrs r3, r1 + 3771 010a 1360 str r3, [r2] + 3772 .LVL330: + 3773 .LBE208: + 3774 .LBE207: +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3775 .loc 1 1450 0 + 3776 010c 2268 ldr r2, [r4] + 3777 010e 1168 ldr r1, [r2] + 3778 0110 8023 movs r3, #128 + 3779 0112 DB01 lsls r3, r3, #7 + 3780 0114 0B43 orrs r3, r1 + 3781 0116 1360 str r3, [r2] +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3782 .loc 1 1473 0 + 3783 0118 0020 movs r0, #0 + 3784 011a 08E0 b .L266 + 3785 .LVL331: + 3786 .L281: + 3787 .LBB210: + 3788 .LBB209: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3789 .loc 1 4728 0 + 3790 011c 9021 movs r1, #144 + 3791 011e F1E7 b .L270 + 3792 .L275: + 3793 0120 9021 movs r1, #144 + 3794 0122 EFE7 b .L270 + 3795 .LVL332: + 3796 .L280: + 3797 .LBE209: + 3798 .LBE210: + 3799 .LBB211: + 3800 .LBB204: + 3801 0124 0021 movs r1, #0 + 3802 0126 B3E7 b .L271 + 3803 .L277: + 3804 0128 0021 movs r1, #0 + 3805 012a B1E7 b .L271 + 3806 .LVL333: + 3807 .L272: + 3808 .LBE204: + 3809 .LBE211: +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3810 .loc 1 1477 0 + 3811 012c 0220 movs r0, #2 + 3812 .LVL334: + 3813 .L266: +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3814 .loc 1 1479 0 + 3815 @ sp needed + 3816 .LVL335: + ARM GAS /tmp/ccpuPECZ.s page 162 + + + 3817 012e F8BD pop {r3, r4, r5, r6, r7, pc} + 3818 .LVL336: + 3819 .L273: +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3820 .loc 1 1391 0 + 3821 0130 0220 movs r0, #2 + 3822 0132 FCE7 b .L266 + 3823 .L274: +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3824 .loc 1 1395 0 + 3825 0134 0220 movs r0, #2 + 3826 0136 FAE7 b .L266 + 3827 .L283: + 3828 .align 2 + 3829 .L282: + 3830 0138 0000FFFF .word -65536 + 3831 013c 00000000 .word I2C_Master_ISR_DMA + 3832 0140 00000000 .word I2C_Master_ISR_IT + 3833 0144 009800FC .word -67069952 + 3834 0148 00200082 .word -2113921024 + 3835 014c 00000000 .word I2C_Slave_ISR_DMA + 3836 0150 00000000 .word I2C_DMAMasterTransmitCplt + 3837 0154 00000000 .word I2C_DMAError + 3838 0158 00200080 .word -2147475456 + 3839 .cfi_endproc + 3840 .LFE51: + 3842 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 3843 .align 1 + 3844 .global HAL_I2C_Master_Receive_DMA + 3845 .syntax unified + 3846 .code 16 + 3847 .thumb_func + 3848 .fpu softvfp + 3850 HAL_I2C_Master_Receive_DMA: + 3851 .LFB52: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 3852 .loc 1 1492 0 + 3853 .cfi_startproc + 3854 @ args = 0, pretend = 0, frame = 0 + 3855 @ frame_needed = 0, uses_anonymous_args = 0 + 3856 .LVL337: + 3857 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3858 .LCFI27: + 3859 .cfi_def_cfa_offset 24 + 3860 .cfi_offset 3, -24 + 3861 .cfi_offset 4, -20 + 3862 .cfi_offset 5, -16 + 3863 .cfi_offset 6, -12 + 3864 .cfi_offset 7, -8 + 3865 .cfi_offset 14, -4 + 3866 0002 0400 movs r4, r0 + 3867 0004 0D00 movs r5, r1 + 3868 .LVL338: +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3869 .loc 1 1495 0 + 3870 0006 4121 movs r1, #65 + 3871 .LVL339: + ARM GAS /tmp/ccpuPECZ.s page 163 + + + 3872 0008 415C ldrb r1, [r0, r1] + 3873 000a 2029 cmp r1, #32 + 3874 000c 00D0 beq .LCB4139 + 3875 000e 8CE0 b .L291 @long jump + 3876 .LCB4139: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3877 .loc 1 1497 0 + 3878 0010 0168 ldr r1, [r0] + 3879 0012 8869 ldr r0, [r1, #24] + 3880 .LVL340: + 3881 0014 0004 lsls r0, r0, #16 + 3882 0016 00D5 bpl .LCB4146 + 3883 0018 89E0 b .L292 @long jump + 3884 .LCB4146: +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3885 .loc 1 1503 0 + 3886 001a 4020 movs r0, #64 + 3887 001c 205C ldrb r0, [r4, r0] + 3888 001e 0128 cmp r0, #1 + 3889 0020 00D1 bne .LCB4150 + 3890 0022 86E0 b .L293 @long jump + 3891 .LCB4150: +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3892 .loc 1 1503 0 is_stmt 0 discriminator 2 + 3893 0024 4020 movs r0, #64 + 3894 0026 0126 movs r6, #1 + 3895 0028 2654 strb r6, [r4, r0] +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3896 .loc 1 1505 0 is_stmt 1 discriminator 2 + 3897 002a 0130 adds r0, r0, #1 + 3898 002c 2136 adds r6, r6, #33 + 3899 002e 2654 strb r6, [r4, r0] +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3900 .loc 1 1506 0 discriminator 2 + 3901 0030 0130 adds r0, r0, #1 + 3902 0032 123E subs r6, r6, #18 + 3903 0034 2654 strb r6, [r4, r0] +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3904 .loc 1 1507 0 discriminator 2 + 3905 0036 0020 movs r0, #0 + 3906 0038 6064 str r0, [r4, #68] +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3907 .loc 1 1510 0 discriminator 2 + 3908 003a 6262 str r2, [r4, #36] +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3909 .loc 1 1511 0 discriminator 2 + 3910 003c 6385 strh r3, [r4, #42] +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3911 .loc 1 1512 0 discriminator 2 + 3912 003e 3E4B ldr r3, .L301 + 3913 .LVL341: + 3914 0040 E362 str r3, [r4, #44] + 3915 .LVL342: +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3916 .loc 1 1513 0 discriminator 2 + 3917 0042 3E4B ldr r3, .L301+4 + 3918 0044 6363 str r3, [r4, #52] + ARM GAS /tmp/ccpuPECZ.s page 164 + + +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3919 .loc 1 1515 0 discriminator 2 + 3920 0046 638D ldrh r3, [r4, #42] + 3921 0048 9BB2 uxth r3, r3 + 3922 004a FF2B cmp r3, #255 + 3923 004c 25D9 bls .L286 +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3924 .loc 1 1517 0 + 3925 004e FF23 movs r3, #255 + 3926 0050 2385 strh r3, [r4, #40] + 3927 .LVL343: +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3928 .loc 1 1518 0 + 3929 0052 8026 movs r6, #128 + 3930 0054 7604 lsls r6, r6, #17 + 3931 .LVL344: + 3932 .L287: +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 3933 .loc 1 1526 0 + 3934 0056 238D ldrh r3, [r4, #40] + 3935 0058 002B cmp r3, #0 + 3936 005a 23D1 bne .L298 +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3937 .loc 1 1563 0 + 3938 005c 384A ldr r2, .L301+8 + 3939 .LVL345: + 3940 005e 6263 str r2, [r4, #52] +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3941 .loc 1 1567 0 + 3942 0060 DBB2 uxtb r3, r3 + 3943 .LVL346: + 3944 .LBB212: + 3945 .LBB213: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 3946 .loc 1 4713 0 + 3947 0062 4A68 ldr r2, [r1, #4] + 3948 0064 3748 ldr r0, .L301+12 + 3949 0066 0240 ands r2, r0 + 3950 0068 AD05 lsls r5, r5, #22 + 3951 .LVL347: + 3952 006a AD0D lsrs r5, r5, #22 + 3953 006c 1B04 lsls r3, r3, #16 + 3954 .LVL348: + 3955 006e 1D43 orrs r5, r3 + 3956 0070 354B ldr r3, .L301+16 + 3957 0072 1D43 orrs r5, r3 + 3958 0074 1543 orrs r5, r2 + 3959 0076 4D60 str r5, [r1, #4] + 3960 .LVL349: + 3961 .LBE213: + 3962 .LBE212: +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3963 .loc 1 1570 0 + 3964 0078 4023 movs r3, #64 + 3965 007a 0022 movs r2, #0 + 3966 007c E254 strb r2, [r4, r3] + 3967 .LVL350: + ARM GAS /tmp/ccpuPECZ.s page 165 + + + 3968 .LBB214: + 3969 .LBB215: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 3970 .loc 1 4728 0 + 3971 007e 636B ldr r3, [r4, #52] + 3972 0080 2E4A ldr r2, .L301+4 + 3973 0082 9342 cmp r3, r2 + 3974 0084 4FD0 beq .L296 + 3975 0086 314A ldr r2, .L301+20 + 3976 0088 9342 cmp r3, r2 + 3977 008a 4AD0 beq .L299 + 3978 008c F221 movs r1, #242 + 3979 .L290: + 3980 .LVL351: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 3981 .loc 1 4785 0 + 3982 008e 2268 ldr r2, [r4] + 3983 0090 1368 ldr r3, [r2] + 3984 0092 0B43 orrs r3, r1 + 3985 0094 1360 str r3, [r2] + 3986 .LBE215: + 3987 .LBE214: +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3988 .loc 1 1580 0 + 3989 0096 0020 movs r0, #0 + 3990 0098 48E0 b .L285 + 3991 .LVL352: + 3992 .L286: +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3993 .loc 1 1522 0 + 3994 009a 638D ldrh r3, [r4, #42] + 3995 009c 2385 strh r3, [r4, #40] + 3996 .LVL353: +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 3997 .loc 1 1523 0 + 3998 009e 8026 movs r6, #128 + 3999 00a0 B604 lsls r6, r6, #18 + 4000 00a2 D8E7 b .L287 + 4001 .LVL354: + 4002 .L298: +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4003 .loc 1 1529 0 + 4004 00a4 E36B ldr r3, [r4, #60] + 4005 00a6 2A49 ldr r1, .L301+24 + 4006 00a8 D962 str r1, [r3, #44] +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4007 .loc 1 1532 0 + 4008 00aa E36B ldr r3, [r4, #60] + 4009 00ac 2949 ldr r1, .L301+28 + 4010 00ae 5963 str r1, [r3, #52] +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4011 .loc 1 1535 0 + 4012 00b0 E36B ldr r3, [r4, #60] + 4013 00b2 0027 movs r7, #0 + 4014 00b4 1F63 str r7, [r3, #48] +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4015 .loc 1 1536 0 + ARM GAS /tmp/ccpuPECZ.s page 166 + + + 4016 00b6 E36B ldr r3, [r4, #60] + 4017 00b8 9F63 str r7, [r3, #56] +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4018 .loc 1 1539 0 + 4019 00ba 2168 ldr r1, [r4] + 4020 00bc 2431 adds r1, r1, #36 + 4021 00be 238D ldrh r3, [r4, #40] + 4022 00c0 E06B ldr r0, [r4, #60] + 4023 00c2 FFF7FEFF bl HAL_DMA_Start_IT + 4024 .LVL355: +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4025 .loc 1 1543 0 + 4026 00c6 238D ldrh r3, [r4, #40] + 4027 00c8 DBB2 uxtb r3, r3 + 4028 .LVL356: + 4029 .LBB217: + 4030 .LBB218: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 4031 .loc 1 4713 0 + 4032 00ca 2168 ldr r1, [r4] + 4033 00cc 4868 ldr r0, [r1, #4] + 4034 00ce 1D4A ldr r2, .L301+12 + 4035 00d0 0240 ands r2, r0 + 4036 00d2 AD05 lsls r5, r5, #22 + 4037 .LVL357: + 4038 00d4 AD0D lsrs r5, r5, #22 + 4039 00d6 1B04 lsls r3, r3, #16 + 4040 .LVL358: + 4041 00d8 1D43 orrs r5, r3 + 4042 00da 2E43 orrs r6, r5 + 4043 .LVL359: + 4044 00dc 1E4D ldr r5, .L301+32 + 4045 00de 2E43 orrs r6, r5 + 4046 00e0 1643 orrs r6, r2 + 4047 00e2 4E60 str r6, [r1, #4] + 4048 .LVL360: + 4049 .LBE218: + 4050 .LBE217: +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4051 .loc 1 1546 0 + 4052 00e4 638D ldrh r3, [r4, #42] + 4053 00e6 228D ldrh r2, [r4, #40] + 4054 00e8 9B1A subs r3, r3, r2 + 4055 00ea 9BB2 uxth r3, r3 + 4056 00ec 6385 strh r3, [r4, #42] +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4057 .loc 1 1549 0 + 4058 00ee 4023 movs r3, #64 + 4059 00f0 E754 strb r7, [r4, r3] + 4060 .LVL361: + 4061 .LBB219: + 4062 .LBB220: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 4063 .loc 1 4728 0 + 4064 00f2 636B ldr r3, [r4, #52] + 4065 00f4 114A ldr r2, .L301+4 + 4066 00f6 9342 cmp r3, r2 + ARM GAS /tmp/ccpuPECZ.s page 167 + + + 4067 00f8 11D0 beq .L294 + 4068 00fa 144A ldr r2, .L301+20 + 4069 00fc 9342 cmp r3, r2 + 4070 00fe 0CD0 beq .L300 + 4071 0100 F221 movs r1, #242 + 4072 .L289: + 4073 .LVL362: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4074 .loc 1 4785 0 + 4075 0102 2268 ldr r2, [r4] + 4076 0104 1368 ldr r3, [r2] + 4077 0106 0B43 orrs r3, r1 + 4078 0108 1360 str r3, [r2] + 4079 .LVL363: + 4080 .LBE220: + 4081 .LBE219: +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4082 .loc 1 1558 0 + 4083 010a 2268 ldr r2, [r4] + 4084 010c 1168 ldr r1, [r2] + 4085 010e 8023 movs r3, #128 + 4086 0110 1B02 lsls r3, r3, #8 + 4087 0112 0B43 orrs r3, r1 + 4088 0114 1360 str r3, [r2] +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4089 .loc 1 1580 0 + 4090 0116 0020 movs r0, #0 + 4091 0118 08E0 b .L285 + 4092 .LVL364: + 4093 .L300: + 4094 .LBB222: + 4095 .LBB221: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 4096 .loc 1 4728 0 + 4097 011a 9021 movs r1, #144 + 4098 011c F1E7 b .L289 + 4099 .L294: + 4100 011e 9021 movs r1, #144 + 4101 0120 EFE7 b .L289 + 4102 .LVL365: + 4103 .L299: + 4104 .LBE221: + 4105 .LBE222: + 4106 .LBB223: + 4107 .LBB216: + 4108 0122 0021 movs r1, #0 + 4109 0124 B3E7 b .L290 + 4110 .L296: + 4111 0126 0021 movs r1, #0 + 4112 0128 B1E7 b .L290 + 4113 .LVL366: + 4114 .L291: + 4115 .LBE216: + 4116 .LBE223: +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4117 .loc 1 1584 0 + 4118 012a 0220 movs r0, #2 + ARM GAS /tmp/ccpuPECZ.s page 168 + + + 4119 .LVL367: + 4120 .L285: +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4121 .loc 1 1586 0 + 4122 @ sp needed + 4123 .LVL368: + 4124 012c F8BD pop {r3, r4, r5, r6, r7, pc} + 4125 .LVL369: + 4126 .L292: +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4127 .loc 1 1499 0 + 4128 012e 0220 movs r0, #2 + 4129 0130 FCE7 b .L285 + 4130 .L293: +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4131 .loc 1 1503 0 + 4132 0132 0220 movs r0, #2 + 4133 0134 FAE7 b .L285 + 4134 .L302: + 4135 0136 C046 .align 2 + 4136 .L301: + 4137 0138 0000FFFF .word -65536 + 4138 013c 00000000 .word I2C_Master_ISR_DMA + 4139 0140 00000000 .word I2C_Master_ISR_IT + 4140 0144 009800FC .word -67069952 + 4141 0148 00240082 .word -2113920000 + 4142 014c 00000000 .word I2C_Slave_ISR_DMA + 4143 0150 00000000 .word I2C_DMAMasterReceiveCplt + 4144 0154 00000000 .word I2C_DMAError + 4145 0158 00240080 .word -2147474432 + 4146 .cfi_endproc + 4147 .LFE52: + 4149 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 4150 .align 1 + 4151 .global HAL_I2C_Slave_Transmit_DMA + 4152 .syntax unified + 4153 .code 16 + 4154 .thumb_func + 4155 .fpu softvfp + 4157 HAL_I2C_Slave_Transmit_DMA: + 4158 .LFB53: +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 4159 .loc 1 1597 0 + 4160 .cfi_startproc + 4161 @ args = 0, pretend = 0, frame = 0 + 4162 @ frame_needed = 0, uses_anonymous_args = 0 + 4163 .LVL370: + 4164 0000 70B5 push {r4, r5, r6, lr} + 4165 .LCFI28: + 4166 .cfi_def_cfa_offset 16 + 4167 .cfi_offset 4, -16 + 4168 .cfi_offset 5, -12 + 4169 .cfi_offset 6, -8 + 4170 .cfi_offset 14, -4 + 4171 0002 0400 movs r4, r0 +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4172 .loc 1 1598 0 + ARM GAS /tmp/ccpuPECZ.s page 169 + + + 4173 0004 4123 movs r3, #65 + 4174 0006 C35C ldrb r3, [r0, r3] + 4175 0008 202B cmp r3, #32 + 4176 000a 3DD1 bne .L305 +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4177 .loc 1 1600 0 + 4178 000c 0029 cmp r1, #0 + 4179 000e 3DD0 beq .L306 +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4180 .loc 1 1600 0 is_stmt 0 discriminator 1 + 4181 0010 002A cmp r2, #0 + 4182 0012 3DD0 beq .L307 +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4183 .loc 1 1605 0 is_stmt 1 + 4184 0014 2033 adds r3, r3, #32 + 4185 0016 C35C ldrb r3, [r0, r3] + 4186 0018 012B cmp r3, #1 + 4187 001a 3BD0 beq .L308 +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4188 .loc 1 1605 0 is_stmt 0 discriminator 2 + 4189 001c 4026 movs r6, #64 + 4190 001e 0123 movs r3, #1 + 4191 0020 8355 strb r3, [r0, r6] +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4192 .loc 1 1607 0 is_stmt 1 discriminator 2 + 4193 0022 4033 adds r3, r3, #64 + 4194 0024 2120 movs r0, #33 + 4195 .LVL371: + 4196 0026 E054 strb r0, [r4, r3] +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4197 .loc 1 1608 0 discriminator 2 + 4198 0028 0133 adds r3, r3, #1 + 4199 002a 0138 subs r0, r0, #1 + 4200 002c E054 strb r0, [r4, r3] +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4201 .loc 1 1609 0 discriminator 2 + 4202 002e 0025 movs r5, #0 + 4203 0030 6564 str r5, [r4, #68] +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4204 .loc 1 1612 0 discriminator 2 + 4205 0032 6162 str r1, [r4, #36] +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4206 .loc 1 1613 0 discriminator 2 + 4207 0034 6285 strh r2, [r4, #42] +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4208 .loc 1 1614 0 discriminator 2 + 4209 0036 638D ldrh r3, [r4, #42] + 4210 0038 2385 strh r3, [r4, #40] +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4211 .loc 1 1615 0 discriminator 2 + 4212 003a 174B ldr r3, .L309 + 4213 003c E362 str r3, [r4, #44] +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4214 .loc 1 1616 0 discriminator 2 + 4215 003e 174B ldr r3, .L309+4 + 4216 0040 6363 str r3, [r4, #52] +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 170 + + + 4217 .loc 1 1619 0 discriminator 2 + 4218 0042 A36B ldr r3, [r4, #56] + 4219 0044 164A ldr r2, .L309+8 + 4220 .LVL372: + 4221 0046 DA62 str r2, [r3, #44] +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4222 .loc 1 1622 0 discriminator 2 + 4223 0048 A36B ldr r3, [r4, #56] + 4224 004a 164A ldr r2, .L309+12 + 4225 004c 5A63 str r2, [r3, #52] +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4226 .loc 1 1625 0 discriminator 2 + 4227 004e A36B ldr r3, [r4, #56] + 4228 0050 1D63 str r5, [r3, #48] +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4229 .loc 1 1626 0 discriminator 2 + 4230 0052 A36B ldr r3, [r4, #56] + 4231 0054 9D63 str r5, [r3, #56] +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4232 .loc 1 1629 0 discriminator 2 + 4233 0056 2268 ldr r2, [r4] + 4234 0058 2832 adds r2, r2, #40 + 4235 005a 238D ldrh r3, [r4, #40] + 4236 005c A06B ldr r0, [r4, #56] + 4237 005e FFF7FEFF bl HAL_DMA_Start_IT + 4238 .LVL373: +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4239 .loc 1 1632 0 discriminator 2 + 4240 0062 2268 ldr r2, [r4] + 4241 0064 5368 ldr r3, [r2, #4] + 4242 0066 1049 ldr r1, .L309+16 + 4243 0068 0B40 ands r3, r1 + 4244 006a 5360 str r3, [r2, #4] +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4245 .loc 1 1635 0 discriminator 2 + 4246 006c A555 strb r5, [r4, r6] + 4247 .LVL374: + 4248 .LBB224: + 4249 .LBB225: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4250 .loc 1 4785 0 discriminator 2 + 4251 006e 2268 ldr r2, [r4] + 4252 0070 1368 ldr r3, [r2] + 4253 0072 B821 movs r1, #184 + 4254 0074 0B43 orrs r3, r1 + 4255 0076 1360 str r3, [r2] + 4256 .LVL375: + 4257 .LBE225: + 4258 .LBE224: +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4259 .loc 1 1644 0 discriminator 2 + 4260 0078 2268 ldr r2, [r4] + 4261 007a 1168 ldr r1, [r2] + 4262 007c 8023 movs r3, #128 + 4263 007e DB01 lsls r3, r3, #7 + 4264 0080 0B43 orrs r3, r1 + 4265 0082 1360 str r3, [r2] + ARM GAS /tmp/ccpuPECZ.s page 171 + + +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4266 .loc 1 1646 0 discriminator 2 + 4267 0084 0020 movs r0, #0 + 4268 0086 00E0 b .L304 + 4269 .LVL376: + 4270 .L305: +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4271 .loc 1 1650 0 + 4272 0088 0220 movs r0, #2 + 4273 .LVL377: + 4274 .L304: +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4275 .loc 1 1652 0 + 4276 @ sp needed + 4277 .LVL378: + 4278 008a 70BD pop {r4, r5, r6, pc} + 4279 .LVL379: + 4280 .L306: +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4281 .loc 1 1602 0 + 4282 008c 0120 movs r0, #1 + 4283 .LVL380: + 4284 008e FCE7 b .L304 + 4285 .LVL381: + 4286 .L307: + 4287 0090 0120 movs r0, #1 + 4288 .LVL382: + 4289 0092 FAE7 b .L304 + 4290 .LVL383: + 4291 .L308: +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4292 .loc 1 1605 0 + 4293 0094 0220 movs r0, #2 + 4294 .LVL384: + 4295 0096 F8E7 b .L304 + 4296 .L310: + 4297 .align 2 + 4298 .L309: + 4299 0098 0000FFFF .word -65536 + 4300 009c 00000000 .word I2C_Slave_ISR_DMA + 4301 00a0 00000000 .word I2C_DMASlaveTransmitCplt + 4302 00a4 00000000 .word I2C_DMAError + 4303 00a8 FF7FFFFF .word -32769 + 4304 .cfi_endproc + 4305 .LFE53: + 4307 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 4308 .align 1 + 4309 .global HAL_I2C_Slave_Receive_DMA + 4310 .syntax unified + 4311 .code 16 + 4312 .thumb_func + 4313 .fpu softvfp + 4315 HAL_I2C_Slave_Receive_DMA: + 4316 .LFB54: +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 4317 .loc 1 1663 0 + 4318 .cfi_startproc + ARM GAS /tmp/ccpuPECZ.s page 172 + + + 4319 @ args = 0, pretend = 0, frame = 0 + 4320 @ frame_needed = 0, uses_anonymous_args = 0 + 4321 .LVL385: + 4322 0000 70B5 push {r4, r5, r6, lr} + 4323 .LCFI29: + 4324 .cfi_def_cfa_offset 16 + 4325 .cfi_offset 4, -16 + 4326 .cfi_offset 5, -12 + 4327 .cfi_offset 6, -8 + 4328 .cfi_offset 14, -4 + 4329 0002 0400 movs r4, r0 +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4330 .loc 1 1664 0 + 4331 0004 4123 movs r3, #65 + 4332 0006 C35C ldrb r3, [r0, r3] + 4333 0008 202B cmp r3, #32 + 4334 000a 3FD1 bne .L313 +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4335 .loc 1 1666 0 + 4336 000c 0029 cmp r1, #0 + 4337 000e 3FD0 beq .L314 +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4338 .loc 1 1666 0 is_stmt 0 discriminator 1 + 4339 0010 002A cmp r2, #0 + 4340 0012 3FD0 beq .L315 +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4341 .loc 1 1671 0 is_stmt 1 + 4342 0014 2033 adds r3, r3, #32 + 4343 0016 C35C ldrb r3, [r0, r3] + 4344 0018 012B cmp r3, #1 + 4345 001a 3DD0 beq .L316 +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4346 .loc 1 1671 0 is_stmt 0 discriminator 2 + 4347 001c 4026 movs r6, #64 + 4348 001e 0123 movs r3, #1 + 4349 0020 8355 strb r3, [r0, r6] +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4350 .loc 1 1673 0 is_stmt 1 discriminator 2 + 4351 0022 4033 adds r3, r3, #64 + 4352 0024 2220 movs r0, #34 + 4353 .LVL386: + 4354 0026 E054 strb r0, [r4, r3] +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4355 .loc 1 1674 0 discriminator 2 + 4356 0028 0133 adds r3, r3, #1 + 4357 002a 0238 subs r0, r0, #2 + 4358 002c E054 strb r0, [r4, r3] +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4359 .loc 1 1675 0 discriminator 2 + 4360 002e 0025 movs r5, #0 + 4361 0030 6564 str r5, [r4, #68] +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4362 .loc 1 1678 0 discriminator 2 + 4363 0032 6162 str r1, [r4, #36] +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4364 .loc 1 1679 0 discriminator 2 + 4365 0034 6285 strh r2, [r4, #42] + ARM GAS /tmp/ccpuPECZ.s page 173 + + +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4366 .loc 1 1680 0 discriminator 2 + 4367 0036 638D ldrh r3, [r4, #42] + 4368 0038 2385 strh r3, [r4, #40] +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4369 .loc 1 1681 0 discriminator 2 + 4370 003a 184B ldr r3, .L317 + 4371 003c E362 str r3, [r4, #44] +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4372 .loc 1 1682 0 discriminator 2 + 4373 003e 184B ldr r3, .L317+4 + 4374 0040 6363 str r3, [r4, #52] +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4375 .loc 1 1685 0 discriminator 2 + 4376 0042 E36B ldr r3, [r4, #60] + 4377 0044 174A ldr r2, .L317+8 + 4378 .LVL387: + 4379 0046 DA62 str r2, [r3, #44] +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4380 .loc 1 1688 0 discriminator 2 + 4381 0048 E36B ldr r3, [r4, #60] + 4382 004a 174A ldr r2, .L317+12 + 4383 004c 5A63 str r2, [r3, #52] +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4384 .loc 1 1691 0 discriminator 2 + 4385 004e E36B ldr r3, [r4, #60] + 4386 0050 1D63 str r5, [r3, #48] +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4387 .loc 1 1692 0 discriminator 2 + 4388 0052 E36B ldr r3, [r4, #60] + 4389 0054 9D63 str r5, [r3, #56] +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4390 .loc 1 1695 0 discriminator 2 + 4391 0056 2068 ldr r0, [r4] + 4392 0058 2430 adds r0, r0, #36 + 4393 005a 238D ldrh r3, [r4, #40] + 4394 005c 0A00 movs r2, r1 + 4395 005e 0100 movs r1, r0 + 4396 .LVL388: + 4397 0060 E06B ldr r0, [r4, #60] + 4398 0062 FFF7FEFF bl HAL_DMA_Start_IT + 4399 .LVL389: +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4400 .loc 1 1698 0 discriminator 2 + 4401 0066 2268 ldr r2, [r4] + 4402 0068 5368 ldr r3, [r2, #4] + 4403 006a 1049 ldr r1, .L317+16 + 4404 006c 0B40 ands r3, r1 + 4405 006e 5360 str r3, [r2, #4] +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4406 .loc 1 1701 0 discriminator 2 + 4407 0070 A555 strb r5, [r4, r6] + 4408 .LVL390: + 4409 .LBB226: + 4410 .LBB227: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4411 .loc 1 4785 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 174 + + + 4412 0072 2268 ldr r2, [r4] + 4413 0074 1368 ldr r3, [r2] + 4414 0076 B821 movs r1, #184 + 4415 0078 0B43 orrs r3, r1 + 4416 007a 1360 str r3, [r2] + 4417 .LVL391: + 4418 .LBE227: + 4419 .LBE226: +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4420 .loc 1 1710 0 discriminator 2 + 4421 007c 2268 ldr r2, [r4] + 4422 007e 1168 ldr r1, [r2] + 4423 0080 8023 movs r3, #128 + 4424 0082 1B02 lsls r3, r3, #8 + 4425 0084 0B43 orrs r3, r1 + 4426 0086 1360 str r3, [r2] +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4427 .loc 1 1712 0 discriminator 2 + 4428 0088 0020 movs r0, #0 + 4429 008a 00E0 b .L312 + 4430 .LVL392: + 4431 .L313: +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4432 .loc 1 1716 0 + 4433 008c 0220 movs r0, #2 + 4434 .LVL393: + 4435 .L312: +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 4436 .loc 1 1718 0 + 4437 @ sp needed + 4438 .LVL394: + 4439 008e 70BD pop {r4, r5, r6, pc} + 4440 .LVL395: + 4441 .L314: +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4442 .loc 1 1668 0 + 4443 0090 0120 movs r0, #1 + 4444 .LVL396: + 4445 0092 FCE7 b .L312 + 4446 .LVL397: + 4447 .L315: + 4448 0094 0120 movs r0, #1 + 4449 .LVL398: + 4450 0096 FAE7 b .L312 + 4451 .LVL399: + 4452 .L316: +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4453 .loc 1 1671 0 + 4454 0098 0220 movs r0, #2 + 4455 .LVL400: + 4456 009a F8E7 b .L312 + 4457 .L318: + 4458 .align 2 + 4459 .L317: + 4460 009c 0000FFFF .word -65536 + 4461 00a0 00000000 .word I2C_Slave_ISR_DMA + 4462 00a4 00000000 .word I2C_DMASlaveReceiveCplt + ARM GAS /tmp/ccpuPECZ.s page 175 + + + 4463 00a8 00000000 .word I2C_DMAError + 4464 00ac FF7FFFFF .word -32769 + 4465 .cfi_endproc + 4466 .LFE54: + 4468 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 4469 .align 1 + 4470 .global HAL_I2C_Mem_Write + 4471 .syntax unified + 4472 .code 16 + 4473 .thumb_func + 4474 .fpu softvfp + 4476 HAL_I2C_Mem_Write: + 4477 .LFB55: +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 4478 .loc 1 1733 0 + 4479 .cfi_startproc + 4480 @ args = 12, pretend = 0, frame = 16 + 4481 @ frame_needed = 0, uses_anonymous_args = 0 + 4482 .LVL401: + 4483 0000 F0B5 push {r4, r5, r6, r7, lr} + 4484 .LCFI30: + 4485 .cfi_def_cfa_offset 20 + 4486 .cfi_offset 4, -20 + 4487 .cfi_offset 5, -16 + 4488 .cfi_offset 6, -12 + 4489 .cfi_offset 7, -8 + 4490 .cfi_offset 14, -4 + 4491 0002 87B0 sub sp, sp, #28 + 4492 .LCFI31: + 4493 .cfi_def_cfa_offset 48 + 4494 0004 0400 movs r4, r0 + 4495 0006 0391 str r1, [sp, #12] + 4496 0008 0492 str r2, [sp, #16] + 4497 000a 0593 str r3, [sp, #20] + 4498 000c 0CAB add r3, sp, #48 + 4499 .LVL402: + 4500 000e 20CB ldmia r3!, {r5} + 4501 .LVL403: + 4502 0010 1F88 ldrh r7, [r3] + 4503 .LVL404: +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4504 .loc 1 1739 0 + 4505 0012 4123 movs r3, #65 + 4506 .LVL405: + 4507 0014 C35C ldrb r3, [r0, r3] + 4508 0016 202B cmp r3, #32 + 4509 0018 00D0 beq .LCB4820 + 4510 001a E1E0 b .L332 @long jump + 4511 .LCB4820: +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4512 .loc 1 1741 0 + 4513 001c 002D cmp r5, #0 + 4514 001e 00D1 bne .LCB4822 + 4515 0020 E1E0 b .L333 @long jump + 4516 .LCB4822: +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4517 .loc 1 1741 0 is_stmt 0 discriminator 1 + ARM GAS /tmp/ccpuPECZ.s page 176 + + + 4518 0022 002F cmp r7, #0 + 4519 0024 00D1 bne .LCB4824 + 4520 0026 E0E0 b .L334 @long jump + 4521 .LCB4824: +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4522 .loc 1 1747 0 is_stmt 1 + 4523 0028 2033 adds r3, r3, #32 + 4524 002a C35C ldrb r3, [r0, r3] + 4525 002c 012B cmp r3, #1 + 4526 002e 00D1 bne .LCB4828 + 4527 0030 DDE0 b .L335 @long jump + 4528 .LCB4828: +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4529 .loc 1 1747 0 is_stmt 0 discriminator 2 + 4530 0032 4023 movs r3, #64 + 4531 0034 0122 movs r2, #1 + 4532 .LVL406: + 4533 0036 C254 strb r2, [r0, r3] +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4534 .loc 1 1750 0 is_stmt 1 discriminator 2 + 4535 0038 FFF7FEFF bl HAL_GetTick + 4536 .LVL407: + 4537 003c 0600 movs r6, r0 + 4538 .LVL408: + 4539 .L321: + 4540 .LBB228: + 4541 .LBB229: +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4542 .loc 1 4487 0 + 4543 003e 2368 ldr r3, [r4] + 4544 0040 9B69 ldr r3, [r3, #24] + 4545 0042 1B04 lsls r3, r3, #16 + 4546 0044 0ED5 bpl .L339 +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4547 .loc 1 4492 0 + 4548 0046 FFF7FEFF bl HAL_GetTick + 4549 .LVL409: + 4550 004a 801B subs r0, r0, r6 + 4551 004c 1928 cmp r0, #25 + 4552 004e F6D9 bls .L321 +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4553 .loc 1 4494 0 + 4554 0050 4123 movs r3, #65 + 4555 0052 2022 movs r2, #32 + 4556 0054 E254 strb r2, [r4, r3] +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4557 .loc 1 4495 0 + 4558 0056 0023 movs r3, #0 + 4559 0058 2232 adds r2, r2, #34 + 4560 005a A354 strb r3, [r4, r2] +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 4561 .loc 1 4498 0 + 4562 005c 023A subs r2, r2, #2 + 4563 005e A354 strb r3, [r4, r2] + 4564 .LVL410: + 4565 .LBE229: + 4566 .LBE228: + ARM GAS /tmp/ccpuPECZ.s page 177 + + +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4567 .loc 1 1754 0 + 4568 0060 0320 movs r0, #3 + 4569 0062 BEE0 b .L320 + 4570 .LVL411: + 4571 .L339: +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4572 .loc 1 1757 0 + 4573 0064 4123 movs r3, #65 + 4574 0066 2122 movs r2, #33 + 4575 0068 E254 strb r2, [r4, r3] +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4576 .loc 1 1758 0 + 4577 006a 0133 adds r3, r3, #1 + 4578 006c 1F32 adds r2, r2, #31 + 4579 006e E254 strb r2, [r4, r3] +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4580 .loc 1 1759 0 + 4581 0070 0023 movs r3, #0 + 4582 0072 6364 str r3, [r4, #68] +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4583 .loc 1 1762 0 + 4584 0074 6562 str r5, [r4, #36] +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4585 .loc 1 1763 0 + 4586 0076 6785 strh r7, [r4, #42] +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4587 .loc 1 1764 0 + 4588 0078 6363 str r3, [r4, #52] +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4589 .loc 1 1767 0 + 4590 007a 0196 str r6, [sp, #4] + 4591 007c 0E9B ldr r3, [sp, #56] + 4592 007e 0093 str r3, [sp] + 4593 0080 059B ldr r3, [sp, #20] + 4594 0082 049A ldr r2, [sp, #16] + 4595 0084 0399 ldr r1, [sp, #12] + 4596 0086 2000 movs r0, r4 + 4597 0088 FFF7FEFF bl I2C_RequestMemoryWrite + 4598 .LVL412: + 4599 008c 0028 cmp r0, #0 + 4600 008e 0CD0 beq .L323 +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4601 .loc 1 1769 0 + 4602 0090 636C ldr r3, [r4, #68] + 4603 0092 042B cmp r3, #4 + 4604 0094 04D1 bne .L324 +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 4605 .loc 1 1772 0 + 4606 0096 3C33 adds r3, r3, #60 + 4607 0098 0022 movs r2, #0 + 4608 009a E254 strb r2, [r4, r3] +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4609 .loc 1 1773 0 + 4610 009c 0120 movs r0, #1 + 4611 009e A0E0 b .L320 + 4612 .L324: + ARM GAS /tmp/ccpuPECZ.s page 178 + + +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 4613 .loc 1 1778 0 + 4614 00a0 4023 movs r3, #64 + 4615 00a2 0022 movs r2, #0 + 4616 00a4 E254 strb r2, [r4, r3] +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4617 .loc 1 1779 0 + 4618 00a6 0320 movs r0, #3 + 4619 00a8 9BE0 b .L320 + 4620 .L323: +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4621 .loc 1 1784 0 + 4622 00aa 638D ldrh r3, [r4, #42] + 4623 00ac 9BB2 uxth r3, r3 + 4624 00ae FF2B cmp r3, #255 + 4625 00b0 11D9 bls .L325 +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 4626 .loc 1 1786 0 + 4627 00b2 FF23 movs r3, #255 + 4628 00b4 2385 strh r3, [r4, #40] + 4629 .LVL413: + 4630 .LBB230: + 4631 .LBB231: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 4632 .loc 1 4713 0 + 4633 00b6 2068 ldr r0, [r4] + 4634 00b8 4368 ldr r3, [r0, #4] + 4635 00ba 514A ldr r2, .L342 + 4636 00bc 1340 ands r3, r2 + 4637 00be 039A ldr r2, [sp, #12] + 4638 00c0 9105 lsls r1, r2, #22 + 4639 00c2 890D lsrs r1, r1, #22 + 4640 00c4 FF22 movs r2, #255 + 4641 00c6 1204 lsls r2, r2, #16 + 4642 00c8 1143 orrs r1, r2 + 4643 00ca 8022 movs r2, #128 + 4644 00cc 5204 lsls r2, r2, #17 + 4645 00ce 0A43 orrs r2, r1 + 4646 00d0 1343 orrs r3, r2 + 4647 00d2 4360 str r3, [r0, #4] + 4648 00d4 2EE0 b .L330 + 4649 .LVL414: + 4650 .L325: + 4651 .LBE231: + 4652 .LBE230: +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 4653 .loc 1 1791 0 + 4654 00d6 638D ldrh r3, [r4, #42] + 4655 00d8 9BB2 uxth r3, r3 + 4656 00da 2385 strh r3, [r4, #40] +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4657 .loc 1 1792 0 + 4658 00dc DBB2 uxtb r3, r3 + 4659 .LVL415: + 4660 .LBB232: + 4661 .LBB233: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + ARM GAS /tmp/ccpuPECZ.s page 179 + + + 4662 .loc 1 4713 0 + 4663 00de 2068 ldr r0, [r4] + 4664 00e0 4268 ldr r2, [r0, #4] + 4665 00e2 4749 ldr r1, .L342 + 4666 00e4 0A40 ands r2, r1 + 4667 00e6 0399 ldr r1, [sp, #12] + 4668 00e8 8905 lsls r1, r1, #22 + 4669 00ea 890D lsrs r1, r1, #22 + 4670 00ec 1B04 lsls r3, r3, #16 + 4671 .LVL416: + 4672 00ee 0B43 orrs r3, r1 + 4673 00f0 8021 movs r1, #128 + 4674 00f2 8904 lsls r1, r1, #18 + 4675 00f4 0B43 orrs r3, r1 + 4676 00f6 1343 orrs r3, r2 + 4677 00f8 4360 str r3, [r0, #4] + 4678 .LVL417: + 4679 00fa 1BE0 b .L330 + 4680 .LVL418: + 4681 .L341: + 4682 .LBE233: + 4683 .LBE232: +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4684 .loc 1 1800 0 + 4685 00fc 636C ldr r3, [r4, #68] + 4686 00fe 042B cmp r3, #4 + 4687 0100 00D0 beq .LCB5020 + 4688 0102 76E0 b .L336 @long jump + 4689 .LCB5020: +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4690 .loc 1 1802 0 + 4691 0104 0120 movs r0, #1 + 4692 0106 6CE0 b .L320 + 4693 .L329: +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 4694 .loc 1 1830 0 + 4695 0108 638D ldrh r3, [r4, #42] + 4696 010a 9BB2 uxth r3, r3 + 4697 010c 2385 strh r3, [r4, #40] +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4698 .loc 1 1831 0 + 4699 010e DBB2 uxtb r3, r3 + 4700 .LVL419: + 4701 .LBB234: + 4702 .LBB235: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 4703 .loc 1 4713 0 + 4704 0110 2068 ldr r0, [r4] + 4705 0112 4268 ldr r2, [r0, #4] + 4706 0114 3A49 ldr r1, .L342 + 4707 0116 0A40 ands r2, r1 + 4708 0118 0399 ldr r1, [sp, #12] + 4709 011a 8905 lsls r1, r1, #22 + 4710 011c 890D lsrs r1, r1, #22 + 4711 011e 1B04 lsls r3, r3, #16 + 4712 .LVL420: + 4713 0120 0B43 orrs r3, r1 + ARM GAS /tmp/ccpuPECZ.s page 180 + + + 4714 0122 8021 movs r1, #128 + 4715 0124 8904 lsls r1, r1, #18 + 4716 0126 0B43 orrs r3, r1 + 4717 0128 1343 orrs r3, r2 + 4718 012a 4360 str r3, [r0, #4] + 4719 .LVL421: + 4720 .L328: + 4721 .LBE235: + 4722 .LBE234: +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4723 .loc 1 1836 0 + 4724 012c 638D ldrh r3, [r4, #42] + 4725 012e 9BB2 uxth r3, r3 + 4726 0130 002B cmp r3, #0 + 4727 0132 39D0 beq .L340 + 4728 .L330: +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4729 .loc 1 1798 0 + 4730 0134 3200 movs r2, r6 + 4731 0136 0E99 ldr r1, [sp, #56] + 4732 0138 2000 movs r0, r4 + 4733 013a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 4734 .LVL422: + 4735 013e 0028 cmp r0, #0 + 4736 0140 DCD1 bne .L341 +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 4737 .loc 1 1811 0 + 4738 0142 636A ldr r3, [r4, #36] + 4739 0144 5A1C adds r2, r3, #1 + 4740 0146 6262 str r2, [r4, #36] + 4741 0148 2268 ldr r2, [r4] + 4742 014a 1B78 ldrb r3, [r3] + 4743 014c 9362 str r3, [r2, #40] +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 4744 .loc 1 1812 0 + 4745 014e 638D ldrh r3, [r4, #42] + 4746 0150 013B subs r3, r3, #1 + 4747 0152 9BB2 uxth r3, r3 + 4748 0154 6385 strh r3, [r4, #42] +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4749 .loc 1 1813 0 + 4750 0156 238D ldrh r3, [r4, #40] + 4751 0158 013B subs r3, r3, #1 + 4752 015a 9BB2 uxth r3, r3 + 4753 015c 2385 strh r3, [r4, #40] +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4754 .loc 1 1815 0 + 4755 015e 002B cmp r3, #0 + 4756 0160 E4D1 bne .L328 +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4757 .loc 1 1815 0 is_stmt 0 discriminator 1 + 4758 0162 638D ldrh r3, [r4, #42] + 4759 0164 9BB2 uxth r3, r3 + 4760 0166 002B cmp r3, #0 + 4761 0168 E0D0 beq .L328 +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4762 .loc 1 1818 0 is_stmt 1 + ARM GAS /tmp/ccpuPECZ.s page 181 + + + 4763 016a 0096 str r6, [sp] + 4764 016c 0E9B ldr r3, [sp, #56] + 4765 016e 0022 movs r2, #0 + 4766 0170 8021 movs r1, #128 + 4767 0172 2000 movs r0, r4 + 4768 0174 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4769 .LVL423: + 4770 0178 0028 cmp r0, #0 + 4771 017a 3CD1 bne .L337 +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4772 .loc 1 1823 0 + 4773 017c 638D ldrh r3, [r4, #42] + 4774 017e 9BB2 uxth r3, r3 + 4775 0180 FF2B cmp r3, #255 + 4776 0182 C1D9 bls .L329 +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 4777 .loc 1 1825 0 + 4778 0184 FF23 movs r3, #255 + 4779 0186 2385 strh r3, [r4, #40] + 4780 .LVL424: + 4781 .LBB236: + 4782 .LBB237: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 4783 .loc 1 4713 0 + 4784 0188 2068 ldr r0, [r4] + 4785 018a 4368 ldr r3, [r0, #4] + 4786 018c 1C4A ldr r2, .L342 + 4787 018e 1340 ands r3, r2 + 4788 0190 039A ldr r2, [sp, #12] + 4789 0192 9105 lsls r1, r2, #22 + 4790 0194 890D lsrs r1, r1, #22 + 4791 0196 FF22 movs r2, #255 + 4792 0198 1204 lsls r2, r2, #16 + 4793 019a 1143 orrs r1, r2 + 4794 019c 8022 movs r2, #128 + 4795 019e 5204 lsls r2, r2, #17 + 4796 01a0 0A43 orrs r2, r1 + 4797 01a2 1343 orrs r3, r2 + 4798 01a4 4360 str r3, [r0, #4] + 4799 01a6 C1E7 b .L328 + 4800 .LVL425: + 4801 .L340: + 4802 .LBE237: + 4803 .LBE236: +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4804 .loc 1 1840 0 + 4805 01a8 3200 movs r2, r6 + 4806 01aa 0E99 ldr r1, [sp, #56] + 4807 01ac 2000 movs r0, r4 + 4808 01ae FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 4809 .LVL426: + 4810 01b2 0028 cmp r0, #0 + 4811 01b4 04D0 beq .L331 +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4812 .loc 1 1842 0 + 4813 01b6 636C ldr r3, [r4, #68] + 4814 01b8 042B cmp r3, #4 + ARM GAS /tmp/ccpuPECZ.s page 182 + + + 4815 01ba 1ED1 bne .L338 +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4816 .loc 1 1844 0 + 4817 01bc 0120 movs r0, #1 + 4818 01be 10E0 b .L320 + 4819 .L331: +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4820 .loc 1 1853 0 + 4821 01c0 2368 ldr r3, [r4] + 4822 01c2 2022 movs r2, #32 + 4823 01c4 DA61 str r2, [r3, #28] +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4824 .loc 1 1856 0 + 4825 01c6 2168 ldr r1, [r4] + 4826 01c8 4B68 ldr r3, [r1, #4] + 4827 01ca 0E4D ldr r5, .L342+4 + 4828 01cc 2B40 ands r3, r5 + 4829 01ce 4B60 str r3, [r1, #4] +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4830 .loc 1 1858 0 + 4831 01d0 4123 movs r3, #65 + 4832 01d2 E254 strb r2, [r4, r3] +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4833 .loc 1 1859 0 + 4834 01d4 0023 movs r3, #0 + 4835 01d6 2232 adds r2, r2, #34 + 4836 01d8 A354 strb r3, [r4, r2] +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4837 .loc 1 1862 0 + 4838 01da 023A subs r2, r2, #2 + 4839 01dc A354 strb r3, [r4, r2] +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4840 .loc 1 1864 0 + 4841 01de 00E0 b .L320 + 4842 .LVL427: + 4843 .L332: +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4844 .loc 1 1868 0 + 4845 01e0 0220 movs r0, #2 + 4846 .LVL428: + 4847 .L320: +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4848 .loc 1 1870 0 + 4849 01e2 07B0 add sp, sp, #28 + 4850 @ sp needed + 4851 .LVL429: + 4852 01e4 F0BD pop {r4, r5, r6, r7, pc} + 4853 .LVL430: + 4854 .L333: +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4855 .loc 1 1743 0 + 4856 01e6 0120 movs r0, #1 + 4857 .LVL431: + 4858 01e8 FBE7 b .L320 + 4859 .LVL432: + 4860 .L334: + 4861 01ea 0120 movs r0, #1 + ARM GAS /tmp/ccpuPECZ.s page 183 + + + 4862 .LVL433: + 4863 01ec F9E7 b .L320 + 4864 .LVL434: + 4865 .L335: +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4866 .loc 1 1747 0 + 4867 01ee 0220 movs r0, #2 + 4868 .LVL435: + 4869 01f0 F7E7 b .L320 + 4870 .LVL436: + 4871 .L336: +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4872 .loc 1 1806 0 + 4873 01f2 0320 movs r0, #3 + 4874 01f4 F5E7 b .L320 + 4875 .L337: +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4876 .loc 1 1820 0 + 4877 01f6 0320 movs r0, #3 + 4878 01f8 F3E7 b .L320 + 4879 .L338: +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4880 .loc 1 1848 0 + 4881 01fa 0320 movs r0, #3 + 4882 01fc F1E7 b .L320 + 4883 .L343: + 4884 01fe C046 .align 2 + 4885 .L342: + 4886 0200 009C00FC .word -67068928 + 4887 0204 00E800FE .word -33495040 + 4888 .cfi_endproc + 4889 .LFE55: + 4891 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 4892 .align 1 + 4893 .global HAL_I2C_Mem_Read + 4894 .syntax unified + 4895 .code 16 + 4896 .thumb_func + 4897 .fpu softvfp + 4899 HAL_I2C_Mem_Read: + 4900 .LFB56: +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 4901 .loc 1 1886 0 + 4902 .cfi_startproc + 4903 @ args = 12, pretend = 0, frame = 16 + 4904 @ frame_needed = 0, uses_anonymous_args = 0 + 4905 .LVL437: + 4906 0000 F0B5 push {r4, r5, r6, r7, lr} + 4907 .LCFI32: + 4908 .cfi_def_cfa_offset 20 + 4909 .cfi_offset 4, -20 + 4910 .cfi_offset 5, -16 + 4911 .cfi_offset 6, -12 + 4912 .cfi_offset 7, -8 + 4913 .cfi_offset 14, -4 + 4914 0002 87B0 sub sp, sp, #28 + 4915 .LCFI33: + ARM GAS /tmp/ccpuPECZ.s page 184 + + + 4916 .cfi_def_cfa_offset 48 + 4917 0004 0400 movs r4, r0 + 4918 0006 0391 str r1, [sp, #12] + 4919 0008 0492 str r2, [sp, #16] + 4920 000a 0593 str r3, [sp, #20] + 4921 000c 0CAB add r3, sp, #48 + 4922 .LVL438: + 4923 000e 20CB ldmia r3!, {r5} + 4924 .LVL439: + 4925 0010 1F88 ldrh r7, [r3] + 4926 .LVL440: +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4927 .loc 1 1892 0 + 4928 0012 4123 movs r3, #65 + 4929 .LVL441: + 4930 0014 C35C ldrb r3, [r0, r3] + 4931 0016 202B cmp r3, #32 + 4932 0018 00D0 beq .LCB5317 + 4933 001a F6E0 b .L345 @long jump + 4934 .LCB5317: +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4935 .loc 1 1894 0 + 4936 001c 002D cmp r5, #0 + 4937 001e 22D0 beq .L346 +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4938 .loc 1 1894 0 is_stmt 0 discriminator 1 + 4939 0020 002F cmp r7, #0 + 4940 0022 20D0 beq .L346 +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4941 .loc 1 1901 0 is_stmt 1 + 4942 0024 4023 movs r3, #64 + 4943 0026 C35C ldrb r3, [r0, r3] + 4944 0028 012B cmp r3, #1 + 4945 002a 00D1 bne .LCB5325 + 4946 002c F2E0 b .L361 @long jump + 4947 .LCB5325: +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4948 .loc 1 1901 0 is_stmt 0 discriminator 2 + 4949 002e 4023 movs r3, #64 + 4950 0030 0122 movs r2, #1 + 4951 .LVL442: + 4952 0032 C254 strb r2, [r0, r3] +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4953 .loc 1 1904 0 is_stmt 1 discriminator 2 + 4954 0034 FFF7FEFF bl HAL_GetTick + 4955 .LVL443: + 4956 0038 0600 movs r6, r0 + 4957 .LVL444: + 4958 .L349: + 4959 .LBB238: + 4960 .LBB239: +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4961 .loc 1 4487 0 + 4962 003a 2368 ldr r3, [r4] + 4963 003c 9B69 ldr r3, [r3, #24] + 4964 003e 1B04 lsls r3, r3, #16 + 4965 0040 17D5 bpl .L363 + ARM GAS /tmp/ccpuPECZ.s page 185 + + +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 4966 .loc 1 4492 0 + 4967 0042 FFF7FEFF bl HAL_GetTick + 4968 .LVL445: + 4969 0046 801B subs r0, r0, r6 + 4970 0048 1928 cmp r0, #25 + 4971 004a F6D9 bls .L349 +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4972 .loc 1 4494 0 + 4973 004c 4123 movs r3, #65 + 4974 004e 2022 movs r2, #32 + 4975 0050 E254 strb r2, [r4, r3] +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 4976 .loc 1 4495 0 + 4977 0052 0023 movs r3, #0 + 4978 0054 2232 adds r2, r2, #34 + 4979 0056 A354 strb r3, [r4, r2] +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 4980 .loc 1 4498 0 + 4981 0058 023A subs r2, r2, #2 + 4982 005a A354 strb r3, [r4, r2] + 4983 .LVL446: + 4984 .LBE239: + 4985 .LBE238: +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 4986 .loc 1 1908 0 + 4987 005c 6E48 ldr r0, .L369 + 4988 005e FFF7FEFF bl vcom_Send + 4989 .LVL447: +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 4990 .loc 1 1909 0 + 4991 0062 0320 movs r0, #3 + 4992 0064 03E0 b .L348 + 4993 .LVL448: + 4994 .L346: +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 4995 .loc 1 1896 0 + 4996 0066 6D48 ldr r0, .L369+4 + 4997 .LVL449: + 4998 0068 FFF7FEFF bl vcom_Send + 4999 .LVL450: +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5000 .loc 1 1897 0 + 5001 006c 0120 movs r0, #1 + 5002 .LVL451: + 5003 .L348: +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 5004 .loc 1 2023 0 + 5005 006e 07B0 add sp, sp, #28 + 5006 @ sp needed + 5007 .LVL452: + 5008 0070 F0BD pop {r4, r5, r6, r7, pc} + 5009 .LVL453: + 5010 .L363: +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5011 .loc 1 1912 0 + 5012 0072 4123 movs r3, #65 + ARM GAS /tmp/ccpuPECZ.s page 186 + + + 5013 0074 2222 movs r2, #34 + 5014 0076 E254 strb r2, [r4, r3] +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5015 .loc 1 1913 0 + 5016 0078 0133 adds r3, r3, #1 + 5017 007a 1E32 adds r2, r2, #30 + 5018 007c E254 strb r2, [r4, r3] +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5019 .loc 1 1914 0 + 5020 007e 0023 movs r3, #0 + 5021 0080 6364 str r3, [r4, #68] +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5022 .loc 1 1917 0 + 5023 0082 6562 str r5, [r4, #36] +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5024 .loc 1 1918 0 + 5025 0084 6785 strh r7, [r4, #42] +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5026 .loc 1 1919 0 + 5027 0086 6363 str r3, [r4, #52] +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5028 .loc 1 1922 0 + 5029 0088 0196 str r6, [sp, #4] + 5030 008a 0E9B ldr r3, [sp, #56] + 5031 008c 0093 str r3, [sp] + 5032 008e 059B ldr r3, [sp, #20] + 5033 0090 049A ldr r2, [sp, #16] + 5034 0092 0399 ldr r1, [sp, #12] + 5035 0094 2000 movs r0, r4 + 5036 0096 FFF7FEFF bl I2C_RequestMemoryRead + 5037 .LVL454: + 5038 009a 0028 cmp r0, #0 + 5039 009c 14D1 bne .L364 +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5040 .loc 1 1941 0 + 5041 009e 638D ldrh r3, [r4, #42] + 5042 00a0 9BB2 uxth r3, r3 + 5043 00a2 FF2B cmp r3, #255 + 5044 00a4 21D9 bls .L353 +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ + 5045 .loc 1 1943 0 + 5046 00a6 FF23 movs r3, #255 + 5047 00a8 2385 strh r3, [r4, #40] + 5048 .LVL455: + 5049 .LBB240: + 5050 .LBB241: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5051 .loc 1 4713 0 + 5052 00aa 2068 ldr r0, [r4] + 5053 00ac 4368 ldr r3, [r0, #4] + 5054 00ae 5C4A ldr r2, .L369+8 + 5055 00b0 1340 ands r3, r2 + 5056 00b2 039A ldr r2, [sp, #12] + 5057 00b4 9105 lsls r1, r2, #22 + 5058 00b6 890D lsrs r1, r1, #22 + 5059 00b8 FF22 movs r2, #255 + 5060 00ba 1204 lsls r2, r2, #16 + ARM GAS /tmp/ccpuPECZ.s page 187 + + + 5061 00bc 1143 orrs r1, r2 + 5062 00be 594A ldr r2, .L369+12 + 5063 00c0 0A43 orrs r2, r1 + 5064 00c2 1343 orrs r3, r2 + 5065 00c4 4360 str r3, [r0, #4] + 5066 00c6 42E0 b .L359 + 5067 .LVL456: + 5068 .L364: + 5069 .LBE241: + 5070 .LBE240: +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + 5071 .loc 1 1924 0 + 5072 00c8 616C ldr r1, [r4, #68] + 5073 00ca 5748 ldr r0, .L369+16 + 5074 00cc FFF7FEFF bl vcom_Send + 5075 .LVL457: +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5076 .loc 1 1925 0 + 5077 00d0 636C ldr r3, [r4, #68] + 5078 00d2 042B cmp r3, #4 + 5079 00d4 04D1 bne .L352 +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 5080 .loc 1 1928 0 + 5081 00d6 3C33 adds r3, r3, #60 + 5082 00d8 0022 movs r2, #0 + 5083 00da E254 strb r2, [r4, r3] +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5084 .loc 1 1929 0 + 5085 00dc 0120 movs r0, #1 + 5086 00de C6E7 b .L348 + 5087 .L352: +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 5088 .loc 1 1934 0 + 5089 00e0 4023 movs r3, #64 + 5090 00e2 0022 movs r2, #0 + 5091 00e4 E254 strb r2, [r4, r3] +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5092 .loc 1 1935 0 + 5093 00e6 0320 movs r0, #3 + 5094 00e8 C1E7 b .L348 + 5095 .L353: +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_REA + 5096 .loc 1 1948 0 + 5097 00ea 638D ldrh r3, [r4, #42] + 5098 00ec 9BB2 uxth r3, r3 + 5099 00ee 2385 strh r3, [r4, #40] +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5100 .loc 1 1949 0 + 5101 00f0 DBB2 uxtb r3, r3 + 5102 .LVL458: + 5103 .LBB242: + 5104 .LBB243: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5105 .loc 1 4713 0 + 5106 00f2 2068 ldr r0, [r4] + 5107 00f4 4268 ldr r2, [r0, #4] + 5108 00f6 4A49 ldr r1, .L369+8 + ARM GAS /tmp/ccpuPECZ.s page 188 + + + 5109 00f8 0A40 ands r2, r1 + 5110 00fa 0399 ldr r1, [sp, #12] + 5111 00fc 8905 lsls r1, r1, #22 + 5112 00fe 890D lsrs r1, r1, #22 + 5113 0100 1B04 lsls r3, r3, #16 + 5114 .LVL459: + 5115 0102 0B43 orrs r3, r1 + 5116 0104 4949 ldr r1, .L369+20 + 5117 0106 0B43 orrs r3, r1 + 5118 0108 1343 orrs r3, r2 + 5119 010a 4360 str r3, [r0, #4] + 5120 .LVL460: + 5121 010c 1FE0 b .L359 + 5122 .LVL461: + 5123 .L366: + 5124 .LBE243: + 5125 .LBE242: +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 5126 .loc 1 1957 0 + 5127 010e 4848 ldr r0, .L369+24 + 5128 0110 FFF7FEFF bl vcom_Send + 5129 .LVL462: +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5130 .loc 1 1958 0 + 5131 0114 0320 movs r0, #3 + 5132 0116 AAE7 b .L348 + 5133 .L367: +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 5134 .loc 1 1971 0 + 5135 0118 4648 ldr r0, .L369+28 + 5136 011a FFF7FEFF bl vcom_Send + 5137 .LVL463: +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5138 .loc 1 1972 0 + 5139 011e 0320 movs r0, #3 + 5140 0120 A5E7 b .L348 + 5141 .L358: +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 5142 .loc 1 1982 0 + 5143 0122 638D ldrh r3, [r4, #42] + 5144 0124 9BB2 uxth r3, r3 + 5145 0126 2385 strh r3, [r4, #40] +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5146 .loc 1 1983 0 + 5147 0128 DBB2 uxtb r3, r3 + 5148 .LVL464: + 5149 .LBB244: + 5150 .LBB245: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5151 .loc 1 4713 0 + 5152 012a 2068 ldr r0, [r4] + 5153 012c 4268 ldr r2, [r0, #4] + 5154 012e 4249 ldr r1, .L369+32 + 5155 0130 0A40 ands r2, r1 + 5156 0132 0399 ldr r1, [sp, #12] + 5157 0134 8905 lsls r1, r1, #22 + 5158 0136 890D lsrs r1, r1, #22 + ARM GAS /tmp/ccpuPECZ.s page 189 + + + 5159 0138 1B04 lsls r3, r3, #16 + 5160 .LVL465: + 5161 013a 0B43 orrs r3, r1 + 5162 013c 8021 movs r1, #128 + 5163 013e 8904 lsls r1, r1, #18 + 5164 0140 0B43 orrs r3, r1 + 5165 0142 1343 orrs r3, r2 + 5166 0144 4360 str r3, [r0, #4] + 5167 .LVL466: + 5168 .L356: + 5169 .LBE245: + 5170 .LBE244: +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5171 .loc 1 1987 0 + 5172 0146 638D ldrh r3, [r4, #42] + 5173 0148 9BB2 uxth r3, r3 + 5174 014a 002B cmp r3, #0 + 5175 014c 3BD0 beq .L365 + 5176 .L359: +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5177 .loc 1 1955 0 + 5178 014e 0096 str r6, [sp] + 5179 0150 0E9B ldr r3, [sp, #56] + 5180 0152 0022 movs r2, #0 + 5181 0154 0421 movs r1, #4 + 5182 0156 2000 movs r0, r4 + 5183 0158 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5184 .LVL467: + 5185 015c 0028 cmp r0, #0 + 5186 015e D6D1 bne .L366 +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 5187 .loc 1 1962 0 + 5188 0160 2368 ldr r3, [r4] + 5189 0162 5A6A ldr r2, [r3, #36] + 5190 0164 636A ldr r3, [r4, #36] + 5191 0166 591C adds r1, r3, #1 + 5192 0168 6162 str r1, [r4, #36] + 5193 016a 1A70 strb r2, [r3] +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 5194 .loc 1 1963 0 + 5195 016c 238D ldrh r3, [r4, #40] + 5196 016e 013B subs r3, r3, #1 + 5197 0170 9BB2 uxth r3, r3 + 5198 0172 2385 strh r3, [r4, #40] +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5199 .loc 1 1964 0 + 5200 0174 628D ldrh r2, [r4, #42] + 5201 0176 013A subs r2, r2, #1 + 5202 0178 92B2 uxth r2, r2 + 5203 017a 6285 strh r2, [r4, #42] +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5204 .loc 1 1966 0 + 5205 017c 002B cmp r3, #0 + 5206 017e E2D1 bne .L356 +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5207 .loc 1 1966 0 is_stmt 0 discriminator 1 + 5208 0180 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccpuPECZ.s page 190 + + + 5209 0182 9BB2 uxth r3, r3 + 5210 0184 002B cmp r3, #0 + 5211 0186 DED0 beq .L356 +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5212 .loc 1 1969 0 is_stmt 1 + 5213 0188 0096 str r6, [sp] + 5214 018a 0E9B ldr r3, [sp, #56] + 5215 018c 0022 movs r2, #0 + 5216 018e 8021 movs r1, #128 + 5217 0190 2000 movs r0, r4 + 5218 0192 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5219 .LVL468: + 5220 0196 0028 cmp r0, #0 + 5221 0198 BED1 bne .L367 +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5222 .loc 1 1975 0 + 5223 019a 638D ldrh r3, [r4, #42] + 5224 019c 9BB2 uxth r3, r3 + 5225 019e FF2B cmp r3, #255 + 5226 01a0 BFD9 bls .L358 +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 5227 .loc 1 1977 0 + 5228 01a2 FF23 movs r3, #255 + 5229 01a4 2385 strh r3, [r4, #40] + 5230 .LVL469: + 5231 .LBB246: + 5232 .LBB247: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5233 .loc 1 4713 0 + 5234 01a6 2068 ldr r0, [r4] + 5235 01a8 4368 ldr r3, [r0, #4] + 5236 01aa 234A ldr r2, .L369+32 + 5237 01ac 1340 ands r3, r2 + 5238 01ae 039A ldr r2, [sp, #12] + 5239 01b0 9105 lsls r1, r2, #22 + 5240 01b2 890D lsrs r1, r1, #22 + 5241 01b4 FF22 movs r2, #255 + 5242 01b6 1204 lsls r2, r2, #16 + 5243 01b8 1143 orrs r1, r2 + 5244 01ba 8022 movs r2, #128 + 5245 01bc 5204 lsls r2, r2, #17 + 5246 01be 0A43 orrs r2, r1 + 5247 01c0 1343 orrs r3, r2 + 5248 01c2 4360 str r3, [r0, #4] + 5249 01c4 BFE7 b .L356 + 5250 .LVL470: + 5251 .L365: + 5252 .LBE247: + 5253 .LBE246: +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5254 .loc 1 1991 0 + 5255 01c6 3200 movs r2, r6 + 5256 01c8 0E99 ldr r1, [sp, #56] + 5257 01ca 2000 movs r0, r4 + 5258 01cc FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5259 .LVL471: + 5260 01d0 0028 cmp r0, #0 + ARM GAS /tmp/ccpuPECZ.s page 191 + + + 5261 01d2 0AD0 beq .L360 +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5262 .loc 1 1993 0 + 5263 01d4 636C ldr r3, [r4, #68] + 5264 01d6 042B cmp r3, #4 + 5265 01d8 01D0 beq .L368 +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5266 .loc 1 2000 0 + 5267 01da 0320 movs r0, #3 + 5268 01dc 47E7 b .L348 + 5269 .L368: +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 5270 .loc 1 1995 0 + 5271 01de 616C ldr r1, [r4, #68] + 5272 01e0 1648 ldr r0, .L369+36 + 5273 01e2 FFF7FEFF bl vcom_Send + 5274 .LVL472: +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5275 .loc 1 1996 0 + 5276 01e6 0120 movs r0, #1 + 5277 01e8 41E7 b .L348 + 5278 .L360: +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5279 .loc 1 2005 0 + 5280 01ea 2368 ldr r3, [r4] + 5281 01ec 2022 movs r2, #32 + 5282 01ee DA61 str r2, [r3, #28] +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5283 .loc 1 2008 0 + 5284 01f0 2168 ldr r1, [r4] + 5285 01f2 4B68 ldr r3, [r1, #4] + 5286 01f4 124D ldr r5, .L369+40 + 5287 01f6 2B40 ands r3, r5 + 5288 01f8 4B60 str r3, [r1, #4] +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5289 .loc 1 2010 0 + 5290 01fa 4123 movs r3, #65 + 5291 01fc E254 strb r2, [r4, r3] +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5292 .loc 1 2011 0 + 5293 01fe 0023 movs r3, #0 + 5294 0200 2232 adds r2, r2, #34 + 5295 0202 A354 strb r3, [r4, r2] +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5296 .loc 1 2014 0 + 5297 0204 023A subs r2, r2, #2 + 5298 0206 A354 strb r3, [r4, r2] +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5299 .loc 1 2016 0 + 5300 0208 31E7 b .L348 + 5301 .LVL473: + 5302 .L345: +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_BUSY; + 5303 .loc 1 2020 0 + 5304 020a 0E48 ldr r0, .L369+44 + 5305 .LVL474: + 5306 020c FFF7FEFF bl vcom_Send + ARM GAS /tmp/ccpuPECZ.s page 192 + + + 5307 .LVL475: +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5308 .loc 1 2021 0 + 5309 0210 0220 movs r0, #2 + 5310 0212 2CE7 b .L348 + 5311 .LVL476: + 5312 .L361: +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5313 .loc 1 1901 0 + 5314 0214 0220 movs r0, #2 + 5315 .LVL477: + 5316 0216 2AE7 b .L348 + 5317 .L370: + 5318 .align 2 + 5319 .L369: + 5320 0218 18000000 .word .LC40 + 5321 021c 00000000 .word .LC38 + 5322 0220 009800FC .word -67069952 + 5323 0224 00240081 .word -2130697216 + 5324 0228 24000000 .word .LC42 + 5325 022c 00240082 .word -2113920000 + 5326 0230 40000000 .word .LC44 + 5327 0234 5C000000 .word .LC46 + 5328 0238 009C00FC .word -67068928 + 5329 023c 78000000 .word .LC48 + 5330 0240 00E800FE .word -33495040 + 5331 0244 94000000 .word .LC50 + 5332 .cfi_endproc + 5333 .LFE56: + 5335 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 5336 .align 1 + 5337 .global HAL_I2C_Mem_Write_IT + 5338 .syntax unified + 5339 .code 16 + 5340 .thumb_func + 5341 .fpu softvfp + 5343 HAL_I2C_Mem_Write_IT: + 5344 .LFB57: +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 5345 .loc 1 2037 0 + 5346 .cfi_startproc + 5347 @ args = 8, pretend = 0, frame = 8 + 5348 @ frame_needed = 0, uses_anonymous_args = 0 + 5349 .LVL478: + 5350 0000 F0B5 push {r4, r5, r6, r7, lr} + 5351 .LCFI34: + 5352 .cfi_def_cfa_offset 20 + 5353 .cfi_offset 4, -20 + 5354 .cfi_offset 5, -16 + 5355 .cfi_offset 6, -12 + 5356 .cfi_offset 7, -8 + 5357 .cfi_offset 14, -4 + 5358 0002 D646 mov lr, r10 + 5359 0004 4746 mov r7, r8 + 5360 0006 80B5 push {r7, lr} + 5361 .LCFI35: + 5362 .cfi_def_cfa_offset 28 + ARM GAS /tmp/ccpuPECZ.s page 193 + + + 5363 .cfi_offset 8, -28 + 5364 .cfi_offset 10, -24 + 5365 0008 85B0 sub sp, sp, #20 + 5366 .LCFI36: + 5367 .cfi_def_cfa_offset 48 + 5368 000a 0700 movs r7, r0 + 5369 000c 0C00 movs r4, r1 + 5370 000e 0292 str r2, [sp, #8] + 5371 0010 0393 str r3, [sp, #12] + 5372 0012 0CAB add r3, sp, #48 + 5373 .LVL479: + 5374 0014 40CB ldmia r3!, {r6} + 5375 .LVL480: + 5376 0016 1D88 ldrh r5, [r3] + 5377 .LVL481: +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5378 .loc 1 2044 0 + 5379 0018 4123 movs r3, #65 + 5380 .LVL482: + 5381 001a C35C ldrb r3, [r0, r3] + 5382 001c 202B cmp r3, #32 + 5383 001e 6DD1 bne .L378 +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5384 .loc 1 2046 0 + 5385 0020 002E cmp r6, #0 + 5386 0022 00D1 bne .LCB5833 + 5387 0024 70E0 b .L379 @long jump + 5388 .LCB5833: +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5389 .loc 1 2046 0 is_stmt 0 discriminator 1 + 5390 0026 002D cmp r5, #0 + 5391 0028 00D1 bne .LCB5835 + 5392 002a 6FE0 b .L380 @long jump + 5393 .LCB5835: +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5394 .loc 1 2051 0 is_stmt 1 + 5395 002c 0368 ldr r3, [r0] + 5396 002e 9B69 ldr r3, [r3, #24] + 5397 0030 1B04 lsls r3, r3, #16 + 5398 0032 00D5 bpl .LCB5841 + 5399 0034 6CE0 b .L381 @long jump + 5400 .LCB5841: +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5401 .loc 1 2057 0 + 5402 0036 4023 movs r3, #64 + 5403 0038 C35C ldrb r3, [r0, r3] + 5404 003a 012B cmp r3, #1 + 5405 003c 6AD0 beq .L382 +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5406 .loc 1 2057 0 is_stmt 0 discriminator 2 + 5407 003e 4023 movs r3, #64 + 5408 0040 9A46 mov r10, r3 + 5409 0042 3F3B subs r3, r3, #63 + 5410 0044 5246 mov r2, r10 + 5411 .LVL483: + 5412 0046 8354 strb r3, [r0, r2] +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 194 + + + 5413 .loc 1 2060 0 is_stmt 1 discriminator 2 + 5414 0048 FFF7FEFF bl HAL_GetTick + 5415 .LVL484: +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5416 .loc 1 2062 0 discriminator 2 + 5417 004c 4123 movs r3, #65 + 5418 004e 2122 movs r2, #33 + 5419 0050 FA54 strb r2, [r7, r3] +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5420 .loc 1 2063 0 discriminator 2 + 5421 0052 0133 adds r3, r3, #1 + 5422 0054 5246 mov r2, r10 + 5423 0056 FA54 strb r2, [r7, r3] +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5424 .loc 1 2064 0 discriminator 2 + 5425 0058 0023 movs r3, #0 + 5426 005a 7B64 str r3, [r7, #68] +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5427 .loc 1 2067 0 discriminator 2 + 5428 005c 7E62 str r6, [r7, #36] +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5429 .loc 1 2068 0 discriminator 2 + 5430 005e 7D85 strh r5, [r7, #42] +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5431 .loc 1 2069 0 discriminator 2 + 5432 0060 2D4B ldr r3, .L386 + 5433 0062 FB62 str r3, [r7, #44] +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5434 .loc 1 2070 0 discriminator 2 + 5435 0064 2D4B ldr r3, .L386+4 + 5436 0066 7B63 str r3, [r7, #52] +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5437 .loc 1 2072 0 discriminator 2 + 5438 0068 7B8D ldrh r3, [r7, #42] + 5439 006a 9BB2 uxth r3, r3 + 5440 006c FF2B cmp r3, #255 + 5441 006e 17D9 bls .L373 +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5442 .loc 1 2074 0 + 5443 0070 FF23 movs r3, #255 + 5444 0072 3B85 strh r3, [r7, #40] + 5445 .LVL485: +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5446 .loc 1 2075 0 + 5447 0074 8023 movs r3, #128 + 5448 0076 5B04 lsls r3, r3, #17 + 5449 0078 9846 mov r8, r3 + 5450 .LVL486: + 5451 .L374: +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5452 .loc 1 2084 0 + 5453 007a 0190 str r0, [sp, #4] + 5454 007c 1923 movs r3, #25 + 5455 007e 0093 str r3, [sp] + 5456 0080 039B ldr r3, [sp, #12] + 5457 0082 029A ldr r2, [sp, #8] + 5458 0084 2100 movs r1, r4 + ARM GAS /tmp/ccpuPECZ.s page 195 + + + 5459 0086 3800 movs r0, r7 + 5460 .LVL487: + 5461 0088 FFF7FEFF bl I2C_RequestMemoryWrite + 5462 .LVL488: + 5463 008c 0028 cmp r0, #0 + 5464 008e 12D0 beq .L375 +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5465 .loc 1 2086 0 + 5466 0090 7B6C ldr r3, [r7, #68] + 5467 0092 042B cmp r3, #4 + 5468 0094 0AD1 bne .L376 +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 5469 .loc 1 2089 0 + 5470 0096 3C33 adds r3, r3, #60 + 5471 0098 0022 movs r2, #0 + 5472 009a FA54 strb r2, [r7, r3] +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5473 .loc 1 2090 0 + 5474 009c 0120 movs r0, #1 + 5475 009e 2EE0 b .L372 + 5476 .LVL489: + 5477 .L373: +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5478 .loc 1 2079 0 + 5479 00a0 7B8D ldrh r3, [r7, #42] + 5480 00a2 3B85 strh r3, [r7, #40] + 5481 .LVL490: +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5482 .loc 1 2080 0 + 5483 00a4 8023 movs r3, #128 + 5484 00a6 9B04 lsls r3, r3, #18 + 5485 00a8 9846 mov r8, r3 + 5486 00aa E6E7 b .L374 + 5487 .LVL491: + 5488 .L376: +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 5489 .loc 1 2095 0 + 5490 00ac 4023 movs r3, #64 + 5491 00ae 0022 movs r2, #0 + 5492 00b0 FA54 strb r2, [r7, r3] +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5493 .loc 1 2096 0 + 5494 00b2 0320 movs r0, #3 + 5495 00b4 23E0 b .L372 + 5496 .L375: +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5497 .loc 1 2101 0 + 5498 00b6 3A8D ldrh r2, [r7, #40] + 5499 00b8 D2B2 uxtb r2, r2 + 5500 .LVL492: + 5501 .LBB248: + 5502 .LBB249: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5503 .loc 1 4713 0 + 5504 00ba 3968 ldr r1, [r7] + 5505 00bc 4B68 ldr r3, [r1, #4] + 5506 00be 184D ldr r5, .L386+8 + ARM GAS /tmp/ccpuPECZ.s page 196 + + + 5507 00c0 2B40 ands r3, r5 + 5508 00c2 A405 lsls r4, r4, #22 + 5509 .LVL493: + 5510 00c4 A40D lsrs r4, r4, #22 + 5511 00c6 1204 lsls r2, r2, #16 + 5512 .LVL494: + 5513 00c8 1443 orrs r4, r2 + 5514 00ca 4246 mov r2, r8 + 5515 00cc 2243 orrs r2, r4 + 5516 00ce 1400 movs r4, r2 + 5517 00d0 1C43 orrs r4, r3 + 5518 00d2 4C60 str r4, [r1, #4] + 5519 .LVL495: + 5520 .LBE249: + 5521 .LBE248: +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5522 .loc 1 2104 0 + 5523 00d4 4023 movs r3, #64 + 5524 00d6 0022 movs r2, #0 + 5525 00d8 FA54 strb r2, [r7, r3] + 5526 .LVL496: + 5527 .LBB250: + 5528 .LBB251: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 5529 .loc 1 4728 0 + 5530 00da 7B6B ldr r3, [r7, #52] + 5531 00dc 114A ldr r2, .L386+12 + 5532 00de 9342 cmp r3, r2 + 5533 00e0 0AD0 beq .L383 + 5534 00e2 114A ldr r2, .L386+16 + 5535 00e4 9342 cmp r3, r2 + 5536 00e6 05D0 beq .L385 + 5537 00e8 F221 movs r1, #242 + 5538 .L377: + 5539 .LVL497: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5540 .loc 1 4785 0 + 5541 00ea 3A68 ldr r2, [r7] + 5542 00ec 1368 ldr r3, [r2] + 5543 00ee 0B43 orrs r3, r1 + 5544 00f0 1360 str r3, [r2] + 5545 .LVL498: + 5546 .LBE251: + 5547 .LBE250: +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5548 .loc 1 2115 0 + 5549 00f2 04E0 b .L372 + 5550 .LVL499: + 5551 .L385: + 5552 .LBB253: + 5553 .LBB252: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 5554 .loc 1 4728 0 + 5555 00f4 0021 movs r1, #0 + 5556 00f6 F8E7 b .L377 + 5557 .L383: + 5558 00f8 0021 movs r1, #0 + ARM GAS /tmp/ccpuPECZ.s page 197 + + + 5559 00fa F6E7 b .L377 + 5560 .LVL500: + 5561 .L378: + 5562 .LBE252: + 5563 .LBE253: +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5564 .loc 1 2119 0 + 5565 00fc 0220 movs r0, #2 + 5566 .LVL501: + 5567 .L372: +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5568 .loc 1 2121 0 + 5569 00fe 05B0 add sp, sp, #20 + 5570 @ sp needed + 5571 .LVL502: + 5572 0100 0CBC pop {r2, r3} + 5573 0102 9046 mov r8, r2 + 5574 0104 9A46 mov r10, r3 + 5575 0106 F0BD pop {r4, r5, r6, r7, pc} + 5576 .LVL503: + 5577 .L379: +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5578 .loc 1 2048 0 + 5579 0108 0120 movs r0, #1 + 5580 .LVL504: + 5581 010a F8E7 b .L372 + 5582 .LVL505: + 5583 .L380: + 5584 010c 0120 movs r0, #1 + 5585 .LVL506: + 5586 010e F6E7 b .L372 + 5587 .LVL507: + 5588 .L381: +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5589 .loc 1 2053 0 + 5590 0110 0220 movs r0, #2 + 5591 .LVL508: + 5592 0112 F4E7 b .L372 + 5593 .LVL509: + 5594 .L382: +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5595 .loc 1 2057 0 + 5596 0114 0220 movs r0, #2 + 5597 .LVL510: + 5598 0116 F2E7 b .L372 + 5599 .L387: + 5600 .align 2 + 5601 .L386: + 5602 0118 0000FFFF .word -65536 + 5603 011c 00000000 .word I2C_Master_ISR_IT + 5604 0120 009C00FC .word -67068928 + 5605 0124 00000000 .word I2C_Master_ISR_DMA + 5606 0128 00000000 .word I2C_Slave_ISR_DMA + 5607 .cfi_endproc + 5608 .LFE57: + 5610 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 5611 .align 1 + ARM GAS /tmp/ccpuPECZ.s page 198 + + + 5612 .global HAL_I2C_Mem_Read_IT + 5613 .syntax unified + 5614 .code 16 + 5615 .thumb_func + 5616 .fpu softvfp + 5618 HAL_I2C_Mem_Read_IT: + 5619 .LFB58: +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 5620 .loc 1 2136 0 + 5621 .cfi_startproc + 5622 @ args = 8, pretend = 0, frame = 8 + 5623 @ frame_needed = 0, uses_anonymous_args = 0 + 5624 .LVL511: + 5625 0000 F0B5 push {r4, r5, r6, r7, lr} + 5626 .LCFI37: + 5627 .cfi_def_cfa_offset 20 + 5628 .cfi_offset 4, -20 + 5629 .cfi_offset 5, -16 + 5630 .cfi_offset 6, -12 + 5631 .cfi_offset 7, -8 + 5632 .cfi_offset 14, -4 + 5633 0002 D646 mov lr, r10 + 5634 0004 4746 mov r7, r8 + 5635 0006 80B5 push {r7, lr} + 5636 .LCFI38: + 5637 .cfi_def_cfa_offset 28 + 5638 .cfi_offset 8, -28 + 5639 .cfi_offset 10, -24 + 5640 0008 85B0 sub sp, sp, #20 + 5641 .LCFI39: + 5642 .cfi_def_cfa_offset 48 + 5643 000a 0700 movs r7, r0 + 5644 000c 0C00 movs r4, r1 + 5645 000e 0292 str r2, [sp, #8] + 5646 0010 0393 str r3, [sp, #12] + 5647 0012 0CAB add r3, sp, #48 + 5648 .LVL512: + 5649 0014 40CB ldmia r3!, {r6} + 5650 .LVL513: + 5651 0016 1D88 ldrh r5, [r3] + 5652 .LVL514: +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5653 .loc 1 2143 0 + 5654 0018 4123 movs r3, #65 + 5655 .LVL515: + 5656 001a C35C ldrb r3, [r0, r3] + 5657 001c 202B cmp r3, #32 + 5658 001e 70D1 bne .L395 +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5659 .loc 1 2145 0 + 5660 0020 002E cmp r6, #0 + 5661 0022 00D1 bne .LCB6150 + 5662 0024 73E0 b .L396 @long jump + 5663 .LCB6150: +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5664 .loc 1 2145 0 is_stmt 0 discriminator 1 + 5665 0026 002D cmp r5, #0 + ARM GAS /tmp/ccpuPECZ.s page 199 + + + 5666 0028 00D1 bne .LCB6152 + 5667 002a 72E0 b .L397 @long jump + 5668 .LCB6152: +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5669 .loc 1 2150 0 is_stmt 1 + 5670 002c 0368 ldr r3, [r0] + 5671 002e 9B69 ldr r3, [r3, #24] + 5672 0030 1B04 lsls r3, r3, #16 + 5673 0032 00D5 bpl .LCB6158 + 5674 0034 6FE0 b .L398 @long jump + 5675 .LCB6158: +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5676 .loc 1 2156 0 + 5677 0036 4023 movs r3, #64 + 5678 0038 C35C ldrb r3, [r0, r3] + 5679 003a 012B cmp r3, #1 + 5680 003c 00D1 bne .LCB6162 + 5681 003e 6CE0 b .L399 @long jump + 5682 .LCB6162: +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5683 .loc 1 2156 0 is_stmt 0 discriminator 2 + 5684 0040 4023 movs r3, #64 + 5685 0042 9A46 mov r10, r3 + 5686 0044 3F3B subs r3, r3, #63 + 5687 0046 5246 mov r2, r10 + 5688 .LVL516: + 5689 0048 8354 strb r3, [r0, r2] +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5690 .loc 1 2159 0 is_stmt 1 discriminator 2 + 5691 004a FFF7FEFF bl HAL_GetTick + 5692 .LVL517: +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5693 .loc 1 2161 0 discriminator 2 + 5694 004e 4123 movs r3, #65 + 5695 0050 2222 movs r2, #34 + 5696 0052 FA54 strb r2, [r7, r3] +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5697 .loc 1 2162 0 discriminator 2 + 5698 0054 0133 adds r3, r3, #1 + 5699 0056 5246 mov r2, r10 + 5700 0058 FA54 strb r2, [r7, r3] +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5701 .loc 1 2163 0 discriminator 2 + 5702 005a 0023 movs r3, #0 + 5703 005c 7B64 str r3, [r7, #68] +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5704 .loc 1 2166 0 discriminator 2 + 5705 005e 7E62 str r6, [r7, #36] +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5706 .loc 1 2167 0 discriminator 2 + 5707 0060 7D85 strh r5, [r7, #42] +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5708 .loc 1 2168 0 discriminator 2 + 5709 0062 2F4B ldr r3, .L403 + 5710 0064 FB62 str r3, [r7, #44] +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5711 .loc 1 2169 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 200 + + + 5712 0066 2F4B ldr r3, .L403+4 + 5713 0068 7B63 str r3, [r7, #52] +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5714 .loc 1 2171 0 discriminator 2 + 5715 006a 7B8D ldrh r3, [r7, #42] + 5716 006c 9BB2 uxth r3, r3 + 5717 006e FF2B cmp r3, #255 + 5718 0070 17D9 bls .L390 +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5719 .loc 1 2173 0 + 5720 0072 FF23 movs r3, #255 + 5721 0074 3B85 strh r3, [r7, #40] + 5722 .LVL518: +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5723 .loc 1 2174 0 + 5724 0076 8023 movs r3, #128 + 5725 0078 5B04 lsls r3, r3, #17 + 5726 007a 9846 mov r8, r3 + 5727 .LVL519: + 5728 .L391: +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5729 .loc 1 2183 0 + 5730 007c 0190 str r0, [sp, #4] + 5731 007e 1923 movs r3, #25 + 5732 0080 0093 str r3, [sp] + 5733 0082 039B ldr r3, [sp, #12] + 5734 0084 029A ldr r2, [sp, #8] + 5735 0086 2100 movs r1, r4 + 5736 0088 3800 movs r0, r7 + 5737 .LVL520: + 5738 008a FFF7FEFF bl I2C_RequestMemoryRead + 5739 .LVL521: + 5740 008e 0028 cmp r0, #0 + 5741 0090 12D0 beq .L392 +2185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5742 .loc 1 2185 0 + 5743 0092 7B6C ldr r3, [r7, #68] + 5744 0094 042B cmp r3, #4 + 5745 0096 0AD1 bne .L393 +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 5746 .loc 1 2188 0 + 5747 0098 3C33 adds r3, r3, #60 + 5748 009a 0022 movs r2, #0 + 5749 009c FA54 strb r2, [r7, r3] +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5750 .loc 1 2189 0 + 5751 009e 0120 movs r0, #1 + 5752 00a0 30E0 b .L389 + 5753 .LVL522: + 5754 .L390: +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5755 .loc 1 2178 0 + 5756 00a2 7B8D ldrh r3, [r7, #42] + 5757 00a4 3B85 strh r3, [r7, #40] + 5758 .LVL523: +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5759 .loc 1 2179 0 + ARM GAS /tmp/ccpuPECZ.s page 201 + + + 5760 00a6 8023 movs r3, #128 + 5761 00a8 9B04 lsls r3, r3, #18 + 5762 00aa 9846 mov r8, r3 + 5763 00ac E6E7 b .L391 + 5764 .LVL524: + 5765 .L393: +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 5766 .loc 1 2194 0 + 5767 00ae 4023 movs r3, #64 + 5768 00b0 0022 movs r2, #0 + 5769 00b2 FA54 strb r2, [r7, r3] +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5770 .loc 1 2195 0 + 5771 00b4 0320 movs r0, #3 + 5772 00b6 25E0 b .L389 + 5773 .L392: +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5774 .loc 1 2200 0 + 5775 00b8 3B8D ldrh r3, [r7, #40] + 5776 00ba DBB2 uxtb r3, r3 + 5777 .LVL525: + 5778 .LBB254: + 5779 .LBB255: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 5780 .loc 1 4713 0 + 5781 00bc 3968 ldr r1, [r7] + 5782 00be 4D68 ldr r5, [r1, #4] + 5783 00c0 194A ldr r2, .L403+8 + 5784 00c2 2A40 ands r2, r5 + 5785 00c4 A405 lsls r4, r4, #22 + 5786 .LVL526: + 5787 00c6 A40D lsrs r4, r4, #22 + 5788 00c8 1B04 lsls r3, r3, #16 + 5789 .LVL527: + 5790 00ca 1C43 orrs r4, r3 + 5791 00cc 4346 mov r3, r8 + 5792 00ce 2343 orrs r3, r4 + 5793 00d0 1C00 movs r4, r3 + 5794 00d2 164B ldr r3, .L403+12 + 5795 00d4 1C43 orrs r4, r3 + 5796 00d6 1443 orrs r4, r2 + 5797 00d8 4C60 str r4, [r1, #4] + 5798 .LVL528: + 5799 .LBE255: + 5800 .LBE254: +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5801 .loc 1 2203 0 + 5802 00da 4023 movs r3, #64 + 5803 00dc 0022 movs r2, #0 + 5804 00de FA54 strb r2, [r7, r3] + 5805 .LVL529: + 5806 .LBB256: + 5807 .LBB257: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 5808 .loc 1 4728 0 + 5809 00e0 7B6B ldr r3, [r7, #52] + 5810 00e2 134A ldr r2, .L403+16 + ARM GAS /tmp/ccpuPECZ.s page 202 + + + 5811 00e4 9342 cmp r3, r2 + 5812 00e6 0AD0 beq .L400 + 5813 00e8 124A ldr r2, .L403+20 + 5814 00ea 9342 cmp r3, r2 + 5815 00ec 05D0 beq .L402 + 5816 00ee F421 movs r1, #244 + 5817 .L394: + 5818 .LVL530: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5819 .loc 1 4785 0 + 5820 00f0 3A68 ldr r2, [r7] + 5821 00f2 1368 ldr r3, [r2] + 5822 00f4 0B43 orrs r3, r1 + 5823 00f6 1360 str r3, [r2] + 5824 .LVL531: + 5825 .LBE257: + 5826 .LBE256: +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5827 .loc 1 2214 0 + 5828 00f8 04E0 b .L389 + 5829 .LVL532: + 5830 .L402: + 5831 .LBB259: + 5832 .LBB258: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 5833 .loc 1 4728 0 + 5834 00fa 0021 movs r1, #0 + 5835 00fc F8E7 b .L394 + 5836 .L400: + 5837 00fe 0021 movs r1, #0 + 5838 0100 F6E7 b .L394 + 5839 .LVL533: + 5840 .L395: + 5841 .LBE258: + 5842 .LBE259: +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5843 .loc 1 2218 0 + 5844 0102 0220 movs r0, #2 + 5845 .LVL534: + 5846 .L389: +2220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /** + 5847 .loc 1 2220 0 + 5848 0104 05B0 add sp, sp, #20 + 5849 @ sp needed + 5850 .LVL535: + 5851 0106 0CBC pop {r2, r3} + 5852 0108 9046 mov r8, r2 + 5853 010a 9A46 mov r10, r3 + 5854 010c F0BD pop {r4, r5, r6, r7, pc} + 5855 .LVL536: + 5856 .L396: +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5857 .loc 1 2147 0 + 5858 010e 0120 movs r0, #1 + 5859 .LVL537: + 5860 0110 F8E7 b .L389 + 5861 .LVL538: + ARM GAS /tmp/ccpuPECZ.s page 203 + + + 5862 .L397: + 5863 0112 0120 movs r0, #1 + 5864 .LVL539: + 5865 0114 F6E7 b .L389 + 5866 .LVL540: + 5867 .L398: +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5868 .loc 1 2152 0 + 5869 0116 0220 movs r0, #2 + 5870 .LVL541: + 5871 0118 F4E7 b .L389 + 5872 .LVL542: + 5873 .L399: +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5874 .loc 1 2156 0 + 5875 011a 0220 movs r0, #2 + 5876 .LVL543: + 5877 011c F2E7 b .L389 + 5878 .L404: + 5879 011e C046 .align 2 + 5880 .L403: + 5881 0120 0000FFFF .word -65536 + 5882 0124 00000000 .word I2C_Master_ISR_IT + 5883 0128 009800FC .word -67069952 + 5884 012c 00240080 .word -2147474432 + 5885 0130 00000000 .word I2C_Master_ISR_DMA + 5886 0134 00000000 .word I2C_Slave_ISR_DMA + 5887 .cfi_endproc + 5888 .LFE58: + 5890 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 5891 .align 1 + 5892 .global HAL_I2C_Mem_Write_DMA + 5893 .syntax unified + 5894 .code 16 + 5895 .thumb_func + 5896 .fpu softvfp + 5898 HAL_I2C_Mem_Write_DMA: + 5899 .LFB59: +2234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 5900 .loc 1 2234 0 + 5901 .cfi_startproc + 5902 @ args = 8, pretend = 0, frame = 16 + 5903 @ frame_needed = 0, uses_anonymous_args = 0 + 5904 .LVL544: + 5905 0000 F0B5 push {r4, r5, r6, r7, lr} + 5906 .LCFI40: + 5907 .cfi_def_cfa_offset 20 + 5908 .cfi_offset 4, -20 + 5909 .cfi_offset 5, -16 + 5910 .cfi_offset 6, -12 + 5911 .cfi_offset 7, -8 + 5912 .cfi_offset 14, -4 + 5913 0002 CE46 mov lr, r9 + 5914 0004 00B5 push {lr} + 5915 .LCFI41: + 5916 .cfi_def_cfa_offset 24 + 5917 .cfi_offset 9, -24 + ARM GAS /tmp/ccpuPECZ.s page 204 + + + 5918 0006 86B0 sub sp, sp, #24 + 5919 .LCFI42: + 5920 .cfi_def_cfa_offset 48 + 5921 0008 0400 movs r4, r0 + 5922 000a 0391 str r1, [sp, #12] + 5923 000c 0492 str r2, [sp, #16] + 5924 000e 0593 str r3, [sp, #20] + 5925 0010 0CAB add r3, sp, #48 + 5926 .LVL545: + 5927 0012 20CB ldmia r3!, {r5} + 5928 .LVL546: + 5929 0014 1E88 ldrh r6, [r3] + 5930 .LVL547: +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5931 .loc 1 2241 0 + 5932 0016 4123 movs r3, #65 + 5933 .LVL548: + 5934 0018 C35C ldrb r3, [r0, r3] + 5935 001a 202B cmp r3, #32 + 5936 001c 00D0 beq .LCB6466 + 5937 001e 88E0 b .L412 @long jump + 5938 .LCB6466: +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5939 .loc 1 2243 0 + 5940 0020 002D cmp r5, #0 + 5941 0022 00D1 bne .LCB6468 + 5942 0024 8BE0 b .L413 @long jump + 5943 .LCB6468: +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5944 .loc 1 2243 0 is_stmt 0 discriminator 1 + 5945 0026 002E cmp r6, #0 + 5946 0028 00D1 bne .LCB6470 + 5947 002a 8AE0 b .L414 @long jump + 5948 .LCB6470: +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5949 .loc 1 2248 0 is_stmt 1 + 5950 002c 0368 ldr r3, [r0] + 5951 002e 9B69 ldr r3, [r3, #24] + 5952 0030 1B04 lsls r3, r3, #16 + 5953 0032 00D5 bpl .LCB6476 + 5954 0034 87E0 b .L415 @long jump + 5955 .LCB6476: +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5956 .loc 1 2254 0 + 5957 0036 4023 movs r3, #64 + 5958 0038 C35C ldrb r3, [r0, r3] + 5959 003a 012B cmp r3, #1 + 5960 003c 00D1 bne .LCB6480 + 5961 003e 84E0 b .L416 @long jump + 5962 .LCB6480: +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5963 .loc 1 2254 0 is_stmt 0 discriminator 2 + 5964 0040 4027 movs r7, #64 + 5965 0042 0123 movs r3, #1 + 5966 0044 C355 strb r3, [r0, r7] +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5967 .loc 1 2257 0 is_stmt 1 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 205 + + + 5968 0046 FFF7FEFF bl HAL_GetTick + 5969 .LVL549: +2259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5970 .loc 1 2259 0 discriminator 2 + 5971 004a 4123 movs r3, #65 + 5972 004c 2122 movs r2, #33 + 5973 004e E254 strb r2, [r4, r3] +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5974 .loc 1 2260 0 discriminator 2 + 5975 0050 0133 adds r3, r3, #1 + 5976 0052 E754 strb r7, [r4, r3] +2261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5977 .loc 1 2261 0 discriminator 2 + 5978 0054 0023 movs r3, #0 + 5979 0056 6364 str r3, [r4, #68] +2264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5980 .loc 1 2264 0 discriminator 2 + 5981 0058 6562 str r5, [r4, #36] +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5982 .loc 1 2265 0 discriminator 2 + 5983 005a 6685 strh r6, [r4, #42] +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 5984 .loc 1 2266 0 discriminator 2 + 5985 005c 3C4B ldr r3, .L420 + 5986 005e E362 str r3, [r4, #44] +2267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 5987 .loc 1 2267 0 discriminator 2 + 5988 0060 3C4B ldr r3, .L420+4 + 5989 0062 6363 str r3, [r4, #52] +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 5990 .loc 1 2269 0 discriminator 2 + 5991 0064 638D ldrh r3, [r4, #42] + 5992 0066 9BB2 uxth r3, r3 + 5993 0068 FF2B cmp r3, #255 + 5994 006a 17D9 bls .L407 +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5995 .loc 1 2271 0 + 5996 006c FF23 movs r3, #255 + 5997 006e 2385 strh r3, [r4, #40] + 5998 .LVL550: +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 5999 .loc 1 2272 0 + 6000 0070 8023 movs r3, #128 + 6001 0072 5B04 lsls r3, r3, #17 + 6002 0074 9946 mov r9, r3 + 6003 .LVL551: + 6004 .L408: +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6005 .loc 1 2281 0 + 6006 0076 0190 str r0, [sp, #4] + 6007 0078 1923 movs r3, #25 + 6008 007a 0093 str r3, [sp] + 6009 007c 059B ldr r3, [sp, #20] + 6010 007e 049A ldr r2, [sp, #16] + 6011 0080 0399 ldr r1, [sp, #12] + 6012 0082 2000 movs r0, r4 + 6013 .LVL552: + ARM GAS /tmp/ccpuPECZ.s page 206 + + + 6014 0084 FFF7FEFF bl I2C_RequestMemoryWrite + 6015 .LVL553: + 6016 0088 061E subs r6, r0, #0 + 6017 008a 12D0 beq .L409 +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6018 .loc 1 2283 0 + 6019 008c 636C ldr r3, [r4, #68] + 6020 008e 042B cmp r3, #4 + 6021 0090 0AD1 bne .L410 +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 6022 .loc 1 2286 0 + 6023 0092 3C33 adds r3, r3, #60 + 6024 0094 0022 movs r2, #0 + 6025 0096 E254 strb r2, [r4, r3] +2287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6026 .loc 1 2287 0 + 6027 0098 0126 movs r6, #1 + 6028 009a 4BE0 b .L406 + 6029 .LVL554: + 6030 .L407: +2276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6031 .loc 1 2276 0 + 6032 009c 638D ldrh r3, [r4, #42] + 6033 009e 2385 strh r3, [r4, #40] + 6034 .LVL555: +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6035 .loc 1 2277 0 + 6036 00a0 8023 movs r3, #128 + 6037 00a2 9B04 lsls r3, r3, #18 + 6038 00a4 9946 mov r9, r3 + 6039 00a6 E6E7 b .L408 + 6040 .LVL556: + 6041 .L410: +2292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 6042 .loc 1 2292 0 + 6043 00a8 4023 movs r3, #64 + 6044 00aa 0022 movs r2, #0 + 6045 00ac E254 strb r2, [r4, r3] +2293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6046 .loc 1 2293 0 + 6047 00ae 0326 movs r6, #3 + 6048 00b0 40E0 b .L406 + 6049 .L409: +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6050 .loc 1 2298 0 + 6051 00b2 A36B ldr r3, [r4, #56] + 6052 00b4 284A ldr r2, .L420+8 + 6053 00b6 DA62 str r2, [r3, #44] +2301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6054 .loc 1 2301 0 + 6055 00b8 A36B ldr r3, [r4, #56] + 6056 00ba 284A ldr r2, .L420+12 + 6057 00bc 5A63 str r2, [r3, #52] +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6058 .loc 1 2304 0 + 6059 00be A36B ldr r3, [r4, #56] + 6060 00c0 0027 movs r7, #0 + ARM GAS /tmp/ccpuPECZ.s page 207 + + + 6061 00c2 1F63 str r7, [r3, #48] +2305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6062 .loc 1 2305 0 + 6063 00c4 A36B ldr r3, [r4, #56] + 6064 00c6 9F63 str r7, [r3, #56] +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6065 .loc 1 2308 0 + 6066 00c8 2268 ldr r2, [r4] + 6067 00ca 2832 adds r2, r2, #40 + 6068 00cc 238D ldrh r3, [r4, #40] + 6069 00ce 2900 movs r1, r5 + 6070 00d0 A06B ldr r0, [r4, #56] + 6071 00d2 FFF7FEFF bl HAL_DMA_Start_IT + 6072 .LVL557: +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6073 .loc 1 2312 0 + 6074 00d6 218D ldrh r1, [r4, #40] + 6075 00d8 C9B2 uxtb r1, r1 + 6076 .LVL558: + 6077 .LBB260: + 6078 .LBB261: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 6079 .loc 1 4713 0 + 6080 00da 2268 ldr r2, [r4] + 6081 00dc 5368 ldr r3, [r2, #4] + 6082 00de 2048 ldr r0, .L420+16 + 6083 00e0 0340 ands r3, r0 + 6084 00e2 0398 ldr r0, [sp, #12] + 6085 00e4 8505 lsls r5, r0, #22 + 6086 00e6 AD0D lsrs r5, r5, #22 + 6087 00e8 0904 lsls r1, r1, #16 + 6088 .LVL559: + 6089 00ea 0D43 orrs r5, r1 + 6090 00ec 4946 mov r1, r9 + 6091 00ee 2943 orrs r1, r5 + 6092 00f0 0D00 movs r5, r1 + 6093 00f2 1D43 orrs r5, r3 + 6094 00f4 5560 str r5, [r2, #4] + 6095 .LVL560: + 6096 .LBE261: + 6097 .LBE260: +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6098 .loc 1 2315 0 + 6099 00f6 638D ldrh r3, [r4, #42] + 6100 00f8 228D ldrh r2, [r4, #40] + 6101 00fa 9B1A subs r3, r3, r2 + 6102 00fc 9BB2 uxth r3, r3 + 6103 00fe 6385 strh r3, [r4, #42] +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6104 .loc 1 2318 0 + 6105 0100 4023 movs r3, #64 + 6106 0102 E754 strb r7, [r4, r3] + 6107 .LVL561: + 6108 .LBB262: + 6109 .LBB263: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6110 .loc 1 4728 0 + ARM GAS /tmp/ccpuPECZ.s page 208 + + + 6111 0104 636B ldr r3, [r4, #52] + 6112 0106 134A ldr r2, .L420+4 + 6113 0108 9342 cmp r3, r2 + 6114 010a 10D0 beq .L417 + 6115 010c 154A ldr r2, .L420+20 + 6116 010e 9342 cmp r3, r2 + 6117 0110 0BD0 beq .L419 + 6118 0112 F221 movs r1, #242 + 6119 .L411: + 6120 .LVL562: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6121 .loc 1 4785 0 + 6122 0114 2268 ldr r2, [r4] + 6123 0116 1368 ldr r3, [r2] + 6124 0118 0B43 orrs r3, r1 + 6125 011a 1360 str r3, [r2] + 6126 .LVL563: + 6127 .LBE263: + 6128 .LBE262: +2327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6129 .loc 1 2327 0 + 6130 011c 2268 ldr r2, [r4] + 6131 011e 1168 ldr r1, [r2] + 6132 0120 8023 movs r3, #128 + 6133 0122 DB01 lsls r3, r3, #7 + 6134 0124 0B43 orrs r3, r1 + 6135 0126 1360 str r3, [r2] +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6136 .loc 1 2329 0 + 6137 0128 04E0 b .L406 + 6138 .LVL564: + 6139 .L419: + 6140 .LBB265: + 6141 .LBB264: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6142 .loc 1 4728 0 + 6143 012a 9021 movs r1, #144 + 6144 012c F2E7 b .L411 + 6145 .L417: + 6146 012e 9021 movs r1, #144 + 6147 0130 F0E7 b .L411 + 6148 .LVL565: + 6149 .L412: + 6150 .LBE264: + 6151 .LBE265: +2333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6152 .loc 1 2333 0 + 6153 0132 0226 movs r6, #2 + 6154 .LVL566: + 6155 .L406: +2335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6156 .loc 1 2335 0 + 6157 0134 3000 movs r0, r6 + 6158 0136 06B0 add sp, sp, #24 + 6159 @ sp needed + 6160 .LVL567: + 6161 0138 04BC pop {r2} + ARM GAS /tmp/ccpuPECZ.s page 209 + + + 6162 013a 9146 mov r9, r2 + 6163 013c F0BD pop {r4, r5, r6, r7, pc} + 6164 .LVL568: + 6165 .L413: +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6166 .loc 1 2245 0 + 6167 013e 0126 movs r6, #1 + 6168 0140 F8E7 b .L406 + 6169 .L414: + 6170 0142 0126 movs r6, #1 + 6171 0144 F6E7 b .L406 + 6172 .L415: +2250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6173 .loc 1 2250 0 + 6174 0146 0226 movs r6, #2 + 6175 0148 F4E7 b .L406 + 6176 .L416: +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6177 .loc 1 2254 0 + 6178 014a 0226 movs r6, #2 + 6179 014c F2E7 b .L406 + 6180 .L421: + 6181 014e C046 .align 2 + 6182 .L420: + 6183 0150 0000FFFF .word -65536 + 6184 0154 00000000 .word I2C_Master_ISR_DMA + 6185 0158 00000000 .word I2C_DMAMasterTransmitCplt + 6186 015c 00000000 .word I2C_DMAError + 6187 0160 009C00FC .word -67068928 + 6188 0164 00000000 .word I2C_Slave_ISR_DMA + 6189 .cfi_endproc + 6190 .LFE59: + 6192 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 6193 .align 1 + 6194 .global HAL_I2C_Mem_Read_DMA + 6195 .syntax unified + 6196 .code 16 + 6197 .thumb_func + 6198 .fpu softvfp + 6200 HAL_I2C_Mem_Read_DMA: + 6201 .LFB60: +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 6202 .loc 1 2350 0 + 6203 .cfi_startproc + 6204 @ args = 8, pretend = 0, frame = 16 + 6205 @ frame_needed = 0, uses_anonymous_args = 0 + 6206 .LVL569: + 6207 0000 F0B5 push {r4, r5, r6, r7, lr} + 6208 .LCFI43: + 6209 .cfi_def_cfa_offset 20 + 6210 .cfi_offset 4, -20 + 6211 .cfi_offset 5, -16 + 6212 .cfi_offset 6, -12 + 6213 .cfi_offset 7, -8 + 6214 .cfi_offset 14, -4 + 6215 0002 CE46 mov lr, r9 + 6216 0004 00B5 push {lr} + ARM GAS /tmp/ccpuPECZ.s page 210 + + + 6217 .LCFI44: + 6218 .cfi_def_cfa_offset 24 + 6219 .cfi_offset 9, -24 + 6220 0006 86B0 sub sp, sp, #24 + 6221 .LCFI45: + 6222 .cfi_def_cfa_offset 48 + 6223 0008 0400 movs r4, r0 + 6224 000a 0391 str r1, [sp, #12] + 6225 000c 0492 str r2, [sp, #16] + 6226 000e 0593 str r3, [sp, #20] + 6227 0010 0CAB add r3, sp, #48 + 6228 .LVL570: + 6229 0012 20CB ldmia r3!, {r5} + 6230 .LVL571: + 6231 0014 1E88 ldrh r6, [r3] + 6232 .LVL572: +2357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6233 .loc 1 2357 0 + 6234 0016 4123 movs r3, #65 + 6235 .LVL573: + 6236 0018 C35C ldrb r3, [r0, r3] + 6237 001a 202B cmp r3, #32 + 6238 001c 00D0 beq .LCB6804 + 6239 001e 8AE0 b .L429 @long jump + 6240 .LCB6804: +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6241 .loc 1 2359 0 + 6242 0020 002D cmp r5, #0 + 6243 0022 00D1 bne .LCB6806 + 6244 0024 8DE0 b .L430 @long jump + 6245 .LCB6806: +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6246 .loc 1 2359 0 is_stmt 0 discriminator 1 + 6247 0026 002E cmp r6, #0 + 6248 0028 00D1 bne .LCB6808 + 6249 002a 8CE0 b .L431 @long jump + 6250 .LCB6808: +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6251 .loc 1 2364 0 is_stmt 1 + 6252 002c 0368 ldr r3, [r0] + 6253 002e 9B69 ldr r3, [r3, #24] + 6254 0030 1B04 lsls r3, r3, #16 + 6255 0032 00D5 bpl .LCB6814 + 6256 0034 89E0 b .L432 @long jump + 6257 .LCB6814: +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6258 .loc 1 2370 0 + 6259 0036 4023 movs r3, #64 + 6260 0038 C35C ldrb r3, [r0, r3] + 6261 003a 012B cmp r3, #1 + 6262 003c 00D1 bne .LCB6818 + 6263 003e 86E0 b .L433 @long jump + 6264 .LCB6818: +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6265 .loc 1 2370 0 is_stmt 0 discriminator 2 + 6266 0040 4027 movs r7, #64 + 6267 0042 0123 movs r3, #1 + ARM GAS /tmp/ccpuPECZ.s page 211 + + + 6268 0044 C355 strb r3, [r0, r7] +2373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6269 .loc 1 2373 0 is_stmt 1 discriminator 2 + 6270 0046 FFF7FEFF bl HAL_GetTick + 6271 .LVL574: +2375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6272 .loc 1 2375 0 discriminator 2 + 6273 004a 4123 movs r3, #65 + 6274 004c 2222 movs r2, #34 + 6275 004e E254 strb r2, [r4, r3] +2376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6276 .loc 1 2376 0 discriminator 2 + 6277 0050 0133 adds r3, r3, #1 + 6278 0052 E754 strb r7, [r4, r3] +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6279 .loc 1 2377 0 discriminator 2 + 6280 0054 0023 movs r3, #0 + 6281 0056 6364 str r3, [r4, #68] +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6282 .loc 1 2380 0 discriminator 2 + 6283 0058 6562 str r5, [r4, #36] +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6284 .loc 1 2381 0 discriminator 2 + 6285 005a 6685 strh r6, [r4, #42] +2382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6286 .loc 1 2382 0 discriminator 2 + 6287 005c 3D4B ldr r3, .L437 + 6288 005e E362 str r3, [r4, #44] +2383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6289 .loc 1 2383 0 discriminator 2 + 6290 0060 3D4B ldr r3, .L437+4 + 6291 0062 6363 str r3, [r4, #52] +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6292 .loc 1 2385 0 discriminator 2 + 6293 0064 638D ldrh r3, [r4, #42] + 6294 0066 9BB2 uxth r3, r3 + 6295 0068 FF2B cmp r3, #255 + 6296 006a 17D9 bls .L424 +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6297 .loc 1 2387 0 + 6298 006c FF23 movs r3, #255 + 6299 006e 2385 strh r3, [r4, #40] + 6300 .LVL575: +2388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6301 .loc 1 2388 0 + 6302 0070 8023 movs r3, #128 + 6303 0072 5B04 lsls r3, r3, #17 + 6304 0074 9946 mov r9, r3 + 6305 .LVL576: + 6306 .L425: +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6307 .loc 1 2397 0 + 6308 0076 0190 str r0, [sp, #4] + 6309 0078 1923 movs r3, #25 + 6310 007a 0093 str r3, [sp] + 6311 007c 059B ldr r3, [sp, #20] + 6312 007e 049A ldr r2, [sp, #16] + ARM GAS /tmp/ccpuPECZ.s page 212 + + + 6313 0080 0399 ldr r1, [sp, #12] + 6314 0082 2000 movs r0, r4 + 6315 .LVL577: + 6316 0084 FFF7FEFF bl I2C_RequestMemoryRead + 6317 .LVL578: + 6318 0088 061E subs r6, r0, #0 + 6319 008a 12D0 beq .L426 +2399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6320 .loc 1 2399 0 + 6321 008c 636C ldr r3, [r4, #68] + 6322 008e 042B cmp r3, #4 + 6323 0090 0AD1 bne .L427 +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_ERROR; + 6324 .loc 1 2402 0 + 6325 0092 3C33 adds r3, r3, #60 + 6326 0094 0022 movs r2, #0 + 6327 0096 E254 strb r2, [r4, r3] +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6328 .loc 1 2403 0 + 6329 0098 0126 movs r6, #1 + 6330 009a 4DE0 b .L423 + 6331 .LVL579: + 6332 .L424: +2392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6333 .loc 1 2392 0 + 6334 009c 638D ldrh r3, [r4, #42] + 6335 009e 2385 strh r3, [r4, #40] + 6336 .LVL580: +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6337 .loc 1 2393 0 + 6338 00a0 8023 movs r3, #128 + 6339 00a2 9B04 lsls r3, r3, #18 + 6340 00a4 9946 mov r9, r3 + 6341 00a6 E6E7 b .L425 + 6342 .LVL581: + 6343 .L427: +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 6344 .loc 1 2408 0 + 6345 00a8 4023 movs r3, #64 + 6346 00aa 0022 movs r2, #0 + 6347 00ac E254 strb r2, [r4, r3] +2409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6348 .loc 1 2409 0 + 6349 00ae 0326 movs r6, #3 + 6350 00b0 42E0 b .L423 + 6351 .L426: +2414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6352 .loc 1 2414 0 + 6353 00b2 E36B ldr r3, [r4, #60] + 6354 00b4 294A ldr r2, .L437+8 + 6355 00b6 DA62 str r2, [r3, #44] +2417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6356 .loc 1 2417 0 + 6357 00b8 E36B ldr r3, [r4, #60] + 6358 00ba 294A ldr r2, .L437+12 + 6359 00bc 5A63 str r2, [r3, #52] +2420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + ARM GAS /tmp/ccpuPECZ.s page 213 + + + 6360 .loc 1 2420 0 + 6361 00be E36B ldr r3, [r4, #60] + 6362 00c0 0027 movs r7, #0 + 6363 00c2 1F63 str r7, [r3, #48] +2421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6364 .loc 1 2421 0 + 6365 00c4 E36B ldr r3, [r4, #60] + 6366 00c6 9F63 str r7, [r3, #56] +2424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6367 .loc 1 2424 0 + 6368 00c8 2168 ldr r1, [r4] + 6369 00ca 2431 adds r1, r1, #36 + 6370 00cc 238D ldrh r3, [r4, #40] + 6371 00ce 2A00 movs r2, r5 + 6372 00d0 E06B ldr r0, [r4, #60] + 6373 00d2 FFF7FEFF bl HAL_DMA_Start_IT + 6374 .LVL582: +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6375 .loc 1 2427 0 + 6376 00d6 238D ldrh r3, [r4, #40] + 6377 00d8 DBB2 uxtb r3, r3 + 6378 .LVL583: + 6379 .LBB266: + 6380 .LBB267: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 6381 .loc 1 4713 0 + 6382 00da 2268 ldr r2, [r4] + 6383 00dc 5068 ldr r0, [r2, #4] + 6384 00de 2149 ldr r1, .L437+16 + 6385 00e0 0140 ands r1, r0 + 6386 00e2 0398 ldr r0, [sp, #12] + 6387 00e4 8505 lsls r5, r0, #22 + 6388 00e6 AD0D lsrs r5, r5, #22 + 6389 00e8 1B04 lsls r3, r3, #16 + 6390 .LVL584: + 6391 00ea 1D43 orrs r5, r3 + 6392 00ec 4B46 mov r3, r9 + 6393 00ee 2B43 orrs r3, r5 + 6394 00f0 1D00 movs r5, r3 + 6395 00f2 1D4B ldr r3, .L437+20 + 6396 00f4 1D43 orrs r5, r3 + 6397 00f6 0D43 orrs r5, r1 + 6398 00f8 5560 str r5, [r2, #4] + 6399 .LVL585: + 6400 .LBE267: + 6401 .LBE266: +2430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6402 .loc 1 2430 0 + 6403 00fa 638D ldrh r3, [r4, #42] + 6404 00fc 228D ldrh r2, [r4, #40] + 6405 00fe 9B1A subs r3, r3, r2 + 6406 0100 9BB2 uxth r3, r3 + 6407 0102 6385 strh r3, [r4, #42] +2433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6408 .loc 1 2433 0 + 6409 0104 4023 movs r3, #64 + 6410 0106 E754 strb r7, [r4, r3] + ARM GAS /tmp/ccpuPECZ.s page 214 + + +2436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6411 .loc 1 2436 0 + 6412 0108 2268 ldr r2, [r4] + 6413 010a 1168 ldr r1, [r2] + 6414 010c 8023 movs r3, #128 + 6415 010e 1B02 lsls r3, r3, #8 + 6416 0110 0B43 orrs r3, r1 + 6417 0112 1360 str r3, [r2] + 6418 .LVL586: + 6419 .LBB268: + 6420 .LBB269: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6421 .loc 1 4728 0 + 6422 0114 636B ldr r3, [r4, #52] + 6423 0116 104A ldr r2, .L437+4 + 6424 0118 9342 cmp r3, r2 + 6425 011a 0AD0 beq .L434 + 6426 011c 134A ldr r2, .L437+24 + 6427 011e 9342 cmp r3, r2 + 6428 0120 05D0 beq .L436 + 6429 0122 F221 movs r1, #242 + 6430 .L428: + 6431 .LVL587: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6432 .loc 1 4785 0 + 6433 0124 2268 ldr r2, [r4] + 6434 0126 1368 ldr r3, [r2] + 6435 0128 0B43 orrs r3, r1 + 6436 012a 1360 str r3, [r2] + 6437 .LVL588: + 6438 .LBE269: + 6439 .LBE268: +2444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6440 .loc 1 2444 0 + 6441 012c 04E0 b .L423 + 6442 .LVL589: + 6443 .L436: + 6444 .LBB271: + 6445 .LBB270: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6446 .loc 1 4728 0 + 6447 012e 9021 movs r1, #144 + 6448 0130 F8E7 b .L428 + 6449 .L434: + 6450 0132 9021 movs r1, #144 + 6451 0134 F6E7 b .L428 + 6452 .LVL590: + 6453 .L429: + 6454 .LBE270: + 6455 .LBE271: +2448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6456 .loc 1 2448 0 + 6457 0136 0226 movs r6, #2 + 6458 .LVL591: + 6459 .L423: +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6460 .loc 1 2450 0 + ARM GAS /tmp/ccpuPECZ.s page 215 + + + 6461 0138 3000 movs r0, r6 + 6462 013a 06B0 add sp, sp, #24 + 6463 @ sp needed + 6464 .LVL592: + 6465 013c 04BC pop {r2} + 6466 013e 9146 mov r9, r2 + 6467 0140 F0BD pop {r4, r5, r6, r7, pc} + 6468 .LVL593: + 6469 .L430: +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6470 .loc 1 2361 0 + 6471 0142 0126 movs r6, #1 + 6472 0144 F8E7 b .L423 + 6473 .L431: + 6474 0146 0126 movs r6, #1 + 6475 0148 F6E7 b .L423 + 6476 .L432: +2366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6477 .loc 1 2366 0 + 6478 014a 0226 movs r6, #2 + 6479 014c F4E7 b .L423 + 6480 .L433: +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6481 .loc 1 2370 0 + 6482 014e 0226 movs r6, #2 + 6483 0150 F2E7 b .L423 + 6484 .L438: + 6485 0152 C046 .align 2 + 6486 .L437: + 6487 0154 0000FFFF .word -65536 + 6488 0158 00000000 .word I2C_Master_ISR_DMA + 6489 015c 00000000 .word I2C_DMAMasterReceiveCplt + 6490 0160 00000000 .word I2C_DMAError + 6491 0164 009800FC .word -67069952 + 6492 0168 00240080 .word -2147474432 + 6493 016c 00000000 .word I2C_Slave_ISR_DMA + 6494 .cfi_endproc + 6495 .LFE60: + 6497 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 6498 .align 1 + 6499 .global HAL_I2C_IsDeviceReady + 6500 .syntax unified + 6501 .code 16 + 6502 .thumb_func + 6503 .fpu softvfp + 6505 HAL_I2C_IsDeviceReady: + 6506 .LFB61: +2464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t tickstart = 0U; + 6507 .loc 1 2464 0 + 6508 .cfi_startproc + 6509 @ args = 0, pretend = 0, frame = 8 + 6510 @ frame_needed = 0, uses_anonymous_args = 0 + 6511 .LVL594: + 6512 0000 F0B5 push {r4, r5, r6, r7, lr} + 6513 .LCFI46: + 6514 .cfi_def_cfa_offset 20 + 6515 .cfi_offset 4, -20 + ARM GAS /tmp/ccpuPECZ.s page 216 + + + 6516 .cfi_offset 5, -16 + 6517 .cfi_offset 6, -12 + 6518 .cfi_offset 7, -8 + 6519 .cfi_offset 14, -4 + 6520 0002 C646 mov lr, r8 + 6521 0004 00B5 push {lr} + 6522 .LCFI47: + 6523 .cfi_def_cfa_offset 24 + 6524 .cfi_offset 8, -24 + 6525 0006 84B0 sub sp, sp, #16 + 6526 .LCFI48: + 6527 .cfi_def_cfa_offset 40 + 6528 0008 0400 movs r4, r0 + 6529 000a 8846 mov r8, r1 + 6530 000c 1700 movs r7, r2 + 6531 000e 1D00 movs r5, r3 + 6532 .LVL595: +2467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6533 .loc 1 2467 0 + 6534 0010 0023 movs r3, #0 + 6535 .LVL596: + 6536 0012 0393 str r3, [sp, #12] +2469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6537 .loc 1 2469 0 + 6538 0014 4133 adds r3, r3, #65 + 6539 0016 C35C ldrb r3, [r0, r3] + 6540 0018 202B cmp r3, #32 + 6541 001a 00D0 beq .LCB7135 + 6542 001c 8BE0 b .L451 @long jump + 6543 .LCB7135: +2471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6544 .loc 1 2471 0 + 6545 001e 0368 ldr r3, [r0] + 6546 0020 9B69 ldr r3, [r3, #24] + 6547 0022 1B04 lsls r3, r3, #16 + 6548 0024 00D5 bpl .LCB7141 + 6549 0026 8BE0 b .L452 @long jump + 6550 .LCB7141: +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6551 .loc 1 2477 0 + 6552 0028 4023 movs r3, #64 + 6553 002a C35C ldrb r3, [r0, r3] + 6554 002c 012B cmp r3, #1 + 6555 002e 00D1 bne .LCB7145 + 6556 0030 88E0 b .L453 @long jump + 6557 .LCB7145: +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6558 .loc 1 2477 0 is_stmt 0 discriminator 2 + 6559 0032 4023 movs r3, #64 + 6560 0034 0122 movs r2, #1 + 6561 .LVL597: + 6562 0036 C254 strb r2, [r0, r3] +2479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6563 .loc 1 2479 0 is_stmt 1 discriminator 2 + 6564 0038 0133 adds r3, r3, #1 + 6565 003a 2332 adds r2, r2, #35 + 6566 003c C254 strb r2, [r0, r3] + ARM GAS /tmp/ccpuPECZ.s page 217 + + +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6567 .loc 1 2480 0 discriminator 2 + 6568 003e 0023 movs r3, #0 + 6569 0040 4364 str r3, [r0, #68] + 6570 0042 20E0 b .L450 + 6571 .LVL598: + 6572 .L460: +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6573 .loc 1 2485 0 discriminator 1 + 6574 0044 4346 mov r3, r8 + 6575 0046 9A05 lsls r2, r3, #22 + 6576 0048 920D lsrs r2, r2, #22 + 6577 004a 424B ldr r3, .L461 + 6578 004c 1343 orrs r3, r2 + 6579 004e 23E0 b .L442 + 6580 .LVL599: + 6581 .L446: +2506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6582 .loc 1 2506 0 + 6583 0050 9369 ldr r3, [r2, #24] + 6584 0052 DB06 lsls r3, r3, #27 + 6585 0054 42D5 bpl .L457 +2528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6586 .loc 1 2528 0 + 6587 0056 0096 str r6, [sp] + 6588 0058 2B00 movs r3, r5 + 6589 005a 0022 movs r2, #0 + 6590 005c 2021 movs r1, #32 + 6591 005e 2000 movs r0, r4 + 6592 0060 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6593 .LVL600: + 6594 0064 0028 cmp r0, #0 + 6595 0066 00D0 beq .LCB7187 + 6596 0068 70E0 b .L455 @long jump + 6597 .LCB7187: +2534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6598 .loc 1 2534 0 + 6599 006a 2368 ldr r3, [r4] + 6600 006c 1022 movs r2, #16 + 6601 006e DA61 str r2, [r3, #28] +2537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6602 .loc 1 2537 0 + 6603 0070 2368 ldr r3, [r4] + 6604 0072 1032 adds r2, r2, #16 + 6605 0074 DA61 str r2, [r3, #28] +2541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6606 .loc 1 2541 0 + 6607 0076 039B ldr r3, [sp, #12] + 6608 0078 5A1C adds r2, r3, #1 + 6609 007a 0392 str r2, [sp, #12] + 6610 007c BB42 cmp r3, r7 + 6611 007e 3FD0 beq .L458 + 6612 .L449: +2556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6613 .loc 1 2556 0 + 6614 0080 039B ldr r3, [sp, #12] + 6615 0082 BB42 cmp r3, r7 + ARM GAS /tmp/ccpuPECZ.s page 218 + + + 6616 0084 4FD2 bcs .L459 + 6617 .LVL601: + 6618 .L450: +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6619 .loc 1 2485 0 + 6620 0086 E368 ldr r3, [r4, #12] + 6621 0088 012B cmp r3, #1 + 6622 008a DBD0 beq .L460 +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6623 .loc 1 2485 0 is_stmt 0 discriminator 2 + 6624 008c 4346 mov r3, r8 + 6625 008e 9A05 lsls r2, r3, #22 + 6626 0090 920D lsrs r2, r2, #22 + 6627 0092 A023 movs r3, #160 + 6628 0094 9B01 lsls r3, r3, #6 + 6629 0096 1343 orrs r3, r2 + 6630 .L442: +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6631 .loc 1 2485 0 discriminator 4 + 6632 0098 2268 ldr r2, [r4] + 6633 009a 5360 str r3, [r2, #4] +2489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_F + 6634 .loc 1 2489 0 is_stmt 1 discriminator 4 + 6635 009c FFF7FEFF bl HAL_GetTick + 6636 .LVL602: + 6637 00a0 0600 movs r6, r0 + 6638 .LVL603: + 6639 .L444: +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6640 .loc 1 2490 0 + 6641 00a2 2268 ldr r2, [r4] + 6642 00a4 9369 ldr r3, [r2, #24] + 6643 00a6 9B06 lsls r3, r3, #26 + 6644 00a8 D2D4 bmi .L446 +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6645 .loc 1 2490 0 is_stmt 0 discriminator 1 + 6646 00aa 9369 ldr r3, [r2, #24] + 6647 00ac DB06 lsls r3, r3, #27 + 6648 00ae CFD4 bmi .L446 +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6649 .loc 1 2490 0 discriminator 2 + 6650 00b0 4123 movs r3, #65 + 6651 00b2 E35C ldrb r3, [r4, r3] + 6652 00b4 DBB2 uxtb r3, r3 + 6653 00b6 A02B cmp r3, #160 + 6654 00b8 CAD0 beq .L446 +2492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6655 .loc 1 2492 0 is_stmt 1 + 6656 00ba 6B1C adds r3, r5, #1 + 6657 00bc F1D0 beq .L444 +2494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6658 .loc 1 2494 0 + 6659 00be 002D cmp r5, #0 + 6660 00c0 04D0 beq .L445 +2494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6661 .loc 1 2494 0 is_stmt 0 discriminator 1 + 6662 00c2 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccpuPECZ.s page 219 + + + 6663 .LVL604: + 6664 00c6 801B subs r0, r0, r6 + 6665 00c8 A842 cmp r0, r5 + 6666 00ca EAD9 bls .L444 + 6667 .L445: +2497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process Unlocked */ + 6668 .loc 1 2497 0 is_stmt 1 + 6669 00cc 4123 movs r3, #65 + 6670 00ce 2022 movs r2, #32 + 6671 00d0 E254 strb r2, [r4, r3] +2499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return HAL_TIMEOUT; + 6672 .loc 1 2499 0 + 6673 00d2 013B subs r3, r3, #1 + 6674 00d4 0022 movs r2, #0 + 6675 00d6 E254 strb r2, [r4, r3] +2500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6676 .loc 1 2500 0 + 6677 00d8 0320 movs r0, #3 + 6678 00da 2DE0 b .L440 + 6679 .L457: +2509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6680 .loc 1 2509 0 + 6681 00dc 0096 str r6, [sp] + 6682 00de 2B00 movs r3, r5 + 6683 00e0 0022 movs r2, #0 + 6684 00e2 2021 movs r1, #32 + 6685 00e4 2000 movs r0, r4 + 6686 00e6 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6687 .LVL605: + 6688 00ea 0028 cmp r0, #0 + 6689 00ec 2CD1 bne .L454 +2515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6690 .loc 1 2515 0 + 6691 00ee 2268 ldr r2, [r4] + 6692 00f0 2023 movs r3, #32 + 6693 00f2 D361 str r3, [r2, #28] +2518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6694 .loc 1 2518 0 + 6695 00f4 4122 movs r2, #65 + 6696 00f6 A354 strb r3, [r4, r2] +2521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6697 .loc 1 2521 0 + 6698 00f8 2033 adds r3, r3, #32 + 6699 00fa 0022 movs r2, #0 + 6700 00fc E254 strb r2, [r4, r3] +2523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6701 .loc 1 2523 0 + 6702 00fe 1BE0 b .L440 + 6703 .L458: +2544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6704 .loc 1 2544 0 + 6705 0100 2268 ldr r2, [r4] + 6706 0102 5168 ldr r1, [r2, #4] + 6707 0104 8023 movs r3, #128 + 6708 0106 DB01 lsls r3, r3, #7 + 6709 0108 0B43 orrs r3, r1 + 6710 010a 5360 str r3, [r2, #4] + ARM GAS /tmp/ccpuPECZ.s page 220 + + +2547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6711 .loc 1 2547 0 + 6712 010c 0096 str r6, [sp] + 6713 010e 2B00 movs r3, r5 + 6714 0110 0022 movs r2, #0 + 6715 0112 2021 movs r1, #32 + 6716 0114 2000 movs r0, r4 + 6717 0116 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6718 .LVL606: + 6719 011a 0028 cmp r0, #0 + 6720 011c 18D1 bne .L456 +2553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6721 .loc 1 2553 0 + 6722 011e 2368 ldr r3, [r4] + 6723 0120 2022 movs r2, #32 + 6724 0122 DA61 str r2, [r3, #28] + 6725 0124 ACE7 b .L449 + 6726 .L459: +2558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6727 .loc 1 2558 0 + 6728 0126 4123 movs r3, #65 + 6729 0128 2022 movs r2, #32 + 6730 012a E254 strb r2, [r4, r3] +2561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6731 .loc 1 2561 0 + 6732 012c 013B subs r3, r3, #1 + 6733 012e 0022 movs r2, #0 + 6734 0130 E254 strb r2, [r4, r3] +2563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6735 .loc 1 2563 0 + 6736 0132 0320 movs r0, #3 + 6737 0134 00E0 b .L440 + 6738 .LVL607: + 6739 .L451: +2567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6740 .loc 1 2567 0 + 6741 0136 0220 movs r0, #2 + 6742 .LVL608: + 6743 .L440: +2569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6744 .loc 1 2569 0 + 6745 0138 04B0 add sp, sp, #16 + 6746 @ sp needed + 6747 .LVL609: + 6748 .LVL610: + 6749 .LVL611: + 6750 013a 04BC pop {r2} + 6751 013c 9046 mov r8, r2 + 6752 013e F0BD pop {r4, r5, r6, r7, pc} + 6753 .LVL612: + 6754 .L452: +2473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6755 .loc 1 2473 0 + 6756 0140 0220 movs r0, #2 + 6757 .LVL613: + 6758 0142 F9E7 b .L440 + 6759 .LVL614: + ARM GAS /tmp/ccpuPECZ.s page 221 + + + 6760 .L453: +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6761 .loc 1 2477 0 + 6762 0144 0220 movs r0, #2 + 6763 .LVL615: + 6764 0146 F7E7 b .L440 + 6765 .LVL616: + 6766 .L454: +2511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6767 .loc 1 2511 0 + 6768 0148 0320 movs r0, #3 + 6769 014a F5E7 b .L440 + 6770 .L455: +2530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6771 .loc 1 2530 0 + 6772 014c 0320 movs r0, #3 + 6773 014e F3E7 b .L440 + 6774 .L456: +2549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6775 .loc 1 2549 0 + 6776 0150 0320 movs r0, #3 + 6777 0152 F1E7 b .L440 + 6778 .L462: + 6779 .align 2 + 6780 .L461: + 6781 0154 00200002 .word 33562624 + 6782 .cfi_endproc + 6783 .LFE61: + 6785 .section .text.HAL_I2C_Master_Sequential_Transmit_IT,"ax",%progbits + 6786 .align 1 + 6787 .global HAL_I2C_Master_Sequential_Transmit_IT + 6788 .syntax unified + 6789 .code 16 + 6790 .thumb_func + 6791 .fpu softvfp + 6793 HAL_I2C_Master_Sequential_Transmit_IT: + 6794 .LFB62: +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 6795 .loc 1 2584 0 + 6796 .cfi_startproc + 6797 @ args = 4, pretend = 0, frame = 0 + 6798 @ frame_needed = 0, uses_anonymous_args = 0 + 6799 .LVL617: + 6800 0000 F0B5 push {r4, r5, r6, r7, lr} + 6801 .LCFI49: + 6802 .cfi_def_cfa_offset 20 + 6803 .cfi_offset 4, -20 + 6804 .cfi_offset 5, -16 + 6805 .cfi_offset 6, -12 + 6806 .cfi_offset 7, -8 + 6807 .cfi_offset 14, -4 + 6808 0002 C646 mov lr, r8 + 6809 0004 00B5 push {lr} + 6810 .LCFI50: + 6811 .cfi_def_cfa_offset 24 + 6812 .cfi_offset 8, -24 + 6813 .LVL618: + ARM GAS /tmp/ccpuPECZ.s page 222 + + +2591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6814 .loc 1 2591 0 + 6815 0006 4124 movs r4, #65 + 6816 0008 045D ldrb r4, [r0, r4] + 6817 000a 202C cmp r4, #32 + 6818 000c 50D1 bne .L469 +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6819 .loc 1 2594 0 + 6820 000e 2034 adds r4, r4, #32 + 6821 0010 045D ldrb r4, [r0, r4] + 6822 0012 012C cmp r4, #1 + 6823 0014 50D0 beq .L470 +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6824 .loc 1 2594 0 is_stmt 0 discriminator 2 + 6825 0016 4024 movs r4, #64 + 6826 0018 0125 movs r5, #1 + 6827 001a 0555 strb r5, [r0, r4] +2596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6828 .loc 1 2596 0 is_stmt 1 discriminator 2 + 6829 001c 0134 adds r4, r4, #1 + 6830 001e 2035 adds r5, r5, #32 + 6831 0020 0555 strb r5, [r0, r4] +2597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6832 .loc 1 2597 0 discriminator 2 + 6833 0022 0134 adds r4, r4, #1 + 6834 0024 113D subs r5, r5, #17 + 6835 0026 0555 strb r5, [r0, r4] +2598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6836 .loc 1 2598 0 discriminator 2 + 6837 0028 0024 movs r4, #0 + 6838 002a 4464 str r4, [r0, #68] +2601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6839 .loc 1 2601 0 discriminator 2 + 6840 002c 4262 str r2, [r0, #36] +2602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6841 .loc 1 2602 0 discriminator 2 + 6842 002e 4385 strh r3, [r0, #42] +2603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6843 .loc 1 2603 0 discriminator 2 + 6844 0030 069B ldr r3, [sp, #24] + 6845 .LVL619: + 6846 0032 C362 str r3, [r0, #44] + 6847 .LVL620: +2604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6848 .loc 1 2604 0 discriminator 2 + 6849 0034 214B ldr r3, .L475 + 6850 0036 4363 str r3, [r0, #52] +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6851 .loc 1 2607 0 discriminator 2 + 6852 0038 438D ldrh r3, [r0, #42] + 6853 003a 9BB2 uxth r3, r3 + 6854 003c FF2B cmp r3, #255 + 6855 003e 2CD9 bls .L465 +2609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6856 .loc 1 2609 0 + 6857 0040 FF23 movs r3, #255 + 6858 0042 0385 strh r3, [r0, #40] + ARM GAS /tmp/ccpuPECZ.s page 223 + + + 6859 .LVL621: +2610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6860 .loc 1 2610 0 + 6861 0044 8023 movs r3, #128 + 6862 0046 5B04 lsls r3, r3, #17 + 6863 0048 9846 mov r8, r3 + 6864 .LVL622: + 6865 .L466: +2620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 6866 .loc 1 2620 0 + 6867 004a 036B ldr r3, [r0, #48] + 6868 004c 112B cmp r3, #17 + 6869 004e 29D0 beq .L471 +2586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6870 .loc 1 2586 0 + 6871 0050 1B4C ldr r4, .L475+4 + 6872 .L467: + 6873 .LVL623: +2626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6874 .loc 1 2626 0 + 6875 0052 028D ldrh r2, [r0, #40] + 6876 .LVL624: + 6877 0054 D2B2 uxtb r2, r2 + 6878 .LVL625: + 6879 .LBB272: + 6880 .LBB273: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 6881 .loc 1 4713 0 + 6882 0056 0568 ldr r5, [r0] + 6883 0058 6B68 ldr r3, [r5, #4] + 6884 005a 670D lsrs r7, r4, #21 + 6885 005c BC46 mov ip, r7 + 6886 005e 194F ldr r7, .L475+8 + 6887 0060 6646 mov r6, ip + 6888 0062 3743 orrs r7, r6 + 6889 0064 BB43 bics r3, r7 + 6890 0066 8905 lsls r1, r1, #22 + 6891 .LVL626: + 6892 0068 890D lsrs r1, r1, #22 + 6893 006a 1204 lsls r2, r2, #16 + 6894 .LVL627: + 6895 006c 1143 orrs r1, r2 + 6896 006e 4246 mov r2, r8 + 6897 0070 1143 orrs r1, r2 + 6898 0072 2143 orrs r1, r4 + 6899 0074 1943 orrs r1, r3 + 6900 0076 6960 str r1, [r5, #4] + 6901 .LVL628: + 6902 .LBE273: + 6903 .LBE272: +2629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6904 .loc 1 2629 0 + 6905 0078 4023 movs r3, #64 + 6906 007a 0022 movs r2, #0 + 6907 007c C254 strb r2, [r0, r3] + 6908 .LVL629: + 6909 .LBB274: + ARM GAS /tmp/ccpuPECZ.s page 224 + + + 6910 .LBB275: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6911 .loc 1 4728 0 + 6912 007e 436B ldr r3, [r0, #52] + 6913 0080 114A ldr r2, .L475+12 + 6914 0082 9342 cmp r3, r2 + 6915 0084 12D0 beq .L472 + 6916 0086 114A ldr r2, .L475+16 + 6917 0088 9342 cmp r3, r2 + 6918 008a 0DD0 beq .L474 + 6919 008c F221 movs r1, #242 + 6920 .L468: + 6921 .LVL630: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6922 .loc 1 4785 0 + 6923 008e 0268 ldr r2, [r0] + 6924 0090 1368 ldr r3, [r2] + 6925 0092 0B43 orrs r3, r1 + 6926 0094 1360 str r3, [r2] + 6927 .LVL631: + 6928 .LBE275: + 6929 .LBE274: +2636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6930 .loc 1 2636 0 + 6931 0096 0020 movs r0, #0 + 6932 .LVL632: + 6933 0098 0BE0 b .L464 + 6934 .LVL633: + 6935 .L465: +2614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6936 .loc 1 2614 0 + 6937 009a 438D ldrh r3, [r0, #42] + 6938 009c 0385 strh r3, [r0, #40] +2615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6939 .loc 1 2615 0 + 6940 009e C36A ldr r3, [r0, #44] + 6941 .LVL634: + 6942 00a0 9846 mov r8, r3 + 6943 .LVL635: + 6944 00a2 D2E7 b .L466 + 6945 .LVL636: + 6946 .L471: +2622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6947 .loc 1 2622 0 + 6948 00a4 0024 movs r4, #0 + 6949 00a6 D4E7 b .L467 + 6950 .LVL637: + 6951 .L474: + 6952 .LBB277: + 6953 .LBB276: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 6954 .loc 1 4728 0 + 6955 00a8 0021 movs r1, #0 + 6956 00aa F0E7 b .L468 + 6957 .L472: + 6958 00ac 0021 movs r1, #0 + 6959 00ae EEE7 b .L468 + ARM GAS /tmp/ccpuPECZ.s page 225 + + + 6960 .LVL638: + 6961 .L469: + 6962 .LBE276: + 6963 .LBE277: +2640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 6964 .loc 1 2640 0 + 6965 00b0 0220 movs r0, #2 + 6966 .LVL639: + 6967 .L464: +2642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6968 .loc 1 2642 0 + 6969 @ sp needed + 6970 00b2 04BC pop {r2} + 6971 00b4 9046 mov r8, r2 + 6972 00b6 F0BD pop {r4, r5, r6, r7, pc} + 6973 .LVL640: + 6974 .L470: +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 6975 .loc 1 2594 0 + 6976 00b8 0220 movs r0, #2 + 6977 .LVL641: + 6978 00ba FAE7 b .L464 + 6979 .L476: + 6980 .align 2 + 6981 .L475: + 6982 00bc 00000000 .word I2C_Master_ISR_IT + 6983 00c0 00200080 .word -2147475456 + 6984 00c4 FF63FF03 .word 67068927 + 6985 00c8 00000000 .word I2C_Master_ISR_DMA + 6986 00cc 00000000 .word I2C_Slave_ISR_DMA + 6987 .cfi_endproc + 6988 .LFE62: + 6990 .section .text.HAL_I2C_Master_Sequential_Receive_IT,"ax",%progbits + 6991 .align 1 + 6992 .global HAL_I2C_Master_Sequential_Receive_IT + 6993 .syntax unified + 6994 .code 16 + 6995 .thumb_func + 6996 .fpu softvfp + 6998 HAL_I2C_Master_Sequential_Receive_IT: + 6999 .LFB63: +2657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t xfermode = 0U; + 7000 .loc 1 2657 0 + 7001 .cfi_startproc + 7002 @ args = 4, pretend = 0, frame = 0 + 7003 @ frame_needed = 0, uses_anonymous_args = 0 + 7004 .LVL642: + 7005 0000 F0B5 push {r4, r5, r6, r7, lr} + 7006 .LCFI51: + 7007 .cfi_def_cfa_offset 20 + 7008 .cfi_offset 4, -20 + 7009 .cfi_offset 5, -16 + 7010 .cfi_offset 6, -12 + 7011 .cfi_offset 7, -8 + 7012 .cfi_offset 14, -4 + 7013 0002 C646 mov lr, r8 + 7014 0004 00B5 push {lr} + ARM GAS /tmp/ccpuPECZ.s page 226 + + + 7015 .LCFI52: + 7016 .cfi_def_cfa_offset 24 + 7017 .cfi_offset 8, -24 + 7018 .LVL643: +2664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7019 .loc 1 2664 0 + 7020 0006 4124 movs r4, #65 + 7021 0008 045D ldrb r4, [r0, r4] + 7022 000a 202C cmp r4, #32 + 7023 000c 50D1 bne .L483 +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7024 .loc 1 2667 0 + 7025 000e 2034 adds r4, r4, #32 + 7026 0010 045D ldrb r4, [r0, r4] + 7027 0012 012C cmp r4, #1 + 7028 0014 50D0 beq .L484 +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7029 .loc 1 2667 0 is_stmt 0 discriminator 2 + 7030 0016 4024 movs r4, #64 + 7031 0018 0125 movs r5, #1 + 7032 001a 0555 strb r5, [r0, r4] +2669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7033 .loc 1 2669 0 is_stmt 1 discriminator 2 + 7034 001c 0134 adds r4, r4, #1 + 7035 001e 2135 adds r5, r5, #33 + 7036 0020 0555 strb r5, [r0, r4] +2670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7037 .loc 1 2670 0 discriminator 2 + 7038 0022 0134 adds r4, r4, #1 + 7039 0024 123D subs r5, r5, #18 + 7040 0026 0555 strb r5, [r0, r4] +2671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7041 .loc 1 2671 0 discriminator 2 + 7042 0028 0024 movs r4, #0 + 7043 002a 4464 str r4, [r0, #68] +2674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7044 .loc 1 2674 0 discriminator 2 + 7045 002c 4262 str r2, [r0, #36] +2675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7046 .loc 1 2675 0 discriminator 2 + 7047 002e 4385 strh r3, [r0, #42] +2676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7048 .loc 1 2676 0 discriminator 2 + 7049 0030 069B ldr r3, [sp, #24] + 7050 .LVL644: + 7051 0032 C362 str r3, [r0, #44] + 7052 .LVL645: +2677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7053 .loc 1 2677 0 discriminator 2 + 7054 0034 214B ldr r3, .L489 + 7055 0036 4363 str r3, [r0, #52] +2680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7056 .loc 1 2680 0 discriminator 2 + 7057 0038 438D ldrh r3, [r0, #42] + 7058 003a 9BB2 uxth r3, r3 + 7059 003c FF2B cmp r3, #255 + 7060 003e 2CD9 bls .L479 + ARM GAS /tmp/ccpuPECZ.s page 227 + + +2682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7061 .loc 1 2682 0 + 7062 0040 FF23 movs r3, #255 + 7063 0042 0385 strh r3, [r0, #40] + 7064 .LVL646: +2683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7065 .loc 1 2683 0 + 7066 0044 8023 movs r3, #128 + 7067 0046 5B04 lsls r3, r3, #17 + 7068 0048 9846 mov r8, r3 + 7069 .LVL647: + 7070 .L480: +2693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7071 .loc 1 2693 0 + 7072 004a 036B ldr r3, [r0, #48] + 7073 004c 122B cmp r3, #18 + 7074 004e 29D0 beq .L485 +2659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7075 .loc 1 2659 0 + 7076 0050 1B4C ldr r4, .L489+4 + 7077 .L481: + 7078 .LVL648: +2699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7079 .loc 1 2699 0 + 7080 0052 028D ldrh r2, [r0, #40] + 7081 .LVL649: + 7082 0054 D2B2 uxtb r2, r2 + 7083 .LVL650: + 7084 .LBB278: + 7085 .LBB279: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 7086 .loc 1 4713 0 + 7087 0056 0568 ldr r5, [r0] + 7088 0058 6B68 ldr r3, [r5, #4] + 7089 005a 670D lsrs r7, r4, #21 + 7090 005c BC46 mov ip, r7 + 7091 005e 194F ldr r7, .L489+8 + 7092 0060 6646 mov r6, ip + 7093 0062 3743 orrs r7, r6 + 7094 0064 BB43 bics r3, r7 + 7095 0066 8905 lsls r1, r1, #22 + 7096 .LVL651: + 7097 0068 890D lsrs r1, r1, #22 + 7098 006a 1204 lsls r2, r2, #16 + 7099 .LVL652: + 7100 006c 1143 orrs r1, r2 + 7101 006e 4246 mov r2, r8 + 7102 0070 1143 orrs r1, r2 + 7103 0072 2143 orrs r1, r4 + 7104 0074 1943 orrs r1, r3 + 7105 0076 6960 str r1, [r5, #4] + 7106 .LVL653: + 7107 .LBE279: + 7108 .LBE278: +2702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7109 .loc 1 2702 0 + 7110 0078 4023 movs r3, #64 + ARM GAS /tmp/ccpuPECZ.s page 228 + + + 7111 007a 0022 movs r2, #0 + 7112 007c C254 strb r2, [r0, r3] + 7113 .LVL654: + 7114 .LBB280: + 7115 .LBB281: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7116 .loc 1 4728 0 + 7117 007e 436B ldr r3, [r0, #52] + 7118 0080 114A ldr r2, .L489+12 + 7119 0082 9342 cmp r3, r2 + 7120 0084 12D0 beq .L486 + 7121 0086 114A ldr r2, .L489+16 + 7122 0088 9342 cmp r3, r2 + 7123 008a 0DD0 beq .L488 + 7124 008c F421 movs r1, #244 + 7125 .L482: + 7126 .LVL655: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7127 .loc 1 4785 0 + 7128 008e 0268 ldr r2, [r0] + 7129 0090 1368 ldr r3, [r2] + 7130 0092 0B43 orrs r3, r1 + 7131 0094 1360 str r3, [r2] + 7132 .LVL656: + 7133 .LBE281: + 7134 .LBE280: +2709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7135 .loc 1 2709 0 + 7136 0096 0020 movs r0, #0 + 7137 .LVL657: + 7138 0098 0BE0 b .L478 + 7139 .LVL658: + 7140 .L479: +2687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7141 .loc 1 2687 0 + 7142 009a 438D ldrh r3, [r0, #42] + 7143 009c 0385 strh r3, [r0, #40] +2688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7144 .loc 1 2688 0 + 7145 009e C36A ldr r3, [r0, #44] + 7146 .LVL659: + 7147 00a0 9846 mov r8, r3 + 7148 .LVL660: + 7149 00a2 D2E7 b .L480 + 7150 .LVL661: + 7151 .L485: +2695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7152 .loc 1 2695 0 + 7153 00a4 0024 movs r4, #0 + 7154 00a6 D4E7 b .L481 + 7155 .LVL662: + 7156 .L488: + 7157 .LBB283: + 7158 .LBB282: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7159 .loc 1 4728 0 + 7160 00a8 0021 movs r1, #0 + ARM GAS /tmp/ccpuPECZ.s page 229 + + + 7161 00aa F0E7 b .L482 + 7162 .L486: + 7163 00ac 0021 movs r1, #0 + 7164 00ae EEE7 b .L482 + 7165 .LVL663: + 7166 .L483: + 7167 .LBE282: + 7168 .LBE283: +2713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7169 .loc 1 2713 0 + 7170 00b0 0220 movs r0, #2 + 7171 .LVL664: + 7172 .L478: +2715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7173 .loc 1 2715 0 + 7174 @ sp needed + 7175 00b2 04BC pop {r2} + 7176 00b4 9046 mov r8, r2 + 7177 00b6 F0BD pop {r4, r5, r6, r7, pc} + 7178 .LVL665: + 7179 .L484: +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7180 .loc 1 2667 0 + 7181 00b8 0220 movs r0, #2 + 7182 .LVL666: + 7183 00ba FAE7 b .L478 + 7184 .L490: + 7185 .align 2 + 7186 .L489: + 7187 00bc 00000000 .word I2C_Master_ISR_IT + 7188 00c0 00240080 .word -2147474432 + 7189 00c4 FF63FF03 .word 67068927 + 7190 00c8 00000000 .word I2C_Master_ISR_DMA + 7191 00cc 00000000 .word I2C_Slave_ISR_DMA + 7192 .cfi_endproc + 7193 .LFE63: + 7195 .section .text.HAL_I2C_Slave_Sequential_Transmit_IT,"ax",%progbits + 7196 .align 1 + 7197 .global HAL_I2C_Slave_Sequential_Transmit_IT + 7198 .syntax unified + 7199 .code 16 + 7200 .thumb_func + 7201 .fpu softvfp + 7203 HAL_I2C_Slave_Sequential_Transmit_IT: + 7204 .LFB64: +2728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ + 7205 .loc 1 2728 0 + 7206 .cfi_startproc + 7207 @ args = 0, pretend = 0, frame = 0 + 7208 @ frame_needed = 0, uses_anonymous_args = 0 + 7209 .LVL667: + 7210 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 7211 .LCFI53: + 7212 .cfi_def_cfa_offset 24 + 7213 .cfi_offset 3, -24 + 7214 .cfi_offset 4, -20 + 7215 .cfi_offset 5, -16 + ARM GAS /tmp/ccpuPECZ.s page 230 + + + 7216 .cfi_offset 6, -12 + 7217 .cfi_offset 7, -8 + 7218 .cfi_offset 14, -4 + 7219 0002 0700 movs r7, r0 + 7220 0004 0C00 movs r4, r1 + 7221 0006 1500 movs r5, r2 + 7222 0008 1E00 movs r6, r3 +2732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7223 .loc 1 2732 0 + 7224 000a 4123 movs r3, #65 + 7225 .LVL668: + 7226 000c C35C ldrb r3, [r0, r3] + 7227 000e 2822 movs r2, #40 + 7228 .LVL669: + 7229 0010 1340 ands r3, r2 + 7230 0012 282B cmp r3, #40 + 7231 0014 01D0 beq .L502 +2787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7232 .loc 1 2787 0 + 7233 0016 0120 movs r0, #1 + 7234 .LVL670: + 7235 .L492: +2789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7236 .loc 1 2789 0 + 7237 @ sp needed + 7238 .LVL671: + 7239 .LVL672: + 7240 .LVL673: + 7241 0018 F8BD pop {r3, r4, r5, r6, r7, pc} + 7242 .LVL674: + 7243 .L502: +2734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7244 .loc 1 2734 0 + 7245 001a 0029 cmp r1, #0 + 7246 001c 45D0 beq .L497 +2734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7247 .loc 1 2734 0 is_stmt 0 discriminator 1 + 7248 001e 002D cmp r5, #0 + 7249 0020 01D1 bne .L503 +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7250 .loc 1 2736 0 is_stmt 1 + 7251 0022 0120 movs r0, #1 + 7252 .LVL675: + 7253 0024 F8E7 b .L492 + 7254 .LVL676: + 7255 .L503: +2740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7256 .loc 1 2740 0 + 7257 0026 0521 movs r1, #5 + 7258 .LVL677: + 7259 0028 FFF7FEFF bl I2C_Disable_IRQ + 7260 .LVL678: +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7261 .loc 1 2743 0 + 7262 002c 4023 movs r3, #64 + 7263 002e FB5C ldrb r3, [r7, r3] + 7264 0030 012B cmp r3, #1 + ARM GAS /tmp/ccpuPECZ.s page 231 + + + 7265 0032 3CD0 beq .L499 +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7266 .loc 1 2743 0 is_stmt 0 discriminator 2 + 7267 0034 4023 movs r3, #64 + 7268 0036 0122 movs r2, #1 + 7269 0038 FA54 strb r2, [r7, r3] +2747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7270 .loc 1 2747 0 is_stmt 1 discriminator 2 + 7271 003a 0133 adds r3, r3, #1 + 7272 003c FB5C ldrb r3, [r7, r3] + 7273 003e 2A2B cmp r3, #42 + 7274 0040 2AD0 beq .L504 + 7275 .L493: +2753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7276 .loc 1 2753 0 + 7277 0042 4123 movs r3, #65 + 7278 0044 2922 movs r2, #41 + 7279 0046 FA54 strb r2, [r7, r3] +2754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7280 .loc 1 2754 0 + 7281 0048 0133 adds r3, r3, #1 + 7282 004a 093A subs r2, r2, #9 + 7283 004c FA54 strb r2, [r7, r3] +2755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7284 .loc 1 2755 0 + 7285 004e 0023 movs r3, #0 + 7286 0050 7B64 str r3, [r7, #68] +2758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7287 .loc 1 2758 0 + 7288 0052 3A68 ldr r2, [r7] + 7289 0054 5368 ldr r3, [r2, #4] + 7290 0056 1749 ldr r1, .L506 + 7291 0058 0B40 ands r3, r1 + 7292 005a 5360 str r3, [r2, #4] +2761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7293 .loc 1 2761 0 + 7294 005c 7C62 str r4, [r7, #36] +2762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7295 .loc 1 2762 0 + 7296 005e 7D85 strh r5, [r7, #42] +2763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7297 .loc 1 2763 0 + 7298 0060 7B8D ldrh r3, [r7, #42] + 7299 0062 3B85 strh r3, [r7, #40] +2764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7300 .loc 1 2764 0 + 7301 0064 FE62 str r6, [r7, #44] +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7302 .loc 1 2765 0 + 7303 0066 144B ldr r3, .L506+4 + 7304 0068 7B63 str r3, [r7, #52] +2767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7305 .loc 1 2767 0 + 7306 006a 3B68 ldr r3, [r7] + 7307 006c 9A69 ldr r2, [r3, #24] + 7308 006e D203 lsls r2, r2, #15 + 7309 0070 01D5 bpl .L494 + ARM GAS /tmp/ccpuPECZ.s page 232 + + +2771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7310 .loc 1 2771 0 + 7311 0072 0822 movs r2, #8 + 7312 0074 DA61 str r2, [r3, #28] + 7313 .L494: +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7314 .loc 1 2775 0 + 7315 0076 4023 movs r3, #64 + 7316 0078 0022 movs r2, #0 + 7317 007a FA54 strb r2, [r7, r3] + 7318 .LVL679: + 7319 .LBB284: + 7320 .LBB285: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7321 .loc 1 4728 0 + 7322 007c 7B6B ldr r3, [r7, #52] + 7323 007e 0F4A ldr r2, .L506+8 + 7324 0080 9342 cmp r3, r2 + 7325 0082 10D0 beq .L500 + 7326 0084 0E4A ldr r2, .L506+12 + 7327 0086 9342 cmp r3, r2 + 7328 0088 0BD0 beq .L505 + 7329 008a FA21 movs r1, #250 + 7330 .L495: + 7331 .LVL680: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7332 .loc 1 4785 0 + 7333 008c 3A68 ldr r2, [r7] + 7334 008e 1368 ldr r3, [r2] + 7335 0090 0B43 orrs r3, r1 + 7336 0092 1360 str r3, [r2] + 7337 .LVL681: + 7338 .LBE285: + 7339 .LBE284: +2783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7340 .loc 1 2783 0 + 7341 0094 0020 movs r0, #0 + 7342 0096 BFE7 b .L492 + 7343 .L504: +2750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7344 .loc 1 2750 0 + 7345 0098 0221 movs r1, #2 + 7346 009a 3800 movs r0, r7 + 7347 009c FFF7FEFF bl I2C_Disable_IRQ + 7348 .LVL682: + 7349 00a0 CFE7 b .L493 + 7350 .LVL683: + 7351 .L505: + 7352 .LBB287: + 7353 .LBB286: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7354 .loc 1 4728 0 + 7355 00a2 B821 movs r1, #184 + 7356 00a4 F2E7 b .L495 + 7357 .L500: + 7358 00a6 B821 movs r1, #184 + 7359 00a8 F0E7 b .L495 + ARM GAS /tmp/ccpuPECZ.s page 233 + + + 7360 .LVL684: + 7361 .L497: + 7362 .LBE286: + 7363 .LBE287: +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7364 .loc 1 2736 0 + 7365 00aa 0120 movs r0, #1 + 7366 .LVL685: + 7367 00ac B4E7 b .L492 + 7368 .LVL686: + 7369 .L499: +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7370 .loc 1 2743 0 + 7371 00ae 0220 movs r0, #2 + 7372 00b0 B2E7 b .L492 + 7373 .L507: + 7374 00b2 C046 .align 2 + 7375 .L506: + 7376 00b4 FF7FFFFF .word -32769 + 7377 00b8 00000000 .word I2C_Slave_ISR_IT + 7378 00bc 00000000 .word I2C_Master_ISR_DMA + 7379 00c0 00000000 .word I2C_Slave_ISR_DMA + 7380 .cfi_endproc + 7381 .LFE64: + 7383 .section .text.HAL_I2C_Slave_Sequential_Receive_IT,"ax",%progbits + 7384 .align 1 + 7385 .global HAL_I2C_Slave_Sequential_Receive_IT + 7386 .syntax unified + 7387 .code 16 + 7388 .thumb_func + 7389 .fpu softvfp + 7391 HAL_I2C_Slave_Sequential_Receive_IT: + 7392 .LFB65: +2802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Check the parameters */ + 7393 .loc 1 2802 0 + 7394 .cfi_startproc + 7395 @ args = 0, pretend = 0, frame = 0 + 7396 @ frame_needed = 0, uses_anonymous_args = 0 + 7397 .LVL687: + 7398 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 7399 .LCFI54: + 7400 .cfi_def_cfa_offset 24 + 7401 .cfi_offset 3, -24 + 7402 .cfi_offset 4, -20 + 7403 .cfi_offset 5, -16 + 7404 .cfi_offset 6, -12 + 7405 .cfi_offset 7, -8 + 7406 .cfi_offset 14, -4 + 7407 0002 0700 movs r7, r0 + 7408 0004 0C00 movs r4, r1 + 7409 0006 1500 movs r5, r2 + 7410 0008 1E00 movs r6, r3 +2806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7411 .loc 1 2806 0 + 7412 000a 4123 movs r3, #65 + 7413 .LVL688: + 7414 000c C35C ldrb r3, [r0, r3] + ARM GAS /tmp/ccpuPECZ.s page 234 + + + 7415 000e 2822 movs r2, #40 + 7416 .LVL689: + 7417 0010 1340 ands r3, r2 + 7418 0012 282B cmp r3, #40 + 7419 0014 01D0 beq .L519 +2861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7420 .loc 1 2861 0 + 7421 0016 0120 movs r0, #1 + 7422 .LVL690: + 7423 .L509: +2863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7424 .loc 1 2863 0 + 7425 @ sp needed + 7426 .LVL691: + 7427 .LVL692: + 7428 .LVL693: + 7429 0018 F8BD pop {r3, r4, r5, r6, r7, pc} + 7430 .LVL694: + 7431 .L519: +2808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7432 .loc 1 2808 0 + 7433 001a 0029 cmp r1, #0 + 7434 001c 45D0 beq .L514 +2808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7435 .loc 1 2808 0 is_stmt 0 discriminator 1 + 7436 001e 002D cmp r5, #0 + 7437 0020 01D1 bne .L520 +2810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7438 .loc 1 2810 0 is_stmt 1 + 7439 0022 0120 movs r0, #1 + 7440 .LVL695: + 7441 0024 F8E7 b .L509 + 7442 .LVL696: + 7443 .L520: +2814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7444 .loc 1 2814 0 + 7445 0026 0621 movs r1, #6 + 7446 .LVL697: + 7447 0028 FFF7FEFF bl I2C_Disable_IRQ + 7448 .LVL698: +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7449 .loc 1 2817 0 + 7450 002c 4023 movs r3, #64 + 7451 002e FB5C ldrb r3, [r7, r3] + 7452 0030 012B cmp r3, #1 + 7453 0032 3CD0 beq .L516 +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7454 .loc 1 2817 0 is_stmt 0 discriminator 2 + 7455 0034 4023 movs r3, #64 + 7456 0036 0122 movs r2, #1 + 7457 0038 FA54 strb r2, [r7, r3] +2821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7458 .loc 1 2821 0 is_stmt 1 discriminator 2 + 7459 003a 0133 adds r3, r3, #1 + 7460 003c FB5C ldrb r3, [r7, r3] + 7461 003e 292B cmp r3, #41 + 7462 0040 2AD0 beq .L521 + ARM GAS /tmp/ccpuPECZ.s page 235 + + + 7463 .L510: +2827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7464 .loc 1 2827 0 + 7465 0042 4123 movs r3, #65 + 7466 0044 2A22 movs r2, #42 + 7467 0046 FA54 strb r2, [r7, r3] +2828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7468 .loc 1 2828 0 + 7469 0048 0133 adds r3, r3, #1 + 7470 004a 0A3A subs r2, r2, #10 + 7471 004c FA54 strb r2, [r7, r3] +2829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7472 .loc 1 2829 0 + 7473 004e 0023 movs r3, #0 + 7474 0050 7B64 str r3, [r7, #68] +2832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7475 .loc 1 2832 0 + 7476 0052 3A68 ldr r2, [r7] + 7477 0054 5368 ldr r3, [r2, #4] + 7478 0056 1749 ldr r1, .L523 + 7479 0058 0B40 ands r3, r1 + 7480 005a 5360 str r3, [r2, #4] +2835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7481 .loc 1 2835 0 + 7482 005c 7C62 str r4, [r7, #36] +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7483 .loc 1 2836 0 + 7484 005e 7D85 strh r5, [r7, #42] +2837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7485 .loc 1 2837 0 + 7486 0060 7B8D ldrh r3, [r7, #42] + 7487 0062 3B85 strh r3, [r7, #40] +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7488 .loc 1 2838 0 + 7489 0064 FE62 str r6, [r7, #44] +2839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7490 .loc 1 2839 0 + 7491 0066 144B ldr r3, .L523+4 + 7492 0068 7B63 str r3, [r7, #52] +2841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7493 .loc 1 2841 0 + 7494 006a 3B68 ldr r3, [r7] + 7495 006c 9A69 ldr r2, [r3, #24] + 7496 006e D203 lsls r2, r2, #15 + 7497 0070 01D4 bmi .L511 +2845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7498 .loc 1 2845 0 + 7499 0072 0822 movs r2, #8 + 7500 0074 DA61 str r2, [r3, #28] + 7501 .L511: +2849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7502 .loc 1 2849 0 + 7503 0076 4023 movs r3, #64 + 7504 0078 0022 movs r2, #0 + 7505 007a FA54 strb r2, [r7, r3] + 7506 .LVL699: + 7507 .LBB288: + ARM GAS /tmp/ccpuPECZ.s page 236 + + + 7508 .LBB289: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7509 .loc 1 4728 0 + 7510 007c 7B6B ldr r3, [r7, #52] + 7511 007e 0F4A ldr r2, .L523+8 + 7512 0080 9342 cmp r3, r2 + 7513 0082 10D0 beq .L517 + 7514 0084 0E4A ldr r2, .L523+12 + 7515 0086 9342 cmp r3, r2 + 7516 0088 0BD0 beq .L522 + 7517 008a FC21 movs r1, #252 + 7518 .L512: + 7519 .LVL700: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7520 .loc 1 4785 0 + 7521 008c 3A68 ldr r2, [r7] + 7522 008e 1368 ldr r3, [r2] + 7523 0090 0B43 orrs r3, r1 + 7524 0092 1360 str r3, [r2] + 7525 .LVL701: + 7526 .LBE289: + 7527 .LBE288: +2857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7528 .loc 1 2857 0 + 7529 0094 0020 movs r0, #0 + 7530 0096 BFE7 b .L509 + 7531 .L521: +2824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7532 .loc 1 2824 0 + 7533 0098 0121 movs r1, #1 + 7534 009a 3800 movs r0, r7 + 7535 009c FFF7FEFF bl I2C_Disable_IRQ + 7536 .LVL702: + 7537 00a0 CFE7 b .L510 + 7538 .LVL703: + 7539 .L522: + 7540 .LBB291: + 7541 .LBB290: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7542 .loc 1 4728 0 + 7543 00a2 B821 movs r1, #184 + 7544 00a4 F2E7 b .L512 + 7545 .L517: + 7546 00a6 B821 movs r1, #184 + 7547 00a8 F0E7 b .L512 + 7548 .LVL704: + 7549 .L514: + 7550 .LBE290: + 7551 .LBE291: +2810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7552 .loc 1 2810 0 + 7553 00aa 0120 movs r0, #1 + 7554 .LVL705: + 7555 00ac B4E7 b .L509 + 7556 .LVL706: + 7557 .L516: +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 237 + + + 7558 .loc 1 2817 0 + 7559 00ae 0220 movs r0, #2 + 7560 00b0 B2E7 b .L509 + 7561 .L524: + 7562 00b2 C046 .align 2 + 7563 .L523: + 7564 00b4 FF7FFFFF .word -32769 + 7565 00b8 00000000 .word I2C_Slave_ISR_IT + 7566 00bc 00000000 .word I2C_Master_ISR_DMA + 7567 00c0 00000000 .word I2C_Slave_ISR_DMA + 7568 .cfi_endproc + 7569 .LFE65: + 7571 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 7572 .align 1 + 7573 .global HAL_I2C_EnableListen_IT + 7574 .syntax unified + 7575 .code 16 + 7576 .thumb_func + 7577 .fpu softvfp + 7579 HAL_I2C_EnableListen_IT: + 7580 .LFB66: +2872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 7581 .loc 1 2872 0 + 7582 .cfi_startproc + 7583 @ args = 0, pretend = 0, frame = 0 + 7584 @ frame_needed = 0, uses_anonymous_args = 0 + 7585 @ link register save eliminated. + 7586 .LVL707: +2873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7587 .loc 1 2873 0 + 7588 0000 4123 movs r3, #65 + 7589 0002 C35C ldrb r3, [r0, r3] + 7590 0004 202B cmp r3, #32 + 7591 0006 0BD1 bne .L527 +2875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7592 .loc 1 2875 0 + 7593 0008 2133 adds r3, r3, #33 + 7594 000a 2822 movs r2, #40 + 7595 000c C254 strb r2, [r0, r3] +2876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7596 .loc 1 2876 0 + 7597 000e 054B ldr r3, .L528 + 7598 0010 4363 str r3, [r0, #52] + 7599 .LVL708: + 7600 .LBB292: + 7601 .LBB293: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7602 .loc 1 4785 0 + 7603 0012 0268 ldr r2, [r0] + 7604 0014 1368 ldr r3, [r2] + 7605 0016 B821 movs r1, #184 + 7606 0018 0B43 orrs r3, r1 + 7607 001a 1360 str r3, [r2] + 7608 .LVL709: + 7609 .LBE293: + 7610 .LBE292: +2881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 238 + + + 7611 .loc 1 2881 0 + 7612 001c 0020 movs r0, #0 + 7613 .LVL710: + 7614 .L526: +2887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7615 .loc 1 2887 0 + 7616 @ sp needed + 7617 001e 7047 bx lr + 7618 .LVL711: + 7619 .L527: +2885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7620 .loc 1 2885 0 + 7621 0020 0220 movs r0, #2 + 7622 .LVL712: + 7623 0022 FCE7 b .L526 + 7624 .L529: + 7625 .align 2 + 7626 .L528: + 7627 0024 00000000 .word I2C_Slave_ISR_IT + 7628 .cfi_endproc + 7629 .LFE66: + 7631 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 7632 .align 1 + 7633 .global HAL_I2C_DisableListen_IT + 7634 .syntax unified + 7635 .code 16 + 7636 .thumb_func + 7637 .fpu softvfp + 7639 HAL_I2C_DisableListen_IT: + 7640 .LFB67: +2896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 7641 .loc 1 2896 0 + 7642 .cfi_startproc + 7643 @ args = 0, pretend = 0, frame = 0 + 7644 @ frame_needed = 0, uses_anonymous_args = 0 + 7645 .LVL713: + 7646 0000 70B5 push {r4, r5, r6, lr} + 7647 .LCFI55: + 7648 .cfi_def_cfa_offset 16 + 7649 .cfi_offset 4, -16 + 7650 .cfi_offset 5, -12 + 7651 .cfi_offset 6, -8 + 7652 .cfi_offset 14, -4 +2901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7653 .loc 1 2901 0 + 7654 0002 4123 movs r3, #65 + 7655 0004 C35C ldrb r3, [r0, r3] + 7656 0006 282B cmp r3, #40 + 7657 0008 01D0 beq .L533 +2916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7658 .loc 1 2916 0 + 7659 000a 0220 movs r0, #2 + 7660 .LVL714: + 7661 .L531: +2918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7662 .loc 1 2918 0 + 7663 @ sp needed + ARM GAS /tmp/ccpuPECZ.s page 239 + + + 7664 000c 70BD pop {r4, r5, r6, pc} + 7665 .LVL715: + 7666 .L533: +2903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 7667 .loc 1 2903 0 + 7668 000e 4124 movs r4, #65 + 7669 0010 025D ldrb r2, [r0, r4] + 7670 .LVL716: +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 7671 .loc 1 2904 0 + 7672 0012 4221 movs r1, #66 + 7673 0014 435C ldrb r3, [r0, r1] + 7674 0016 0325 movs r5, #3 + 7675 0018 2A40 ands r2, r5 + 7676 .LVL717: + 7677 001a 1343 orrs r3, r2 + 7678 001c 0363 str r3, [r0, #48] +2905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7679 .loc 1 2905 0 + 7680 001e 2023 movs r3, #32 + 7681 0020 0355 strb r3, [r0, r4] +2906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 7682 .loc 1 2906 0 + 7683 0022 0023 movs r3, #0 + 7684 0024 4354 strb r3, [r0, r1] +2907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7685 .loc 1 2907 0 + 7686 0026 4363 str r3, [r0, #52] +2910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7687 .loc 1 2910 0 + 7688 0028 3E39 subs r1, r1, #62 + 7689 002a FFF7FEFF bl I2C_Disable_IRQ + 7690 .LVL718: +2912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7691 .loc 1 2912 0 + 7692 002e 0020 movs r0, #0 + 7693 0030 ECE7 b .L531 + 7694 .cfi_endproc + 7695 .LFE67: + 7697 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 7698 .align 1 + 7699 .global HAL_I2C_Master_Abort_IT + 7700 .syntax unified + 7701 .code 16 + 7702 .thumb_func + 7703 .fpu softvfp + 7705 HAL_I2C_Master_Abort_IT: + 7706 .LFB68: +2929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 7707 .loc 1 2929 0 + 7708 .cfi_startproc + 7709 @ args = 0, pretend = 0, frame = 0 + 7710 @ frame_needed = 0, uses_anonymous_args = 0 + 7711 .LVL719: + 7712 0000 70B5 push {r4, r5, r6, lr} + 7713 .LCFI56: + 7714 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccpuPECZ.s page 240 + + + 7715 .cfi_offset 4, -16 + 7716 .cfi_offset 5, -12 + 7717 .cfi_offset 6, -8 + 7718 .cfi_offset 14, -4 + 7719 0002 0400 movs r4, r0 + 7720 0004 0D00 movs r5, r1 +2930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7721 .loc 1 2930 0 + 7722 0006 4223 movs r3, #66 + 7723 0008 C35C ldrb r3, [r0, r3] + 7724 000a 102B cmp r3, #16 + 7725 000c 01D0 beq .L541 +2960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7726 .loc 1 2960 0 + 7727 000e 0120 movs r0, #1 + 7728 .LVL720: + 7729 .L535: +2962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7730 .loc 1 2962 0 + 7731 @ sp needed + 7732 .LVL721: + 7733 0010 70BD pop {r4, r5, r6, pc} + 7734 .LVL722: + 7735 .L541: +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7736 .loc 1 2933 0 + 7737 0012 3033 adds r3, r3, #48 + 7738 0014 C35C ldrb r3, [r0, r3] + 7739 0016 012B cmp r3, #1 + 7740 0018 2AD0 beq .L538 +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7741 .loc 1 2933 0 is_stmt 0 discriminator 2 + 7742 001a 4026 movs r6, #64 + 7743 001c 0123 movs r3, #1 + 7744 001e 8355 strb r3, [r0, r6] +2936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 7745 .loc 1 2936 0 is_stmt 1 discriminator 2 + 7746 0020 0221 movs r1, #2 + 7747 .LVL723: + 7748 0022 FFF7FEFF bl I2C_Disable_IRQ + 7749 .LVL724: +2937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7750 .loc 1 2937 0 discriminator 2 + 7751 0026 0121 movs r1, #1 + 7752 0028 2000 movs r0, r4 + 7753 002a FFF7FEFF bl I2C_Disable_IRQ + 7754 .LVL725: +2940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7755 .loc 1 2940 0 discriminator 2 + 7756 002e 4123 movs r3, #65 + 7757 0030 6022 movs r2, #96 + 7758 0032 E254 strb r2, [r4, r3] + 7759 .LVL726: + 7760 .LBB294: + 7761 .LBB295: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 7762 .loc 1 4713 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 241 + + + 7763 0034 2168 ldr r1, [r4] + 7764 0036 4B68 ldr r3, [r1, #4] + 7765 0038 0E4A ldr r2, .L543 + 7766 003a 1340 ands r3, r2 + 7767 003c AD05 lsls r5, r5, #22 + 7768 .LVL727: + 7769 003e AD0D lsrs r5, r5, #22 + 7770 0040 0D4A ldr r2, .L543+4 + 7771 0042 1543 orrs r5, r2 + 7772 0044 1D43 orrs r5, r3 + 7773 0046 4D60 str r5, [r1, #4] + 7774 .LVL728: + 7775 .LBE295: + 7776 .LBE294: +2947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7777 .loc 1 2947 0 discriminator 2 + 7778 0048 0023 movs r3, #0 + 7779 004a A355 strb r3, [r4, r6] + 7780 .LVL729: + 7781 .LBB296: + 7782 .LBB297: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7783 .loc 1 4728 0 discriminator 2 + 7784 004c 636B ldr r3, [r4, #52] + 7785 004e 0B4A ldr r2, .L543+8 + 7786 0050 9342 cmp r3, r2 + 7787 0052 0BD0 beq .L539 +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 7788 .loc 1 4728 0 is_stmt 0 + 7789 0054 0A4A ldr r2, .L543+12 + 7790 0056 9342 cmp r3, r2 + 7791 0058 06D0 beq .L542 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7792 .loc 1 4778 0 is_stmt 1 + 7793 005a F421 movs r1, #244 + 7794 .L536: + 7795 .LVL730: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7796 .loc 1 4785 0 + 7797 005c 2268 ldr r2, [r4] + 7798 005e 1368 ldr r3, [r2] + 7799 0060 0B43 orrs r3, r1 + 7800 0062 1360 str r3, [r2] + 7801 .LVL731: + 7802 .LBE297: + 7803 .LBE296: +2954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7804 .loc 1 2954 0 + 7805 0064 0020 movs r0, #0 + 7806 0066 D3E7 b .L535 + 7807 .LVL732: + 7808 .L542: + 7809 .LBB299: + 7810 .LBB298: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7811 .loc 1 4752 0 + 7812 0068 6021 movs r1, #96 + ARM GAS /tmp/ccpuPECZ.s page 242 + + + 7813 006a F7E7 b .L536 + 7814 .L539: + 7815 006c 6021 movs r1, #96 + 7816 006e F5E7 b .L536 + 7817 .LVL733: + 7818 .L538: + 7819 .LBE298: + 7820 .LBE299: +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7821 .loc 1 2933 0 + 7822 0070 0220 movs r0, #2 + 7823 .LVL734: + 7824 0072 CDE7 b .L535 + 7825 .L544: + 7826 .align 2 + 7827 .L543: + 7828 0074 009800FC .word -67069952 + 7829 0078 00400182 .word -2113847296 + 7830 007c 00000000 .word I2C_Master_ISR_DMA + 7831 0080 00000000 .word I2C_Slave_ISR_DMA + 7832 .cfi_endproc + 7833 .LFE68: + 7835 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + 7836 .align 1 + 7837 .global HAL_I2C_EV_IRQHandler + 7838 .syntax unified + 7839 .code 16 + 7840 .thumb_func + 7841 .fpu softvfp + 7843 HAL_I2C_EV_IRQHandler: + 7844 .LFB69: +2979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 7845 .loc 1 2979 0 + 7846 .cfi_startproc + 7847 @ args = 0, pretend = 0, frame = 0 + 7848 @ frame_needed = 0, uses_anonymous_args = 0 + 7849 .LVL735: + 7850 0000 10B5 push {r4, lr} + 7851 .LCFI57: + 7852 .cfi_def_cfa_offset 8 + 7853 .cfi_offset 4, -8 + 7854 .cfi_offset 14, -4 +2981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 7855 .loc 1 2981 0 + 7856 0002 0368 ldr r3, [r0] + 7857 0004 9969 ldr r1, [r3, #24] + 7858 .LVL736: +2982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7859 .loc 1 2982 0 + 7860 0006 1A68 ldr r2, [r3] + 7861 .LVL737: +2985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7862 .loc 1 2985 0 + 7863 0008 436B ldr r3, [r0, #52] + 7864 000a 002B cmp r3, #0 + 7865 000c 00D0 beq .L545 +2987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 243 + + + 7866 .loc 1 2987 0 + 7867 000e 9847 blx r3 + 7868 .LVL738: + 7869 .L545: +2989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7870 .loc 1 2989 0 + 7871 @ sp needed + 7872 0010 10BD pop {r4, pc} + 7873 .cfi_endproc + 7874 .LFE69: + 7876 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + 7877 .align 1 + 7878 .weak HAL_I2C_MasterTxCpltCallback + 7879 .syntax unified + 7880 .code 16 + 7881 .thumb_func + 7882 .fpu softvfp + 7884 HAL_I2C_MasterTxCpltCallback: + 7885 .LFB71: +3043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 7886 .loc 1 3043 0 + 7887 .cfi_startproc + 7888 @ args = 0, pretend = 0, frame = 0 + 7889 @ frame_needed = 0, uses_anonymous_args = 0 + 7890 @ link register save eliminated. + 7891 .LVL739: +3050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7892 .loc 1 3050 0 + 7893 @ sp needed + 7894 0000 7047 bx lr + 7895 .cfi_endproc + 7896 .LFE71: + 7898 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 7899 .align 1 + 7900 .weak HAL_I2C_MasterRxCpltCallback + 7901 .syntax unified + 7902 .code 16 + 7903 .thumb_func + 7904 .fpu softvfp + 7906 HAL_I2C_MasterRxCpltCallback: + 7907 .LFB72: +3059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 7908 .loc 1 3059 0 + 7909 .cfi_startproc + 7910 @ args = 0, pretend = 0, frame = 0 + 7911 @ frame_needed = 0, uses_anonymous_args = 0 + 7912 @ link register save eliminated. + 7913 .LVL740: +3066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7914 .loc 1 3066 0 + 7915 @ sp needed + 7916 0000 7047 bx lr + 7917 .cfi_endproc + 7918 .LFE72: + 7920 .section .text.I2C_ITMasterSequentialCplt,"ax",%progbits + 7921 .align 1 + 7922 .syntax unified + ARM GAS /tmp/ccpuPECZ.s page 244 + + + 7923 .code 16 + 7924 .thumb_func + 7925 .fpu softvfp + 7927 I2C_ITMasterSequentialCplt: + 7928 .LFB91: +3865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset I2C handle mode */ + 7929 .loc 1 3865 0 + 7930 .cfi_startproc + 7931 @ args = 0, pretend = 0, frame = 0 + 7932 @ frame_needed = 0, uses_anonymous_args = 0 + 7933 .LVL741: + 7934 0000 70B5 push {r4, r5, r6, lr} + 7935 .LCFI58: + 7936 .cfi_def_cfa_offset 16 + 7937 .cfi_offset 4, -16 + 7938 .cfi_offset 5, -12 + 7939 .cfi_offset 6, -8 + 7940 .cfi_offset 14, -4 + 7941 0002 0400 movs r4, r0 +3867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7942 .loc 1 3867 0 + 7943 0004 4223 movs r3, #66 + 7944 0006 0022 movs r2, #0 + 7945 0008 C254 strb r2, [r0, r3] +3871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 7946 .loc 1 3871 0 + 7947 000a 013B subs r3, r3, #1 + 7948 000c C35C ldrb r3, [r0, r3] + 7949 000e 212B cmp r3, #33 + 7950 0010 0FD0 beq .L552 +3889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 7951 .loc 1 3889 0 + 7952 0012 4123 movs r3, #65 + 7953 0014 2022 movs r2, #32 + 7954 0016 C254 strb r2, [r0, r3] +3890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 7955 .loc 1 3890 0 + 7956 0018 2F3B subs r3, r3, #47 + 7957 001a 0363 str r3, [r0, #48] +3891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7958 .loc 1 3891 0 + 7959 001c 0025 movs r5, #0 + 7960 001e 4563 str r5, [r0, #52] +3894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7961 .loc 1 3894 0 + 7962 0020 0221 movs r1, #2 + 7963 0022 FFF7FEFF bl I2C_Disable_IRQ + 7964 .LVL742: +3897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7965 .loc 1 3897 0 + 7966 0026 4023 movs r3, #64 + 7967 0028 E554 strb r5, [r4, r3] +3900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7968 .loc 1 3900 0 + 7969 002a 2000 movs r0, r4 + 7970 002c FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 7971 .LVL743: + ARM GAS /tmp/ccpuPECZ.s page 245 + + + 7972 .L549: +3902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7973 .loc 1 3902 0 + 7974 @ sp needed + 7975 .LVL744: + 7976 0030 70BD pop {r4, r5, r6, pc} + 7977 .LVL745: + 7978 .L552: +3873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 7979 .loc 1 3873 0 + 7980 0032 2033 adds r3, r3, #32 + 7981 0034 2032 adds r2, r2, #32 + 7982 0036 C254 strb r2, [r0, r3] +3874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 7983 .loc 1 3874 0 + 7984 0038 303B subs r3, r3, #48 + 7985 003a 0363 str r3, [r0, #48] +3875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7986 .loc 1 3875 0 + 7987 003c 0025 movs r5, #0 + 7988 003e 4563 str r5, [r0, #52] +3878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7989 .loc 1 3878 0 + 7990 0040 0121 movs r1, #1 + 7991 0042 FFF7FEFF bl I2C_Disable_IRQ + 7992 .LVL746: +3881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 7993 .loc 1 3881 0 + 7994 0046 4023 movs r3, #64 + 7995 0048 E554 strb r5, [r4, r3] +3884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 7996 .loc 1 3884 0 + 7997 004a 2000 movs r0, r4 + 7998 004c FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 7999 .LVL747: + 8000 0050 EEE7 b .L549 + 8001 .cfi_endproc + 8002 .LFE91: + 8004 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 8005 .align 1 + 8006 .weak HAL_I2C_SlaveTxCpltCallback + 8007 .syntax unified + 8008 .code 16 + 8009 .thumb_func + 8010 .fpu softvfp + 8012 HAL_I2C_SlaveTxCpltCallback: + 8013 .LFB73: +3074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8014 .loc 1 3074 0 + 8015 .cfi_startproc + 8016 @ args = 0, pretend = 0, frame = 0 + 8017 @ frame_needed = 0, uses_anonymous_args = 0 + 8018 @ link register save eliminated. + 8019 .LVL748: +3081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8020 .loc 1 3081 0 + 8021 @ sp needed + ARM GAS /tmp/ccpuPECZ.s page 246 + + + 8022 0000 7047 bx lr + 8023 .cfi_endproc + 8024 .LFE73: + 8026 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 8027 .align 1 + 8028 .weak HAL_I2C_SlaveRxCpltCallback + 8029 .syntax unified + 8030 .code 16 + 8031 .thumb_func + 8032 .fpu softvfp + 8034 HAL_I2C_SlaveRxCpltCallback: + 8035 .LFB74: +3090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8036 .loc 1 3090 0 + 8037 .cfi_startproc + 8038 @ args = 0, pretend = 0, frame = 0 + 8039 @ frame_needed = 0, uses_anonymous_args = 0 + 8040 @ link register save eliminated. + 8041 .LVL749: +3097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8042 .loc 1 3097 0 + 8043 @ sp needed + 8044 0000 7047 bx lr + 8045 .cfi_endproc + 8046 .LFE74: + 8048 .section .text.I2C_ITSlaveSequentialCplt,"ax",%progbits + 8049 .align 1 + 8050 .syntax unified + 8051 .code 16 + 8052 .thumb_func + 8053 .fpu softvfp + 8055 I2C_ITSlaveSequentialCplt: + 8056 .LFB92: +3910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset I2C handle mode */ + 8057 .loc 1 3910 0 + 8058 .cfi_startproc + 8059 @ args = 0, pretend = 0, frame = 0 + 8060 @ frame_needed = 0, uses_anonymous_args = 0 + 8061 .LVL750: + 8062 0000 10B5 push {r4, lr} + 8063 .LCFI59: + 8064 .cfi_def_cfa_offset 8 + 8065 .cfi_offset 4, -8 + 8066 .cfi_offset 14, -4 + 8067 0002 0400 movs r4, r0 +3912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8068 .loc 1 3912 0 + 8069 0004 4223 movs r3, #66 + 8070 0006 0022 movs r2, #0 + 8071 0008 C254 strb r2, [r0, r3] +3914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8072 .loc 1 3914 0 + 8073 000a 013B subs r3, r3, #1 + 8074 000c C35C ldrb r3, [r0, r3] + 8075 000e 292B cmp r3, #41 + 8076 0010 04D0 beq .L558 +3930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 247 + + + 8077 .loc 1 3930 0 + 8078 0012 4123 movs r3, #65 + 8079 0014 C35C ldrb r3, [r0, r3] + 8080 0016 2A2B cmp r3, #42 + 8081 0018 0FD0 beq .L559 + 8082 .LVL751: + 8083 .L555: +3945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8084 .loc 1 3945 0 + 8085 @ sp needed + 8086 .LVL752: + 8087 001a 10BD pop {r4, pc} + 8088 .LVL753: + 8089 .L558: +3917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 8090 .loc 1 3917 0 + 8091 001c 1833 adds r3, r3, #24 + 8092 001e 2832 adds r2, r2, #40 + 8093 0020 C254 strb r2, [r0, r3] +3918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8094 .loc 1 3918 0 + 8095 0022 203B subs r3, r3, #32 + 8096 0024 0363 str r3, [r0, #48] +3921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8097 .loc 1 3921 0 + 8098 0026 0121 movs r1, #1 + 8099 0028 FFF7FEFF bl I2C_Disable_IRQ + 8100 .LVL754: +3924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8101 .loc 1 3924 0 + 8102 002c 4023 movs r3, #64 + 8103 002e 0022 movs r2, #0 + 8104 0030 E254 strb r2, [r4, r3] +3927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8105 .loc 1 3927 0 + 8106 0032 2000 movs r0, r4 + 8107 0034 FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 8108 .LVL755: + 8109 0038 EFE7 b .L555 + 8110 .LVL756: + 8111 .L559: +3933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 8112 .loc 1 3933 0 + 8113 003a 1733 adds r3, r3, #23 + 8114 003c 2822 movs r2, #40 + 8115 003e C254 strb r2, [r0, r3] +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8116 .loc 1 3934 0 + 8117 0040 1F3B subs r3, r3, #31 + 8118 0042 0363 str r3, [r0, #48] +3937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8119 .loc 1 3937 0 + 8120 0044 0221 movs r1, #2 + 8121 0046 FFF7FEFF bl I2C_Disable_IRQ + 8122 .LVL757: +3940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8123 .loc 1 3940 0 + ARM GAS /tmp/ccpuPECZ.s page 248 + + + 8124 004a 4023 movs r3, #64 + 8125 004c 0022 movs r2, #0 + 8126 004e E254 strb r2, [r4, r3] +3943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8127 .loc 1 3943 0 + 8128 0050 2000 movs r0, r4 + 8129 0052 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 8130 .LVL758: +3945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8131 .loc 1 3945 0 + 8132 0056 E0E7 b .L555 + 8133 .cfi_endproc + 8134 .LFE92: + 8136 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 8137 .align 1 + 8138 .weak HAL_I2C_AddrCallback + 8139 .syntax unified + 8140 .code 16 + 8141 .thumb_func + 8142 .fpu softvfp + 8144 HAL_I2C_AddrCallback: + 8145 .LFB75: +3108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8146 .loc 1 3108 0 + 8147 .cfi_startproc + 8148 @ args = 0, pretend = 0, frame = 0 + 8149 @ frame_needed = 0, uses_anonymous_args = 0 + 8150 @ link register save eliminated. + 8151 .LVL759: +3117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8152 .loc 1 3117 0 + 8153 @ sp needed + 8154 0000 7047 bx lr + 8155 .cfi_endproc + 8156 .LFE75: + 8158 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 8159 .align 1 + 8160 .weak HAL_I2C_ListenCpltCallback + 8161 .syntax unified + 8162 .code 16 + 8163 .thumb_func + 8164 .fpu softvfp + 8166 HAL_I2C_ListenCpltCallback: + 8167 .LFB76: +3126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8168 .loc 1 3126 0 + 8169 .cfi_startproc + 8170 @ args = 0, pretend = 0, frame = 0 + 8171 @ frame_needed = 0, uses_anonymous_args = 0 + 8172 @ link register save eliminated. + 8173 .LVL760: +3133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8174 .loc 1 3133 0 + 8175 @ sp needed + 8176 0000 7047 bx lr + 8177 .cfi_endproc + 8178 .LFE76: + ARM GAS /tmp/ccpuPECZ.s page 249 + + + 8180 .section .text.I2C_ITListenCplt,"ax",%progbits + 8181 .align 1 + 8182 .syntax unified + 8183 .code 16 + 8184 .thumb_func + 8185 .fpu softvfp + 8187 I2C_ITListenCplt: + 8188 .LFB95: +4152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset handle parameters */ + 8189 .loc 1 4152 0 + 8190 .cfi_startproc + 8191 @ args = 0, pretend = 0, frame = 0 + 8192 @ frame_needed = 0, uses_anonymous_args = 0 + 8193 .LVL761: + 8194 0000 10B5 push {r4, lr} + 8195 .LCFI60: + 8196 .cfi_def_cfa_offset 8 + 8197 .cfi_offset 4, -8 + 8198 .cfi_offset 14, -4 + 8199 0002 0400 movs r4, r0 +4154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 8200 .loc 1 4154 0 + 8201 0004 164B ldr r3, .L564 + 8202 0006 C362 str r3, [r0, #44] +4155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 8203 .loc 1 4155 0 + 8204 0008 0023 movs r3, #0 + 8205 000a 0363 str r3, [r0, #48] +4156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8206 .loc 1 4156 0 + 8207 000c 4122 movs r2, #65 + 8208 000e 2020 movs r0, #32 + 8209 .LVL762: + 8210 0010 A054 strb r0, [r4, r2] +4157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 8211 .loc 1 4157 0 + 8212 0012 0132 adds r2, r2, #1 + 8213 0014 A354 strb r3, [r4, r2] +4158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8214 .loc 1 4158 0 + 8215 0016 6363 str r3, [r4, #52] +4161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8216 .loc 1 4161 0 + 8217 0018 4B07 lsls r3, r1, #29 + 8218 001a 12D5 bpl .L563 +4164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8219 .loc 1 4164 0 + 8220 001c 2368 ldr r3, [r4] + 8221 001e 5A6A ldr r2, [r3, #36] + 8222 0020 636A ldr r3, [r4, #36] + 8223 0022 591C adds r1, r3, #1 + 8224 .LVL763: + 8225 0024 6162 str r1, [r4, #36] + 8226 0026 1A70 strb r2, [r3] +4166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8227 .loc 1 4166 0 + 8228 0028 238D ldrh r3, [r4, #40] + ARM GAS /tmp/ccpuPECZ.s page 250 + + + 8229 002a 002B cmp r3, #0 + 8230 002c 09D0 beq .L563 +4168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 8231 .loc 1 4168 0 + 8232 002e 013B subs r3, r3, #1 + 8233 0030 2385 strh r3, [r4, #40] +4169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8234 .loc 1 4169 0 + 8235 0032 638D ldrh r3, [r4, #42] + 8236 0034 013B subs r3, r3, #1 + 8237 0036 9BB2 uxth r3, r3 + 8238 0038 6385 strh r3, [r4, #42] +4172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8239 .loc 1 4172 0 + 8240 003a 636C ldr r3, [r4, #68] + 8241 003c 0422 movs r2, #4 + 8242 003e 1343 orrs r3, r2 + 8243 0040 6364 str r3, [r4, #68] + 8244 .L563: +4177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8245 .loc 1 4177 0 + 8246 0042 0721 movs r1, #7 + 8247 0044 2000 movs r0, r4 + 8248 0046 FFF7FEFF bl I2C_Disable_IRQ + 8249 .LVL764: +4180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8250 .loc 1 4180 0 + 8251 004a 2368 ldr r3, [r4] + 8252 004c 1022 movs r2, #16 + 8253 004e DA61 str r2, [r3, #28] +4183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8254 .loc 1 4183 0 + 8255 0050 4023 movs r3, #64 + 8256 0052 0022 movs r2, #0 + 8257 0054 E254 strb r2, [r4, r3] +4186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8258 .loc 1 4186 0 + 8259 0056 2000 movs r0, r4 + 8260 0058 FFF7FEFF bl HAL_I2C_ListenCpltCallback + 8261 .LVL765: +4187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8262 .loc 1 4187 0 + 8263 @ sp needed + 8264 .LVL766: + 8265 005c 10BD pop {r4, pc} + 8266 .L565: + 8267 005e C046 .align 2 + 8268 .L564: + 8269 0060 0000FFFF .word -65536 + 8270 .cfi_endproc + 8271 .LFE95: + 8273 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 8274 .align 1 + 8275 .weak HAL_I2C_MemTxCpltCallback + 8276 .syntax unified + 8277 .code 16 + 8278 .thumb_func + ARM GAS /tmp/ccpuPECZ.s page 251 + + + 8279 .fpu softvfp + 8281 HAL_I2C_MemTxCpltCallback: + 8282 .LFB77: +3142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8283 .loc 1 3142 0 + 8284 .cfi_startproc + 8285 @ args = 0, pretend = 0, frame = 0 + 8286 @ frame_needed = 0, uses_anonymous_args = 0 + 8287 @ link register save eliminated. + 8288 .LVL767: +3149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8289 .loc 1 3149 0 + 8290 @ sp needed + 8291 0000 7047 bx lr + 8292 .cfi_endproc + 8293 .LFE77: + 8295 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 8296 .align 1 + 8297 .weak HAL_I2C_MemRxCpltCallback + 8298 .syntax unified + 8299 .code 16 + 8300 .thumb_func + 8301 .fpu softvfp + 8303 HAL_I2C_MemRxCpltCallback: + 8304 .LFB78: +3158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8305 .loc 1 3158 0 + 8306 .cfi_startproc + 8307 @ args = 0, pretend = 0, frame = 0 + 8308 @ frame_needed = 0, uses_anonymous_args = 0 + 8309 @ link register save eliminated. + 8310 .LVL768: +3165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8311 .loc 1 3165 0 + 8312 @ sp needed + 8313 0000 7047 bx lr + 8314 .cfi_endproc + 8315 .LFE78: + 8317 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 8318 .align 1 + 8319 .weak HAL_I2C_ErrorCallback + 8320 .syntax unified + 8321 .code 16 + 8322 .thumb_func + 8323 .fpu softvfp + 8325 HAL_I2C_ErrorCallback: + 8326 .LFB79: +3174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8327 .loc 1 3174 0 + 8328 .cfi_startproc + 8329 @ args = 0, pretend = 0, frame = 0 + 8330 @ frame_needed = 0, uses_anonymous_args = 0 + 8331 @ link register save eliminated. + 8332 .LVL769: +3181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8333 .loc 1 3181 0 + 8334 @ sp needed + ARM GAS /tmp/ccpuPECZ.s page 252 + + + 8335 0000 7047 bx lr + 8336 .cfi_endproc + 8337 .LFE79: + 8339 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 8340 .align 1 + 8341 .weak HAL_I2C_AbortCpltCallback + 8342 .syntax unified + 8343 .code 16 + 8344 .thumb_func + 8345 .fpu softvfp + 8347 HAL_I2C_AbortCpltCallback: + 8348 .LFB80: +3190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 8349 .loc 1 3190 0 + 8350 .cfi_startproc + 8351 @ args = 0, pretend = 0, frame = 0 + 8352 @ frame_needed = 0, uses_anonymous_args = 0 + 8353 @ link register save eliminated. + 8354 .LVL770: +3197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8355 .loc 1 3197 0 + 8356 @ sp needed + 8357 0000 7047 bx lr + 8358 .cfi_endproc + 8359 .LFE80: + 8361 .section .text.I2C_ITError,"ax",%progbits + 8362 .align 1 + 8363 .syntax unified + 8364 .code 16 + 8365 .thumb_func + 8366 .fpu softvfp + 8368 I2C_ITError: + 8369 .LFB96: +4196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Reset handle parameters */ + 8370 .loc 1 4196 0 + 8371 .cfi_startproc + 8372 @ args = 0, pretend = 0, frame = 0 + 8373 @ frame_needed = 0, uses_anonymous_args = 0 + 8374 .LVL771: + 8375 0000 10B5 push {r4, lr} + 8376 .LCFI61: + 8377 .cfi_def_cfa_offset 8 + 8378 .cfi_offset 4, -8 + 8379 .cfi_offset 14, -4 + 8380 0002 0400 movs r4, r0 +4198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 8381 .loc 1 4198 0 + 8382 0004 0023 movs r3, #0 + 8383 0006 4222 movs r2, #66 + 8384 0008 8354 strb r3, [r0, r2] +4199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount = 0U; + 8385 .loc 1 4199 0 + 8386 000a 364A ldr r2, .L582 + 8387 000c C262 str r2, [r0, #44] +4200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8388 .loc 1 4200 0 + 8389 000e 4385 strh r3, [r0, #42] + ARM GAS /tmp/ccpuPECZ.s page 253 + + +4203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8390 .loc 1 4203 0 + 8391 0010 436C ldr r3, [r0, #68] + 8392 0012 1943 orrs r1, r3 + 8393 .LVL772: + 8394 0014 4164 str r1, [r0, #68] +4206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 8395 .loc 1 4206 0 + 8396 0016 4123 movs r3, #65 + 8397 0018 C35C ldrb r3, [r0, r3] + 8398 001a 282B cmp r3, #40 + 8399 001c 07D0 beq .L571 +4207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 8400 .loc 1 4207 0 discriminator 1 + 8401 001e 4123 movs r3, #65 + 8402 0020 C35C ldrb r3, [r0, r3] +4206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 8403 .loc 1 4206 0 discriminator 1 + 8404 0022 292B cmp r3, #41 + 8405 0024 03D0 beq .L571 +4208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8406 .loc 1 4208 0 + 8407 0026 4123 movs r3, #65 + 8408 0028 C35C ldrb r3, [r0, r3] +4207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 8409 .loc 1 4207 0 + 8410 002a 2A2B cmp r3, #42 + 8411 002c 1CD1 bne .L572 + 8412 .L571: +4211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8413 .loc 1 4211 0 + 8414 002e 0321 movs r1, #3 + 8415 0030 2000 movs r0, r4 + 8416 .LVL773: + 8417 0032 FFF7FEFF bl I2C_Disable_IRQ + 8418 .LVL774: +4214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 8419 .loc 1 4214 0 + 8420 0036 4123 movs r3, #65 + 8421 0038 2822 movs r2, #40 + 8422 003a E254 strb r2, [r4, r3] +4215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8423 .loc 1 4215 0 + 8424 003c 0023 movs r3, #0 + 8425 003e 2363 str r3, [r4, #48] +4216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8426 .loc 1 4216 0 + 8427 0040 294B ldr r3, .L582+4 + 8428 0042 6363 str r3, [r4, #52] + 8429 .L573: +4235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8430 .loc 1 4235 0 + 8431 0044 2368 ldr r3, [r4] + 8432 0046 1A68 ldr r2, [r3] + 8433 0048 5204 lsls r2, r2, #17 + 8434 004a 1BD4 bmi .L579 +4254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 254 + + + 8435 .loc 1 4254 0 + 8436 004c 1A68 ldr r2, [r3] + 8437 004e 1204 lsls r2, r2, #16 + 8438 0050 2BD4 bmi .L580 +4272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8439 .loc 1 4272 0 + 8440 0052 4123 movs r3, #65 + 8441 0054 E35C ldrb r3, [r4, r3] + 8442 0056 602B cmp r3, #96 + 8443 0058 3AD0 beq .L581 +4285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8444 .loc 1 4285 0 + 8445 005a 4023 movs r3, #64 + 8446 005c 0022 movs r2, #0 + 8447 005e E254 strb r2, [r4, r3] +4288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8448 .loc 1 4288 0 + 8449 0060 2000 movs r0, r4 + 8450 0062 FFF7FEFF bl HAL_I2C_ErrorCallback + 8451 .LVL775: + 8452 .L570: +4290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8453 .loc 1 4290 0 + 8454 @ sp needed + 8455 .LVL776: + 8456 0066 10BD pop {r4, pc} + 8457 .LVL777: + 8458 .L572: +4221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8459 .loc 1 4221 0 + 8460 0068 0721 movs r1, #7 + 8461 006a FFF7FEFF bl I2C_Disable_IRQ + 8462 .LVL778: +4225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8463 .loc 1 4225 0 + 8464 006e 4123 movs r3, #65 + 8465 0070 E35C ldrb r3, [r4, r3] + 8466 0072 602B cmp r3, #96 + 8467 0074 02D0 beq .L574 +4228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8468 .loc 1 4228 0 + 8469 0076 4123 movs r3, #65 + 8470 0078 2022 movs r2, #32 + 8471 007a E254 strb r2, [r4, r3] + 8472 .L574: +4230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 8473 .loc 1 4230 0 + 8474 007c 0023 movs r3, #0 + 8475 007e 2363 str r3, [r4, #48] +4231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8476 .loc 1 4231 0 + 8477 0080 6363 str r3, [r4, #52] + 8478 0082 DFE7 b .L573 + 8479 .L579: +4237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8480 .loc 1 4237 0 + 8481 0084 1A68 ldr r2, [r3] + ARM GAS /tmp/ccpuPECZ.s page 255 + + + 8482 0086 1949 ldr r1, .L582+8 + 8483 0088 0A40 ands r2, r1 + 8484 008a 1A60 str r2, [r3] +4241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8485 .loc 1 4241 0 + 8486 008c A36B ldr r3, [r4, #56] + 8487 008e 184A ldr r2, .L582+12 + 8488 0090 9A63 str r2, [r3, #56] +4244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8489 .loc 1 4244 0 + 8490 0092 4023 movs r3, #64 + 8491 0094 0022 movs r2, #0 + 8492 0096 E254 strb r2, [r4, r3] +4247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8493 .loc 1 4247 0 + 8494 0098 A06B ldr r0, [r4, #56] + 8495 009a FFF7FEFF bl HAL_DMA_Abort_IT + 8496 .LVL779: + 8497 009e 0028 cmp r0, #0 + 8498 00a0 E1D0 beq .L570 +4250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8499 .loc 1 4250 0 + 8500 00a2 A06B ldr r0, [r4, #56] + 8501 00a4 836B ldr r3, [r0, #56] + 8502 00a6 9847 blx r3 + 8503 .LVL780: + 8504 00a8 DDE7 b .L570 + 8505 .L580: +4256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8506 .loc 1 4256 0 + 8507 00aa 1A68 ldr r2, [r3] + 8508 00ac 1149 ldr r1, .L582+16 + 8509 00ae 0A40 ands r2, r1 + 8510 00b0 1A60 str r2, [r3] +4260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8511 .loc 1 4260 0 + 8512 00b2 E36B ldr r3, [r4, #60] + 8513 00b4 0E4A ldr r2, .L582+12 + 8514 00b6 9A63 str r2, [r3, #56] +4263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8515 .loc 1 4263 0 + 8516 00b8 4023 movs r3, #64 + 8517 00ba 0022 movs r2, #0 + 8518 00bc E254 strb r2, [r4, r3] +4266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8519 .loc 1 4266 0 + 8520 00be E06B ldr r0, [r4, #60] + 8521 00c0 FFF7FEFF bl HAL_DMA_Abort_IT + 8522 .LVL781: + 8523 00c4 0028 cmp r0, #0 + 8524 00c6 CED0 beq .L570 +4269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8525 .loc 1 4269 0 + 8526 00c8 E06B ldr r0, [r4, #60] + 8527 00ca 836B ldr r3, [r0, #56] + 8528 00cc 9847 blx r3 + 8529 .LVL782: + ARM GAS /tmp/ccpuPECZ.s page 256 + + + 8530 00ce CAE7 b .L570 + 8531 .L581: +4274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8532 .loc 1 4274 0 + 8533 00d0 1F3B subs r3, r3, #31 + 8534 00d2 2022 movs r2, #32 + 8535 00d4 E254 strb r2, [r4, r3] +4277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8536 .loc 1 4277 0 + 8537 00d6 013B subs r3, r3, #1 + 8538 00d8 0022 movs r2, #0 + 8539 00da E254 strb r2, [r4, r3] +4280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8540 .loc 1 4280 0 + 8541 00dc 2000 movs r0, r4 + 8542 00de FFF7FEFF bl HAL_I2C_AbortCpltCallback + 8543 .LVL783: + 8544 00e2 C0E7 b .L570 + 8545 .L583: + 8546 .align 2 + 8547 .L582: + 8548 00e4 0000FFFF .word -65536 + 8549 00e8 00000000 .word I2C_Slave_ISR_IT + 8550 00ec FFBFFFFF .word -16385 + 8551 00f0 00000000 .word I2C_DMAAbort + 8552 00f4 FF7FFFFF .word -32769 + 8553 .cfi_endproc + 8554 .LFE96: + 8556 .section .text.I2C_ITSlaveCplt,"ax",%progbits + 8557 .align 1 + 8558 .syntax unified + 8559 .code 16 + 8560 .thumb_func + 8561 .fpu softvfp + 8563 I2C_ITSlaveCplt: + 8564 .LFB94: +4046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ + 8565 .loc 1 4046 0 + 8566 .cfi_startproc + 8567 @ args = 0, pretend = 0, frame = 0 + 8568 @ frame_needed = 0, uses_anonymous_args = 0 + 8569 .LVL784: + 8570 0000 70B5 push {r4, r5, r6, lr} + 8571 .LCFI62: + 8572 .cfi_def_cfa_offset 16 + 8573 .cfi_offset 4, -16 + 8574 .cfi_offset 5, -12 + 8575 .cfi_offset 6, -8 + 8576 .cfi_offset 14, -4 + 8577 0002 0400 movs r4, r0 + 8578 0004 0D00 movs r5, r1 +4048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8579 .loc 1 4048 0 + 8580 0006 0368 ldr r3, [r0] + 8581 0008 2022 movs r2, #32 + 8582 000a DA61 str r2, [r3, #28] +4051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + ARM GAS /tmp/ccpuPECZ.s page 257 + + + 8583 .loc 1 4051 0 + 8584 000c 0368 ldr r3, [r0] + 8585 000e 183A subs r2, r2, #24 + 8586 0010 DA61 str r2, [r3, #28] +4054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8587 .loc 1 4054 0 + 8588 0012 0721 movs r1, #7 + 8589 .LVL785: + 8590 0014 FFF7FEFF bl I2C_Disable_IRQ + 8591 .LVL786: +4057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8592 .loc 1 4057 0 + 8593 0018 2268 ldr r2, [r4] + 8594 001a 5168 ldr r1, [r2, #4] + 8595 001c 8023 movs r3, #128 + 8596 001e 1B02 lsls r3, r3, #8 + 8597 0020 0B43 orrs r3, r1 + 8598 0022 5360 str r3, [r2, #4] +4060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8599 .loc 1 4060 0 + 8600 0024 2268 ldr r2, [r4] + 8601 0026 5368 ldr r3, [r2, #4] + 8602 0028 3E49 ldr r1, .L601 + 8603 002a 0B40 ands r3, r1 + 8604 002c 5360 str r3, [r2, #4] + 8605 .LVL787: + 8606 .LBB300: + 8607 .LBB301: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8608 .loc 1 4301 0 + 8609 002e 2368 ldr r3, [r4] + 8610 0030 9A69 ldr r2, [r3, #24] + 8611 0032 9207 lsls r2, r2, #30 + 8612 0034 01D5 bpl .L585 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8613 .loc 1 4303 0 + 8614 0036 0022 movs r2, #0 + 8615 0038 9A62 str r2, [r3, #40] + 8616 .L585: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8617 .loc 1 4307 0 + 8618 003a 2368 ldr r3, [r4] + 8619 003c 9A69 ldr r2, [r3, #24] + 8620 003e D207 lsls r2, r2, #31 + 8621 0040 03D4 bmi .L586 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8622 .loc 1 4309 0 + 8623 0042 9A69 ldr r2, [r3, #24] + 8624 0044 0121 movs r1, #1 + 8625 0046 0A43 orrs r2, r1 + 8626 0048 9A61 str r2, [r3, #24] + 8627 .L586: + 8628 .LVL788: + 8629 .LBE301: + 8630 .LBE300: +4066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + 8631 .loc 1 4066 0 + ARM GAS /tmp/ccpuPECZ.s page 258 + + + 8632 004a 2268 ldr r2, [r4] + 8633 004c 1368 ldr r3, [r2] + 8634 004e 5B04 lsls r3, r3, #17 + 8635 0050 02D4 bmi .L587 +4067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8636 .loc 1 4067 0 discriminator 1 + 8637 0052 1368 ldr r3, [r2] +4066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + 8638 .loc 1 4066 0 discriminator 1 + 8639 0054 1B04 lsls r3, r3, #16 + 8640 0056 08D5 bpl .L588 + 8641 .L587: +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8642 .loc 1 4069 0 + 8643 0058 4123 movs r3, #65 + 8644 005a E35C ldrb r3, [r4, r3] + 8645 005c 212B cmp r3, #33 + 8646 005e 3AD0 beq .L597 +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8647 .loc 1 4069 0 is_stmt 0 discriminator 2 + 8648 0060 E36B ldr r3, [r4, #60] + 8649 0062 1B68 ldr r3, [r3] + 8650 0064 5B68 ldr r3, [r3, #4] + 8651 0066 9BB2 uxth r3, r3 + 8652 .L590: +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8653 .loc 1 4069 0 discriminator 4 + 8654 0068 6385 strh r3, [r4, #42] + 8655 .L588: +4073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8656 .loc 1 4073 0 is_stmt 1 + 8657 006a 638D ldrh r3, [r4, #42] + 8658 006c 9BB2 uxth r3, r3 + 8659 006e 002B cmp r3, #0 + 8660 0070 03D0 beq .L591 +4076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8661 .loc 1 4076 0 + 8662 0072 636C ldr r3, [r4, #68] + 8663 0074 0421 movs r1, #4 + 8664 0076 0B43 orrs r3, r1 + 8665 0078 6364 str r3, [r4, #68] + 8666 .L591: +4080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8667 .loc 1 4080 0 + 8668 007a 6B07 lsls r3, r5, #29 + 8669 007c 11D5 bpl .L592 +4083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8670 .loc 1 4083 0 + 8671 007e 526A ldr r2, [r2, #36] + 8672 0080 636A ldr r3, [r4, #36] + 8673 0082 591C adds r1, r3, #1 + 8674 0084 6162 str r1, [r4, #36] + 8675 0086 1A70 strb r2, [r3] +4085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8676 .loc 1 4085 0 + 8677 0088 238D ldrh r3, [r4, #40] + 8678 008a 002B cmp r3, #0 + ARM GAS /tmp/ccpuPECZ.s page 259 + + + 8679 008c 09D0 beq .L592 +4087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 8680 .loc 1 4087 0 + 8681 008e 013B subs r3, r3, #1 + 8682 0090 2385 strh r3, [r4, #40] +4088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8683 .loc 1 4088 0 + 8684 0092 638D ldrh r3, [r4, #42] + 8685 0094 013B subs r3, r3, #1 + 8686 0096 9BB2 uxth r3, r3 + 8687 0098 6385 strh r3, [r4, #42] +4091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8688 .loc 1 4091 0 + 8689 009a 636C ldr r3, [r4, #68] + 8690 009c 0422 movs r2, #4 + 8691 009e 1343 orrs r3, r2 + 8692 00a0 6364 str r3, [r4, #68] + 8693 .L592: +4095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8694 .loc 1 4095 0 + 8695 00a2 0023 movs r3, #0 + 8696 00a4 2363 str r3, [r4, #48] +4096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 8697 .loc 1 4096 0 + 8698 00a6 4222 movs r2, #66 + 8699 00a8 A354 strb r3, [r4, r2] +4097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8700 .loc 1 4097 0 + 8701 00aa 6363 str r3, [r4, #52] +4099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8702 .loc 1 4099 0 + 8703 00ac 636C ldr r3, [r4, #68] + 8704 00ae 002B cmp r3, #0 + 8705 00b0 16D1 bne .L598 +4111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8706 .loc 1 4111 0 + 8707 00b2 E26A ldr r2, [r4, #44] + 8708 00b4 1C4B ldr r3, .L601+4 + 8709 00b6 9A42 cmp r2, r3 + 8710 00b8 1FD1 bne .L599 +4123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8711 .loc 1 4123 0 + 8712 00ba 4123 movs r3, #65 + 8713 00bc E35C ldrb r3, [r4, r3] + 8714 00be 222B cmp r3, #34 + 8715 00c0 26D0 beq .L600 +4135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8716 .loc 1 4135 0 + 8717 00c2 4123 movs r3, #65 + 8718 00c4 2022 movs r2, #32 + 8719 00c6 E254 strb r2, [r4, r3] +4138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8720 .loc 1 4138 0 + 8721 00c8 013B subs r3, r3, #1 + 8722 00ca 0022 movs r2, #0 + 8723 00cc E254 strb r2, [r4, r3] +4141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + ARM GAS /tmp/ccpuPECZ.s page 260 + + + 8724 .loc 1 4141 0 + 8725 00ce 2000 movs r0, r4 + 8726 00d0 FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 8727 .LVL789: +4143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8728 .loc 1 4143 0 + 8729 00d4 1BE0 b .L584 + 8730 .L597: +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8731 .loc 1 4069 0 discriminator 1 + 8732 00d6 A36B ldr r3, [r4, #56] + 8733 00d8 1B68 ldr r3, [r3] + 8734 00da 5B68 ldr r3, [r3, #4] + 8735 00dc 9BB2 uxth r3, r3 + 8736 00de C3E7 b .L590 + 8737 .L598: +4102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8738 .loc 1 4102 0 + 8739 00e0 616C ldr r1, [r4, #68] + 8740 00e2 2000 movs r0, r4 + 8741 00e4 FFF7FEFF bl I2C_ITError + 8742 .LVL790: +4105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8743 .loc 1 4105 0 + 8744 00e8 4123 movs r3, #65 + 8745 00ea E35C ldrb r3, [r4, r3] + 8746 00ec 282B cmp r3, #40 + 8747 00ee 0ED1 bne .L584 +4108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8748 .loc 1 4108 0 + 8749 00f0 2900 movs r1, r5 + 8750 00f2 2000 movs r0, r4 + 8751 00f4 FFF7FEFF bl I2C_ITListenCplt + 8752 .LVL791: + 8753 00f8 09E0 b .L584 + 8754 .L599: +4113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 8755 .loc 1 4113 0 + 8756 00fa E362 str r3, [r4, #44] +4114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8757 .loc 1 4114 0 + 8758 00fc 4123 movs r3, #65 + 8759 00fe 2022 movs r2, #32 + 8760 0100 E254 strb r2, [r4, r3] +4117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8761 .loc 1 4117 0 + 8762 0102 013B subs r3, r3, #1 + 8763 0104 0022 movs r2, #0 + 8764 0106 E254 strb r2, [r4, r3] +4120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8765 .loc 1 4120 0 + 8766 0108 2000 movs r0, r4 + 8767 010a FFF7FEFF bl HAL_I2C_ListenCpltCallback + 8768 .LVL792: + 8769 .L584: +4143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8770 .loc 1 4143 0 + ARM GAS /tmp/ccpuPECZ.s page 261 + + + 8771 @ sp needed + 8772 .LVL793: + 8773 .LVL794: + 8774 010e 70BD pop {r4, r5, r6, pc} + 8775 .LVL795: + 8776 .L600: +4125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8777 .loc 1 4125 0 + 8778 0110 1F33 adds r3, r3, #31 + 8779 0112 2022 movs r2, #32 + 8780 0114 E254 strb r2, [r4, r3] +4128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8781 .loc 1 4128 0 + 8782 0116 013B subs r3, r3, #1 + 8783 0118 0022 movs r2, #0 + 8784 011a E254 strb r2, [r4, r3] +4131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8785 .loc 1 4131 0 + 8786 011c 2000 movs r0, r4 + 8787 011e FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 8788 .LVL796: + 8789 0122 F4E7 b .L584 + 8790 .L602: + 8791 .align 2 + 8792 .L601: + 8793 0124 00E800FE .word -33495040 + 8794 0128 0000FFFF .word -65536 + 8795 .cfi_endproc + 8796 .LFE94: + 8798 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 8799 .align 1 + 8800 .syntax unified + 8801 .code 16 + 8802 .thumb_func + 8803 .fpu softvfp + 8805 I2C_Slave_ISR_IT: + 8806 .LFB85: +3394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process locked */ + 8807 .loc 1 3394 0 + 8808 .cfi_startproc + 8809 @ args = 0, pretend = 0, frame = 0 + 8810 @ frame_needed = 0, uses_anonymous_args = 0 + 8811 .LVL797: + 8812 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8813 .LCFI63: + 8814 .cfi_def_cfa_offset 24 + 8815 .cfi_offset 3, -24 + 8816 .cfi_offset 4, -20 + 8817 .cfi_offset 5, -16 + 8818 .cfi_offset 6, -12 + 8819 .cfi_offset 7, -8 + 8820 .cfi_offset 14, -4 + 8821 0002 CE46 mov lr, r9 + 8822 0004 4746 mov r7, r8 + 8823 0006 80B5 push {r7, lr} + 8824 .LCFI64: + 8825 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccpuPECZ.s page 262 + + + 8826 .cfi_offset 8, -32 + 8827 .cfi_offset 9, -28 + 8828 0008 0400 movs r4, r0 + 8829 000a 0D00 movs r5, r1 + 8830 000c 1600 movs r6, r2 +3396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8831 .loc 1 3396 0 + 8832 000e 4023 movs r3, #64 + 8833 0010 C35C ldrb r3, [r0, r3] + 8834 0012 012B cmp r3, #1 + 8835 0014 00D1 bne .LCB9391 + 8836 0016 EEE0 b .L622 @long jump + 8837 .LCB9391: +3396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8838 .loc 1 3396 0 is_stmt 0 discriminator 2 + 8839 0018 4023 movs r3, #64 + 8840 001a 0122 movs r2, #1 + 8841 .LVL798: + 8842 001c C254 strb r2, [r0, r3] +3398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8843 .loc 1 3398 0 is_stmt 1 discriminator 2 + 8844 001e CB06 lsls r3, r1, #27 + 8845 0020 4BD5 bpl .L605 +3398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8846 .loc 1 3398 0 is_stmt 0 discriminator 1 + 8847 0022 F306 lsls r3, r6, #27 + 8848 0024 49D5 bpl .L605 +3404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8849 .loc 1 3404 0 is_stmt 1 + 8850 0026 438D ldrh r3, [r0, #42] + 8851 0028 9BB2 uxth r3, r3 + 8852 002a 002B cmp r3, #0 + 8853 002c 31D1 bne .L606 +3406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_LISTEN)) + 8854 .loc 1 3406 0 + 8855 002e C26A ldr r2, [r0, #44] + 8856 0030 8023 movs r3, #128 + 8857 0032 9B04 lsls r3, r3, #18 + 8858 0034 9A42 cmp r2, r3 + 8859 0036 02D0 beq .L607 +3406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_LISTEN)) + 8860 .loc 1 3406 0 is_stmt 0 discriminator 2 + 8861 0038 C26A ldr r2, [r0, #44] + 8862 003a 9A42 cmp r2, r3 + 8863 003c 03D1 bne .L608 + 8864 .L607: +3407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8865 .loc 1 3407 0 is_stmt 1 discriminator 3 + 8866 003e 4123 movs r3, #65 + 8867 0040 E35C ldrb r3, [r4, r3] +3406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->State == HAL_I2C_STATE_LISTEN)) + 8868 .loc 1 3406 0 discriminator 3 + 8869 0042 282B cmp r3, #40 + 8870 0044 0BD0 beq .L623 + 8871 .L608: +3412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8872 .loc 1 3412 0 + ARM GAS /tmp/ccpuPECZ.s page 263 + + + 8873 0046 E26A ldr r2, [r4, #44] + 8874 0048 6C4B ldr r3, .L628 + 8875 004a 9A42 cmp r2, r3 + 8876 004c 03D0 beq .L610 +3412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8877 .loc 1 3412 0 is_stmt 0 discriminator 1 + 8878 004e 4123 movs r3, #65 + 8879 0050 E35C ldrb r3, [r4, r3] + 8880 0052 292B cmp r3, #41 + 8881 0054 08D0 beq .L624 + 8882 .L610: +3427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8883 .loc 1 3427 0 is_stmt 1 + 8884 0056 2368 ldr r3, [r4] + 8885 0058 1022 movs r2, #16 + 8886 005a DA61 str r2, [r3, #28] + 8887 005c 20E0 b .L609 + 8888 .L623: +3410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8889 .loc 1 3410 0 + 8890 005e 2900 movs r1, r5 + 8891 .LVL799: + 8892 0060 2000 movs r0, r4 + 8893 .LVL800: + 8894 0062 FFF7FEFF bl I2C_ITListenCplt + 8895 .LVL801: + 8896 0066 1BE0 b .L609 + 8897 .LVL802: + 8898 .L624: +3415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8899 .loc 1 3415 0 + 8900 0068 2368 ldr r3, [r4] + 8901 006a 1022 movs r2, #16 + 8902 006c DA61 str r2, [r3, #28] + 8903 .LVL803: + 8904 .LBB306: + 8905 .LBB307: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8906 .loc 1 4301 0 + 8907 006e 2368 ldr r3, [r4] + 8908 0070 9A69 ldr r2, [r3, #24] + 8909 0072 9207 lsls r2, r2, #30 + 8910 0074 01D5 bpl .L611 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8911 .loc 1 4303 0 + 8912 0076 0022 movs r2, #0 + 8913 0078 9A62 str r2, [r3, #40] + 8914 .L611: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8915 .loc 1 4307 0 + 8916 007a 2368 ldr r3, [r4] + 8917 007c 9A69 ldr r2, [r3, #24] + 8918 007e D207 lsls r2, r2, #31 + 8919 0080 03D4 bmi .L612 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8920 .loc 1 4309 0 + 8921 0082 9A69 ldr r2, [r3, #24] + ARM GAS /tmp/ccpuPECZ.s page 264 + + + 8922 0084 0121 movs r1, #1 + 8923 .LVL804: + 8924 0086 0A43 orrs r2, r1 + 8925 0088 9A61 str r2, [r3, #24] + 8926 .L612: + 8927 .LVL805: + 8928 .LBE307: + 8929 .LBE306: +3422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8930 .loc 1 3422 0 + 8931 008a 2000 movs r0, r4 + 8932 .LVL806: + 8933 008c FFF7FEFF bl I2C_ITSlaveSequentialCplt + 8934 .LVL807: + 8935 0090 06E0 b .L609 + 8936 .LVL808: + 8937 .L606: +3434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8938 .loc 1 3434 0 + 8939 0092 0368 ldr r3, [r0] + 8940 0094 1022 movs r2, #16 + 8941 0096 DA61 str r2, [r3, #28] +3437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8942 .loc 1 3437 0 + 8943 0098 436C ldr r3, [r0, #68] + 8944 009a 0C3A subs r2, r2, #12 + 8945 009c 1343 orrs r3, r2 + 8946 009e 4364 str r3, [r0, #68] + 8947 .LVL809: + 8948 .L609: +3486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8949 .loc 1 3486 0 + 8950 00a0 AB06 lsls r3, r5, #26 + 8951 00a2 02D5 bpl .L621 +3486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8952 .loc 1 3486 0 is_stmt 0 discriminator 1 + 8953 00a4 B306 lsls r3, r6, #26 + 8954 00a6 00D5 bpl .LCB9514 + 8955 00a8 A0E0 b .L625 @long jump + 8956 .LCB9514: + 8957 .L621: +3493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8958 .loc 1 3493 0 is_stmt 1 + 8959 00aa 4023 movs r3, #64 + 8960 00ac 0022 movs r2, #0 + 8961 00ae E254 strb r2, [r4, r3] +3495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8962 .loc 1 3495 0 + 8963 00b0 0020 movs r0, #0 + 8964 .L604: +3496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 8965 .loc 1 3496 0 + 8966 @ sp needed + 8967 .LVL810: + 8968 .LVL811: + 8969 .LVL812: + 8970 00b2 0CBC pop {r2, r3} + ARM GAS /tmp/ccpuPECZ.s page 265 + + + 8971 00b4 9046 mov r8, r2 + 8972 00b6 9946 mov r9, r3 + 8973 00b8 F8BD pop {r3, r4, r5, r6, r7, pc} + 8974 .LVL813: + 8975 .L605: +3440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8976 .loc 1 3440 0 + 8977 00ba 6B07 lsls r3, r5, #29 + 8978 00bc 1ED5 bpl .L613 +3440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8979 .loc 1 3440 0 is_stmt 0 discriminator 1 + 8980 00be 7307 lsls r3, r6, #29 + 8981 00c0 1CD5 bpl .L613 +3442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 8982 .loc 1 3442 0 is_stmt 1 + 8983 00c2 638D ldrh r3, [r4, #42] + 8984 00c4 9BB2 uxth r3, r3 + 8985 00c6 002B cmp r3, #0 + 8986 00c8 0CD0 beq .L614 +3445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 8987 .loc 1 3445 0 + 8988 00ca 2368 ldr r3, [r4] + 8989 00cc 5A6A ldr r2, [r3, #36] + 8990 00ce 636A ldr r3, [r4, #36] + 8991 00d0 591C adds r1, r3, #1 + 8992 .LVL814: + 8993 00d2 6162 str r1, [r4, #36] + 8994 00d4 1A70 strb r2, [r3] +3446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 8995 .loc 1 3446 0 + 8996 00d6 238D ldrh r3, [r4, #40] + 8997 00d8 013B subs r3, r3, #1 + 8998 00da 2385 strh r3, [r4, #40] +3447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 8999 .loc 1 3447 0 + 9000 00dc 638D ldrh r3, [r4, #42] + 9001 00de 013B subs r3, r3, #1 + 9002 00e0 9BB2 uxth r3, r3 + 9003 00e2 6385 strh r3, [r4, #42] + 9004 .L614: +3450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + 9005 .loc 1 3450 0 + 9006 00e4 638D ldrh r3, [r4, #42] + 9007 00e6 9BB2 uxth r3, r3 + 9008 00e8 002B cmp r3, #0 + 9009 00ea D9D1 bne .L609 +3451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9010 .loc 1 3451 0 discriminator 1 + 9011 00ec E26A ldr r2, [r4, #44] +3450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + 9012 .loc 1 3450 0 discriminator 1 + 9013 00ee 434B ldr r3, .L628 + 9014 00f0 9A42 cmp r2, r3 + 9015 00f2 D5D0 beq .L609 +3454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9016 .loc 1 3454 0 + 9017 00f4 2000 movs r0, r4 + ARM GAS /tmp/ccpuPECZ.s page 266 + + + 9018 .LVL815: + 9019 00f6 FFF7FEFF bl I2C_ITSlaveSequentialCplt + 9020 .LVL816: + 9021 00fa D1E7 b .L609 + 9022 .LVL817: + 9023 .L613: +3457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9024 .loc 1 3457 0 + 9025 00fc 2B07 lsls r3, r5, #28 + 9026 00fe 01D5 bpl .L615 +3457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9027 .loc 1 3457 0 is_stmt 0 discriminator 1 + 9028 0100 3307 lsls r3, r6, #28 + 9029 0102 15D4 bmi .L626 + 9030 .L615: +3461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9031 .loc 1 3461 0 is_stmt 1 + 9032 0104 AB07 lsls r3, r5, #30 + 9033 0106 CBD5 bpl .L609 +3461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9034 .loc 1 3461 0 is_stmt 0 discriminator 1 + 9035 0108 B307 lsls r3, r6, #30 + 9036 010a C9D5 bpl .L609 +3467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9037 .loc 1 3467 0 is_stmt 1 + 9038 010c 638D ldrh r3, [r4, #42] + 9039 010e 9BB2 uxth r3, r3 + 9040 0110 002B cmp r3, #0 + 9041 0112 5ED0 beq .L619 +3470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 9042 .loc 1 3470 0 + 9043 0114 636A ldr r3, [r4, #36] + 9044 0116 5A1C adds r2, r3, #1 + 9045 0118 6262 str r2, [r4, #36] + 9046 011a 2268 ldr r2, [r4] + 9047 011c 1B78 ldrb r3, [r3] + 9048 011e 9362 str r3, [r2, #40] +3471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 9049 .loc 1 3471 0 + 9050 0120 638D ldrh r3, [r4, #42] + 9051 0122 013B subs r3, r3, #1 + 9052 0124 9BB2 uxth r3, r3 + 9053 0126 6385 strh r3, [r4, #42] +3472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9054 .loc 1 3472 0 + 9055 0128 238D ldrh r3, [r4, #40] + 9056 012a 013B subs r3, r3, #1 + 9057 012c 2385 strh r3, [r4, #40] + 9058 012e B7E7 b .L609 + 9059 .L626: + 9060 .LVL818: + 9061 .LBB308: + 9062 .LBB309: +3792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9063 .loc 1 3792 0 + 9064 0130 4123 movs r3, #65 + 9065 0132 E35C ldrb r3, [r4, r3] + ARM GAS /tmp/ccpuPECZ.s page 267 + + + 9066 0134 2822 movs r2, #40 + 9067 0136 1340 ands r3, r2 + 9068 0138 282B cmp r3, #40 + 9069 013a 06D0 beq .L627 +3852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9070 .loc 1 3852 0 + 9071 013c 2368 ldr r3, [r4] + 9072 013e 0822 movs r2, #8 + 9073 0140 DA61 str r2, [r3, #28] +3855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9074 .loc 1 3855 0 + 9075 0142 4023 movs r3, #64 + 9076 0144 0022 movs r2, #0 + 9077 0146 E254 strb r2, [r4, r3] + 9078 0148 AAE7 b .L609 + 9079 .L627: +3794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9080 .loc 1 3794 0 + 9081 014a 2368 ldr r3, [r4] + 9082 014c 9A69 ldr r2, [r3, #24] + 9083 014e 120C lsrs r2, r2, #16 + 9084 0150 0121 movs r1, #1 + 9085 .LVL819: + 9086 0152 0A40 ands r2, r1 + 9087 0154 9046 mov r8, r2 + 9088 .LVL820: +3795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9089 .loc 1 3795 0 + 9090 0156 9F69 ldr r7, [r3, #24] + 9091 0158 3F0C lsrs r7, r7, #16 + 9092 015a FD31 adds r1, r1, #253 + 9093 015c 0F40 ands r7, r1 + 9094 .LVL821: +3796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9095 .loc 1 3796 0 + 9096 015e 9A68 ldr r2, [r3, #8] + 9097 0160 9205 lsls r2, r2, #22 + 9098 0162 920D lsrs r2, r2, #22 + 9099 .LVL822: +3797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9100 .loc 1 3797 0 + 9101 0164 D868 ldr r0, [r3, #12] + 9102 .LVL823: + 9103 0166 0840 ands r0, r1 + 9104 0168 8146 mov r9, r0 + 9105 .LVL824: +3800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9106 .loc 1 3800 0 + 9107 016a E168 ldr r1, [r4, #12] + 9108 016c 0229 cmp r1, #2 + 9109 016e 23D1 bne .L617 +3802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9110 .loc 1 3802 0 + 9111 0170 D109 lsrs r1, r2, #7 + 9112 0172 4F40 eors r7, r1 + 9113 .LVL825: + 9114 0174 0621 movs r1, #6 + ARM GAS /tmp/ccpuPECZ.s page 268 + + + 9115 0176 3942 tst r1, r7 + 9116 0178 11D1 bne .L618 + 9117 .LVL826: +3805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9118 .loc 1 3805 0 + 9119 017a A16C ldr r1, [r4, #72] + 9120 017c 0131 adds r1, r1, #1 + 9121 017e A164 str r1, [r4, #72] +3806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9122 .loc 1 3806 0 + 9123 0180 A16C ldr r1, [r4, #72] + 9124 0182 0229 cmp r1, #2 + 9125 0184 00D0 beq .LCB9707 + 9126 0186 8BE7 b .L609 @long jump + 9127 .LCB9707: +3809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9128 .loc 1 3809 0 + 9129 0188 0021 movs r1, #0 + 9130 018a A164 str r1, [r4, #72] +3812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9131 .loc 1 3812 0 + 9132 018c 0820 movs r0, #8 + 9133 018e D861 str r0, [r3, #28] +3815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9134 .loc 1 3815 0 + 9135 0190 4023 movs r3, #64 + 9136 0192 E154 strb r1, [r4, r3] +3818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9137 .loc 1 3818 0 + 9138 0194 4146 mov r1, r8 + 9139 0196 2000 movs r0, r4 + 9140 0198 FFF7FEFF bl HAL_I2C_AddrCallback + 9141 .LVL827: + 9142 019c 80E7 b .L609 + 9143 .LVL828: + 9144 .L618: +3826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9145 .loc 1 3826 0 + 9146 019e 0421 movs r1, #4 + 9147 01a0 2000 movs r0, r4 + 9148 01a2 FFF7FEFF bl I2C_Disable_IRQ + 9149 .LVL829: +3829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9150 .loc 1 3829 0 + 9151 01a6 4023 movs r3, #64 + 9152 01a8 0022 movs r2, #0 + 9153 01aa E254 strb r2, [r4, r3] +3832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9154 .loc 1 3832 0 + 9155 01ac 4A46 mov r2, r9 + 9156 01ae 4146 mov r1, r8 + 9157 01b0 2000 movs r0, r4 + 9158 01b2 FFF7FEFF bl HAL_I2C_AddrCallback + 9159 .LVL830: + 9160 01b6 73E7 b .L609 + 9161 .LVL831: + 9162 .L617: + ARM GAS /tmp/ccpuPECZ.s page 269 + + +3839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9163 .loc 1 3839 0 + 9164 01b8 0421 movs r1, #4 + 9165 01ba 2000 movs r0, r4 + 9166 01bc FFF7FEFF bl I2C_Disable_IRQ + 9167 .LVL832: +3842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9168 .loc 1 3842 0 + 9169 01c0 4023 movs r3, #64 + 9170 01c2 0022 movs r2, #0 + 9171 01c4 E254 strb r2, [r4, r3] +3845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9172 .loc 1 3845 0 + 9173 01c6 3A00 movs r2, r7 + 9174 01c8 4146 mov r1, r8 + 9175 01ca 2000 movs r0, r4 + 9176 01cc FFF7FEFF bl HAL_I2C_AddrCallback + 9177 .LVL833: + 9178 01d0 66E7 b .L609 + 9179 .LVL834: + 9180 .L619: + 9181 .LBE309: + 9182 .LBE308: +3476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9183 .loc 1 3476 0 + 9184 01d2 E26A ldr r2, [r4, #44] + 9185 01d4 8023 movs r3, #128 + 9186 01d6 5B04 lsls r3, r3, #17 + 9187 01d8 9A42 cmp r2, r3 + 9188 01da 03D0 beq .L620 +3476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9189 .loc 1 3476 0 is_stmt 0 discriminator 1 + 9190 01dc E36A ldr r3, [r4, #44] + 9191 01de 002B cmp r3, #0 + 9192 01e0 00D0 beq .LCB9783 + 9193 01e2 5DE7 b .L609 @long jump + 9194 .LCB9783: + 9195 .L620: +3480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9196 .loc 1 3480 0 is_stmt 1 + 9197 01e4 2000 movs r0, r4 + 9198 .LVL835: + 9199 01e6 FFF7FEFF bl I2C_ITSlaveSequentialCplt + 9200 .LVL836: + 9201 01ea 59E7 b .L609 + 9202 .L625: +3489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9203 .loc 1 3489 0 + 9204 01ec 2900 movs r1, r5 + 9205 01ee 2000 movs r0, r4 + 9206 01f0 FFF7FEFF bl I2C_ITSlaveCplt + 9207 .LVL837: + 9208 01f4 59E7 b .L621 + 9209 .LVL838: + 9210 .L622: +3396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9211 .loc 1 3396 0 + ARM GAS /tmp/ccpuPECZ.s page 270 + + + 9212 01f6 0220 movs r0, #2 + 9213 .LVL839: + 9214 01f8 5BE7 b .L604 + 9215 .L629: + 9216 01fa C046 .align 2 + 9217 .L628: + 9218 01fc 0000FFFF .word -65536 + 9219 .cfi_endproc + 9220 .LFE85: + 9222 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 9223 .align 1 + 9224 .syntax unified + 9225 .code 16 + 9226 .thumb_func + 9227 .fpu softvfp + 9229 I2C_Slave_ISR_DMA: + 9230 .LFB87: +3596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Process locked */ + 9231 .loc 1 3596 0 + 9232 .cfi_startproc + 9233 @ args = 0, pretend = 0, frame = 0 + 9234 @ frame_needed = 0, uses_anonymous_args = 0 + 9235 .LVL840: + 9236 0000 10B5 push {r4, lr} + 9237 .LCFI65: + 9238 .cfi_def_cfa_offset 8 + 9239 .cfi_offset 4, -8 + 9240 .cfi_offset 14, -4 + 9241 0002 0400 movs r4, r0 +3598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9242 .loc 1 3598 0 + 9243 0004 4023 movs r3, #64 + 9244 0006 C35C ldrb r3, [r0, r3] + 9245 0008 012B cmp r3, #1 + 9246 000a 3AD0 beq .L638 +3598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9247 .loc 1 3598 0 is_stmt 0 discriminator 2 + 9248 000c 4023 movs r3, #64 + 9249 000e 0120 movs r0, #1 + 9250 .LVL841: + 9251 0010 E054 strb r0, [r4, r3] +3600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9252 .loc 1 3600 0 is_stmt 1 discriminator 2 + 9253 0012 CB06 lsls r3, r1, #27 + 9254 0014 20D5 bpl .L632 +3600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9255 .loc 1 3600 0 is_stmt 0 discriminator 1 + 9256 0016 D306 lsls r3, r2, #27 + 9257 0018 1ED5 bpl .L632 +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9258 .loc 1 3606 0 is_stmt 1 + 9259 001a 4123 movs r3, #65 + 9260 001c E35C ldrb r3, [r4, r3] + 9261 001e 212B cmp r3, #33 + 9262 0020 0BD0 beq .L639 +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9263 .loc 1 3606 0 is_stmt 0 discriminator 2 + ARM GAS /tmp/ccpuPECZ.s page 271 + + + 9264 0022 E36B ldr r3, [r4, #60] + 9265 0024 1B68 ldr r3, [r3] + 9266 0026 5B68 ldr r3, [r3, #4] + 9267 0028 5A42 rsbs r2, r3, #0 + 9268 002a 5341 adcs r3, r3, r2 + 9269 .LVL842: + 9270 002c DBB2 uxtb r3, r3 + 9271 .L634: +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9272 .loc 1 3606 0 discriminator 4 + 9273 002e 002B cmp r3, #0 + 9274 0030 0AD0 beq .L635 +3609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9275 .loc 1 3609 0 is_stmt 1 + 9276 0032 2368 ldr r3, [r4] + 9277 0034 1022 movs r2, #16 + 9278 0036 DA61 str r2, [r3, #28] + 9279 0038 1AE0 b .L636 + 9280 .LVL843: + 9281 .L639: +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9282 .loc 1 3606 0 discriminator 1 + 9283 003a A36B ldr r3, [r4, #56] + 9284 003c 1B68 ldr r3, [r3] + 9285 003e 5B68 ldr r3, [r3, #4] + 9286 0040 5A42 rsbs r2, r3, #0 + 9287 0042 5341 adcs r3, r3, r2 + 9288 .LVL844: + 9289 0044 DBB2 uxtb r3, r3 + 9290 0046 F2E7 b .L634 + 9291 .L635: +3615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9292 .loc 1 3615 0 + 9293 0048 2368 ldr r3, [r4] + 9294 004a 1022 movs r2, #16 + 9295 004c DA61 str r2, [r3, #28] +3618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9296 .loc 1 3618 0 + 9297 004e 636C ldr r3, [r4, #68] + 9298 0050 0C3A subs r2, r2, #12 + 9299 0052 1343 orrs r3, r2 + 9300 0054 6364 str r3, [r4, #68] + 9301 0056 0BE0 b .L636 + 9302 .LVL845: + 9303 .L632: +3621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9304 .loc 1 3621 0 + 9305 0058 0B07 lsls r3, r1, #28 + 9306 005a 05D5 bpl .L637 +3621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9307 .loc 1 3621 0 is_stmt 0 discriminator 1 + 9308 005c 1307 lsls r3, r2, #28 + 9309 005e 03D5 bpl .L637 +3624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9310 .loc 1 3624 0 is_stmt 1 + 9311 0060 2368 ldr r3, [r4] + 9312 0062 0822 movs r2, #8 + ARM GAS /tmp/ccpuPECZ.s page 272 + + + 9313 .LVL846: + 9314 0064 DA61 str r2, [r3, #28] + 9315 0066 03E0 b .L636 + 9316 .LVL847: + 9317 .L637: +3626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9318 .loc 1 3626 0 + 9319 0068 8B06 lsls r3, r1, #26 + 9320 006a 01D5 bpl .L636 +3626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9321 .loc 1 3626 0 is_stmt 0 discriminator 1 + 9322 006c 9306 lsls r3, r2, #26 + 9323 006e 04D4 bmi .L640 + 9324 .LVL848: + 9325 .L636: +3633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9326 .loc 1 3633 0 is_stmt 1 + 9327 0070 4023 movs r3, #64 + 9328 0072 0022 movs r2, #0 + 9329 0074 E254 strb r2, [r4, r3] +3635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9330 .loc 1 3635 0 + 9331 0076 0020 movs r0, #0 + 9332 .L631: +3636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9333 .loc 1 3636 0 + 9334 @ sp needed + 9335 .LVL849: + 9336 0078 10BD pop {r4, pc} + 9337 .LVL850: + 9338 .L640: +3629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9339 .loc 1 3629 0 + 9340 007a 2000 movs r0, r4 + 9341 007c FFF7FEFF bl I2C_ITSlaveCplt + 9342 .LVL851: + 9343 0080 F6E7 b .L636 + 9344 .LVL852: + 9345 .L638: +3598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9346 .loc 1 3598 0 + 9347 0082 0220 movs r0, #2 + 9348 .LVL853: + 9349 0084 F8E7 b .L631 + 9350 .cfi_endproc + 9351 .LFE87: + 9353 .section .text.I2C_ITMasterCplt,"ax",%progbits + 9354 .align 1 + 9355 .syntax unified + 9356 .code 16 + 9357 .thumb_func + 9358 .fpu softvfp + 9360 I2C_ITMasterCplt: + 9361 .LFB93: +3954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Clear STOP Flag */ + 9362 .loc 1 3954 0 + 9363 .cfi_startproc + ARM GAS /tmp/ccpuPECZ.s page 273 + + + 9364 @ args = 0, pretend = 0, frame = 0 + 9365 @ frame_needed = 0, uses_anonymous_args = 0 + 9366 .LVL854: + 9367 0000 10B5 push {r4, lr} + 9368 .LCFI66: + 9369 .cfi_def_cfa_offset 8 + 9370 .cfi_offset 4, -8 + 9371 .cfi_offset 14, -4 + 9372 0002 0400 movs r4, r0 +3956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9373 .loc 1 3956 0 + 9374 0004 0368 ldr r3, [r0] + 9375 0006 2022 movs r2, #32 + 9376 0008 DA61 str r2, [r3, #28] +3959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9377 .loc 1 3959 0 + 9378 000a 0268 ldr r2, [r0] + 9379 000c 5368 ldr r3, [r2, #4] + 9380 000e 3448 ldr r0, .L654 + 9381 .LVL855: + 9382 0010 0340 ands r3, r0 + 9383 0012 5360 str r3, [r2, #4] +3962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9384 .loc 1 3962 0 + 9385 0014 0023 movs r3, #0 + 9386 0016 2363 str r3, [r4, #48] +3963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 9387 .loc 1 3963 0 + 9388 0018 6363 str r3, [r4, #52] +3964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9389 .loc 1 3964 0 + 9390 001a 324B ldr r3, .L654+4 + 9391 001c E362 str r3, [r4, #44] +3966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9392 .loc 1 3966 0 + 9393 001e CB06 lsls r3, r1, #27 + 9394 0020 06D5 bpl .L642 +3969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9395 .loc 1 3969 0 + 9396 0022 2368 ldr r3, [r4] + 9397 0024 1022 movs r2, #16 + 9398 0026 DA61 str r2, [r3, #28] +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9399 .loc 1 3972 0 + 9400 0028 636C ldr r3, [r4, #68] + 9401 002a 0C3A subs r2, r2, #12 + 9402 002c 1343 orrs r3, r2 + 9403 002e 6364 str r3, [r4, #68] + 9404 .L642: + 9405 .LVL856: + 9406 .LBB310: + 9407 .LBB311: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9408 .loc 1 4301 0 + 9409 0030 2368 ldr r3, [r4] + 9410 0032 9A69 ldr r2, [r3, #24] + 9411 0034 9207 lsls r2, r2, #30 + ARM GAS /tmp/ccpuPECZ.s page 274 + + + 9412 0036 01D5 bpl .L643 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9413 .loc 1 4303 0 + 9414 0038 0022 movs r2, #0 + 9415 003a 9A62 str r2, [r3, #40] + 9416 .L643: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9417 .loc 1 4307 0 + 9418 003c 2368 ldr r3, [r4] + 9419 003e 9A69 ldr r2, [r3, #24] + 9420 0040 D207 lsls r2, r2, #31 + 9421 0042 03D4 bmi .L644 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9422 .loc 1 4309 0 + 9423 0044 9A69 ldr r2, [r3, #24] + 9424 0046 0121 movs r1, #1 + 9425 .LVL857: + 9426 0048 0A43 orrs r2, r1 + 9427 004a 9A61 str r2, [r3, #24] + 9428 .L644: + 9429 .LVL858: + 9430 .LBE311: + 9431 .LBE310: +3979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9432 .loc 1 3979 0 + 9433 004c 0321 movs r1, #3 + 9434 004e 2000 movs r0, r4 + 9435 0050 FFF7FEFF bl I2C_Disable_IRQ + 9436 .LVL859: +3982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9437 .loc 1 3982 0 + 9438 0054 636C ldr r3, [r4, #68] + 9439 0056 002B cmp r3, #0 + 9440 0058 1BD1 bne .L645 +3982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9441 .loc 1 3982 0 is_stmt 0 discriminator 1 + 9442 005a 4133 adds r3, r3, #65 + 9443 005c E35C ldrb r3, [r4, r3] + 9444 005e 602B cmp r3, #96 + 9445 0060 17D0 beq .L645 +3988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9446 .loc 1 3988 0 is_stmt 1 + 9447 0062 4123 movs r3, #65 + 9448 0064 E35C ldrb r3, [r4, r3] + 9449 0066 212B cmp r3, #33 + 9450 0068 18D0 beq .L651 +4014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9451 .loc 1 4014 0 + 9452 006a 4123 movs r3, #65 + 9453 006c E35C ldrb r3, [r4, r3] + 9454 006e 222B cmp r3, #34 + 9455 0070 13D1 bne .L641 +4016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9456 .loc 1 4016 0 + 9457 0072 1F33 adds r3, r3, #31 + 9458 0074 2022 movs r2, #32 + 9459 0076 E254 strb r2, [r4, r3] + ARM GAS /tmp/ccpuPECZ.s page 275 + + +4018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9460 .loc 1 4018 0 + 9461 0078 0133 adds r3, r3, #1 + 9462 007a E35C ldrb r3, [r4, r3] + 9463 007c 402B cmp r3, #64 + 9464 007e 26D0 beq .L652 +4029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9465 .loc 1 4029 0 + 9466 0080 0023 movs r3, #0 + 9467 0082 4222 movs r2, #66 + 9468 0084 A354 strb r3, [r4, r2] +4032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9469 .loc 1 4032 0 + 9470 0086 023A subs r2, r2, #2 + 9471 0088 A354 strb r3, [r4, r2] +4034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9472 .loc 1 4034 0 + 9473 008a 2000 movs r0, r4 + 9474 008c FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 9475 .LVL860: +4037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9476 .loc 1 4037 0 + 9477 0090 03E0 b .L641 + 9478 .L645: +3985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9479 .loc 1 3985 0 + 9480 0092 616C ldr r1, [r4, #68] + 9481 0094 2000 movs r0, r4 + 9482 0096 FFF7FEFF bl I2C_ITError + 9483 .LVL861: + 9484 .L641: +4037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9485 .loc 1 4037 0 + 9486 @ sp needed + 9487 .LVL862: + 9488 009a 10BD pop {r4, pc} + 9489 .LVL863: + 9490 .L651: +3990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9491 .loc 1 3990 0 + 9492 009c 2033 adds r3, r3, #32 + 9493 009e 2022 movs r2, #32 + 9494 00a0 E254 strb r2, [r4, r3] +3992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9495 .loc 1 3992 0 + 9496 00a2 0133 adds r3, r3, #1 + 9497 00a4 E35C ldrb r3, [r4, r3] + 9498 00a6 402B cmp r3, #64 + 9499 00a8 08D0 beq .L653 +4004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9500 .loc 1 4004 0 + 9501 00aa 0023 movs r3, #0 + 9502 00ac 4222 movs r2, #66 + 9503 00ae A354 strb r3, [r4, r2] +4007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9504 .loc 1 4007 0 + 9505 00b0 023A subs r2, r2, #2 + ARM GAS /tmp/ccpuPECZ.s page 276 + + + 9506 00b2 A354 strb r3, [r4, r2] +4010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9507 .loc 1 4010 0 + 9508 00b4 2000 movs r0, r4 + 9509 00b6 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 9510 .LVL864: + 9511 00ba EEE7 b .L641 + 9512 .L653: +3994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9513 .loc 1 3994 0 + 9514 00bc 0023 movs r3, #0 + 9515 00be 2232 adds r2, r2, #34 + 9516 00c0 A354 strb r3, [r4, r2] +3997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9517 .loc 1 3997 0 + 9518 00c2 023A subs r2, r2, #2 + 9519 00c4 A354 strb r3, [r4, r2] +4000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9520 .loc 1 4000 0 + 9521 00c6 2000 movs r0, r4 + 9522 00c8 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 9523 .LVL865: + 9524 00cc E5E7 b .L641 + 9525 .L652: +4020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9526 .loc 1 4020 0 + 9527 00ce 0023 movs r3, #0 + 9528 00d0 2232 adds r2, r2, #34 + 9529 00d2 A354 strb r3, [r4, r2] +4023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9530 .loc 1 4023 0 + 9531 00d4 023A subs r2, r2, #2 + 9532 00d6 A354 strb r3, [r4, r2] +4025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9533 .loc 1 4025 0 + 9534 00d8 2000 movs r0, r4 + 9535 00da FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 9536 .LVL866: + 9537 00de DCE7 b .L641 + 9538 .L655: + 9539 .align 2 + 9540 .L654: + 9541 00e0 00E800FE .word -33495040 + 9542 00e4 0000FFFF .word -65536 + 9543 .cfi_endproc + 9544 .LFE93: + 9546 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 9547 .align 1 + 9548 .syntax unified + 9549 .code 16 + 9550 .thumb_func + 9551 .fpu softvfp + 9553 I2C_Master_ISR_IT: + 9554 .LFB84: +3273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t devaddress = 0U; + 9555 .loc 1 3273 0 + 9556 .cfi_startproc + ARM GAS /tmp/ccpuPECZ.s page 277 + + + 9557 @ args = 0, pretend = 0, frame = 0 + 9558 @ frame_needed = 0, uses_anonymous_args = 0 + 9559 .LVL867: + 9560 0000 F0B5 push {r4, r5, r6, r7, lr} + 9561 .LCFI67: + 9562 .cfi_def_cfa_offset 20 + 9563 .cfi_offset 4, -20 + 9564 .cfi_offset 5, -16 + 9565 .cfi_offset 6, -12 + 9566 .cfi_offset 7, -8 + 9567 .cfi_offset 14, -4 + 9568 0002 C646 mov lr, r8 + 9569 0004 00B5 push {lr} + 9570 .LCFI68: + 9571 .cfi_def_cfa_offset 24 + 9572 .cfi_offset 8, -24 + 9573 0006 0400 movs r4, r0 + 9574 0008 0D00 movs r5, r1 + 9575 000a 1600 movs r6, r2 + 9576 .LVL868: +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9577 .loc 1 3277 0 + 9578 000c 4023 movs r3, #64 + 9579 000e C35C ldrb r3, [r0, r3] + 9580 0010 012B cmp r3, #1 + 9581 0012 00D1 bne .LCB10164 + 9582 0014 C1E0 b .L671 @long jump + 9583 .LCB10164: +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9584 .loc 1 3277 0 is_stmt 0 discriminator 2 + 9585 0016 4023 movs r3, #64 + 9586 0018 0122 movs r2, #1 + 9587 .LVL869: + 9588 001a C254 strb r2, [r0, r3] +3279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9589 .loc 1 3279 0 is_stmt 1 discriminator 2 + 9590 001c CB06 lsls r3, r1, #27 + 9591 001e 17D5 bpl .L658 +3279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9592 .loc 1 3279 0 is_stmt 0 discriminator 1 + 9593 0020 F306 lsls r3, r6, #27 + 9594 0022 15D5 bpl .L658 +3282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9595 .loc 1 3282 0 is_stmt 1 + 9596 0024 0368 ldr r3, [r0] + 9597 0026 0F32 adds r2, r2, #15 + 9598 0028 DA61 str r2, [r3, #28] +3287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9599 .loc 1 3287 0 + 9600 002a 436C ldr r3, [r0, #68] + 9601 002c 0C3A subs r2, r2, #12 + 9602 002e 1343 orrs r3, r2 + 9603 0030 4364 str r3, [r0, #68] + 9604 .LVL870: + 9605 .LBB312: + 9606 .LBB313: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + ARM GAS /tmp/ccpuPECZ.s page 278 + + + 9607 .loc 1 4301 0 + 9608 0032 0368 ldr r3, [r0] + 9609 0034 9A69 ldr r2, [r3, #24] + 9610 0036 9207 lsls r2, r2, #30 + 9611 0038 01D5 bpl .L659 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9612 .loc 1 4303 0 + 9613 003a 0022 movs r2, #0 + 9614 003c 9A62 str r2, [r3, #40] + 9615 .L659: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9616 .loc 1 4307 0 + 9617 003e 2368 ldr r3, [r4] + 9618 0040 9A69 ldr r2, [r3, #24] + 9619 0042 D207 lsls r2, r2, #31 + 9620 0044 15D4 bmi .L660 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9621 .loc 1 4309 0 + 9622 0046 9A69 ldr r2, [r3, #24] + 9623 0048 0121 movs r1, #1 + 9624 .LVL871: + 9625 004a 0A43 orrs r2, r1 + 9626 004c 9A61 str r2, [r3, #24] + 9627 004e 10E0 b .L660 + 9628 .LVL872: + 9629 .L658: + 9630 .LBE313: + 9631 .LBE312: +3292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9632 .loc 1 3292 0 + 9633 0050 6B07 lsls r3, r5, #29 + 9634 0052 1AD5 bpl .L661 +3292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9635 .loc 1 3292 0 is_stmt 0 discriminator 1 + 9636 0054 7307 lsls r3, r6, #29 + 9637 0056 18D5 bpl .L661 +3295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 9638 .loc 1 3295 0 is_stmt 1 + 9639 0058 2368 ldr r3, [r4] + 9640 005a 5A6A ldr r2, [r3, #36] + 9641 005c 636A ldr r3, [r4, #36] + 9642 005e 591C adds r1, r3, #1 + 9643 .LVL873: + 9644 0060 6162 str r1, [r4, #36] + 9645 0062 1A70 strb r2, [r3] +3296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 9646 .loc 1 3296 0 + 9647 0064 238D ldrh r3, [r4, #40] + 9648 0066 013B subs r3, r3, #1 + 9649 0068 2385 strh r3, [r4, #40] +3297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9650 .loc 1 3297 0 + 9651 006a 638D ldrh r3, [r4, #42] + 9652 006c 013B subs r3, r3, #1 + 9653 006e 9BB2 uxth r3, r3 + 9654 0070 6385 strh r3, [r4, #42] + 9655 .LVL874: + ARM GAS /tmp/ccpuPECZ.s page 279 + + + 9656 .L660: +3373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9657 .loc 1 3373 0 + 9658 0072 AB06 lsls r3, r5, #26 + 9659 0074 02D5 bpl .L670 +3373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9660 .loc 1 3373 0 is_stmt 0 discriminator 1 + 9661 0076 B306 lsls r3, r6, #26 + 9662 0078 00D5 bpl .LCB10251 + 9663 007a 89E0 b .L672 @long jump + 9664 .LCB10251: + 9665 .L670: +3380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9666 .loc 1 3380 0 is_stmt 1 + 9667 007c 4023 movs r3, #64 + 9668 007e 0022 movs r2, #0 + 9669 0080 E254 strb r2, [r4, r3] +3382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9670 .loc 1 3382 0 + 9671 0082 0020 movs r0, #0 + 9672 .L657: +3383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9673 .loc 1 3383 0 + 9674 @ sp needed + 9675 .LVL875: + 9676 .LVL876: + 9677 .LVL877: + 9678 0084 04BC pop {r2} + 9679 0086 9046 mov r8, r2 + 9680 0088 F0BD pop {r4, r5, r6, r7, pc} + 9681 .LVL878: + 9682 .L661: +3299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9683 .loc 1 3299 0 + 9684 008a AB07 lsls r3, r5, #30 + 9685 008c 0FD5 bpl .L662 +3299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9686 .loc 1 3299 0 is_stmt 0 discriminator 1 + 9687 008e B307 lsls r3, r6, #30 + 9688 0090 0DD5 bpl .L662 +3302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferSize--; + 9689 .loc 1 3302 0 is_stmt 1 + 9690 0092 636A ldr r3, [r4, #36] + 9691 0094 5A1C adds r2, r3, #1 + 9692 0096 6262 str r2, [r4, #36] + 9693 0098 2268 ldr r2, [r4] + 9694 009a 1B78 ldrb r3, [r3] + 9695 009c 9362 str r3, [r2, #40] +3303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->XferCount--; + 9696 .loc 1 3303 0 + 9697 009e 238D ldrh r3, [r4, #40] + 9698 00a0 013B subs r3, r3, #1 + 9699 00a2 2385 strh r3, [r4, #40] +3304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9700 .loc 1 3304 0 + 9701 00a4 638D ldrh r3, [r4, #42] + 9702 00a6 013B subs r3, r3, #1 + ARM GAS /tmp/ccpuPECZ.s page 280 + + + 9703 00a8 9BB2 uxth r3, r3 + 9704 00aa 6385 strh r3, [r4, #42] + 9705 00ac E1E7 b .L660 + 9706 .L662: +3306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9707 .loc 1 3306 0 + 9708 00ae 2B06 lsls r3, r5, #24 + 9709 00b0 4CD5 bpl .L663 +3306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9710 .loc 1 3306 0 is_stmt 0 discriminator 1 + 9711 00b2 7306 lsls r3, r6, #25 + 9712 00b4 4AD5 bpl .L663 +3308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9713 .loc 1 3308 0 is_stmt 1 + 9714 00b6 238D ldrh r3, [r4, #40] + 9715 00b8 002B cmp r3, #0 + 9716 00ba 3AD1 bne .L664 +3308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9717 .loc 1 3308 0 is_stmt 0 discriminator 1 + 9718 00bc 638D ldrh r3, [r4, #42] + 9719 00be 9BB2 uxth r3, r3 + 9720 00c0 002B cmp r3, #0 + 9721 00c2 36D0 beq .L664 +3310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9722 .loc 1 3310 0 is_stmt 1 + 9723 00c4 2068 ldr r0, [r4] + 9724 .LVL879: + 9725 00c6 4368 ldr r3, [r0, #4] + 9726 00c8 9B05 lsls r3, r3, #22 + 9727 00ca 9F0D lsrs r7, r3, #22 + 9728 .LVL880: +3312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9729 .loc 1 3312 0 + 9730 00cc 618D ldrh r1, [r4, #42] + 9731 .LVL881: + 9732 00ce 89B2 uxth r1, r1 + 9733 00d0 FF29 cmp r1, #255 + 9734 00d2 0DD9 bls .L665 +3314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 9735 .loc 1 3314 0 + 9736 00d4 FF23 movs r3, #255 + 9737 00d6 2385 strh r3, [r4, #40] + 9738 .LVL882: + 9739 .LBB314: + 9740 .LBB315: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 9741 .loc 1 4713 0 + 9742 00d8 4368 ldr r3, [r0, #4] + 9743 00da 3149 ldr r1, .L673 + 9744 00dc 1940 ands r1, r3 + 9745 00de FF23 movs r3, #255 + 9746 00e0 1B04 lsls r3, r3, #16 + 9747 00e2 1F43 orrs r7, r3 + 9748 .LVL883: + 9749 00e4 8023 movs r3, #128 + 9750 00e6 5B04 lsls r3, r3, #17 + 9751 00e8 3B43 orrs r3, r7 + ARM GAS /tmp/ccpuPECZ.s page 281 + + + 9752 00ea 0B43 orrs r3, r1 + 9753 00ec 4360 str r3, [r0, #4] + 9754 00ee C0E7 b .L660 + 9755 .LVL884: + 9756 .L665: + 9757 .LBE315: + 9758 .LBE314: +3319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 9759 .loc 1 3319 0 + 9760 00f0 638D ldrh r3, [r4, #42] + 9761 00f2 9BB2 uxth r3, r3 + 9762 00f4 2385 strh r3, [r4, #40] +3320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9763 .loc 1 3320 0 + 9764 00f6 E16A ldr r1, [r4, #44] + 9765 00f8 2A4A ldr r2, .L673+4 + 9766 00fa 9142 cmp r1, r2 + 9767 00fc 0CD0 beq .L666 +3322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9768 .loc 1 3322 0 + 9769 00fe DBB2 uxtb r3, r3 + 9770 0100 9846 mov r8, r3 + 9771 0102 E16A ldr r1, [r4, #44] + 9772 .LVL885: + 9773 .LBB316: + 9774 .LBB317: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 9775 .loc 1 4713 0 + 9776 0104 4268 ldr r2, [r0, #4] + 9777 0106 264B ldr r3, .L673 + 9778 0108 1A40 ands r2, r3 + 9779 010a 4346 mov r3, r8 + 9780 010c 1B04 lsls r3, r3, #16 + 9781 010e 3B43 orrs r3, r7 + 9782 0110 0B43 orrs r3, r1 + 9783 0112 1343 orrs r3, r2 + 9784 0114 4360 str r3, [r0, #4] + 9785 0116 ACE7 b .L660 + 9786 .LVL886: + 9787 .L666: + 9788 .LBE317: + 9789 .LBE316: +3326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9790 .loc 1 3326 0 + 9791 0118 DAB2 uxtb r2, r3 + 9792 .LVL887: + 9793 .LBB318: + 9794 .LBB319: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 9795 .loc 1 4713 0 + 9796 011a 4368 ldr r3, [r0, #4] + 9797 011c 2049 ldr r1, .L673 + 9798 011e 1940 ands r1, r3 + 9799 0120 1204 lsls r2, r2, #16 + 9800 .LVL888: + 9801 0122 3B00 movs r3, r7 + 9802 0124 1343 orrs r3, r2 + ARM GAS /tmp/ccpuPECZ.s page 282 + + + 9803 0126 8027 movs r7, #128 + 9804 .LVL889: + 9805 0128 BF04 lsls r7, r7, #18 + 9806 012a 3B43 orrs r3, r7 + 9807 012c 0B43 orrs r3, r1 + 9808 012e 4360 str r3, [r0, #4] + 9809 0130 9FE7 b .L660 + 9810 .LVL890: + 9811 .L664: + 9812 .LBE319: + 9813 .LBE318: +3333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9814 .loc 1 3333 0 + 9815 0132 2368 ldr r3, [r4] + 9816 0134 5B68 ldr r3, [r3, #4] + 9817 0136 9B01 lsls r3, r3, #6 + 9818 0138 03D4 bmi .L667 +3336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9819 .loc 1 3336 0 + 9820 013a 2000 movs r0, r4 + 9821 .LVL891: + 9822 013c FFF7FEFF bl I2C_ITMasterSequentialCplt + 9823 .LVL892: + 9824 0140 97E7 b .L660 + 9825 .LVL893: + 9826 .L667: +3342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9827 .loc 1 3342 0 + 9828 0142 4021 movs r1, #64 + 9829 .LVL894: + 9830 0144 2000 movs r0, r4 + 9831 .LVL895: + 9832 0146 FFF7FEFF bl I2C_ITError + 9833 .LVL896: + 9834 014a 92E7 b .L660 + 9835 .LVL897: + 9836 .L663: +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9837 .loc 1 3346 0 + 9838 014c 6B06 lsls r3, r5, #25 + 9839 014e 00D4 bmi .LCB10478 + 9840 0150 8FE7 b .L660 @long jump + 9841 .LCB10478: +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9842 .loc 1 3346 0 is_stmt 0 discriminator 1 + 9843 0152 7306 lsls r3, r6, #25 + 9844 0154 00D4 bmi .LCB10482 + 9845 0156 8CE7 b .L660 @long jump + 9846 .LCB10482: +3348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9847 .loc 1 3348 0 is_stmt 1 + 9848 0158 638D ldrh r3, [r4, #42] + 9849 015a 9BB2 uxth r3, r3 + 9850 015c 002B cmp r3, #0 + 9851 015e 12D1 bne .L668 +3350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9852 .loc 1 3350 0 + ARM GAS /tmp/ccpuPECZ.s page 283 + + + 9853 0160 2368 ldr r3, [r4] + 9854 0162 5A68 ldr r2, [r3, #4] + 9855 0164 9201 lsls r2, r2, #6 + 9856 0166 00D5 bpl .LCB10492 + 9857 0168 83E7 b .L660 @long jump + 9858 .LCB10492: +3353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9859 .loc 1 3353 0 + 9860 016a E16A ldr r1, [r4, #44] + 9861 .LVL898: + 9862 016c 0D4A ldr r2, .L673+4 + 9863 016e 9142 cmp r1, r2 + 9864 0170 05D1 bne .L669 +3356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9865 .loc 1 3356 0 + 9866 0172 5968 ldr r1, [r3, #4] + 9867 0174 8022 movs r2, #128 + 9868 0176 D201 lsls r2, r2, #7 + 9869 0178 0A43 orrs r2, r1 + 9870 017a 5A60 str r2, [r3, #4] + 9871 017c 79E7 b .L660 + 9872 .L669: +3361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9873 .loc 1 3361 0 + 9874 017e 2000 movs r0, r4 + 9875 .LVL899: + 9876 0180 FFF7FEFF bl I2C_ITMasterSequentialCplt + 9877 .LVL900: + 9878 0184 75E7 b .L660 + 9879 .LVL901: + 9880 .L668: +3369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9881 .loc 1 3369 0 + 9882 0186 4021 movs r1, #64 + 9883 .LVL902: + 9884 0188 2000 movs r0, r4 + 9885 .LVL903: + 9886 018a FFF7FEFF bl I2C_ITError + 9887 .LVL904: + 9888 018e 70E7 b .L660 + 9889 .LVL905: + 9890 .L672: +3376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9891 .loc 1 3376 0 + 9892 0190 2900 movs r1, r5 + 9893 0192 2000 movs r0, r4 + 9894 0194 FFF7FEFF bl I2C_ITMasterCplt + 9895 .LVL906: + 9896 0198 70E7 b .L670 + 9897 .LVL907: + 9898 .L671: +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9899 .loc 1 3277 0 + 9900 019a 0220 movs r0, #2 + 9901 .LVL908: + 9902 019c 72E7 b .L657 + 9903 .L674: + ARM GAS /tmp/ccpuPECZ.s page 284 + + + 9904 019e C046 .align 2 + 9905 .L673: + 9906 01a0 009C00FC .word -67068928 + 9907 01a4 0000FFFF .word -65536 + 9908 .cfi_endproc + 9909 .LFE84: + 9911 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 9912 .align 1 + 9913 .syntax unified + 9914 .code 16 + 9915 .thumb_func + 9916 .fpu softvfp + 9918 I2C_Master_ISR_DMA: + 9919 .LFB86: +3507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint16_t devaddress = 0U; + 9920 .loc 1 3507 0 + 9921 .cfi_startproc + 9922 @ args = 0, pretend = 0, frame = 0 + 9923 @ frame_needed = 0, uses_anonymous_args = 0 + 9924 .LVL909: + 9925 0000 70B5 push {r4, r5, r6, lr} + 9926 .LCFI69: + 9927 .cfi_def_cfa_offset 16 + 9928 .cfi_offset 4, -16 + 9929 .cfi_offset 5, -12 + 9930 .cfi_offset 6, -8 + 9931 .cfi_offset 14, -4 + 9932 0002 0400 movs r4, r0 + 9933 .LVL910: +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9934 .loc 1 3512 0 + 9935 0004 4023 movs r3, #64 + 9936 0006 C35C ldrb r3, [r0, r3] + 9937 0008 012B cmp r3, #1 + 9938 000a 00D1 bne .LCB10573 + 9939 000c 7DE0 b .L686 @long jump + 9940 .LCB10573: +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9941 .loc 1 3512 0 is_stmt 0 discriminator 2 + 9942 000e 4023 movs r3, #64 + 9943 0010 0120 movs r0, #1 + 9944 .LVL911: + 9945 0012 E054 strb r0, [r4, r3] +3514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9946 .loc 1 3514 0 is_stmt 1 discriminator 2 + 9947 0014 CB06 lsls r3, r1, #27 + 9948 0016 27D5 bpl .L677 +3514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9949 .loc 1 3514 0 is_stmt 0 discriminator 1 + 9950 0018 D306 lsls r3, r2, #27 + 9951 001a 25D5 bpl .L677 +3517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9952 .loc 1 3517 0 is_stmt 1 + 9953 001c 2368 ldr r3, [r4] + 9954 001e 1022 movs r2, #16 + 9955 .LVL912: + 9956 0020 DA61 str r2, [r3, #28] + ARM GAS /tmp/ccpuPECZ.s page 285 + + +3520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9957 .loc 1 3520 0 + 9958 0022 636C ldr r3, [r4, #68] + 9959 0024 0C3A subs r2, r2, #12 + 9960 0026 1343 orrs r3, r2 + 9961 0028 6364 str r3, [r4, #68] + 9962 .LVL913: + 9963 .LBB320: + 9964 .LBB321: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) + 9965 .loc 1 4728 0 + 9966 002a 636B ldr r3, [r4, #52] + 9967 002c 384A ldr r2, .L692 + 9968 002e 9342 cmp r3, r2 + 9969 0030 18D0 beq .L687 + 9970 0032 384A ldr r2, .L692+4 + 9971 0034 9342 cmp r3, r2 + 9972 0036 13D0 beq .L689 +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9973 .loc 1 4778 0 + 9974 0038 F421 movs r1, #244 + 9975 .LVL914: + 9976 .L678: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 9977 .loc 1 4785 0 + 9978 003a 2268 ldr r2, [r4] + 9979 003c 1368 ldr r3, [r2] + 9980 003e 0B43 orrs r3, r1 + 9981 0040 1360 str r3, [r2] + 9982 .LVL915: + 9983 .LBE321: + 9984 .LBE320: + 9985 .LBB323: + 9986 .LBB324: +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9987 .loc 1 4301 0 + 9988 0042 2368 ldr r3, [r4] + 9989 0044 9A69 ldr r2, [r3, #24] + 9990 0046 9207 lsls r2, r2, #30 + 9991 0048 01D5 bpl .L679 +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 9992 .loc 1 4303 0 + 9993 004a 0022 movs r2, #0 + 9994 004c 9A62 str r2, [r3, #40] + 9995 .L679: +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 9996 .loc 1 4307 0 + 9997 004e 2368 ldr r3, [r4] + 9998 0050 9A69 ldr r2, [r3, #24] + 9999 0052 D207 lsls r2, r2, #31 + 10000 0054 50D4 bmi .L680 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10001 .loc 1 4309 0 + 10002 0056 9A69 ldr r2, [r3, #24] + 10003 0058 0121 movs r1, #1 + 10004 005a 0A43 orrs r2, r1 + 10005 005c 9A61 str r2, [r3, #24] + ARM GAS /tmp/ccpuPECZ.s page 286 + + + 10006 005e 4BE0 b .L680 + 10007 .LVL916: + 10008 .L689: + 10009 .LBE324: + 10010 .LBE323: + 10011 .LBB325: + 10012 .LBB322: +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10013 .loc 1 4752 0 + 10014 0060 6021 movs r1, #96 + 10015 .LVL917: + 10016 0062 EAE7 b .L678 + 10017 .LVL918: + 10018 .L687: + 10019 0064 6021 movs r1, #96 + 10020 .LVL919: + 10021 0066 E8E7 b .L678 + 10022 .LVL920: + 10023 .L677: + 10024 .LBE322: + 10025 .LBE325: +3530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10026 .loc 1 3530 0 + 10027 0068 0B06 lsls r3, r1, #24 + 10028 006a 41D5 bpl .L681 +3530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10029 .loc 1 3530 0 is_stmt 0 discriminator 1 + 10030 006c 5306 lsls r3, r2, #25 + 10031 006e 3FD5 bpl .L681 +3533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10032 .loc 1 3533 0 is_stmt 1 + 10033 0070 2268 ldr r2, [r4] + 10034 .LVL921: + 10035 0072 1368 ldr r3, [r2] + 10036 0074 4021 movs r1, #64 + 10037 .LVL922: + 10038 0076 8B43 bics r3, r1 + 10039 0078 1360 str r3, [r2] +3535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10040 .loc 1 3535 0 + 10041 007a 638D ldrh r3, [r4, #42] + 10042 007c 9BB2 uxth r3, r3 + 10043 007e 002B cmp r3, #0 + 10044 0080 31D0 beq .L682 +3538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10045 .loc 1 3538 0 + 10046 0082 2668 ldr r6, [r4] + 10047 0084 7268 ldr r2, [r6, #4] + 10048 0086 9205 lsls r2, r2, #22 + 10049 0088 950D lsrs r5, r2, #22 + 10050 .LVL923: +3541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10051 .loc 1 3541 0 + 10052 008a 638D ldrh r3, [r4, #42] + 10053 008c 9BB2 uxth r3, r3 + 10054 008e FF2B cmp r3, #255 + 10055 0090 1DD9 bls .L683 + ARM GAS /tmp/ccpuPECZ.s page 287 + + +3543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 10056 .loc 1 3543 0 + 10057 0092 FF23 movs r3, #255 + 10058 0094 2385 strh r3, [r4, #40] + 10059 .LVL924: +3544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10060 .loc 1 3544 0 + 10061 0096 8020 movs r0, #128 + 10062 0098 4004 lsls r0, r0, #17 + 10063 .LVL925: + 10064 .L684: +3553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10065 .loc 1 3553 0 + 10066 009a 228D ldrh r2, [r4, #40] + 10067 009c D2B2 uxtb r2, r2 + 10068 .LVL926: + 10069 .LBB326: + 10070 .LBB327: +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ + 10071 .loc 1 4713 0 + 10072 009e 7368 ldr r3, [r6, #4] + 10073 00a0 1D49 ldr r1, .L692+8 + 10074 00a2 0B40 ands r3, r1 + 10075 00a4 1204 lsls r2, r2, #16 + 10076 .LVL927: + 10077 00a6 2A43 orrs r2, r5 + 10078 00a8 0243 orrs r2, r0 + 10079 00aa 1343 orrs r3, r2 + 10080 00ac 7360 str r3, [r6, #4] + 10081 .LVL928: + 10082 .LBE327: + 10083 .LBE326: +3556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10084 .loc 1 3556 0 + 10085 00ae 638D ldrh r3, [r4, #42] + 10086 00b0 228D ldrh r2, [r4, #40] + 10087 00b2 9B1A subs r3, r3, r2 + 10088 00b4 9BB2 uxth r3, r3 + 10089 00b6 6385 strh r3, [r4, #42] +3559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10090 .loc 1 3559 0 + 10091 00b8 4123 movs r3, #65 + 10092 00ba E35C ldrb r3, [r4, r3] + 10093 00bc 222B cmp r3, #34 + 10094 00be 0BD0 beq .L690 +3565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10095 .loc 1 3565 0 + 10096 00c0 2268 ldr r2, [r4] + 10097 00c2 1168 ldr r1, [r2] + 10098 00c4 8023 movs r3, #128 + 10099 00c6 DB01 lsls r3, r3, #7 + 10100 00c8 0B43 orrs r3, r1 + 10101 00ca 1360 str r3, [r2] + 10102 00cc 14E0 b .L680 + 10103 .LVL929: + 10104 .L683: +3548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + ARM GAS /tmp/ccpuPECZ.s page 288 + + + 10105 .loc 1 3548 0 + 10106 00ce 638D ldrh r3, [r4, #42] + 10107 00d0 2385 strh r3, [r4, #40] + 10108 .LVL930: +3549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10109 .loc 1 3549 0 + 10110 00d2 8020 movs r0, #128 + 10111 00d4 8004 lsls r0, r0, #18 + 10112 00d6 E0E7 b .L684 + 10113 .LVL931: + 10114 .L690: +3561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10115 .loc 1 3561 0 + 10116 00d8 2268 ldr r2, [r4] + 10117 00da 1168 ldr r1, [r2] + 10118 00dc 8023 movs r3, #128 + 10119 00de 1B02 lsls r3, r3, #8 + 10120 00e0 0B43 orrs r3, r1 + 10121 00e2 1360 str r3, [r2] + 10122 00e4 08E0 b .L680 + 10123 .LVL932: + 10124 .L682: +3572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10125 .loc 1 3572 0 + 10126 00e6 4021 movs r1, #64 + 10127 00e8 2000 movs r0, r4 + 10128 00ea FFF7FEFF bl I2C_ITError + 10129 .LVL933: + 10130 00ee 03E0 b .L680 + 10131 .LVL934: + 10132 .L681: +3575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10133 .loc 1 3575 0 + 10134 00f0 8B06 lsls r3, r1, #26 + 10135 00f2 01D5 bpl .L680 +3575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10136 .loc 1 3575 0 is_stmt 0 discriminator 1 + 10137 00f4 9306 lsls r3, r2, #26 + 10138 00f6 04D4 bmi .L691 + 10139 .LVL935: + 10140 .L680: +3582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10141 .loc 1 3582 0 is_stmt 1 + 10142 00f8 4023 movs r3, #64 + 10143 00fa 0022 movs r2, #0 + 10144 00fc E254 strb r2, [r4, r3] +3584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10145 .loc 1 3584 0 + 10146 00fe 0020 movs r0, #0 + 10147 .L676: +3585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10148 .loc 1 3585 0 + 10149 @ sp needed + 10150 .LVL936: + 10151 0100 70BD pop {r4, r5, r6, pc} + 10152 .LVL937: + 10153 .L691: + ARM GAS /tmp/ccpuPECZ.s page 289 + + +3578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10154 .loc 1 3578 0 + 10155 0102 2000 movs r0, r4 + 10156 0104 FFF7FEFF bl I2C_ITMasterCplt + 10157 .LVL938: + 10158 0108 F6E7 b .L680 + 10159 .LVL939: + 10160 .L686: +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10161 .loc 1 3512 0 + 10162 010a 0220 movs r0, #2 + 10163 .LVL940: + 10164 010c F8E7 b .L676 + 10165 .L693: + 10166 010e C046 .align 2 + 10167 .L692: + 10168 0110 00000000 .word I2C_Master_ISR_DMA + 10169 0114 00000000 .word I2C_Slave_ISR_DMA + 10170 0118 009C00FC .word -67068928 + 10171 .cfi_endproc + 10172 .LFE86: + 10174 .section .text.I2C_DMAError,"ax",%progbits + 10175 .align 1 + 10176 .syntax unified + 10177 .code 16 + 10178 .thumb_func + 10179 .fpu softvfp + 10181 I2C_DMAError: + 10182 .LFB102: +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 10183 .loc 1 4433 0 + 10184 .cfi_startproc + 10185 @ args = 0, pretend = 0, frame = 0 + 10186 @ frame_needed = 0, uses_anonymous_args = 0 + 10187 .LVL941: + 10188 0000 10B5 push {r4, lr} + 10189 .LCFI70: + 10190 .cfi_def_cfa_offset 8 + 10191 .cfi_offset 4, -8 + 10192 .cfi_offset 14, -4 +4434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10193 .loc 1 4434 0 + 10194 0002 806A ldr r0, [r0, #40] + 10195 .LVL942: +4437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10196 .loc 1 4437 0 + 10197 0004 0268 ldr r2, [r0] + 10198 0006 5168 ldr r1, [r2, #4] + 10199 0008 8023 movs r3, #128 + 10200 000a 1B02 lsls r3, r3, #8 + 10201 000c 0B43 orrs r3, r1 + 10202 000e 5360 str r3, [r2, #4] +4440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10203 .loc 1 4440 0 + 10204 0010 1021 movs r1, #16 + 10205 0012 FFF7FEFF bl I2C_ITError + 10206 .LVL943: + ARM GAS /tmp/ccpuPECZ.s page 290 + + +4441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10207 .loc 1 4441 0 + 10208 @ sp needed + 10209 0016 10BD pop {r4, pc} + 10210 .cfi_endproc + 10211 .LFE102: + 10213 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 10214 .align 1 + 10215 .global HAL_I2C_ER_IRQHandler + 10216 .syntax unified + 10217 .code 16 + 10218 .thumb_func + 10219 .fpu softvfp + 10221 HAL_I2C_ER_IRQHandler: + 10222 .LFB70: +2998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 10223 .loc 1 2998 0 + 10224 .cfi_startproc + 10225 @ args = 0, pretend = 0, frame = 0 + 10226 @ frame_needed = 0, uses_anonymous_args = 0 + 10227 .LVL944: + 10228 0000 70B5 push {r4, r5, r6, lr} + 10229 .LCFI71: + 10230 .cfi_def_cfa_offset 16 + 10231 .cfi_offset 4, -16 + 10232 .cfi_offset 5, -12 + 10233 .cfi_offset 6, -8 + 10234 .cfi_offset 14, -4 +2999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10235 .loc 1 2999 0 + 10236 0002 0268 ldr r2, [r0] + 10237 0004 9369 ldr r3, [r2, #24] + 10238 .LVL945: +3000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10239 .loc 1 3000 0 + 10240 0006 1168 ldr r1, [r2] + 10241 .LVL946: +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10242 .loc 1 3003 0 + 10243 0008 DC05 lsls r4, r3, #23 + 10244 000a 08D5 bpl .L696 +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10245 .loc 1 3003 0 is_stmt 0 discriminator 1 + 10246 000c 0C06 lsls r4, r1, #24 + 10247 000e 06D5 bpl .L696 +3005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10248 .loc 1 3005 0 is_stmt 1 + 10249 0010 446C ldr r4, [r0, #68] + 10250 0012 0125 movs r5, #1 + 10251 0014 2C43 orrs r4, r5 + 10252 0016 4464 str r4, [r0, #68] +3008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10253 .loc 1 3008 0 + 10254 0018 8024 movs r4, #128 + 10255 001a 6400 lsls r4, r4, #1 + 10256 001c D461 str r4, [r2, #28] + 10257 .L696: + ARM GAS /tmp/ccpuPECZ.s page 291 + + +3012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10258 .loc 1 3012 0 + 10259 001e 5A05 lsls r2, r3, #21 + 10260 0020 09D5 bpl .L697 +3012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10261 .loc 1 3012 0 is_stmt 0 discriminator 1 + 10262 0022 0A06 lsls r2, r1, #24 + 10263 0024 07D5 bpl .L697 +3014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10264 .loc 1 3014 0 is_stmt 1 + 10265 0026 426C ldr r2, [r0, #68] + 10266 0028 0824 movs r4, #8 + 10267 002a 2243 orrs r2, r4 + 10268 002c 4264 str r2, [r0, #68] +3017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10269 .loc 1 3017 0 + 10270 002e 0268 ldr r2, [r0] + 10271 0030 8024 movs r4, #128 + 10272 0032 E400 lsls r4, r4, #3 + 10273 0034 D461 str r4, [r2, #28] + 10274 .L697: +3021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10275 .loc 1 3021 0 + 10276 0036 9B05 lsls r3, r3, #22 + 10277 0038 09D5 bpl .L698 + 10278 .LVL947: +3021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10279 .loc 1 3021 0 is_stmt 0 discriminator 1 + 10280 003a 0B06 lsls r3, r1, #24 + 10281 003c 07D5 bpl .L698 +3023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10282 .loc 1 3023 0 is_stmt 1 + 10283 003e 436C ldr r3, [r0, #68] + 10284 0040 0222 movs r2, #2 + 10285 0042 1343 orrs r3, r2 + 10286 0044 4364 str r3, [r0, #68] +3026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10287 .loc 1 3026 0 + 10288 0046 0368 ldr r3, [r0] + 10289 0048 FF32 adds r2, r2, #255 + 10290 004a FF32 adds r2, r2, #255 + 10291 004c DA61 str r2, [r3, #28] + 10292 .L698: +3030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10293 .loc 1 3030 0 + 10294 004e 436C ldr r3, [r0, #68] + 10295 0050 0B22 movs r2, #11 + 10296 0052 1A42 tst r2, r3 + 10297 0054 00D1 bne .L700 + 10298 .LVL948: + 10299 .L695: +3034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10300 .loc 1 3034 0 + 10301 @ sp needed + 10302 0056 70BD pop {r4, r5, r6, pc} + 10303 .LVL949: + 10304 .L700: + ARM GAS /tmp/ccpuPECZ.s page 292 + + +3032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10305 .loc 1 3032 0 + 10306 0058 416C ldr r1, [r0, #68] + 10307 .LVL950: + 10308 005a FFF7FEFF bl I2C_ITError + 10309 .LVL951: +3034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10310 .loc 1 3034 0 + 10311 005e FAE7 b .L695 + 10312 .cfi_endproc + 10313 .LFE70: + 10315 .section .text.I2C_DMAAbort,"ax",%progbits + 10316 .align 1 + 10317 .syntax unified + 10318 .code 16 + 10319 .thumb_func + 10320 .fpu softvfp + 10322 I2C_DMAAbort: + 10323 .LFB103: +4450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 10324 .loc 1 4450 0 + 10325 .cfi_startproc + 10326 @ args = 0, pretend = 0, frame = 0 + 10327 @ frame_needed = 0, uses_anonymous_args = 0 + 10328 .LVL952: + 10329 0000 10B5 push {r4, lr} + 10330 .LCFI72: + 10331 .cfi_def_cfa_offset 8 + 10332 .cfi_offset 4, -8 + 10333 .cfi_offset 14, -4 +4451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10334 .loc 1 4451 0 + 10335 0002 806A ldr r0, [r0, #40] + 10336 .LVL953: +4454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10337 .loc 1 4454 0 + 10338 0004 0268 ldr r2, [r0] + 10339 0006 5168 ldr r1, [r2, #4] + 10340 0008 8023 movs r3, #128 + 10341 000a 1B02 lsls r3, r3, #8 + 10342 000c 0B43 orrs r3, r1 + 10343 000e 5360 str r3, [r2, #4] +4457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 10344 .loc 1 4457 0 + 10345 0010 826B ldr r2, [r0, #56] + 10346 0012 0023 movs r3, #0 + 10347 0014 9363 str r3, [r2, #56] +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10348 .loc 1 4458 0 + 10349 0016 C26B ldr r2, [r0, #60] + 10350 0018 9363 str r3, [r2, #56] +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** { + 10351 .loc 1 4461 0 + 10352 001a 4133 adds r3, r3, #65 + 10353 001c C35C ldrb r3, [r0, r3] + 10354 001e 602B cmp r3, #96 + 10355 0020 02D0 beq .L704 + ARM GAS /tmp/ccpuPECZ.s page 293 + + +4471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10356 .loc 1 4471 0 + 10357 0022 FFF7FEFF bl HAL_I2C_ErrorCallback + 10358 .LVL954: + 10359 .L701: +4473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10360 .loc 1 4473 0 + 10361 @ sp needed + 10362 0026 10BD pop {r4, pc} + 10363 .LVL955: + 10364 .L704: +4463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10365 .loc 1 4463 0 + 10366 0028 1F3B subs r3, r3, #31 + 10367 002a 2022 movs r2, #32 + 10368 002c C254 strb r2, [r0, r3] +4466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10369 .loc 1 4466 0 + 10370 002e FFF7FEFF bl HAL_I2C_AbortCpltCallback + 10371 .LVL956: + 10372 0032 F8E7 b .L701 + 10373 .cfi_endproc + 10374 .LFE103: + 10376 .section .text.HAL_I2C_GetState,"ax",%progbits + 10377 .align 1 + 10378 .global HAL_I2C_GetState + 10379 .syntax unified + 10380 .code 16 + 10381 .thumb_func + 10382 .fpu softvfp + 10384 HAL_I2C_GetState: + 10385 .LFB81: +3225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** /* Return I2C handle state */ + 10386 .loc 1 3225 0 + 10387 .cfi_startproc + 10388 @ args = 0, pretend = 0, frame = 0 + 10389 @ frame_needed = 0, uses_anonymous_args = 0 + 10390 @ link register save eliminated. + 10391 .LVL957: +3227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10392 .loc 1 3227 0 + 10393 0000 4123 movs r3, #65 + 10394 0002 C05C ldrb r0, [r0, r3] + 10395 .LVL958: + 10396 0004 C0B2 uxtb r0, r0 +3228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10397 .loc 1 3228 0 + 10398 @ sp needed + 10399 0006 7047 bx lr + 10400 .cfi_endproc + 10401 .LFE81: + 10403 .section .text.HAL_I2C_GetMode,"ax",%progbits + 10404 .align 1 + 10405 .global HAL_I2C_GetMode + 10406 .syntax unified + 10407 .code 16 + 10408 .thumb_func + ARM GAS /tmp/ccpuPECZ.s page 294 + + + 10409 .fpu softvfp + 10411 HAL_I2C_GetMode: + 10412 .LFB82: +3237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return hi2c->Mode; + 10413 .loc 1 3237 0 + 10414 .cfi_startproc + 10415 @ args = 0, pretend = 0, frame = 0 + 10416 @ frame_needed = 0, uses_anonymous_args = 0 + 10417 @ link register save eliminated. + 10418 .LVL959: +3238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10419 .loc 1 3238 0 + 10420 0000 4223 movs r3, #66 + 10421 0002 C05C ldrb r0, [r0, r3] + 10422 .LVL960: + 10423 0004 C0B2 uxtb r0, r0 +3239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10424 .loc 1 3239 0 + 10425 @ sp needed + 10426 0006 7047 bx lr + 10427 .cfi_endproc + 10428 .LFE82: + 10430 .section .text.HAL_I2C_GetError,"ax",%progbits + 10431 .align 1 + 10432 .global HAL_I2C_GetError + 10433 .syntax unified + 10434 .code 16 + 10435 .thumb_func + 10436 .fpu softvfp + 10438 HAL_I2C_GetError: + 10439 .LFB83: +3248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** return hi2c->ErrorCode; + 10440 .loc 1 3248 0 + 10441 .cfi_startproc + 10442 @ args = 0, pretend = 0, frame = 0 + 10443 @ frame_needed = 0, uses_anonymous_args = 0 + 10444 @ link register save eliminated. + 10445 .LVL961: +3249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** } + 10446 .loc 1 3249 0 + 10447 0000 406C ldr r0, [r0, #68] + 10448 .LVL962: +3250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c **** + 10449 .loc 1 3250 0 + 10450 @ sp needed + 10451 0002 7047 bx lr + 10452 .cfi_endproc + 10453 .LFE83: + 10455 .section .rodata.HAL_I2C_Mem_Read.str1.4,"aMS",%progbits,1 + 10456 .align 2 + 10457 .LC38: + 10458 0000 42616420 .ascii "Bad pData or Size=0\015\012\000" + 10458 70446174 + 10458 61206F72 + 10458 2053697A + 10458 653D300D + 10459 0016 0000 .space 2 + ARM GAS /tmp/ccpuPECZ.s page 295 + + + 10460 .LC40: + 10461 0018 54696D65 .ascii "Timeout\015\012\000" + 10461 6F75740D + 10461 0A00 + 10462 0022 0000 .space 2 + 10463 .LC42: + 10464 0024 4572726F .ascii "Error in memory read - %d\015\012\000" + 10464 7220696E + 10464 206D656D + 10464 6F727920 + 10464 72656164 + 10465 .LC44: + 10466 0040 77616974 .ascii "waiting for flag timeout1\015\012\000" + 10466 696E6720 + 10466 666F7220 + 10466 666C6167 + 10466 2074696D + 10467 .LC46: + 10468 005c 77616974 .ascii "waiting for flag timeout2\015\012\000" + 10468 696E6720 + 10468 666F7220 + 10468 666C6167 + 10468 2074696D + 10469 .LC48: + 10470 0078 77616974 .ascii "waiting for stop error %d\015\012\000" + 10470 696E6720 + 10470 666F7220 + 10470 73746F70 + 10470 20657272 + 10471 .LC50: + 10472 0094 62757379 .ascii "busy!!\015\012\000" + 10472 21210D0A + 10472 00 + 10473 .section .rodata.I2C_RequestMemoryRead.str1.4,"aMS",%progbits,1 + 10474 .align 2 + 10475 .LC4: + 10476 0000 4932435F .ascii "I2C_RequestMemoryRead error %d\015\012\000" + 10476 52657175 + 10476 6573744D + 10476 656D6F72 + 10476 79526561 + 10477 0021 000000 .space 3 + 10478 .LC6: + 10479 0024 4932435F .ascii "I2C_RequestMemoryRead error2 %d\015\012\000" + 10479 52657175 + 10479 6573744D + 10479 656D6F72 + 10479 79526561 + 10480 0046 0000 .space 2 + 10481 .LC8: + 10482 0048 4932435F .ascii "I2C_RequestMemoryRead TIMEOUT\015\012\000" + 10482 52657175 + 10482 6573744D + 10482 656D6F72 + 10482 79526561 + 10483 .section .rodata.I2C_WaitOnTXISFlagUntilTimeout.str1.4,"aMS",%progbits,1 + 10484 .align 2 + ARM GAS /tmp/ccpuPECZ.s page 296 + + + 10485 .LC0: + 10486 0000 4932435F .ascii "I2C_WaitOnTXISFlagUntilTimeout ->I2C_IsAcknowledgeF" + 10486 57616974 + 10486 4F6E5458 + 10486 4953466C + 10486 6167556E + 10487 0033 61696C65 .ascii "ailed error\015\012\000" + 10487 64206572 + 10487 726F720D + 10487 0A00 + 10488 0041 000000 .space 3 + 10489 .LC2: + 10490 0044 4932435F .ascii "I2C_WaitOnTXISFlagUntilTimeout timeout\015\012\000" + 10490 57616974 + 10490 4F6E5458 + 10490 4953466C + 10490 6167556E + 10491 .text + 10492 .Letext0: + 10493 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 10494 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 10495 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 10496 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 10497 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 10498 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 10499 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 10500 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 10501 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 10502 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 10503 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 10504 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h" + 10505 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 10506 .file 15 "Inc/vcom.h" + ARM GAS /tmp/ccpuPECZ.s page 297 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_i2c.c + /tmp/ccpuPECZ.s:16 .text.I2C_DMASlaveTransmitCplt:0000000000000000 $t + /tmp/ccpuPECZ.s:22 .text.I2C_DMASlaveTransmitCplt:0000000000000000 I2C_DMASlaveTransmitCplt + /tmp/ccpuPECZ.s:38 .text.I2C_DMASlaveReceiveCplt:0000000000000000 $t + /tmp/ccpuPECZ.s:44 .text.I2C_DMASlaveReceiveCplt:0000000000000000 I2C_DMASlaveReceiveCplt + /tmp/ccpuPECZ.s:59 .text.I2C_Disable_IRQ:0000000000000000 $t + /tmp/ccpuPECZ.s:65 .text.I2C_Disable_IRQ:0000000000000000 I2C_Disable_IRQ + /tmp/ccpuPECZ.s:186 .text.I2C_IsAcknowledgeFailed:0000000000000000 $t + /tmp/ccpuPECZ.s:192 .text.I2C_IsAcknowledgeFailed:0000000000000000 I2C_IsAcknowledgeFailed + /tmp/ccpuPECZ.s:321 .text.I2C_IsAcknowledgeFailed:000000000000008c $d + /tmp/ccpuPECZ.s:326 .text.I2C_WaitOnFlagUntilTimeout:0000000000000000 $t + /tmp/ccpuPECZ.s:332 .text.I2C_WaitOnFlagUntilTimeout:0000000000000000 I2C_WaitOnFlagUntilTimeout + /tmp/ccpuPECZ.s:405 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Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_i2c_ex.lst b/build/stm32l0xx_hal_i2c_ex.lst new file mode 100644 index 0000000..de8943e --- /dev/null +++ b/build/stm32l0xx_hal_i2c_ex.lst @@ -0,0 +1,868 @@ +ARM GAS /tmp/ccHVO7A6.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_i2c_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits + 16 .align 1 + 17 .global HAL_I2CEx_ConfigAnalogFilter + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_I2CEx_ConfigAnalogFilter: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @file stm32l0xx_hal_i2c_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + Extended features functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** @verbatim + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ============================================================================== + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features ##### + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ============================================================================== + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32L0xx + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** devices contains the following additional features + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Disable or enable wakeup from Stop mode(s) + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ##### How to use this driver ##### + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ============================================================================== + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** [..] This driver provides functions to configure Noise Filter and Wake Up Feature + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableWakeUp() + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableWakeUp() + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions : + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus() + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus() + ARM GAS /tmp/ccHVO7A6.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** @endverbatim + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ****************************************************************************** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @attention + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * are permitted provided that the following conditions are met: + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * this list of conditions and the following disclaimer. + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * this list of conditions and the following disclaimer in the documentation + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * and/or other materials provided with the distribution. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * may be used to endorse or promote products derived from this software + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * without specific prior written permission. + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ****************************************************************************** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** #include "stm32l0xx_hal.h" + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @{ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @{ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @{ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + ARM GAS /tmp/ccHVO7A6.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Extended features functions + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** @verbatim + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** =============================================================================== + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** ##### Extended features functions ##### + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** =============================================================================== + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** @endverbatim + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @{ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval HAL status + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 26 .loc 1 114 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F0B5 push {r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 20 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + 36 .cfi_offset 6, -12 + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameters */ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 39 .loc 1 119 0 + 40 0002 4123 movs r3, #65 + 41 0004 C35C ldrb r3, [r0, r3] + 42 0006 202B cmp r3, #32 + 43 0008 20D1 bne .L3 + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Locked */ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 44 .loc 1 122 0 + 45 000a 2033 adds r3, r3, #32 + 46 000c C35C ldrb r3, [r0, r3] + 47 000e 012B cmp r3, #1 + 48 0010 1ED0 beq .L4 + 49 .loc 1 122 0 is_stmt 0 discriminator 2 + 50 0012 4024 movs r4, #64 + ARM GAS /tmp/ccHVO7A6.s page 4 + + + 51 0014 0122 movs r2, #1 + 52 0016 0255 strb r2, [r0, r4] + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 53 .loc 1 124 0 is_stmt 1 discriminator 2 + 54 0018 4125 movs r5, #65 + 55 001a 2423 movs r3, #36 + 56 001c 4355 strb r3, [r0, r5] + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 57 .loc 1 127 0 discriminator 2 + 58 001e 0668 ldr r6, [r0] + 59 0020 3368 ldr r3, [r6] + 60 0022 9343 bics r3, r2 + 61 0024 3360 str r3, [r6] + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 62 .loc 1 130 0 discriminator 2 + 63 0026 0668 ldr r6, [r0] + 64 0028 3368 ldr r3, [r6] + 65 002a 0A4F ldr r7, .L5 + 66 002c 3B40 ands r3, r7 + 67 002e 3360 str r3, [r6] + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 68 .loc 1 133 0 discriminator 2 + 69 0030 0668 ldr r6, [r0] + 70 0032 3368 ldr r3, [r6] + 71 0034 1943 orrs r1, r3 + 72 .LVL1: + 73 0036 3160 str r1, [r6] + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 74 .loc 1 135 0 discriminator 2 + 75 0038 0168 ldr r1, [r0] + 76 003a 0B68 ldr r3, [r1] + 77 003c 1343 orrs r3, r2 + 78 003e 0B60 str r3, [r1] + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 79 .loc 1 137 0 discriminator 2 + 80 0040 2023 movs r3, #32 + 81 0042 4355 strb r3, [r0, r5] + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 82 .loc 1 140 0 discriminator 2 + 83 0044 0023 movs r3, #0 + 84 0046 0355 strb r3, [r0, r4] + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_OK; + 85 .loc 1 142 0 discriminator 2 + 86 0048 0020 movs r0, #0 + 87 .LVL2: + ARM GAS /tmp/ccHVO7A6.s page 5 + + + 88 004a 00E0 b .L2 + 89 .LVL3: + 90 .L3: + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** else + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_BUSY; + 91 .loc 1 146 0 + 92 004c 0220 movs r0, #2 + 93 .LVL4: + 94 .L2: + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 95 .loc 1 148 0 + 96 @ sp needed + 97 004e F0BD pop {r4, r5, r6, r7, pc} + 98 .LVL5: + 99 .L4: + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 100 .loc 1 122 0 + 101 0050 0220 movs r0, #2 + 102 .LVL6: + 103 0052 FCE7 b .L2 + 104 .L6: + 105 .align 2 + 106 .L5: + 107 0054 FFEFFFFF .word -4097 + 108 .cfi_endproc + 109 .LFE39: + 111 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 112 .align 1 + 113 .global HAL_I2CEx_ConfigDigitalFilter + 114 .syntax unified + 115 .code 16 + 116 .thumb_func + 117 .fpu softvfp + 119 HAL_I2CEx_ConfigDigitalFilter: + 120 .LFB40: + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval HAL status + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 121 .loc 1 158 0 + 122 .cfi_startproc + 123 @ args = 0, pretend = 0, frame = 0 + 124 @ frame_needed = 0, uses_anonymous_args = 0 + 125 .LVL7: + 126 0000 F0B5 push {r4, r5, r6, r7, lr} + 127 .LCFI1: + 128 .cfi_def_cfa_offset 20 + 129 .cfi_offset 4, -20 + ARM GAS /tmp/ccHVO7A6.s page 6 + + + 130 .cfi_offset 5, -16 + 131 .cfi_offset 6, -12 + 132 .cfi_offset 7, -8 + 133 .cfi_offset 14, -4 + 134 .LVL8: + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** uint32_t tmpreg = 0U; + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameters */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 135 .loc 1 165 0 + 136 0002 4123 movs r3, #65 + 137 0004 C35C ldrb r3, [r0, r3] + 138 0006 202B cmp r3, #32 + 139 0008 1ED1 bne .L9 + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Locked */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 140 .loc 1 168 0 + 141 000a 2033 adds r3, r3, #32 + 142 000c C35C ldrb r3, [r0, r3] + 143 000e 012B cmp r3, #1 + 144 0010 1CD0 beq .L10 + 145 .loc 1 168 0 is_stmt 0 discriminator 2 + 146 0012 4024 movs r4, #64 + 147 0014 0122 movs r2, #1 + 148 0016 0255 strb r2, [r0, r4] + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 149 .loc 1 170 0 is_stmt 1 discriminator 2 + 150 0018 4125 movs r5, #65 + 151 001a 2423 movs r3, #36 + 152 001c 4355 strb r3, [r0, r5] + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 153 .loc 1 173 0 discriminator 2 + 154 001e 0668 ldr r6, [r0] + 155 0020 3368 ldr r3, [r6] + 156 0022 9343 bics r3, r2 + 157 0024 3360 str r3, [r6] + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Get the old register value */ + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 158 .loc 1 176 0 discriminator 2 + 159 0026 0668 ldr r6, [r0] + 160 0028 3368 ldr r3, [r6] + 161 .LVL9: + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 162 .loc 1 179 0 discriminator 2 + 163 002a 094F ldr r7, .L11 + 164 002c 3B40 ands r3, r7 + 165 .LVL10: + ARM GAS /tmp/ccHVO7A6.s page 7 + + + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 166 .loc 1 182 0 discriminator 2 + 167 002e 0902 lsls r1, r1, #8 + 168 .LVL11: + 169 0030 1943 orrs r1, r3 + 170 .LVL12: + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Store the new register value */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 171 .loc 1 185 0 discriminator 2 + 172 0032 3160 str r1, [r6] + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 173 .loc 1 187 0 discriminator 2 + 174 0034 0168 ldr r1, [r0] + 175 .LVL13: + 176 0036 0B68 ldr r3, [r1] + 177 0038 1343 orrs r3, r2 + 178 003a 0B60 str r3, [r1] + 179 .LVL14: + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 180 .loc 1 189 0 discriminator 2 + 181 003c 2023 movs r3, #32 + 182 003e 4355 strb r3, [r0, r5] + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 183 .loc 1 192 0 discriminator 2 + 184 0040 0023 movs r3, #0 + 185 0042 0355 strb r3, [r0, r4] + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_OK; + 186 .loc 1 194 0 discriminator 2 + 187 0044 0020 movs r0, #0 + 188 .LVL15: + 189 0046 00E0 b .L8 + 190 .LVL16: + 191 .L9: + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** else + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_BUSY; + 192 .loc 1 198 0 + 193 0048 0220 movs r0, #2 + 194 .LVL17: + 195 .L8: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 196 .loc 1 200 0 + 197 @ sp needed + 198 004a F0BD pop {r4, r5, r6, r7, pc} + 199 .LVL18: + 200 .L10: + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccHVO7A6.s page 8 + + + 201 .loc 1 168 0 + 202 004c 0220 movs r0, #2 + 203 .LVL19: + 204 004e FCE7 b .L8 + 205 .L12: + 206 .align 2 + 207 .L11: + 208 0050 FFF0FFFF .word -3841 + 209 .cfi_endproc + 210 .LFE40: + 212 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits + 213 .align 1 + 214 .global HAL_I2CEx_EnableWakeUp + 215 .syntax unified + 216 .code 16 + 217 .thumb_func + 218 .fpu softvfp + 220 HAL_I2CEx_EnableWakeUp: + 221 .LFB41: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s). + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval HAL status + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 222 .loc 1 209 0 + 223 .cfi_startproc + 224 @ args = 0, pretend = 0, frame = 0 + 225 @ frame_needed = 0, uses_anonymous_args = 0 + 226 .LVL20: + 227 0000 70B5 push {r4, r5, r6, lr} + 228 .LCFI2: + 229 .cfi_def_cfa_offset 16 + 230 .cfi_offset 4, -16 + 231 .cfi_offset 5, -12 + 232 .cfi_offset 6, -8 + 233 .cfi_offset 14, -4 + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameters */ + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 234 .loc 1 213 0 + 235 0002 4123 movs r3, #65 + 236 0004 C35C ldrb r3, [r0, r3] + 237 0006 202B cmp r3, #32 + 238 0008 1DD1 bne .L15 + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Locked */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 239 .loc 1 216 0 + 240 000a 2033 adds r3, r3, #32 + 241 000c C35C ldrb r3, [r0, r3] + 242 000e 012B cmp r3, #1 + 243 0010 1BD0 beq .L16 + ARM GAS /tmp/ccHVO7A6.s page 9 + + + 244 .loc 1 216 0 is_stmt 0 discriminator 2 + 245 0012 4021 movs r1, #64 + 246 0014 0122 movs r2, #1 + 247 0016 4254 strb r2, [r0, r1] + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 248 .loc 1 218 0 is_stmt 1 discriminator 2 + 249 0018 4124 movs r4, #65 + 250 001a 2423 movs r3, #36 + 251 001c 0355 strb r3, [r0, r4] + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 252 .loc 1 221 0 discriminator 2 + 253 001e 0568 ldr r5, [r0] + 254 0020 2B68 ldr r3, [r5] + 255 0022 9343 bics r3, r2 + 256 0024 2B60 str r3, [r5] + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + 257 .loc 1 224 0 discriminator 2 + 258 0026 0568 ldr r5, [r0] + 259 0028 2E68 ldr r6, [r5] + 260 002a 8023 movs r3, #128 + 261 002c DB02 lsls r3, r3, #11 + 262 002e 3343 orrs r3, r6 + 263 0030 2B60 str r3, [r5] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 264 .loc 1 226 0 discriminator 2 + 265 0032 0568 ldr r5, [r0] + 266 0034 2B68 ldr r3, [r5] + 267 0036 1343 orrs r3, r2 + 268 0038 2B60 str r3, [r5] + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 269 .loc 1 228 0 discriminator 2 + 270 003a 2023 movs r3, #32 + 271 003c 0355 strb r3, [r0, r4] + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 272 .loc 1 231 0 discriminator 2 + 273 003e 0023 movs r3, #0 + 274 0040 4354 strb r3, [r0, r1] + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_OK; + 275 .loc 1 233 0 discriminator 2 + 276 0042 0020 movs r0, #0 + 277 .LVL21: + 278 0044 00E0 b .L14 + 279 .LVL22: + 280 .L15: + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** else + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + ARM GAS /tmp/ccHVO7A6.s page 10 + + + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_BUSY; + 281 .loc 1 237 0 + 282 0046 0220 movs r0, #2 + 283 .LVL23: + 284 .L14: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 285 .loc 1 239 0 + 286 @ sp needed + 287 0048 70BD pop {r4, r5, r6, pc} + 288 .LVL24: + 289 .L16: + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 290 .loc 1 216 0 + 291 004a 0220 movs r0, #2 + 292 .LVL25: + 293 004c FCE7 b .L14 + 294 .cfi_endproc + 295 .LFE41: + 297 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits + 298 .align 1 + 299 .global HAL_I2CEx_DisableWakeUp + 300 .syntax unified + 301 .code 16 + 302 .thumb_func + 303 .fpu softvfp + 305 HAL_I2CEx_DisableWakeUp: + 306 .LFB42: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s). + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval HAL status + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 307 .loc 1 248 0 + 308 .cfi_startproc + 309 @ args = 0, pretend = 0, frame = 0 + 310 @ frame_needed = 0, uses_anonymous_args = 0 + 311 .LVL26: + 312 0000 70B5 push {r4, r5, r6, lr} + 313 .LCFI3: + 314 .cfi_def_cfa_offset 16 + 315 .cfi_offset 4, -16 + 316 .cfi_offset 5, -12 + 317 .cfi_offset 6, -8 + 318 .cfi_offset 14, -4 + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameters */ + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 319 .loc 1 252 0 + 320 0002 4123 movs r3, #65 + 321 0004 C35C ldrb r3, [r0, r3] + 322 0006 202B cmp r3, #32 + ARM GAS /tmp/ccHVO7A6.s page 11 + + + 323 0008 1CD1 bne .L19 + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Locked */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 324 .loc 1 255 0 + 325 000a 2033 adds r3, r3, #32 + 326 000c C35C ldrb r3, [r0, r3] + 327 000e 012B cmp r3, #1 + 328 0010 1AD0 beq .L20 + 329 .loc 1 255 0 is_stmt 0 discriminator 2 + 330 0012 4021 movs r1, #64 + 331 0014 0122 movs r2, #1 + 332 0016 4254 strb r2, [r0, r1] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 333 .loc 1 257 0 is_stmt 1 discriminator 2 + 334 0018 4124 movs r4, #65 + 335 001a 2423 movs r3, #36 + 336 001c 0355 strb r3, [r0, r4] + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 337 .loc 1 260 0 discriminator 2 + 338 001e 0568 ldr r5, [r0] + 339 0020 2B68 ldr r3, [r5] + 340 0022 9343 bics r3, r2 + 341 0024 2B60 str r3, [r5] + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + 342 .loc 1 263 0 discriminator 2 + 343 0026 0568 ldr r5, [r0] + 344 0028 2B68 ldr r3, [r5] + 345 002a 084E ldr r6, .L21 + 346 002c 3340 ands r3, r6 + 347 002e 2B60 str r3, [r5] + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 348 .loc 1 265 0 discriminator 2 + 349 0030 0568 ldr r5, [r0] + 350 0032 2B68 ldr r3, [r5] + 351 0034 1343 orrs r3, r2 + 352 0036 2B60 str r3, [r5] + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 353 .loc 1 267 0 discriminator 2 + 354 0038 2023 movs r3, #32 + 355 003a 0355 strb r3, [r0, r4] + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 356 .loc 1 270 0 discriminator 2 + 357 003c 0023 movs r3, #0 + 358 003e 4354 strb r3, [r0, r1] + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_OK; + 359 .loc 1 272 0 discriminator 2 + ARM GAS /tmp/ccHVO7A6.s page 12 + + + 360 0040 0020 movs r0, #0 + 361 .LVL27: + 362 0042 00E0 b .L18 + 363 .LVL28: + 364 .L19: + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** else + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** return HAL_BUSY; + 365 .loc 1 276 0 + 366 0044 0220 movs r0, #2 + 367 .LVL29: + 368 .L18: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 369 .loc 1 278 0 + 370 @ sp needed + 371 0046 70BD pop {r4, r5, r6, pc} + 372 .LVL30: + 373 .L20: + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 374 .loc 1 255 0 + 375 0048 0220 movs r0, #2 + 376 .LVL31: + 377 004a FCE7 b .L18 + 378 .L22: + 379 .align 2 + 380 .L21: + 381 004c FFFFFBFF .word -262145 + 382 .cfi_endproc + 383 .LFE42: + 385 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + 386 .align 1 + 387 .global HAL_I2CEx_EnableFastModePlus + 388 .syntax unified + 389 .code 16 + 390 .thumb_func + 391 .fpu softvfp + 393 HAL_I2CEx_EnableFastModePlus: + 394 .LFB43: + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval None + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + ARM GAS /tmp/ccHVO7A6.s page 13 + + + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 395 .loc 1 296 0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 399 @ link register save eliminated. + 400 .LVL32: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameter */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 401 .loc 1 301 0 + 402 0000 044A ldr r2, .L24 + 403 0002 536B ldr r3, [r2, #52] + 404 0004 0121 movs r1, #1 + 405 0006 0B43 orrs r3, r1 + 406 0008 5363 str r3, [r2, #52] + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus); + 407 .loc 1 304 0 + 408 000a 034A ldr r2, .L24+4 + 409 000c 5368 ldr r3, [r2, #4] + 410 000e 1843 orrs r0, r3 + 411 .LVL33: + 412 0010 5060 str r0, [r2, #4] + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 413 .loc 1 305 0 + 414 @ sp needed + 415 0012 7047 bx lr + 416 .L25: + 417 .align 2 + 418 .L24: + 419 0014 00100240 .word 1073876992 + 420 0018 00000140 .word 1073807360 + 421 .cfi_endproc + 422 .LFE43: + 424 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 425 .align 1 + 426 .global HAL_I2CEx_DisableFastModePlus + 427 .syntax unified + 428 .code 16 + 429 .thumb_func + 430 .fpu softvfp + 432 HAL_I2CEx_DisableFastModePlus: + 433 .LFB44: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /** + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + ARM GAS /tmp/ccHVO7A6.s page 14 + + + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** * @retval None + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** */ + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** { + 434 .loc 1 323 0 + 435 .cfi_startproc + 436 @ args = 0, pretend = 0, frame = 0 + 437 @ frame_needed = 0, uses_anonymous_args = 0 + 438 @ link register save eliminated. + 439 .LVL34: + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Check the parameter */ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 440 .loc 1 328 0 + 441 0000 044A ldr r2, .L27 + 442 0002 536B ldr r3, [r2, #52] + 443 0004 0121 movs r1, #1 + 444 0006 0B43 orrs r3, r1 + 445 0008 5363 str r3, [r2, #52] + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus); + 446 .loc 1 331 0 + 447 000a 034A ldr r2, .L27+4 + 448 000c 5368 ldr r3, [r2, #4] + 449 000e 8343 bics r3, r0 + 450 0010 5360 str r3, [r2, #4] + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c **** } + 451 .loc 1 332 0 + 452 @ sp needed + 453 0012 7047 bx lr + 454 .L28: + 455 .align 2 + 456 .L27: + 457 0014 00100240 .word 1073876992 + 458 0018 00000140 .word 1073807360 + 459 .cfi_endproc + 460 .LFE44: + 462 .text + 463 .Letext0: + 464 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 465 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 466 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 467 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 468 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 469 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 470 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 471 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 472 .file 10 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 473 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 474 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h" + ARM GAS /tmp/ccHVO7A6.s page 15 + + + ARM GAS /tmp/ccHVO7A6.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_i2c_ex.c + /tmp/ccHVO7A6.s:16 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 $t + /tmp/ccHVO7A6.s:23 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/ccHVO7A6.s:107 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000054 $d + /tmp/ccHVO7A6.s:112 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 $t + /tmp/ccHVO7A6.s:119 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/ccHVO7A6.s:208 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000050 $d + /tmp/ccHVO7A6.s:213 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 $t + /tmp/ccHVO7A6.s:220 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 HAL_I2CEx_EnableWakeUp + /tmp/ccHVO7A6.s:298 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 $t + /tmp/ccHVO7A6.s:305 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 HAL_I2CEx_DisableWakeUp + /tmp/ccHVO7A6.s:381 .text.HAL_I2CEx_DisableWakeUp:000000000000004c $d + /tmp/ccHVO7A6.s:386 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 $t + /tmp/ccHVO7A6.s:393 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 HAL_I2CEx_EnableFastModePlus + /tmp/ccHVO7A6.s:419 .text.HAL_I2CEx_EnableFastModePlus:0000000000000014 $d + /tmp/ccHVO7A6.s:425 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 $t + /tmp/ccHVO7A6.s:432 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 HAL_I2CEx_DisableFastModePlus + /tmp/ccHVO7A6.s:457 .text.HAL_I2CEx_DisableFastModePlus:0000000000000014 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_i2s.d b/build/stm32l0xx_hal_i2s.d new file mode 100644 index 0000000..7f9c986 --- /dev/null +++ b/build/stm32l0xx_hal_i2s.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_i2s.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_i2s.lst b/build/stm32l0xx_hal_i2s.lst new file mode 100644 index 0000000..e3aab03 --- /dev/null +++ b/build/stm32l0xx_hal_i2s.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccv2GA5P.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_i2s.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccv2GA5P.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_i2s.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_irda.d b/build/stm32l0xx_hal_irda.d new file mode 100644 index 0000000..93e5cd1 --- /dev/null +++ b/build/stm32l0xx_hal_irda.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_irda.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_irda.lst b/build/stm32l0xx_hal_irda.lst new file mode 100644 index 0000000..7f003cf --- /dev/null +++ b/build/stm32l0xx_hal_irda.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccXPAaVX.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_irda.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccXPAaVX.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_irda.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_iwdg.d b/build/stm32l0xx_hal_iwdg.d new file mode 100644 index 0000000..a24a68a --- /dev/null +++ b/build/stm32l0xx_hal_iwdg.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_iwdg.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_iwdg.lst b/build/stm32l0xx_hal_iwdg.lst new file mode 100644 index 0000000..b18a7df --- /dev/null +++ b/build/stm32l0xx_hal_iwdg.lst @@ -0,0 +1,457 @@ +ARM GAS /tmp/ccx6pHMx.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_iwdg.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_IWDG_Init,"ax",%progbits + 16 .align 1 + 17 .global HAL_IWDG_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_IWDG_Init: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @file stm32l0xx_hal_iwdg.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief IWDG HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * functionalities of the Independent Watchdog (IWDG) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + Initialization and Start functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + IO operation functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @verbatim + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ============================================================================== + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ##### IWDG Generic features ##### + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) The IWDG can be started by either software or hardware (configurable + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** through option byte). + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** if the main clock fails. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Once the IWDG is started, the LSI is forced ON and both can not be + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** disabled. The counter starts counting down from the reset value (0xFFF). + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** When it reaches the end of count value (0x000) a reset signal is + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** generated (IWDG reset). + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** the IWDG_RLR value is reloaded in the counter and the watchdog reset is + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** prevented. + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) The IWDG is implemented in the VDD voltage domain that is still functional + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + ARM GAS /tmp/ccx6pHMx.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** reset occurs. + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Debug mode : When the microcontroller enters debug mode (core halted), + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** the IWDG counter either continues to work normally or stops, depending + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** on DBG_IWDG_STOP configuration bit in DBG module, accessible through + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] Min-max timeout value @32KHz (LSI): ~0.512ms / ~32.0s + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** The IWDG timeout may vary due to LSI frequency dispersion. STM32L0xx + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** devices provide the capability to measure the LSI frequency (LSI clock + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** connected internally to TIM5 CH4 input capture). The measured value + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** can be used to have an IWDG timeout with an acceptable accuracy. + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ##### How to use this driver ##### + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ============================================================================== + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (#) Use IWDG using HAL_IWDG_Init() function to : + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** clock is forced ON and IWDG counter starts downcounting. + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** IWDG_WINR. + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (++) Configure the IWDG prescaler and counter reload value. This reload + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** value will be loaded in the IWDG counter each time the watchdog is + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** reloaded, then the IWDG will start counting down from this value. + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (++) Wait for status flags to be reset + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (++) Depending on window parameter: + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+++) If Window Init parameter is same as Window register value, + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** nothing more is done but reload counter value in order to exit + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** function withy exact time base. + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+++) Else modify Window register. This will automatically reload + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** watchdog counter. + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (#) Then the application program must refresh the IWDG counter at regular + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** intervals during normal operation to prevent an MCU reset, using + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** HAL_IWDG_Refresh() function. + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** *** IWDG HAL driver macros list *** + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ==================================== + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** Below the list of most used macros in IWDG HAL driver: + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) __HAL_IWDG_START: Enable the IWDG peripheral + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** the reload register + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @endverbatim + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ****************************************************************************** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @attention + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * Redistribution and use in source and binary forms, with or without modification, + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * are permitted provided that the following conditions are met: + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * 1. Redistributions of source code must retain the above copyright notice, + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * this list of conditions and the following disclaimer. + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * this list of conditions and the following disclaimer in the documentation + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * and/or other materials provided with the distribution. + ARM GAS /tmp/ccx6pHMx.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * may be used to endorse or promote products derived from this software + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * without specific prior written permission. + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ****************************************************************************** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Includes ------------------------------------------------------------------*/ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** #include "stm32l0xx_hal.h" + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @addtogroup STM32L0xx_HAL_Driver + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** #ifdef HAL_IWDG_MODULE_ENABLED + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @addtogroup IWDG + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief IWDG HAL module driver. + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Private typedef -----------------------------------------------------------*/ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Private define ------------------------------------------------------------*/ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @defgroup IWDG_Private_Defines IWDG Private Defines + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Status register need 5 RC LSI divided by prescaler clock to be updated. With + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** higher prescaler (256), and according to LSI variation, we need to wait at + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** least 6 cycles so 48 ms. */ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** #define HAL_IWDG_DEFAULT_TIMEOUT 48U + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @} + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Private macro -------------------------------------------------------------*/ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Private variables ---------------------------------------------------------*/ + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Private function prototypes -----------------------------------------------*/ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Exported functions --------------------------------------------------------*/ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions_Group1 + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief Initialization and Start functions. + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @verbatim + ARM GAS /tmp/ccx6pHMx.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** =============================================================================== + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ##### Initialization and Start functions ##### + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** =============================================================================== + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] This section provides functions allowing to: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Initialize the IWDG according to the specified parameters in the + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** IWDG_InitTypeDef of associated handle. + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Manage Window option. + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** is reloaded in order to exit function with correct time base. + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @endverbatim + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief Initialize the IWDG according to the specified parameters in the + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * IWDG_InitTypeDef and start watchdog. Before exiting function, + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * watchdog is refreshed in order to have correct time base. + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * the configuration information for the specified IWDG module. + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @retval HAL status + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 26 .loc 1 171 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 041E subs r4, r0, #0 + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** uint32_t tickstart; + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Check the IWDG handle allocation */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** if(hiwdg == NULL) + 39 .loc 1 175 0 + 40 0004 24D0 beq .L6 + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** return HAL_ERROR; + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Check the parameters */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Enable IWDG. LSI is turned on automaticaly */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** __HAL_IWDG_START(hiwdg); + 41 .loc 1 187 0 + 42 0006 0368 ldr r3, [r0] + ARM GAS /tmp/ccx6pHMx.s page 5 + + + 43 0008 124A ldr r2, .L9 + 44 000a 1A60 str r2, [r3] + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** 0x5555 in KR */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** IWDG_ENABLE_WRITE_ACCESS(hiwdg); + 45 .loc 1 191 0 + 46 000c 0368 ldr r3, [r0] + 47 000e 124A ldr r2, .L9+4 + 48 0010 1A60 str r2, [r3] + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Write to IWDG registers the Prescaler & Reload values to work with */ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** hiwdg->Instance->PR = hiwdg->Init.Prescaler; + 49 .loc 1 194 0 + 50 0012 0368 ldr r3, [r0] + 51 0014 4268 ldr r2, [r0, #4] + 52 0016 5A60 str r2, [r3, #4] + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** hiwdg->Instance->RLR = hiwdg->Init.Reload; + 53 .loc 1 195 0 + 54 0018 0368 ldr r3, [r0] + 55 001a 8268 ldr r2, [r0, #8] + 56 001c 9A60 str r2, [r3, #8] + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Check pending flag, if previous update not done, return timeout */ + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** tickstart = HAL_GetTick(); + 57 .loc 1 198 0 + 58 001e FFF7FEFF bl HAL_GetTick + 59 .LVL1: + 60 0022 0500 movs r5, r0 + 61 .LVL2: + 62 .L3: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Wait for register to be updated */ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** while(hiwdg->Instance->SR != RESET) + 63 .loc 1 201 0 + 64 0024 2368 ldr r3, [r4] + 65 0026 DA68 ldr r2, [r3, #12] + 66 0028 002A cmp r2, #0 + 67 002a 06D0 beq .L8 + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + 68 .loc 1 203 0 + 69 002c FFF7FEFF bl HAL_GetTick + 70 .LVL3: + 71 0030 401B subs r0, r0, r5 + 72 0032 3028 cmp r0, #48 + 73 0034 F6D9 bls .L3 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** return HAL_TIMEOUT; + 74 .loc 1 205 0 + 75 0036 0320 movs r0, #3 + 76 0038 0BE0 b .L2 + 77 .L8: + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* If window parameter is different than current value, modify window + ARM GAS /tmp/ccx6pHMx.s page 6 + + + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** register */ + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** if(hiwdg->Instance->WINR != hiwdg->Init.Window) + 78 .loc 1 211 0 + 79 003a 1969 ldr r1, [r3, #16] + 80 003c E268 ldr r2, [r4, #12] + 81 003e 9142 cmp r1, r2 + 82 0040 02D0 beq .L5 + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** even if window feature is disabled, Watchdog will be reloaded by writing + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** windows register */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** hiwdg->Instance->WINR = hiwdg->Init.Window; + 83 .loc 1 216 0 + 84 0042 1A61 str r2, [r3, #16] + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** else + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Reload IWDG counter with value defined in the reload register */ + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** __HAL_IWDG_RELOAD_COUNTER(hiwdg); + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Return function status */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** return HAL_OK; + 85 .loc 1 225 0 + 86 0044 0020 movs r0, #0 + 87 0046 04E0 b .L2 + 88 .L5: + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 89 .loc 1 221 0 + 90 0048 044A ldr r2, .L9+8 + 91 004a 1A60 str r2, [r3] + 92 .loc 1 225 0 + 93 004c 0020 movs r0, #0 + 94 004e 00E0 b .L2 + 95 .LVL4: + 96 .L6: + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 97 .loc 1 177 0 + 98 0050 0120 movs r0, #1 + 99 .LVL5: + 100 .L2: + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 101 .loc 1 226 0 + 102 @ sp needed + 103 .LVL6: + 104 0052 70BD pop {r4, r5, r6, pc} + 105 .L10: + 106 .align 2 + 107 .L9: + 108 0054 CCCC0000 .word 52428 + 109 0058 55550000 .word 21845 + 110 005c AAAA0000 .word 43690 + 111 .cfi_endproc + 112 .LFE39: + 114 .section .text.HAL_IWDG_Refresh,"ax",%progbits + 115 .align 1 + 116 .global HAL_IWDG_Refresh + ARM GAS /tmp/ccx6pHMx.s page 7 + + + 117 .syntax unified + 118 .code 16 + 119 .thumb_func + 120 .fpu softvfp + 122 HAL_IWDG_Refresh: + 123 .LFB40: + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @} + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** @addtogroup IWDG_Exported_Functions_Group2 + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief IO operation functions + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @verbatim + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** =============================================================================== + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** ##### IO operation functions ##### + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** =============================================================================== + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** [..] This section provides functions allowing to: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** (+) Refresh the IWDG. + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** @endverbatim + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @{ + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @brief Refresh the IWDG. + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * the configuration information for the specified IWDG module. + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** * @retval HAL status + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** */ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** { + 124 .loc 1 255 0 + 125 .cfi_startproc + 126 @ args = 0, pretend = 0, frame = 0 + 127 @ frame_needed = 0, uses_anonymous_args = 0 + 128 @ link register save eliminated. + 129 .LVL7: + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Reload IWDG counter with value defined in the reload register */ + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** __HAL_IWDG_RELOAD_COUNTER(hiwdg); + 130 .loc 1 257 0 + 131 0000 0368 ldr r3, [r0] + 132 0002 024A ldr r2, .L12 + 133 0004 1A60 str r2, [r3] + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** /* Return function status */ + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** return HAL_OK; + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c **** } + 134 .loc 1 261 0 + 135 0006 0020 movs r0, #0 + 136 .LVL8: + 137 @ sp needed + 138 0008 7047 bx lr + 139 .L13: + ARM GAS /tmp/ccx6pHMx.s page 8 + + + 140 000a C046 .align 2 + 141 .L12: + 142 000c AAAA0000 .word 43690 + 143 .cfi_endproc + 144 .LFE40: + 146 .text + 147 .Letext0: + 148 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 149 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 150 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 151 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 152 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 153 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 154 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 155 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 156 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 157 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 158 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h" + 159 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccx6pHMx.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_iwdg.c + /tmp/ccx6pHMx.s:16 .text.HAL_IWDG_Init:0000000000000000 $t + /tmp/ccx6pHMx.s:23 .text.HAL_IWDG_Init:0000000000000000 HAL_IWDG_Init + /tmp/ccx6pHMx.s:108 .text.HAL_IWDG_Init:0000000000000054 $d + /tmp/ccx6pHMx.s:115 .text.HAL_IWDG_Refresh:0000000000000000 $t + /tmp/ccx6pHMx.s:122 .text.HAL_IWDG_Refresh:0000000000000000 HAL_IWDG_Refresh + /tmp/ccx6pHMx.s:142 .text.HAL_IWDG_Refresh:000000000000000c $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/build/stm32l0xx_hal_lcd.d b/build/stm32l0xx_hal_lcd.d new file mode 100644 index 0000000..9566f36 --- /dev/null +++ b/build/stm32l0xx_hal_lcd.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_lcd.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_lcd.lst b/build/stm32l0xx_hal_lcd.lst new file mode 100644 index 0000000..cc67283 --- /dev/null +++ b/build/stm32l0xx_hal_lcd.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccsHrVGL.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_lcd.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccsHrVGL.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_lcd.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_lptim.d b/build/stm32l0xx_hal_lptim.d new file mode 100644 index 0000000..5b4e279 --- /dev/null +++ b/build/stm32l0xx_hal_lptim.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_lptim.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_lptim.lst b/build/stm32l0xx_hal_lptim.lst new file mode 100644 index 0000000..817eb05 --- /dev/null +++ b/build/stm32l0xx_hal_lptim.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cc97zjw3.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_lptim.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc97zjw3.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_lptim.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_msp.d b/build/stm32l0xx_hal_msp.d new file mode 100644 index 0000000..a68d229 --- /dev/null +++ b/build/stm32l0xx_hal_msp.d @@ -0,0 +1,147 @@ +build/stm32l0xx_hal_msp.d: Src/stm32l0xx_hal_msp.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/low_power.h \ + Middlewares/Third_Party/Lora/Utilities/delay.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/low_power.h: + +Middlewares/Third_Party/Lora/Utilities/delay.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: diff --git a/build/stm32l0xx_hal_msp.lst b/build/stm32l0xx_hal_msp.lst new file mode 100644 index 0000000..68c8592 --- /dev/null +++ b/build/stm32l0xx_hal_msp.lst @@ -0,0 +1,676 @@ +ARM GAS /tmp/ccbuzBhk.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_msp.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_InitTick,"ax",%progbits + 16 .align 1 + 17 .global HAL_InitTick + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_InitTick: + 24 .LFB96: + 25 .file 1 "./Src/stm32l0xx_hal_msp.c" + 1:./Src/stm32l0xx_hal_msp.c **** + 2:./Src/stm32l0xx_hal_msp.c **** /****************************************************************************** + 3:./Src/stm32l0xx_hal_msp.c **** * @file stm32l0xx_hal_msp.c + 4:./Src/stm32l0xx_hal_msp.c **** * @author MCD Application Team + 5:./Src/stm32l0xx_hal_msp.c **** * @version V1.1.2 + 6:./Src/stm32l0xx_hal_msp.c **** * @date 08-September-2017 + 7:./Src/stm32l0xx_hal_msp.c **** * @brief msp file for HAL + 8:./Src/stm32l0xx_hal_msp.c **** ****************************************************************************** + 9:./Src/stm32l0xx_hal_msp.c **** * @attention + 10:./Src/stm32l0xx_hal_msp.c **** * + 11:./Src/stm32l0xx_hal_msp.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 12:./Src/stm32l0xx_hal_msp.c **** * All rights reserved.

+ 13:./Src/stm32l0xx_hal_msp.c **** * + 14:./Src/stm32l0xx_hal_msp.c **** * Redistribution and use in source and binary forms, with or without + 15:./Src/stm32l0xx_hal_msp.c **** * modification, are permitted, provided that the following conditions are met: + 16:./Src/stm32l0xx_hal_msp.c **** * + 17:./Src/stm32l0xx_hal_msp.c **** * 1. Redistribution of source code must retain the above copyright notice, + 18:./Src/stm32l0xx_hal_msp.c **** * this list of conditions and the following disclaimer. + 19:./Src/stm32l0xx_hal_msp.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 20:./Src/stm32l0xx_hal_msp.c **** * this list of conditions and the following disclaimer in the documentation + 21:./Src/stm32l0xx_hal_msp.c **** * and/or other materials provided with the distribution. + 22:./Src/stm32l0xx_hal_msp.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 23:./Src/stm32l0xx_hal_msp.c **** * contributors to this software may be used to endorse or promote products + 24:./Src/stm32l0xx_hal_msp.c **** * derived from this software without specific written permission. + 25:./Src/stm32l0xx_hal_msp.c **** * 4. This software, including modifications and/or derivative works of this + 26:./Src/stm32l0xx_hal_msp.c **** * software, must execute solely and exclusively on microcontroller or + 27:./Src/stm32l0xx_hal_msp.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 28:./Src/stm32l0xx_hal_msp.c **** * 5. Redistribution and use of this software other than as permitted under + 29:./Src/stm32l0xx_hal_msp.c **** * this license is void and will automatically terminate your rights under + 30:./Src/stm32l0xx_hal_msp.c **** * this license. + 31:./Src/stm32l0xx_hal_msp.c **** * + 32:./Src/stm32l0xx_hal_msp.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 33:./Src/stm32l0xx_hal_msp.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + ARM GAS /tmp/ccbuzBhk.s page 2 + + + 34:./Src/stm32l0xx_hal_msp.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 35:./Src/stm32l0xx_hal_msp.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 36:./Src/stm32l0xx_hal_msp.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 37:./Src/stm32l0xx_hal_msp.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 38:./Src/stm32l0xx_hal_msp.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 39:./Src/stm32l0xx_hal_msp.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 40:./Src/stm32l0xx_hal_msp.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 41:./Src/stm32l0xx_hal_msp.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 42:./Src/stm32l0xx_hal_msp.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 43:./Src/stm32l0xx_hal_msp.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 44:./Src/stm32l0xx_hal_msp.c **** * + 45:./Src/stm32l0xx_hal_msp.c **** ****************************************************************************** + 46:./Src/stm32l0xx_hal_msp.c **** */ + 47:./Src/stm32l0xx_hal_msp.c **** + 48:./Src/stm32l0xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ + 49:./Src/stm32l0xx_hal_msp.c **** #include "hw.h" + 50:./Src/stm32l0xx_hal_msp.c **** #include "low_power.h" + 51:./Src/stm32l0xx_hal_msp.c **** #include "delay.h" + 52:./Src/stm32l0xx_hal_msp.c **** #include "timeServer.h" + 53:./Src/stm32l0xx_hal_msp.c **** /* when fast wake up is enabled, the mcu wakes up in ~20us * and + 54:./Src/stm32l0xx_hal_msp.c **** * does not wait for the VREFINT to be settled. THis is ok for + 55:./Src/stm32l0xx_hal_msp.c **** * most of the case except when adc must be used in this case before + 56:./Src/stm32l0xx_hal_msp.c **** *starting the adc, you must make sure VREFINT is settled*/ + 57:./Src/stm32l0xx_hal_msp.c **** #define ENABLE_FAST_WAKEUP + 58:./Src/stm32l0xx_hal_msp.c **** + 59:./Src/stm32l0xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ + 60:./Src/stm32l0xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ + 61:./Src/stm32l0xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ + 62:./Src/stm32l0xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ + 63:./Src/stm32l0xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ + 64:./Src/stm32l0xx_hal_msp.c **** /* Private functions ---------------------------------------------------------*/ + 65:./Src/stm32l0xx_hal_msp.c **** + 66:./Src/stm32l0xx_hal_msp.c **** /** + 67:./Src/stm32l0xx_hal_msp.c **** * @brief This function configures the source of the time base. + 68:./Src/stm32l0xx_hal_msp.c **** * @brief don't enable systick + 69:./Src/stm32l0xx_hal_msp.c **** * @param TickPriority: Tick interrupt priority. + 70:./Src/stm32l0xx_hal_msp.c **** * @retval HAL status + 71:./Src/stm32l0xx_hal_msp.c **** */ + 72:./Src/stm32l0xx_hal_msp.c **** HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 73:./Src/stm32l0xx_hal_msp.c **** { + 26 .loc 1 73 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 74:./Src/stm32l0xx_hal_msp.c **** /* Return function status */ + 75:./Src/stm32l0xx_hal_msp.c **** return HAL_OK; + 76:./Src/stm32l0xx_hal_msp.c **** } + 32 .loc 1 76 0 + 33 0000 0020 movs r0, #0 + 34 .LVL1: + 35 @ sp needed + 36 0002 7047 bx lr + 37 .cfi_endproc + 38 .LFE96: + 40 .section .text.HAL_Delay,"ax",%progbits + ARM GAS /tmp/ccbuzBhk.s page 3 + + + 41 .align 1 + 42 .global HAL_Delay + 43 .syntax unified + 44 .code 16 + 45 .thumb_func + 46 .fpu softvfp + 48 HAL_Delay: + 49 .LFB97: + 77:./Src/stm32l0xx_hal_msp.c **** + 78:./Src/stm32l0xx_hal_msp.c **** /** + 79:./Src/stm32l0xx_hal_msp.c **** * @brief This function provides delay (in ms) + 80:./Src/stm32l0xx_hal_msp.c **** * @param Delay: specifies the delay time length, in milliseconds. + 81:./Src/stm32l0xx_hal_msp.c **** * @retval None + 82:./Src/stm32l0xx_hal_msp.c **** */ + 83:./Src/stm32l0xx_hal_msp.c **** void HAL_Delay(__IO uint32_t Delay) + 84:./Src/stm32l0xx_hal_msp.c **** { + 50 .loc 1 84 0 + 51 .cfi_startproc + 52 @ args = 0, pretend = 0, frame = 8 + 53 @ frame_needed = 0, uses_anonymous_args = 0 + 54 .LVL2: + 55 0000 00B5 push {lr} + 56 .LCFI0: + 57 .cfi_def_cfa_offset 4 + 58 .cfi_offset 14, -4 + 59 0002 83B0 sub sp, sp, #12 + 60 .LCFI1: + 61 .cfi_def_cfa_offset 16 + 62 0004 0190 str r0, [sp, #4] + 85:./Src/stm32l0xx_hal_msp.c **** DelayMs( Delay ); /* based on RTC */ + 63 .loc 1 85 0 + 64 0006 0198 ldr r0, [sp, #4] + 65 .LVL3: + 66 0008 FFF7FEFF bl DelayMs + 67 .LVL4: + 86:./Src/stm32l0xx_hal_msp.c **** } + 68 .loc 1 86 0 + 69 000c 03B0 add sp, sp, #12 + 70 @ sp needed + 71 000e 00BD pop {pc} + 72 .cfi_endproc + 73 .LFE97: + 75 .section .text.HAL_MspInit,"ax",%progbits + 76 .align 1 + 77 .global HAL_MspInit + 78 .syntax unified + 79 .code 16 + 80 .thumb_func + 81 .fpu softvfp + 83 HAL_MspInit: + 84 .LFB98: + 87:./Src/stm32l0xx_hal_msp.c **** + 88:./Src/stm32l0xx_hal_msp.c **** /** + 89:./Src/stm32l0xx_hal_msp.c **** * @brief Initializes the MSP. + 90:./Src/stm32l0xx_hal_msp.c **** * @retval None + 91:./Src/stm32l0xx_hal_msp.c **** */ + 92:./Src/stm32l0xx_hal_msp.c **** void HAL_MspInit(void) + ARM GAS /tmp/ccbuzBhk.s page 4 + + + 93:./Src/stm32l0xx_hal_msp.c **** { + 85 .loc 1 93 0 + 86 .cfi_startproc + 87 @ args = 0, pretend = 0, frame = 0 + 88 @ frame_needed = 0, uses_anonymous_args = 0 + 89 0000 10B5 push {r4, lr} + 90 .LCFI2: + 91 .cfi_def_cfa_offset 8 + 92 .cfi_offset 4, -8 + 93 .cfi_offset 14, -4 + 94:./Src/stm32l0xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 94 .loc 1 94 0 + 95 0002 094A ldr r2, .L4 + 96 0004 916B ldr r1, [r2, #56] + 97 0006 8023 movs r3, #128 + 98 0008 5B05 lsls r3, r3, #21 + 99 000a 0B43 orrs r3, r1 + 100 000c 9363 str r3, [r2, #56] + 95:./Src/stm32l0xx_hal_msp.c **** + 96:./Src/stm32l0xx_hal_msp.c **** /* Disable the Power Voltage Detector */ + 97:./Src/stm32l0xx_hal_msp.c **** HAL_PWR_DisablePVD( ); + 101 .loc 1 97 0 + 102 000e FFF7FEFF bl HAL_PWR_DisablePVD + 103 .LVL5: + 98:./Src/stm32l0xx_hal_msp.c **** + 99:./Src/stm32l0xx_hal_msp.c **** /* Enables the Ultra Low Power mode */ + 100:./Src/stm32l0xx_hal_msp.c **** HAL_PWREx_EnableUltraLowPower( ); + 104 .loc 1 100 0 + 105 0012 FFF7FEFF bl HAL_PWREx_EnableUltraLowPower + 106 .LVL6: + 101:./Src/stm32l0xx_hal_msp.c **** + 102:./Src/stm32l0xx_hal_msp.c **** __HAL_FLASH_SLEEP_POWERDOWN_ENABLE(); + 107 .loc 1 102 0 + 108 0016 054A ldr r2, .L4+4 + 109 0018 1368 ldr r3, [r2] + 110 001a 0821 movs r1, #8 + 111 001c 0B43 orrs r3, r1 + 112 001e 1360 str r3, [r2] + 103:./Src/stm32l0xx_hal_msp.c **** + 104:./Src/stm32l0xx_hal_msp.c **** /*In debug mode, e.g. when DBGMCU is activated, Arm core has always clocks + 105:./Src/stm32l0xx_hal_msp.c **** * And will not wait that the FLACH is ready to be read. It can miss in this + 106:./Src/stm32l0xx_hal_msp.c **** * case the first instruction. To overcome this issue, the flash remain clcoked during sleep mode + 107:./Src/stm32l0xx_hal_msp.c **** */ + 108:./Src/stm32l0xx_hal_msp.c **** DBG( __HAL_FLASH_SLEEP_POWERDOWN_DISABLE(); ); + 109:./Src/stm32l0xx_hal_msp.c **** + 110:./Src/stm32l0xx_hal_msp.c **** #ifdef ENABLE_FAST_WAKEUP + 111:./Src/stm32l0xx_hal_msp.c **** /*Enable fast wakeUp*/ + 112:./Src/stm32l0xx_hal_msp.c **** HAL_PWREx_EnableFastWakeUp( ); + 113 .loc 1 112 0 + 114 0020 FFF7FEFF bl HAL_PWREx_EnableFastWakeUp + 115 .LVL7: + 113:./Src/stm32l0xx_hal_msp.c **** #else + 114:./Src/stm32l0xx_hal_msp.c **** HAL_PWREx_DisableFastWakeUp( ); + 115:./Src/stm32l0xx_hal_msp.c **** #endif + 116:./Src/stm32l0xx_hal_msp.c **** } + 116 .loc 1 116 0 + 117 @ sp needed + ARM GAS /tmp/ccbuzBhk.s page 5 + + + 118 0024 10BD pop {r4, pc} + 119 .L5: + 120 0026 C046 .align 2 + 121 .L4: + 122 0028 00100240 .word 1073876992 + 123 002c 00200240 .word 1073881088 + 124 .cfi_endproc + 125 .LFE98: + 127 .section .text.HAL_RTC_MspInit,"ax",%progbits + 128 .align 1 + 129 .global HAL_RTC_MspInit + 130 .syntax unified + 131 .code 16 + 132 .thumb_func + 133 .fpu softvfp + 135 HAL_RTC_MspInit: + 136 .LFB99: + 117:./Src/stm32l0xx_hal_msp.c **** + 118:./Src/stm32l0xx_hal_msp.c **** /** + 119:./Src/stm32l0xx_hal_msp.c **** * @brief RTC MSP Initialization + 120:./Src/stm32l0xx_hal_msp.c **** * This function configures the hardware resources used in this example: + 121:./Src/stm32l0xx_hal_msp.c **** * - Peripheral's clock enable + 122:./Src/stm32l0xx_hal_msp.c **** * @param hrtc: RTC handle pointer + 123:./Src/stm32l0xx_hal_msp.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 124:./Src/stm32l0xx_hal_msp.c **** * the RTC clock source; in this case the Backup domain will be reset in + 125:./Src/stm32l0xx_hal_msp.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 126:./Src/stm32l0xx_hal_msp.c **** * the backup registers) and RCC_CSR register are set to their reset values. + 127:./Src/stm32l0xx_hal_msp.c **** * @retval None + 128:./Src/stm32l0xx_hal_msp.c **** */ + 129:./Src/stm32l0xx_hal_msp.c **** void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) + 130:./Src/stm32l0xx_hal_msp.c **** { + 137 .loc 1 130 0 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 96 + 140 @ frame_needed = 0, uses_anonymous_args = 0 + 141 .LVL8: + 142 0000 00B5 push {lr} + 143 .LCFI3: + 144 .cfi_def_cfa_offset 4 + 145 .cfi_offset 14, -4 + 146 0002 99B0 sub sp, sp, #100 + 147 .LCFI4: + 148 .cfi_def_cfa_offset 104 + 131:./Src/stm32l0xx_hal_msp.c **** RCC_OscInitTypeDef RCC_OscInitStruct; + 132:./Src/stm32l0xx_hal_msp.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + 133:./Src/stm32l0xx_hal_msp.c **** + 134:./Src/stm32l0xx_hal_msp.c **** /*##-1- Configue the RTC clock soucre ######################################*/ + 135:./Src/stm32l0xx_hal_msp.c **** /* -a- Enable LSE Oscillator */ + 136:./Src/stm32l0xx_hal_msp.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + 149 .loc 1 136 0 + 150 0004 0423 movs r3, #4 + 151 0006 0A93 str r3, [sp, #40] + 137:./Src/stm32l0xx_hal_msp.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 152 .loc 1 137 0 + 153 0008 0023 movs r3, #0 + 154 000a 1493 str r3, [sp, #80] + 138:./Src/stm32l0xx_hal_msp.c **** RCC_OscInitStruct.LSEState = RCC_LSE_ON; + ARM GAS /tmp/ccbuzBhk.s page 6 + + + 155 .loc 1 138 0 + 156 000c 0133 adds r3, r3, #1 + 157 000e FF33 adds r3, r3, #255 + 158 0010 0C93 str r3, [sp, #48] + 139:./Src/stm32l0xx_hal_msp.c **** if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 159 .loc 1 139 0 + 160 0012 0AA8 add r0, sp, #40 + 161 .LVL9: + 162 0014 FFF7FEFF bl HAL_RCC_OscConfig + 163 .LVL10: + 164 0018 0028 cmp r0, #0 + 165 001a 19D1 bne .L9 + 166 .L7: + 140:./Src/stm32l0xx_hal_msp.c **** { + 141:./Src/stm32l0xx_hal_msp.c **** Error_Handler(); + 142:./Src/stm32l0xx_hal_msp.c **** } + 143:./Src/stm32l0xx_hal_msp.c **** + 144:./Src/stm32l0xx_hal_msp.c **** /* -b- Select LSI as RTC clock source */ + 145:./Src/stm32l0xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 167 .loc 1 145 0 + 168 001c 2023 movs r3, #32 + 169 001e 0093 str r3, [sp] + 146:./Src/stm32l0xx_hal_msp.c **** PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 170 .loc 1 146 0 + 171 0020 8023 movs r3, #128 + 172 0022 5B02 lsls r3, r3, #9 + 173 0024 0193 str r3, [sp, #4] + 147:./Src/stm32l0xx_hal_msp.c **** if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 174 .loc 1 147 0 + 175 0026 6846 mov r0, sp + 176 0028 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 177 .LVL11: + 178 002c 0028 cmp r0, #0 + 179 002e 14D1 bne .L10 + 180 .L8: + 148:./Src/stm32l0xx_hal_msp.c **** { + 149:./Src/stm32l0xx_hal_msp.c **** Error_Handler(); + 150:./Src/stm32l0xx_hal_msp.c **** } + 151:./Src/stm32l0xx_hal_msp.c **** + 152:./Src/stm32l0xx_hal_msp.c **** /*##-2- Enable the RTC peripheral Clock ####################################*/ + 153:./Src/stm32l0xx_hal_msp.c **** /* Enable RTC Clock */ + 154:./Src/stm32l0xx_hal_msp.c **** __HAL_RCC_RTC_ENABLE(); + 181 .loc 1 154 0 + 182 0030 0C4A ldr r2, .L11 + 183 0032 116D ldr r1, [r2, #80] + 184 0034 8023 movs r3, #128 + 185 0036 DB02 lsls r3, r3, #11 + 186 0038 0B43 orrs r3, r1 + 187 003a 1365 str r3, [r2, #80] + 155:./Src/stm32l0xx_hal_msp.c **** + 156:./Src/stm32l0xx_hal_msp.c **** /*##-3- Configure the NVIC for RTC Alarm ###################################*/ + 157:./Src/stm32l0xx_hal_msp.c **** HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0x0, 0); + 188 .loc 1 157 0 + 189 003c 0022 movs r2, #0 + 190 003e 0021 movs r1, #0 + 191 0040 0220 movs r0, #2 + 192 0042 FFF7FEFF bl HAL_NVIC_SetPriority + ARM GAS /tmp/ccbuzBhk.s page 7 + + + 193 .LVL12: + 158:./Src/stm32l0xx_hal_msp.c **** HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + 194 .loc 1 158 0 + 195 0046 0220 movs r0, #2 + 196 0048 FFF7FEFF bl HAL_NVIC_EnableIRQ + 197 .LVL13: + 159:./Src/stm32l0xx_hal_msp.c **** } + 198 .loc 1 159 0 + 199 004c 19B0 add sp, sp, #100 + 200 @ sp needed + 201 004e 00BD pop {pc} + 202 .L9: + 141:./Src/stm32l0xx_hal_msp.c **** } + 203 .loc 1 141 0 + 204 0050 8D21 movs r1, #141 + 205 0052 0548 ldr r0, .L11+4 + 206 0054 FFF7FEFF bl _Error_Handler + 207 .LVL14: + 208 0058 E0E7 b .L7 + 209 .L10: + 149:./Src/stm32l0xx_hal_msp.c **** } + 210 .loc 1 149 0 + 211 005a 9521 movs r1, #149 + 212 005c 0248 ldr r0, .L11+4 + 213 005e FFF7FEFF bl _Error_Handler + 214 .LVL15: + 215 0062 E5E7 b .L8 + 216 .L12: + 217 .align 2 + 218 .L11: + 219 0064 00100240 .word 1073876992 + 220 0068 00000000 .word .LC0 + 221 .cfi_endproc + 222 .LFE99: + 224 .section .text.HAL_RTC_MspDeInit,"ax",%progbits + 225 .align 1 + 226 .global HAL_RTC_MspDeInit + 227 .syntax unified + 228 .code 16 + 229 .thumb_func + 230 .fpu softvfp + 232 HAL_RTC_MspDeInit: + 233 .LFB100: + 160:./Src/stm32l0xx_hal_msp.c **** + 161:./Src/stm32l0xx_hal_msp.c **** /** + 162:./Src/stm32l0xx_hal_msp.c **** * @brief RTC MSP De-Initialization + 163:./Src/stm32l0xx_hal_msp.c **** * This function freeze the hardware resources used in this example: + 164:./Src/stm32l0xx_hal_msp.c **** * - Disable the Peripheral's clock + 165:./Src/stm32l0xx_hal_msp.c **** * @param hrtc: RTC handle pointer + 166:./Src/stm32l0xx_hal_msp.c **** * @retval None + 167:./Src/stm32l0xx_hal_msp.c **** */ + 168:./Src/stm32l0xx_hal_msp.c **** void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) + 169:./Src/stm32l0xx_hal_msp.c **** { + 234 .loc 1 169 0 + 235 .cfi_startproc + 236 @ args = 0, pretend = 0, frame = 0 + 237 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccbuzBhk.s page 8 + + + 238 @ link register save eliminated. + 239 .LVL16: + 170:./Src/stm32l0xx_hal_msp.c **** /* Reset peripherals */ + 171:./Src/stm32l0xx_hal_msp.c **** __HAL_RCC_RTC_DISABLE(); + 240 .loc 1 171 0 + 241 0000 024A ldr r2, .L14 + 242 0002 136D ldr r3, [r2, #80] + 243 0004 0249 ldr r1, .L14+4 + 244 0006 0B40 ands r3, r1 + 245 0008 1365 str r3, [r2, #80] + 172:./Src/stm32l0xx_hal_msp.c **** } + 246 .loc 1 172 0 + 247 @ sp needed + 248 000a 7047 bx lr + 249 .L15: + 250 .align 2 + 251 .L14: + 252 000c 00100240 .word 1073876992 + 253 0010 FFFFFBFF .word -262145 + 254 .cfi_endproc + 255 .LFE100: + 257 .section .text.HAL_RTC_AlarmAEventCallback,"ax",%progbits + 258 .align 1 + 259 .global HAL_RTC_AlarmAEventCallback + 260 .syntax unified + 261 .code 16 + 262 .thumb_func + 263 .fpu softvfp + 265 HAL_RTC_AlarmAEventCallback: + 266 .LFB101: + 173:./Src/stm32l0xx_hal_msp.c **** + 174:./Src/stm32l0xx_hal_msp.c **** + 175:./Src/stm32l0xx_hal_msp.c **** /** + 176:./Src/stm32l0xx_hal_msp.c **** * @brief Alarm A callback. + 177:./Src/stm32l0xx_hal_msp.c **** * @param hrtc: RTC handle + 178:./Src/stm32l0xx_hal_msp.c **** * @retval None + 179:./Src/stm32l0xx_hal_msp.c **** */ + 180:./Src/stm32l0xx_hal_msp.c **** void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) + 181:./Src/stm32l0xx_hal_msp.c **** { + 267 .loc 1 181 0 + 268 .cfi_startproc + 269 @ args = 0, pretend = 0, frame = 0 + 270 @ frame_needed = 0, uses_anonymous_args = 0 + 271 .LVL17: + 272 0000 10B5 push {r4, lr} + 273 .LCFI5: + 274 .cfi_def_cfa_offset 8 + 275 .cfi_offset 4, -8 + 276 .cfi_offset 14, -4 + 182:./Src/stm32l0xx_hal_msp.c **** TimerIrqHandler( ); + 277 .loc 1 182 0 + 278 0002 FFF7FEFF bl TimerIrqHandler + 279 .LVL18: + 183:./Src/stm32l0xx_hal_msp.c **** } + 280 .loc 1 183 0 + 281 @ sp needed + 282 0006 10BD pop {r4, pc} + ARM GAS /tmp/ccbuzBhk.s page 9 + + + 283 .cfi_endproc + 284 .LFE101: + 286 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 287 .align 1 + 288 .global HAL_GPIO_EXTI_Callback + 289 .syntax unified + 290 .code 16 + 291 .thumb_func + 292 .fpu softvfp + 294 HAL_GPIO_EXTI_Callback: + 295 .LFB102: + 184:./Src/stm32l0xx_hal_msp.c **** + 185:./Src/stm32l0xx_hal_msp.c **** /** + 186:./Src/stm32l0xx_hal_msp.c **** * @brief EXTI line detection callbacks. + 187:./Src/stm32l0xx_hal_msp.c **** * @param GPIO_Pin: Specifies the pins connected to the EXTI line. + 188:./Src/stm32l0xx_hal_msp.c **** * @retval None + 189:./Src/stm32l0xx_hal_msp.c **** */ + 190:./Src/stm32l0xx_hal_msp.c **** void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 191:./Src/stm32l0xx_hal_msp.c **** { + 296 .loc 1 191 0 + 297 .cfi_startproc + 298 @ args = 0, pretend = 0, frame = 0 + 299 @ frame_needed = 0, uses_anonymous_args = 0 + 300 .LVL19: + 301 0000 10B5 push {r4, lr} + 302 .LCFI6: + 303 .cfi_def_cfa_offset 8 + 304 .cfi_offset 4, -8 + 305 .cfi_offset 14, -4 + 192:./Src/stm32l0xx_hal_msp.c **** HW_GPIO_IrqHandler( GPIO_Pin ); + 306 .loc 1 192 0 + 307 0002 FFF7FEFF bl HW_GPIO_IrqHandler + 308 .LVL20: + 193:./Src/stm32l0xx_hal_msp.c **** } + 309 .loc 1 193 0 + 310 @ sp needed + 311 0006 10BD pop {r4, pc} + 312 .cfi_endproc + 313 .LFE102: + 315 .section .text.MSP_GetIRQn,"ax",%progbits + 316 .align 1 + 317 .global MSP_GetIRQn + 318 .syntax unified + 319 .code 16 + 320 .thumb_func + 321 .fpu softvfp + 323 MSP_GetIRQn: + 324 .LFB103: + 194:./Src/stm32l0xx_hal_msp.c **** + 195:./Src/stm32l0xx_hal_msp.c **** /** + 196:./Src/stm32l0xx_hal_msp.c **** * @brief Gets IRQ number as a function of the GPIO_Pin. + 197:./Src/stm32l0xx_hal_msp.c **** * @param GPIO_Pin: Specifies the pins connected to the EXTI line. + 198:./Src/stm32l0xx_hal_msp.c **** * @retval IRQ number + 199:./Src/stm32l0xx_hal_msp.c **** */ + 200:./Src/stm32l0xx_hal_msp.c **** IRQn_Type MSP_GetIRQn( uint16_t GPIO_Pin) + 201:./Src/stm32l0xx_hal_msp.c **** { + 325 .loc 1 201 0 + ARM GAS /tmp/ccbuzBhk.s page 10 + + + 326 .cfi_startproc + 327 @ args = 0, pretend = 0, frame = 0 + 328 @ frame_needed = 0, uses_anonymous_args = 0 + 329 @ link register save eliminated. + 330 .LVL21: + 202:./Src/stm32l0xx_hal_msp.c **** switch( GPIO_Pin ) + 331 .loc 1 202 0 + 332 0000 0428 cmp r0, #4 + 333 0002 09D0 beq .L23 + 334 0004 04D8 bhi .L21 + 335 0006 0138 subs r0, r0, #1 + 336 .LVL22: + 337 0008 0128 cmp r0, #1 + 338 000a 03D8 bhi .L19 + 203:./Src/stm32l0xx_hal_msp.c **** { + 204:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_0: + 205:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_1: return EXTI0_1_IRQn; + 339 .loc 1 205 0 + 340 000c 0520 movs r0, #5 + 341 .L20: + 206:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_2: + 207:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_3: return EXTI2_3_IRQn; + 208:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_4: + 209:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_5: + 210:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_6: + 211:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_7: + 212:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_8: + 213:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_9: + 214:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_10: + 215:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_11: + 216:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_12: + 217:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_13: + 218:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_14: + 219:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_15: + 220:./Src/stm32l0xx_hal_msp.c **** default: return EXTI4_15_IRQn; + 221:./Src/stm32l0xx_hal_msp.c **** } + 222:./Src/stm32l0xx_hal_msp.c **** } + 342 .loc 1 222 0 + 343 @ sp needed + 344 000e 7047 bx lr + 345 .LVL23: + 346 .L21: + 202:./Src/stm32l0xx_hal_msp.c **** { + 347 .loc 1 202 0 + 348 0010 0828 cmp r0, #8 + 349 0012 01D0 beq .L23 + 350 .LVL24: + 351 .L19: + 220:./Src/stm32l0xx_hal_msp.c **** } + 352 .loc 1 220 0 + 353 0014 0720 movs r0, #7 + 354 0016 FAE7 b .L20 + 355 .LVL25: + 356 .L23: + 207:./Src/stm32l0xx_hal_msp.c **** case GPIO_PIN_4: + 357 .loc 1 207 0 + 358 0018 0620 movs r0, #6 + ARM GAS /tmp/ccbuzBhk.s page 11 + + + 359 .LVL26: + 360 001a F8E7 b .L20 + 361 .cfi_endproc + 362 .LFE103: + 364 .section .rodata.HAL_RTC_MspInit.str1.4,"aMS",%progbits,1 + 365 .align 2 + 366 .LC0: + 367 0000 2E2F5372 .ascii "./Src/stm32l0xx_hal_msp.c\000" + 367 632F7374 + 367 6D33326C + 367 3078785F + 367 68616C5F + 368 .text + 369 .Letext0: + 370 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 371 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 372 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 373 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 374 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 375 .file 7 "/usr/arm-none-eabi/include/math.h" + 376 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 377 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 378 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 379 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 380 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h" + 381 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h" + 382 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h" + 383 .file 15 "Inc/hw_gpio.h" + 384 .file 16 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + 385 .file 17 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + 386 .file 18 "Inc/debug.h" + 387 .file 19 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h" + 388 .file 20 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h" + 389 .file 21 "Middlewares/Third_Party/Lora/Utilities/delay.h" + ARM GAS /tmp/ccbuzBhk.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_msp.c + /tmp/ccbuzBhk.s:16 .text.HAL_InitTick:0000000000000000 $t + /tmp/ccbuzBhk.s:23 .text.HAL_InitTick:0000000000000000 HAL_InitTick + /tmp/ccbuzBhk.s:41 .text.HAL_Delay:0000000000000000 $t + /tmp/ccbuzBhk.s:48 .text.HAL_Delay:0000000000000000 HAL_Delay + /tmp/ccbuzBhk.s:76 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccbuzBhk.s:83 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccbuzBhk.s:122 .text.HAL_MspInit:0000000000000028 $d + /tmp/ccbuzBhk.s:128 .text.HAL_RTC_MspInit:0000000000000000 $t + /tmp/ccbuzBhk.s:135 .text.HAL_RTC_MspInit:0000000000000000 HAL_RTC_MspInit + /tmp/ccbuzBhk.s:219 .text.HAL_RTC_MspInit:0000000000000064 $d + /tmp/ccbuzBhk.s:225 .text.HAL_RTC_MspDeInit:0000000000000000 $t + /tmp/ccbuzBhk.s:232 .text.HAL_RTC_MspDeInit:0000000000000000 HAL_RTC_MspDeInit + /tmp/ccbuzBhk.s:252 .text.HAL_RTC_MspDeInit:000000000000000c $d + /tmp/ccbuzBhk.s:258 .text.HAL_RTC_AlarmAEventCallback:0000000000000000 $t + /tmp/ccbuzBhk.s:265 .text.HAL_RTC_AlarmAEventCallback:0000000000000000 HAL_RTC_AlarmAEventCallback + /tmp/ccbuzBhk.s:287 .text.HAL_GPIO_EXTI_Callback:0000000000000000 $t + /tmp/ccbuzBhk.s:294 .text.HAL_GPIO_EXTI_Callback:0000000000000000 HAL_GPIO_EXTI_Callback + /tmp/ccbuzBhk.s:316 .text.MSP_GetIRQn:0000000000000000 $t + /tmp/ccbuzBhk.s:323 .text.MSP_GetIRQn:0000000000000000 MSP_GetIRQn + /tmp/ccbuzBhk.s:365 .rodata.HAL_RTC_MspInit.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +DelayMs +HAL_PWR_DisablePVD +HAL_PWREx_EnableUltraLowPower +HAL_PWREx_EnableFastWakeUp +HAL_RCC_OscConfig +HAL_RCCEx_PeriphCLKConfig +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +_Error_Handler +TimerIrqHandler +HW_GPIO_IrqHandler diff --git a/build/stm32l0xx_hal_pcd.d b/build/stm32l0xx_hal_pcd.d new file mode 100644 index 0000000..fd23715 --- /dev/null +++ b/build/stm32l0xx_hal_pcd.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_pcd.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_pcd.lst b/build/stm32l0xx_hal_pcd.lst new file mode 100644 index 0000000..13cc5f8 --- /dev/null +++ b/build/stm32l0xx_hal_pcd.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccRd2IQL.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_pcd.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccRd2IQL.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_pcd.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_pcd_ex.d b/build/stm32l0xx_hal_pcd_ex.d new file mode 100644 index 0000000..12dfdc1 --- /dev/null +++ b/build/stm32l0xx_hal_pcd_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_pcd_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_pcd_ex.lst b/build/stm32l0xx_hal_pcd_ex.lst new file mode 100644 index 0000000..26cda4a --- /dev/null +++ b/build/stm32l0xx_hal_pcd_ex.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccMFCrZT.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_pcd_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccMFCrZT.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_pcd_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_pwr.d b/build/stm32l0xx_hal_pwr.d new file mode 100644 index 0000000..dd3a5d6 --- /dev/null +++ b/build/stm32l0xx_hal_pwr.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_pwr.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_pwr.lst b/build/stm32l0xx_hal_pwr.lst new file mode 100644 index 0000000..d149f4b --- /dev/null +++ b/build/stm32l0xx_hal_pwr.lst @@ -0,0 +1,2041 @@ +ARM GAS /tmp/ccnH7zer.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_pwr.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_PWR_DeInit,"ax",%progbits + 16 .align 1 + 17 .global HAL_PWR_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_PWR_DeInit: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @file stm32l0xx_hal_pwr.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief PWR HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This file provides firmware functions to manage the following + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + Initialization/de-initialization functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + Peripheral Control functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ****************************************************************************** + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @attention + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Redistribution and use in source and binary forms, with or without modification, + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * are permitted provided that the following conditions are met: + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 1. Redistributions of source code must retain the above copyright notice, + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * this list of conditions and the following disclaimer. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * this list of conditions and the following disclaimer in the documentation + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * and/or other materials provided with the distribution. + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * may be used to endorse or promote products derived from this software + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * without specific prior written permission. + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + ARM GAS /tmp/ccnH7zer.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ****************************************************************************** + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #include "stm32l0xx_hal.h" + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup STM32L0xx_HAL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Private + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_MODE_IT ((uint32_t)0x00010000U) + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_MODE_EVT ((uint32_t)0x00020000U) + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_RISING_EDGE ((uint32_t)0x00000001U) + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_FALLING_EDGE ((uint32_t)0x00000002U) + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @} + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @} + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group1 + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Initialization and de-initialization functions + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @verbatim + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =============================================================================== + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =============================================================================== + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @endverbatim + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + ARM GAS /tmp/ccnH7zer.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DeInit(void) + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 26 .loc 1 95 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); + 31 .loc 1 96 0 + 32 0000 054B ldr r3, .L2 + 33 0002 996A ldr r1, [r3, #40] + 34 0004 8022 movs r2, #128 + 35 0006 5205 lsls r2, r2, #21 + 36 0008 0A43 orrs r2, r1 + 37 000a 9A62 str r2, [r3, #40] + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); + 38 .loc 1 97 0 + 39 000c 9A6A ldr r2, [r3, #40] + 40 000e 0349 ldr r1, .L2+4 + 41 0010 0A40 ands r2, r1 + 42 0012 9A62 str r2, [r3, #40] + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 43 .loc 1 98 0 + 44 @ sp needed + 45 0014 7047 bx lr + 46 .L3: + 47 0016 C046 .align 2 + 48 .L2: + 49 0018 00100240 .word 1073876992 + 50 001c FFFFFFEF .word -268435457 + 51 .cfi_endproc + 52 .LFE39: + 54 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 55 .align 1 + 56 .global HAL_PWR_EnableBkUpAccess + 57 .syntax unified + 58 .code 16 + 59 .thumb_func + 60 .fpu softvfp + 62 HAL_PWR_EnableBkUpAccess: + 63 .LFB40: + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @} + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group2 + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Low Power modes configuration functions + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @verbatim + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =============================================================================== + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ##### Peripheral Control functions ##### + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =============================================================================== + ARM GAS /tmp/ccnH7zer.s page 4 + + + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Backup domain *** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ========================= + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** registers) is protected against possible unwanted + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** write accesses. + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** PVD configuration *** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ========================= + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD can use an external input analog voltage (PVD_IN) which is compared + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** WakeUp pin configuration *** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================================ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) There are two WakeUp pins: + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 1 on PA.00. + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 2 on PC.13. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 3 on PE.06 . + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Main and Backup Regulators configuration *** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================================================ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The main internal regulator can be configured to have a tradeoff between + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** performance and power consumption when the device does not operate at + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** macro which configures the two VOS bits in PWR_CR register: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mod + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 32 MHz. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mod + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 16 MHz. + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mod + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 4.2 MHz. + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Refer to the datasheets for more details. + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low Power modes configuration *** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ===================================== + ARM GAS /tmp/ccnH7zer.s page 5 + + + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The device features 5 low-power modes: + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Low power run mode: regulator in low power mode, limited clock frequency, + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** limited number of peripherals running. + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running. + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency, + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** limited number of peripherals running, regulator in low power mode. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Standby mode: VCORE domain powered off + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low power run mode *** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ========================= + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To further reduce the consumption when the system is in Run mode, the regulator can be + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** configured in low power mode. In this mode, the system frequency should not exceed + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** MSI frequency range1. + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Low power run mode, all I/O pins keep the same state as in Run mode. + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry: + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) VCORE in range2 + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1. + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function. + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit: + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunM + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function. + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Increase the system frequency if needed. + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Sleep mode *** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================== + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions with + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit: + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the MCU exits Sleep mode as soon as an event occurs. + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low power sleep mode *** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ============================ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry: + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGUL + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions with + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_AC + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** This reduces power consumption but increases the wake-up time. + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit: + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrup + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** acknowledged by the nested vectored interrupt controller (NVIC) can wake up the devic + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** from Low power sleep mode. If the WFE instruction was used to enter Low power sleep m + ARM GAS /tmp/ccnH7zer.s page 6 + + + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the MCU exits Sleep mode as soon as an event occurs. + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Stop mode *** + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================= + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** clock gating. The voltage regulator can be configured either in normal or low-power mode. + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To get the lowest consumption in Stop mode, the internal Flash memory also enters low + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** power mode. When the Flash memory is in power-down mode, an additional startup delay is + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** incurred when waking up from Stop mode. + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** sensor can be switched off before entering Stop mode. They can be switched on again by + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** software after exiting Stop mode using the ULP bit in the PWR_CR register. + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Stop mode, all I/O pins keep the same state as in Run mode. + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry: + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function with: + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Main regulator ON. + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Low Power regulator ON. + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit: + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** register + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Standby mode *** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ==================== + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based on the + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** also switched off. SRAM and register contents are lost except for the RTC registers, RTC + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** backup registers and Standby circuitry. + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** sensor can be switched off before entering the Standby mode. They can be switched + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** on again by software after exiting the Standby mode. + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function. + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry: + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit: + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ============================================= + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..] + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event, + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode). + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop mode + ARM GAS /tmp/ccnH7zer.s page 7 + + + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function. + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and RTC_AlarmCmd() functions. + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** is necessary to: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function. + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function. + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to detect the tamper or time stamp event using the + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions. + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function. + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConf + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Standby mode + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and RTC_AlarmCmd() functions. + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** is necessary to: + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to detect the tamper or time stamp event using the + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions. + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConf + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** event, it is necessary to: + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function. + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the comparator to generate the event. + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @endverbatim + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * backup data registers ). + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + ARM GAS /tmp/ccnH7zer.s page 8 + + + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 64 .loc 1 341 0 + 65 .cfi_startproc + 66 @ args = 0, pretend = 0, frame = 0 + 67 @ frame_needed = 0, uses_anonymous_args = 0 + 68 @ link register save eliminated. + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable access to RTC and backup registers */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 69 .loc 1 343 0 + 70 0000 034A ldr r2, .L5 + 71 0002 1168 ldr r1, [r2] + 72 0004 8023 movs r3, #128 + 73 0006 5B00 lsls r3, r3, #1 + 74 0008 0B43 orrs r3, r1 + 75 000a 1360 str r3, [r2] + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 76 .loc 1 344 0 + 77 @ sp needed + 78 000c 7047 bx lr + 79 .L6: + 80 000e C046 .align 2 + 81 .L5: + 82 0010 00700040 .word 1073770496 + 83 .cfi_endproc + 84 .LFE40: + 86 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 87 .align 1 + 88 .global HAL_PWR_DisableBkUpAccess + 89 .syntax unified + 90 .code 16 + 91 .thumb_func + 92 .fpu softvfp + 94 HAL_PWR_DisableBkUpAccess: + 95 .LFB41: + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables access to the backup domain + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Applies to RTC registers, RTC backup data registers. + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 96 .loc 1 354 0 + 97 .cfi_startproc + 98 @ args = 0, pretend = 0, frame = 0 + 99 @ frame_needed = 0, uses_anonymous_args = 0 + 100 @ link register save eliminated. + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable access to RTC and backup registers */ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP); + 101 .loc 1 356 0 + 102 0000 024A ldr r2, .L8 + 103 0002 1368 ldr r3, [r2] + 104 0004 0249 ldr r1, .L8+4 + 105 0006 0B40 ands r3, r1 + ARM GAS /tmp/ccnH7zer.s page 9 + + + 106 0008 1360 str r3, [r2] + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 107 .loc 1 357 0 + 108 @ sp needed + 109 000a 7047 bx lr + 110 .L9: + 111 .align 2 + 112 .L8: + 113 000c 00700040 .word 1073770496 + 114 0010 FFFEFFFF .word -257 + 115 .cfi_endproc + 116 .LFE41: + 118 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits + 119 .align 1 + 120 .global HAL_PWR_ConfigPVD + 121 .syntax unified + 122 .code 16 + 123 .thumb_func + 124 .fpu softvfp + 126 HAL_PWR_ConfigPVD: + 127 .LFB42: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * information for the PVD. + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * detection level. + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 128 .loc 1 369 0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 133 .LVL0: + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + 134 .loc 1 375 0 + 135 0000 1C4A ldr r2, .L15 + 136 0002 1368 ldr r3, [r2] + 137 0004 E021 movs r1, #224 + 138 0006 8B43 bics r3, r1 + 139 0008 0168 ldr r1, [r0] + 140 000a 0B43 orrs r3, r1 + 141 000c 1360 str r3, [r2] + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + 142 .loc 1 378 0 + ARM GAS /tmp/ccnH7zer.s page 10 + + + 143 000e 1A4B ldr r3, .L15+4 + 144 0010 5968 ldr r1, [r3, #4] + 145 0012 1A4A ldr r2, .L15+8 + 146 0014 1140 ands r1, r2 + 147 0016 5960 str r1, [r3, #4] + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); + 148 .loc 1 379 0 + 149 0018 1968 ldr r1, [r3] + 150 001a 1140 ands r1, r2 + 151 001c 1960 str r1, [r3] + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + 152 .loc 1 380 0 + 153 001e D968 ldr r1, [r3, #12] + 154 0020 1140 ands r1, r2 + 155 0022 D960 str r1, [r3, #12] + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + 156 .loc 1 381 0 + 157 0024 9968 ldr r1, [r3, #8] + 158 0026 0A40 ands r2, r1 + 159 0028 9A60 str r2, [r3, #8] + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure interrupt mode */ + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 160 .loc 1 384 0 + 161 002a 4368 ldr r3, [r0, #4] + 162 002c DB03 lsls r3, r3, #15 + 163 002e 05D5 bpl .L11 + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); + 164 .loc 1 386 0 + 165 0030 114A ldr r2, .L15+4 + 166 0032 1168 ldr r1, [r2] + 167 0034 8023 movs r3, #128 + 168 0036 5B02 lsls r3, r3, #9 + 169 0038 0B43 orrs r3, r1 + 170 003a 1360 str r3, [r2] + 171 .L11: + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure event mode */ + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 172 .loc 1 390 0 + 173 003c 4368 ldr r3, [r0, #4] + 174 003e 9B03 lsls r3, r3, #14 + 175 0040 05D5 bpl .L12 + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + 176 .loc 1 392 0 + 177 0042 0D4A ldr r2, .L15+4 + 178 0044 5168 ldr r1, [r2, #4] + 179 0046 8023 movs r3, #128 + 180 0048 5B02 lsls r3, r3, #9 + 181 004a 0B43 orrs r3, r1 + 182 004c 5360 str r3, [r2, #4] + 183 .L12: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + ARM GAS /tmp/ccnH7zer.s page 11 + + + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure the edge */ + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 184 .loc 1 396 0 + 185 004e 4368 ldr r3, [r0, #4] + 186 0050 DB07 lsls r3, r3, #31 + 187 0052 05D5 bpl .L13 + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + 188 .loc 1 398 0 + 189 0054 084A ldr r2, .L15+4 + 190 0056 9168 ldr r1, [r2, #8] + 191 0058 8023 movs r3, #128 + 192 005a 5B02 lsls r3, r3, #9 + 193 005c 0B43 orrs r3, r1 + 194 005e 9360 str r3, [r2, #8] + 195 .L13: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 196 .loc 1 401 0 + 197 0060 4368 ldr r3, [r0, #4] + 198 0062 9B07 lsls r3, r3, #30 + 199 0064 05D5 bpl .L10 + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + 200 .loc 1 403 0 + 201 0066 044A ldr r2, .L15+4 + 202 0068 D168 ldr r1, [r2, #12] + 203 006a 8023 movs r3, #128 + 204 006c 5B02 lsls r3, r3, #9 + 205 006e 0B43 orrs r3, r1 + 206 0070 D360 str r3, [r2, #12] + 207 .L10: + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 208 .loc 1 405 0 + 209 @ sp needed + 210 0072 7047 bx lr + 211 .L16: + 212 .align 2 + 213 .L15: + 214 0074 00700040 .word 1073770496 + 215 0078 00040140 .word 1073808384 + 216 007c FFFFFEFF .word -65537 + 217 .cfi_endproc + 218 .LFE42: + 220 .section .text.HAL_PWR_EnablePVD,"ax",%progbits + 221 .align 1 + 222 .global HAL_PWR_EnablePVD + 223 .syntax unified + 224 .code 16 + 225 .thumb_func + 226 .fpu softvfp + 228 HAL_PWR_EnablePVD: + 229 .LFB43: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + ARM GAS /tmp/ccnH7zer.s page 12 + + + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 230 .loc 1 412 0 + 231 .cfi_startproc + 232 @ args = 0, pretend = 0, frame = 0 + 233 @ frame_needed = 0, uses_anonymous_args = 0 + 234 @ link register save eliminated. + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable the power voltage detector */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PVDE); + 235 .loc 1 414 0 + 236 0000 024A ldr r2, .L18 + 237 0002 1368 ldr r3, [r2] + 238 0004 1021 movs r1, #16 + 239 0006 0B43 orrs r3, r1 + 240 0008 1360 str r3, [r2] + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 241 .loc 1 415 0 + 242 @ sp needed + 243 000a 7047 bx lr + 244 .L19: + 245 .align 2 + 246 .L18: + 247 000c 00700040 .word 1073770496 + 248 .cfi_endproc + 249 .LFE43: + 251 .section .text.HAL_PWR_DisablePVD,"ax",%progbits + 252 .align 1 + 253 .global HAL_PWR_DisablePVD + 254 .syntax unified + 255 .code 16 + 256 .thumb_func + 257 .fpu softvfp + 259 HAL_PWR_DisablePVD: + 260 .LFB44: + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 261 .loc 1 422 0 + 262 .cfi_startproc + 263 @ args = 0, pretend = 0, frame = 0 + 264 @ frame_needed = 0, uses_anonymous_args = 0 + 265 @ link register save eliminated. + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable the power voltage detector */ + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_PVDE); + 266 .loc 1 424 0 + 267 0000 024A ldr r2, .L21 + 268 0002 1368 ldr r3, [r2] + 269 0004 1021 movs r1, #16 + 270 0006 8B43 bics r3, r1 + 271 0008 1360 str r3, [r2] + ARM GAS /tmp/ccnH7zer.s page 13 + + + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 272 .loc 1 425 0 + 273 @ sp needed + 274 000a 7047 bx lr + 275 .L22: + 276 .align 2 + 277 .L21: + 278 000c 00700040 .word 1073770496 + 279 .cfi_endproc + 280 .LFE44: + 282 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 283 .align 1 + 284 .global HAL_PWR_EnableWakeUpPin + 285 .syntax unified + 286 .code 16 + 287 .thumb_func + 288 .fpu softvfp + 290 HAL_PWR_EnableWakeUpPin: + 291 .LFB45: + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality. + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 292 .loc 1 437 0 + 293 .cfi_startproc + 294 @ args = 0, pretend = 0, frame = 0 + 295 @ frame_needed = 0, uses_anonymous_args = 0 + 296 @ link register save eliminated. + 297 .LVL1: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameter */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable the EWUPx pin */ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); + 298 .loc 1 441 0 + 299 0000 024A ldr r2, .L24 + 300 0002 5368 ldr r3, [r2, #4] + 301 0004 1843 orrs r0, r3 + 302 .LVL2: + 303 0006 5060 str r0, [r2, #4] + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 304 .loc 1 442 0 + 305 @ sp needed + 306 0008 7047 bx lr + 307 .L25: + 308 000a C046 .align 2 + 309 .L24: + 310 000c 00700040 .word 1073770496 + 311 .cfi_endproc + 312 .LFE45: + ARM GAS /tmp/ccnH7zer.s page 14 + + + 314 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 315 .align 1 + 316 .global HAL_PWR_DisableWakeUpPin + 317 .syntax unified + 318 .code 16 + 319 .thumb_func + 320 .fpu softvfp + 322 HAL_PWR_DisableWakeUpPin: + 323 .LFB46: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality. + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 324 .loc 1 454 0 + 325 .cfi_startproc + 326 @ args = 0, pretend = 0, frame = 0 + 327 @ frame_needed = 0, uses_anonymous_args = 0 + 328 @ link register save eliminated. + 329 .LVL3: + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameter */ + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable the EWUPx pin */ + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); + 330 .loc 1 458 0 + 331 0000 024A ldr r2, .L27 + 332 0002 5368 ldr r3, [r2, #4] + 333 0004 8343 bics r3, r0 + 334 0006 5360 str r3, [r2, #4] + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 335 .loc 1 459 0 + 336 @ sp needed + 337 0008 7047 bx lr + 338 .L28: + 339 000a C046 .align 2 + 340 .L27: + 341 000c 00700040 .word 1073770496 + 342 .cfi_endproc + 343 .LFE46: + 345 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 346 .align 1 + 347 .global HAL_PWR_EnterSLEEPMode + 348 .syntax unified + 349 .code 16 + 350 .thumb_func + 351 .fpu softvfp + 353 HAL_PWR_EnterSLEEPMode: + 354 .LFB47: + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + ARM GAS /tmp/ccnH7zer.s page 15 + + + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Sleep mode. + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in SLEEP mode. + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * the interrupt wake up source. + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 355 .loc 1 477 0 + 356 .cfi_startproc + 357 @ args = 0, pretend = 0, frame = 0 + 358 @ frame_needed = 0, uses_anonymous_args = 0 + 359 .LVL4: + 360 0000 10B5 push {r4, lr} + 361 .LCFI0: + 362 .cfi_def_cfa_offset 8 + 363 .cfi_offset 4, -8 + 364 .cfi_offset 14, -4 + 365 .LVL5: + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** uint32_t tmpreg = 0U; + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */ + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select the regulator state in Sleep mode ---------------------------------*/ + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tmpreg = PWR->CR; + 366 .loc 1 484 0 + 367 0002 094A ldr r2, .L33 + 368 0004 1368 ldr r3, [r2] + 369 .LVL6: + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */ + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); + 370 .loc 1 487 0 + 371 0006 0324 movs r4, #3 + 372 0008 A343 bics r3, r4 + 373 .LVL7: + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set LPSDSR bit according to PWR_Regulator value */ + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(tmpreg, Regulator); + 374 .loc 1 490 0 + 375 000a 1843 orrs r0, r3 + 376 .LVL8: + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Store the new value */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** PWR->CR = tmpreg; + 377 .loc 1 493 0 + 378 000c 1060 str r0, [r2] + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + ARM GAS /tmp/ccnH7zer.s page 16 + + + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 379 .loc 1 496 0 + 380 000e 074A ldr r2, .L33+4 + 381 0010 1369 ldr r3, [r2, #16] + 382 0012 0420 movs r0, #4 + 383 .LVL9: + 384 0014 8343 bics r3, r0 + 385 0016 1361 str r3, [r2, #16] + 386 .LVL10: + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + 387 .loc 1 499 0 + 388 0018 0129 cmp r1, #1 + 389 001a 03D0 beq .L32 + 390 .LBB20: + 391 .LBB21: + 392 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + ARM GAS /tmp/ccnH7zer.s page 17 + + + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccnH7zer.s page 18 + + + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + ARM GAS /tmp/ccnH7zer.s page 19 + + + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + ARM GAS /tmp/ccnH7zer.s page 20 + + + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccnH7zer.s page 21 + + + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */ + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccnH7zer.s page 22 + + + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0); + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop"); + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + ARM GAS /tmp/ccnH7zer.s page 23 + + + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void) + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfi"); + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void) + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfe"); + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void) + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("sev"); + 393 .loc 2 406 0 + 394 .syntax divided + 395 @ 406 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 396 001c 40BF sev + 397 @ 0 "" 2 + 398 .thumb + 399 .syntax unified + 400 .LBE21: + 401 .LBE20: + 402 .LBB22: + 403 .LBB23: + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404 .loc 2 396 0 + 405 .syntax divided + 406 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 407 001e 20BF wfe + 408 @ 0 "" 2 + 409 .thumb + 410 .syntax unified + 411 .LBE23: + 412 .LBE22: + 413 .LBB24: + 414 .LBB25: + 415 .syntax divided + 416 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 417 0020 20BF wfe + 418 @ 0 "" 2 + 419 .thumb + 420 .syntax unified + 421 .L29: + 422 .LBE25: + ARM GAS /tmp/ccnH7zer.s page 24 + + + 423 .LBE24: + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI(); + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** else + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Event */ + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __SEV(); + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE(); + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE(); + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 424 .loc 1 511 0 + 425 @ sp needed + 426 0022 10BD pop {r4, pc} + 427 .L32: + 428 .LBB26: + 429 .LBB27: + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 430 .loc 2 385 0 + 431 .syntax divided + 432 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 433 0024 30BF wfi + 434 @ 0 "" 2 + 435 .thumb + 436 .syntax unified + 437 0026 FCE7 b .L29 + 438 .L34: + 439 .align 2 + 440 .L33: + 441 0028 00700040 .word 1073770496 + 442 002c 00ED00E0 .word -536810240 + 443 .LBE27: + 444 .LBE26: + 445 .cfi_endproc + 446 .LFE47: + 448 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 449 .align 1 + 450 .global HAL_PWR_EnterSTOPMode + 451 .syntax unified + 452 .code 16 + 453 .thumb_func + 454 .fpu softvfp + 456 HAL_PWR_EnterSTOPMode: + 457 .LFB48: + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Stop mode. + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * MSI or HSI16 RCoscillator is selected as system clock depending + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * the bit STOPWUCK in the RCC_CFGR register. + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * is higher although the startup time is reduced. + ARM GAS /tmp/ccnH7zer.s page 25 + + + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Before entering in this function, it is important to ensure that the WUF + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * wakeup flag is cleared. To perform this action, it is possible to call the + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU) + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode. + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values: + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 458 .loc 1 538 0 + 459 .cfi_startproc + 460 @ args = 0, pretend = 0, frame = 0 + 461 @ frame_needed = 0, uses_anonymous_args = 0 + 462 .LVL11: + 463 0000 10B5 push {r4, lr} + 464 .LCFI1: + 465 .cfi_def_cfa_offset 8 + 466 .cfi_offset 4, -8 + 467 .cfi_offset 14, -4 + 468 .LVL12: + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** uint32_t tmpreg = 0U; + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */ + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select the regulator state in Stop mode ---------------------------------*/ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tmpreg = PWR->CR; + 469 .loc 1 546 0 + 470 0002 0C4A ldr r2, .L39 + 471 0004 1368 ldr r3, [r2] + 472 .LVL13: + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */ + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); + 473 .loc 1 549 0 + 474 0006 0324 movs r4, #3 + 475 0008 A343 bics r3, r4 + 476 .LVL14: + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set LPSDSR bit according to PWR_Regulator value */ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(tmpreg, Regulator); + 477 .loc 1 552 0 + 478 000a 1843 orrs r0, r3 + 479 .LVL15: + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Store the new value */ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** PWR->CR = tmpreg; + 480 .loc 1 555 0 + 481 000c 1060 str r0, [r2] + ARM GAS /tmp/ccnH7zer.s page 26 + + + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 482 .loc 1 558 0 + 483 000e 0A4A ldr r2, .L39+4 + 484 0010 1369 ldr r3, [r2, #16] + 485 0012 0420 movs r0, #4 + 486 .LVL16: + 487 0014 0343 orrs r3, r0 + 488 0016 1361 str r3, [r2, #16] + 489 .LVL17: + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) + 490 .loc 1 561 0 + 491 0018 0129 cmp r1, #1 + 492 001a 08D0 beq .L38 + 493 .LBB28: + 494 .LBB29: + 495 .loc 2 406 0 + 496 .syntax divided + 497 @ 406 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 498 001c 40BF sev + 499 @ 0 "" 2 + 500 .thumb + 501 .syntax unified + 502 .LBE29: + 503 .LBE28: + 504 .LBB30: + 505 .LBB31: + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 506 .loc 2 396 0 + 507 .syntax divided + 508 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 509 001e 20BF wfe + 510 @ 0 "" 2 + 511 .thumb + 512 .syntax unified + 513 .LBE31: + 514 .LBE30: + 515 .LBB32: + 516 .LBB33: + 517 .syntax divided + 518 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 519 0020 20BF wfe + 520 @ 0 "" 2 + 521 .thumb + 522 .syntax unified + 523 .L37: + 524 .LBE33: + 525 .LBE32: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI(); + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** else + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + ARM GAS /tmp/ccnH7zer.s page 27 + + + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Event */ + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __SEV(); + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE(); + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE(); + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 526 .loc 1 575 0 + 527 0022 054A ldr r2, .L39+4 + 528 0024 1369 ldr r3, [r2, #16] + 529 0026 0421 movs r1, #4 + 530 .LVL18: + 531 0028 8B43 bics r3, r1 + 532 002a 1361 str r3, [r2, #16] + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 533 .loc 1 577 0 + 534 @ sp needed + 535 002c 10BD pop {r4, pc} + 536 .LVL19: + 537 .L38: + 538 .LBB34: + 539 .LBB35: + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 540 .loc 2 385 0 + 541 .syntax divided + 542 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 543 002e 30BF wfi + 544 @ 0 "" 2 + 545 .thumb + 546 .syntax unified + 547 0030 F7E7 b .L37 + 548 .L40: + 549 0032 C046 .align 2 + 550 .L39: + 551 0034 00700040 .word 1073770496 + 552 0038 00ED00E0 .word -536810240 + 553 .LBE35: + 554 .LBE34: + 555 .cfi_endproc + 556 .LFE48: + 558 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 559 .align 1 + 560 .global HAL_PWR_EnterSTANDBYMode + 561 .syntax unified + 562 .code 16 + 563 .thumb_func + 564 .fpu softvfp + 566 HAL_PWR_EnterSTANDBYMode: + 567 .LFB49: + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Standby mode. + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - Reset pad (still available) + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + ARM GAS /tmp/ccnH7zer.s page 28 + + + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - RTC_AF2 pin (PC13) if configured for tamper. + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 1 (PA00) if enabled. + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 2 (PC13) if enabled. + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only. + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only. + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 568 .loc 1 593 0 + 569 .cfi_startproc + 570 @ args = 0, pretend = 0, frame = 0 + 571 @ frame_needed = 0, uses_anonymous_args = 0 + 572 @ link register save eliminated. + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select Standby mode */ + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); + 573 .loc 1 595 0 + 574 0000 054A ldr r2, .L42 + 575 0002 1368 ldr r3, [r2] + 576 0004 0221 movs r1, #2 + 577 0006 0B43 orrs r3, r1 + 578 0008 1360 str r3, [r2] + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 579 .loc 1 598 0 + 580 000a 044A ldr r2, .L42+4 + 581 000c 1369 ldr r3, [r2, #16] + 582 000e 0231 adds r1, r1, #2 + 583 0010 0B43 orrs r3, r1 + 584 0012 1361 str r3, [r2, #16] + 585 .LBB36: + 586 .LBB37: + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 587 .loc 2 385 0 + 588 .syntax divided + 589 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 590 0014 30BF wfi + 591 @ 0 "" 2 + 592 .thumb + 593 .syntax unified + 594 .LBE37: + 595 .LBE36: + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #if defined ( __CC_ARM) + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __force_stores(); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #endif + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI(); + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 596 .loc 1 606 0 + 597 @ sp needed + 598 0016 7047 bx lr + 599 .L43: + 600 .align 2 + ARM GAS /tmp/ccnH7zer.s page 29 + + + 601 .L42: + 602 0018 00700040 .word 1073770496 + 603 001c 00ED00E0 .word -536810240 + 604 .cfi_endproc + 605 .LFE49: + 607 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + 608 .align 1 + 609 .global HAL_PWR_EnableSleepOnExit + 610 .syntax unified + 611 .code 16 + 612 .thumb_func + 613 .fpu softvfp + 615 HAL_PWR_EnableSleepOnExit: + 616 .LFB50: + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * interruptions handling. + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 617 .loc 1 617 0 + 618 .cfi_startproc + 619 @ args = 0, pretend = 0, frame = 0 + 620 @ frame_needed = 0, uses_anonymous_args = 0 + 621 @ link register save eliminated. + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 622 .loc 1 619 0 + 623 0000 024A ldr r2, .L45 + 624 0002 1369 ldr r3, [r2, #16] + 625 0004 0221 movs r1, #2 + 626 0006 0B43 orrs r3, r1 + 627 0008 1361 str r3, [r2, #16] + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 628 .loc 1 620 0 + 629 @ sp needed + 630 000a 7047 bx lr + 631 .L46: + 632 .align 2 + 633 .L45: + 634 000c 00ED00E0 .word -536810240 + 635 .cfi_endproc + 636 .LFE50: + 638 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 639 .align 1 + 640 .global HAL_PWR_DisableSleepOnExit + 641 .syntax unified + 642 .code 16 + 643 .thumb_func + 644 .fpu softvfp + 646 HAL_PWR_DisableSleepOnExit: + 647 .LFB51: + ARM GAS /tmp/ccnH7zer.s page 30 + + + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 648 .loc 1 630 0 + 649 .cfi_startproc + 650 @ args = 0, pretend = 0, frame = 0 + 651 @ frame_needed = 0, uses_anonymous_args = 0 + 652 @ link register save eliminated. + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 653 .loc 1 632 0 + 654 0000 024A ldr r2, .L48 + 655 0002 1369 ldr r3, [r2, #16] + 656 0004 0221 movs r1, #2 + 657 0006 8B43 bics r3, r1 + 658 0008 1361 str r3, [r2, #16] + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 659 .loc 1 633 0 + 660 @ sp needed + 661 000a 7047 bx lr + 662 .L49: + 663 .align 2 + 664 .L48: + 665 000c 00ED00E0 .word -536810240 + 666 .cfi_endproc + 667 .LFE51: + 669 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 670 .align 1 + 671 .global HAL_PWR_EnableSEVOnPend + 672 .syntax unified + 673 .code 16 + 674 .thumb_func + 675 .fpu softvfp + 677 HAL_PWR_EnableSEVOnPend: + 678 .LFB52: + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables CORTEX M0+ SEVONPEND bit. + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 679 .loc 1 643 0 + 680 .cfi_startproc + 681 @ args = 0, pretend = 0, frame = 0 + 682 @ frame_needed = 0, uses_anonymous_args = 0 + 683 @ link register save eliminated. + ARM GAS /tmp/ccnH7zer.s page 31 + + + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 684 .loc 1 645 0 + 685 0000 024A ldr r2, .L51 + 686 0002 1369 ldr r3, [r2, #16] + 687 0004 1021 movs r1, #16 + 688 0006 0B43 orrs r3, r1 + 689 0008 1361 str r3, [r2, #16] + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 690 .loc 1 646 0 + 691 @ sp needed + 692 000a 7047 bx lr + 693 .L52: + 694 .align 2 + 695 .L51: + 696 000c 00ED00E0 .word -536810240 + 697 .cfi_endproc + 698 .LFE52: + 700 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 701 .align 1 + 702 .global HAL_PWR_DisableSEVOnPend + 703 .syntax unified + 704 .code 16 + 705 .thumb_func + 706 .fpu softvfp + 708 HAL_PWR_DisableSEVOnPend: + 709 .LFB53: + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables CORTEX M0+ SEVONPEND bit. + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 710 .loc 1 656 0 + 711 .cfi_startproc + 712 @ args = 0, pretend = 0, frame = 0 + 713 @ frame_needed = 0, uses_anonymous_args = 0 + 714 @ link register save eliminated. + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 715 .loc 1 658 0 + 716 0000 024A ldr r2, .L54 + 717 0002 1369 ldr r3, [r2, #16] + 718 0004 1021 movs r1, #16 + 719 0006 8B43 bics r3, r1 + 720 0008 1361 str r3, [r2, #16] + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 721 .loc 1 659 0 + 722 @ sp needed + 723 000a 7047 bx lr + 724 .L55: + 725 .align 2 + 726 .L54: + ARM GAS /tmp/ccnH7zer.s page 32 + + + 727 000c 00ED00E0 .word -536810240 + 728 .cfi_endproc + 729 .LFE53: + 731 .section .text.HAL_PWR_PVDCallback,"ax",%progbits + 732 .align 1 + 733 .weak HAL_PWR_PVDCallback + 734 .syntax unified + 735 .code 16 + 736 .thumb_func + 737 .fpu softvfp + 739 HAL_PWR_PVDCallback: + 740 .LFB55: + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check PWR exti flag */ + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** HAL_PWR_PVDCallback(); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief PWR PVD interrupt callback + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 741 .loc 1 684 0 + 742 .cfi_startproc + 743 @ args = 0, pretend = 0, frame = 0 + 744 @ frame_needed = 0, uses_anonymous_args = 0 + 745 @ link register save eliminated. + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */ + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 746 .loc 1 688 0 + 747 @ sp needed + 748 0000 7047 bx lr + 749 .cfi_endproc + 750 .LFE55: + 752 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits + 753 .align 1 + 754 .global HAL_PWR_PVD_IRQHandler + 755 .syntax unified + 756 .code 16 + 757 .thumb_func + ARM GAS /tmp/ccnH7zer.s page 33 + + + 758 .fpu softvfp + 760 HAL_PWR_PVD_IRQHandler: + 761 .LFB54: + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check PWR exti flag */ + 762 .loc 1 667 0 + 763 .cfi_startproc + 764 @ args = 0, pretend = 0, frame = 0 + 765 @ frame_needed = 0, uses_anonymous_args = 0 + 766 0000 10B5 push {r4, lr} + 767 .LCFI2: + 768 .cfi_def_cfa_offset 8 + 769 .cfi_offset 4, -8 + 770 .cfi_offset 14, -4 + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** { + 771 .loc 1 669 0 + 772 0002 064B ldr r3, .L60 + 773 0004 5B69 ldr r3, [r3, #20] + 774 0006 DB03 lsls r3, r3, #15 + 775 0008 00D4 bmi .L59 + 776 .L57: + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 777 .loc 1 677 0 + 778 @ sp needed + 779 000a 10BD pop {r4, pc} + 780 .L59: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 781 .loc 1 672 0 + 782 000c FFF7FEFF bl HAL_PWR_PVDCallback + 783 .LVL20: + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** } + 784 .loc 1 675 0 + 785 0010 024B ldr r3, .L60 + 786 0012 8022 movs r2, #128 + 787 0014 5202 lsls r2, r2, #9 + 788 0016 5A61 str r2, [r3, #20] + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** + 789 .loc 1 677 0 + 790 0018 F7E7 b .L57 + 791 .L61: + 792 001a C046 .align 2 + 793 .L60: + 794 001c 00040140 .word 1073808384 + 795 .cfi_endproc + 796 .LFE54: + 798 .text + 799 .Letext0: + 800 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 801 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 802 .file 5 "Drivers/CMSIS/Include/core_cm0plus.h" + 803 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 804 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 805 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 806 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 807 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 808 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + 809 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h" + 810 .file 13 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + ARM GAS /tmp/ccnH7zer.s page 34 + + + ARM GAS /tmp/ccnH7zer.s page 35 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_pwr.c + /tmp/ccnH7zer.s:16 .text.HAL_PWR_DeInit:0000000000000000 $t + /tmp/ccnH7zer.s:23 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit + /tmp/ccnH7zer.s:49 .text.HAL_PWR_DeInit:0000000000000018 $d + /tmp/ccnH7zer.s:55 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t + /tmp/ccnH7zer.s:62 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess + /tmp/ccnH7zer.s:82 .text.HAL_PWR_EnableBkUpAccess:0000000000000010 $d + /tmp/ccnH7zer.s:87 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t + /tmp/ccnH7zer.s:94 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess + /tmp/ccnH7zer.s:113 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d + /tmp/ccnH7zer.s:119 .text.HAL_PWR_ConfigPVD:0000000000000000 $t + /tmp/ccnH7zer.s:126 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD + /tmp/ccnH7zer.s:214 .text.HAL_PWR_ConfigPVD:0000000000000074 $d + /tmp/ccnH7zer.s:221 .text.HAL_PWR_EnablePVD:0000000000000000 $t + /tmp/ccnH7zer.s:228 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD + /tmp/ccnH7zer.s:247 .text.HAL_PWR_EnablePVD:000000000000000c $d + /tmp/ccnH7zer.s:252 .text.HAL_PWR_DisablePVD:0000000000000000 $t + /tmp/ccnH7zer.s:259 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD + /tmp/ccnH7zer.s:278 .text.HAL_PWR_DisablePVD:000000000000000c $d + /tmp/ccnH7zer.s:283 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t + /tmp/ccnH7zer.s:290 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin + /tmp/ccnH7zer.s:310 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d + /tmp/ccnH7zer.s:315 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t + /tmp/ccnH7zer.s:322 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin + /tmp/ccnH7zer.s:341 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d + /tmp/ccnH7zer.s:346 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t + /tmp/ccnH7zer.s:353 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode + /tmp/ccnH7zer.s:441 .text.HAL_PWR_EnterSLEEPMode:0000000000000028 $d + /tmp/ccnH7zer.s:449 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t + /tmp/ccnH7zer.s:456 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode + /tmp/ccnH7zer.s:551 .text.HAL_PWR_EnterSTOPMode:0000000000000034 $d + /tmp/ccnH7zer.s:559 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t + /tmp/ccnH7zer.s:566 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode + /tmp/ccnH7zer.s:602 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d + /tmp/ccnH7zer.s:608 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t + /tmp/ccnH7zer.s:615 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit + /tmp/ccnH7zer.s:634 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d + /tmp/ccnH7zer.s:639 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t + /tmp/ccnH7zer.s:646 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit + /tmp/ccnH7zer.s:665 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d + /tmp/ccnH7zer.s:670 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t + /tmp/ccnH7zer.s:677 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend + /tmp/ccnH7zer.s:696 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d + /tmp/ccnH7zer.s:701 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t + /tmp/ccnH7zer.s:708 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend + /tmp/ccnH7zer.s:727 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d + /tmp/ccnH7zer.s:732 .text.HAL_PWR_PVDCallback:0000000000000000 $t + /tmp/ccnH7zer.s:739 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback + /tmp/ccnH7zer.s:753 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t + /tmp/ccnH7zer.s:760 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler + /tmp/ccnH7zer.s:794 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_pwr_ex.d b/build/stm32l0xx_hal_pwr_ex.d new file mode 100644 index 0000000..dcb7643 --- /dev/null +++ b/build/stm32l0xx_hal_pwr_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_pwr_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_pwr_ex.lst b/build/stm32l0xx_hal_pwr_ex.lst new file mode 100644 index 0000000..6ff73d7 --- /dev/null +++ b/build/stm32l0xx_hal_pwr_ex.lst @@ -0,0 +1,539 @@ +ARM GAS /tmp/ccerSDRQ.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_pwr_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits + 16 .align 1 + 17 .global HAL_PWREx_GetVoltageRange + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_PWREx_GetVoltageRange: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @file stm32l0xx_hal_pwr_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + Extended Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + Extended Peripheral Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** ****************************************************************************** + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @attention + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * are permitted provided that the following conditions are met: + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * this list of conditions and the following disclaimer. + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * this list of conditions and the following disclaimer in the documentation + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * and/or other materials provided with the distribution. + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * may be used to endorse or promote products derived from this software + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * without specific prior written permission. + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + ARM GAS /tmp/ccerSDRQ.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** ****************************************************************************** + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** #include "stm32l0xx_hal.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @{ + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** @addtogroup PWREx + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @{ + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @{ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** #define PWR_FLAG_SETTING_DELAY_US 50U + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @} + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @} + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Exported_Functions + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Low Power modes configuration functions + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** @verbatim + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** =============================================================================== + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** ##### Peripheral extended features functions ##### + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** =============================================================================== + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** @endverbatim + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @{ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Return Voltage Scaling Range. + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULA + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void) + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 26 .loc 1 87 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccerSDRQ.s page 3 + + + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** return (PWR->CR & PWR_CR_VOS); + 31 .loc 1 88 0 + 32 0000 024B ldr r3, .L2 + 33 0002 1868 ldr r0, [r3] + 34 0004 C023 movs r3, #192 + 35 0006 5B01 lsls r3, r3, #5 + 36 0008 1840 ands r0, r3 + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 37 .loc 1 89 0 + 38 @ sp needed + 39 000a 7047 bx lr + 40 .L3: + 41 .align 2 + 42 .L2: + 43 000c 00700040 .word 1073770496 + 44 .cfi_endproc + 45 .LFE39: + 47 .section .text.HAL_PWREx_EnableFastWakeUp,"ax",%progbits + 48 .align 1 + 49 .global HAL_PWREx_EnableFastWakeUp + 50 .syntax unified + 51 .code 16 + 52 .thumb_func + 53 .fpu softvfp + 55 HAL_PWREx_EnableFastWakeUp: + 56 .LFB40: + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Enables the Fast WakeUp from Ultra Low Power mode. + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @note This bit works in conjunction with ULP bit. + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * exiting from low power mode. + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval None + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFastWakeUp(void) + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 57 .loc 1 100 0 + 58 .cfi_startproc + 59 @ args = 0, pretend = 0, frame = 0 + 60 @ frame_needed = 0, uses_anonymous_args = 0 + 61 @ link register save eliminated. + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Enable the fast wake up */ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_FWU); + 62 .loc 1 102 0 + 63 0000 034A ldr r2, .L5 + 64 0002 1168 ldr r1, [r2] + 65 0004 8023 movs r3, #128 + 66 0006 DB00 lsls r3, r3, #3 + 67 0008 0B43 orrs r3, r1 + 68 000a 1360 str r3, [r2] + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 69 .loc 1 103 0 + 70 @ sp needed + 71 000c 7047 bx lr + ARM GAS /tmp/ccerSDRQ.s page 4 + + + 72 .L6: + 73 000e C046 .align 2 + 74 .L5: + 75 0010 00700040 .word 1073770496 + 76 .cfi_endproc + 77 .LFE40: + 79 .section .text.HAL_PWREx_DisableFastWakeUp,"ax",%progbits + 80 .align 1 + 81 .global HAL_PWREx_DisableFastWakeUp + 82 .syntax unified + 83 .code 16 + 84 .thumb_func + 85 .fpu softvfp + 87 HAL_PWREx_DisableFastWakeUp: + 88 .LFB41: + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Disables the Fast WakeUp from Ultra Low Power mode. + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval None + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFastWakeUp(void) + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 89 .loc 1 110 0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 0 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 93 @ link register save eliminated. + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Disable the fast wake up */ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_FWU); + 94 .loc 1 112 0 + 95 0000 024A ldr r2, .L8 + 96 0002 1368 ldr r3, [r2] + 97 0004 0249 ldr r1, .L8+4 + 98 0006 0B40 ands r3, r1 + 99 0008 1360 str r3, [r2] + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 100 .loc 1 113 0 + 101 @ sp needed + 102 000a 7047 bx lr + 103 .L9: + 104 .align 2 + 105 .L8: + 106 000c 00700040 .word 1073770496 + 107 0010 FFFBFFFF .word -1025 + 108 .cfi_endproc + 109 .LFE41: + 111 .section .text.HAL_PWREx_EnableUltraLowPower,"ax",%progbits + 112 .align 1 + 113 .global HAL_PWREx_EnableUltraLowPower + 114 .syntax unified + 115 .code 16 + 116 .thumb_func + 117 .fpu softvfp + 119 HAL_PWREx_EnableUltraLowPower: + 120 .LFB42: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccerSDRQ.s page 5 + + + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Enables the Ultra Low Power mode + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval None + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUltraLowPower(void) + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 121 .loc 1 120 0 + 122 .cfi_startproc + 123 @ args = 0, pretend = 0, frame = 0 + 124 @ frame_needed = 0, uses_anonymous_args = 0 + 125 @ link register save eliminated. + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Enable the Ultra Low Power mode */ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_ULP); + 126 .loc 1 122 0 + 127 0000 034A ldr r2, .L11 + 128 0002 1168 ldr r1, [r2] + 129 0004 8023 movs r3, #128 + 130 0006 9B00 lsls r3, r3, #2 + 131 0008 0B43 orrs r3, r1 + 132 000a 1360 str r3, [r2] + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 133 .loc 1 123 0 + 134 @ sp needed + 135 000c 7047 bx lr + 136 .L12: + 137 000e C046 .align 2 + 138 .L11: + 139 0010 00700040 .word 1073770496 + 140 .cfi_endproc + 141 .LFE42: + 143 .section .text.HAL_PWREx_DisableUltraLowPower,"ax",%progbits + 144 .align 1 + 145 .global HAL_PWREx_DisableUltraLowPower + 146 .syntax unified + 147 .code 16 + 148 .thumb_func + 149 .fpu softvfp + 151 HAL_PWREx_DisableUltraLowPower: + 152 .LFB43: + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Disables the Ultra Low Power mode + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval None + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUltraLowPower(void) + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 153 .loc 1 130 0 + 154 .cfi_startproc + 155 @ args = 0, pretend = 0, frame = 0 + 156 @ frame_needed = 0, uses_anonymous_args = 0 + 157 @ link register save eliminated. + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Disable the Ultra Low Power mode */ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_ULP); + 158 .loc 1 132 0 + 159 0000 024A ldr r2, .L14 + 160 0002 1368 ldr r3, [r2] + 161 0004 0249 ldr r1, .L14+4 + 162 0006 0B40 ands r3, r1 + ARM GAS /tmp/ccerSDRQ.s page 6 + + + 163 0008 1360 str r3, [r2] + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 164 .loc 1 133 0 + 165 @ sp needed + 166 000a 7047 bx lr + 167 .L15: + 168 .align 2 + 169 .L14: + 170 000c 00700040 .word 1073770496 + 171 0010 FFFDFFFF .word -513 + 172 .cfi_endproc + 173 .LFE43: + 175 .section .text.HAL_PWREx_EnableLowPowerRunMode,"ax",%progbits + 176 .align 1 + 177 .global HAL_PWREx_EnableLowPowerRunMode + 178 .syntax unified + 179 .code 16 + 180 .thumb_func + 181 .fpu softvfp + 183 HAL_PWREx_EnableLowPowerRunMode: + 184 .LFB44: + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Enable the Low Power Run mode. + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @note Low power run mode can only be entered when VCORE is in range 2. + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * In addition, the dynamic voltage scaling must not be used when Low + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * power run mode is selected. Only Stop and Sleep modes with regulator + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * configured in Low power mode is allowed when Low power run mode is + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * selected. + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @note The frequency of the system clock must be decreased to not exceed the + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * frequency of RCC_MSIRANGE_1. + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @note In Low power run mode, all I/O pins keep the same state as in Run mode. + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval None + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableLowPowerRunMode(void) + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 185 .loc 1 148 0 + 186 .cfi_startproc + 187 @ args = 0, pretend = 0, frame = 0 + 188 @ frame_needed = 0, uses_anonymous_args = 0 + 189 @ link register save eliminated. + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Enters the Low Power Run mode */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_LPSDSR); + 190 .loc 1 150 0 + 191 0000 054B ldr r3, .L17 + 192 0002 1A68 ldr r2, [r3] + 193 0004 0121 movs r1, #1 + 194 0006 0A43 orrs r2, r1 + 195 0008 1A60 str r2, [r3] + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_LPRUN); + 196 .loc 1 151 0 + 197 000a 1968 ldr r1, [r3] + 198 000c 8022 movs r2, #128 + 199 000e D201 lsls r2, r2, #7 + 200 0010 0A43 orrs r2, r1 + 201 0012 1A60 str r2, [r3] + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccerSDRQ.s page 7 + + + 202 .loc 1 152 0 + 203 @ sp needed + 204 0014 7047 bx lr + 205 .L18: + 206 0016 C046 .align 2 + 207 .L17: + 208 0018 00700040 .word 1073770496 + 209 .cfi_endproc + 210 .LFE44: + 212 .global __aeabi_uidiv + 213 .section .text.HAL_PWREx_DisableLowPowerRunMode,"ax",%progbits + 214 .align 1 + 215 .global HAL_PWREx_DisableLowPowerRunMode + 216 .syntax unified + 217 .code 16 + 218 .thumb_func + 219 .fpu softvfp + 221 HAL_PWREx_DisableLowPowerRunMode: + 222 .LFB45: + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @brief Disable the Low Power Run mode. + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * returns HAL_TIMEOUT status). The system clock frequency can then be + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * increased above 2 MHz. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** * @retval HAL_StatusTypeDef + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 223 .loc 1 163 0 + 224 .cfi_startproc + 225 @ args = 0, pretend = 0, frame = 0 + 226 @ frame_needed = 0, uses_anonymous_args = 0 + 227 0000 10B5 push {r4, lr} + 228 .LCFI0: + 229 .cfi_def_cfa_offset 8 + 230 .cfi_offset 4, -8 + 231 .cfi_offset 14, -4 + 232 .LVL0: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** uint32_t wait_loop_index = 0U; + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Exit the Low Power Run mode */ + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); + 233 .loc 1 167 0 + 234 0002 104B ldr r3, .L26 + 235 0004 1A68 ldr r2, [r3] + 236 0006 1049 ldr r1, .L26+4 + 237 0008 0A40 ands r2, r1 + 238 000a 1A60 str r2, [r3] + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); + 239 .loc 1 168 0 + 240 000c 1A68 ldr r2, [r3] + 241 000e 0121 movs r1, #1 + 242 0010 8A43 bics r2, r1 + 243 0012 1A60 str r2, [r3] + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccerSDRQ.s page 8 + + + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** /* Wait until REGLPF is reset */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); + 244 .loc 1 171 0 + 245 0014 0D4B ldr r3, .L26+8 + 246 0016 1868 ldr r0, [r3] + 247 0018 0D49 ldr r1, .L26+12 + 248 001a FFF7FEFF bl __aeabi_uidiv + 249 .LVL1: + 250 001e 3223 movs r3, #50 + 251 0020 5843 muls r0, r3 + 252 .LVL2: + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))) + 253 .loc 1 173 0 + 254 0022 00E0 b .L20 + 255 .L22: + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** wait_loop_index--; + 256 .loc 1 175 0 + 257 0024 0138 subs r0, r0, #1 + 258 .LVL3: + 259 .L20: + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 260 .loc 1 173 0 + 261 0026 0028 cmp r0, #0 + 262 0028 03D0 beq .L21 + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 263 .loc 1 173 0 is_stmt 0 discriminator 1 + 264 002a 064B ldr r3, .L26 + 265 002c 5B68 ldr r3, [r3, #4] + 266 002e 9B06 lsls r3, r3, #26 + 267 0030 F8D4 bmi .L22 + 268 .L21: + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** if (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)) + 269 .loc 1 178 0 is_stmt 1 + 270 0032 044B ldr r3, .L26 + 271 0034 5B68 ldr r3, [r3, #4] + 272 0036 9B06 lsls r3, r3, #26 + 273 0038 01D4 bmi .L25 + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** { + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** return HAL_OK; + 274 .loc 1 183 0 + 275 003a 0020 movs r0, #0 + 276 .LVL4: + 277 .L23: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + 278 .loc 1 184 0 + 279 @ sp needed + 280 003c 10BD pop {r4, pc} + 281 .LVL5: + 282 .L25: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccerSDRQ.s page 9 + + + 283 .loc 1 180 0 + 284 003e 0320 movs r0, #3 + 285 .LVL6: + 286 0040 FCE7 b .L23 + 287 .L27: + 288 0042 C046 .align 2 + 289 .L26: + 290 0044 00700040 .word 1073770496 + 291 0048 FFBFFFFF .word -16385 + 292 004c 00000000 .word SystemCoreClock + 293 0050 40420F00 .word 1000000 + 294 .cfi_endproc + 295 .LFE45: + 297 .text + 298 .Letext0: + 299 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 300 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 301 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 302 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 303 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 304 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 305 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 306 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 307 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 308 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + ARM GAS /tmp/ccerSDRQ.s page 10 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_pwr_ex.c + /tmp/ccerSDRQ.s:16 .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t + /tmp/ccerSDRQ.s:23 .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange + /tmp/ccerSDRQ.s:43 .text.HAL_PWREx_GetVoltageRange:000000000000000c $d + /tmp/ccerSDRQ.s:48 .text.HAL_PWREx_EnableFastWakeUp:0000000000000000 $t + /tmp/ccerSDRQ.s:55 .text.HAL_PWREx_EnableFastWakeUp:0000000000000000 HAL_PWREx_EnableFastWakeUp + /tmp/ccerSDRQ.s:75 .text.HAL_PWREx_EnableFastWakeUp:0000000000000010 $d + /tmp/ccerSDRQ.s:80 .text.HAL_PWREx_DisableFastWakeUp:0000000000000000 $t + /tmp/ccerSDRQ.s:87 .text.HAL_PWREx_DisableFastWakeUp:0000000000000000 HAL_PWREx_DisableFastWakeUp + /tmp/ccerSDRQ.s:106 .text.HAL_PWREx_DisableFastWakeUp:000000000000000c $d + /tmp/ccerSDRQ.s:112 .text.HAL_PWREx_EnableUltraLowPower:0000000000000000 $t + /tmp/ccerSDRQ.s:119 .text.HAL_PWREx_EnableUltraLowPower:0000000000000000 HAL_PWREx_EnableUltraLowPower + /tmp/ccerSDRQ.s:139 .text.HAL_PWREx_EnableUltraLowPower:0000000000000010 $d + /tmp/ccerSDRQ.s:144 .text.HAL_PWREx_DisableUltraLowPower:0000000000000000 $t + /tmp/ccerSDRQ.s:151 .text.HAL_PWREx_DisableUltraLowPower:0000000000000000 HAL_PWREx_DisableUltraLowPower + /tmp/ccerSDRQ.s:170 .text.HAL_PWREx_DisableUltraLowPower:000000000000000c $d + /tmp/ccerSDRQ.s:176 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000000 $t + /tmp/ccerSDRQ.s:183 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000000 HAL_PWREx_EnableLowPowerRunMode + /tmp/ccerSDRQ.s:208 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000018 $d + /tmp/ccerSDRQ.s:214 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000000 $t + /tmp/ccerSDRQ.s:221 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000000 HAL_PWREx_DisableLowPowerRunMode + /tmp/ccerSDRQ.s:290 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000044 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +SystemCoreClock diff --git a/build/stm32l0xx_hal_rcc.d b/build/stm32l0xx_hal_rcc.d new file mode 100644 index 0000000..965ccf7 --- /dev/null +++ b/build/stm32l0xx_hal_rcc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_rcc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_rcc.lst b/build/stm32l0xx_hal_rcc.lst new file mode 100644 index 0000000..2003cf9 --- /dev/null +++ b/build/stm32l0xx_hal_rcc.lst @@ -0,0 +1,4313 @@ +ARM GAS /tmp/cchbc9tY.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_rcc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.RCC_SetFlashLatencyFromMSIRange,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 RCC_SetFlashLatencyFromMSIRange: + 23 .LFB52: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @file stm32l0xx_hal_rcc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief RCC HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + Peripheral Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @verbatim + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ============================================================================== + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ##### RCC specific features ##### + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** After reset the device is running from multispeed internal oscillator clock + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** and all peripherals are off except internal SRAM, Flash and JTAG. + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** all peripherals mapped on these buses are running at MSI speed. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** are assigned to be used for debug purpose. + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] Once the device started from reset, the user application has to: + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (if the application needs higher frequency/performance) + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals whose clocks are not + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (*) SDIO only for STM32L0xxxD devices + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ##### RCC Limitations ##### + ARM GAS /tmp/cchbc9tY.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ============================================================================== + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** from/to registers. + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (++) AHB & APB peripherals, 1 dummy read is necessary + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** Workarounds: + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @endverbatim + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ****************************************************************************** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @attention + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * Redistribution and use in source and binary forms, with or without modification, + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * are permitted provided that the following conditions are met: + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * this list of conditions and the following disclaimer. + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * this list of conditions and the following disclaimer in the documentation + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * and/or other materials provided with the distribution. + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * may be used to endorse or promote products derived from this software + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * without specific prior written permission. + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ****************************************************************************** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #include "stm32l0xx_hal.h" + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @addtogroup STM32L0xx_HAL_Driver + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC RCC + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief RCC HAL module driver + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + ARM GAS /tmp/cchbc9tY.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Bits position in in the CFGR register */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_CFGR_PLLMUL_BITNUMBER RCC_CFGR_PLLMUL_Pos + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_CFGR_PLLDIV_BITNUMBER RCC_CFGR_PLLDIV_Pos + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_CFGR_HPRE_BITNUMBER RCC_CFGR_HPRE_Pos + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_CFGR_PPRE1_BITNUMBER RCC_CFGR_PPRE1_Pos + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_CFGR_PPRE2_BITNUMBER RCC_CFGR_PPRE2_Pos + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Bits position in in the ICSCR register */ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_ICSCR_MSIRANGE_BITNUMBER RCC_ICSCR_MSIRANGE_Pos + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define RCC_ICSCR_MSITRIM_BITNUMBER RCC_ICSCR_MSITRIM_Pos + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO2_GPIO_PORT GPIOA + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO2_PIN GPIO_PIN_9 + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx) + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO3_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO3_GPIO_PORT GPIOB + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #define MCO3_PIN GPIO_PIN_13 + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Private_Functions RCC Private Functions + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange); + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + ARM GAS /tmp/cchbc9tY.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @verbatim + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** =============================================================================== + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** =============================================================================== + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** and APB2). + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** the PLL as System clock source. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** clock source. + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring different output clocks: + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 32 MHz) + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** clock source), the System clocks automatically switched to MSI and an interrupt + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M0+ NMI + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) MCO1/MCO2/MCO3 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HSE, HSI48 or PLL clock (through a configurable prescaler) on PA8/PA9/PB13 pins. + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HSE and PLL. + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** the peripherals mapped on these buses. You can use + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + ARM GAS /tmp/cchbc9tY.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RT + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** macros to configure this clock. + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG() + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** macros to configure this clock. + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+@) USB FS and RNG: USB FS require a frequency equal to 48 MHz to work correctly. + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** This clock is derived of the main PLL through PLL Multiplier or HSI48 RC oscillator. + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (+@) IWDG clock which is always the LSI clock. + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** and PCLK1 32 MHz. Depending on the device voltage range, the maximum + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** frequency should be adapted accordingly. + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @endverbatim + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** Additional consideration on the HCLK based on Latency settings: + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +----------------------------------------------------------------------+ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | Latency | HCLK clock frequency (MHz) | + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | |------------------------------------------------------| + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | | voltage range 1 | voltage range 2 | voltage range 3 | + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | | 1.8 V | 1.5 V | 1.2 V | + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |---------------|------------------|-----------------|-----------------| + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 | + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |---------------|------------------|-----------------|-----------------| + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +----------------------------------------------------------------------+ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** The following table gives the different clock source frequencies depending on the product + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** voltage range: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +------------------------------------------------------------------------------------------+ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | Product voltage | Clock frequency | + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | |------------------|-----------------------------|-----------------------| + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | range | MSI | HSI | HSE | PLL | + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |-----------------|---------|--------|-----------------------------|-----------------------| + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz | + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) | + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |-----------------|---------|--------|-----------------------------|-----------------------| + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz | + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | | | | | (PLLVCO max = 48 MHz) | + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** |-----------------|---------|--------|-----------------------------|-----------------------| + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | | | | | (PLLVCO max = 24 MHz) | + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +------------------------------------------------------------------------------------------+ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - MSI ON and used as system clock source + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - HSI, HSE and PLL OFF + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + ARM GAS /tmp/cchbc9tY.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - CSS and MCO1/MCO2/MCO3 OFF + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - All interrupts disabled + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note This function does not modify the configuration of the + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - Peripheral clocks + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * - HSI48 clock + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_DeInit(void) + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __IO uint32_t tmpreg; + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set MSION bit */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_MSION); + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Switch SYSCLK to MSI*/ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Reset HSE, HSI, CSS, PLL */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN) + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #elif !defined(RCC_CR_CSSHSEON) && defined(RCC_CR_HSIOUTEN) + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_CR_HSEON | RCC_CR_PLLON); + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #elif defined(RCC_CR_CSSHSEON) && !defined(RCC_CR_HSIOUTEN) + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Delay after an RCC peripheral clock */ \ + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** UNUSED(tmpreg); + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Reset HSEBYP bit */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Reset CFGR register */ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */ + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITR + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set HSITRIM bits to the reset value */ + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << 8)); + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable all interrupts */ + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** CLEAR_REG(RCC->CIER); + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SystemCoreClock = MSI_VALUE; + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * RCC_OscInitTypeDef. + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + ARM GAS /tmp/cchbc9tY.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * supported by this macro. User should request a transition to LSE Off + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * supported by this macro. User should request a transition to HSE Off + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval HAL status + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tickstart = 0U; + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != NULL); + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the HSE State */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSE is ready */ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + ARM GAS /tmp/cchbc9tY.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the HSI State */ + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */ + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSI is ready */ + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + ARM GAS /tmp/cchbc9tY.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSI is disabled */ + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*----------------------------- MSI Configuration --------------------------*/ + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* When the MSI is used as system clock it will not be disabled */ + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_ + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Otherwise, just the calibration and MSI range change are allowed */ + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check MSICalibrationValue and MSIClockRange input parameters */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* First increase number of wait states update if necessary */ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Else, keep current flash latency while decreasing applies */ + ARM GAS /tmp/cchbc9tY.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Decrease number of wait states update if necessary */ + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SystemCoreClock = (32768U * (1U << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANG + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_InitTick (TICK_INT_PRIORITY); + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check MSI State */ + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the MSI State */ + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable the Multi Speed oscillator (MSI). */ + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_ENABLE(); + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till MSI is ready */ + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check MSICalibrationValue and MSIClockRange input parameters */ + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the Multi Speed oscillator (MSI). */ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MSI_DISABLE(); + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + ARM GAS /tmp/cchbc9tY.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till MSI is ready */ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSI State */ + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till LSI is ready */ + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till LSI is disabled */ + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + ARM GAS /tmp/cchbc9tY.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pwrclkchanged = SET; + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till LSE is ready */ + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till LSE is disabled */ + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + ARM GAS /tmp/cchbc9tY.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Require to disable power clock if necessary */ + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(pwrclkchanged == SET) + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*----------------------------- HSI48 Configuration --------------------------*/ + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the HSI48 State */ + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI48). */ + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI48_ENABLE(); + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSI48 is ready */ + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI48). */ + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_HSI48_DISABLE(); + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till HSI48 is ready */ + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + ARM GAS /tmp/cchbc9tY.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the main PLL. */ + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Configure the main PLL clock source, multiplication and division factors. */ + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL, + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLDIV); + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Enable the main PLL. */ + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till PLL is ready */ + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Disable the main PLL. */ + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + ARM GAS /tmp/cchbc9tY.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_OK; + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param FLatency FLASH Latency + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * The value of this parameter depend on device used within the same series + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The MSI is used (enabled by hardware) as system clock source after + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * clock source is ready (clock stable after start-up delay or PLL locked). + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * occur when the clock source will be ready. + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * currently used as system clock source. + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Depending on the device voltage range, the software has to set correctly + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * (for more details refer to section above "Initialization/de-initialization functions") + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval HAL status + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tickstart = 0U; + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != NULL); + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + ARM GAS /tmp/cchbc9tY.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the HSE ready flag */ + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the PLL ready flag */ + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the HSI ready flag */ + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* MSI is selected as System Clock Source */ + ARM GAS /tmp/cchbc9tY.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the MSI ready flag */ + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get Start Tick */ + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_TIMEOUT; + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + ARM GAS /tmp/cchbc9tY.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CF + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_InitTick (TICK_INT_PRIORITY); + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_OK; + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief RCC clocks control functions + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @verbatim + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** =============================================================================== + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** ##### Peripheral Control functions ##### + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** =============================================================================== + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** [..] + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** frequencies. + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @endverbatim + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + ARM GAS /tmp/cchbc9tY.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * This parameter can be one of the following values: +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA9). +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @if STM32L031xx +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L041xx +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L073xx +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L083xx +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L072xx +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L082xx +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L071xx +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L081xx +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO3 Clock source to output on MCO3 pin(PB13) +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @endif +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * This parameter can be one of the following values: +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @if STM32L052xx +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L053xx +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L062xx +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L063xx +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L072xx +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L073xx +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L082xx +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @elseif STM32L083xx +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** @endif +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * This parameter can be one of the following values: +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) + ARM GAS /tmp/cchbc9tY.s page 20 + + +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** GPIO_InitTypeDef gpio = {0}; +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Mode = GPIO_MODE_AF_PP; +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Speed = GPIO_SPEED_FREQ_HIGH; +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Pull = GPIO_NOPULL; +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(RCC_MCOx == RCC_MCO1) +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Pin = MCO1_PIN; +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* MCO1 Clock Enable */ +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MCO1_CLK_ENABLE(); +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \ +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx) +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if (RCC_MCOx == RCC_MCO3) +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Pin = MCO3_PIN; +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF2_MCO; +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* MCO3 Clock Enable */ +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MCO3_CLK_ENABLE(); +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO3_GPIO_PORT, &gpio); +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Pin = MCO2_PIN; +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* MCO2 Clock Enable */ +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** MCO2_CLK_ENABLE(); +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &gpio); +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Configure the MCO clock source */ +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_HSECSS_SUPPORT) +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Enables the Clock Security System. +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ + ARM GAS /tmp/cchbc9tY.s page 21 + + +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSON) ; +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSECSS_SUPPORT */ +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * constant and the selected clock source: +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note If SYSCLK source is MSI, function returns a value based on MSI +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * Value as defined by the MSI range. +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**) +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**) +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * 16 MHz) but the real value may vary depending on the variations +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * in voltage and temperature. +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * have wrong result. +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * value for HSE crystal. +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note This function can be used by the user application to compute the +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval SYSCLK frequency +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0; +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t sysclockfreq = 0; +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** tmpreg = RCC->CFGR; +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** switch (tmpreg & RCC_CFGR_SWS) +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSIDIVF) != 0) +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = (HSI_VALUE >> 2); +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; + ARM GAS /tmp/cchbc9tY.s page 22 + + +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1; +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* HSE used as PLL clock source */ +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pllvco = (HSE_VALUE * pllm) / plld; +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSIDIVF) != 0) +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pllvco = ((HSI_VALUE >> 2) * pllm) / plld; +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pllvco = (HSI_VALUE * pllm) / plld; +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = pllvco; +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** default: /* MSI used as system clock */ +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_BITNUMBER; +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = (32768 * (1 << (msiclkrange + 1))); +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return sysclockfreq; +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Returns the HCLK frequency +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * and updated within this function +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval HCLK frequency +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return SystemCoreClock; +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the + ARM GAS /tmp/cchbc9tY.s page 23 + + +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval PCLK1 frequency +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BIT +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval PCLK2 frequency +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITN +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * RCC configuration registers. +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * will be configured. +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != NULL); +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + ARM GAS /tmp/cchbc9tY.s page 24 + + +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> 8); +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the MSI configuration -----------------------------------------------*/ +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->MSIState = RCC_MSI_ON; +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->MSIState = RCC_MSI_OFF; +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the HSI48 configuration if any-----------------------------------------*/ +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + ARM GAS /tmp/cchbc9tY.s page 25 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Get the RCC_ClkInitStruct according to the internal +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * RCC configuration registers. +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * contains the current clock configuration. +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != NULL); +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** assert_param(pFLatency != NULL); +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #if defined(RCC_HSECSS_SUPPORT) +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval None +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check RCC CSSF flag */ +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_GET_IT(RCC_IT_CSS)) +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_RCC_CSSCallback(); +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ + ARM GAS /tmp/cchbc9tY.s page 26 + + +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval none +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSECSS_SUPPORT */ +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @} +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** @addtogroup RCC_Private_Functions +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @{ +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /** +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @brief Update number of Flash wait states in line with MSI range and current +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** voltage range +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** * @retval HAL status +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** */ +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 25 .loc 1 1438 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 30B5 push {r4, r5, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 12 + 33 .cfi_offset 4, -12 + 34 .cfi_offset 5, -8 + 35 .cfi_offset 14, -4 + 36 .LVL1: +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t vos = 0; +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 37 .loc 1 1443 0 + 38 0002 1B4B ldr r3, .L9 + 39 0004 DB68 ldr r3, [r3, #12] + 40 0006 F022 movs r2, #240 + ARM GAS /tmp/cchbc9tY.s page 27 + + + 41 0008 1340 ands r3, r2 + 42 000a 22D1 bne .L6 +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 43 .loc 1 1445 0 + 44 000c 184A ldr r2, .L9 + 45 000e 926B ldr r2, [r2, #56] + 46 0010 D200 lsls r2, r2, #3 + 47 0012 0ED5 bpl .L3 +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 48 .loc 1 1447 0 + 49 0014 174A ldr r2, .L9+4 + 50 0016 1268 ldr r2, [r2] + 51 0018 C021 movs r1, #192 + 52 001a 4901 lsls r1, r1, #5 + 53 001c 0A40 ands r2, r1 + 54 .LVL2: + 55 .L4: +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** else +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** vos = READ_BIT(PWR->CR, PWR_CR_VOS); +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 56 .loc 1 1457 0 + 57 001e C021 movs r1, #192 + 58 0020 4901 lsls r1, r1, #5 + 59 0022 8A42 cmp r2, r1 + 60 0024 16D1 bne .L2 + 61 .loc 1 1457 0 is_stmt 0 discriminator 1 + 62 0026 C022 movs r2, #192 + 63 .LVL3: + 64 0028 1202 lsls r2, r2, #8 + 65 002a 9042 cmp r0, r2 + 66 002c 12D1 bne .L2 +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** latency = FLASH_LATENCY_1; /* 1WS */ + 67 .loc 1 1459 0 is_stmt 1 + 68 002e 0123 movs r3, #1 + 69 0030 10E0 b .L2 + 70 .LVL4: + 71 .L3: +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 72 .loc 1 1451 0 + 73 0032 0F49 ldr r1, .L9 + 74 0034 8C6B ldr r4, [r1, #56] + 75 0036 8022 movs r2, #128 + 76 0038 5205 lsls r2, r2, #21 + 77 003a 2243 orrs r2, r4 + 78 003c 8A63 str r2, [r1, #56] +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 79 .loc 1 1452 0 + ARM GAS /tmp/cchbc9tY.s page 28 + + + 80 003e 0D4A ldr r2, .L9+4 + 81 0040 1268 ldr r2, [r2] + 82 0042 C024 movs r4, #192 + 83 0044 6401 lsls r4, r4, #5 + 84 0046 2240 ands r2, r4 + 85 .LVL5: +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 86 .loc 1 1453 0 + 87 0048 8C6B ldr r4, [r1, #56] + 88 004a 0B4D ldr r5, .L9+8 + 89 004c 2C40 ands r4, r5 + 90 004e 8C63 str r4, [r1, #56] + 91 0050 E5E7 b .L4 + 92 .LVL6: + 93 .L6: +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 94 .loc 1 1440 0 + 95 0052 0023 movs r3, #0 + 96 .LVL7: + 97 .L2: +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(latency); + 98 .loc 1 1463 0 + 99 0054 0948 ldr r0, .L9+12 + 100 .LVL8: + 101 0056 0268 ldr r2, [r0] + 102 0058 0121 movs r1, #1 + 103 005a 8A43 bics r2, r1 + 104 005c 1A43 orrs r2, r3 + 105 005e 0260 str r2, [r0] +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + 106 .loc 1 1467 0 + 107 0060 0268 ldr r2, [r0] + 108 0062 1140 ands r1, r2 + 109 0064 9942 cmp r1, r3 + 110 0066 01D0 beq .L8 +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_ERROR; + 111 .loc 1 1469 0 + 112 0068 0120 movs r0, #1 + 113 .L5: +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return HAL_OK; +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 114 .loc 1 1473 0 + 115 @ sp needed + 116 006a 30BD pop {r4, r5, pc} + 117 .L8: +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 118 .loc 1 1472 0 + 119 006c 0020 movs r0, #0 + ARM GAS /tmp/cchbc9tY.s page 29 + + + 120 006e FCE7 b .L5 + 121 .L10: + 122 .align 2 + 123 .L9: + 124 0070 00100240 .word 1073876992 + 125 0074 00700040 .word 1073770496 + 126 0078 FFFFFFEF .word -268435457 + 127 007c 00200240 .word 1073881088 + 128 .cfi_endproc + 129 .LFE52: + 131 .section .text.HAL_RCC_DeInit,"ax",%progbits + 132 .align 1 + 133 .global HAL_RCC_DeInit + 134 .syntax unified + 135 .code 16 + 136 .thumb_func + 137 .fpu softvfp + 139 HAL_RCC_DeInit: + 140 .LFB39: + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** __IO uint32_t tmpreg; + 141 .loc 1 272 0 + 142 .cfi_startproc + 143 @ args = 0, pretend = 0, frame = 8 + 144 @ frame_needed = 0, uses_anonymous_args = 0 + 145 @ link register save eliminated. + 146 0000 82B0 sub sp, sp, #8 + 147 .LCFI1: + 148 .cfi_def_cfa_offset 8 + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 149 .loc 1 276 0 + 150 0002 174B ldr r3, .L12 + 151 0004 1968 ldr r1, [r3] + 152 0006 8022 movs r2, #128 + 153 0008 5200 lsls r2, r2, #1 + 154 000a 0A43 orrs r2, r1 + 155 000c 1A60 str r2, [r3] + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 156 .loc 1 279 0 + 157 000e DA68 ldr r2, [r3, #12] + 158 0010 0321 movs r1, #3 + 159 0012 8A43 bics r2, r1 + 160 0014 DA60 str r2, [r3, #12] + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); + 161 .loc 1 283 0 + 162 0016 1A68 ldr r2, [r3] + 163 0018 1249 ldr r1, .L12+4 + 164 001a 0A40 ands r2, r1 + 165 001c 1A60 str r2, [r3] + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** UNUSED(tmpreg); + 166 .loc 1 294 0 + 167 001e 1A68 ldr r2, [r3] + 168 0020 8021 movs r1, #128 + 169 0022 4902 lsls r1, r1, #9 + 170 0024 0A40 ands r2, r1 + 171 0026 0192 str r2, [sp, #4] + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 172 .loc 1 295 0 + ARM GAS /tmp/cchbc9tY.s page 30 + + + 173 0028 019A ldr r2, [sp, #4] + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 174 .loc 1 298 0 + 175 002a 1A68 ldr r2, [r3] + 176 002c 0E49 ldr r1, .L12+8 + 177 002e 0A40 ands r2, r1 + 178 0030 1A60 str r2, [r3] + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 179 .loc 1 301 0 + 180 0032 0020 movs r0, #0 + 181 0034 D860 str r0, [r3, #12] + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 182 .loc 1 304 0 + 183 0036 5A68 ldr r2, [r3, #4] + 184 0038 0C49 ldr r1, .L12+12 + 185 003a 1140 ands r1, r2 + 186 003c A022 movs r2, #160 + 187 003e 1202 lsls r2, r2, #8 + 188 0040 0A43 orrs r2, r1 + 189 0042 5A60 str r2, [r3, #4] + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 190 .loc 1 307 0 + 191 0044 5A68 ldr r2, [r3, #4] + 192 0046 0A49 ldr r1, .L12+16 + 193 0048 1140 ands r1, r2 + 194 004a 8022 movs r2, #128 + 195 004c 5201 lsls r2, r2, #5 + 196 004e 0A43 orrs r2, r1 + 197 0050 5A60 str r2, [r3, #4] + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 198 .loc 1 310 0 + 199 0052 1861 str r0, [r3, #16] + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 200 .loc 1 313 0 + 201 0054 074B ldr r3, .L12+20 + 202 0056 084A ldr r2, .L12+24 + 203 0058 1A60 str r2, [r3] + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 204 .loc 1 314 0 + 205 005a 02B0 add sp, sp, #8 + 206 @ sp needed + 207 005c 7047 bx lr + 208 .L13: + 209 005e C046 .align 2 + 210 .L12: + 211 0060 00100240 .word 1073876992 + 212 0064 D4FFF6FE .word -17367084 + 213 0068 FFFFFBFF .word -262145 + 214 006c FF1FFF00 .word 16719871 + 215 0070 FFE0FFFF .word -7937 + 216 0074 00000000 .word SystemCoreClock + 217 0078 80841E00 .word 2000000 + 218 .cfi_endproc + 219 .LFE39: + 221 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 222 .align 1 + 223 .global HAL_RCC_OscConfig + ARM GAS /tmp/cchbc9tY.s page 31 + + + 224 .syntax unified + 225 .code 16 + 226 .thumb_func + 227 .fpu softvfp + 229 HAL_RCC_OscConfig: + 230 .LFB40: + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tickstart = 0U; + 231 .loc 1 331 0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 8 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 .LVL9: + 236 0000 70B5 push {r4, r5, r6, lr} + 237 .LCFI2: + 238 .cfi_def_cfa_offset 16 + 239 .cfi_offset 4, -16 + 240 .cfi_offset 5, -12 + 241 .cfi_offset 6, -8 + 242 .cfi_offset 14, -4 + 243 0002 82B0 sub sp, sp, #8 + 244 .LCFI3: + 245 .cfi_def_cfa_offset 24 + 246 0004 0400 movs r4, r0 + 247 .LVL10: + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 248 .loc 1 339 0 + 249 0006 0368 ldr r3, [r0] + 250 0008 DB07 lsls r3, r3, #31 + 251 000a 41D5 bpl .L15 + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 252 .loc 1 345 0 + 253 000c BB4B ldr r3, .L119 + 254 000e DA68 ldr r2, [r3, #12] + 255 0010 0C23 movs r3, #12 + 256 0012 1340 ands r3, r2 + 257 0014 082B cmp r3, #8 + 258 0016 33D0 beq .L16 + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 259 .loc 1 346 0 + 260 0018 B84B ldr r3, .L119 + 261 001a DA68 ldr r2, [r3, #12] + 262 001c 0C23 movs r3, #12 + 263 001e 1340 ands r3, r2 + 264 0020 0C2B cmp r3, #12 + 265 0022 29D0 beq .L104 + 266 .L17: + 267 .LBB6: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 268 .loc 1 356 0 + 269 0024 6368 ldr r3, [r4, #4] + 270 0026 8022 movs r2, #128 + 271 0028 5202 lsls r2, r2, #9 + 272 002a 9342 cmp r3, r2 + 273 002c 58D0 beq .L105 + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 274 .loc 1 356 0 is_stmt 0 discriminator 2 + 275 002e A022 movs r2, #160 + ARM GAS /tmp/cchbc9tY.s page 32 + + + 276 0030 D202 lsls r2, r2, #11 + 277 0032 9342 cmp r3, r2 + 278 0034 5BD0 beq .L106 + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 279 .loc 1 356 0 discriminator 4 + 280 0036 B14B ldr r3, .L119 + 281 0038 1A68 ldr r2, [r3] + 282 003a B149 ldr r1, .L119+4 + 283 003c 0A40 ands r2, r1 + 284 003e 1A60 str r2, [r3] + 285 0040 1A68 ldr r2, [r3] + 286 0042 8021 movs r1, #128 + 287 0044 4902 lsls r1, r1, #9 + 288 0046 0A40 ands r2, r1 + 289 0048 0192 str r2, [sp, #4] + 290 004a 019A ldr r2, [sp, #4] + 291 004c 1A68 ldr r2, [r3] + 292 004e AD49 ldr r1, .L119+8 + 293 0050 0A40 ands r2, r1 + 294 0052 1A60 str r2, [r3] + 295 .L20: + 296 .LBE6: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 297 .loc 1 360 0 is_stmt 1 + 298 0054 6368 ldr r3, [r4, #4] + 299 0056 002B cmp r3, #0 + 300 0058 55D0 beq .L22 + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 301 .loc 1 363 0 + 302 005a FFF7FEFF bl HAL_GetTick + 303 .LVL11: + 304 005e 0500 movs r5, r0 + 305 .LVL12: + 306 .L23: + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 307 .loc 1 366 0 + 308 0060 A64B ldr r3, .L119 + 309 0062 1B68 ldr r3, [r3] + 310 0064 9B03 lsls r3, r3, #14 + 311 0066 13D4 bmi .L15 + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 312 .loc 1 368 0 + 313 0068 FFF7FEFF bl HAL_GetTick + 314 .LVL13: + 315 006c 401B subs r0, r0, r5 + 316 006e A64B ldr r3, .L119+12 + 317 0070 9842 cmp r0, r3 + 318 0072 F5D9 bls .L23 + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 319 .loc 1 370 0 + 320 0074 0320 movs r0, #3 + 321 0076 69E2 b .L18 + 322 .LVL14: + 323 .L104: + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 324 .loc 1 346 0 discriminator 1 + 325 0078 A04B ldr r3, .L119 + ARM GAS /tmp/cchbc9tY.s page 33 + + + 326 007a DB68 ldr r3, [r3, #12] + 327 007c DB03 lsls r3, r3, #15 + 328 007e D1D5 bpl .L17 + 329 .L16: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 330 .loc 1 348 0 + 331 0080 9E4B ldr r3, .L119 + 332 0082 1B68 ldr r3, [r3] + 333 0084 9B03 lsls r3, r3, #14 + 334 0086 03D5 bpl .L15 + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 335 .loc 1 348 0 is_stmt 0 discriminator 1 + 336 0088 6368 ldr r3, [r4, #4] + 337 008a 002B cmp r3, #0 + 338 008c 00D1 bne .LCB296 + 339 008e 56E2 b .L107 @long jump + 340 .LCB296: + 341 .LVL15: + 342 .L15: + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 343 .loc 1 391 0 is_stmt 1 + 344 0090 2368 ldr r3, [r4] + 345 0092 9B07 lsls r3, r3, #30 + 346 0094 5BD5 bpl .L27 + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 347 .loc 1 398 0 + 348 0096 994B ldr r3, .L119 + 349 0098 DA68 ldr r2, [r3, #12] + 350 009a 0C23 movs r3, #12 + 351 009c 1340 ands r3, r2 + 352 009e 042B cmp r3, #4 + 353 00a0 44D0 beq .L28 + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 354 .loc 1 399 0 + 355 00a2 964B ldr r3, .L119 + 356 00a4 DA68 ldr r2, [r3, #12] + 357 00a6 0C23 movs r3, #12 + 358 00a8 1340 ands r3, r2 + 359 00aa 0C2B cmp r3, #12 + 360 00ac 3AD0 beq .L108 + 361 .L29: + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 362 .loc 1 416 0 + 363 00ae E368 ldr r3, [r4, #12] + 364 00b0 002B cmp r3, #0 + 365 00b2 00D1 bne .LCB321 + 366 00b4 AEE0 b .L31 @long jump + 367 .LCB321: + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 368 .loc 1 419 0 + 369 00b6 9149 ldr r1, .L119 + 370 00b8 0A68 ldr r2, [r1] + 371 00ba 0920 movs r0, #9 + 372 00bc 8243 bics r2, r0 + 373 00be 1343 orrs r3, r2 + 374 00c0 0B60 str r3, [r1] + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + ARM GAS /tmp/cchbc9tY.s page 34 + + + 375 .loc 1 422 0 + 376 00c2 FFF7FEFF bl HAL_GetTick + 377 .LVL16: + 378 00c6 0500 movs r5, r0 + 379 .LVL17: + 380 .L32: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 381 .loc 1 425 0 + 382 00c8 8C4B ldr r3, .L119 + 383 00ca 1B68 ldr r3, [r3] + 384 00cc 5B07 lsls r3, r3, #29 + 385 00ce 00D5 bpl .LCB340 + 386 00d0 97E0 b .L109 @long jump + 387 .LCB340: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 388 .loc 1 427 0 + 389 00d2 FFF7FEFF bl HAL_GetTick + 390 .LVL18: + 391 00d6 401B subs r0, r0, r5 + 392 00d8 0228 cmp r0, #2 + 393 00da F5D9 bls .L32 + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 394 .loc 1 429 0 + 395 00dc 0320 movs r0, #3 + 396 00de 35E2 b .L18 + 397 .LVL19: + 398 .L105: + 399 .LBB7: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 400 .loc 1 356 0 discriminator 1 + 401 00e0 864A ldr r2, .L119 + 402 00e2 1168 ldr r1, [r2] + 403 00e4 8023 movs r3, #128 + 404 00e6 5B02 lsls r3, r3, #9 + 405 00e8 0B43 orrs r3, r1 + 406 00ea 1360 str r3, [r2] + 407 00ec B2E7 b .L20 + 408 .L106: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 409 .loc 1 356 0 is_stmt 0 discriminator 3 + 410 00ee 834B ldr r3, .L119 + 411 00f0 1968 ldr r1, [r3] + 412 00f2 8022 movs r2, #128 + 413 00f4 D202 lsls r2, r2, #11 + 414 00f6 0A43 orrs r2, r1 + 415 00f8 1A60 str r2, [r3] + 416 00fa 1968 ldr r1, [r3] + 417 00fc 8022 movs r2, #128 + 418 00fe 5202 lsls r2, r2, #9 + 419 0100 0A43 orrs r2, r1 + 420 0102 1A60 str r2, [r3] + 421 0104 A6E7 b .L20 + 422 .L22: + 423 .LBE7: + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 424 .loc 1 377 0 is_stmt 1 + 425 0106 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/cchbc9tY.s page 35 + + + 426 .LVL20: + 427 010a 0500 movs r5, r0 + 428 .LVL21: + 429 .L25: + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 430 .loc 1 380 0 + 431 010c 7B4B ldr r3, .L119 + 432 010e 1B68 ldr r3, [r3] + 433 0110 9B03 lsls r3, r3, #14 + 434 0112 BDD5 bpl .L15 + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 435 .loc 1 382 0 + 436 0114 FFF7FEFF bl HAL_GetTick + 437 .LVL22: + 438 0118 401B subs r0, r0, r5 + 439 011a 7B4B ldr r3, .L119+12 + 440 011c 9842 cmp r0, r3 + 441 011e F5D9 bls .L25 + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 442 .loc 1 384 0 + 443 0120 0320 movs r0, #3 + 444 0122 13E2 b .L18 + 445 .LVL23: + 446 .L108: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 447 .loc 1 399 0 discriminator 1 + 448 0124 754B ldr r3, .L119 + 449 0126 DB68 ldr r3, [r3, #12] + 450 0128 DB03 lsls r3, r3, #15 + 451 012a C0D4 bmi .L29 + 452 .L28: + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 453 .loc 1 402 0 + 454 012c 734B ldr r3, .L119 + 455 012e 1B68 ldr r3, [r3] + 456 0130 5B07 lsls r3, r3, #29 + 457 0132 04D5 bpl .L30 + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 458 .loc 1 402 0 is_stmt 0 discriminator 1 + 459 0134 E368 ldr r3, [r4, #12] + 460 0136 012B cmp r3, #1 + 461 0138 01D0 beq .L30 + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 462 .loc 1 404 0 is_stmt 1 + 463 013a 0120 movs r0, #1 + 464 013c 06E2 b .L18 + 465 .L30: + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 466 .loc 1 410 0 + 467 013e 6F49 ldr r1, .L119 + 468 0140 4B68 ldr r3, [r1, #4] + 469 0142 724A ldr r2, .L119+16 + 470 0144 1340 ands r3, r2 + 471 0146 2269 ldr r2, [r4, #16] + 472 0148 1202 lsls r2, r2, #8 + 473 014a 1343 orrs r3, r2 + 474 014c 4B60 str r3, [r1, #4] + ARM GAS /tmp/cchbc9tY.s page 36 + + + 475 .L27: + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 476 .loc 1 456 0 + 477 014e 2368 ldr r3, [r4] + 478 0150 DB06 lsls r3, r3, #27 + 479 0152 3BD5 bpl .L36 + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 480 .loc 1 459 0 + 481 0154 694B ldr r3, .L119 + 482 0156 DB68 ldr r3, [r3, #12] + 483 0158 0C22 movs r2, #12 + 484 015a 1A42 tst r2, r3 + 485 015c 00D0 beq .LCB454 + 486 015e 80E0 b .L37 @long jump + 487 .LCB454: + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 488 .loc 1 461 0 + 489 0160 664B ldr r3, .L119 + 490 0162 1B68 ldr r3, [r3] + 491 0164 9B05 lsls r3, r3, #22 + 492 0166 03D5 bpl .L38 + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 493 .loc 1 461 0 is_stmt 0 discriminator 1 + 494 0168 E369 ldr r3, [r4, #28] + 495 016a 002B cmp r3, #0 + 496 016c 00D1 bne .LCB464 + 497 016e E8E1 b .L86 @long jump + 498 .LCB464: + 499 .L38: + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 500 .loc 1 475 0 is_stmt 1 + 501 0170 606A ldr r0, [r4, #36] + 502 0172 624B ldr r3, .L119 + 503 0174 5B68 ldr r3, [r3, #4] + 504 0176 E022 movs r2, #224 + 505 0178 1202 lsls r2, r2, #8 + 506 017a 1340 ands r3, r2 + 507 017c 9842 cmp r0, r3 + 508 017e 5CD9 bls .L39 + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 509 .loc 1 478 0 + 510 0180 FFF7FEFF bl RCC_SetFlashLatencyFromMSIRange + 511 .LVL24: + 512 0184 0028 cmp r0, #0 + 513 0186 00D0 beq .LCB477 + 514 0188 DDE1 b .L87 @long jump + 515 .LCB477: + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 516 .loc 1 484 0 + 517 018a 5C4A ldr r2, .L119 + 518 018c 5368 ldr r3, [r2, #4] + 519 018e 6049 ldr r1, .L119+20 + 520 0190 0B40 ands r3, r1 + 521 0192 616A ldr r1, [r4, #36] + 522 0194 0B43 orrs r3, r1 + 523 0196 5360 str r3, [r2, #4] + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + ARM GAS /tmp/cchbc9tY.s page 37 + + + 524 .loc 1 486 0 + 525 0198 5368 ldr r3, [r2, #4] + 526 019a 1B02 lsls r3, r3, #8 + 527 019c 1B0A lsrs r3, r3, #8 + 528 019e 216A ldr r1, [r4, #32] + 529 01a0 0906 lsls r1, r1, #24 + 530 01a2 0B43 orrs r3, r1 + 531 01a4 5360 str r3, [r2, #4] + 532 .L40: + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER + 533 .loc 1 504 0 + 534 01a6 636A ldr r3, [r4, #36] + 535 01a8 5A0B lsrs r2, r3, #13 + 536 01aa 0132 adds r2, r2, #1 + 537 01ac 8023 movs r3, #128 + 538 01ae 1B02 lsls r3, r3, #8 + 539 01b0 9340 lsls r3, r3, r2 + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 540 .loc 1 505 0 + 541 01b2 524A ldr r2, .L119 + 542 01b4 D168 ldr r1, [r2, #12] + 543 01b6 0909 lsrs r1, r1, #4 + 544 01b8 0F22 movs r2, #15 + 545 01ba 0A40 ands r2, r1 + 546 01bc 5549 ldr r1, .L119+24 + 547 01be 8A5C ldrb r2, [r1, r2] + 548 01c0 D340 lsrs r3, r3, r2 + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER + 549 .loc 1 504 0 + 550 01c2 554A ldr r2, .L119+28 + 551 01c4 1360 str r3, [r2] + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 552 .loc 1 508 0 + 553 01c6 0320 movs r0, #3 + 554 01c8 FFF7FEFF bl HAL_InitTick + 555 .LVL25: + 556 .L36: + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 557 .loc 1 563 0 + 558 01cc 2368 ldr r3, [r4] + 559 01ce 1B07 lsls r3, r3, #28 + 560 01d0 00D4 bmi .LCB524 + 561 01d2 A5E0 b .L46 @long jump + 562 .LCB524: + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 563 .loc 1 569 0 + 564 01d4 6369 ldr r3, [r4, #20] + 565 01d6 002B cmp r3, #0 + 566 01d8 7CD0 beq .L47 + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 567 .loc 1 572 0 + 568 01da 484A ldr r2, .L119 + 569 01dc 136D ldr r3, [r2, #80] + 570 01de 0121 movs r1, #1 + 571 01e0 0B43 orrs r3, r1 + 572 01e2 1365 str r3, [r2, #80] + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + ARM GAS /tmp/cchbc9tY.s page 38 + + + 573 .loc 1 575 0 + 574 01e4 FFF7FEFF bl HAL_GetTick + 575 .LVL26: + 576 01e8 0500 movs r5, r0 + 577 .LVL27: + 578 .L48: + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 579 .loc 1 578 0 + 580 01ea 444B ldr r3, .L119 + 581 01ec 1B6D ldr r3, [r3, #80] + 582 01ee 9B07 lsls r3, r3, #30 + 583 01f0 00D5 bpl .LCB546 + 584 01f2 95E0 b .L46 @long jump + 585 .LCB546: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 586 .loc 1 580 0 + 587 01f4 FFF7FEFF bl HAL_GetTick + 588 .LVL28: + 589 01f8 401B subs r0, r0, r5 + 590 01fa 0228 cmp r0, #2 + 591 01fc F5D9 bls .L48 + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 592 .loc 1 582 0 + 593 01fe 0320 movs r0, #3 + 594 0200 A4E1 b .L18 + 595 .L109: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 596 .loc 1 434 0 + 597 0202 3E49 ldr r1, .L119 + 598 0204 4B68 ldr r3, [r1, #4] + 599 0206 414A ldr r2, .L119+16 + 600 0208 1340 ands r3, r2 + 601 020a 2269 ldr r2, [r4, #16] + 602 020c 1202 lsls r2, r2, #8 + 603 020e 1343 orrs r3, r2 + 604 0210 4B60 str r3, [r1, #4] + 605 0212 9CE7 b .L27 + 606 .LVL29: + 607 .L31: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 608 .loc 1 439 0 + 609 0214 394A ldr r2, .L119 + 610 0216 1368 ldr r3, [r2] + 611 0218 0121 movs r1, #1 + 612 021a 8B43 bics r3, r1 + 613 021c 1360 str r3, [r2] + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 614 .loc 1 442 0 + 615 021e FFF7FEFF bl HAL_GetTick + 616 .LVL30: + 617 0222 0500 movs r5, r0 + 618 .LVL31: + 619 .L34: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 620 .loc 1 445 0 + 621 0224 354B ldr r3, .L119 + 622 0226 1B68 ldr r3, [r3] + ARM GAS /tmp/cchbc9tY.s page 39 + + + 623 0228 5B07 lsls r3, r3, #29 + 624 022a 90D5 bpl .L27 + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 625 .loc 1 447 0 + 626 022c FFF7FEFF bl HAL_GetTick + 627 .LVL32: + 628 0230 401B subs r0, r0, r5 + 629 0232 0228 cmp r0, #2 + 630 0234 F6D9 bls .L34 + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 631 .loc 1 449 0 + 632 0236 0320 movs r0, #3 + 633 0238 88E1 b .L18 + 634 .LVL33: + 635 .L39: + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 636 .loc 1 492 0 + 637 023a 304A ldr r2, .L119 + 638 023c 5368 ldr r3, [r2, #4] + 639 023e 3449 ldr r1, .L119+20 + 640 0240 0B40 ands r3, r1 + 641 0242 1843 orrs r0, r3 + 642 0244 5060 str r0, [r2, #4] + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 643 .loc 1 494 0 + 644 0246 5368 ldr r3, [r2, #4] + 645 0248 1B02 lsls r3, r3, #8 + 646 024a 1B0A lsrs r3, r3, #8 + 647 024c 216A ldr r1, [r4, #32] + 648 024e 0906 lsls r1, r1, #24 + 649 0250 0B43 orrs r3, r1 + 650 0252 5360 str r3, [r2, #4] + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 651 .loc 1 497 0 + 652 0254 606A ldr r0, [r4, #36] + 653 0256 FFF7FEFF bl RCC_SetFlashLatencyFromMSIRange + 654 .LVL34: + 655 025a 0028 cmp r0, #0 + 656 025c A3D0 beq .L40 + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 657 .loc 1 499 0 + 658 025e 0120 movs r0, #1 + 659 0260 74E1 b .L18 + 660 .L37: + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 661 .loc 1 517 0 + 662 0262 E369 ldr r3, [r4, #28] + 663 0264 002B cmp r3, #0 + 664 0266 22D0 beq .L41 + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 665 .loc 1 520 0 + 666 0268 244A ldr r2, .L119 + 667 026a 1168 ldr r1, [r2] + 668 026c 8023 movs r3, #128 + 669 026e 5B00 lsls r3, r3, #1 + 670 0270 0B43 orrs r3, r1 + 671 0272 1360 str r3, [r2] + ARM GAS /tmp/cchbc9tY.s page 40 + + + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 672 .loc 1 523 0 + 673 0274 FFF7FEFF bl HAL_GetTick + 674 .LVL35: + 675 0278 0500 movs r5, r0 + 676 .LVL36: + 677 .L42: + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 678 .loc 1 526 0 + 679 027a 204B ldr r3, .L119 + 680 027c 1B68 ldr r3, [r3] + 681 027e 9B05 lsls r3, r3, #22 + 682 0280 06D4 bmi .L110 + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 683 .loc 1 528 0 + 684 0282 FFF7FEFF bl HAL_GetTick + 685 .LVL37: + 686 0286 401B subs r0, r0, r5 + 687 0288 0228 cmp r0, #2 + 688 028a F6D9 bls .L42 + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 689 .loc 1 530 0 + 690 028c 0320 movs r0, #3 + 691 028e 5DE1 b .L18 + 692 .L110: + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + 693 .loc 1 538 0 + 694 0290 1A4A ldr r2, .L119 + 695 0292 5368 ldr r3, [r2, #4] + 696 0294 1E49 ldr r1, .L119+20 + 697 0296 0B40 ands r3, r1 + 698 0298 616A ldr r1, [r4, #36] + 699 029a 0B43 orrs r3, r1 + 700 029c 5360 str r3, [r2, #4] + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 701 .loc 1 540 0 + 702 029e 5368 ldr r3, [r2, #4] + 703 02a0 1B02 lsls r3, r3, #8 + 704 02a2 1B0A lsrs r3, r3, #8 + 705 02a4 216A ldr r1, [r4, #32] + 706 02a6 0906 lsls r1, r1, #24 + 707 02a8 0B43 orrs r3, r1 + 708 02aa 5360 str r3, [r2, #4] + 709 02ac 8EE7 b .L36 + 710 .LVL38: + 711 .L41: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 712 .loc 1 546 0 + 713 02ae 134A ldr r2, .L119 + 714 02b0 1368 ldr r3, [r2] + 715 02b2 1A49 ldr r1, .L119+32 + 716 02b4 0B40 ands r3, r1 + 717 02b6 1360 str r3, [r2] + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 718 .loc 1 549 0 + 719 02b8 FFF7FEFF bl HAL_GetTick + 720 .LVL39: + ARM GAS /tmp/cchbc9tY.s page 41 + + + 721 02bc 0500 movs r5, r0 + 722 .LVL40: + 723 .L44: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 724 .loc 1 552 0 + 725 02be 0F4B ldr r3, .L119 + 726 02c0 1B68 ldr r3, [r3] + 727 02c2 9B05 lsls r3, r3, #22 + 728 02c4 82D5 bpl .L36 + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 729 .loc 1 554 0 + 730 02c6 FFF7FEFF bl HAL_GetTick + 731 .LVL41: + 732 02ca 401B subs r0, r0, r5 + 733 02cc 0228 cmp r0, #2 + 734 02ce F6D9 bls .L44 + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 735 .loc 1 556 0 + 736 02d0 0320 movs r0, #3 + 737 02d2 3BE1 b .L18 + 738 .LVL42: + 739 .L47: + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 740 .loc 1 589 0 + 741 02d4 094A ldr r2, .L119 + 742 02d6 136D ldr r3, [r2, #80] + 743 02d8 0121 movs r1, #1 + 744 02da 8B43 bics r3, r1 + 745 02dc 1365 str r3, [r2, #80] + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 746 .loc 1 592 0 + 747 02de FFF7FEFF bl HAL_GetTick + 748 .LVL43: + 749 02e2 0500 movs r5, r0 + 750 .LVL44: + 751 .L50: + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 752 .loc 1 595 0 + 753 02e4 054B ldr r3, .L119 + 754 02e6 1B6D ldr r3, [r3, #80] + 755 02e8 9B07 lsls r3, r3, #30 + 756 02ea 19D5 bpl .L46 + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 757 .loc 1 597 0 + 758 02ec FFF7FEFF bl HAL_GetTick + 759 .LVL45: + 760 02f0 401B subs r0, r0, r5 + 761 02f2 0228 cmp r0, #2 + 762 02f4 F6D9 bls .L50 + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 763 .loc 1 599 0 + 764 02f6 0320 movs r0, #3 + 765 02f8 28E1 b .L18 + 766 .L120: + 767 02fa C046 .align 2 + 768 .L119: + 769 02fc 00100240 .word 1073876992 + ARM GAS /tmp/cchbc9tY.s page 42 + + + 770 0300 FFFFFEFF .word -65537 + 771 0304 FFFFFBFF .word -262145 + 772 0308 88130000 .word 5000 + 773 030c FFE0FFFF .word -7937 + 774 0310 FF1FFFFF .word -57345 + 775 0314 00000000 .word AHBPrescTable + 776 0318 00000000 .word SystemCoreClock + 777 031c FFFEFFFF .word -257 + 778 .LVL46: + 779 .L46: + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 780 .loc 1 605 0 + 781 0320 2368 ldr r3, [r4] + 782 0322 5B07 lsls r3, r3, #29 + 783 0324 78D5 bpl .L52 + 784 .LVL47: + 785 .LBB8: + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 786 .loc 1 614 0 + 787 0326 8B4B ldr r3, .L121 + 788 0328 9B6B ldr r3, [r3, #56] + 789 032a DB00 lsls r3, r3, #3 + 790 032c 1BD4 bmi .L93 + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** pwrclkchanged = SET; + 791 .loc 1 616 0 + 792 032e 894A ldr r2, .L121 + 793 0330 916B ldr r1, [r2, #56] + 794 0332 8023 movs r3, #128 + 795 0334 5B05 lsls r3, r3, #21 + 796 0336 0B43 orrs r3, r1 + 797 0338 9363 str r3, [r2, #56] + 798 .LVL48: + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 799 .loc 1 617 0 + 800 033a 0125 movs r5, #1 + 801 .LVL49: + 802 .L53: + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 803 .loc 1 620 0 + 804 033c 864B ldr r3, .L121+4 + 805 033e 1B68 ldr r3, [r3] + 806 0340 DB05 lsls r3, r3, #23 + 807 0342 12D5 bpl .L111 + 808 .L54: + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 809 .loc 1 638 0 + 810 0344 A368 ldr r3, [r4, #8] + 811 0346 8022 movs r2, #128 + 812 0348 5200 lsls r2, r2, #1 + 813 034a 9342 cmp r3, r2 + 814 034c 21D0 beq .L112 + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 815 .loc 1 638 0 is_stmt 0 discriminator 2 + 816 034e 002B cmp r3, #0 + 817 0350 37D1 bne .L59 + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 818 .loc 1 638 0 discriminator 3 + ARM GAS /tmp/cchbc9tY.s page 43 + + + 819 0352 804B ldr r3, .L121 + 820 0354 1A6D ldr r2, [r3, #80] + 821 0356 8149 ldr r1, .L121+8 + 822 0358 0A40 ands r2, r1 + 823 035a 1A65 str r2, [r3, #80] + 824 035c 1A6D ldr r2, [r3, #80] + 825 035e 8049 ldr r1, .L121+12 + 826 0360 0A40 ands r2, r1 + 827 0362 1A65 str r2, [r3, #80] + 828 0364 1BE0 b .L58 + 829 .LVL50: + 830 .L93: + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 831 .loc 1 607 0 is_stmt 1 + 832 0366 0025 movs r5, #0 + 833 0368 E8E7 b .L53 + 834 .LVL51: + 835 .L111: + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 836 .loc 1 623 0 + 837 036a 7B4A ldr r2, .L121+4 + 838 036c 1168 ldr r1, [r2] + 839 036e 8023 movs r3, #128 + 840 0370 5B00 lsls r3, r3, #1 + 841 0372 0B43 orrs r3, r1 + 842 0374 1360 str r3, [r2] + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 843 .loc 1 626 0 + 844 0376 FFF7FEFF bl HAL_GetTick + 845 .LVL52: + 846 037a 0600 movs r6, r0 + 847 .LVL53: + 848 .L55: + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 849 .loc 1 628 0 + 850 037c 764B ldr r3, .L121+4 + 851 037e 1B68 ldr r3, [r3] + 852 0380 DB05 lsls r3, r3, #23 + 853 0382 DFD4 bmi .L54 + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 854 .loc 1 630 0 + 855 0384 FFF7FEFF bl HAL_GetTick + 856 .LVL54: + 857 0388 801B subs r0, r0, r6 + 858 038a 6428 cmp r0, #100 + 859 038c F6D9 bls .L55 + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 860 .loc 1 632 0 + 861 038e 0320 movs r0, #3 + 862 0390 DCE0 b .L18 + 863 .LVL55: + 864 .L112: + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 865 .loc 1 638 0 discriminator 1 + 866 0392 704A ldr r2, .L121 + 867 0394 116D ldr r1, [r2, #80] + 868 0396 8023 movs r3, #128 + ARM GAS /tmp/cchbc9tY.s page 44 + + + 869 0398 5B00 lsls r3, r3, #1 + 870 039a 0B43 orrs r3, r1 + 871 039c 1365 str r3, [r2, #80] + 872 .L58: + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 873 .loc 1 640 0 + 874 039e A368 ldr r3, [r4, #8] + 875 03a0 002B cmp r3, #0 + 876 03a2 28D0 beq .L61 + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 877 .loc 1 643 0 + 878 03a4 FFF7FEFF bl HAL_GetTick + 879 .LVL56: + 880 03a8 0600 movs r6, r0 + 881 .LVL57: + 882 .L62: + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 883 .loc 1 646 0 + 884 03aa 6A4B ldr r3, .L121 + 885 03ac 1B6D ldr r3, [r3, #80] + 886 03ae 9B05 lsls r3, r3, #22 + 887 03b0 30D4 bmi .L64 + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 888 .loc 1 648 0 + 889 03b2 FFF7FEFF bl HAL_GetTick + 890 .LVL58: + 891 03b6 801B subs r0, r0, r6 + 892 03b8 6A4B ldr r3, .L121+16 + 893 03ba 9842 cmp r0, r3 + 894 03bc F5D9 bls .L62 + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 895 .loc 1 650 0 + 896 03be 0320 movs r0, #3 + 897 03c0 C4E0 b .L18 + 898 .LVL59: + 899 .L59: + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 900 .loc 1 638 0 discriminator 4 + 901 03c2 A022 movs r2, #160 + 902 03c4 D200 lsls r2, r2, #3 + 903 03c6 9342 cmp r3, r2 + 904 03c8 09D0 beq .L113 + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 905 .loc 1 638 0 is_stmt 0 discriminator 6 + 906 03ca 624B ldr r3, .L121 + 907 03cc 1A6D ldr r2, [r3, #80] + 908 03ce 6349 ldr r1, .L121+8 + 909 03d0 0A40 ands r2, r1 + 910 03d2 1A65 str r2, [r3, #80] + 911 03d4 1A6D ldr r2, [r3, #80] + 912 03d6 6249 ldr r1, .L121+12 + 913 03d8 0A40 ands r2, r1 + 914 03da 1A65 str r2, [r3, #80] + 915 03dc DFE7 b .L58 + 916 .L113: + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the LSE State */ + 917 .loc 1 638 0 discriminator 5 + ARM GAS /tmp/cchbc9tY.s page 45 + + + 918 03de 5D4B ldr r3, .L121 + 919 03e0 196D ldr r1, [r3, #80] + 920 03e2 013A subs r2, r2, #1 + 921 03e4 FF3A subs r2, r2, #255 + 922 03e6 0A43 orrs r2, r1 + 923 03e8 1A65 str r2, [r3, #80] + 924 03ea 196D ldr r1, [r3, #80] + 925 03ec 8022 movs r2, #128 + 926 03ee 5200 lsls r2, r2, #1 + 927 03f0 0A43 orrs r2, r1 + 928 03f2 1A65 str r2, [r3, #80] + 929 03f4 D3E7 b .L58 + 930 .L61: + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 931 .loc 1 657 0 is_stmt 1 + 932 03f6 FFF7FEFF bl HAL_GetTick + 933 .LVL60: + 934 03fa 0600 movs r6, r0 + 935 .LVL61: + 936 .L65: + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 937 .loc 1 660 0 + 938 03fc 554B ldr r3, .L121 + 939 03fe 1B6D ldr r3, [r3, #80] + 940 0400 9B05 lsls r3, r3, #22 + 941 0402 07D5 bpl .L64 + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 942 .loc 1 662 0 + 943 0404 FFF7FEFF bl HAL_GetTick + 944 .LVL62: + 945 0408 801B subs r0, r0, r6 + 946 040a 564B ldr r3, .L121+16 + 947 040c 9842 cmp r0, r3 + 948 040e F5D9 bls .L65 + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 949 .loc 1 664 0 + 950 0410 0320 movs r0, #3 + 951 0412 9BE0 b .L18 + 952 .L64: + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 953 .loc 1 670 0 + 954 0414 012D cmp r5, #1 + 955 0416 21D0 beq .L114 + 956 .LVL63: + 957 .L52: + 958 .LBE8: + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 959 .loc 1 678 0 + 960 0418 2368 ldr r3, [r4] + 961 041a 9B06 lsls r3, r3, #26 + 962 041c 3CD5 bpl .L67 + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 963 .loc 1 684 0 + 964 041e A369 ldr r3, [r4, #24] + 965 0420 002B cmp r3, #0 + 966 0422 21D0 beq .L68 + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + ARM GAS /tmp/cchbc9tY.s page 46 + + + 967 .loc 1 687 0 + 968 0424 4B4B ldr r3, .L121 + 969 0426 9968 ldr r1, [r3, #8] + 970 0428 0120 movs r0, #1 + 971 042a 0143 orrs r1, r0 + 972 042c 9960 str r1, [r3, #8] + 973 042e 5A6B ldr r2, [r3, #52] + 974 0430 0243 orrs r2, r0 + 975 0432 5A63 str r2, [r3, #52] + 976 0434 4C4A ldr r2, .L121+20 + 977 0436 116A ldr r1, [r2, #32] + 978 0438 8023 movs r3, #128 + 979 043a 9B01 lsls r3, r3, #6 + 980 043c 0B43 orrs r3, r1 + 981 043e 1362 str r3, [r2, #32] + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 982 .loc 1 690 0 + 983 0440 FFF7FEFF bl HAL_GetTick + 984 .LVL64: + 985 0444 0500 movs r5, r0 + 986 .LVL65: + 987 .L69: + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 988 .loc 1 693 0 + 989 0446 434B ldr r3, .L121 + 990 0448 9B68 ldr r3, [r3, #8] + 991 044a 9B07 lsls r3, r3, #30 + 992 044c 24D4 bmi .L67 + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 993 .loc 1 695 0 + 994 044e FFF7FEFF bl HAL_GetTick + 995 .LVL66: + 996 0452 401B subs r0, r0, r5 + 997 0454 0228 cmp r0, #2 + 998 0456 F6D9 bls .L69 + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 999 .loc 1 697 0 + 1000 0458 0320 movs r0, #3 + 1001 045a 77E0 b .L18 + 1002 .LVL67: + 1003 .L114: + 1004 .LBB9: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1005 .loc 1 672 0 + 1006 045c 3D4A ldr r2, .L121 + 1007 045e 936B ldr r3, [r2, #56] + 1008 0460 4249 ldr r1, .L121+24 + 1009 0462 0B40 ands r3, r1 + 1010 0464 9363 str r3, [r2, #56] + 1011 0466 D7E7 b .L52 + 1012 .LVL68: + 1013 .L68: + 1014 .LBE9: + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1015 .loc 1 704 0 + 1016 0468 3A4A ldr r2, .L121 + 1017 046a 9368 ldr r3, [r2, #8] + ARM GAS /tmp/cchbc9tY.s page 47 + + + 1018 046c 0121 movs r1, #1 + 1019 046e 8B43 bics r3, r1 + 1020 0470 9360 str r3, [r2, #8] + 1021 0472 3D4A ldr r2, .L121+20 + 1022 0474 136A ldr r3, [r2, #32] + 1023 0476 3E49 ldr r1, .L121+28 + 1024 0478 0B40 ands r3, r1 + 1025 047a 1362 str r3, [r2, #32] + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1026 .loc 1 707 0 + 1027 047c FFF7FEFF bl HAL_GetTick + 1028 .LVL69: + 1029 0480 0500 movs r5, r0 + 1030 .LVL70: + 1031 .L71: + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1032 .loc 1 710 0 + 1033 0482 344B ldr r3, .L121 + 1034 0484 9B68 ldr r3, [r3, #8] + 1035 0486 9B07 lsls r3, r3, #30 + 1036 0488 06D5 bpl .L67 + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1037 .loc 1 712 0 + 1038 048a FFF7FEFF bl HAL_GetTick + 1039 .LVL71: + 1040 048e 401B subs r0, r0, r5 + 1041 0490 0228 cmp r0, #2 + 1042 0492 F6D9 bls .L71 + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1043 .loc 1 714 0 + 1044 0494 0320 movs r0, #3 + 1045 0496 59E0 b .L18 + 1046 .LVL72: + 1047 .L67: + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1048 .loc 1 724 0 + 1049 0498 A36A ldr r3, [r4, #40] + 1050 049a 002B cmp r3, #0 + 1051 049c 55D0 beq .L99 + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1052 .loc 1 727 0 + 1053 049e 2D4A ldr r2, .L121 + 1054 04a0 D168 ldr r1, [r2, #12] + 1055 04a2 0C22 movs r2, #12 + 1056 04a4 0A40 ands r2, r1 + 1057 04a6 0C2A cmp r2, #12 + 1058 04a8 52D0 beq .L100 + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1059 .loc 1 729 0 + 1060 04aa 022B cmp r3, #2 + 1061 04ac 12D0 beq .L115 + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1062 .loc 1 773 0 + 1063 04ae 294A ldr r2, .L121 + 1064 04b0 1368 ldr r3, [r2] + 1065 04b2 3049 ldr r1, .L121+32 + 1066 04b4 0B40 ands r3, r1 + ARM GAS /tmp/cchbc9tY.s page 48 + + + 1067 04b6 1360 str r3, [r2] + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1068 .loc 1 776 0 + 1069 04b8 FFF7FEFF bl HAL_GetTick + 1070 .LVL73: + 1071 04bc 0400 movs r4, r0 + 1072 .LVL74: + 1073 .L78: + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1074 .loc 1 779 0 + 1075 04be 254B ldr r3, .L121 + 1076 04c0 1B68 ldr r3, [r3] + 1077 04c2 9B01 lsls r3, r3, #6 + 1078 04c4 39D5 bpl .L116 + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1079 .loc 1 781 0 + 1080 04c6 FFF7FEFF bl HAL_GetTick + 1081 .LVL75: + 1082 04ca 001B subs r0, r0, r4 + 1083 04cc 0228 cmp r0, #2 + 1084 04ce F6D9 bls .L78 + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1085 .loc 1 783 0 + 1086 04d0 0320 movs r0, #3 + 1087 04d2 3BE0 b .L18 + 1088 .LVL76: + 1089 .L115: + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1090 .loc 1 737 0 + 1091 04d4 1F4A ldr r2, .L121 + 1092 04d6 1368 ldr r3, [r2] + 1093 04d8 2649 ldr r1, .L121+32 + 1094 04da 0B40 ands r3, r1 + 1095 04dc 1360 str r3, [r2] + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1096 .loc 1 740 0 + 1097 04de FFF7FEFF bl HAL_GetTick + 1098 .LVL77: + 1099 04e2 0500 movs r5, r0 + 1100 .LVL78: + 1101 .L74: + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1102 .loc 1 743 0 + 1103 04e4 1B4B ldr r3, .L121 + 1104 04e6 1B68 ldr r3, [r3] + 1105 04e8 9B01 lsls r3, r3, #6 + 1106 04ea 06D5 bpl .L117 + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1107 .loc 1 745 0 + 1108 04ec FFF7FEFF bl HAL_GetTick + 1109 .LVL79: + 1110 04f0 401B subs r0, r0, r5 + 1111 04f2 0228 cmp r0, #2 + 1112 04f4 F6D9 bls .L74 + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1113 .loc 1 747 0 + 1114 04f6 0320 movs r0, #3 + ARM GAS /tmp/cchbc9tY.s page 49 + + + 1115 04f8 28E0 b .L18 + 1116 .L117: + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL, + 1117 .loc 1 752 0 + 1118 04fa 1649 ldr r1, .L121 + 1119 04fc CB68 ldr r3, [r1, #12] + 1120 04fe 1E4A ldr r2, .L121+36 + 1121 0500 1340 ands r3, r2 + 1122 0502 E26A ldr r2, [r4, #44] + 1123 0504 206B ldr r0, [r4, #48] + 1124 0506 0243 orrs r2, r0 + 1125 0508 606B ldr r0, [r4, #52] + 1126 050a 0243 orrs r2, r0 + 1127 050c 1343 orrs r3, r2 + 1128 050e CB60 str r3, [r1, #12] + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1129 .loc 1 756 0 + 1130 0510 0A68 ldr r2, [r1] + 1131 0512 8023 movs r3, #128 + 1132 0514 5B04 lsls r3, r3, #17 + 1133 0516 1343 orrs r3, r2 + 1134 0518 0B60 str r3, [r1] + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1135 .loc 1 759 0 + 1136 051a FFF7FEFF bl HAL_GetTick + 1137 .LVL80: + 1138 051e 0400 movs r4, r0 + 1139 .LVL81: + 1140 .L76: + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1141 .loc 1 762 0 + 1142 0520 0C4B ldr r3, .L121 + 1143 0522 1B68 ldr r3, [r3] + 1144 0524 9B01 lsls r3, r3, #6 + 1145 0526 06D4 bmi .L118 + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1146 .loc 1 764 0 + 1147 0528 FFF7FEFF bl HAL_GetTick + 1148 .LVL82: + 1149 052c 001B subs r0, r0, r4 + 1150 052e 0228 cmp r0, #2 + 1151 0530 F6D9 bls .L76 + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1152 .loc 1 766 0 + 1153 0532 0320 movs r0, #3 + 1154 0534 0AE0 b .L18 + 1155 .L118: + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1156 .loc 1 794 0 + 1157 0536 0020 movs r0, #0 + 1158 0538 08E0 b .L18 + 1159 .L116: + 1160 053a 0020 movs r0, #0 + 1161 053c 06E0 b .L18 + 1162 .LVL83: + 1163 .L107: + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + ARM GAS /tmp/cchbc9tY.s page 50 + + + 1164 .loc 1 350 0 + 1165 053e 0120 movs r0, #1 + 1166 .LVL84: + 1167 0540 04E0 b .L18 + 1168 .LVL85: + 1169 .L86: + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1170 .loc 1 463 0 + 1171 0542 0120 movs r0, #1 + 1172 0544 02E0 b .L18 + 1173 .L87: + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1174 .loc 1 480 0 + 1175 0546 0120 movs r0, #1 + 1176 0548 00E0 b .L18 + 1177 .L99: + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1178 .loc 1 794 0 + 1179 054a 0020 movs r0, #0 + 1180 .LVL86: + 1181 .L18: + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1182 .loc 1 795 0 + 1183 054c 02B0 add sp, sp, #8 + 1184 @ sp needed + 1185 054e 70BD pop {r4, r5, r6, pc} + 1186 .LVL87: + 1187 .L100: + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1188 .loc 1 790 0 + 1189 0550 0120 movs r0, #1 + 1190 0552 FBE7 b .L18 + 1191 .L122: + 1192 .align 2 + 1193 .L121: + 1194 0554 00100240 .word 1073876992 + 1195 0558 00700040 .word 1073770496 + 1196 055c FFFEFFFF .word -257 + 1197 0560 FFFBFFFF .word -1025 + 1198 0564 88130000 .word 5000 + 1199 0568 00000140 .word 1073807360 + 1200 056c FFFFFFEF .word -268435457 + 1201 0570 FFDFFFFF .word -8193 + 1202 0574 FFFFFFFE .word -16777217 + 1203 0578 FFFF02FF .word -16580609 + 1204 .cfi_endproc + 1205 .LFE40: + 1207 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 1208 .align 1 + 1209 .global HAL_RCC_MCOConfig + 1210 .syntax unified + 1211 .code 16 + 1212 .thumb_func + 1213 .fpu softvfp + 1215 HAL_RCC_MCOConfig: + 1216 .LFB42: +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** GPIO_InitTypeDef gpio = {0}; + ARM GAS /tmp/cchbc9tY.s page 51 + + + 1217 .loc 1 1061 0 + 1218 .cfi_startproc + 1219 @ args = 0, pretend = 0, frame = 32 + 1220 @ frame_needed = 0, uses_anonymous_args = 0 + 1221 .LVL88: + 1222 0000 70B5 push {r4, r5, r6, lr} + 1223 .LCFI4: + 1224 .cfi_def_cfa_offset 16 + 1225 .cfi_offset 4, -16 + 1226 .cfi_offset 5, -12 + 1227 .cfi_offset 6, -8 + 1228 .cfi_offset 14, -4 + 1229 0002 88B0 sub sp, sp, #32 + 1230 .LCFI5: + 1231 .cfi_def_cfa_offset 48 + 1232 0004 0500 movs r5, r0 + 1233 0006 0C00 movs r4, r1 + 1234 0008 1600 movs r6, r2 +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1235 .loc 1 1062 0 + 1236 000a 1422 movs r2, #20 + 1237 .LVL89: + 1238 000c 0021 movs r1, #0 + 1239 .LVL90: + 1240 000e 03A8 add r0, sp, #12 + 1241 .LVL91: + 1242 0010 FFF7FEFF bl memset + 1243 .LVL92: +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Speed = GPIO_SPEED_FREQ_HIGH; + 1244 .loc 1 1070 0 + 1245 0014 0223 movs r3, #2 + 1246 0016 0493 str r3, [sp, #16] +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Pull = GPIO_NOPULL; + 1247 .loc 1 1071 0 + 1248 0018 0693 str r3, [sp, #24] +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1249 .loc 1 1073 0 + 1250 001a 002D cmp r5, #0 + 1251 001c 1BD0 beq .L127 +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1252 .loc 1 1084 0 + 1253 001e 022D cmp r5, #2 + 1254 0020 2AD0 beq .L128 +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; + 1255 .loc 1 1096 0 + 1256 0022 8023 movs r3, #128 + 1257 0024 9B00 lsls r3, r3, #2 + 1258 0026 0393 str r3, [sp, #12] + 1259 .LBB10: +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &gpio); + 1260 .loc 1 1100 0 + 1261 0028 1C4A ldr r2, .L129 + 1262 002a D16A ldr r1, [r2, #44] + 1263 002c 0123 movs r3, #1 + 1264 002e 1943 orrs r1, r3 + 1265 0030 D162 str r1, [r2, #44] + 1266 0032 D26A ldr r2, [r2, #44] + ARM GAS /tmp/cchbc9tY.s page 52 + + + 1267 0034 1340 ands r3, r2 + 1268 0036 0293 str r3, [sp, #8] + 1269 0038 029B ldr r3, [sp, #8] + 1270 .LBE10: +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1271 .loc 1 1101 0 + 1272 003a A020 movs r0, #160 + 1273 003c 03A9 add r1, sp, #12 + 1274 003e C005 lsls r0, r0, #23 + 1275 0040 FFF7FEFF bl HAL_GPIO_Init + 1276 .LVL93: + 1277 .L125: +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1278 .loc 1 1105 0 + 1279 0044 154B ldr r3, .L129 + 1280 0046 DA68 ldr r2, [r3, #12] + 1281 0048 1549 ldr r1, .L129+4 + 1282 004a 0A40 ands r2, r1 + 1283 004c 3443 orrs r4, r6 + 1284 .LVL94: + 1285 004e 2243 orrs r2, r4 + 1286 0050 DA60 str r2, [r3, #12] +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1287 .loc 1 1106 0 + 1288 0052 08B0 add sp, sp, #32 + 1289 @ sp needed + 1290 .LVL95: + 1291 .LVL96: + 1292 0054 70BD pop {r4, r5, r6, pc} + 1293 .LVL97: + 1294 .L127: +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; + 1295 .loc 1 1075 0 + 1296 0056 FE33 adds r3, r3, #254 + 1297 0058 0393 str r3, [sp, #12] + 1298 .LBB11: +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + 1299 .loc 1 1079 0 + 1300 005a 104A ldr r2, .L129 + 1301 005c D16A ldr r1, [r2, #44] + 1302 005e FF3B subs r3, r3, #255 + 1303 0060 1943 orrs r1, r3 + 1304 0062 D162 str r1, [r2, #44] + 1305 0064 D26A ldr r2, [r2, #44] + 1306 0066 1340 ands r3, r2 + 1307 0068 0093 str r3, [sp] + 1308 006a 009B ldr r3, [sp] + 1309 .LBE11: +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1310 .loc 1 1080 0 + 1311 006c A020 movs r0, #160 + 1312 006e 03A9 add r1, sp, #12 + 1313 0070 C005 lsls r0, r0, #23 + 1314 0072 FFF7FEFF bl HAL_GPIO_Init + 1315 .LVL98: + 1316 0076 E5E7 b .L125 + 1317 .L128: + ARM GAS /tmp/cchbc9tY.s page 53 + + +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** gpio.Alternate = GPIO_AF2_MCO; + 1318 .loc 1 1086 0 + 1319 0078 8023 movs r3, #128 + 1320 007a 9B01 lsls r3, r3, #6 + 1321 007c 0393 str r3, [sp, #12] +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1322 .loc 1 1087 0 + 1323 007e 0223 movs r3, #2 + 1324 0080 0793 str r3, [sp, #28] + 1325 .LBB12: +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** HAL_GPIO_Init(MCO3_GPIO_PORT, &gpio); + 1326 .loc 1 1090 0 + 1327 0082 064A ldr r2, .L129 + 1328 0084 D16A ldr r1, [r2, #44] + 1329 0086 1943 orrs r1, r3 + 1330 0088 D162 str r1, [r2, #44] + 1331 008a D26A ldr r2, [r2, #44] + 1332 008c 1340 ands r3, r2 + 1333 008e 0193 str r3, [sp, #4] + 1334 0090 019B ldr r3, [sp, #4] + 1335 .LBE12: +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1336 .loc 1 1091 0 + 1337 0092 03A9 add r1, sp, #12 + 1338 0094 0348 ldr r0, .L129+8 + 1339 0096 FFF7FEFF bl HAL_GPIO_Init + 1340 .LVL99: + 1341 009a D3E7 b .L125 + 1342 .L130: + 1343 .align 2 + 1344 .L129: + 1345 009c 00100240 .word 1073876992 + 1346 00a0 FFFFFF80 .word -2130706433 + 1347 00a4 00040050 .word 1342178304 + 1348 .cfi_endproc + 1349 .LFE42: + 1351 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 1352 .align 1 + 1353 .global HAL_RCC_EnableCSS + 1354 .syntax unified + 1355 .code 16 + 1356 .thumb_func + 1357 .fpu softvfp + 1359 HAL_RCC_EnableCSS: + 1360 .LFB43: +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSON) ; + 1361 .loc 1 1119 0 + 1362 .cfi_startproc + 1363 @ args = 0, pretend = 0, frame = 0 + 1364 @ frame_needed = 0, uses_anonymous_args = 0 + 1365 @ link register save eliminated. +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1366 .loc 1 1120 0 + 1367 0000 034A ldr r2, .L132 + 1368 0002 1168 ldr r1, [r2] + 1369 0004 8023 movs r3, #128 + 1370 0006 1B03 lsls r3, r3, #12 + ARM GAS /tmp/cchbc9tY.s page 54 + + + 1371 0008 0B43 orrs r3, r1 + 1372 000a 1360 str r3, [r2] +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1373 .loc 1 1121 0 + 1374 @ sp needed + 1375 000c 7047 bx lr + 1376 .L133: + 1377 000e C046 .align 2 + 1378 .L132: + 1379 0010 00100240 .word 1073876992 + 1380 .cfi_endproc + 1381 .LFE43: + 1383 .global __aeabi_uidiv + 1384 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 1385 .align 1 + 1386 .global HAL_RCC_GetSysClockFreq + 1387 .syntax unified + 1388 .code 16 + 1389 .thumb_func + 1390 .fpu softvfp + 1392 HAL_RCC_GetSysClockFreq: + 1393 .LFB44: +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0; + 1394 .loc 1 1155 0 + 1395 .cfi_startproc + 1396 @ args = 0, pretend = 0, frame = 0 + 1397 @ frame_needed = 0, uses_anonymous_args = 0 + 1398 0000 10B5 push {r4, lr} + 1399 .LCFI6: + 1400 .cfi_def_cfa_offset 8 + 1401 .cfi_offset 4, -8 + 1402 .cfi_offset 14, -4 + 1403 .LVL100: +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1404 .loc 1 1159 0 + 1405 0002 264B ldr r3, .L146 + 1406 0004 D968 ldr r1, [r3, #12] + 1407 .LVL101: +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1408 .loc 1 1162 0 + 1409 0006 0C23 movs r3, #12 + 1410 0008 0B40 ands r3, r1 + 1411 000a 082B cmp r3, #8 + 1412 000c 42D0 beq .L141 + 1413 000e 0C2B cmp r3, #12 + 1414 0010 11D0 beq .L137 + 1415 0012 042B cmp r3, #4 + 1416 0014 09D0 beq .L144 +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** sysclockfreq = (32768 * (1 << (msiclkrange + 1))); + 1417 .loc 1 1207 0 + 1418 0016 214B ldr r3, .L146 + 1419 0018 5A68 ldr r2, [r3, #4] + 1420 001a 520B lsrs r2, r2, #13 + 1421 001c 0723 movs r3, #7 + 1422 001e 1340 ands r3, r2 + 1423 .LVL102: +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; + ARM GAS /tmp/cchbc9tY.s page 55 + + + 1424 .loc 1 1208 0 + 1425 0020 0133 adds r3, r3, #1 + 1426 .LVL103: + 1427 0022 8020 movs r0, #128 + 1428 0024 0002 lsls r0, r0, #8 + 1429 0026 9840 lsls r0, r0, r3 + 1430 .LVL104: + 1431 .L134: +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1432 .loc 1 1213 0 + 1433 @ sp needed + 1434 0028 10BD pop {r4, pc} + 1435 .LVL105: + 1436 .L144: +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1437 .loc 1 1166 0 + 1438 002a 1C4B ldr r3, .L146 + 1439 002c 1B68 ldr r3, [r3] + 1440 002e DB06 lsls r3, r3, #27 + 1441 0030 32D5 bpl .L142 +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1442 .loc 1 1168 0 + 1443 0032 1B48 ldr r0, .L146+4 + 1444 0034 F8E7 b .L134 + 1445 .L137: +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1; + 1446 .loc 1 1183 0 + 1447 0036 8A0C lsrs r2, r1, #18 + 1448 0038 0F23 movs r3, #15 + 1449 003a 1340 ands r3, r2 + 1450 003c 194A ldr r2, .L146+8 + 1451 003e D05C ldrb r0, [r2, r3] + 1452 .LVL106: +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 1453 .loc 1 1184 0 + 1454 0040 890D lsrs r1, r1, #22 + 1455 .LVL107: + 1456 0042 0322 movs r2, #3 + 1457 0044 1140 ands r1, r2 + 1458 0046 0131 adds r1, r1, #1 + 1459 .LVL108: +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1460 .loc 1 1185 0 + 1461 0048 144B ldr r3, .L146 + 1462 004a DB68 ldr r3, [r3, #12] + 1463 004c DB03 lsls r3, r3, #15 + 1464 004e 0DD4 bmi .L145 +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1465 .loc 1 1192 0 + 1466 0050 124B ldr r3, .L146 + 1467 0052 1B68 ldr r3, [r3] + 1468 0054 DB06 lsls r3, r3, #27 + 1469 0056 13D5 bpl .L140 +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1470 .loc 1 1194 0 + 1471 0058 4201 lsls r2, r0, #5 + 1472 005a 121A subs r2, r2, r0 + ARM GAS /tmp/cchbc9tY.s page 56 + + + 1473 005c 9301 lsls r3, r2, #6 + 1474 005e 9B1A subs r3, r3, r2 + 1475 0060 DB00 lsls r3, r3, #3 + 1476 0062 1B18 adds r3, r3, r0 + 1477 0064 1802 lsls r0, r3, #8 + 1478 .LVL109: + 1479 0066 FFF7FEFF bl __aeabi_uidiv + 1480 .LVL110: + 1481 006a DDE7 b .L134 + 1482 .LVL111: + 1483 .L145: +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1484 .loc 1 1188 0 + 1485 006c 4201 lsls r2, r0, #5 + 1486 006e 121A subs r2, r2, r0 + 1487 0070 9301 lsls r3, r2, #6 + 1488 0072 9B1A subs r3, r3, r2 + 1489 0074 DB00 lsls r3, r3, #3 + 1490 0076 1B18 adds r3, r3, r0 + 1491 0078 5802 lsls r0, r3, #9 + 1492 .LVL112: + 1493 007a FFF7FEFF bl __aeabi_uidiv + 1494 .LVL113: + 1495 007e D3E7 b .L134 + 1496 .LVL114: + 1497 .L140: +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1498 .loc 1 1198 0 + 1499 0080 4201 lsls r2, r0, #5 + 1500 0082 121A subs r2, r2, r0 + 1501 0084 9301 lsls r3, r2, #6 + 1502 0086 9B1A subs r3, r3, r2 + 1503 0088 DB00 lsls r3, r3, #3 + 1504 008a 1B18 adds r3, r3, r0 + 1505 008c 9802 lsls r0, r3, #10 + 1506 .LVL115: + 1507 008e FFF7FEFF bl __aeabi_uidiv + 1508 .LVL116: + 1509 0092 C9E7 b .L134 + 1510 .LVL117: + 1511 .L141: +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** break; + 1512 .loc 1 1178 0 + 1513 0094 0448 ldr r0, .L146+12 + 1514 0096 C7E7 b .L134 + 1515 .L142: +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1516 .loc 1 1172 0 + 1517 0098 0448 ldr r0, .L146+16 + 1518 .LVL118: +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1519 .loc 1 1212 0 + 1520 009a C5E7 b .L134 + 1521 .L147: + 1522 .align 2 + 1523 .L146: + 1524 009c 00100240 .word 1073876992 + ARM GAS /tmp/cchbc9tY.s page 57 + + + 1525 00a0 00093D00 .word 4000000 + 1526 00a4 00000000 .word PLLMulTable + 1527 00a8 00127A00 .word 8000000 + 1528 00ac 0024F400 .word 16000000 + 1529 .cfi_endproc + 1530 .LFE44: + 1532 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 1533 .align 1 + 1534 .global HAL_RCC_ClockConfig + 1535 .syntax unified + 1536 .code 16 + 1537 .thumb_func + 1538 .fpu softvfp + 1540 HAL_RCC_ClockConfig: + 1541 .LFB41: + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** uint32_t tickstart = 0U; + 1542 .loc 1 824 0 + 1543 .cfi_startproc + 1544 @ args = 0, pretend = 0, frame = 0 + 1545 @ frame_needed = 0, uses_anonymous_args = 0 + 1546 .LVL119: + 1547 0000 70B5 push {r4, r5, r6, lr} + 1548 .LCFI7: + 1549 .cfi_def_cfa_offset 16 + 1550 .cfi_offset 4, -16 + 1551 .cfi_offset 5, -12 + 1552 .cfi_offset 6, -8 + 1553 .cfi_offset 14, -4 + 1554 0002 0400 movs r4, r0 + 1555 0004 0D00 movs r5, r1 + 1556 .LVL120: + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1557 .loc 1 837 0 + 1558 0006 5F4B ldr r3, .L186 + 1559 0008 1A68 ldr r2, [r3] + 1560 000a 0123 movs r3, #1 + 1561 000c 1340 ands r3, r2 + 1562 000e 8B42 cmp r3, r1 + 1563 0010 0BD2 bcs .L149 + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1564 .loc 1 840 0 + 1565 0012 5C49 ldr r1, .L186 + 1566 .LVL121: + 1567 0014 0B68 ldr r3, [r1] + 1568 0016 0122 movs r2, #1 + 1569 0018 9343 bics r3, r2 + 1570 001a 2B43 orrs r3, r5 + 1571 001c 0B60 str r3, [r1] + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1572 .loc 1 844 0 + 1573 001e 0B68 ldr r3, [r1] + 1574 0020 1A40 ands r2, r3 + 1575 0022 AA42 cmp r2, r5 + 1576 0024 01D0 beq .L149 + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1577 .loc 1 846 0 + 1578 0026 0120 movs r0, #1 + ARM GAS /tmp/cchbc9tY.s page 58 + + + 1579 .LVL122: + 1580 .L150: + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1581 .loc 1 979 0 + 1582 @ sp needed + 1583 .LVL123: + 1584 .LVL124: + 1585 0028 70BD pop {r4, r5, r6, pc} + 1586 .LVL125: + 1587 .L149: + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1588 .loc 1 851 0 + 1589 002a 2368 ldr r3, [r4] + 1590 002c 9B07 lsls r3, r3, #30 + 1591 002e 06D5 bpl .L151 + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1592 .loc 1 854 0 + 1593 0030 554A ldr r2, .L186+4 + 1594 0032 D368 ldr r3, [r2, #12] + 1595 0034 F021 movs r1, #240 + 1596 0036 8B43 bics r3, r1 + 1597 0038 A168 ldr r1, [r4, #8] + 1598 003a 0B43 orrs r3, r1 + 1599 003c D360 str r3, [r2, #12] + 1600 .L151: + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1601 .loc 1 858 0 + 1602 003e 2368 ldr r3, [r4] + 1603 0040 DB07 lsls r3, r3, #31 + 1604 0042 64D5 bpl .L152 + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1605 .loc 1 863 0 + 1606 0044 6368 ldr r3, [r4, #4] + 1607 0046 022B cmp r3, #2 + 1608 0048 09D0 beq .L182 + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1609 .loc 1 872 0 + 1610 004a 032B cmp r3, #3 + 1611 004c 29D0 beq .L183 + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1612 .loc 1 881 0 + 1613 004e 012B cmp r3, #1 + 1614 0050 2DD0 beq .L184 + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1615 .loc 1 893 0 + 1616 0052 4D4A ldr r2, .L186+4 + 1617 0054 1268 ldr r2, [r2] + 1618 0056 9205 lsls r2, r2, #22 + 1619 0058 06D4 bmi .L154 + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1620 .loc 1 895 0 + 1621 005a 0120 movs r0, #1 + 1622 .LVL126: + 1623 005c E4E7 b .L150 + 1624 .LVL127: + 1625 .L182: + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + ARM GAS /tmp/cchbc9tY.s page 59 + + + 1626 .loc 1 866 0 + 1627 005e 4A4A ldr r2, .L186+4 + 1628 0060 1268 ldr r2, [r2] + 1629 0062 9203 lsls r2, r2, #14 + 1630 0064 00D4 bmi .LCB1665 + 1631 0066 8AE0 b .L185 @long jump + 1632 .LCB1665: + 1633 .L154: + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1634 .loc 1 898 0 + 1635 0068 4749 ldr r1, .L186+4 + 1636 006a CA68 ldr r2, [r1, #12] + 1637 006c 0320 movs r0, #3 + 1638 .LVL128: + 1639 006e 8243 bics r2, r0 + 1640 0070 1343 orrs r3, r2 + 1641 0072 CB60 str r3, [r1, #12] + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1642 .loc 1 901 0 + 1643 0074 FFF7FEFF bl HAL_GetTick + 1644 .LVL129: + 1645 0078 0600 movs r6, r0 + 1646 .LVL130: + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1647 .loc 1 903 0 + 1648 007a 6368 ldr r3, [r4, #4] + 1649 007c 022B cmp r3, #2 + 1650 007e 1CD0 beq .L157 + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1651 .loc 1 913 0 + 1652 0080 032B cmp r3, #3 + 1653 0082 28D0 beq .L160 + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1654 .loc 1 923 0 + 1655 0084 012B cmp r3, #1 + 1656 0086 34D0 beq .L163 + 1657 .LVL131: + 1658 .L164: + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1659 .loc 1 935 0 + 1660 0088 3F4B ldr r3, .L186+4 + 1661 008a DB68 ldr r3, [r3, #12] + 1662 008c 0C22 movs r2, #12 + 1663 008e 1A42 tst r2, r3 + 1664 0090 3DD0 beq .L152 + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1665 .loc 1 937 0 + 1666 0092 FFF7FEFF bl HAL_GetTick + 1667 .LVL132: + 1668 0096 801B subs r0, r0, r6 + 1669 0098 3C4B ldr r3, .L186+8 + 1670 009a 9842 cmp r0, r3 + 1671 009c F4D9 bls .L164 + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1672 .loc 1 939 0 + 1673 009e 0320 movs r0, #3 + 1674 00a0 C2E7 b .L150 + ARM GAS /tmp/cchbc9tY.s page 60 + + + 1675 .LVL133: + 1676 .L183: + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1677 .loc 1 875 0 + 1678 00a2 394A ldr r2, .L186+4 + 1679 00a4 1268 ldr r2, [r2] + 1680 00a6 9201 lsls r2, r2, #6 + 1681 00a8 DED4 bmi .L154 + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1682 .loc 1 877 0 + 1683 00aa 0120 movs r0, #1 + 1684 .LVL134: + 1685 00ac BCE7 b .L150 + 1686 .LVL135: + 1687 .L184: + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1688 .loc 1 884 0 + 1689 00ae 364A ldr r2, .L186+4 + 1690 00b0 1268 ldr r2, [r2] + 1691 00b2 5207 lsls r2, r2, #29 + 1692 00b4 D8D4 bmi .L154 + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1693 .loc 1 886 0 + 1694 00b6 0120 movs r0, #1 + 1695 .LVL136: + 1696 00b8 B6E7 b .L150 + 1697 .LVL137: + 1698 .L157: + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1699 .loc 1 905 0 + 1700 00ba 334B ldr r3, .L186+4 + 1701 00bc DA68 ldr r2, [r3, #12] + 1702 00be 0C23 movs r3, #12 + 1703 00c0 1340 ands r3, r2 + 1704 00c2 082B cmp r3, #8 + 1705 00c4 23D0 beq .L152 + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1706 .loc 1 907 0 + 1707 00c6 FFF7FEFF bl HAL_GetTick + 1708 .LVL138: + 1709 00ca 801B subs r0, r0, r6 + 1710 00cc 2F4B ldr r3, .L186+8 + 1711 00ce 9842 cmp r0, r3 + 1712 00d0 F3D9 bls .L157 + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1713 .loc 1 909 0 + 1714 00d2 0320 movs r0, #3 + 1715 00d4 A8E7 b .L150 + 1716 .L160: + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1717 .loc 1 915 0 + 1718 00d6 2C4B ldr r3, .L186+4 + 1719 00d8 DA68 ldr r2, [r3, #12] + 1720 00da 0C23 movs r3, #12 + 1721 00dc 1340 ands r3, r2 + 1722 00de 0C2B cmp r3, #12 + 1723 00e0 15D0 beq .L152 + ARM GAS /tmp/cchbc9tY.s page 61 + + + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1724 .loc 1 917 0 + 1725 00e2 FFF7FEFF bl HAL_GetTick + 1726 .LVL139: + 1727 00e6 801B subs r0, r0, r6 + 1728 00e8 284B ldr r3, .L186+8 + 1729 00ea 9842 cmp r0, r3 + 1730 00ec F3D9 bls .L160 + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1731 .loc 1 919 0 + 1732 00ee 0320 movs r0, #3 + 1733 00f0 9AE7 b .L150 + 1734 .L163: + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1735 .loc 1 925 0 + 1736 00f2 254B ldr r3, .L186+4 + 1737 00f4 DA68 ldr r2, [r3, #12] + 1738 00f6 0C23 movs r3, #12 + 1739 00f8 1340 ands r3, r2 + 1740 00fa 042B cmp r3, #4 + 1741 00fc 07D0 beq .L152 + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1742 .loc 1 927 0 + 1743 00fe FFF7FEFF bl HAL_GetTick + 1744 .LVL140: + 1745 0102 801B subs r0, r0, r6 + 1746 0104 214B ldr r3, .L186+8 + 1747 0106 9842 cmp r0, r3 + 1748 0108 F3D9 bls .L163 + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1749 .loc 1 929 0 + 1750 010a 0320 movs r0, #3 + 1751 010c 8CE7 b .L150 + 1752 .LVL141: + 1753 .L152: + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1754 .loc 1 945 0 + 1755 010e 1D4B ldr r3, .L186 + 1756 0110 1A68 ldr r2, [r3] + 1757 0112 0123 movs r3, #1 + 1758 0114 1340 ands r3, r2 + 1759 0116 AB42 cmp r3, r5 + 1760 0118 0BD9 bls .L167 + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1761 .loc 1 948 0 + 1762 011a 1A49 ldr r1, .L186 + 1763 011c 0B68 ldr r3, [r1] + 1764 011e 0122 movs r2, #1 + 1765 0120 9343 bics r3, r2 + 1766 0122 2B43 orrs r3, r5 + 1767 0124 0B60 str r3, [r1] + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1768 .loc 1 952 0 + 1769 0126 0B68 ldr r3, [r1] + 1770 0128 1A40 ands r2, r3 + 1771 012a AA42 cmp r2, r5 + 1772 012c 01D0 beq .L167 + ARM GAS /tmp/cchbc9tY.s page 62 + + + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1773 .loc 1 954 0 + 1774 012e 0120 movs r0, #1 + 1775 0130 7AE7 b .L150 + 1776 .L167: + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1777 .loc 1 959 0 + 1778 0132 2368 ldr r3, [r4] + 1779 0134 5B07 lsls r3, r3, #29 + 1780 0136 06D5 bpl .L168 + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1781 .loc 1 962 0 + 1782 0138 134A ldr r2, .L186+4 + 1783 013a D368 ldr r3, [r2, #12] + 1784 013c 1449 ldr r1, .L186+12 + 1785 013e 0B40 ands r3, r1 + 1786 0140 E168 ldr r1, [r4, #12] + 1787 0142 0B43 orrs r3, r1 + 1788 0144 D360 str r3, [r2, #12] + 1789 .L168: + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1790 .loc 1 966 0 + 1791 0146 2368 ldr r3, [r4] + 1792 0148 1B07 lsls r3, r3, #28 + 1793 014a 07D5 bpl .L169 + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1794 .loc 1 969 0 + 1795 014c 0E49 ldr r1, .L186+4 + 1796 014e CB68 ldr r3, [r1, #12] + 1797 0150 104A ldr r2, .L186+16 + 1798 0152 1340 ands r3, r2 + 1799 0154 2269 ldr r2, [r4, #16] + 1800 0156 D200 lsls r2, r2, #3 + 1801 0158 1343 orrs r3, r2 + 1802 015a CB60 str r3, [r1, #12] + 1803 .L169: + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1804 .loc 1 973 0 + 1805 015c FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1806 .LVL142: + 1807 0160 094B ldr r3, .L186+4 + 1808 0162 DA68 ldr r2, [r3, #12] + 1809 0164 1209 lsrs r2, r2, #4 + 1810 0166 0F23 movs r3, #15 + 1811 0168 1340 ands r3, r2 + 1812 016a 0B4A ldr r2, .L186+20 + 1813 016c D35C ldrb r3, [r2, r3] + 1814 016e D840 lsrs r0, r0, r3 + 1815 0170 0A4B ldr r3, .L186+24 + 1816 0172 1860 str r0, [r3] + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1817 .loc 1 976 0 + 1818 0174 0320 movs r0, #3 + 1819 0176 FFF7FEFF bl HAL_InitTick + 1820 .LVL143: + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1821 .loc 1 978 0 + ARM GAS /tmp/cchbc9tY.s page 63 + + + 1822 017a 0020 movs r0, #0 + 1823 017c 54E7 b .L150 + 1824 .LVL144: + 1825 .L185: + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1826 .loc 1 868 0 + 1827 017e 0120 movs r0, #1 + 1828 .LVL145: + 1829 0180 52E7 b .L150 + 1830 .L187: + 1831 0182 C046 .align 2 + 1832 .L186: + 1833 0184 00200240 .word 1073881088 + 1834 0188 00100240 .word 1073876992 + 1835 018c 88130000 .word 5000 + 1836 0190 FFF8FFFF .word -1793 + 1837 0194 FFC7FFFF .word -14337 + 1838 0198 00000000 .word AHBPrescTable + 1839 019c 00000000 .word SystemCoreClock + 1840 .cfi_endproc + 1841 .LFE41: + 1843 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 1844 .align 1 + 1845 .global HAL_RCC_GetHCLKFreq + 1846 .syntax unified + 1847 .code 16 + 1848 .thumb_func + 1849 .fpu softvfp + 1851 HAL_RCC_GetHCLKFreq: + 1852 .LFB45: +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** return SystemCoreClock; + 1853 .loc 1 1225 0 + 1854 .cfi_startproc + 1855 @ args = 0, pretend = 0, frame = 0 + 1856 @ frame_needed = 0, uses_anonymous_args = 0 + 1857 @ link register save eliminated. +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1858 .loc 1 1226 0 + 1859 0000 014B ldr r3, .L189 + 1860 0002 1868 ldr r0, [r3] +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1861 .loc 1 1227 0 + 1862 @ sp needed + 1863 0004 7047 bx lr + 1864 .L190: + 1865 0006 C046 .align 2 + 1866 .L189: + 1867 0008 00000000 .word SystemCoreClock + 1868 .cfi_endproc + 1869 .LFE45: + 1871 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 1872 .align 1 + 1873 .global HAL_RCC_GetPCLK1Freq + 1874 .syntax unified + 1875 .code 16 + 1876 .thumb_func + 1877 .fpu softvfp + ARM GAS /tmp/cchbc9tY.s page 64 + + + 1879 HAL_RCC_GetPCLK1Freq: + 1880 .LFB46: +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + 1881 .loc 1 1236 0 + 1882 .cfi_startproc + 1883 @ args = 0, pretend = 0, frame = 0 + 1884 @ frame_needed = 0, uses_anonymous_args = 0 + 1885 @ link register save eliminated. + 1886 .LBB13: + 1887 .LBB14: +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1888 .loc 1 1226 0 + 1889 0000 054B ldr r3, .L192 + 1890 0002 1868 ldr r0, [r3] + 1891 .LBE14: + 1892 .LBE13: +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1893 .loc 1 1238 0 + 1894 0004 054B ldr r3, .L192+4 + 1895 0006 DA68 ldr r2, [r3, #12] + 1896 0008 120A lsrs r2, r2, #8 + 1897 000a 0723 movs r3, #7 + 1898 000c 1340 ands r3, r2 + 1899 000e 044A ldr r2, .L192+8 + 1900 0010 D35C ldrb r3, [r2, r3] + 1901 0012 D840 lsrs r0, r0, r3 +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1902 .loc 1 1239 0 + 1903 @ sp needed + 1904 0014 7047 bx lr + 1905 .L193: + 1906 0016 C046 .align 2 + 1907 .L192: + 1908 0018 00000000 .word SystemCoreClock + 1909 001c 00100240 .word 1073876992 + 1910 0020 00000000 .word APBPrescTable + 1911 .cfi_endproc + 1912 .LFE46: + 1914 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits + 1915 .align 1 + 1916 .global HAL_RCC_GetPCLK2Freq + 1917 .syntax unified + 1918 .code 16 + 1919 .thumb_func + 1920 .fpu softvfp + 1922 HAL_RCC_GetPCLK2Freq: + 1923 .LFB47: +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + 1924 .loc 1 1248 0 + 1925 .cfi_startproc + 1926 @ args = 0, pretend = 0, frame = 0 + 1927 @ frame_needed = 0, uses_anonymous_args = 0 + 1928 @ link register save eliminated. + 1929 .LBB15: + 1930 .LBB16: +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1931 .loc 1 1226 0 + ARM GAS /tmp/cchbc9tY.s page 65 + + + 1932 0000 054B ldr r3, .L195 + 1933 0002 1868 ldr r0, [r3] + 1934 .LBE16: + 1935 .LBE15: +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1936 .loc 1 1250 0 + 1937 0004 054B ldr r3, .L195+4 + 1938 0006 DA68 ldr r2, [r3, #12] + 1939 0008 D20A lsrs r2, r2, #11 + 1940 000a 0723 movs r3, #7 + 1941 000c 1340 ands r3, r2 + 1942 000e 044A ldr r2, .L195+8 + 1943 0010 D35C ldrb r3, [r2, r3] + 1944 0012 D840 lsrs r0, r0, r3 +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1945 .loc 1 1251 0 + 1946 @ sp needed + 1947 0014 7047 bx lr + 1948 .L196: + 1949 0016 C046 .align 2 + 1950 .L195: + 1951 0018 00000000 .word SystemCoreClock + 1952 001c 00100240 .word 1073876992 + 1953 0020 00000000 .word APBPrescTable + 1954 .cfi_endproc + 1955 .LFE47: + 1957 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 1958 .align 1 + 1959 .global HAL_RCC_GetOscConfig + 1960 .syntax unified + 1961 .code 16 + 1962 .thumb_func + 1963 .fpu softvfp + 1965 HAL_RCC_GetOscConfig: + 1966 .LFB48: +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 1967 .loc 1 1261 0 + 1968 .cfi_startproc + 1969 @ args = 0, pretend = 0, frame = 0 + 1970 @ frame_needed = 0, uses_anonymous_args = 0 + 1971 @ link register save eliminated. + 1972 .LVL146: +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 1973 .loc 1 1269 0 + 1974 0000 3F23 movs r3, #63 + 1975 0002 0360 str r3, [r0] +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1976 .loc 1 1274 0 + 1977 0004 344B ldr r3, .L213 + 1978 0006 1B68 ldr r3, [r3] + 1979 0008 5B03 lsls r3, r3, #13 + 1980 000a 43D5 bpl .L198 +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1981 .loc 1 1276 0 + 1982 000c A023 movs r3, #160 + 1983 000e DB02 lsls r3, r3, #11 + 1984 0010 4360 str r3, [r0, #4] + ARM GAS /tmp/cchbc9tY.s page 66 + + + 1985 .L199: +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 1986 .loc 1 1288 0 + 1987 0012 314B ldr r3, .L213 + 1988 0014 1B68 ldr r3, [r3] + 1989 0016 DB07 lsls r3, r3, #31 + 1990 0018 47D5 bpl .L201 +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 1991 .loc 1 1290 0 + 1992 001a 0123 movs r3, #1 + 1993 001c C360 str r3, [r0, #12] + 1994 .L202: +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 1995 .loc 1 1297 0 + 1996 001e 2E49 ldr r1, .L213 + 1997 0020 4A68 ldr r2, [r1, #4] + 1998 0022 120A lsrs r2, r2, #8 + 1999 0024 1F23 movs r3, #31 + 2000 0026 1340 ands r3, r2 + 2001 0028 0361 str r3, [r0, #16] +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2002 .loc 1 1300 0 + 2003 002a 0B68 ldr r3, [r1] + 2004 002c DB05 lsls r3, r3, #23 + 2005 002e 3FD5 bpl .L203 +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2006 .loc 1 1302 0 + 2007 0030 0123 movs r3, #1 + 2008 0032 C361 str r3, [r0, #28] + 2009 .L204: +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); + 2010 .loc 1 1309 0 + 2011 0034 284B ldr r3, .L213 + 2012 0036 5A68 ldr r2, [r3, #4] + 2013 0038 120E lsrs r2, r2, #24 + 2014 003a 0262 str r2, [r0, #32] +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2015 .loc 1 1310 0 + 2016 003c 5A68 ldr r2, [r3, #4] + 2017 003e E021 movs r1, #224 + 2018 0040 0902 lsls r1, r1, #8 + 2019 0042 0A40 ands r2, r1 + 2020 0044 4262 str r2, [r0, #36] +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2021 .loc 1 1313 0 + 2022 0046 1B6D ldr r3, [r3, #80] + 2023 0048 5B05 lsls r3, r3, #21 + 2024 004a 34D5 bpl .L205 +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2025 .loc 1 1315 0 + 2026 004c A023 movs r3, #160 + 2027 004e DB00 lsls r3, r3, #3 + 2028 0050 8360 str r3, [r0, #8] + 2029 .L206: +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2030 .loc 1 1327 0 + 2031 0052 214B ldr r3, .L213 + ARM GAS /tmp/cchbc9tY.s page 67 + + + 2032 0054 1B6D ldr r3, [r3, #80] + 2033 0056 DB07 lsls r3, r3, #31 + 2034 0058 38D5 bpl .L208 +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2035 .loc 1 1329 0 + 2036 005a 0123 movs r3, #1 + 2037 005c 4361 str r3, [r0, #20] + 2038 .L209: +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 2039 .loc 1 1338 0 + 2040 005e 1E4A ldr r2, .L213 + 2041 0060 9168 ldr r1, [r2, #8] + 2042 0062 0123 movs r3, #1 + 2043 0064 0B40 ands r3, r1 + 2044 0066 8361 str r3, [r0, #24] +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2045 .loc 1 1342 0 + 2046 0068 1368 ldr r3, [r2] + 2047 006a DB01 lsls r3, r3, #7 + 2048 006c 31D4 bmi .L212 +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2049 .loc 1 1348 0 + 2050 006e 0123 movs r3, #1 + 2051 0070 8362 str r3, [r0, #40] + 2052 .L211: +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + 2053 .loc 1 1350 0 + 2054 0072 194B ldr r3, .L213 + 2055 0074 DA68 ldr r2, [r3, #12] + 2056 0076 8021 movs r1, #128 + 2057 0078 4902 lsls r1, r1, #9 + 2058 007a 0A40 ands r2, r1 + 2059 007c C262 str r2, [r0, #44] +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); + 2060 .loc 1 1351 0 + 2061 007e DA68 ldr r2, [r3, #12] + 2062 0080 F021 movs r1, #240 + 2063 0082 8903 lsls r1, r1, #14 + 2064 0084 0A40 ands r2, r1 + 2065 0086 0263 str r2, [r0, #48] +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2066 .loc 1 1352 0 + 2067 0088 DB68 ldr r3, [r3, #12] + 2068 008a C022 movs r2, #192 + 2069 008c 1204 lsls r2, r2, #16 + 2070 008e 1340 ands r3, r2 + 2071 0090 4363 str r3, [r0, #52] +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2072 .loc 1 1353 0 + 2073 @ sp needed + 2074 0092 7047 bx lr + 2075 .L198: +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2076 .loc 1 1278 0 + 2077 0094 104B ldr r3, .L213 + 2078 0096 1B68 ldr r3, [r3] + 2079 0098 DB03 lsls r3, r3, #15 + ARM GAS /tmp/cchbc9tY.s page 68 + + + 2080 009a 03D5 bpl .L200 +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2081 .loc 1 1280 0 + 2082 009c 8023 movs r3, #128 + 2083 009e 5B02 lsls r3, r3, #9 + 2084 00a0 4360 str r3, [r0, #4] + 2085 00a2 B6E7 b .L199 + 2086 .L200: +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2087 .loc 1 1284 0 + 2088 00a4 0023 movs r3, #0 + 2089 00a6 4360 str r3, [r0, #4] + 2090 00a8 B3E7 b .L199 + 2091 .L201: +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2092 .loc 1 1294 0 + 2093 00aa 0023 movs r3, #0 + 2094 00ac C360 str r3, [r0, #12] + 2095 00ae B6E7 b .L202 + 2096 .L203: +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2097 .loc 1 1306 0 + 2098 00b0 0023 movs r3, #0 + 2099 00b2 C361 str r3, [r0, #28] + 2100 00b4 BEE7 b .L204 + 2101 .L205: +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2102 .loc 1 1317 0 + 2103 00b6 084B ldr r3, .L213 + 2104 00b8 1B6D ldr r3, [r3, #80] + 2105 00ba DB05 lsls r3, r3, #23 + 2106 00bc 03D5 bpl .L207 +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2107 .loc 1 1319 0 + 2108 00be 8023 movs r3, #128 + 2109 00c0 5B00 lsls r3, r3, #1 + 2110 00c2 8360 str r3, [r0, #8] + 2111 00c4 C5E7 b .L206 + 2112 .L207: +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2113 .loc 1 1323 0 + 2114 00c6 0023 movs r3, #0 + 2115 00c8 8360 str r3, [r0, #8] + 2116 00ca C2E7 b .L206 + 2117 .L208: +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2118 .loc 1 1333 0 + 2119 00cc 0023 movs r3, #0 + 2120 00ce 4361 str r3, [r0, #20] + 2121 00d0 C5E7 b .L209 + 2122 .L212: +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2123 .loc 1 1344 0 + 2124 00d2 0223 movs r3, #2 + 2125 00d4 8362 str r3, [r0, #40] + 2126 00d6 CCE7 b .L211 + 2127 .L214: + ARM GAS /tmp/cchbc9tY.s page 69 + + + 2128 .align 2 + 2129 .L213: + 2130 00d8 00100240 .word 1073876992 + 2131 .cfi_endproc + 2132 .LFE48: + 2134 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 2135 .align 1 + 2136 .global HAL_RCC_GetClockConfig + 2137 .syntax unified + 2138 .code 16 + 2139 .thumb_func + 2140 .fpu softvfp + 2142 HAL_RCC_GetClockConfig: + 2143 .LFB49: +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check the parameters */ + 2144 .loc 1 1364 0 + 2145 .cfi_startproc + 2146 @ args = 0, pretend = 0, frame = 0 + 2147 @ frame_needed = 0, uses_anonymous_args = 0 + 2148 .LVL147: + 2149 0000 30B5 push {r4, r5, lr} + 2150 .LCFI8: + 2151 .cfi_def_cfa_offset 12 + 2152 .cfi_offset 4, -12 + 2153 .cfi_offset 5, -8 + 2154 .cfi_offset 14, -4 +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2155 .loc 1 1370 0 + 2156 0002 0F23 movs r3, #15 + 2157 0004 0360 str r3, [r0] +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2158 .loc 1 1373 0 + 2159 0006 0C4A ldr r2, .L216 + 2160 0008 D468 ldr r4, [r2, #12] + 2161 000a 0C3B subs r3, r3, #12 + 2162 000c 2340 ands r3, r4 + 2163 000e 4360 str r3, [r0, #4] +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2164 .loc 1 1376 0 + 2165 0010 D468 ldr r4, [r2, #12] + 2166 0012 F023 movs r3, #240 + 2167 0014 2340 ands r3, r4 + 2168 0016 8360 str r3, [r0, #8] +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2169 .loc 1 1379 0 + 2170 0018 D468 ldr r4, [r2, #12] + 2171 001a E025 movs r5, #224 + 2172 001c ED00 lsls r5, r5, #3 + 2173 001e 2C40 ands r4, r5 + 2174 0020 C460 str r4, [r0, #12] +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2175 .loc 1 1382 0 + 2176 0022 D368 ldr r3, [r2, #12] + 2177 0024 DB08 lsrs r3, r3, #3 + 2178 0026 2B40 ands r3, r5 + 2179 0028 0361 str r3, [r0, #16] +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + ARM GAS /tmp/cchbc9tY.s page 70 + + + 2180 .loc 1 1385 0 + 2181 002a 044B ldr r3, .L216+4 + 2182 002c 1A68 ldr r2, [r3] + 2183 002e 0123 movs r3, #1 + 2184 0030 1340 ands r3, r2 + 2185 0032 0B60 str r3, [r1] +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2186 .loc 1 1386 0 + 2187 @ sp needed + 2188 0034 30BD pop {r4, r5, pc} + 2189 .L217: + 2190 0036 C046 .align 2 + 2191 .L216: + 2192 0038 00100240 .word 1073876992 + 2193 003c 00200240 .word 1073881088 + 2194 .cfi_endproc + 2195 .LFE49: + 2197 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 2198 .align 1 + 2199 .weak HAL_RCC_CSSCallback + 2200 .syntax unified + 2201 .code 16 + 2202 .thumb_func + 2203 .fpu softvfp + 2205 HAL_RCC_CSSCallback: + 2206 .LFB51: +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 2207 .loc 1 1412 0 + 2208 .cfi_startproc + 2209 @ args = 0, pretend = 0, frame = 0 + 2210 @ frame_needed = 0, uses_anonymous_args = 0 + 2211 @ link register save eliminated. +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2212 .loc 1 1416 0 + 2213 @ sp needed + 2214 0000 7047 bx lr + 2215 .cfi_endproc + 2216 .LFE51: + 2218 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 2219 .align 1 + 2220 .global HAL_RCC_NMI_IRQHandler + 2221 .syntax unified + 2222 .code 16 + 2223 .thumb_func + 2224 .fpu softvfp + 2226 HAL_RCC_NMI_IRQHandler: + 2227 .LFB50: +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** /* Check RCC CSSF flag */ + 2228 .loc 1 1395 0 + 2229 .cfi_startproc + 2230 @ args = 0, pretend = 0, frame = 0 + 2231 @ frame_needed = 0, uses_anonymous_args = 0 + 2232 0000 10B5 push {r4, lr} + 2233 .LCFI9: + 2234 .cfi_def_cfa_offset 8 + 2235 .cfi_offset 4, -8 + 2236 .cfi_offset 14, -4 + ARM GAS /tmp/cchbc9tY.s page 71 + + +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** { + 2237 .loc 1 1397 0 + 2238 0002 064B ldr r3, .L222 + 2239 0004 5B69 ldr r3, [r3, #20] + 2240 0006 DB05 lsls r3, r3, #23 + 2241 0008 00D4 bmi .L221 + 2242 .L219: +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2243 .loc 1 1405 0 + 2244 @ sp needed + 2245 000a 10BD pop {r4, pc} + 2246 .L221: +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2247 .loc 1 1400 0 + 2248 000c FFF7FEFF bl HAL_RCC_CSSCallback + 2249 .LVL148: +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** } + 2250 .loc 1 1403 0 + 2251 0010 024B ldr r3, .L222 + 2252 0012 8022 movs r2, #128 + 2253 0014 5200 lsls r2, r2, #1 + 2254 0016 9A61 str r2, [r3, #24] +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c **** + 2255 .loc 1 1405 0 + 2256 0018 F7E7 b .L219 + 2257 .L223: + 2258 001a C046 .align 2 + 2259 .L222: + 2260 001c 00100240 .word 1073876992 + 2261 .cfi_endproc + 2262 .LFE50: + 2264 .text + 2265 .Letext0: + 2266 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2267 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2268 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 2269 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 2270 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 2271 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 2272 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 2273 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 2274 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 2275 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 2276 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h" + 2277 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 2278 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 2279 .file 15 "" + ARM GAS /tmp/cchbc9tY.s page 72 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_rcc.c + /tmp/cchbc9tY.s:16 .text.RCC_SetFlashLatencyFromMSIRange:0000000000000000 $t + /tmp/cchbc9tY.s:22 .text.RCC_SetFlashLatencyFromMSIRange:0000000000000000 RCC_SetFlashLatencyFromMSIRange + /tmp/cchbc9tY.s:124 .text.RCC_SetFlashLatencyFromMSIRange:0000000000000070 $d + /tmp/cchbc9tY.s:132 .text.HAL_RCC_DeInit:0000000000000000 $t + /tmp/cchbc9tY.s:139 .text.HAL_RCC_DeInit:0000000000000000 HAL_RCC_DeInit + /tmp/cchbc9tY.s:211 .text.HAL_RCC_DeInit:0000000000000060 $d + /tmp/cchbc9tY.s:222 .text.HAL_RCC_OscConfig:0000000000000000 $t + /tmp/cchbc9tY.s:229 .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig + /tmp/cchbc9tY.s:769 .text.HAL_RCC_OscConfig:00000000000002fc $d + /tmp/cchbc9tY.s:781 .text.HAL_RCC_OscConfig:0000000000000320 $t + /tmp/cchbc9tY.s:1194 .text.HAL_RCC_OscConfig:0000000000000554 $d + /tmp/cchbc9tY.s:1208 .text.HAL_RCC_MCOConfig:0000000000000000 $t + /tmp/cchbc9tY.s:1215 .text.HAL_RCC_MCOConfig:0000000000000000 HAL_RCC_MCOConfig + /tmp/cchbc9tY.s:1345 .text.HAL_RCC_MCOConfig:000000000000009c $d + /tmp/cchbc9tY.s:1352 .text.HAL_RCC_EnableCSS:0000000000000000 $t + /tmp/cchbc9tY.s:1359 .text.HAL_RCC_EnableCSS:0000000000000000 HAL_RCC_EnableCSS + /tmp/cchbc9tY.s:1379 .text.HAL_RCC_EnableCSS:0000000000000010 $d + /tmp/cchbc9tY.s:1385 .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t + /tmp/cchbc9tY.s:1392 .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq + /tmp/cchbc9tY.s:1524 .text.HAL_RCC_GetSysClockFreq:000000000000009c $d + /tmp/cchbc9tY.s:1533 .text.HAL_RCC_ClockConfig:0000000000000000 $t + /tmp/cchbc9tY.s:1540 .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig + /tmp/cchbc9tY.s:1833 .text.HAL_RCC_ClockConfig:0000000000000184 $d + /tmp/cchbc9tY.s:1844 .text.HAL_RCC_GetHCLKFreq:0000000000000000 $t + /tmp/cchbc9tY.s:1851 .text.HAL_RCC_GetHCLKFreq:0000000000000000 HAL_RCC_GetHCLKFreq + /tmp/cchbc9tY.s:1867 .text.HAL_RCC_GetHCLKFreq:0000000000000008 $d + /tmp/cchbc9tY.s:1872 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t + /tmp/cchbc9tY.s:1879 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq + /tmp/cchbc9tY.s:1908 .text.HAL_RCC_GetPCLK1Freq:0000000000000018 $d + /tmp/cchbc9tY.s:1915 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t + /tmp/cchbc9tY.s:1922 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq + /tmp/cchbc9tY.s:1951 .text.HAL_RCC_GetPCLK2Freq:0000000000000018 $d + /tmp/cchbc9tY.s:1958 .text.HAL_RCC_GetOscConfig:0000000000000000 $t + /tmp/cchbc9tY.s:1965 .text.HAL_RCC_GetOscConfig:0000000000000000 HAL_RCC_GetOscConfig + /tmp/cchbc9tY.s:2130 .text.HAL_RCC_GetOscConfig:00000000000000d8 $d + /tmp/cchbc9tY.s:2135 .text.HAL_RCC_GetClockConfig:0000000000000000 $t + /tmp/cchbc9tY.s:2142 .text.HAL_RCC_GetClockConfig:0000000000000000 HAL_RCC_GetClockConfig + /tmp/cchbc9tY.s:2192 .text.HAL_RCC_GetClockConfig:0000000000000038 $d + /tmp/cchbc9tY.s:2198 .text.HAL_RCC_CSSCallback:0000000000000000 $t + /tmp/cchbc9tY.s:2205 .text.HAL_RCC_CSSCallback:0000000000000000 HAL_RCC_CSSCallback + /tmp/cchbc9tY.s:2219 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 $t + /tmp/cchbc9tY.s:2226 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 HAL_RCC_NMI_IRQHandler + /tmp/cchbc9tY.s:2260 .text.HAL_RCC_NMI_IRQHandler:000000000000001c $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +SystemCoreClock +HAL_GetTick +HAL_InitTick +AHBPrescTable +memset +HAL_GPIO_Init +__aeabi_uidiv +PLLMulTable +APBPrescTable + ARM GAS /tmp/cchbc9tY.s page 73 + + diff --git a/build/stm32l0xx_hal_rcc_ex.d b/build/stm32l0xx_hal_rcc_ex.d new file mode 100644 index 0000000..c7a7de2 --- /dev/null +++ b/build/stm32l0xx_hal_rcc_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_rcc_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_rcc_ex.lst b/build/stm32l0xx_hal_rcc_ex.lst new file mode 100644 index 0000000..7fe1149 --- /dev/null +++ b/build/stm32l0xx_hal_rcc_ex.lst @@ -0,0 +1,3456 @@ +ARM GAS /tmp/cc4UWnQP.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_rcc_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 16 .align 1 + 17 .global HAL_RCCEx_PeriphCLKConfig + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_RCCEx_PeriphCLKConfig: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @file stm32l0xx_hal_rcc_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * functionalities RCC extension peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + Extended Clock Recovery System Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ****************************************************************************** + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @attention + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * are permitted provided that the following conditions are met: + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * this list of conditions and the following disclaimer. + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * this list of conditions and the following disclaimer in the documentation + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * and/or other materials provided with the distribution. + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * may be used to endorse or promote products derived from this software + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * without specific prior written permission. + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + ARM GAS /tmp/cc4UWnQP.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ****************************************************************************** + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #include "stm32l0xx_hal.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCC Extension HAL module driver + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private define ------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Constants RCCEx Private Constants + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined (CRS) + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Bit position in register */ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #define CRS_CFGR_FELIM_BITNUMBER CRS_CFGR_FELIM_Pos + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #define CRS_CR_TRIM_BITNUMBER CRS_CR_TRIM_Pos + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #define CRS_ISR_FECAP_BITNUMBER CRS_ISR_FECAP_Pos + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* CRS */ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** extern const uint8_t PLLMulTable[]; + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @} + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @} + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Private functions ---------------------------------------------------------*/ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + ARM GAS /tmp/cc4UWnQP.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** @verbatim + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** =============================================================================== + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** =============================================================================== + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** [..] + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequencies. + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** [..] + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the backup registers) are set to their reset values. + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** @endverbatim + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals clocks(USART1,USART + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval HAL status + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfi + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * to possibly update HSE divider. + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 26 .loc 1 121 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 0400 movs r4, r0 + 39 .LVL1: + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t temp_reg = 0U; + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*------------------------------- RTC/LCD Configuration ------------------------*/ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) + 40 .loc 1 131 0 + 41 0004 8223 movs r3, #130 + ARM GAS /tmp/cc4UWnQP.s page 4 + + + 42 0006 1B01 lsls r3, r3, #4 + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 43 .loc 1 129 0 + 44 0008 0268 ldr r2, [r0] + 45 000a 1A42 tst r2, r3 + 46 000c 5AD0 beq .L2 + 47 .LVL2: + 48 .LBB2: + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ) + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* check for RTC Parameters used to output RTCCLK */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* As soon as function is called to change RTC clock source, activation of the + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** power domain is done. */ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Requires to enable write access to Backup Domain of necessary */ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 49 .loc 1 153 0 + 50 000e 754B ldr r3, .L33 + 51 0010 9B6B ldr r3, [r3, #56] + 52 0012 DB00 lsls r3, r3, #3 + 53 0014 00D5 bpl .LCB29 + 54 0016 9DE0 b .L22 @long jump + 55 .LCB29: + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 56 .loc 1 155 0 + 57 0018 724A ldr r2, .L33 + 58 001a 916B ldr r1, [r2, #56] + 59 001c 8023 movs r3, #128 + 60 001e 5B05 lsls r3, r3, #21 + 61 0020 0B43 orrs r3, r1 + 62 0022 9363 str r3, [r2, #56] + 63 .LVL3: + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 64 .loc 1 156 0 + 65 0024 0125 movs r5, #1 + 66 .LVL4: + 67 .L3: + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 68 .loc 1 159 0 + 69 0026 704B ldr r3, .L33+4 + ARM GAS /tmp/cc4UWnQP.s page 5 + + + 70 0028 1B68 ldr r3, [r3] + 71 002a DB05 lsls r3, r3, #23 + 72 002c 00D4 bmi .LCB47 + 73 002e 93E0 b .L27 @long jump + 74 .LCB47: + 75 .LVL5: + 76 .L4: + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** temp_reg = (RCC->CR & RCC_CR_RTCPRE); + 77 .loc 1 177 0 + 78 0030 6C4B ldr r3, .L33 + 79 0032 1A68 ldr r2, [r3] + 80 0034 C023 movs r3, #192 + 81 0036 9B03 lsls r3, r3, #14 + 82 0038 1A40 ands r2, r3 + 83 .LVL6: + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) + 84 .loc 1 178 0 + 85 003a 6168 ldr r1, [r4, #4] + 86 003c 0B40 ands r3, r1 + 87 003e 9342 cmp r3, r2 + 88 0040 00D1 bne .LCB60 + 89 0042 9EE0 b .L28 @long jump + 90 .LCB60: + 91 .L8: + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined (LCD) + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ) + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { /* Check HSE State */ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT + 92 .loc 1 184 0 + 93 0044 C023 movs r3, #192 + 94 0046 9B02 lsls r3, r3, #10 + 95 0048 0A00 movs r2, r1 + 96 .LVL7: + 97 004a 1A40 ands r2, r3 + 98 004c 9A42 cmp r2, r3 + 99 004e 00D1 bne .LCB68 + 100 0050 9FE0 b .L29 @long jump + 101 .LCB68: + ARM GAS /tmp/cc4UWnQP.s page 6 + + + 102 .L9: + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* To update HSE divider, first switch-OFF HSE clock oscillator*/ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return HAL_ERROR; + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); + 103 .loc 1 192 0 + 104 0052 644B ldr r3, .L33 + 105 0054 1B6D ldr r3, [r3, #80] + 106 0056 C022 movs r2, #192 + 107 0058 9202 lsls r2, r2, #10 + 108 005a 1340 ands r3, r2 + 109 .LVL8: + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCS + 110 .loc 1 194 0 + 111 005c 1FD0 beq .L10 + 112 .loc 1 194 0 is_stmt 0 discriminator 1 + 113 005e 1140 ands r1, r2 + 114 0060 9942 cmp r1, r3 + 115 0062 02D0 beq .L11 + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + 116 .loc 1 195 0 is_stmt 1 + 117 0064 2268 ldr r2, [r4] + 118 0066 9206 lsls r2, r2, #26 + 119 0068 08D4 bmi .L12 + 120 .L11: + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ + 121 .loc 1 197 0 + 122 006a C022 movs r2, #192 + 123 006c 9202 lsls r2, r2, #10 + 124 006e A168 ldr r1, [r4, #8] + 125 0070 0A40 ands r2, r1 + 126 0072 9A42 cmp r2, r3 + 127 0074 13D0 beq .L10 + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) + 128 .loc 1 198 0 + 129 0076 2368 ldr r3, [r4] + 130 .LVL9: + 131 0078 1B05 lsls r3, r3, #20 + 132 007a 10D5 bpl .L10 + 133 .L12: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** )) + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Store the content of CSR register before the reset of Backup Domain */ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + 134 .loc 1 203 0 + 135 007c 594B ldr r3, .L33 + 136 007e 186D ldr r0, [r3, #80] + 137 0080 5A4A ldr r2, .L33+8 + 138 0082 0240 ands r2, r0 + 139 .LVL10: + ARM GAS /tmp/cc4UWnQP.s page 7 + + + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 140 .loc 1 206 0 + 141 0084 1E6D ldr r6, [r3, #80] + 142 0086 8021 movs r1, #128 + 143 0088 0903 lsls r1, r1, #12 + 144 008a 3143 orrs r1, r6 + 145 008c 1965 str r1, [r3, #80] + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 146 .loc 1 207 0 + 147 008e 196D ldr r1, [r3, #80] + 148 0090 574E ldr r6, .L33+12 + 149 0092 3140 ands r1, r6 + 150 0094 1965 str r1, [r3, #80] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Restore the Content of CSR register */ + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** RCC->CSR = temp_reg; + 151 .loc 1 210 0 + 152 0096 1A65 str r2, [r3, #80] + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Wait for LSERDY if LSE was enabled */ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) + 153 .loc 1 213 0 + 154 0098 C305 lsls r3, r0, #23 + 155 009a 00D5 bpl .LCB123 + 156 009c 80E0 b .L30 @long jump + 157 .LCB123: + 158 .LVL11: + 159 .L10: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get Start Tick */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 160 .loc 1 228 0 + 161 009e 6368 ldr r3, [r4, #4] + 162 00a0 C022 movs r2, #192 + 163 00a2 9202 lsls r2, r2, #10 + 164 00a4 1900 movs r1, r3 + 165 00a6 1140 ands r1, r2 + 166 00a8 9142 cmp r1, r2 + 167 00aa 00D1 bne .LCB132 + 168 00ac 88E0 b .L31 @long jump + 169 .LCB132: + 170 .L15: + 171 .loc 1 228 0 is_stmt 0 discriminator 3 + ARM GAS /tmp/cc4UWnQP.s page 8 + + + 172 00ae 4D49 ldr r1, .L33 + 173 00b0 0B6D ldr r3, [r1, #80] + 174 00b2 C022 movs r2, #192 + 175 00b4 9202 lsls r2, r2, #10 + 176 00b6 6068 ldr r0, [r4, #4] + 177 00b8 0240 ands r2, r0 + 178 00ba 1343 orrs r3, r2 + 179 00bc 0B65 str r3, [r1, #80] + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Require to disable power clock if necessary */ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(pwrclkchanged == SET) + 180 .loc 1 231 0 is_stmt 1 discriminator 3 + 181 00be 012D cmp r5, #1 + 182 00c0 00D1 bne .LCB144 + 183 00c2 87E0 b .L32 @long jump + 184 .LCB144: + 185 .LVL12: + 186 .L2: + 187 .LBE2: + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined (RCC_CCIPR_USART1SEL) + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*------------------------------- USART1 Configuration ------------------------*/ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 188 .loc 1 239 0 + 189 00c4 2368 ldr r3, [r4] + 190 00c6 DB07 lsls r3, r3, #31 + 191 00c8 06D5 bpl .L16 + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 192 .loc 1 245 0 + 193 00ca 464A ldr r2, .L33 + 194 00cc D36C ldr r3, [r2, #76] + 195 00ce 0321 movs r1, #3 + 196 00d0 8B43 bics r3, r1 + 197 00d2 E168 ldr r1, [r4, #12] + 198 00d4 0B43 orrs r3, r1 + 199 00d6 D364 str r3, [r2, #76] + 200 .L16: + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART1SEL */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*----------------------------- USART2 Configuration --------------------------*/ + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 201 .loc 1 250 0 + 202 00d8 2368 ldr r3, [r4] + 203 00da 9B07 lsls r3, r3, #30 + 204 00dc 06D5 bpl .L17 + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/cc4UWnQP.s page 9 + + + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 205 .loc 1 256 0 + 206 00de 414A ldr r2, .L33 + 207 00e0 D36C ldr r3, [r2, #76] + 208 00e2 0C21 movs r1, #12 + 209 00e4 8B43 bics r3, r1 + 210 00e6 2169 ldr r1, [r4, #16] + 211 00e8 0B43 orrs r3, r1 + 212 00ea D364 str r3, [r2, #76] + 213 .L17: + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*------------------------------ LPUART1 Configuration ------------------------*/ + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 214 .loc 1 260 0 + 215 00ec 2368 ldr r3, [r4] + 216 00ee 5B07 lsls r3, r3, #29 + 217 00f0 06D5 bpl .L18 + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Configure the LPUAR1 clock source */ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 218 .loc 1 266 0 + 219 00f2 3C4A ldr r2, .L33 + 220 00f4 D36C ldr r3, [r2, #76] + 221 00f6 3F49 ldr r1, .L33+16 + 222 00f8 0B40 ands r3, r1 + 223 00fa 6169 ldr r1, [r4, #20] + 224 00fc 0B43 orrs r3, r1 + 225 00fe D364 str r3, [r2, #76] + 226 .L18: + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*------------------------------ I2C1 Configuration ------------------------*/ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 227 .loc 1 270 0 + 228 0100 2368 ldr r3, [r4] + 229 0102 1B07 lsls r3, r3, #28 + 230 0104 06D5 bpl .L19 + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 231 .loc 1 276 0 + 232 0106 374A ldr r2, .L33 + 233 0108 D36C ldr r3, [r2, #76] + 234 010a 3B49 ldr r1, .L33+20 + 235 010c 0B40 ands r3, r1 + 236 010e A169 ldr r1, [r4, #24] + 237 0110 0B43 orrs r3, r1 + ARM GAS /tmp/cc4UWnQP.s page 10 + + + 238 0112 D364 str r3, [r2, #76] + 239 .L19: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined (RCC_CCIPR_I2C3SEL) + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*------------------------------ I2C3 Configuration ------------------------*/ + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 240 .loc 1 281 0 + 241 0114 2368 ldr r3, [r4] + 242 0116 DB05 lsls r3, r3, #23 + 243 0118 06D5 bpl .L20 + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 244 .loc 1 287 0 + 245 011a 324A ldr r2, .L33 + 246 011c D36C ldr r3, [r2, #76] + 247 011e 3349 ldr r1, .L33+8 + 248 0120 0B40 ands r3, r1 + 249 0122 E169 ldr r1, [r4, #28] + 250 0124 0B43 orrs r3, r1 + 251 0126 D364 str r3, [r2, #76] + 252 .L20: + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C3SEL */ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*---------------------------- USB and RNG configuration --------------------*/ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) + 253 .loc 1 293 0 + 254 0128 2368 ldr r3, [r4] + 255 012a 5B06 lsls r3, r3, #25 + 256 012c 06D5 bpl .L21 + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 257 .loc 1 296 0 + 258 012e 2D4A ldr r2, .L33 + 259 0130 D36C ldr r3, [r2, #76] + 260 0132 3249 ldr r1, .L33+24 + 261 0134 0B40 ands r3, r1 + 262 0136 616A ldr r1, [r4, #36] + 263 0138 0B43 orrs r3, r1 + 264 013a D364 str r3, [r2, #76] + 265 .L21: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /*---------------------------- LPTIM1 configuration ------------------------*/ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 266 .loc 1 301 0 + 267 013c 2368 ldr r3, [r4] + 268 013e 1B06 lsls r3, r3, #24 + 269 0140 4ED5 bpl .L26 + ARM GAS /tmp/cc4UWnQP.s page 11 + + + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection)); + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); + 270 .loc 1 304 0 + 271 0142 284A ldr r2, .L33 + 272 0144 D36C ldr r3, [r2, #76] + 273 0146 2E49 ldr r1, .L33+28 + 274 0148 0B40 ands r3, r1 + 275 014a 216A ldr r1, [r4, #32] + 276 014c 0B43 orrs r3, r1 + 277 014e D364 str r3, [r2, #76] + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return HAL_OK; + 278 .loc 1 307 0 + 279 0150 0020 movs r0, #0 + 280 .L6: + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 281 .loc 1 308 0 + 282 @ sp needed + 283 .LVL13: + 284 0152 70BD pop {r4, r5, r6, pc} + 285 .LVL14: + 286 .L22: + 287 .LBB3: + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 288 .loc 1 148 0 + 289 0154 0025 movs r5, #0 + 290 0156 66E7 b .L3 + 291 .LVL15: + 292 .L27: + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 293 .loc 1 162 0 + 294 0158 234A ldr r2, .L33+4 + 295 015a 1168 ldr r1, [r2] + 296 015c 8023 movs r3, #128 + 297 015e 5B00 lsls r3, r3, #1 + 298 0160 0B43 orrs r3, r1 + 299 0162 1360 str r3, [r2] + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 300 .loc 1 165 0 + 301 0164 FFF7FEFF bl HAL_GetTick + 302 .LVL16: + 303 0168 0600 movs r6, r0 + 304 .LVL17: + 305 .L5: + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 306 .loc 1 167 0 + 307 016a 1F4B ldr r3, .L33+4 + 308 016c 1B68 ldr r3, [r3] + 309 016e DB05 lsls r3, r3, #23 + 310 0170 00D5 bpl .LCB303 + 311 0172 5DE7 b .L4 @long jump + 312 .LCB303: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 313 .loc 1 169 0 + 314 0174 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/cc4UWnQP.s page 12 + + + 315 .LVL18: + 316 0178 801B subs r0, r0, r6 + 317 017a 6428 cmp r0, #100 + 318 017c F5D9 bls .L5 + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 319 .loc 1 171 0 + 320 017e 0320 movs r0, #3 + 321 0180 E7E7 b .L6 + 322 .LVL19: + 323 .L28: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 324 .loc 1 180 0 + 325 0182 C023 movs r3, #192 + 326 0184 9B03 lsls r3, r3, #14 + 327 0186 A068 ldr r0, [r4, #8] + 328 0188 0340 ands r3, r0 + 329 018a 9342 cmp r3, r2 + 330 018c 00D0 beq .LCB323 + 331 018e 59E7 b .L8 @long jump + 332 .LCB323: + 333 0190 5FE7 b .L9 + 334 .LVL20: + 335 .L29: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 336 .loc 1 184 0 discriminator 1 + 337 0192 144B ldr r3, .L33 + 338 0194 1B68 ldr r3, [r3] + 339 0196 9B03 lsls r3, r3, #14 + 340 0198 00D4 bmi .LCB335 + 341 019a 5AE7 b .L9 @long jump + 342 .LCB335: + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 343 .loc 1 187 0 + 344 019c 0120 movs r0, #1 + 345 019e D8E7 b .L6 + 346 .LVL21: + 347 .L30: + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 348 .loc 1 216 0 + 349 01a0 FFF7FEFF bl HAL_GetTick + 350 .LVL22: + 351 01a4 0600 movs r6, r0 + 352 .LVL23: + 353 .L13: + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 354 .loc 1 219 0 + 355 01a6 0F4B ldr r3, .L33 + 356 01a8 1B6D ldr r3, [r3, #80] + 357 01aa 9B05 lsls r3, r3, #22 + 358 01ac 00D5 bpl .LCB355 + 359 01ae 76E7 b .L10 @long jump + 360 .LCB355: + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 361 .loc 1 221 0 + 362 01b0 FFF7FEFF bl HAL_GetTick + 363 .LVL24: + 364 01b4 801B subs r0, r0, r6 + ARM GAS /tmp/cc4UWnQP.s page 13 + + + 365 01b6 134B ldr r3, .L33+32 + 366 01b8 9842 cmp r0, r3 + 367 01ba F4D9 bls .L13 + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 368 .loc 1 223 0 + 369 01bc 0320 movs r0, #3 + 370 01be C8E7 b .L6 + 371 .LVL25: + 372 .L31: + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 373 .loc 1 228 0 discriminator 1 + 374 01c0 0849 ldr r1, .L33 + 375 01c2 0A68 ldr r2, [r1] + 376 01c4 1048 ldr r0, .L33+36 + 377 01c6 0240 ands r2, r0 + 378 01c8 C020 movs r0, #192 + 379 01ca 8003 lsls r0, r0, #14 + 380 01cc 0340 ands r3, r0 + 381 01ce 1343 orrs r3, r2 + 382 01d0 0B60 str r3, [r1] + 383 01d2 6CE7 b .L15 + 384 .L32: + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 385 .loc 1 233 0 + 386 01d4 0A00 movs r2, r1 + 387 01d6 8B6B ldr r3, [r1, #56] + 388 01d8 0C49 ldr r1, .L33+40 + 389 01da 0B40 ands r3, r1 + 390 01dc 9363 str r3, [r2, #56] + 391 01de 71E7 b .L2 + 392 .LVL26: + 393 .L26: + 394 .LBE3: + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 395 .loc 1 307 0 + 396 01e0 0020 movs r0, #0 + 397 01e2 B6E7 b .L6 + 398 .L34: + 399 .align 2 + 400 .L33: + 401 01e4 00100240 .word 1073876992 + 402 01e8 00700040 .word 1073770496 + 403 01ec FFFFFCFF .word -196609 + 404 01f0 FFFFF7FF .word -524289 + 405 01f4 FFF3FFFF .word -3073 + 406 01f8 FFCFFFFF .word -12289 + 407 01fc FFFFFFFB .word -67108865 + 408 0200 FFFFF3FF .word -786433 + 409 0204 88130000 .word 5000 + 410 0208 FFFFCFFF .word -3145729 + 411 020c FFFFFFEF .word -268435457 + 412 .cfi_endproc + 413 .LFE39: + 415 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + 416 .align 1 + 417 .global HAL_RCCEx_GetPeriphCLKConfig + 418 .syntax unified + ARM GAS /tmp/cc4UWnQP.s page 14 + + + 419 .code 16 + 420 .thumb_func + 421 .fpu softvfp + 423 HAL_RCCEx_GetPeriphCLKConfig: + 424 .LFB40: + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Get the PeriphClkInit according to the internal RCC configuration registers. + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals clocks(USART1,USART2 + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 425 .loc 1 318 0 + 426 .cfi_startproc + 427 @ args = 0, pretend = 0, frame = 0 + 428 @ frame_needed = 0, uses_anonymous_args = 0 + 429 .LVL27: + 430 0000 10B5 push {r4, lr} + 431 .LCFI1: + 432 .cfi_def_cfa_offset 8 + 433 .cfi_offset 4, -8 + 434 .cfi_offset 14, -4 + 435 .LVL28: + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t srcclk = 0; + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter -----------*/ + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Common part first */ + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1; + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART1SEL) + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART1; + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART1SEL */ + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C3SEL) + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C3SEL */ + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; + 436 .loc 1 336 0 + 437 0002 1D4B ldr r3, .L38 + 438 0004 0360 str r3, [r0] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the RTC/LCD configuration -----------------------------------------------*/ + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE(); + 439 .loc 1 340 0 + 440 0006 1D4B ldr r3, .L38+4 + 441 0008 1B6D ldr r3, [r3, #80] + 442 000a C022 movs r2, #192 + 443 000c 9202 lsls r2, r2, #10 + 444 000e 1340 ands r3, r2 + ARM GAS /tmp/cc4UWnQP.s page 15 + + + 445 .LVL29: + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) + 446 .loc 1 341 0 + 447 0010 9342 cmp r3, r2 + 448 0012 28D0 beq .L36 + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Source clock is LSE or LSI*/ + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = srcclk; + 449 .loc 1 344 0 + 450 0014 4360 str r3, [r0, #4] + 451 .LVL30: + 452 .L37: + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Source clock is HSE. Need to get the prescaler value*/ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; + 453 .loc 1 352 0 + 454 0016 4368 ldr r3, [r0, #4] + 455 0018 8360 str r3, [r0, #8] + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART1SEL) + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the USART1 configuration --------------------------------------------*/ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + 456 .loc 1 356 0 + 457 001a 184B ldr r3, .L38+4 + 458 001c D96C ldr r1, [r3, #76] + 459 001e 0322 movs r2, #3 + 460 0020 0A40 ands r2, r1 + 461 0022 C260 str r2, [r0, #12] + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART1SEL */ + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the USART2 clock source ---------------------------------------------*/ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + 462 .loc 1 359 0 + 463 0024 D96C ldr r1, [r3, #76] + 464 0026 0C22 movs r2, #12 + 465 0028 0A40 ands r2, r1 + 466 002a 0261 str r2, [r0, #16] + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source ---------------------------------------------*/ + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + 467 .loc 1 361 0 + 468 002c DA6C ldr r2, [r3, #76] + 469 002e C021 movs r1, #192 + 470 0030 0901 lsls r1, r1, #4 + 471 0032 0A40 ands r2, r1 + 472 0034 4261 str r2, [r0, #20] + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the I2C1 clock source -----------------------------------------------*/ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + 473 .loc 1 363 0 + 474 0036 DA6C ldr r2, [r3, #76] + 475 0038 C021 movs r1, #192 + 476 003a 8901 lsls r1, r1, #6 + 477 003c 0A40 ands r2, r1 + 478 003e 8261 str r2, [r0, #24] + ARM GAS /tmp/cc4UWnQP.s page 16 + + + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C3SEL) + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the I2C3 clock source -----------------------------------------------*/ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + 479 .loc 1 366 0 + 480 0040 D96C ldr r1, [r3, #76] + 481 0042 C024 movs r4, #192 + 482 0044 A402 lsls r4, r4, #10 + 483 0046 2140 ands r1, r4 + 484 0048 C161 str r1, [r0, #28] + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C3SEL */ + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock source -----------------------------------------------*/ + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + 485 .loc 1 369 0 + 486 004a D96C ldr r1, [r3, #76] + 487 004c C022 movs r2, #192 + 488 004e 1203 lsls r2, r2, #12 + 489 0050 1140 ands r1, r2 + 490 0052 0162 str r1, [r0, #32] + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the RTC clock source -----------------------------------------------*/ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + 491 .loc 1 371 0 + 492 0054 1A6D ldr r2, [r3, #80] + 493 0056 2240 ands r2, r4 + 494 0058 4260 str r2, [r0, #4] + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the USB/RNG clock source -----------------------------------------------*/ + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + 495 .loc 1 374 0 + 496 005a DB6C ldr r3, [r3, #76] + 497 005c 8022 movs r2, #128 + 498 005e D204 lsls r2, r2, #19 + 499 0060 1340 ands r3, r2 + 500 0062 4362 str r3, [r0, #36] + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 501 .loc 1 376 0 + 502 @ sp needed + 503 0064 10BD pop {r4, pc} + 504 .LVL31: + 505 .L36: + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 506 .loc 1 349 0 + 507 0066 054A ldr r2, .L38+4 + 508 0068 1268 ldr r2, [r2] + 509 006a C021 movs r1, #192 + 510 006c 8903 lsls r1, r1, #14 + 511 006e 0A40 ands r2, r1 + 512 0070 1343 orrs r3, r2 + 513 .LVL32: + 514 0072 4360 str r3, [r0, #4] + 515 0074 CFE7 b .L37 + 516 .L39: + 517 0076 C046 .align 2 + 518 .L38: + 519 0078 EF090000 .word 2543 + 520 007c 00100240 .word 1073876992 + 521 .cfi_endproc + ARM GAS /tmp/cc4UWnQP.s page 17 + + + 522 .LFE40: + 524 .global __aeabi_uidiv + 525 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 526 .align 1 + 527 .global HAL_RCCEx_GetPeriphCLKFreq + 528 .syntax unified + 529 .code 16 + 530 .thumb_func + 531 .fpu softvfp + 533 HAL_RCCEx_GetPeriphCLKFreq: + 534 .LFB41: + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Return the peripheral clock frequency + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note Return 0 if peripheral clock is unknown + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * This parameter can be one of the following values: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*) + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB or RNG peripheral clock (*) + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock (*) + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (*) + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*) + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note (*) means that this peripheral is not present on all the devices + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 535 .loc 1 396 0 + 536 .cfi_startproc + 537 @ args = 0, pretend = 0, frame = 0 + 538 @ frame_needed = 0, uses_anonymous_args = 0 + 539 .LVL33: + 540 0000 10B5 push {r4, lr} + 541 .LCFI2: + 542 .cfi_def_cfa_offset 8 + 543 .cfi_offset 4, -8 + 544 .cfi_offset 14, -4 + 545 .LVL34: + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t temp_reg = 0U, clkprediv = 0U, frequency = 0U; + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t srcclk = 0U; + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U; + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** switch (PeriphClk) + 546 .loc 1 406 0 + 547 0002 1028 cmp r0, #16 + 548 0004 00D1 bne .LCB527 + 549 0006 20E1 b .L42 @long jump + 550 .LCB527: + ARM GAS /tmp/cc4UWnQP.s page 18 + + + 551 0008 2ED8 bhi .L43 + 552 000a 0228 cmp r0, #2 + 553 000c 00D1 bne .LCB531 + 554 000e CAE0 b .L44 @long jump + 555 .LCB531: + 556 0010 17D9 bls .L98 + 557 0012 0428 cmp r0, #4 + 558 0014 00D1 bne .LCB535 + 559 0016 E5E0 b .L47 @long jump + 560 .LCB535: + 561 0018 0828 cmp r0, #8 + 562 001a 59D1 bne .L73 + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_RTC: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(LCD) + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LCD: + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* LCD */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get RCC CSR configuration ------------------------------------------------------*/ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** temp_reg = RCC->CSR; + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current RTC source */ + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE(); + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LSE is ready if RTC clock selection is LSE */ + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY))) + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LSI is ready if RTC clock selection is LSI */ + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSIRDY))) + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = LSI_VALUE; + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSE is ready and if RTC clock selection is HSE */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current HSE clock divider */ + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** clkprediv = __HAL_RCC_GET_RTC_HSE_PRESCALER(); + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** switch (clkprediv) + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 16U; + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 8U; + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 4U; + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 19 + + + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** default: /* HSE DIV2 has been selected */ + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 2U; + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for RTC */ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(USB) + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USB: + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current USB source */ + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USB_SOURCE(); + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get PLL clock source and multiplication factor ----------------------*/ + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Compute PLL clock input */ + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllvco = (HSI_VALUE >> 2U); + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllvco = HSI_VALUE; + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else /* HSE source */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllvco = HSE_VALUE; + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* pllvco * pllmul / plldiv */ + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllvco = (pllvco * pllmul); + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = (pllvco/ plldiv); + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RD + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI48_VALUE; + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else /* RCC_USBCLKSOURCE_NONE */ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 20 + + + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* USB */ + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART1SEL) + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART1: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current USART1 source */ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART1_SOURCE(); + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is PCLK2 */ + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq(); + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART1 clock selection is HSI */ + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is SYSCLK */ + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART1 clock selection is LSE */ + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for USART1*/ + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART1SEL */ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART2: + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current USART2 source */ + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART2_SOURCE(); + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is PCLK1 */ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART2 clock selection is HSI */ + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is SYSCLK */ + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 21 + + + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART2 clock selection is LSE */ + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for USART2*/ + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPUART1: + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current LPUART1 source */ + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LPUART1 clock selection is PCLK1 */ + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSI is ready and if LPUART1 clock selection is HSI */ + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LPUART1 clock selection is SYSCLK */ + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if LSE is ready and if LPUART1 clock selection is LSE */ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for LPUART1*/ + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C1: + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current I2C1 source */ + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + 563 .loc 1 613 0 + 564 001c 9E4B ldr r3, .L125 + 565 001e DB6C ldr r3, [r3, #76] + 566 0020 C022 movs r2, #192 + 567 0022 9201 lsls r2, r2, #6 + 568 0024 1340 ands r3, r2 + 569 .LVL35: + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if I2C1 clock selection is PCLK1 */ + ARM GAS /tmp/cc4UWnQP.s page 22 + + + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + 570 .loc 1 616 0 + 571 0026 00D1 bne .LCB545 + 572 0028 02E1 b .L99 @long jump + 573 .LCB545: + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C1 clock selection is HSI */ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + 574 .loc 1 621 0 + 575 002a 8022 movs r2, #128 + 576 002c 9201 lsls r2, r2, #6 + 577 002e 9342 cmp r3, r2 + 578 0030 00D1 bne .LCB549 + 579 0032 00E1 b .L100 @long jump + 580 .LCB549: + 581 .L70: + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if I2C1 clock selection is SYSCLK */ + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + 582 .loc 1 626 0 + 583 0034 8022 movs r2, #128 + 584 0036 5201 lsls r2, r2, #5 + 585 0038 9342 cmp r3, r2 + 586 003a 00D1 bne .LCB554 + 587 003c 02E1 b .L101 @long jump + 588 .LCB554: + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for I2C1*/ + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 589 .loc 1 633 0 + 590 003e 0020 movs r0, #0 + 591 .LVL36: + 592 0040 47E0 b .L40 + 593 .LVL37: + 594 .L98: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 595 .loc 1 406 0 + 596 0042 0128 cmp r0, #1 + 597 0044 44D1 bne .L73 + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 598 .loc 1 516 0 + 599 0046 944B ldr r3, .L125 + 600 0048 DA6C ldr r2, [r3, #76] + 601 004a 0323 movs r3, #3 + 602 004c 1340 ands r3, r2 + 603 .LVL38: + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 604 .loc 1 519 0 + 605 004e 00D1 bne .LCB571 + ARM GAS /tmp/cc4UWnQP.s page 23 + + + 606 0050 96E0 b .L102 @long jump + 607 .LCB571: + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 608 .loc 1 524 0 + 609 0052 022B cmp r3, #2 + 610 0054 00D1 bne .LCB573 + 611 0056 96E0 b .L103 @long jump + 612 .LCB573: + 613 .L61: + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 614 .loc 1 529 0 + 615 0058 012B cmp r3, #1 + 616 005a 00D1 bne .LCB576 + 617 005c 9AE0 b .L104 @long jump + 618 .LCB576: + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 619 .loc 1 534 0 + 620 005e 032B cmp r3, #3 + 621 0060 00D1 bne .LCB578 + 622 0062 9AE0 b .L105 @long jump + 623 .LCB578: + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 624 .loc 1 541 0 + 625 0064 0020 movs r0, #0 + 626 .LVL39: + 627 0066 34E0 b .L40 + 628 .LVL40: + 629 .L43: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 630 .loc 1 406 0 + 631 0068 4028 cmp r0, #64 + 632 006a 59D0 beq .L49 + 633 006c 16D9 bls .L106 + 634 006e 8023 movs r3, #128 + 635 0070 5B00 lsls r3, r3, #1 + 636 0072 9842 cmp r0, r3 + 637 0074 28D1 bne .L107 + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(I2C2) + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C2: + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if I2C2 on APB1 clock enabled*/ + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN) + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* I2C2 */ + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + ARM GAS /tmp/cc4UWnQP.s page 24 + + + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C3SEL) + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C3: + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the current I2C1 source */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + 638 .loc 1 658 0 + 639 0076 884B ldr r3, .L125 + 640 0078 DB6C ldr r3, [r3, #76] + 641 007a C022 movs r2, #192 + 642 007c 9202 lsls r2, r2, #10 + 643 007e 1340 ands r3, r2 + 644 .LVL41: + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if I2C3 clock selection is PCLK1 */ + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2C3CLKSOURCE_PCLK1) + 645 .loc 1 661 0 + 646 0080 00D1 bne .LCB602 + 647 0082 EBE0 b .L108 @long jump + 648 .LCB602: + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C3 clock selection is HSI */ + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + 649 .loc 1 666 0 + 650 0084 8022 movs r2, #128 + 651 0086 9202 lsls r2, r2, #10 + 652 0088 9342 cmp r3, r2 + 653 008a 00D1 bne .LCB606 + 654 008c E9E0 b .L109 @long jump + 655 .LCB606: + 656 .L72: + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check if I2C3 clock selection is SYSCLK */ + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) + 657 .loc 1 671 0 + 658 008e 8022 movs r2, #128 + 659 0090 5202 lsls r2, r2, #9 + 660 0092 9342 cmp r3, r2 + 661 0094 00D1 bne .LCB611 + 662 0096 EBE0 b .L110 @long jump + 663 .LCB611: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clock not enabled for I2C3*/ + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = 0U; + 664 .loc 1 678 0 + 665 0098 0020 movs r0, #0 + 666 .LVL42: + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 25 + + + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C3SEL */ + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** default: + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return(frequency); + 667 .loc 1 688 0 + 668 009a 1AE0 b .L40 + 669 .LVL43: + 670 .L106: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 671 .loc 1 406 0 + 672 009c 2028 cmp r0, #32 + 673 009e 17D1 bne .L73 + 674 .L51: + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 675 .loc 1 414 0 + 676 00a0 7D4B ldr r3, .L125 + 677 00a2 196D ldr r1, [r3, #80] + 678 .LVL44: + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 679 .loc 1 417 0 + 680 00a4 1B6D ldr r3, [r3, #80] + 681 00a6 C022 movs r2, #192 + 682 00a8 9202 lsls r2, r2, #10 + 683 00aa 1340 ands r3, r2 + 684 .LVL45: + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 685 .loc 1 420 0 + 686 00ac 8022 movs r2, #128 + 687 00ae 5202 lsls r2, r2, #9 + 688 00b0 9342 cmp r3, r2 + 689 00b2 0FD0 beq .L111 + 690 .L53: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 691 .loc 1 425 0 + 692 00b4 8022 movs r2, #128 + 693 00b6 9202 lsls r2, r2, #10 + 694 00b8 9342 cmp r3, r2 + 695 00ba 10D0 beq .L112 + 696 .L54: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 697 .loc 1 430 0 + 698 00bc C022 movs r2, #192 + 699 00be 9202 lsls r2, r2, #10 + 700 00c0 9342 cmp r3, r2 + 701 00c2 10D0 beq .L113 + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 702 .loc 1 462 0 + 703 00c4 0020 movs r0, #0 + 704 .LVL46: + 705 00c6 04E0 b .L40 + 706 .LVL47: + 707 .L107: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 708 .loc 1 406 0 + ARM GAS /tmp/cc4UWnQP.s page 26 + + + 709 00c8 8023 movs r3, #128 + 710 00ca 1B01 lsls r3, r3, #4 + 711 00cc 9842 cmp r0, r3 + 712 00ce E7D0 beq .L51 + 713 .L73: + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t srcclk = 0U; + 714 .loc 1 397 0 + 715 00d0 0020 movs r0, #0 + 716 .LVL48: + 717 .L40: + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 718 .loc 1 689 0 + 719 @ sp needed + 720 00d2 10BD pop {r4, pc} + 721 .LVL49: + 722 .L111: + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 723 .loc 1 420 0 discriminator 1 + 724 00d4 8A05 lsls r2, r1, #22 + 725 00d6 EDD5 bpl .L53 + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 726 .loc 1 422 0 + 727 00d8 8020 movs r0, #128 + 728 .LVL50: + 729 00da 0002 lsls r0, r0, #8 + 730 00dc F9E7 b .L40 + 731 .LVL51: + 732 .L112: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 733 .loc 1 425 0 discriminator 1 + 734 00de 8A07 lsls r2, r1, #30 + 735 00e0 ECD5 bpl .L54 + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 736 .loc 1 427 0 + 737 00e2 6E48 ldr r0, .L125+4 + 738 .LVL52: + 739 00e4 F5E7 b .L40 + 740 .LVL53: + 741 .L113: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 742 .loc 1 430 0 discriminator 1 + 743 00e6 6C4B ldr r3, .L125 + 744 .LVL54: + 745 00e8 1B68 ldr r3, [r3] + 746 00ea 9B03 lsls r3, r3, #14 + 747 00ec 00D4 bmi .LCB716 + 748 00ee C2E0 b .L77 @long jump + 749 .LCB716: + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 750 .loc 1 433 0 + 751 00f0 694B ldr r3, .L125 + 752 00f2 1B68 ldr r3, [r3] + 753 00f4 C022 movs r2, #192 + 754 00f6 9203 lsls r2, r2, #14 + 755 00f8 1340 ands r3, r2 + 756 .LVL55: + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + ARM GAS /tmp/cc4UWnQP.s page 27 + + + 757 .loc 1 435 0 + 758 00fa 8022 movs r2, #128 + 759 00fc 9203 lsls r2, r2, #14 + 760 00fe 9342 cmp r3, r2 + 761 0100 00D1 bne .LCB726 + 762 0102 BAE0 b .L78 @long jump + 763 .LCB726: + 764 0104 C022 movs r2, #192 + 765 0106 9203 lsls r2, r2, #14 + 766 0108 9342 cmp r3, r2 + 767 010a 05D0 beq .L56 + 768 010c 8022 movs r2, #128 + 769 010e 5203 lsls r2, r2, #13 + 770 0110 9342 cmp r3, r2 + 771 0112 03D0 beq .L114 + 772 .LVL56: + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 773 .loc 1 454 0 + 774 0114 6248 ldr r0, .L125+8 + 775 .LVL57: + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 776 .loc 1 455 0 + 777 0116 DCE7 b .L40 + 778 .LVL58: + 779 .L56: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 780 .loc 1 439 0 + 781 0118 6248 ldr r0, .L125+12 + 782 .LVL59: + 783 011a DAE7 b .L40 + 784 .LVL60: + 785 .L114: + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 786 .loc 1 449 0 + 787 011c 6248 ldr r0, .L125+16 + 788 .LVL61: + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 789 .loc 1 450 0 + 790 011e D8E7 b .L40 + 791 .LVL62: + 792 .L49: + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 793 .loc 1 470 0 + 794 0120 5D4B ldr r3, .L125 + 795 0122 DB6C ldr r3, [r3, #76] + 796 0124 8022 movs r2, #128 + 797 0126 D204 lsls r2, r2, #19 + 798 0128 1340 ands r3, r2 + 799 .LVL63: + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 800 .loc 1 472 0 + 801 012a 1FD1 bne .L58 + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 802 .loc 1 472 0 is_stmt 0 discriminator 1 + 803 012c 5A4A ldr r2, .L125 + 804 012e 1268 ldr r2, [r2] + 805 0130 9201 lsls r2, r2, #6 + ARM GAS /tmp/cc4UWnQP.s page 28 + + + 806 0132 1BD5 bpl .L58 + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + 807 .loc 1 475 0 is_stmt 1 + 808 0134 584B ldr r3, .L125 + 809 .LVL64: + 810 0136 D868 ldr r0, [r3, #12] + 811 .LVL65: + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; + 812 .loc 1 476 0 + 813 0138 D968 ldr r1, [r3, #12] + 814 .LVL66: + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; + 815 .loc 1 477 0 + 816 013a 800C lsrs r0, r0, #18 + 817 .LVL67: + 818 013c 0F22 movs r2, #15 + 819 013e 0240 ands r2, r0 + 820 0140 5A48 ldr r0, .L125+20 + 821 0142 805C ldrb r0, [r0, r2] + 822 .LVL68: + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 823 .loc 1 478 0 + 824 0144 8A0D lsrs r2, r1, #22 + 825 0146 0321 movs r1, #3 + 826 .LVL69: + 827 0148 1140 ands r1, r2 + 828 014a 0131 adds r1, r1, #1 + 829 .LVL70: + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 830 .loc 1 481 0 + 831 014c DB68 ldr r3, [r3, #12] + 832 014e DB03 lsls r3, r3, #15 + 833 0150 07D4 bmi .L79 + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 834 .loc 1 483 0 + 835 0152 514B ldr r3, .L125 + 836 0154 1B68 ldr r3, [r3] + 837 0156 DB06 lsls r3, r3, #27 + 838 0158 01D4 bmi .L115 + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 839 .loc 1 489 0 + 840 015a 554B ldr r3, .L125+24 + 841 015c 02E0 b .L59 + 842 .L115: + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 843 .loc 1 485 0 + 844 015e 504B ldr r3, .L125+8 + 845 0160 00E0 b .L59 + 846 .L79: + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 847 .loc 1 494 0 + 848 0162 544B ldr r3, .L125+28 + 849 .L59: + 850 .LVL71: + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** frequency = (pllvco/ plldiv); + 851 .loc 1 497 0 + 852 0164 5843 muls r0, r3 + ARM GAS /tmp/cc4UWnQP.s page 29 + + + 853 .LVL72: + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 854 .loc 1 498 0 + 855 0166 FFF7FEFF bl __aeabi_uidiv + 856 .LVL73: + 857 016a B2E7 b .L40 + 858 .LVL74: + 859 .L58: + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 860 .loc 1 501 0 + 861 016c 002B cmp r3, #0 + 862 016e 00D1 bne .LCB841 + 863 0170 85E0 b .L81 @long jump + 864 .LCB841: + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 865 .loc 1 501 0 is_stmt 0 discriminator 1 + 866 0172 494B ldr r3, .L125 + 867 .LVL75: + 868 0174 9B68 ldr r3, [r3, #8] + 869 0176 9B07 lsls r3, r3, #30 + 870 0178 00D5 bpl .LCB848 + 871 017a 82E0 b .L82 @long jump + 872 .LCB848: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 873 .loc 1 507 0 is_stmt 1 + 874 017c 0020 movs r0, #0 + 875 .LVL76: + 876 017e A8E7 b .L40 + 877 .LVL77: + 878 .L102: + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 879 .loc 1 521 0 + 880 0180 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 881 .LVL78: + 882 0184 A5E7 b .L40 + 883 .LVL79: + 884 .L103: + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 885 .loc 1 524 0 discriminator 1 + 886 0186 444A ldr r2, .L125 + 887 0188 1268 ldr r2, [r2] + 888 018a 5207 lsls r2, r2, #29 + 889 018c 00D4 bmi .LCB874 + 890 018e 63E7 b .L61 @long jump + 891 .LCB874: + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 892 .loc 1 526 0 + 893 0190 4748 ldr r0, .L125+24 + 894 .LVL80: + 895 0192 9EE7 b .L40 + 896 .LVL81: + 897 .L104: + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 898 .loc 1 531 0 + 899 0194 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 900 .LVL82: + 901 0198 9BE7 b .L40 + ARM GAS /tmp/cc4UWnQP.s page 30 + + + 902 .LVL83: + 903 .L105: + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 904 .loc 1 534 0 discriminator 1 + 905 019a 3F4B ldr r3, .L125 + 906 .LVL84: + 907 019c 1B6D ldr r3, [r3, #80] + 908 019e 9B05 lsls r3, r3, #22 + 909 01a0 71D4 bmi .L85 + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 910 .loc 1 541 0 + 911 01a2 0020 movs r0, #0 + 912 .LVL85: + 913 01a4 95E7 b .L40 + 914 .LVL86: + 915 .L44: + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 916 .loc 1 549 0 + 917 01a6 3C4B ldr r3, .L125 + 918 01a8 DA6C ldr r2, [r3, #76] + 919 01aa 0C23 movs r3, #12 + 920 01ac 1340 ands r3, r2 + 921 .LVL87: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 922 .loc 1 552 0 + 923 01ae 07D0 beq .L116 + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 924 .loc 1 557 0 + 925 01b0 082B cmp r3, #8 + 926 01b2 08D0 beq .L117 + 927 .L64: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 928 .loc 1 562 0 + 929 01b4 042B cmp r3, #4 + 930 01b6 0CD0 beq .L118 + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 931 .loc 1 567 0 + 932 01b8 0C2B cmp r3, #12 + 933 01ba 0DD0 beq .L119 + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 934 .loc 1 574 0 + 935 01bc 0020 movs r0, #0 + 936 .LVL88: + 937 01be 88E7 b .L40 + 938 .LVL89: + 939 .L116: + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 940 .loc 1 554 0 + 941 01c0 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 942 .LVL90: + 943 01c4 85E7 b .L40 + 944 .LVL91: + 945 .L117: + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 946 .loc 1 557 0 discriminator 1 + 947 01c6 344A ldr r2, .L125 + 948 01c8 1268 ldr r2, [r2] + ARM GAS /tmp/cc4UWnQP.s page 31 + + + 949 01ca 5207 lsls r2, r2, #29 + 950 01cc F2D5 bpl .L64 + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 951 .loc 1 559 0 + 952 01ce 3848 ldr r0, .L125+24 + 953 .LVL92: + 954 01d0 7FE7 b .L40 + 955 .LVL93: + 956 .L118: + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 957 .loc 1 564 0 + 958 01d2 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 959 .LVL94: + 960 01d6 7CE7 b .L40 + 961 .LVL95: + 962 .L119: + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 963 .loc 1 567 0 discriminator 1 + 964 01d8 2F4B ldr r3, .L125 + 965 .LVL96: + 966 01da 1B6D ldr r3, [r3, #80] + 967 01dc 9B05 lsls r3, r3, #22 + 968 01de 55D4 bmi .L88 + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 969 .loc 1 574 0 + 970 01e0 0020 movs r0, #0 + 971 .LVL97: + 972 01e2 76E7 b .L40 + 973 .LVL98: + 974 .L47: + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 975 .loc 1 581 0 + 976 01e4 2C4B ldr r3, .L125 + 977 01e6 DB6C ldr r3, [r3, #76] + 978 01e8 C022 movs r2, #192 + 979 01ea 1201 lsls r2, r2, #4 + 980 01ec 1340 ands r3, r2 + 981 .LVL99: + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 982 .loc 1 584 0 + 983 01ee 0DD0 beq .L120 + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 984 .loc 1 589 0 + 985 01f0 8022 movs r2, #128 + 986 01f2 1201 lsls r2, r2, #4 + 987 01f4 9342 cmp r3, r2 + 988 01f6 0CD0 beq .L121 + 989 .L67: + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 990 .loc 1 594 0 + 991 01f8 8022 movs r2, #128 + 992 01fa D200 lsls r2, r2, #3 + 993 01fc 9342 cmp r3, r2 + 994 01fe 0ED0 beq .L122 + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 995 .loc 1 599 0 + 996 0200 C022 movs r2, #192 + ARM GAS /tmp/cc4UWnQP.s page 32 + + + 997 0202 1201 lsls r2, r2, #4 + 998 0204 9342 cmp r3, r2 + 999 0206 0DD0 beq .L123 + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1000 .loc 1 606 0 + 1001 0208 0020 movs r0, #0 + 1002 .LVL100: + 1003 020a 62E7 b .L40 + 1004 .LVL101: + 1005 .L120: + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1006 .loc 1 586 0 + 1007 020c FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1008 .LVL102: + 1009 0210 5FE7 b .L40 + 1010 .LVL103: + 1011 .L121: + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1012 .loc 1 589 0 discriminator 1 + 1013 0212 214A ldr r2, .L125 + 1014 0214 1268 ldr r2, [r2] + 1015 0216 5207 lsls r2, r2, #29 + 1016 0218 EED5 bpl .L67 + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1017 .loc 1 591 0 + 1018 021a 2548 ldr r0, .L125+24 + 1019 .LVL104: + 1020 021c 59E7 b .L40 + 1021 .LVL105: + 1022 .L122: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1023 .loc 1 596 0 + 1024 021e FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1025 .LVL106: + 1026 0222 56E7 b .L40 + 1027 .LVL107: + 1028 .L123: + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1029 .loc 1 599 0 discriminator 1 + 1030 0224 1C4B ldr r3, .L125 + 1031 .LVL108: + 1032 0226 1B6D ldr r3, [r3, #80] + 1033 0228 9B05 lsls r3, r3, #22 + 1034 022a 32D4 bmi .L91 + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1035 .loc 1 606 0 + 1036 022c 0020 movs r0, #0 + 1037 .LVL109: + 1038 022e 50E7 b .L40 + 1039 .LVL110: + 1040 .L99: + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1041 .loc 1 618 0 + 1042 0230 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1043 .LVL111: + 1044 0234 4DE7 b .L40 + 1045 .LVL112: + ARM GAS /tmp/cc4UWnQP.s page 33 + + + 1046 .L100: + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1047 .loc 1 621 0 discriminator 1 + 1048 0236 184A ldr r2, .L125 + 1049 0238 1268 ldr r2, [r2] + 1050 023a 5207 lsls r2, r2, #29 + 1051 023c 00D4 bmi .LCB1079 + 1052 023e F9E6 b .L70 @long jump + 1053 .LCB1079: + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1054 .loc 1 623 0 + 1055 0240 1B48 ldr r0, .L125+24 + 1056 .LVL113: + 1057 0242 46E7 b .L40 + 1058 .LVL114: + 1059 .L101: + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1060 .loc 1 628 0 + 1061 0244 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1062 .LVL115: + 1063 0248 43E7 b .L40 + 1064 .LVL116: + 1065 .L42: + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1066 .loc 1 642 0 + 1067 024a 134B ldr r3, .L125 + 1068 024c 9B6B ldr r3, [r3, #56] + 1069 024e 5B02 lsls r3, r3, #9 + 1070 0250 01D4 bmi .L124 + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1071 .loc 1 648 0 + 1072 0252 0020 movs r0, #0 + 1073 .LVL117: + 1074 0254 3DE7 b .L40 + 1075 .LVL118: + 1076 .L124: + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1077 .loc 1 644 0 + 1078 0256 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1079 .LVL119: + 1080 025a 3AE7 b .L40 + 1081 .LVL120: + 1082 .L108: + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1083 .loc 1 663 0 + 1084 025c FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1085 .LVL121: + 1086 0260 37E7 b .L40 + 1087 .LVL122: + 1088 .L109: + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1089 .loc 1 666 0 discriminator 1 + 1090 0262 0D4A ldr r2, .L125 + 1091 0264 1268 ldr r2, [r2] + 1092 0266 5207 lsls r2, r2, #29 + 1093 0268 00D4 bmi .LCB1140 + 1094 026a 10E7 b .L72 @long jump + ARM GAS /tmp/cc4UWnQP.s page 34 + + + 1095 .LCB1140: + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1096 .loc 1 668 0 + 1097 026c 1048 ldr r0, .L125+24 + 1098 .LVL123: + 1099 026e 30E7 b .L40 + 1100 .LVL124: + 1101 .L110: + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1102 .loc 1 673 0 + 1103 0270 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1104 .LVL125: + 1105 0274 2DE7 b .L40 + 1106 .LVL126: + 1107 .L77: + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1108 .loc 1 462 0 + 1109 0276 0020 movs r0, #0 + 1110 .LVL127: + 1111 0278 2BE7 b .L40 + 1112 .LVL128: + 1113 .L78: + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** break; + 1114 .loc 1 444 0 + 1115 027a 0F48 ldr r0, .L125+32 + 1116 .LVL129: + 1117 027c 29E7 b .L40 + 1118 .LVL130: + 1119 .L81: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1120 .loc 1 507 0 + 1121 027e 0020 movs r0, #0 + 1122 .LVL131: + 1123 0280 27E7 b .L40 + 1124 .LVL132: + 1125 .L82: + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1126 .loc 1 503 0 + 1127 0282 0E48 ldr r0, .L125+36 + 1128 .LVL133: + 1129 0284 25E7 b .L40 + 1130 .LVL134: + 1131 .L85: + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1132 .loc 1 536 0 + 1133 0286 8020 movs r0, #128 + 1134 .LVL135: + 1135 0288 0002 lsls r0, r0, #8 + 1136 028a 22E7 b .L40 + 1137 .LVL136: + 1138 .L88: + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1139 .loc 1 569 0 + 1140 028c 8020 movs r0, #128 + 1141 .LVL137: + 1142 028e 0002 lsls r0, r0, #8 + 1143 0290 1FE7 b .L40 + ARM GAS /tmp/cc4UWnQP.s page 35 + + + 1144 .LVL138: + 1145 .L91: + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1146 .loc 1 601 0 + 1147 0292 8020 movs r0, #128 + 1148 .LVL139: + 1149 0294 0002 lsls r0, r0, #8 + 1150 0296 1CE7 b .L40 + 1151 .L126: + 1152 .align 2 + 1153 .L125: + 1154 0298 00100240 .word 1073876992 + 1155 029c 88900000 .word 37000 + 1156 02a0 00093D00 .word 4000000 + 1157 02a4 20A10700 .word 500000 + 1158 02a8 80841E00 .word 2000000 + 1159 02ac 00000000 .word PLLMulTable + 1160 02b0 0024F400 .word 16000000 + 1161 02b4 00127A00 .word 8000000 + 1162 02b8 40420F00 .word 1000000 + 1163 02bc 006CDC02 .word 48000000 + 1164 .cfi_endproc + 1165 .LFE41: + 1167 .section .text.HAL_RCCEx_EnableLSECSS,"ax",%progbits + 1168 .align 1 + 1169 .global HAL_RCCEx_EnableLSECSS + 1170 .syntax unified + 1171 .code 16 + 1172 .thumb_func + 1173 .fpu softvfp + 1175 HAL_RCCEx_EnableLSECSS: + 1176 .LFB42: + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Enables the LSE Clock Security System. + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS(void) + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1177 .loc 1 696 0 + 1178 .cfi_startproc + 1179 @ args = 0, pretend = 0, frame = 0 + 1180 @ frame_needed = 0, uses_anonymous_args = 0 + 1181 @ link register save eliminated. + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; + 1182 .loc 1 697 0 + 1183 0000 034A ldr r2, .L128 + 1184 0002 116D ldr r1, [r2, #80] + 1185 0004 8023 movs r3, #128 + 1186 0006 9B01 lsls r3, r3, #6 + 1187 0008 0B43 orrs r3, r1 + 1188 000a 1365 str r3, [r2, #80] + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1189 .loc 1 698 0 + 1190 @ sp needed + 1191 000c 7047 bx lr + 1192 .L129: + ARM GAS /tmp/cc4UWnQP.s page 36 + + + 1193 000e C046 .align 2 + 1194 .L128: + 1195 0010 00100240 .word 1073876992 + 1196 .cfi_endproc + 1197 .LFE42: + 1199 .section .text.HAL_RCCEx_DisableLSECSS,"ax",%progbits + 1200 .align 1 + 1201 .global HAL_RCCEx_DisableLSECSS + 1202 .syntax unified + 1203 .code 16 + 1204 .thumb_func + 1205 .fpu softvfp + 1207 HAL_RCCEx_DisableLSECSS: + 1208 .LFB43: + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Disables the LSE Clock Security System. + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note Once enabled this bit cannot be disabled, except after an LSE failure detection + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * Reset by power on reset and RTC software reset (RTCRST bit). + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSECSS(void) + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1209 .loc 1 708 0 + 1210 .cfi_startproc + 1211 @ args = 0, pretend = 0, frame = 0 + 1212 @ frame_needed = 0, uses_anonymous_args = 0 + 1213 @ link register save eliminated. + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Disable LSE CSS */ + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; + 1214 .loc 1 710 0 + 1215 0000 044B ldr r3, .L131 + 1216 0002 1A6D ldr r2, [r3, #80] + 1217 0004 0449 ldr r1, .L131+4 + 1218 0006 0A40 ands r2, r1 + 1219 0008 1A65 str r2, [r3, #80] + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Disable LSE CSS IT */ + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); + 1220 .loc 1 713 0 + 1221 000a 1A69 ldr r2, [r3, #16] + 1222 000c 8021 movs r1, #128 + 1223 000e 8A43 bics r2, r1 + 1224 0010 1A61 str r2, [r3, #16] + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1225 .loc 1 714 0 + 1226 @ sp needed + 1227 0012 7047 bx lr + 1228 .L132: + 1229 .align 2 + 1230 .L131: + 1231 0014 00100240 .word 1073876992 + 1232 0018 FFDFFFFF .word -8193 + 1233 .cfi_endproc + 1234 .LFE43: + 1236 .section .text.HAL_RCCEx_EnableLSECSS_IT,"ax",%progbits + ARM GAS /tmp/cc4UWnQP.s page 37 + + + 1237 .align 1 + 1238 .global HAL_RCCEx_EnableLSECSS_IT + 1239 .syntax unified + 1240 .code 16 + 1241 .thumb_func + 1242 .fpu softvfp + 1244 HAL_RCCEx_EnableLSECSS_IT: + 1245 .LFB44: + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS_IT(void) + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1246 .loc 1 722 0 + 1247 .cfi_startproc + 1248 @ args = 0, pretend = 0, frame = 0 + 1249 @ frame_needed = 0, uses_anonymous_args = 0 + 1250 @ link register save eliminated. + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable LSE CSS */ + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; + 1251 .loc 1 724 0 + 1252 0000 094B ldr r3, .L134 + 1253 0002 196D ldr r1, [r3, #80] + 1254 0004 8022 movs r2, #128 + 1255 0006 9201 lsls r2, r2, #6 + 1256 0008 0A43 orrs r2, r1 + 1257 000a 1A65 str r2, [r3, #80] + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable LSE CSS IT */ + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + 1258 .loc 1 727 0 + 1259 000c 1A69 ldr r2, [r3, #16] + 1260 000e 8021 movs r1, #128 + 1261 0010 0A43 orrs r2, r1 + 1262 0012 1A61 str r2, [r3, #16] + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable IT on EXTI Line 19 */ + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); + 1263 .loc 1 730 0 + 1264 0014 054B ldr r3, .L134+4 + 1265 0016 1968 ldr r1, [r3] + 1266 0018 8022 movs r2, #128 + 1267 001a 1203 lsls r2, r2, #12 + 1268 001c 1143 orrs r1, r2 + 1269 001e 1960 str r1, [r3] + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); + 1270 .loc 1 731 0 + 1271 0020 9968 ldr r1, [r3, #8] + 1272 0022 0A43 orrs r2, r1 + 1273 0024 9A60 str r2, [r3, #8] + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1274 .loc 1 732 0 + 1275 @ sp needed + 1276 0026 7047 bx lr + ARM GAS /tmp/cc4UWnQP.s page 38 + + + 1277 .L135: + 1278 .align 2 + 1279 .L134: + 1280 0028 00100240 .word 1073876992 + 1281 002c 00040140 .word 1073808384 + 1282 .cfi_endproc + 1283 .LFE44: + 1285 .section .text.HAL_RCCEx_LSECSS_Callback,"ax",%progbits + 1286 .align 1 + 1287 .weak HAL_RCCEx_LSECSS_Callback + 1288 .syntax unified + 1289 .code 16 + 1290 .thumb_func + 1291 .fpu softvfp + 1293 HAL_RCCEx_LSECSS_Callback: + 1294 .LFB46: + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Handle the RCC LSE Clock Security System interrupt request. + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_LSECSS_IRQHandler(void) + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */ + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* RCC LSE Clock Security System interrupt user callback */ + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_LSECSS_Callback(); + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear RCC LSE CSS pending bit */ + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCCEx LSE Clock Security System interrupt callback. + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval none + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_LSECSS_Callback(void) + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1295 .loc 1 756 0 + 1296 .cfi_startproc + 1297 @ args = 0, pretend = 0, frame = 0 + 1298 @ frame_needed = 0, uses_anonymous_args = 0 + 1299 @ link register save eliminated. + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1300 .loc 1 760 0 + 1301 @ sp needed + 1302 0000 7047 bx lr + 1303 .cfi_endproc + 1304 .LFE46: + 1306 .section .text.HAL_RCCEx_LSECSS_IRQHandler,"ax",%progbits + 1307 .align 1 + 1308 .global HAL_RCCEx_LSECSS_IRQHandler + ARM GAS /tmp/cc4UWnQP.s page 39 + + + 1309 .syntax unified + 1310 .code 16 + 1311 .thumb_func + 1312 .fpu softvfp + 1314 HAL_RCCEx_LSECSS_IRQHandler: + 1315 .LFB45: + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */ + 1316 .loc 1 739 0 + 1317 .cfi_startproc + 1318 @ args = 0, pretend = 0, frame = 0 + 1319 @ frame_needed = 0, uses_anonymous_args = 0 + 1320 0000 10B5 push {r4, lr} + 1321 .LCFI3: + 1322 .cfi_def_cfa_offset 8 + 1323 .cfi_offset 4, -8 + 1324 .cfi_offset 14, -4 + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1325 .loc 1 741 0 + 1326 0002 054B ldr r3, .L140 + 1327 0004 5B69 ldr r3, [r3, #20] + 1328 0006 1B06 lsls r3, r3, #24 + 1329 0008 00D4 bmi .L139 + 1330 .L137: + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1331 .loc 1 749 0 + 1332 @ sp needed + 1333 000a 10BD pop {r4, pc} + 1334 .L139: + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1335 .loc 1 744 0 + 1336 000c FFF7FEFF bl HAL_RCCEx_LSECSS_Callback + 1337 .LVL140: + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1338 .loc 1 747 0 + 1339 0010 014B ldr r3, .L140 + 1340 0012 8022 movs r2, #128 + 1341 0014 9A61 str r2, [r3, #24] + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1342 .loc 1 749 0 + 1343 0016 F8E7 b .L137 + 1344 .L141: + 1345 .align 2 + 1346 .L140: + 1347 0018 00100240 .word 1073876992 + 1348 .cfi_endproc + 1349 .LFE45: + 1351 .section .text.HAL_RCCEx_EnableHSI48_VREFINT,"ax",%progbits + 1352 .align 1 + 1353 .global HAL_RCCEx_EnableHSI48_VREFINT + 1354 .syntax unified + 1355 .code 16 + 1356 .thumb_func + 1357 .fpu softvfp + 1359 HAL_RCCEx_EnableHSI48_VREFINT: + 1360 .LFB47: + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined(SYSCFG_CFGR3_ENREF_HSI48) + ARM GAS /tmp/cc4UWnQP.s page 40 + + + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Enables Vrefint for the HSI48. + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note This is functional only if the LOCK is not set + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableHSI48_VREFINT(void) + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1361 .loc 1 769 0 + 1362 .cfi_startproc + 1363 @ args = 0, pretend = 0, frame = 0 + 1364 @ frame_needed = 0, uses_anonymous_args = 0 + 1365 @ link register save eliminated. + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); + 1366 .loc 1 771 0 + 1367 0000 034A ldr r2, .L143 + 1368 0002 116A ldr r1, [r2, #32] + 1369 0004 8023 movs r3, #128 + 1370 0006 9B01 lsls r3, r3, #6 + 1371 0008 0B43 orrs r3, r1 + 1372 000a 1362 str r3, [r2, #32] + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1373 .loc 1 772 0 + 1374 @ sp needed + 1375 000c 7047 bx lr + 1376 .L144: + 1377 000e C046 .align 2 + 1378 .L143: + 1379 0010 00000140 .word 1073807360 + 1380 .cfi_endproc + 1381 .LFE47: + 1383 .section .text.HAL_RCCEx_DisableHSI48_VREFINT,"ax",%progbits + 1384 .align 1 + 1385 .global HAL_RCCEx_DisableHSI48_VREFINT + 1386 .syntax unified + 1387 .code 16 + 1388 .thumb_func + 1389 .fpu softvfp + 1391 HAL_RCCEx_DisableHSI48_VREFINT: + 1392 .LFB48: + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Disables the Vrefint for the HSI48. + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note This is functional only if the LOCK is not set + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableHSI48_VREFINT(void) + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1393 .loc 1 780 0 + 1394 .cfi_startproc + 1395 @ args = 0, pretend = 0, frame = 0 + 1396 @ frame_needed = 0, uses_anonymous_args = 0 + 1397 @ link register save eliminated. + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */ + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); + 1398 .loc 1 782 0 + 1399 0000 024A ldr r2, .L146 + ARM GAS /tmp/cc4UWnQP.s page 41 + + + 1400 0002 136A ldr r3, [r2, #32] + 1401 0004 0249 ldr r1, .L146+4 + 1402 0006 0B40 ands r3, r1 + 1403 0008 1362 str r3, [r2, #32] + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1404 .loc 1 783 0 + 1405 @ sp needed + 1406 000a 7047 bx lr + 1407 .L147: + 1408 .align 2 + 1409 .L146: + 1410 000c 00000140 .word 1073807360 + 1411 0010 FFDFFFFF .word -8193 + 1412 .cfi_endproc + 1413 .LFE48: + 1415 .section .text.HAL_RCCEx_CRSConfig,"ax",%progbits + 1416 .align 1 + 1417 .global HAL_RCCEx_CRSConfig + 1418 .syntax unified + 1419 .code 16 + 1420 .thumb_func + 1421 .fpu softvfp + 1423 HAL_RCCEx_CRSConfig: + 1424 .LFB49: + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #endif /* SYSCFG_CFGR3_ENREF_HSI48 */ + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @} + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** #if defined (CRS) + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Extended Clock Recovery System Control functions + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** @verbatim + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** =============================================================================== + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** ##### Extended Clock Recovery System Control functions ##### + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** =============================================================================== + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** [..] + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) In System clock config, HSI48 needs to be enabled + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) Enable CRS clock in IP MSP init which will use CRS functions + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) Call CRS functions as follows: + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (##) Prepare synchronization configuration necessary for HSI48 calibration + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Default values can be set for frequency Error Measurement (reload and error lim + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** and also HSI48 oscillator smooth trimming. + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** directly reload value with target and synchronization frequencies values + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (##) Call function @ref HAL_RCCEx_CRSConfig which + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Reset CRS registers to their default values. + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Configure CRS registers with synchronization configuration + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Enable automatic calibration and frequency error counter feature + ARM GAS /tmp/cc4UWnQP.s page 42 + + + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** should be used as SYNC signal. + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (##) A polling function is provided to wait for complete synchronization + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) According to CRS status, user can decide to adjust again the calibration or con + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** application if synchronization is OK + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) User can retrieve information related to synchronization in calling function + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** @ref HAL_RCCEx_CRSGetSynchronizationInfo() + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) Regarding synchronization status and synchronization information, user can try a new cali + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** Note: When the SYNC event is detected during the downcounting phase (before reaching the + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** it means that the actual frequency is lower than the target (and so, that the TRIM value + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** incremented), while when it is detected during the upcounting phase it means that the ac + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** is higher (and that the TRIM value should be decremented). + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interr + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** through CRS Handler (RCC_IRQn/RCC_IRQHandler) + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (++) Call function @ref HAL_RCCEx_CRSConfig() + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (++) Enable RCC_IRQn (thanks to NVIC functions) + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (++) Implement CRS status management in the following user callbacks called from + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_IRQHandler(): + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizatio + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Syst + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** @endverbatim + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @{ + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Start automatic synchronization for polling mode + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param pInit Pointer on RCC_CRSInitTypeDef structure + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1425 .loc 1 863 0 + 1426 .cfi_startproc + 1427 @ args = 0, pretend = 0, frame = 0 + 1428 @ frame_needed = 0, uses_anonymous_args = 0 + 1429 @ link register save eliminated. + 1430 .LVL141: + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t value = 0; + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameters */ + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + ARM GAS /tmp/cc4UWnQP.s page 43 + + + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CONFIGURATION */ + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Before configuration, reset CRS registers to their default values*/ + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_FORCE_RESET(); + 1431 .loc 1 877 0 + 1432 0000 104B ldr r3, .L149 + 1433 0002 996A ldr r1, [r3, #40] + 1434 0004 8022 movs r2, #128 + 1435 0006 1205 lsls r2, r2, #20 + 1436 0008 0A43 orrs r2, r1 + 1437 000a 9A62 str r2, [r3, #40] + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET(); + 1438 .loc 1 878 0 + 1439 000c 9A6A ldr r2, [r3, #40] + 1440 000e 0E49 ldr r1, .L149+4 + 1441 0010 0A40 ands r2, r1 + 1442 0012 9A62 str r2, [r3, #40] + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the SYNCSRC[1:0] bits according to Source value */ + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the SYNCSPOL bit according to Polarity value */ + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + 1443 .loc 1 883 0 + 1444 0014 0268 ldr r2, [r0] + 1445 0016 4368 ldr r3, [r0, #4] + 1446 0018 1A43 orrs r2, r3 + 1447 001a 8368 ldr r3, [r0, #8] + 1448 001c 1A43 orrs r2, r3 + 1449 .LVL142: + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the RELOAD[15:0] bits according to ReloadValue value */ + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** value |= pInit->ReloadValue; + 1450 .loc 1 885 0 + 1451 001e C368 ldr r3, [r0, #12] + 1452 0020 1343 orrs r3, r2 + 1453 .LVL143: + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + 1454 .loc 1 887 0 + 1455 0022 0269 ldr r2, [r0, #16] + 1456 0024 1204 lsls r2, r2, #16 + 1457 0026 1A43 orrs r2, r3 + 1458 .LVL144: + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value); + 1459 .loc 1 888 0 + 1460 0028 084B ldr r3, .L149+8 + 1461 002a 5A60 str r2, [r3, #4] + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Adjust HSI48 oscillator smooth trimming */ + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); + 1462 .loc 1 892 0 + ARM GAS /tmp/cc4UWnQP.s page 44 + + + 1463 002c 1A68 ldr r2, [r3] + 1464 .LVL145: + 1465 002e 0849 ldr r1, .L149+12 + 1466 0030 0A40 ands r2, r1 + 1467 0032 4169 ldr r1, [r0, #20] + 1468 0034 0902 lsls r1, r1, #8 + 1469 0036 0A43 orrs r2, r1 + 1470 0038 1A60 str r2, [r3] + 1471 .LVL146: + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* START AUTOMATIC SYNCHRONIZATION*/ + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Enable Automatic trimming & Frequency error counter */ + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); + 1472 .loc 1 897 0 + 1473 003a 1A68 ldr r2, [r3] + 1474 003c 6021 movs r1, #96 + 1475 003e 0A43 orrs r2, r1 + 1476 0040 1A60 str r2, [r3] + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1477 .loc 1 898 0 + 1478 @ sp needed + 1479 0042 7047 bx lr + 1480 .L150: + 1481 .align 2 + 1482 .L149: + 1483 0044 00100240 .word 1073876992 + 1484 0048 FFFFFFF7 .word -134217729 + 1485 004c 006C0040 .word 1073769472 + 1486 0050 FFC0FFFF .word -16129 + 1487 .cfi_endproc + 1488 .LFE49: + 1490 .section .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate,"ax",%progbits + 1491 .align 1 + 1492 .global HAL_RCCEx_CRSSoftwareSynchronizationGenerate + 1493 .syntax unified + 1494 .code 16 + 1495 .thumb_func + 1496 .fpu softvfp + 1498 HAL_RCCEx_CRSSoftwareSynchronizationGenerate: + 1499 .LFB50: + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Generate the software synchronization event + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1500 .loc 1 905 0 + 1501 .cfi_startproc + 1502 @ args = 0, pretend = 0, frame = 0 + 1503 @ frame_needed = 0, uses_anonymous_args = 0 + 1504 @ link register save eliminated. + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_SWSYNC); + 1505 .loc 1 906 0 + 1506 0000 024A ldr r2, .L152 + 1507 0002 1368 ldr r3, [r2] + ARM GAS /tmp/cc4UWnQP.s page 45 + + + 1508 0004 8021 movs r1, #128 + 1509 0006 0B43 orrs r3, r1 + 1510 0008 1360 str r3, [r2] + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1511 .loc 1 907 0 + 1512 @ sp needed + 1513 000a 7047 bx lr + 1514 .L153: + 1515 .align 2 + 1516 .L152: + 1517 000c 006C0040 .word 1073769472 + 1518 .cfi_endproc + 1519 .LFE50: + 1521 .section .text.HAL_RCCEx_CRSGetSynchronizationInfo,"ax",%progbits + 1522 .align 1 + 1523 .global HAL_RCCEx_CRSGetSynchronizationInfo + 1524 .syntax unified + 1525 .code 16 + 1526 .thumb_func + 1527 .fpu softvfp + 1529 HAL_RCCEx_CRSGetSynchronizationInfo: + 1530 .LFB51: + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Return synchronization info + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1531 .loc 1 915 0 + 1532 .cfi_startproc + 1533 @ args = 0, pretend = 0, frame = 0 + 1534 @ frame_needed = 0, uses_anonymous_args = 0 + 1535 @ link register save eliminated. + 1536 .LVL147: + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check the parameter */ + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** assert_param(pSynchroInfo != NULL); + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get the reload value */ + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + 1537 .loc 1 920 0 + 1538 0000 094A ldr r2, .L155 + 1539 0002 5368 ldr r3, [r2, #4] + 1540 0004 1B04 lsls r3, r3, #16 + 1541 0006 1B0C lsrs r3, r3, #16 + 1542 0008 0360 str r3, [r0] + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get HSI48 oscillator smooth trimming */ + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BI + 1543 .loc 1 923 0 + 1544 000a 1168 ldr r1, [r2] + 1545 000c 090A lsrs r1, r1, #8 + 1546 000e 3F23 movs r3, #63 + 1547 0010 0B40 ands r3, r1 + 1548 0012 4360 str r3, [r0, #4] + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + ARM GAS /tmp/cc4UWnQP.s page 46 + + + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get Frequency error capture */ + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BI + 1549 .loc 1 926 0 + 1550 0014 9368 ldr r3, [r2, #8] + 1551 0016 1B0C lsrs r3, r3, #16 + 1552 0018 8360 str r3, [r0, #8] + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get Frequency error direction */ + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); + 1553 .loc 1 929 0 + 1554 001a 9368 ldr r3, [r2, #8] + 1555 001c 8022 movs r2, #128 + 1556 001e 1202 lsls r2, r2, #8 + 1557 0020 1340 ands r3, r2 + 1558 0022 C360 str r3, [r0, #12] + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1559 .loc 1 930 0 + 1560 @ sp needed + 1561 0024 7047 bx lr + 1562 .L156: + 1563 0026 C046 .align 2 + 1564 .L155: + 1565 0028 006C0040 .word 1073769472 + 1566 .cfi_endproc + 1567 .LFE51: + 1569 .section .text.HAL_RCCEx_CRSWaitSynchronization,"ax",%progbits + 1570 .align 1 + 1571 .global HAL_RCCEx_CRSWaitSynchronization + 1572 .syntax unified + 1573 .code 16 + 1574 .thumb_func + 1575 .fpu softvfp + 1577 HAL_RCCEx_CRSWaitSynchronization: + 1578 .LFB52: + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Wait for CRS Synchronization status. + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param Timeout Duration of the timeout + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * frequency. + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval Combination of Synchronization status + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values: + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TIMEOUT + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCOK + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCWARN + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1579 .loc 1 948 0 + 1580 .cfi_startproc + 1581 @ args = 0, pretend = 0, frame = 0 + 1582 @ frame_needed = 0, uses_anonymous_args = 0 + 1583 .LVL148: + ARM GAS /tmp/cc4UWnQP.s page 47 + + + 1584 0000 70B5 push {r4, r5, r6, lr} + 1585 .LCFI4: + 1586 .cfi_def_cfa_offset 16 + 1587 .cfi_offset 4, -16 + 1588 .cfi_offset 5, -12 + 1589 .cfi_offset 6, -8 + 1590 .cfi_offset 14, -4 + 1591 0002 0500 movs r5, r0 + 1592 .LVL149: + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE; + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get timeout */ + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 1593 .loc 1 953 0 + 1594 0004 FFF7FEFF bl HAL_GetTick + 1595 .LVL150: + 1596 0008 0600 movs r6, r0 + 1597 .LVL151: + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE; + 1598 .loc 1 949 0 + 1599 000a 0024 movs r4, #0 + 1600 000c 3AE0 b .L165 + 1601 .LVL152: + 1602 .L169: + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Wait for CRS flag or timeout detection */ + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** do + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + 1603 .loc 1 960 0 discriminator 1 + 1604 000e FFF7FEFF bl HAL_GetTick + 1605 .LVL153: + 1606 0012 801B subs r0, r0, r6 + 1607 0014 A842 cmp r0, r5 + 1608 0016 3BD8 bhi .L167 + 1609 .LVL154: + 1610 .L158: + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus = RCC_CRS_TIMEOUT; + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */ + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + 1611 .loc 1 966 0 + 1612 0018 1F4B ldr r3, .L170 + 1613 001a 9B68 ldr r3, [r3, #8] + 1614 001c DB07 lsls r3, r3, #31 + 1615 001e 04D5 bpl .L159 + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CRS SYNC event OK */ + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCOK; + 1616 .loc 1 969 0 + 1617 0020 0223 movs r3, #2 + 1618 0022 1C43 orrs r4, r3 + ARM GAS /tmp/cc4UWnQP.s page 48 + + + 1619 .LVL155: + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK bit */ + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + 1620 .loc 1 972 0 + 1621 0024 1C4B ldr r3, .L170 + 1622 0026 0122 movs r2, #1 + 1623 0028 DA60 str r2, [r3, #12] + 1624 .L159: + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */ + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + 1625 .loc 1 976 0 + 1626 002a 1B4B ldr r3, .L170 + 1627 002c 9B68 ldr r3, [r3, #8] + 1628 002e 9B07 lsls r3, r3, #30 + 1629 0030 04D5 bpl .L160 + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CRS SYNC warning */ + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCWARN; + 1630 .loc 1 979 0 + 1631 0032 0423 movs r3, #4 + 1632 0034 1C43 orrs r4, r3 + 1633 .LVL156: + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN bit */ + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + 1634 .loc 1 982 0 + 1635 0036 184B ldr r3, .L170 + 1636 0038 0222 movs r2, #2 + 1637 003a DA60 str r2, [r3, #12] + 1638 .L160: + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS TRIM overflow flag */ + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + 1639 .loc 1 986 0 + 1640 003c 164B ldr r3, .L170 + 1641 003e 9B68 ldr r3, [r3, #8] + 1642 0040 5B05 lsls r3, r3, #21 + 1643 0042 04D5 bpl .L161 + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CRS SYNC Error */ + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_TRIMOVF; + 1644 .loc 1 989 0 + 1645 0044 2023 movs r3, #32 + 1646 0046 1C43 orrs r4, r3 + 1647 .LVL157: + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS Error bit */ + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + 1648 .loc 1 992 0 + 1649 0048 134B ldr r3, .L170 + 1650 004a 0422 movs r2, #4 + 1651 004c DA60 str r2, [r3, #12] + 1652 .L161: + ARM GAS /tmp/cc4UWnQP.s page 49 + + + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS Error flag */ + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + 1653 .loc 1 996 0 + 1654 004e 124B ldr r3, .L170 + 1655 0050 9B68 ldr r3, [r3, #8] + 1656 0052 DB05 lsls r3, r3, #23 + 1657 0054 04D5 bpl .L162 + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CRS SYNC Error */ + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCERR; + 1658 .loc 1 999 0 + 1659 0056 0823 movs r3, #8 + 1660 0058 1C43 orrs r4, r3 + 1661 .LVL158: +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS Error bit */ +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + 1662 .loc 1 1002 0 + 1663 005a 0F4B ldr r3, .L170 + 1664 005c 0422 movs r2, #4 + 1665 005e DA60 str r2, [r3, #12] + 1666 .L162: +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS SYNC Missed flag */ +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + 1667 .loc 1 1006 0 + 1668 0060 0D4B ldr r3, .L170 + 1669 0062 9B68 ldr r3, [r3, #8] + 1670 0064 9B05 lsls r3, r3, #22 + 1671 0066 04D5 bpl .L163 +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* CRS SYNC Missed */ +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCMISS; + 1672 .loc 1 1009 0 + 1673 0068 1023 movs r3, #16 + 1674 006a 1C43 orrs r4, r3 + 1675 .LVL159: +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS SYNC Missed bit */ +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + 1676 .loc 1 1012 0 + 1677 006c 0A4B ldr r3, .L170 + 1678 006e 0422 movs r2, #4 + 1679 0070 DA60 str r2, [r3, #12] + 1680 .L163: +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */ +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + 1681 .loc 1 1016 0 + 1682 0072 094B ldr r3, .L170 + 1683 0074 9B68 ldr r3, [r3, #8] + 1684 0076 1B07 lsls r3, r3, #28 + 1685 0078 02D5 bpl .L164 + ARM GAS /tmp/cc4UWnQP.s page 50 + + +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */ +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + 1686 .loc 1 1019 0 discriminator 2 + 1687 007a 074B ldr r3, .L170 + 1688 007c 0822 movs r2, #8 + 1689 007e DA60 str r2, [r3, #12] + 1690 .L164: +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } while(RCC_CRS_NONE == crsstatus); + 1691 .loc 1 1021 0 + 1692 0080 002C cmp r4, #0 + 1693 0082 07D1 bne .L168 + 1694 .LVL160: + 1695 .L165: + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1696 .loc 1 958 0 + 1697 0084 6B1C adds r3, r5, #1 + 1698 0086 C7D0 beq .L158 + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1699 .loc 1 960 0 + 1700 0088 002D cmp r5, #0 + 1701 008a C0D1 bne .L169 + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1702 .loc 1 962 0 + 1703 008c 0124 movs r4, #1 + 1704 .LVL161: + 1705 008e C3E7 b .L158 + 1706 .LVL162: + 1707 .L167: + 1708 0090 0124 movs r4, #1 + 1709 .LVL163: + 1710 0092 C1E7 b .L158 + 1711 .LVL164: + 1712 .L168: +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** return crsstatus; +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1713 .loc 1 1024 0 + 1714 0094 2000 movs r0, r4 + 1715 @ sp needed + 1716 .LVL165: + 1717 .LVL166: + 1718 .LVL167: + 1719 0096 70BD pop {r4, r5, r6, pc} + 1720 .L171: + 1721 .align 2 + 1722 .L170: + 1723 0098 006C0040 .word 1073769472 + 1724 .cfi_endproc + 1725 .LFE52: + 1727 .section .text.HAL_RCCEx_CRS_SyncOkCallback,"ax",%progbits + 1728 .align 1 + 1729 .weak HAL_RCCEx_CRS_SyncOkCallback + 1730 .syntax unified + 1731 .code 16 + 1732 .thumb_func + ARM GAS /tmp/cc4UWnQP.s page 51 + + + 1733 .fpu softvfp + 1735 HAL_RCCEx_CRS_SyncOkCallback: + 1736 .LFB54: +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief Handle the Clock Recovery System interrupt request. +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval None +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** void HAL_RCCEx_CRS_IRQHandler(void) +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE; +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get current IT flags and IT sources values */ +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t itflags = READ_REG(CRS->ISR); +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR); +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */ +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK flag */ +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* user callback */ +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncOkCallback(); +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */ +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RES +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN flag */ +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* user callback */ +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncWarnCallback(); +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */ +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */ +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* user callback */ +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ExpectedSyncCallback(); +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Check CRS Error flags */ +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** else +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCERR; +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCMISS; +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + ARM GAS /tmp/cc4UWnQP.s page 52 + + +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** crserror |= RCC_CRS_TRIMOVF; +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Clear CRS Error flags */ +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* user error callback */ +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ErrorCallback(crserror); +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval none +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncOkCallback(void) +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1737 .loc 1 1096 0 + 1738 .cfi_startproc + 1739 @ args = 0, pretend = 0, frame = 0 + 1740 @ frame_needed = 0, uses_anonymous_args = 0 + 1741 @ link register save eliminated. +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1742 .loc 1 1100 0 + 1743 @ sp needed + 1744 0000 7047 bx lr + 1745 .cfi_endproc + 1746 .LFE54: + 1748 .section .text.HAL_RCCEx_CRS_SyncWarnCallback,"ax",%progbits + 1749 .align 1 + 1750 .weak HAL_RCCEx_CRS_SyncWarnCallback + 1751 .syntax unified + 1752 .code 16 + 1753 .thumb_func + 1754 .fpu softvfp + 1756 HAL_RCCEx_CRS_SyncWarnCallback: + 1757 .LFB55: +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval none +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1758 .loc 1 1107 0 + 1759 .cfi_startproc + 1760 @ args = 0, pretend = 0, frame = 0 + 1761 @ frame_needed = 0, uses_anonymous_args = 0 + 1762 @ link register save eliminated. +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 53 + + + 1763 .loc 1 1111 0 + 1764 @ sp needed + 1765 0000 7047 bx lr + 1766 .cfi_endproc + 1767 .LFE55: + 1769 .section .text.HAL_RCCEx_CRS_ExpectedSyncCallback,"ax",%progbits + 1770 .align 1 + 1771 .weak HAL_RCCEx_CRS_ExpectedSyncCallback + 1772 .syntax unified + 1773 .code 16 + 1774 .thumb_func + 1775 .fpu softvfp + 1777 HAL_RCCEx_CRS_ExpectedSyncCallback: + 1778 .LFB56: +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval none +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1779 .loc 1 1118 0 + 1780 .cfi_startproc + 1781 @ args = 0, pretend = 0, frame = 0 + 1782 @ frame_needed = 0, uses_anonymous_args = 0 + 1783 @ link register save eliminated. +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1784 .loc 1 1122 0 + 1785 @ sp needed + 1786 0000 7047 bx lr + 1787 .cfi_endproc + 1788 .LFE56: + 1790 .section .text.HAL_RCCEx_CRS_ErrorCallback,"ax",%progbits + 1791 .align 1 + 1792 .weak HAL_RCCEx_CRS_ErrorCallback + 1793 .syntax unified + 1794 .code 16 + 1795 .thumb_func + 1796 .fpu softvfp + 1798 HAL_RCCEx_CRS_ErrorCallback: + 1799 .LFB57: +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /** +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Error interrupt callback. +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @param Error Combination of Error status. +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values: +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** * @retval none +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1800 .loc 1 1134 0 + ARM GAS /tmp/cc4UWnQP.s page 54 + + + 1801 .cfi_startproc + 1802 @ args = 0, pretend = 0, frame = 0 + 1803 @ frame_needed = 0, uses_anonymous_args = 0 + 1804 @ link register save eliminated. + 1805 .LVL168: +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Prevent unused argument(s) compilation warning */ +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** UNUSED(Error); +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** */ +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1806 .loc 1 1141 0 + 1807 @ sp needed + 1808 0000 7047 bx lr + 1809 .cfi_endproc + 1810 .LFE57: + 1812 .section .text.HAL_RCCEx_CRS_IRQHandler,"ax",%progbits + 1813 .align 1 + 1814 .global HAL_RCCEx_CRS_IRQHandler + 1815 .syntax unified + 1816 .code 16 + 1817 .thumb_func + 1818 .fpu softvfp + 1820 HAL_RCCEx_CRS_IRQHandler: + 1821 .LFB53: +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE; + 1822 .loc 1 1031 0 + 1823 .cfi_startproc + 1824 @ args = 0, pretend = 0, frame = 0 + 1825 @ frame_needed = 0, uses_anonymous_args = 0 + 1826 0000 10B5 push {r4, lr} + 1827 .LCFI5: + 1828 .cfi_def_cfa_offset 8 + 1829 .cfi_offset 4, -8 + 1830 .cfi_offset 14, -4 + 1831 .LVL169: +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR); + 1832 .loc 1 1034 0 + 1833 0002 1C4A ldr r2, .L188 + 1834 0004 9368 ldr r3, [r2, #8] + 1835 .LVL170: +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1836 .loc 1 1035 0 + 1837 0006 1268 ldr r2, [r2] + 1838 .LVL171: +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1839 .loc 1 1038 0 + 1840 0008 D907 lsls r1, r3, #31 + 1841 000a 01D5 bpl .L177 +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1842 .loc 1 1038 0 is_stmt 0 discriminator 1 + 1843 000c D107 lsls r1, r2, #31 + 1844 000e 1CD4 bmi .L185 + 1845 .L177: +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1846 .loc 1 1047 0 is_stmt 1 + ARM GAS /tmp/cc4UWnQP.s page 55 + + + 1847 0010 9907 lsls r1, r3, #30 + 1848 0012 01D5 bpl .L179 +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1849 .loc 1 1047 0 is_stmt 0 discriminator 1 + 1850 0014 9107 lsls r1, r2, #30 + 1851 0016 1ED4 bmi .L186 + 1852 .L179: +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1853 .loc 1 1056 0 is_stmt 1 + 1854 0018 1907 lsls r1, r3, #28 + 1855 001a 01D5 bpl .L180 +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1856 .loc 1 1056 0 is_stmt 0 discriminator 1 + 1857 001c 1107 lsls r1, r2, #28 + 1858 001e 20D4 bmi .L187 + 1859 .L180: +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1860 .loc 1 1067 0 is_stmt 1 + 1861 0020 5907 lsls r1, r3, #29 + 1862 0022 11D5 bpl .L176 +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1863 .loc 1 1067 0 is_stmt 0 discriminator 1 + 1864 0024 5207 lsls r2, r2, #29 + 1865 0026 0FD5 bpl .L176 + 1866 .LVL172: +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1867 .loc 1 1069 0 is_stmt 1 + 1868 0028 DA05 lsls r2, r3, #23 + 1869 002a 20D4 bmi .L184 +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** /* Get current IT flags and IT sources values */ + 1870 .loc 1 1032 0 + 1871 002c 0020 movs r0, #0 + 1872 .L181: + 1873 .LVL173: +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1874 .loc 1 1073 0 + 1875 002e 9A05 lsls r2, r3, #22 + 1876 0030 01D5 bpl .L182 +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1877 .loc 1 1075 0 + 1878 0032 1022 movs r2, #16 + 1879 0034 1043 orrs r0, r2 + 1880 .LVL174: + 1881 .L182: +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** { + 1882 .loc 1 1077 0 + 1883 0036 5B05 lsls r3, r3, #21 + 1884 0038 01D5 bpl .L183 + 1885 .LVL175: +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1886 .loc 1 1079 0 + 1887 003a 2023 movs r3, #32 + 1888 003c 1843 orrs r0, r3 + 1889 .LVL176: + 1890 .L183: +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1891 .loc 1 1083 0 + ARM GAS /tmp/cc4UWnQP.s page 56 + + + 1892 003e 0D4B ldr r3, .L188 + 1893 0040 0422 movs r2, #4 + 1894 0042 DA60 str r2, [r3, #12] +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1895 .loc 1 1086 0 + 1896 0044 FFF7FEFF bl HAL_RCCEx_CRS_ErrorCallback + 1897 .LVL177: + 1898 .L176: +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1899 .loc 1 1089 0 + 1900 @ sp needed + 1901 0048 10BD pop {r4, pc} + 1902 .LVL178: + 1903 .L185: +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1904 .loc 1 1041 0 + 1905 004a 0A4B ldr r3, .L188 + 1906 .LVL179: + 1907 004c 0122 movs r2, #1 + 1908 .LVL180: + 1909 004e DA60 str r2, [r3, #12] +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1910 .loc 1 1044 0 + 1911 0050 FFF7FEFF bl HAL_RCCEx_CRS_SyncOkCallback + 1912 .LVL181: + 1913 0054 F8E7 b .L176 + 1914 .LVL182: + 1915 .L186: +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1916 .loc 1 1050 0 + 1917 0056 074B ldr r3, .L188 + 1918 .LVL183: + 1919 0058 0222 movs r2, #2 + 1920 .LVL184: + 1921 005a DA60 str r2, [r3, #12] +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1922 .loc 1 1053 0 + 1923 005c FFF7FEFF bl HAL_RCCEx_CRS_SyncWarnCallback + 1924 .LVL185: + 1925 0060 F2E7 b .L176 + 1926 .LVL186: + 1927 .L187: +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** + 1928 .loc 1 1059 0 + 1929 0062 044B ldr r3, .L188 + 1930 .LVL187: + 1931 0064 0822 movs r2, #8 + 1932 .LVL188: + 1933 0066 DA60 str r2, [r3, #12] +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + 1934 .loc 1 1062 0 + 1935 0068 FFF7FEFF bl HAL_RCCEx_CRS_ExpectedSyncCallback + 1936 .LVL189: + 1937 006c ECE7 b .L176 + 1938 .LVL190: + 1939 .L184: +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/cc4UWnQP.s page 57 + + + 1940 .loc 1 1071 0 + 1941 006e 0820 movs r0, #8 + 1942 0070 DDE7 b .L181 + 1943 .L189: + 1944 0072 C046 .align 2 + 1945 .L188: + 1946 0074 006C0040 .word 1073769472 + 1947 .cfi_endproc + 1948 .LFE53: + 1950 .text + 1951 .Letext0: + 1952 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1953 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1954 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1955 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1956 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1957 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 1958 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 1959 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1960 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 1961 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 1962 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h" + 1963 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 1964 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h" + ARM GAS /tmp/cc4UWnQP.s page 58 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_rcc_ex.c + /tmp/cc4UWnQP.s:16 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t + /tmp/cc4UWnQP.s:23 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig + /tmp/cc4UWnQP.s:401 .text.HAL_RCCEx_PeriphCLKConfig:00000000000001e4 $d + /tmp/cc4UWnQP.s:416 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t + /tmp/cc4UWnQP.s:423 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/cc4UWnQP.s:519 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000078 $d + /tmp/cc4UWnQP.s:526 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t + /tmp/cc4UWnQP.s:533 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/cc4UWnQP.s:1154 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000298 $d + /tmp/cc4UWnQP.s:1168 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 $t + /tmp/cc4UWnQP.s:1175 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 HAL_RCCEx_EnableLSECSS + /tmp/cc4UWnQP.s:1195 .text.HAL_RCCEx_EnableLSECSS:0000000000000010 $d + /tmp/cc4UWnQP.s:1200 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 $t + /tmp/cc4UWnQP.s:1207 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 HAL_RCCEx_DisableLSECSS + /tmp/cc4UWnQP.s:1231 .text.HAL_RCCEx_DisableLSECSS:0000000000000014 $d + /tmp/cc4UWnQP.s:1237 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 $t + /tmp/cc4UWnQP.s:1244 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 HAL_RCCEx_EnableLSECSS_IT + /tmp/cc4UWnQP.s:1280 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000028 $d + /tmp/cc4UWnQP.s:1286 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 $t + /tmp/cc4UWnQP.s:1293 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 HAL_RCCEx_LSECSS_Callback + /tmp/cc4UWnQP.s:1307 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 $t + /tmp/cc4UWnQP.s:1314 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 HAL_RCCEx_LSECSS_IRQHandler + /tmp/cc4UWnQP.s:1347 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000018 $d + /tmp/cc4UWnQP.s:1352 .text.HAL_RCCEx_EnableHSI48_VREFINT:0000000000000000 $t + /tmp/cc4UWnQP.s:1359 .text.HAL_RCCEx_EnableHSI48_VREFINT:0000000000000000 HAL_RCCEx_EnableHSI48_VREFINT + /tmp/cc4UWnQP.s:1379 .text.HAL_RCCEx_EnableHSI48_VREFINT:0000000000000010 $d + /tmp/cc4UWnQP.s:1384 .text.HAL_RCCEx_DisableHSI48_VREFINT:0000000000000000 $t + /tmp/cc4UWnQP.s:1391 .text.HAL_RCCEx_DisableHSI48_VREFINT:0000000000000000 HAL_RCCEx_DisableHSI48_VREFINT + /tmp/cc4UWnQP.s:1410 .text.HAL_RCCEx_DisableHSI48_VREFINT:000000000000000c $d + /tmp/cc4UWnQP.s:1416 .text.HAL_RCCEx_CRSConfig:0000000000000000 $t + /tmp/cc4UWnQP.s:1423 .text.HAL_RCCEx_CRSConfig:0000000000000000 HAL_RCCEx_CRSConfig + /tmp/cc4UWnQP.s:1483 .text.HAL_RCCEx_CRSConfig:0000000000000044 $d + /tmp/cc4UWnQP.s:1491 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 $t + /tmp/cc4UWnQP.s:1498 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 HAL_RCCEx_CRSSoftwareSynchronizationGenerate + /tmp/cc4UWnQP.s:1517 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:000000000000000c $d + /tmp/cc4UWnQP.s:1522 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 $t + /tmp/cc4UWnQP.s:1529 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 HAL_RCCEx_CRSGetSynchronizationInfo + /tmp/cc4UWnQP.s:1565 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000028 $d + /tmp/cc4UWnQP.s:1570 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 $t + /tmp/cc4UWnQP.s:1577 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 HAL_RCCEx_CRSWaitSynchronization + /tmp/cc4UWnQP.s:1723 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000098 $d + /tmp/cc4UWnQP.s:1728 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 $t + /tmp/cc4UWnQP.s:1735 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 HAL_RCCEx_CRS_SyncOkCallback + /tmp/cc4UWnQP.s:1749 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 $t + /tmp/cc4UWnQP.s:1756 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 HAL_RCCEx_CRS_SyncWarnCallback + /tmp/cc4UWnQP.s:1770 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 $t + /tmp/cc4UWnQP.s:1777 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 HAL_RCCEx_CRS_ExpectedSyncCallback + /tmp/cc4UWnQP.s:1791 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 $t + /tmp/cc4UWnQP.s:1798 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 HAL_RCCEx_CRS_ErrorCallback + /tmp/cc4UWnQP.s:1813 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 $t + /tmp/cc4UWnQP.s:1820 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 HAL_RCCEx_CRS_IRQHandler + /tmp/cc4UWnQP.s:1946 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000074 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS + ARM GAS /tmp/cc4UWnQP.s page 59 + + +HAL_GetTick +__aeabi_uidiv +HAL_RCC_GetPCLK2Freq +HAL_RCC_GetSysClockFreq +HAL_RCC_GetPCLK1Freq +PLLMulTable diff --git a/build/stm32l0xx_hal_rng.d b/build/stm32l0xx_hal_rng.d new file mode 100644 index 0000000..ecaba83 --- /dev/null +++ b/build/stm32l0xx_hal_rng.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_rng.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_rng.lst b/build/stm32l0xx_hal_rng.lst new file mode 100644 index 0000000..01a5dcd --- /dev/null +++ b/build/stm32l0xx_hal_rng.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccsrYcbn.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_rng.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccsrYcbn.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_rng.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_rtc.d b/build/stm32l0xx_hal_rtc.d new file mode 100644 index 0000000..114019b --- /dev/null +++ b/build/stm32l0xx_hal_rtc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_rtc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_rtc.lst b/build/stm32l0xx_hal_rtc.lst new file mode 100644 index 0000000..0a39d69 --- /dev/null +++ b/build/stm32l0xx_hal_rtc.lst @@ -0,0 +1,5279 @@ +ARM GAS /tmp/ccjtTCRz.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_rtc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_RTC_MspInit,"ax",%progbits + 16 .align 1 + 17 .weak HAL_RTC_MspInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_RTC_MspInit: + 24 .LFB41: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @file stm32l0xx_hal_rtc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief RTC HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * functionalities of the Real Time Clock (RTC) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + Initialization/de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + I/O operation functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + Peripheral Control functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + Peripheral State functions + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Backup Domain Operating Condition ##### + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ============================================================================== + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] As long as the supply voltage remains in the operating range, + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** the RTC never stops, regardless of the device status (Run mode, + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** low power modes or under reset). + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Backup Domain Reset ##### + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ================================================================== + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] The backup domain reset sets all RTC registers and the RCC_CSR register + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** to their reset values. + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] A backup domain reset is generated when one of the following events occurs: + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Software reset, triggered by setting the RTCRST bit in the + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RCC Control Status register (RCC_CSR). + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Power reset (BOR/POR/PDR). + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Backup Domain Access ##### + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ================================================================== + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] After reset, the backup domain (RTC registers and RTC backup data registers) + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** is protected against possible unwanted write accesses. + ARM GAS /tmp/ccjtTCRz.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RCC_PWR_CLK_ENABLE() function. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### How to use RTC Driver ##### + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =================================================================== + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Enable the RTC domain access (see description in the section above). + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** format using the HAL_RTC_Init() function. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** *** Time and Date configuration *** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =================================== + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** and HAL_RTC_SetDate() functions. + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** *** Alarm configuration *** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =========================== + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** You can also configure the RTC Alarm with interrupt mode using the + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTC_SetAlarm_IT() function. + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### RTC and low power modes ##### + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ================================================================== + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] The MCU can be woken up from a low power mode by an RTC alternate + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** function. + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** These RTC alternate functions can wake up the system from the Stop and + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Standby low power modes. + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] The system can also wake up from low power modes without depending + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** on an external interrupt (Auto-wakeup mode), by using the RTC alarm + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** or the RTC wakeup events. + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] The RTC provides a programmable time base for waking up from the + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Stop or Standby mode at regular intervals. + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** is LSE or LSI. + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ****************************************************************************** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @attention + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * Redistribution and use in source and binary forms, with or without modification, + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * are permitted provided that the following conditions are met: + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * this list of conditions and the following disclaimer. + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + ARM GAS /tmp/ccjtTCRz.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * this list of conditions and the following disclaimer in the documentation + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * and/or other materials provided with the distribution. + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * may be used to endorse or promote products derived from this software + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * without specific prior written permission. + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ****************************************************************************** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Includes ------------------------------------------------------------------*/ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** #include "stm32l0xx_hal.h" + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup STM32L0xx_HAL_Driver + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief RTC HAL module driver + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** #ifdef HAL_RTC_MODULE_ENABLED + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Private typedef -----------------------------------------------------------*/ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Private define ------------------------------------------------------------*/ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Private macro -------------------------------------------------------------*/ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Private variables ---------------------------------------------------------*/ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Private function prototypes -----------------------------------------------*/ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Exported functions --------------------------------------------------------*/ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions_Group1 + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Initialization and Configuration functions + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Initialization and de-initialization functions ##### + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] This section provides functions allowing to initialize and configure the + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RTC registers Write protection, enter and exit the RTC initialization mode, + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RTC registers synchronization check and reference clock detection enable. + ARM GAS /tmp/ccjtTCRz.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** It is split into 2 programmable prescalers to minimize power consumption. + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (++) When both prescalers are used, it is recommended to configure the + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** asynchronous prescaler to a high value to minimize power consumption. + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (#) All RTC registers are Write protected. Writing to the RTC registers + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** is enabled by writing a key into the Write Protection register, RTC_WPR. + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (#) To configure the RTC Calendar, user application should enter + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** initialization mode. In this mode, the calendar counter is stopped + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** and its value can be updated. When the initialization sequence is + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** complete, the calendar restarts counting after 4 RTCCLK cycles. + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (#) To read the calendar through the shadow registers after Calendar + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** initialization, calendar update or after wakeup from low power modes + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** the software must first clear the RSF flag. The software must then + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** wait until it is set again before reading the calendar, which means + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** that the calendar registers have been correctly copied into the + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** implements the above software sequence (RSF clear and RSF check). + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Initialize the RTC peripheral + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the RTC peripheral state */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(hrtc == NULL) + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(hrtc->State == HAL_RTC_STATE_RESET) + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Allocate lock resource and initialize it */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Lock = HAL_UNLOCKED; + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Initialize RTC MSP */ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTC_MspInit(hrtc); + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + ARM GAS /tmp/ccjtTCRz.s page 5 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set Initialization mode */ + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear RTC_CR FMT, OSEL and POL Bits */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC_CR register */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutP + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the RTC PRER */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Exit Initialization mode */ + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief DeInitialize the RTC peripheral. + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note This function doesn't reset the RTC Backup Data registers. + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + ARM GAS /tmp/ccjtTCRz.s page 6 + + + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set Initialization mode */ + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset TR, DR and CR registers */ + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->TR = (uint32_t)0x00000000U; + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset All CR bits except CR[2:0] */ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR &= RTC_CR_WUCKSEL; + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till WUTWF flag is set and if Time out is reached exit */ + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset all RTC CR register bits */ + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR &= (uint32_t)0x00000000U; + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->WUTR = RTC_WUTR_WUT; + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMAR = (uint32_t)0x00000000U; + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBR = (uint32_t)0x00000000U; + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->SHIFTR = (uint32_t)0x00000000U; + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CALR = (uint32_t)0x00000000U; + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U; + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset ISR register and exit initialization mode */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR = (uint32_t)0x00000000U; + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset Tamper configuration register */ + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->TAMPCR = 0x00000000U; + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 7 + + + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset Option register */ + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->OR = 0x00000000U; + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* De-Initialize RTC MSP */ + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTC_MspDeInit(hrtc); + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_RESET; + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Release Lock */ + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Initialize the RTC MSP. + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval None + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 26 .loc 1 357 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Prevent unused argument(s) compilation warning */ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** UNUSED(hrtc); + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* NOTE : This function should not be modified, when the callback is needed, + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** the HAL_RTC_MspInit could be implemented in the user file + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 32 .loc 1 364 0 + 33 @ sp needed + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE41: + ARM GAS /tmp/ccjtTCRz.s page 8 + + + 38 .section .text.HAL_RTC_MspDeInit,"ax",%progbits + 39 .align 1 + 40 .weak HAL_RTC_MspDeInit + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 HAL_RTC_MspDeInit: + 47 .LFB42: + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief DeInitialize the RTC MSP. + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval None + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 48 .loc 1 372 0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 53 .LVL1: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Prevent unused argument(s) compilation warning */ + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** UNUSED(hrtc); + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* NOTE : This function should not be modified, when the callback is needed, + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** the HAL_RTC_MspDeInit could be implemented in the user file + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 54 .loc 1 379 0 + 55 @ sp needed + 56 0000 7047 bx lr + 57 .cfi_endproc + 58 .LFE42: + 60 .section .text.HAL_RTC_GetTime,"ax",%progbits + 61 .align 1 + 62 .global HAL_RTC_GetTime + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 HAL_RTC_GetTime: + 69 .LFB44: + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions_Group2 + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief RTC Time and Date functions + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### RTC Time and Date functions ##### + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 9 + + + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] This section provides functions allowing to configure Time and Date features + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Set RTC current time. + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sTime: Pointer to Time structure + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U; + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Locked */ + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_LOCK(hrtc); + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(sTime->Hours)); + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->TimeFormat = 0x00U; + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sTime->Hours)); + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(sTime->Minutes)); + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(sTime->Seconds)); + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sTime->TimeFormat) << 16U)); + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sTime->Hours); + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(tmpreg)); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + ARM GAS /tmp/ccjtTCRz.s page 10 + + + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->TimeFormat = 0x00U; + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->Minutes) << 8U) | \ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sTime->Seconds) | \ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->TimeFormat) << 16U)); + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** UNUSED(tmpreg); + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set Initialization mode */ + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state */ + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set the RTC_TR register */ + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear the bits to be configured */ + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the RTC_CR register */ + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Exit Initialization mode */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + ARM GAS /tmp/ccjtTCRz.s page 11 + + + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Get RTC current time. + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * with input format (BIN or BCD), also SubSeconds field returning the + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * factor to be used for second fraction ratio computation. + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert S + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * value in second fraction ratio with time unit following generic formula: + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * ti + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * in the higher-order calendar shadow registers to ensure consistency between the time and + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * Reading RTC current time locks the values in calendar shadow registers until Current dat + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * to ensure consistency between the time and date values. + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 70 .loc 1 545 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .LVL2: + 75 0000 70B5 push {r4, r5, r6, lr} + 76 .LCFI0: + 77 .cfi_def_cfa_offset 16 + 78 .cfi_offset 4, -16 + 79 .cfi_offset 5, -12 + 80 .cfi_offset 6, -8 + 81 .cfi_offset 14, -4 + 82 .LVL3: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U; + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 12 + + + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get subseconds structure field from the corresponding register*/ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + 83 .loc 1 552 0 + 84 0002 0368 ldr r3, [r0] + 85 0004 9B6A ldr r3, [r3, #40] + 86 0006 4B60 str r3, [r1, #4] + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get SecondFraction structure field from the corresponding register field*/ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + 87 .loc 1 555 0 + 88 0008 0368 ldr r3, [r0] + 89 000a 1B69 ldr r3, [r3, #16] + 90 000c 5B04 lsls r3, r3, #17 + 91 000e 5B0C lsrs r3, r3, #17 + 92 0010 8B60 str r3, [r1, #8] + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the TR register */ + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + 93 .loc 1 558 0 + 94 0012 0368 ldr r3, [r0] + 95 0014 1C68 ldr r4, [r3] + 96 0016 144B ldr r3, .L5 + 97 0018 1C40 ands r4, r3 + 98 .LVL4: + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Fill the structure fields with the read parameters */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + 99 .loc 1 561 0 + 100 001a 260C lsrs r6, r4, #16 + 101 001c 3F20 movs r0, #63 + 102 .LVL5: + 103 001e 3040 ands r0, r6 + 104 0020 0870 strb r0, [r1] + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); + 105 .loc 1 562 0 + 106 0022 230A lsrs r3, r4, #8 + 107 0024 7F25 movs r5, #127 + 108 0026 2B40 ands r3, r5 + 109 0028 4B70 strb r3, [r1, #1] + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + 110 .loc 1 563 0 + 111 002a 2C40 ands r4, r5 + 112 .LVL6: + 113 002c 8C70 strb r4, [r1, #2] + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); + 114 .loc 1 564 0 + 115 002e 3F3D subs r5, r5, #63 + 116 0030 3540 ands r5, r6 + 117 0032 CD70 strb r5, [r1, #3] + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the input parameters format */ + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 118 .loc 1 567 0 + 119 0034 002A cmp r2, #0 + 120 0036 15D1 bne .L4 + 121 .LVL7: + 122 .LBB68: + ARM GAS /tmp/ccjtTCRz.s page 13 + + + 123 .LBB69: + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Convert the time structure parameters to Binary format */ + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Set RTC current date. + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sDate: Pointer to date structure + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: specifies the format of the entered parameters. + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t datetmpreg = 0U; + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Locked */ + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_LOCK(hrtc); + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_YEAR(sDate->Year)); + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MONTH(sDate->Month)); + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_DATE(sDate->Date)); + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sDate->WeekDay << 13U)); + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** datetmpreg = RTC_Bcd2ToByte(sDate->Month); + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MONTH(datetmpreg)); + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** datetmpreg = RTC_Bcd2ToByte(sDate->Date); + ARM GAS /tmp/ccjtTCRz.s page 14 + + + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_DATE(datetmpreg)); + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sDate->Month) << 8U) | \ + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sDate->Date) | \ + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sDate->WeekDay) << 13U)); + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set Initialization mode */ + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC state*/ + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set the RTC_DR register */ + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Exit Initialization mode */ + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_ERROR; + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY ; + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + ARM GAS /tmp/ccjtTCRz.s page 15 + + + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Get RTC current date. + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sDate: Pointer to Date structure + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * in the higher-order calendar shadow registers to ensure consistency between the time and + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * Reading RTC current time locks the values in calendar shadow registers until Current dat + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t datetmpreg = 0U; + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the DR register */ + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Fill the structure fields with the read parameters */ + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the input parameters format */ + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Convert the date structure parameters to Binary format */ + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions_Group3 + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief RTC Alarm functions + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### RTC Alarm functions ##### + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 16 + + + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] This section provides functions allowing to configure Alarm feature + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Set the specified RTC Alarm. + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sAlarm: Pointer to Alarm structure + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Form + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Locked */ + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_LOCK(hrtc); + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = 0x00U; + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 17 + + + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmMask)); + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(tmpreg)); + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = 0x00U; + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmMask)); + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A or Alarm B Sub Second registers */ + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmS + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm register */ + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->Alarm == RTC_ALARM_A) + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the Alarm A interrupt */ + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMA_DISABLE(hrtc); + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 18 + + + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A Sub Second register */ + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMASSR = subsecondtmpreg; + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMA_ENABLE(hrtc); + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the Alarm B interrupt */ + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMB_DISABLE(hrtc); + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBR = (uint32_t)tmpreg; + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm B Sub Second register */ + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBSSR = subsecondtmpreg; + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + ARM GAS /tmp/ccjtTCRz.s page 19 + + + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMB_ENABLE(hrtc); + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Change RTC state */ + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Set the specified RTC Alarm with Interrupt. + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sAlarm: Pointer to Alarm structure + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note The Alarm register can only be written when the corresponding Alarm + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * is disabled (Use the HAL_RTC_DeactivateAlarm()). + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t F + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Locked */ + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_LOCK(hrtc); + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = 0x00U; + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + ARM GAS /tmp/ccjtTCRz.s page 20 + + + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmMask)); + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR12(tmpreg)); + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = 0x00U; + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmMask)); +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A or Alarm B Sub Second registers */ +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmS + ARM GAS /tmp/ccjtTCRz.s page 21 + + +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm register */ +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(sAlarm->Alarm == RTC_ALARM_A) +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the Alarm A interrupt */ +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMA_DISABLE(hrtc); +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear flag alarm A */ +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMAR = (uint32_t)tmpreg; +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A Sub Second register */ +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMASSR = subsecondtmpreg; +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMA_ENABLE(hrtc); +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm interrupt */ +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the Alarm B interrupt */ +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMB_DISABLE(hrtc); +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear flag alarm B */ +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + ARM GAS /tmp/ccjtTCRz.s page 22 + + +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBR = (uint32_t)tmpreg; +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm B Sub Second register */ +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBSSR = subsecondtmpreg; +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMB_ENABLE(hrtc); +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm interrupt */ +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* RTC Alarm Interrupt Configuration: EXTI configuration */ +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_EXTI_ENABLE_IT(); +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Deactivate the specified RTC Alarm. +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Alarm: Specifies the Alarm. +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_ALARM_A: AlarmA +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_ALARM_B: AlarmB +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM(Alarm)); +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Locked */ +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_LOCK(hrtc); +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_BUSY; +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Disable the write protection for RTC registers */ +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 23 + + +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Alarm == RTC_ALARM_A) +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* AlarmA */ +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMA_DISABLE(hrtc); +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* AlarmB */ +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARMB_DISABLE(hrtc); +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Enable the write protection for RTC registers */ +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 24 + + +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Process Unlocked */ +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_UNLOCK(hrtc); +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Get the RTC Alarm value and masks. +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param sAlarm: Pointer to Date structure +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Alarm: Specifies the Alarm. +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_ALARM_A: AlarmA +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_ALARM_B: AlarmB +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Format: Specifies the format of the entered parameters. +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * This parameter can be one of the following values: +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BIN: Binary data format +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @arg RTC_FORMAT_BCD: BCD data format +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alar +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U, subsecondtmpreg = 0U; +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the parameters */ +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_FORMAT(Format)); +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_ALARM(Alarm)); +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Alarm == RTC_ALARM_A) +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* AlarmA */ +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->Alarm = RTC_ALARM_A; +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Fill the structure with the read parameters */ +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** else +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->Alarm = RTC_ALARM_B; +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Fill the structure with the read parameters */ +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U); + ARM GAS /tmp/ccjtTCRz.s page 25 + + +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U); +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16U); +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U); +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Format == RTC_FORMAT_BIN) +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Handle Alarm interrupt request. +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval None +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the AlarmA interrupt source enable status */ +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the pending status of the AlarmA Interrupt */ +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET) +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* AlarmA callback */ +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTC_AlarmAEventCallback(hrtc); +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear the AlarmA interrupt pending bit */ +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the AlarmB interrupt source enable status */ +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the pending status of the AlarmB Interrupt */ +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET) +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* AlarmB callback */ +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTCEx_AlarmBEventCallback(hrtc); +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear the AlarmB interrupt pending bit */ +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear the EXTI's line Flag for RTC Alarm */ +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + ARM GAS /tmp/ccjtTCRz.s page 26 + + +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Change RTC state */ +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Alarm A callback. +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval None +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Prevent unused argument(s) compilation warning */ +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** UNUSED(hrtc); +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* NOTE : This function should not be modified, when the callback is needed, +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** the HAL_RTC_AlarmAEventCallback could be implemented in the user file +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Handle AlarmA Polling request. +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Timeout: Timeout duration +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = HAL_GetTick(); +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if(Timeout != HAL_MAX_DELAY) +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear the Alarm interrupt pending bit */ +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Change RTC state */ +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->State = HAL_RTC_STATE_READY; +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions_Group4 + ARM GAS /tmp/ccjtTCRz.s page 27 + + +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Peripheral Control functions +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Peripheral Control functions ##### +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** This subsection provides functions allowing to +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Wait for RTC Time and Date Synchronization +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * synchronized with RTC APB clock. +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note The RTC Resynchronization mode is write protected, use the +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note To read the calendar through the shadow registers after Calendar +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * initialization, calendar update or after wakeup from low power modes +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * the software must first clear the RSF flag. +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * The software must then wait until it is set again before reading +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * the calendar, which means that the calendar registers have been +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * correctly copied into the RTC_TR and RTC_DR shadow registers. +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Clear RSF flag */ +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait the registers to be synchronised */ +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Exported_Functions_Group5 +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Peripheral State functions +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @verbatim + ARM GAS /tmp/ccjtTCRz.s page 28 + + +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ##### Peripheral State functions ##### +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** =============================================================================== +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** [..] +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** This subsection provides functions allowing to +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (+) Get RTC state +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** @endverbatim +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Return the RTC handle state. +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL state +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Return RTC handle state */ +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return hrtc->State; +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @} +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** @addtogroup RTC_Private_Functions +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @{ +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Enter the RTC Initialization mode. +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @note The RTC Initialization mode is write protected, use the +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param hrtc: RTC handle +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval HAL status +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check if the Initialization mode is set */ +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set the Initialization mode */ +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tickstart = HAL_GetTick(); +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC is in INIT state and if Time out is reached exit */ +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + ARM GAS /tmp/ccjtTCRz.s page 29 + + +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_OK; +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Convert a 2 digit decimal to BCD format. +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Value: Byte to be converted +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval Converted byte +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint8_t RTC_ByteToBcd2(uint8_t Value) +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t bcdhigh = 0U; +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** while(Value >= 10U) +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** bcdhigh++; +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return ((uint8_t)(bcdhigh << 4U) | Value); +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /** +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @brief Convert from 2 digit BCD to Binary. +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @param Value: BCD value to be converted +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** * @retval Converted word +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** */ +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint8_t RTC_Bcd2ToByte(uint8_t Value) +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmp = 0U; +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U; + 124 .loc 1 1511 0 + 125 0038 0509 lsrs r5, r0, #4 + 126 003a AA00 lsls r2, r5, #2 + 127 .LVL8: + 128 003c 5219 adds r2, r2, r5 + 129 003e 5500 lsls r5, r2, #1 + 130 .LVL9: +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 131 .loc 1 1512 0 + 132 0040 0F22 movs r2, #15 + 133 0042 1040 ands r0, r2 + 134 .LVL10: + 135 0044 4019 adds r0, r0, r5 + 136 .LVL11: + 137 .LBE69: + 138 .LBE68: + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + 139 .loc 1 570 0 + 140 0046 0870 strb r0, [r1] + 141 .LVL12: + 142 .LBB70: + 143 .LBB71: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 144 .loc 1 1511 0 + ARM GAS /tmp/ccjtTCRz.s page 30 + + + 145 0048 1D09 lsrs r5, r3, #4 + 146 004a A800 lsls r0, r5, #2 + 147 004c 4019 adds r0, r0, r5 + 148 004e 4500 lsls r5, r0, #1 + 149 .LVL13: + 150 .loc 1 1512 0 + 151 0050 1340 ands r3, r2 + 152 .LVL14: + 153 0052 5B19 adds r3, r3, r5 + 154 .LVL15: + 155 .LBE71: + 156 .LBE70: + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + 157 .loc 1 571 0 + 158 0054 4B70 strb r3, [r1, #1] + 159 .LVL16: + 160 .LBB72: + 161 .LBB73: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 162 .loc 1 1511 0 + 163 0056 2009 lsrs r0, r4, #4 + 164 0058 8300 lsls r3, r0, #2 + 165 005a 1B18 adds r3, r3, r0 + 166 005c 5800 lsls r0, r3, #1 + 167 .LVL17: + 168 .loc 1 1512 0 + 169 005e 1440 ands r4, r2 + 170 .LVL18: + 171 0060 2418 adds r4, r4, r0 + 172 .LVL19: + 173 .LBE73: + 174 .LBE72: + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 175 .loc 1 572 0 + 176 0062 8C70 strb r4, [r1, #2] + 177 .L4: + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 178 .loc 1 576 0 + 179 0064 0020 movs r0, #0 + 180 @ sp needed + 181 0066 70BD pop {r4, r5, r6, pc} + 182 .L6: + 183 .align 2 + 184 .L5: + 185 0068 7F7F7F00 .word 8355711 + 186 .cfi_endproc + 187 .LFE44: + 189 .section .text.HAL_RTC_GetDate,"ax",%progbits + 190 .align 1 + 191 .global HAL_RTC_GetDate + 192 .syntax unified + 193 .code 16 + 194 .thumb_func + 195 .fpu softvfp + 197 HAL_RTC_GetDate: + 198 .LFB46: + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t datetmpreg = 0U; + ARM GAS /tmp/ccjtTCRz.s page 31 + + + 199 .loc 1 700 0 + 200 .cfi_startproc + 201 @ args = 0, pretend = 0, frame = 0 + 202 @ frame_needed = 0, uses_anonymous_args = 0 + 203 .LVL20: + 204 0000 70B5 push {r4, r5, r6, lr} + 205 .LCFI1: + 206 .cfi_def_cfa_offset 16 + 207 .cfi_offset 4, -16 + 208 .cfi_offset 5, -12 + 209 .cfi_offset 6, -8 + 210 .cfi_offset 14, -4 + 211 .LVL21: + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 212 .loc 1 707 0 + 213 0002 0368 ldr r3, [r0] + 214 0004 5B68 ldr r3, [r3, #4] + 215 0006 1448 ldr r0, .L9 + 216 .LVL22: + 217 0008 0340 ands r3, r0 + 218 .LVL23: + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); + 219 .loc 1 710 0 + 220 000a 1C0C lsrs r4, r3, #16 + 221 000c CC70 strb r4, [r1, #3] + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + 222 .loc 1 711 0 + 223 000e 180A lsrs r0, r3, #8 + 224 0010 1F25 movs r5, #31 + 225 0012 2840 ands r0, r5 + 226 0014 4870 strb r0, [r1, #1] + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); + 227 .loc 1 712 0 + 228 0016 2035 adds r5, r5, #32 + 229 0018 1D40 ands r5, r3 + 230 001a 8D70 strb r5, [r1, #2] + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 231 .loc 1 713 0 + 232 001c 5B0B lsrs r3, r3, #13 + 233 .LVL24: + 234 001e 0726 movs r6, #7 + 235 0020 3340 ands r3, r6 + 236 0022 0B70 strb r3, [r1] + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 237 .loc 1 716 0 + 238 0024 002A cmp r2, #0 + 239 0026 15D1 bne .L8 + 240 .LVL25: + 241 .LBB74: + 242 .LBB75: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 243 .loc 1 1511 0 + 244 0028 2209 lsrs r2, r4, #4 + 245 .LVL26: + 246 002a 9300 lsls r3, r2, #2 + 247 002c 9B18 adds r3, r3, r2 + 248 002e 5A00 lsls r2, r3, #1 + ARM GAS /tmp/ccjtTCRz.s page 32 + + + 249 .LVL27: + 250 .loc 1 1512 0 + 251 0030 0F23 movs r3, #15 + 252 0032 1C40 ands r4, r3 + 253 .LVL28: + 254 0034 A418 adds r4, r4, r2 + 255 .LVL29: + 256 .LBE75: + 257 .LBE74: + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + 258 .loc 1 719 0 + 259 0036 CC70 strb r4, [r1, #3] + 260 .LVL30: + 261 .LBB76: + 262 .LBB77: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 263 .loc 1 1511 0 + 264 0038 0409 lsrs r4, r0, #4 + 265 003a A200 lsls r2, r4, #2 + 266 003c 1219 adds r2, r2, r4 + 267 003e 5400 lsls r4, r2, #1 + 268 .LVL31: + 269 .loc 1 1512 0 + 270 0040 1840 ands r0, r3 + 271 .LVL32: + 272 0042 0019 adds r0, r0, r4 + 273 .LVL33: + 274 .LBE77: + 275 .LBE76: + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + 276 .loc 1 720 0 + 277 0044 4870 strb r0, [r1, #1] + 278 .LVL34: + 279 .LBB78: + 280 .LBB79: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 281 .loc 1 1511 0 + 282 0046 2809 lsrs r0, r5, #4 + 283 0048 8200 lsls r2, r0, #2 + 284 004a 1218 adds r2, r2, r0 + 285 004c 5000 lsls r0, r2, #1 + 286 .LVL35: + 287 .loc 1 1512 0 + 288 004e 1D40 ands r5, r3 + 289 .LVL36: + 290 0050 2D18 adds r5, r5, r0 + 291 .LVL37: + 292 .LBE79: + 293 .LBE78: + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 294 .loc 1 721 0 + 295 0052 8D70 strb r5, [r1, #2] + 296 .L8: + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 297 .loc 1 724 0 + 298 0054 0020 movs r0, #0 + 299 @ sp needed + ARM GAS /tmp/ccjtTCRz.s page 33 + + + 300 0056 70BD pop {r4, r5, r6, pc} + 301 .L10: + 302 .align 2 + 303 .L9: + 304 0058 3FFFFF00 .word 16777023 + 305 .cfi_endproc + 306 .LFE46: + 308 .section .text.HAL_RTC_SetAlarm,"ax",%progbits + 309 .align 1 + 310 .global HAL_RTC_SetAlarm + 311 .syntax unified + 312 .code 16 + 313 .thumb_func + 314 .fpu softvfp + 316 HAL_RTC_SetAlarm: + 317 .LFB47: + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 318 .loc 1 754 0 + 319 .cfi_startproc + 320 @ args = 0, pretend = 0, frame = 0 + 321 @ frame_needed = 0, uses_anonymous_args = 0 + 322 .LVL38: + 323 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 324 .LCFI2: + 325 .cfi_def_cfa_offset 24 + 326 .cfi_offset 3, -24 + 327 .cfi_offset 4, -20 + 328 .cfi_offset 5, -16 + 329 .cfi_offset 6, -12 + 330 .cfi_offset 7, -8 + 331 .cfi_offset 14, -4 + 332 0002 0400 movs r4, r0 + 333 .LVL39: + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 334 .loc 1 767 0 + 335 0004 2023 movs r3, #32 + 336 0006 C35C ldrb r3, [r0, r3] + 337 0008 012B cmp r3, #1 + 338 000a 00D1 bne .LCB298 + 339 000c D1E0 b .L31 @long jump + 340 .LCB298: + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 341 .loc 1 767 0 is_stmt 0 discriminator 2 + 342 000e 2023 movs r3, #32 + 343 0010 0120 movs r0, #1 + 344 .LVL40: + 345 0012 E054 strb r0, [r4, r3] + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 346 .loc 1 769 0 is_stmt 1 discriminator 2 + 347 0014 0133 adds r3, r3, #1 + 348 0016 0130 adds r0, r0, #1 + 349 0018 E054 strb r0, [r4, r3] + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 350 .loc 1 771 0 discriminator 2 + 351 001a 002A cmp r2, #0 + 352 001c 6FD1 bne .L13 + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + ARM GAS /tmp/ccjtTCRz.s page 34 + + + 353 .loc 1 773 0 + 354 001e 2368 ldr r3, [r4] + 355 0020 9B68 ldr r3, [r3, #8] + 356 0022 5B06 lsls r3, r3, #25 + 357 0024 01D4 bmi .L14 + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + 358 .loc 1 780 0 + 359 0026 0023 movs r3, #0 + 360 0028 CB70 strb r3, [r1, #3] + 361 .L14: + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 362 .loc 1 786 0 + 363 002a CE69 ldr r6, [r1, #28] + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 364 .loc 1 795 0 + 365 002c 0B78 ldrb r3, [r1] + 366 .LVL41: + 367 .LBB80: + 368 .LBB81: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 369 .loc 1 1492 0 + 370 002e 1000 movs r0, r2 + 371 0030 02E0 b .L15 + 372 .LVL42: + 373 .L16: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 374 .loc 1 1496 0 + 375 0032 0130 adds r0, r0, #1 + 376 .LVL43: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 377 .loc 1 1497 0 + 378 0034 0A3B subs r3, r3, #10 + 379 .LVL44: + 380 0036 DBB2 uxtb r3, r3 + 381 .LVL45: + 382 .L15: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 383 .loc 1 1494 0 + 384 0038 092B cmp r3, #9 + 385 003a FAD8 bhi .L16 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 386 .loc 1 1500 0 + 387 003c 0001 lsls r0, r0, #4 + 388 .LVL46: + 389 003e C0B2 uxtb r0, r0 + 390 0040 1843 orrs r0, r3 + 391 .LVL47: + 392 .LBE81: + 393 .LBE80: + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 394 .loc 1 795 0 + 395 0042 0004 lsls r0, r0, #16 + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 396 .loc 1 796 0 + 397 0044 4B78 ldrb r3, [r1, #1] + 398 .LVL48: + 399 .LBB82: + ARM GAS /tmp/ccjtTCRz.s page 35 + + + 400 .LBB83: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 401 .loc 1 1492 0 + 402 0046 1500 movs r5, r2 + 403 0048 02E0 b .L17 + 404 .LVL49: + 405 .L18: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 406 .loc 1 1496 0 + 407 004a 0135 adds r5, r5, #1 + 408 .LVL50: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 409 .loc 1 1497 0 + 410 004c 0A3B subs r3, r3, #10 + 411 .LVL51: + 412 004e DBB2 uxtb r3, r3 + 413 .LVL52: + 414 .L17: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 415 .loc 1 1494 0 + 416 0050 092B cmp r3, #9 + 417 0052 FAD8 bhi .L18 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 418 .loc 1 1500 0 + 419 0054 2D01 lsls r5, r5, #4 + 420 .LVL53: + 421 0056 EDB2 uxtb r5, r5 + 422 0058 2B43 orrs r3, r5 + 423 .LVL54: + 424 .LBE83: + 425 .LBE82: + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 426 .loc 1 796 0 + 427 005a 1B02 lsls r3, r3, #8 + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 428 .loc 1 795 0 + 429 005c 0343 orrs r3, r0 + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 430 .loc 1 797 0 + 431 005e 8878 ldrb r0, [r1, #2] + 432 .LVL55: + 433 .LBB84: + 434 .LBB85: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 435 .loc 1 1492 0 + 436 0060 1500 movs r5, r2 + 437 0062 02E0 b .L19 + 438 .LVL56: + 439 .L20: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 440 .loc 1 1496 0 + 441 0064 0135 adds r5, r5, #1 + 442 .LVL57: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 443 .loc 1 1497 0 + 444 0066 0A38 subs r0, r0, #10 + 445 .LVL58: + ARM GAS /tmp/ccjtTCRz.s page 36 + + + 446 0068 C0B2 uxtb r0, r0 + 447 .LVL59: + 448 .L19: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 449 .loc 1 1494 0 + 450 006a 0928 cmp r0, #9 + 451 006c FAD8 bhi .L20 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 452 .loc 1 1500 0 + 453 006e 2D01 lsls r5, r5, #4 + 454 .LVL60: + 455 0070 EDB2 uxtb r5, r5 + 456 0072 2843 orrs r0, r5 + 457 .LVL61: + 458 .LBE85: + 459 .LBE84: + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 460 .loc 1 796 0 + 461 0074 1843 orrs r0, r3 + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 462 .loc 1 798 0 + 463 0076 CB78 ldrb r3, [r1, #3] + 464 0078 1B04 lsls r3, r3, #16 + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 465 .loc 1 797 0 + 466 007a 1843 orrs r0, r3 + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 467 .loc 1 799 0 + 468 007c 2023 movs r3, #32 + 469 007e CD5C ldrb r5, [r1, r3] + 470 .LVL62: + 471 0080 02E0 b .L21 + 472 .LVL63: + 473 .L22: + 474 .LBB86: + 475 .LBB87: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 476 .loc 1 1496 0 + 477 0082 0132 adds r2, r2, #1 + 478 .LVL64: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 479 .loc 1 1497 0 + 480 0084 0A3D subs r5, r5, #10 + 481 .LVL65: + 482 0086 EDB2 uxtb r5, r5 + 483 .LVL66: + 484 .L21: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 485 .loc 1 1494 0 + 486 0088 092D cmp r5, #9 + 487 008a FAD8 bhi .L22 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 488 .loc 1 1500 0 + 489 008c 1201 lsls r2, r2, #4 + 490 .LVL67: + 491 008e D3B2 uxtb r3, r2 + 492 0090 2B43 orrs r3, r5 + ARM GAS /tmp/ccjtTCRz.s page 37 + + + 493 .LVL68: + 494 .LBE87: + 495 .LBE86: + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 496 .loc 1 799 0 + 497 0092 1B06 lsls r3, r3, #24 + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 498 .loc 1 798 0 + 499 0094 0343 orrs r3, r0 + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 500 .loc 1 799 0 + 501 0096 1E43 orrs r6, r3 + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 502 .loc 1 795 0 + 503 0098 4B69 ldr r3, [r1, #20] + 504 009a 1E43 orrs r6, r3 + 505 .LVL69: + 506 .L23: + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 507 .loc 1 841 0 + 508 009c 4D68 ldr r5, [r1, #4] + 509 009e 8B69 ldr r3, [r1, #24] + 510 00a0 1D43 orrs r5, r3 + 511 .LVL70: + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 512 .loc 1 844 0 + 513 00a2 2368 ldr r3, [r4] + 514 00a4 CA22 movs r2, #202 + 515 00a6 5A62 str r2, [r3, #36] + 516 00a8 2368 ldr r3, [r4] + 517 00aa 773A subs r2, r2, #119 + 518 00ac 5A62 str r2, [r3, #36] + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 519 .loc 1 847 0 + 520 00ae 4A6A ldr r2, [r1, #36] + 521 00b0 8023 movs r3, #128 + 522 00b2 5B00 lsls r3, r3, #1 + 523 00b4 9A42 cmp r2, r3 + 524 00b6 3BD0 beq .L32 + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 525 .loc 1 882 0 + 526 00b8 2268 ldr r2, [r4] + 527 00ba 9368 ldr r3, [r2, #8] + 528 00bc 3E49 ldr r1, .L35 + 529 .LVL71: + 530 00be 0B40 ands r3, r1 + 531 00c0 9360 str r3, [r2, #8] + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 532 .loc 1 885 0 + 533 00c2 2268 ldr r2, [r4] + 534 00c4 9368 ldr r3, [r2, #8] + 535 00c6 3D49 ldr r1, .L35+4 + 536 00c8 0B40 ands r3, r1 + 537 00ca 9360 str r3, [r2, #8] + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + 538 .loc 1 887 0 + 539 00cc FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccjtTCRz.s page 38 + + + 540 .LVL72: + 541 00d0 0700 movs r7, r0 + 542 .LVL73: + 543 .L29: + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 544 .loc 1 889 0 + 545 00d2 2268 ldr r2, [r4] + 546 00d4 D168 ldr r1, [r2, #12] + 547 00d6 8B07 lsls r3, r1, #30 + 548 00d8 57D4 bmi .L33 + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 549 .loc 1 891 0 + 550 00da FFF7FEFF bl HAL_GetTick + 551 .LVL74: + 552 00de C01B subs r0, r0, r7 + 553 00e0 FA23 movs r3, #250 + 554 00e2 9B00 lsls r3, r3, #2 + 555 00e4 9842 cmp r0, r3 + 556 00e6 F4D9 bls .L29 + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 557 .loc 1 894 0 + 558 00e8 2368 ldr r3, [r4] + 559 00ea FF22 movs r2, #255 + 560 00ec 5A62 str r2, [r3, #36] + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 561 .loc 1 896 0 + 562 00ee 2123 movs r3, #33 + 563 00f0 FC3A subs r2, r2, #252 + 564 00f2 E254 strb r2, [r4, r3] + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 565 .loc 1 899 0 + 566 00f4 013B subs r3, r3, #1 + 567 00f6 0022 movs r2, #0 + 568 00f8 E254 strb r2, [r4, r3] + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 569 .loc 1 901 0 + 570 00fa 0320 movs r0, #3 + 571 00fc 58E0 b .L12 + 572 .LVL75: + 573 .L13: + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 574 .loc 1 805 0 + 575 00fe 2368 ldr r3, [r4] + 576 0100 9B68 ldr r3, [r3, #8] + 577 0102 5B06 lsls r3, r3, #25 + 578 0104 01D4 bmi .L24 + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + 579 .loc 1 813 0 + 580 0106 0023 movs r3, #0 + 581 0108 CB70 strb r3, [r1, #3] + 582 .L24: + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 583 .loc 1 831 0 + 584 010a 0E78 ldrb r6, [r1] + 585 010c 3604 lsls r6, r6, #16 + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 586 .loc 1 832 0 + ARM GAS /tmp/ccjtTCRz.s page 39 + + + 587 010e 4B78 ldrb r3, [r1, #1] + 588 0110 1B02 lsls r3, r3, #8 + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 589 .loc 1 831 0 + 590 0112 1E43 orrs r6, r3 + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 591 .loc 1 833 0 + 592 0114 8B78 ldrb r3, [r1, #2] + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 593 .loc 1 832 0 + 594 0116 1E43 orrs r6, r3 + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 595 .loc 1 834 0 + 596 0118 CB78 ldrb r3, [r1, #3] + 597 011a 1B04 lsls r3, r3, #16 + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 598 .loc 1 833 0 + 599 011c 1E43 orrs r6, r3 + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 600 .loc 1 835 0 + 601 011e 2023 movs r3, #32 + 602 0120 CB5C ldrb r3, [r1, r3] + 603 0122 1B06 lsls r3, r3, #24 + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 604 .loc 1 834 0 + 605 0124 1E43 orrs r6, r3 + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 606 .loc 1 835 0 + 607 0126 CB69 ldr r3, [r1, #28] + 608 0128 1E43 orrs r6, r3 + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 609 .loc 1 831 0 + 610 012a 4B69 ldr r3, [r1, #20] + 611 012c 1E43 orrs r6, r3 + 612 .LVL76: + 613 012e B5E7 b .L23 + 614 .LVL77: + 615 .L32: + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 616 .loc 1 850 0 + 617 0130 2268 ldr r2, [r4] + 618 0132 9368 ldr r3, [r2, #8] + 619 0134 2249 ldr r1, .L35+8 + 620 .LVL78: + 621 0136 0B40 ands r3, r1 + 622 0138 9360 str r3, [r2, #8] + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 623 .loc 1 853 0 + 624 013a 2268 ldr r2, [r4] + 625 013c 9368 ldr r3, [r2, #8] + 626 013e 2149 ldr r1, .L35+12 + 627 0140 0B40 ands r3, r1 + 628 0142 9360 str r3, [r2, #8] + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + 629 .loc 1 855 0 + 630 0144 FFF7FEFF bl HAL_GetTick + 631 .LVL79: + ARM GAS /tmp/ccjtTCRz.s page 40 + + + 632 0148 0700 movs r7, r0 + 633 .LVL80: + 634 .L26: + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 635 .loc 1 857 0 + 636 014a 2368 ldr r3, [r4] + 637 014c DA68 ldr r2, [r3, #12] + 638 014e D207 lsls r2, r2, #31 + 639 0150 11D4 bmi .L34 + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 640 .loc 1 859 0 + 641 0152 FFF7FEFF bl HAL_GetTick + 642 .LVL81: + 643 0156 C01B subs r0, r0, r7 + 644 0158 FA23 movs r3, #250 + 645 015a 9B00 lsls r3, r3, #2 + 646 015c 9842 cmp r0, r3 + 647 015e F4D9 bls .L26 + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 648 .loc 1 862 0 + 649 0160 2368 ldr r3, [r4] + 650 0162 FF22 movs r2, #255 + 651 0164 5A62 str r2, [r3, #36] + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 652 .loc 1 864 0 + 653 0166 2123 movs r3, #33 + 654 0168 FC3A subs r2, r2, #252 + 655 016a E254 strb r2, [r4, r3] + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 656 .loc 1 867 0 + 657 016c 013B subs r3, r3, #1 + 658 016e 0022 movs r2, #0 + 659 0170 E254 strb r2, [r4, r3] + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 660 .loc 1 869 0 + 661 0172 0320 movs r0, #3 + 662 0174 1CE0 b .L12 + 663 .L34: + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A Sub Second register */ + 664 .loc 1 873 0 + 665 0176 DE61 str r6, [r3, #28] + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + 666 .loc 1 875 0 + 667 0178 2368 ldr r3, [r4] + 668 017a 5D64 str r5, [r3, #68] + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 669 .loc 1 877 0 + 670 017c 2268 ldr r2, [r4] + 671 017e 9168 ldr r1, [r2, #8] + 672 0180 8023 movs r3, #128 + 673 0182 5B00 lsls r3, r3, #1 + 674 0184 0B43 orrs r3, r1 + 675 0186 9360 str r3, [r2, #8] + 676 0188 08E0 b .L28 + 677 .L33: + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm B Sub Second register */ + 678 .loc 1 905 0 + ARM GAS /tmp/ccjtTCRz.s page 41 + + + 679 018a 1662 str r6, [r2, #32] + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + 680 .loc 1 907 0 + 681 018c 2368 ldr r3, [r4] + 682 018e 9D64 str r5, [r3, #72] + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 683 .loc 1 909 0 + 684 0190 2268 ldr r2, [r4] + 685 0192 9168 ldr r1, [r2, #8] + 686 0194 8023 movs r3, #128 + 687 0196 9B00 lsls r3, r3, #2 + 688 0198 0B43 orrs r3, r1 + 689 019a 9360 str r3, [r2, #8] + 690 .L28: + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 691 .loc 1 913 0 + 692 019c 2368 ldr r3, [r4] + 693 019e FF22 movs r2, #255 + 694 01a0 5A62 str r2, [r3, #36] + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 695 .loc 1 916 0 + 696 01a2 2123 movs r3, #33 + 697 01a4 FE3A subs r2, r2, #254 + 698 01a6 E254 strb r2, [r4, r3] + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 699 .loc 1 919 0 + 700 01a8 013B subs r3, r3, #1 + 701 01aa 0022 movs r2, #0 + 702 01ac E254 strb r2, [r4, r3] + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 703 .loc 1 921 0 + 704 01ae 0020 movs r0, #0 + 705 .LVL82: + 706 .L12: + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 707 .loc 1 922 0 + 708 @ sp needed + 709 .LVL83: + 710 01b0 F8BD pop {r3, r4, r5, r6, r7, pc} + 711 .LVL84: + 712 .L31: + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 713 .loc 1 767 0 + 714 01b2 0220 movs r0, #2 + 715 .LVL85: + 716 01b4 FCE7 b .L12 + 717 .L36: + 718 01b6 C046 .align 2 + 719 .L35: + 720 01b8 FFFDFFFF .word -513 + 721 01bc FFDFFFFF .word -8193 + 722 01c0 FFFEFFFF .word -257 + 723 01c4 FFEFFFFF .word -4097 + 724 .cfi_endproc + 725 .LFE47: + 727 .section .text.HAL_RTC_SetAlarm_IT,"ax",%progbits + 728 .align 1 + ARM GAS /tmp/ccjtTCRz.s page 42 + + + 729 .global HAL_RTC_SetAlarm_IT + 730 .syntax unified + 731 .code 16 + 732 .thumb_func + 733 .fpu softvfp + 735 HAL_RTC_SetAlarm_IT: + 736 .LFB48: + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 737 .loc 1 938 0 + 738 .cfi_startproc + 739 @ args = 0, pretend = 0, frame = 0 + 740 @ frame_needed = 0, uses_anonymous_args = 0 + 741 .LVL86: + 742 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 743 .LCFI3: + 744 .cfi_def_cfa_offset 24 + 745 .cfi_offset 3, -24 + 746 .cfi_offset 4, -20 + 747 .cfi_offset 5, -16 + 748 .cfi_offset 6, -12 + 749 .cfi_offset 7, -8 + 750 .cfi_offset 14, -4 + 751 0002 0400 movs r4, r0 + 752 .LVL87: + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 753 .loc 1 951 0 + 754 0004 2023 movs r3, #32 + 755 0006 C35C ldrb r3, [r0, r3] + 756 0008 012B cmp r3, #1 + 757 000a 00D1 bne .LCB747 + 758 000c EAE0 b .L57 @long jump + 759 .LCB747: + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 760 .loc 1 951 0 is_stmt 0 discriminator 2 + 761 000e 2023 movs r3, #32 + 762 0010 0120 movs r0, #1 + 763 .LVL88: + 764 0012 E054 strb r0, [r4, r3] + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 765 .loc 1 953 0 is_stmt 1 discriminator 2 + 766 0014 0133 adds r3, r3, #1 + 767 0016 0130 adds r0, r0, #1 + 768 0018 E054 strb r0, [r4, r3] + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 769 .loc 1 955 0 discriminator 2 + 770 001a 002A cmp r2, #0 + 771 001c 71D1 bne .L39 + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 772 .loc 1 957 0 + 773 001e 2368 ldr r3, [r4] + 774 0020 9B68 ldr r3, [r3, #8] + 775 0022 5B06 lsls r3, r3, #25 + 776 0024 01D4 bmi .L40 + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + 777 .loc 1 964 0 + 778 0026 0023 movs r3, #0 + 779 0028 CB70 strb r3, [r1, #3] + ARM GAS /tmp/ccjtTCRz.s page 43 + + + 780 .L40: + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 781 .loc 1 970 0 + 782 002a CE69 ldr r6, [r1, #28] + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 783 .loc 1 978 0 + 784 002c 0B78 ldrb r3, [r1] + 785 .LVL89: + 786 .LBB88: + 787 .LBB89: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 788 .loc 1 1492 0 + 789 002e 1000 movs r0, r2 + 790 0030 02E0 b .L41 + 791 .LVL90: + 792 .L42: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 793 .loc 1 1496 0 + 794 0032 0130 adds r0, r0, #1 + 795 .LVL91: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 796 .loc 1 1497 0 + 797 0034 0A3B subs r3, r3, #10 + 798 .LVL92: + 799 0036 DBB2 uxtb r3, r3 + 800 .LVL93: + 801 .L41: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 802 .loc 1 1494 0 + 803 0038 092B cmp r3, #9 + 804 003a FAD8 bhi .L42 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 805 .loc 1 1500 0 + 806 003c 0001 lsls r0, r0, #4 + 807 .LVL94: + 808 003e C0B2 uxtb r0, r0 + 809 0040 1843 orrs r0, r3 + 810 .LVL95: + 811 .LBE89: + 812 .LBE88: + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 813 .loc 1 978 0 + 814 0042 0004 lsls r0, r0, #16 + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 815 .loc 1 979 0 + 816 0044 4B78 ldrb r3, [r1, #1] + 817 .LVL96: + 818 .LBB90: + 819 .LBB91: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 820 .loc 1 1492 0 + 821 0046 1500 movs r5, r2 + 822 0048 02E0 b .L43 + 823 .LVL97: + 824 .L44: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 825 .loc 1 1496 0 + ARM GAS /tmp/ccjtTCRz.s page 44 + + + 826 004a 0135 adds r5, r5, #1 + 827 .LVL98: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 828 .loc 1 1497 0 + 829 004c 0A3B subs r3, r3, #10 + 830 .LVL99: + 831 004e DBB2 uxtb r3, r3 + 832 .LVL100: + 833 .L43: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 834 .loc 1 1494 0 + 835 0050 092B cmp r3, #9 + 836 0052 FAD8 bhi .L44 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 837 .loc 1 1500 0 + 838 0054 2D01 lsls r5, r5, #4 + 839 .LVL101: + 840 0056 EDB2 uxtb r5, r5 + 841 0058 2B43 orrs r3, r5 + 842 .LVL102: + 843 .LBE91: + 844 .LBE90: + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 845 .loc 1 979 0 + 846 005a 1B02 lsls r3, r3, #8 + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 847 .loc 1 978 0 + 848 005c 0343 orrs r3, r0 + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 849 .loc 1 980 0 + 850 005e 8878 ldrb r0, [r1, #2] + 851 .LVL103: + 852 .LBB92: + 853 .LBB93: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 854 .loc 1 1492 0 + 855 0060 1500 movs r5, r2 + 856 0062 02E0 b .L45 + 857 .LVL104: + 858 .L46: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 859 .loc 1 1496 0 + 860 0064 0135 adds r5, r5, #1 + 861 .LVL105: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 862 .loc 1 1497 0 + 863 0066 0A38 subs r0, r0, #10 + 864 .LVL106: + 865 0068 C0B2 uxtb r0, r0 + 866 .LVL107: + 867 .L45: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 868 .loc 1 1494 0 + 869 006a 0928 cmp r0, #9 + 870 006c FAD8 bhi .L46 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 871 .loc 1 1500 0 + ARM GAS /tmp/ccjtTCRz.s page 45 + + + 872 006e 2D01 lsls r5, r5, #4 + 873 .LVL108: + 874 0070 EDB2 uxtb r5, r5 + 875 0072 2843 orrs r0, r5 + 876 .LVL109: + 877 .LBE93: + 878 .LBE92: + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 879 .loc 1 979 0 + 880 0074 1843 orrs r0, r3 + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 881 .loc 1 981 0 + 882 0076 CB78 ldrb r3, [r1, #3] + 883 0078 1B04 lsls r3, r3, #16 + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 884 .loc 1 980 0 + 885 007a 1843 orrs r0, r3 + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 886 .loc 1 982 0 + 887 007c 2023 movs r3, #32 + 888 007e CD5C ldrb r5, [r1, r3] + 889 .LVL110: + 890 0080 02E0 b .L47 + 891 .LVL111: + 892 .L48: + 893 .LBB94: + 894 .LBB95: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 895 .loc 1 1496 0 + 896 0082 0132 adds r2, r2, #1 + 897 .LVL112: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 898 .loc 1 1497 0 + 899 0084 0A3D subs r5, r5, #10 + 900 .LVL113: + 901 0086 EDB2 uxtb r5, r5 + 902 .LVL114: + 903 .L47: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 904 .loc 1 1494 0 + 905 0088 092D cmp r5, #9 + 906 008a FAD8 bhi .L48 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 907 .loc 1 1500 0 + 908 008c 1201 lsls r2, r2, #4 + 909 .LVL115: + 910 008e D3B2 uxtb r3, r2 + 911 0090 2B43 orrs r3, r5 + 912 .LVL116: + 913 .LBE95: + 914 .LBE94: + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 915 .loc 1 982 0 + 916 0092 1B06 lsls r3, r3, #24 + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 917 .loc 1 981 0 + 918 0094 0343 orrs r3, r0 + ARM GAS /tmp/ccjtTCRz.s page 46 + + + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 919 .loc 1 982 0 + 920 0096 1E43 orrs r6, r3 + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 921 .loc 1 978 0 + 922 0098 4B69 ldr r3, [r1, #20] + 923 009a 1E43 orrs r6, r3 + 924 .LVL117: + 925 .L49: +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 926 .loc 1 1022 0 + 927 009c 4D68 ldr r5, [r1, #4] + 928 009e 8B69 ldr r3, [r1, #24] + 929 00a0 1D43 orrs r5, r3 + 930 .LVL118: +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 931 .loc 1 1025 0 + 932 00a2 2368 ldr r3, [r4] + 933 00a4 CA22 movs r2, #202 + 934 00a6 5A62 str r2, [r3, #36] + 935 00a8 2368 ldr r3, [r4] + 936 00aa 773A subs r2, r2, #119 + 937 00ac 5A62 str r2, [r3, #36] +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 938 .loc 1 1028 0 + 939 00ae 4A6A ldr r2, [r1, #36] + 940 00b0 8023 movs r3, #128 + 941 00b2 5B00 lsls r3, r3, #1 + 942 00b4 9A42 cmp r2, r3 + 943 00b6 3DD0 beq .L58 +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 944 .loc 1 1065 0 + 945 00b8 2268 ldr r2, [r4] + 946 00ba 9368 ldr r3, [r2, #8] + 947 00bc 4A49 ldr r1, .L61 + 948 .LVL119: + 949 00be 0B40 ands r3, r1 + 950 00c0 9360 str r3, [r2, #8] +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 951 .loc 1 1068 0 + 952 00c2 2168 ldr r1, [r4] + 953 00c4 CA68 ldr r2, [r1, #12] + 954 00c6 FF23 movs r3, #255 + 955 00c8 1A40 ands r2, r3 + 956 00ca 484B ldr r3, .L61+4 + 957 00cc 1343 orrs r3, r2 + 958 00ce CB60 str r3, [r1, #12] +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + 959 .loc 1 1070 0 + 960 00d0 FFF7FEFF bl HAL_GetTick + 961 .LVL120: + 962 00d4 0700 movs r7, r0 + 963 .LVL121: + 964 .L55: +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 965 .loc 1 1072 0 + 966 00d6 2268 ldr r2, [r4] + ARM GAS /tmp/ccjtTCRz.s page 47 + + + 967 00d8 D168 ldr r1, [r2, #12] + 968 00da 8B07 lsls r3, r1, #30 + 969 00dc 5FD4 bmi .L59 +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 970 .loc 1 1074 0 + 971 00de FFF7FEFF bl HAL_GetTick + 972 .LVL122: + 973 00e2 C01B subs r0, r0, r7 + 974 00e4 FA23 movs r3, #250 + 975 00e6 9B00 lsls r3, r3, #2 + 976 00e8 9842 cmp r0, r3 + 977 00ea F4D9 bls .L55 +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 978 .loc 1 1077 0 + 979 00ec 2368 ldr r3, [r4] + 980 00ee FF22 movs r2, #255 + 981 00f0 5A62 str r2, [r3, #36] +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 982 .loc 1 1079 0 + 983 00f2 2123 movs r3, #33 + 984 00f4 FC3A subs r2, r2, #252 + 985 00f6 E254 strb r2, [r4, r3] +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 986 .loc 1 1082 0 + 987 00f8 013B subs r3, r3, #1 + 988 00fa 0022 movs r2, #0 + 989 00fc E254 strb r2, [r4, r3] +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 990 .loc 1 1084 0 + 991 00fe 0320 movs r0, #3 + 992 0100 6FE0 b .L38 + 993 .LVL123: + 994 .L39: + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 995 .loc 1 988 0 + 996 0102 2368 ldr r3, [r4] + 997 0104 9B68 ldr r3, [r3, #8] + 998 0106 5B06 lsls r3, r3, #25 + 999 0108 01D4 bmi .L50 + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + 1000 .loc 1 996 0 + 1001 010a 0023 movs r3, #0 + 1002 010c CB70 strb r3, [r1, #3] + 1003 .L50: +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 1004 .loc 1 1013 0 + 1005 010e 0E78 ldrb r6, [r1] + 1006 0110 3604 lsls r6, r6, #16 +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 1007 .loc 1 1014 0 + 1008 0112 4B78 ldrb r3, [r1, #1] + 1009 0114 1B02 lsls r3, r3, #8 +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 1010 .loc 1 1013 0 + 1011 0116 1E43 orrs r6, r3 +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 1012 .loc 1 1015 0 + ARM GAS /tmp/ccjtTCRz.s page 48 + + + 1013 0118 8B78 ldrb r3, [r1, #2] +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 1014 .loc 1 1014 0 + 1015 011a 1E43 orrs r6, r3 +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 1016 .loc 1 1016 0 + 1017 011c CB78 ldrb r3, [r1, #3] + 1018 011e 1B04 lsls r3, r3, #16 +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 1019 .loc 1 1015 0 + 1020 0120 1E43 orrs r6, r3 +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 1021 .loc 1 1017 0 + 1022 0122 2023 movs r3, #32 + 1023 0124 CB5C ldrb r3, [r1, r3] + 1024 0126 1B06 lsls r3, r3, #24 +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 1025 .loc 1 1016 0 + 1026 0128 1E43 orrs r6, r3 +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 1027 .loc 1 1017 0 + 1028 012a CB69 ldr r3, [r1, #28] + 1029 012c 1E43 orrs r6, r3 +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 1030 .loc 1 1013 0 + 1031 012e 4B69 ldr r3, [r1, #20] + 1032 0130 1E43 orrs r6, r3 + 1033 .LVL124: + 1034 0132 B3E7 b .L49 + 1035 .LVL125: + 1036 .L58: +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1037 .loc 1 1031 0 + 1038 0134 2268 ldr r2, [r4] + 1039 0136 9368 ldr r3, [r2, #8] + 1040 0138 2D49 ldr r1, .L61+8 + 1041 .LVL126: + 1042 013a 0B40 ands r3, r1 + 1043 013c 9360 str r3, [r2, #8] +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1044 .loc 1 1034 0 + 1045 013e 2168 ldr r1, [r4] + 1046 0140 CA68 ldr r2, [r1, #12] + 1047 0142 FF23 movs r3, #255 + 1048 0144 1A40 ands r2, r3 + 1049 0146 2B4B ldr r3, .L61+12 + 1050 0148 1343 orrs r3, r2 + 1051 014a CB60 str r3, [r1, #12] +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + 1052 .loc 1 1036 0 + 1053 014c FFF7FEFF bl HAL_GetTick + 1054 .LVL127: + 1055 0150 0700 movs r7, r0 + 1056 .LVL128: + 1057 .L52: +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1058 .loc 1 1038 0 + ARM GAS /tmp/ccjtTCRz.s page 49 + + + 1059 0152 2368 ldr r3, [r4] + 1060 0154 DA68 ldr r2, [r3, #12] + 1061 0156 D207 lsls r2, r2, #31 + 1062 0158 11D4 bmi .L60 +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1063 .loc 1 1040 0 + 1064 015a FFF7FEFF bl HAL_GetTick + 1065 .LVL129: + 1066 015e C01B subs r0, r0, r7 + 1067 0160 FA23 movs r3, #250 + 1068 0162 9B00 lsls r3, r3, #2 + 1069 0164 9842 cmp r0, r3 + 1070 0166 F4D9 bls .L52 +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1071 .loc 1 1043 0 + 1072 0168 2368 ldr r3, [r4] + 1073 016a FF22 movs r2, #255 + 1074 016c 5A62 str r2, [r3, #36] +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1075 .loc 1 1045 0 + 1076 016e 2123 movs r3, #33 + 1077 0170 FC3A subs r2, r2, #252 + 1078 0172 E254 strb r2, [r4, r3] +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1079 .loc 1 1048 0 + 1080 0174 013B subs r3, r3, #1 + 1081 0176 0022 movs r2, #0 + 1082 0178 E254 strb r2, [r4, r3] +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1083 .loc 1 1050 0 + 1084 017a 0320 movs r0, #3 + 1085 017c 31E0 b .L38 + 1086 .L60: +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm A Sub Second register */ + 1087 .loc 1 1054 0 + 1088 017e DE61 str r6, [r3, #28] +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + 1089 .loc 1 1056 0 + 1090 0180 2368 ldr r3, [r4] + 1091 0182 5D64 str r5, [r3, #68] +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm interrupt */ + 1092 .loc 1 1058 0 + 1093 0184 2268 ldr r2, [r4] + 1094 0186 9168 ldr r1, [r2, #8] + 1095 0188 8023 movs r3, #128 + 1096 018a 5B00 lsls r3, r3, #1 + 1097 018c 0B43 orrs r3, r1 + 1098 018e 9360 str r3, [r2, #8] +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1099 .loc 1 1060 0 + 1100 0190 2268 ldr r2, [r4] + 1101 0192 9168 ldr r1, [r2, #8] + 1102 0194 8023 movs r3, #128 + 1103 0196 5B01 lsls r3, r3, #5 + 1104 0198 0B43 orrs r3, r1 + 1105 019a 9360 str r3, [r2, #8] + 1106 019c 0EE0 b .L54 + ARM GAS /tmp/ccjtTCRz.s page 50 + + + 1107 .L59: +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm B Sub Second register */ + 1108 .loc 1 1088 0 + 1109 019e 1662 str r6, [r2, #32] +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm state: Enable Alarm */ + 1110 .loc 1 1090 0 + 1111 01a0 2368 ldr r3, [r4] + 1112 01a2 9D64 str r5, [r3, #72] +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Configure the Alarm interrupt */ + 1113 .loc 1 1092 0 + 1114 01a4 2268 ldr r2, [r4] + 1115 01a6 9168 ldr r1, [r2, #8] + 1116 01a8 8023 movs r3, #128 + 1117 01aa 9B00 lsls r3, r3, #2 + 1118 01ac 0B43 orrs r3, r1 + 1119 01ae 9360 str r3, [r2, #8] +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1120 .loc 1 1094 0 + 1121 01b0 2268 ldr r2, [r4] + 1122 01b2 9168 ldr r1, [r2, #8] + 1123 01b4 8023 movs r3, #128 + 1124 01b6 9B01 lsls r3, r3, #6 + 1125 01b8 0B43 orrs r3, r1 + 1126 01ba 9360 str r3, [r2, #8] + 1127 .L54: +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1128 .loc 1 1098 0 + 1129 01bc 0E4B ldr r3, .L61+16 + 1130 01be 1968 ldr r1, [r3] + 1131 01c0 8022 movs r2, #128 + 1132 01c2 9202 lsls r2, r2, #10 + 1133 01c4 1143 orrs r1, r2 + 1134 01c6 1960 str r1, [r3] +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1135 .loc 1 1100 0 + 1136 01c8 9968 ldr r1, [r3, #8] + 1137 01ca 0A43 orrs r2, r1 + 1138 01cc 9A60 str r2, [r3, #8] +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1139 .loc 1 1103 0 + 1140 01ce 2368 ldr r3, [r4] + 1141 01d0 FF22 movs r2, #255 + 1142 01d2 5A62 str r2, [r3, #36] +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1143 .loc 1 1105 0 + 1144 01d4 2123 movs r3, #33 + 1145 01d6 FE3A subs r2, r2, #254 + 1146 01d8 E254 strb r2, [r4, r3] +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1147 .loc 1 1108 0 + 1148 01da 013B subs r3, r3, #1 + 1149 01dc 0022 movs r2, #0 + 1150 01de E254 strb r2, [r4, r3] +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1151 .loc 1 1110 0 + 1152 01e0 0020 movs r0, #0 + 1153 .LVL130: + ARM GAS /tmp/ccjtTCRz.s page 51 + + + 1154 .L38: +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1155 .loc 1 1111 0 + 1156 @ sp needed + 1157 .LVL131: + 1158 01e2 F8BD pop {r3, r4, r5, r6, r7, pc} + 1159 .LVL132: + 1160 .L57: + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1161 .loc 1 951 0 + 1162 01e4 0220 movs r0, #2 + 1163 .LVL133: + 1164 01e6 FCE7 b .L38 + 1165 .L62: + 1166 .align 2 + 1167 .L61: + 1168 01e8 FFFDFFFF .word -513 + 1169 01ec 7FFDFFFF .word -641 + 1170 01f0 FFFEFFFF .word -257 + 1171 01f4 7FFEFFFF .word -385 + 1172 01f8 00040140 .word 1073808384 + 1173 .cfi_endproc + 1174 .LFE48: + 1176 .section .text.HAL_RTC_DeactivateAlarm,"ax",%progbits + 1177 .align 1 + 1178 .global HAL_RTC_DeactivateAlarm + 1179 .syntax unified + 1180 .code 16 + 1181 .thumb_func + 1182 .fpu softvfp + 1184 HAL_RTC_DeactivateAlarm: + 1185 .LFB49: +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 1186 .loc 1 1123 0 + 1187 .cfi_startproc + 1188 @ args = 0, pretend = 0, frame = 0 + 1189 @ frame_needed = 0, uses_anonymous_args = 0 + 1190 .LVL134: + 1191 0000 70B5 push {r4, r5, r6, lr} + 1192 .LCFI4: + 1193 .cfi_def_cfa_offset 16 + 1194 .cfi_offset 4, -16 + 1195 .cfi_offset 5, -12 + 1196 .cfi_offset 6, -8 + 1197 .cfi_offset 14, -4 + 1198 0002 0400 movs r4, r0 + 1199 .LVL135: +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1200 .loc 1 1130 0 + 1201 0004 2023 movs r3, #32 + 1202 0006 C35C ldrb r3, [r0, r3] + 1203 0008 012B cmp r3, #1 + 1204 000a 60D0 beq .L71 +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1205 .loc 1 1130 0 is_stmt 0 discriminator 2 + 1206 000c 2023 movs r3, #32 + 1207 000e 0122 movs r2, #1 + ARM GAS /tmp/ccjtTCRz.s page 52 + + + 1208 0010 C254 strb r2, [r0, r3] +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1209 .loc 1 1132 0 is_stmt 1 discriminator 2 + 1210 0012 0133 adds r3, r3, #1 + 1211 0014 0132 adds r2, r2, #1 + 1212 0016 C254 strb r2, [r0, r3] +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1213 .loc 1 1135 0 discriminator 2 + 1214 0018 0368 ldr r3, [r0] + 1215 001a C832 adds r2, r2, #200 + 1216 001c 5A62 str r2, [r3, #36] + 1217 001e 0368 ldr r3, [r0] + 1218 0020 773A subs r2, r2, #119 + 1219 0022 5A62 str r2, [r3, #36] +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1220 .loc 1 1137 0 discriminator 2 + 1221 0024 8023 movs r3, #128 + 1222 0026 5B00 lsls r3, r3, #1 + 1223 0028 9942 cmp r1, r3 + 1224 002a 22D0 beq .L72 +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1225 .loc 1 1167 0 + 1226 002c 0268 ldr r2, [r0] + 1227 002e 9368 ldr r3, [r2, #8] + 1228 0030 2849 ldr r1, .L73 + 1229 .LVL136: + 1230 0032 0B40 ands r3, r1 + 1231 0034 9360 str r3, [r2, #8] +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1232 .loc 1 1170 0 + 1233 0036 0268 ldr r2, [r0] + 1234 0038 9368 ldr r3, [r2, #8] + 1235 003a 2749 ldr r1, .L73+4 + 1236 003c 0B40 ands r3, r1 + 1237 003e 9360 str r3, [r2, #8] +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1238 .loc 1 1172 0 + 1239 0040 FFF7FEFF bl HAL_GetTick + 1240 .LVL137: + 1241 0044 0500 movs r5, r0 + 1242 .LVL138: + 1243 .L69: +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1244 .loc 1 1175 0 + 1245 0046 2368 ldr r3, [r4] + 1246 0048 DB68 ldr r3, [r3, #12] + 1247 004a 9B07 lsls r3, r3, #30 + 1248 004c 34D4 bmi .L68 +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1249 .loc 1 1177 0 + 1250 004e FFF7FEFF bl HAL_GetTick + 1251 .LVL139: + 1252 0052 401B subs r0, r0, r5 + 1253 0054 FA23 movs r3, #250 + 1254 0056 9B00 lsls r3, r3, #2 + 1255 0058 9842 cmp r0, r3 + 1256 005a F4D9 bls .L69 + ARM GAS /tmp/ccjtTCRz.s page 53 + + +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1257 .loc 1 1180 0 + 1258 005c 2368 ldr r3, [r4] + 1259 005e FF22 movs r2, #255 + 1260 0060 5A62 str r2, [r3, #36] +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1261 .loc 1 1182 0 + 1262 0062 2123 movs r3, #33 + 1263 0064 FC3A subs r2, r2, #252 + 1264 0066 E254 strb r2, [r4, r3] +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1265 .loc 1 1185 0 + 1266 0068 013B subs r3, r3, #1 + 1267 006a 0022 movs r2, #0 + 1268 006c E254 strb r2, [r4, r3] +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1269 .loc 1 1187 0 + 1270 006e 0320 movs r0, #3 + 1271 0070 2CE0 b .L64 + 1272 .LVL140: + 1273 .L72: +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1274 .loc 1 1140 0 + 1275 0072 0268 ldr r2, [r0] + 1276 0074 9368 ldr r3, [r2, #8] + 1277 0076 1949 ldr r1, .L73+8 + 1278 .LVL141: + 1279 0078 0B40 ands r3, r1 + 1280 007a 9360 str r3, [r2, #8] +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1281 .loc 1 1143 0 + 1282 007c 0268 ldr r2, [r0] + 1283 007e 9368 ldr r3, [r2, #8] + 1284 0080 1749 ldr r1, .L73+12 + 1285 0082 0B40 ands r3, r1 + 1286 0084 9360 str r3, [r2, #8] +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1287 .loc 1 1145 0 + 1288 0086 FFF7FEFF bl HAL_GetTick + 1289 .LVL142: + 1290 008a 0500 movs r5, r0 + 1291 .LVL143: + 1292 .L66: +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1293 .loc 1 1148 0 + 1294 008c 2368 ldr r3, [r4] + 1295 008e DB68 ldr r3, [r3, #12] + 1296 0090 DB07 lsls r3, r3, #31 + 1297 0092 11D4 bmi .L68 +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1298 .loc 1 1150 0 + 1299 0094 FFF7FEFF bl HAL_GetTick + 1300 .LVL144: + 1301 0098 401B subs r0, r0, r5 + 1302 009a FA23 movs r3, #250 + 1303 009c 9B00 lsls r3, r3, #2 + 1304 009e 9842 cmp r0, r3 + ARM GAS /tmp/ccjtTCRz.s page 54 + + + 1305 00a0 F4D9 bls .L66 +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1306 .loc 1 1153 0 + 1307 00a2 2368 ldr r3, [r4] + 1308 00a4 FF22 movs r2, #255 + 1309 00a6 5A62 str r2, [r3, #36] +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1310 .loc 1 1155 0 + 1311 00a8 2123 movs r3, #33 + 1312 00aa FC3A subs r2, r2, #252 + 1313 00ac E254 strb r2, [r4, r3] +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1314 .loc 1 1158 0 + 1315 00ae 013B subs r3, r3, #1 + 1316 00b0 0022 movs r2, #0 + 1317 00b2 E254 strb r2, [r4, r3] +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1318 .loc 1 1160 0 + 1319 00b4 0320 movs r0, #3 + 1320 00b6 09E0 b .L64 + 1321 .L68: +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1322 .loc 1 1192 0 + 1323 00b8 2368 ldr r3, [r4] + 1324 00ba FF22 movs r2, #255 + 1325 00bc 5A62 str r2, [r3, #36] +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1326 .loc 1 1194 0 + 1327 00be 2123 movs r3, #33 + 1328 00c0 FE3A subs r2, r2, #254 + 1329 00c2 E254 strb r2, [r4, r3] +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1330 .loc 1 1197 0 + 1331 00c4 013B subs r3, r3, #1 + 1332 00c6 0022 movs r2, #0 + 1333 00c8 E254 strb r2, [r4, r3] +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1334 .loc 1 1199 0 + 1335 00ca 0020 movs r0, #0 + 1336 .LVL145: + 1337 .L64: +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1338 .loc 1 1200 0 + 1339 @ sp needed + 1340 .LVL146: + 1341 00cc 70BD pop {r4, r5, r6, pc} + 1342 .LVL147: + 1343 .L71: +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1344 .loc 1 1130 0 + 1345 00ce 0220 movs r0, #2 + 1346 .LVL148: + 1347 00d0 FCE7 b .L64 + 1348 .L74: + 1349 00d2 C046 .align 2 + 1350 .L73: + 1351 00d4 FFFDFFFF .word -513 + ARM GAS /tmp/ccjtTCRz.s page 55 + + + 1352 00d8 FFDFFFFF .word -8193 + 1353 00dc FFFEFFFF .word -257 + 1354 00e0 FFEFFFFF .word -4097 + 1355 .cfi_endproc + 1356 .LFE49: + 1358 .section .text.HAL_RTC_GetAlarm,"ax",%progbits + 1359 .align 1 + 1360 .global HAL_RTC_GetAlarm + 1361 .syntax unified + 1362 .code 16 + 1363 .thumb_func + 1364 .fpu softvfp + 1366 HAL_RTC_GetAlarm: + 1367 .LFB50: +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + 1368 .loc 1 1217 0 + 1369 .cfi_startproc + 1370 @ args = 0, pretend = 0, frame = 0 + 1371 @ frame_needed = 0, uses_anonymous_args = 0 + 1372 .LVL149: + 1373 0000 F0B5 push {r4, r5, r6, r7, lr} + 1374 .LCFI5: + 1375 .cfi_def_cfa_offset 20 + 1376 .cfi_offset 4, -20 + 1377 .cfi_offset 5, -16 + 1378 .cfi_offset 6, -12 + 1379 .cfi_offset 7, -8 + 1380 .cfi_offset 14, -4 + 1381 .LVL150: +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1382 .loc 1 1224 0 + 1383 0002 8024 movs r4, #128 + 1384 0004 6400 lsls r4, r4, #1 + 1385 0006 A242 cmp r2, r4 + 1386 0008 48D0 beq .L79 +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1387 .loc 1 1244 0 + 1388 000a 8022 movs r2, #128 + 1389 .LVL151: + 1390 000c 9200 lsls r2, r2, #2 + 1391 000e 4A62 str r2, [r1, #36] +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); + 1392 .loc 1 1246 0 + 1393 0010 0068 ldr r0, [r0] + 1394 .LVL152: + 1395 0012 026A ldr r2, [r0, #32] + 1396 .LVL153: +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1397 .loc 1 1247 0 + 1398 0014 806C ldr r0, [r0, #72] + 1399 0016 4004 lsls r0, r0, #17 + 1400 0018 400C lsrs r0, r0, #17 + 1401 .LVL154: +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U); + 1402 .loc 1 1250 0 + 1403 001a 150C lsrs r5, r2, #16 + 1404 001c EDB2 uxtb r5, r5 + ARM GAS /tmp/ccjtTCRz.s page 56 + + + 1405 001e 3F24 movs r4, #63 + 1406 0020 2600 movs r6, r4 + 1407 0022 2E40 ands r6, r5 + 1408 0024 0E70 strb r6, [r1] +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); + 1409 .loc 1 1251 0 + 1410 0026 170A lsrs r7, r2, #8 + 1411 0028 7F26 movs r6, #127 + 1412 002a 3740 ands r7, r6 + 1413 002c 4F70 strb r7, [r1, #1] +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16U); + 1414 .loc 1 1252 0 + 1415 002e 1640 ands r6, r2 + 1416 0030 8E70 strb r6, [r1, #2] +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + 1417 .loc 1 1253 0 + 1418 0032 4026 movs r6, #64 + 1419 0034 3540 ands r5, r6 + 1420 0036 CD70 strb r5, [r1, #3] +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U); + 1421 .loc 1 1254 0 + 1422 0038 4860 str r0, [r1, #4] +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + 1423 .loc 1 1255 0 + 1424 003a 100E lsrs r0, r2, #24 + 1425 .LVL155: + 1426 003c 0440 ands r4, r0 + 1427 003e 2020 movs r0, #32 + 1428 0040 0C54 strb r4, [r1, r0] + 1429 .LVL156: +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + 1430 .loc 1 1256 0 + 1431 0042 8020 movs r0, #128 + 1432 0044 C005 lsls r0, r0, #23 + 1433 0046 1040 ands r0, r2 + 1434 0048 C861 str r0, [r1, #28] +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1435 .loc 1 1257 0 + 1436 004a 2548 ldr r0, .L80 + 1437 004c 0240 ands r2, r0 + 1438 .LVL157: + 1439 004e 4A61 str r2, [r1, #20] + 1440 .L77: +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1441 .loc 1 1260 0 + 1442 0050 002B cmp r3, #0 + 1443 0052 21D1 bne .L78 +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + 1444 .loc 1 1262 0 + 1445 0054 0A78 ldrb r2, [r1] + 1446 .LVL158: + 1447 .LBB96: + 1448 .LBB97: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 1449 .loc 1 1511 0 + 1450 0056 1009 lsrs r0, r2, #4 + 1451 0058 8300 lsls r3, r0, #2 + ARM GAS /tmp/ccjtTCRz.s page 57 + + + 1452 .LVL159: + 1453 005a 1B18 adds r3, r3, r0 + 1454 005c 5800 lsls r0, r3, #1 + 1455 .LVL160: + 1456 .loc 1 1512 0 + 1457 005e 0F23 movs r3, #15 + 1458 0060 1A40 ands r2, r3 + 1459 .LVL161: + 1460 0062 1218 adds r2, r2, r0 + 1461 .LVL162: + 1462 .LBE97: + 1463 .LBE96: +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + 1464 .loc 1 1262 0 + 1465 0064 0A70 strb r2, [r1] +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + 1466 .loc 1 1263 0 + 1467 0066 4A78 ldrb r2, [r1, #1] + 1468 .LVL163: + 1469 .LBB98: + 1470 .LBB99: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 1471 .loc 1 1511 0 + 1472 0068 1409 lsrs r4, r2, #4 + 1473 006a A000 lsls r0, r4, #2 + 1474 006c 0019 adds r0, r0, r4 + 1475 006e 4400 lsls r4, r0, #1 + 1476 .LVL164: + 1477 .loc 1 1512 0 + 1478 0070 1A40 ands r2, r3 + 1479 .LVL165: + 1480 0072 1219 adds r2, r2, r4 + 1481 .LVL166: + 1482 .LBE99: + 1483 .LBE98: +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + 1484 .loc 1 1263 0 + 1485 0074 4A70 strb r2, [r1, #1] +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + 1486 .loc 1 1264 0 + 1487 0076 8A78 ldrb r2, [r1, #2] + 1488 .LVL167: + 1489 .LBB100: + 1490 .LBB101: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 1491 .loc 1 1511 0 + 1492 0078 1409 lsrs r4, r2, #4 + 1493 007a A000 lsls r0, r4, #2 + 1494 007c 0019 adds r0, r0, r4 + 1495 007e 4400 lsls r4, r0, #1 + 1496 .LVL168: + 1497 .loc 1 1512 0 + 1498 0080 1A40 ands r2, r3 + 1499 .LVL169: + 1500 0082 1219 adds r2, r2, r4 + 1501 .LVL170: + 1502 .LBE101: + ARM GAS /tmp/ccjtTCRz.s page 58 + + + 1503 .LBE100: +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + 1504 .loc 1 1264 0 + 1505 0084 8A70 strb r2, [r1, #2] +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1506 .loc 1 1265 0 + 1507 0086 2020 movs r0, #32 + 1508 0088 0D5C ldrb r5, [r1, r0] + 1509 .LVL171: + 1510 .LBB102: + 1511 .LBB103: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 1512 .loc 1 1511 0 + 1513 008a 2C09 lsrs r4, r5, #4 + 1514 008c A200 lsls r2, r4, #2 + 1515 008e 1219 adds r2, r2, r4 + 1516 0090 5400 lsls r4, r2, #1 + 1517 .LVL172: + 1518 .loc 1 1512 0 + 1519 0092 2B40 ands r3, r5 + 1520 0094 1B19 adds r3, r3, r4 + 1521 .LVL173: + 1522 .LBE103: + 1523 .LBE102: +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1524 .loc 1 1265 0 + 1525 0096 0B54 strb r3, [r1, r0] + 1526 .L78: +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1527 .loc 1 1269 0 + 1528 0098 0020 movs r0, #0 + 1529 @ sp needed + 1530 009a F0BD pop {r4, r5, r6, r7, pc} + 1531 .LVL174: + 1532 .L79: +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1533 .loc 1 1227 0 + 1534 009c 4C62 str r4, [r1, #36] +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + 1535 .loc 1 1229 0 + 1536 009e 0068 ldr r0, [r0] + 1537 .LVL175: + 1538 00a0 C269 ldr r2, [r0, #28] + 1539 .LVL176: +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1540 .loc 1 1230 0 + 1541 00a2 406C ldr r0, [r0, #68] + 1542 00a4 4004 lsls r0, r0, #17 + 1543 00a6 400C lsrs r0, r0, #17 + 1544 .LVL177: +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); + 1545 .loc 1 1233 0 + 1546 00a8 150C lsrs r5, r2, #16 + 1547 00aa EDB2 uxtb r5, r5 + 1548 00ac C13C subs r4, r4, #193 + 1549 00ae 2600 movs r6, r4 + 1550 00b0 2E40 ands r6, r5 + ARM GAS /tmp/ccjtTCRz.s page 59 + + + 1551 00b2 0E70 strb r6, [r1] +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + 1552 .loc 1 1234 0 + 1553 00b4 170A lsrs r7, r2, #8 + 1554 00b6 7F26 movs r6, #127 + 1555 00b8 3740 ands r7, r6 + 1556 00ba 4F70 strb r7, [r1, #1] +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); + 1557 .loc 1 1235 0 + 1558 00bc 1640 ands r6, r2 + 1559 00be 8E70 strb r6, [r1, #2] +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + 1560 .loc 1 1236 0 + 1561 00c0 4026 movs r6, #64 + 1562 00c2 3540 ands r5, r6 + 1563 00c4 CD70 strb r5, [r1, #3] +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); + 1564 .loc 1 1237 0 + 1565 00c6 4860 str r0, [r1, #4] +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + 1566 .loc 1 1238 0 + 1567 00c8 100E lsrs r0, r2, #24 + 1568 .LVL178: + 1569 00ca 0440 ands r4, r0 + 1570 00cc 2020 movs r0, #32 + 1571 00ce 0C54 strb r4, [r1, r0] + 1572 .LVL179: +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + 1573 .loc 1 1239 0 + 1574 00d0 8020 movs r0, #128 + 1575 00d2 C005 lsls r0, r0, #23 + 1576 00d4 1040 ands r0, r2 + 1577 00d6 C861 str r0, [r1, #28] +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1578 .loc 1 1240 0 + 1579 00d8 0148 ldr r0, .L80 + 1580 00da 0240 ands r2, r0 + 1581 .LVL180: + 1582 00dc 4A61 str r2, [r1, #20] + 1583 00de B7E7 b .L77 + 1584 .L81: + 1585 .align 2 + 1586 .L80: + 1587 00e0 80808080 .word -2139062144 + 1588 .cfi_endproc + 1589 .LFE50: + 1591 .section .text.HAL_RTC_AlarmAEventCallback,"ax",%progbits + 1592 .align 1 + 1593 .weak HAL_RTC_AlarmAEventCallback + 1594 .syntax unified + 1595 .code 16 + 1596 .thumb_func + 1597 .fpu softvfp + 1599 HAL_RTC_AlarmAEventCallback: + 1600 .LFB52: +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Prevent unused argument(s) compilation warning */ + 1601 .loc 1 1319 0 + ARM GAS /tmp/ccjtTCRz.s page 60 + + + 1602 .cfi_startproc + 1603 @ args = 0, pretend = 0, frame = 0 + 1604 @ frame_needed = 0, uses_anonymous_args = 0 + 1605 @ link register save eliminated. + 1606 .LVL181: +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1607 .loc 1 1326 0 + 1608 @ sp needed + 1609 0000 7047 bx lr + 1610 .cfi_endproc + 1611 .LFE52: + 1613 .section .text.HAL_RTC_AlarmIRQHandler,"ax",%progbits + 1614 .align 1 + 1615 .global HAL_RTC_AlarmIRQHandler + 1616 .syntax unified + 1617 .code 16 + 1618 .thumb_func + 1619 .fpu softvfp + 1621 HAL_RTC_AlarmIRQHandler: + 1622 .LFB51: +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Get the AlarmA interrupt source enable status */ + 1623 .loc 1 1277 0 + 1624 .cfi_startproc + 1625 @ args = 0, pretend = 0, frame = 0 + 1626 @ frame_needed = 0, uses_anonymous_args = 0 + 1627 .LVL182: + 1628 0000 10B5 push {r4, lr} + 1629 .LCFI6: + 1630 .cfi_def_cfa_offset 8 + 1631 .cfi_offset 4, -8 + 1632 .cfi_offset 14, -4 + 1633 0002 0400 movs r4, r0 +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1634 .loc 1 1279 0 + 1635 0004 0368 ldr r3, [r0] + 1636 0006 9A68 ldr r2, [r3, #8] + 1637 0008 D204 lsls r2, r2, #19 + 1638 000a 02D5 bpl .L84 +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1639 .loc 1 1282 0 + 1640 000c DB68 ldr r3, [r3, #12] + 1641 000e DB05 lsls r3, r3, #23 + 1642 0010 0ED4 bmi .L86 + 1643 .LVL183: + 1644 .L84: +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1645 .loc 1 1293 0 + 1646 0012 2368 ldr r3, [r4] + 1647 0014 9A68 ldr r2, [r3, #8] + 1648 0016 9204 lsls r2, r2, #18 + 1649 0018 02D5 bpl .L85 +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1650 .loc 1 1296 0 + 1651 001a DB68 ldr r3, [r3, #12] + 1652 001c 9B05 lsls r3, r3, #22 + 1653 001e 11D4 bmi .L87 + 1654 .L85: + ARM GAS /tmp/ccjtTCRz.s page 61 + + +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1655 .loc 1 1307 0 + 1656 0020 0E4B ldr r3, .L88 + 1657 0022 8022 movs r2, #128 + 1658 0024 9202 lsls r2, r2, #10 + 1659 0026 5A61 str r2, [r3, #20] +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1660 .loc 1 1310 0 + 1661 0028 2123 movs r3, #33 + 1662 002a 0122 movs r2, #1 + 1663 002c E254 strb r2, [r4, r3] +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1664 .loc 1 1311 0 + 1665 @ sp needed + 1666 .LVL184: + 1667 002e 10BD pop {r4, pc} + 1668 .LVL185: + 1669 .L86: +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1670 .loc 1 1285 0 + 1671 0030 FFF7FEFF bl HAL_RTC_AlarmAEventCallback + 1672 .LVL186: +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1673 .loc 1 1288 0 + 1674 0034 2168 ldr r1, [r4] + 1675 0036 CA68 ldr r2, [r1, #12] + 1676 0038 FF23 movs r3, #255 + 1677 003a 1A40 ands r2, r3 + 1678 003c 084B ldr r3, .L88+4 + 1679 003e 1343 orrs r3, r2 + 1680 0040 CB60 str r3, [r1, #12] + 1681 0042 E6E7 b .L84 + 1682 .L87: +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1683 .loc 1 1299 0 + 1684 0044 2000 movs r0, r4 + 1685 0046 FFF7FEFF bl HAL_RTCEx_AlarmBEventCallback + 1686 .LVL187: +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1687 .loc 1 1302 0 + 1688 004a 2168 ldr r1, [r4] + 1689 004c CA68 ldr r2, [r1, #12] + 1690 004e FF23 movs r3, #255 + 1691 0050 1A40 ands r2, r3 + 1692 0052 044B ldr r3, .L88+8 + 1693 0054 1343 orrs r3, r2 + 1694 0056 CB60 str r3, [r1, #12] + 1695 0058 E2E7 b .L85 + 1696 .L89: + 1697 005a C046 .align 2 + 1698 .L88: + 1699 005c 00040140 .word 1073808384 + 1700 0060 7FFEFFFF .word -385 + 1701 0064 7FFDFFFF .word -641 + 1702 .cfi_endproc + 1703 .LFE51: + 1705 .section .text.HAL_RTC_PollForAlarmAEvent,"ax",%progbits + ARM GAS /tmp/ccjtTCRz.s page 62 + + + 1706 .align 1 + 1707 .global HAL_RTC_PollForAlarmAEvent + 1708 .syntax unified + 1709 .code 16 + 1710 .thumb_func + 1711 .fpu softvfp + 1713 HAL_RTC_PollForAlarmAEvent: + 1714 .LFB53: +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1715 .loc 1 1335 0 + 1716 .cfi_startproc + 1717 @ args = 0, pretend = 0, frame = 0 + 1718 @ frame_needed = 0, uses_anonymous_args = 0 + 1719 .LVL188: + 1720 0000 70B5 push {r4, r5, r6, lr} + 1721 .LCFI7: + 1722 .cfi_def_cfa_offset 16 + 1723 .cfi_offset 4, -16 + 1724 .cfi_offset 5, -12 + 1725 .cfi_offset 6, -8 + 1726 .cfi_offset 14, -4 + 1727 0002 0400 movs r4, r0 + 1728 0004 0D00 movs r5, r1 +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1729 .loc 1 1337 0 + 1730 0006 FFF7FEFF bl HAL_GetTick + 1731 .LVL189: + 1732 000a 0600 movs r6, r0 + 1733 .LVL190: + 1734 .L92: +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1735 .loc 1 1339 0 + 1736 000c 2368 ldr r3, [r4] + 1737 000e DA68 ldr r2, [r3, #12] + 1738 0010 D205 lsls r2, r2, #23 + 1739 0012 0DD4 bmi .L96 +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1740 .loc 1 1341 0 + 1741 0014 6B1C adds r3, r5, #1 + 1742 0016 F9D0 beq .L92 +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1743 .loc 1 1343 0 + 1744 0018 002D cmp r5, #0 + 1745 001a 04D0 beq .L93 +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1746 .loc 1 1343 0 is_stmt 0 discriminator 1 + 1747 001c FFF7FEFF bl HAL_GetTick + 1748 .LVL191: + 1749 0020 801B subs r0, r0, r6 + 1750 0022 A842 cmp r0, r5 + 1751 0024 F2D9 bls .L92 + 1752 .L93: +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return HAL_TIMEOUT; + 1753 .loc 1 1345 0 is_stmt 1 + 1754 0026 2123 movs r3, #33 + 1755 0028 0322 movs r2, #3 + 1756 002a E254 strb r2, [r4, r3] + ARM GAS /tmp/ccjtTCRz.s page 63 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1757 .loc 1 1346 0 + 1758 002c 0320 movs r0, #3 + 1759 002e 09E0 b .L94 + 1760 .L96: +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1761 .loc 1 1352 0 + 1762 0030 D968 ldr r1, [r3, #12] + 1763 0032 FF22 movs r2, #255 + 1764 0034 1140 ands r1, r2 + 1765 0036 044A ldr r2, .L97 + 1766 0038 0A43 orrs r2, r1 + 1767 003a DA60 str r2, [r3, #12] +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1768 .loc 1 1355 0 + 1769 003c 2123 movs r3, #33 + 1770 003e 0122 movs r2, #1 + 1771 0040 E254 strb r2, [r4, r3] +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1772 .loc 1 1357 0 + 1773 0042 0020 movs r0, #0 + 1774 .L94: +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1775 .loc 1 1358 0 + 1776 @ sp needed + 1777 .LVL192: + 1778 .LVL193: + 1779 .LVL194: + 1780 0044 70BD pop {r4, r5, r6, pc} + 1781 .L98: + 1782 0046 C046 .align 2 + 1783 .L97: + 1784 0048 7FFEFFFF .word -385 + 1785 .cfi_endproc + 1786 .LFE53: + 1788 .section .text.HAL_RTC_WaitForSynchro,"ax",%progbits + 1789 .align 1 + 1790 .global HAL_RTC_WaitForSynchro + 1791 .syntax unified + 1792 .code 16 + 1793 .thumb_func + 1794 .fpu softvfp + 1796 HAL_RTC_WaitForSynchro: + 1797 .LFB54: +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 1798 .loc 1 1394 0 + 1799 .cfi_startproc + 1800 @ args = 0, pretend = 0, frame = 0 + 1801 @ frame_needed = 0, uses_anonymous_args = 0 + 1802 .LVL195: + 1803 0000 70B5 push {r4, r5, r6, lr} + 1804 .LCFI8: + 1805 .cfi_def_cfa_offset 16 + 1806 .cfi_offset 4, -16 + 1807 .cfi_offset 5, -12 + 1808 .cfi_offset 6, -8 + 1809 .cfi_offset 14, -4 + ARM GAS /tmp/ccjtTCRz.s page 64 + + + 1810 0002 0400 movs r4, r0 + 1811 .LVL196: +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1812 .loc 1 1398 0 + 1813 0004 0268 ldr r2, [r0] + 1814 0006 D368 ldr r3, [r2, #12] + 1815 0008 A021 movs r1, #160 + 1816 000a 8B43 bics r3, r1 + 1817 000c D360 str r3, [r2, #12] +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1818 .loc 1 1400 0 + 1819 000e FFF7FEFF bl HAL_GetTick + 1820 .LVL197: + 1821 0012 0500 movs r5, r0 + 1822 .LVL198: + 1823 .L100: +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1824 .loc 1 1403 0 + 1825 0014 2368 ldr r3, [r4] + 1826 0016 DB68 ldr r3, [r3, #12] + 1827 0018 9B06 lsls r3, r3, #26 + 1828 001a 08D4 bmi .L104 +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1829 .loc 1 1405 0 + 1830 001c FFF7FEFF bl HAL_GetTick + 1831 .LVL199: + 1832 0020 401B subs r0, r0, r5 + 1833 0022 FA23 movs r3, #250 + 1834 0024 9B00 lsls r3, r3, #2 + 1835 0026 9842 cmp r0, r3 + 1836 0028 F4D9 bls .L100 +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1837 .loc 1 1407 0 + 1838 002a 0320 movs r0, #3 + 1839 002c 00E0 b .L101 + 1840 .L104: +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1841 .loc 1 1411 0 + 1842 002e 0020 movs r0, #0 + 1843 .L101: +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1844 .loc 1 1412 0 + 1845 @ sp needed + 1846 .LVL200: + 1847 .LVL201: + 1848 0030 70BD pop {r4, r5, r6, pc} + 1849 .cfi_endproc + 1850 .LFE54: + 1852 .section .text.HAL_RTC_GetState,"ax",%progbits + 1853 .align 1 + 1854 .global HAL_RTC_GetState + 1855 .syntax unified + 1856 .code 16 + 1857 .thumb_func + 1858 .fpu softvfp + 1860 HAL_RTC_GetState: + 1861 .LFB55: + ARM GAS /tmp/ccjtTCRz.s page 65 + + +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Return RTC handle state */ + 1862 .loc 1 1438 0 + 1863 .cfi_startproc + 1864 @ args = 0, pretend = 0, frame = 0 + 1865 @ frame_needed = 0, uses_anonymous_args = 0 + 1866 @ link register save eliminated. + 1867 .LVL202: +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1868 .loc 1 1440 0 + 1869 0000 2123 movs r3, #33 + 1870 0002 C05C ldrb r0, [r0, r3] + 1871 .LVL203: + 1872 0004 C0B2 uxtb r0, r0 +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1873 .loc 1 1441 0 + 1874 @ sp needed + 1875 0006 7047 bx lr + 1876 .cfi_endproc + 1877 .LFE55: + 1879 .section .text.RTC_EnterInitMode,"ax",%progbits + 1880 .align 1 + 1881 .global RTC_EnterInitMode + 1882 .syntax unified + 1883 .code 16 + 1884 .thumb_func + 1885 .fpu softvfp + 1887 RTC_EnterInitMode: + 1888 .LFB56: +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 1889 .loc 1 1461 0 + 1890 .cfi_startproc + 1891 @ args = 0, pretend = 0, frame = 0 + 1892 @ frame_needed = 0, uses_anonymous_args = 0 + 1893 .LVL204: + 1894 0000 70B5 push {r4, r5, r6, lr} + 1895 .LCFI9: + 1896 .cfi_def_cfa_offset 16 + 1897 .cfi_offset 4, -16 + 1898 .cfi_offset 5, -12 + 1899 .cfi_offset 6, -8 + 1900 .cfi_offset 14, -4 + 1901 0002 0400 movs r4, r0 + 1902 .LVL205: +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1903 .loc 1 1465 0 + 1904 0004 0368 ldr r3, [r0] + 1905 0006 DA68 ldr r2, [r3, #12] + 1906 0008 5206 lsls r2, r2, #25 + 1907 000a 01D5 bpl .L112 +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1908 .loc 1 1481 0 + 1909 000c 0020 movs r0, #0 + 1910 .LVL206: + 1911 .L107: +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1912 .loc 1 1482 0 + 1913 @ sp needed + ARM GAS /tmp/ccjtTCRz.s page 66 + + + 1914 .LVL207: + 1915 000e 70BD pop {r4, r5, r6, pc} + 1916 .LVL208: + 1917 .L112: +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1918 .loc 1 1468 0 + 1919 0010 0122 movs r2, #1 + 1920 0012 5242 rsbs r2, r2, #0 + 1921 0014 DA60 str r2, [r3, #12] +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Wait till RTC is in INIT state and if Time out is reached exit */ + 1922 .loc 1 1470 0 + 1923 0016 FFF7FEFF bl HAL_GetTick + 1924 .LVL209: + 1925 001a 0500 movs r5, r0 + 1926 .LVL210: + 1927 .L108: +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1928 .loc 1 1472 0 + 1929 001c 2368 ldr r3, [r4] + 1930 001e DB68 ldr r3, [r3, #12] + 1931 0020 5B06 lsls r3, r3, #25 + 1932 0022 08D4 bmi .L113 +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1933 .loc 1 1474 0 + 1934 0024 FFF7FEFF bl HAL_GetTick + 1935 .LVL211: + 1936 0028 401B subs r0, r0, r5 + 1937 002a FA23 movs r3, #250 + 1938 002c 9B00 lsls r3, r3, #2 + 1939 002e 9842 cmp r0, r3 + 1940 0030 F4D9 bls .L108 +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1941 .loc 1 1476 0 + 1942 0032 0320 movs r0, #3 + 1943 0034 EBE7 b .L107 + 1944 .L113: +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 1945 .loc 1 1481 0 + 1946 0036 0020 movs r0, #0 + 1947 0038 E9E7 b .L107 + 1948 .cfi_endproc + 1949 .LFE56: + 1951 .section .text.HAL_RTC_Init,"ax",%progbits + 1952 .align 1 + 1953 .global HAL_RTC_Init + 1954 .syntax unified + 1955 .code 16 + 1956 .thumb_func + 1957 .fpu softvfp + 1959 HAL_RTC_Init: + 1960 .LFB39: + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Check the RTC peripheral state */ + 1961 .loc 1 177 0 + 1962 .cfi_startproc + 1963 @ args = 0, pretend = 0, frame = 0 + 1964 @ frame_needed = 0, uses_anonymous_args = 0 + 1965 .LVL212: + ARM GAS /tmp/ccjtTCRz.s page 67 + + + 1966 0000 70B5 push {r4, r5, r6, lr} + 1967 .LCFI10: + 1968 .cfi_def_cfa_offset 16 + 1969 .cfi_offset 4, -16 + 1970 .cfi_offset 5, -12 + 1971 .cfi_offset 6, -8 + 1972 .cfi_offset 14, -4 + 1973 0002 041E subs r4, r0, #0 + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1974 .loc 1 179 0 + 1975 0004 4ED0 beq .L118 + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1976 .loc 1 194 0 + 1977 0006 2123 movs r3, #33 + 1978 0008 C35C ldrb r3, [r0, r3] + 1979 000a 002B cmp r3, #0 + 1980 000c 3CD0 beq .L119 + 1981 .LVL213: + 1982 .L116: + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1983 .loc 1 204 0 + 1984 000e 2123 movs r3, #33 + 1985 0010 0222 movs r2, #2 + 1986 0012 E254 strb r2, [r4, r3] + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 1987 .loc 1 207 0 + 1988 0014 2368 ldr r3, [r4] + 1989 0016 C832 adds r2, r2, #200 + 1990 0018 5A62 str r2, [r3, #36] + 1991 001a 2368 ldr r3, [r4] + 1992 001c 773A subs r2, r2, #119 + 1993 001e 5A62 str r2, [r3, #36] + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 1994 .loc 1 210 0 + 1995 0020 2000 movs r0, r4 + 1996 0022 FFF7FEFF bl RTC_EnterInitMode + 1997 .LVL214: + 1998 0026 0028 cmp r0, #0 + 1999 0028 34D1 bne .L120 + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Set RTC_CR register */ + 2000 .loc 1 223 0 + 2001 002a 2268 ldr r2, [r4] + 2002 002c 9368 ldr r3, [r2, #8] + 2003 002e 1E49 ldr r1, .L121 + 2004 0030 0B40 ands r3, r1 + 2005 0032 9360 str r3, [r2, #8] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2006 .loc 1 225 0 + 2007 0034 2168 ldr r1, [r4] + 2008 0036 8A68 ldr r2, [r1, #8] + 2009 0038 6368 ldr r3, [r4, #4] + 2010 003a 2569 ldr r5, [r4, #16] + 2011 003c 2B43 orrs r3, r5 + 2012 003e A569 ldr r5, [r4, #24] + 2013 0040 2B43 orrs r3, r5 + 2014 0042 1343 orrs r3, r2 + 2015 0044 8B60 str r3, [r1, #8] + ARM GAS /tmp/ccjtTCRz.s page 68 + + + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); + 2016 .loc 1 228 0 + 2017 0046 2368 ldr r3, [r4] + 2018 0048 E268 ldr r2, [r4, #12] + 2019 004a 1A61 str r2, [r3, #16] + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2020 .loc 1 229 0 + 2021 004c 2168 ldr r1, [r4] + 2022 004e 0B69 ldr r3, [r1, #16] + 2023 0050 A268 ldr r2, [r4, #8] + 2024 0052 1204 lsls r2, r2, #16 + 2025 0054 1343 orrs r3, r2 + 2026 0056 0B61 str r3, [r1, #16] + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2027 .loc 1 232 0 + 2028 0058 2268 ldr r2, [r4] + 2029 005a D368 ldr r3, [r2, #12] + 2030 005c 8021 movs r1, #128 + 2031 005e 8B43 bics r3, r1 + 2032 0060 D360 str r3, [r2, #12] + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + 2033 .loc 1 234 0 + 2034 0062 2268 ldr r2, [r4] + 2035 0064 D36C ldr r3, [r2, #76] + 2036 0066 7D39 subs r1, r1, #125 + 2037 0068 8B43 bics r3, r1 + 2038 006a D364 str r3, [r2, #76] + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2039 .loc 1 235 0 + 2040 006c 2168 ldr r1, [r4] + 2041 006e CB6C ldr r3, [r1, #76] + 2042 0070 E269 ldr r2, [r4, #28] + 2043 0072 6569 ldr r5, [r4, #20] + 2044 0074 2A43 orrs r2, r5 + 2045 0076 1343 orrs r3, r2 + 2046 0078 CB64 str r3, [r1, #76] + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2047 .loc 1 238 0 + 2048 007a 2368 ldr r3, [r4] + 2049 007c FF22 movs r2, #255 + 2050 007e 5A62 str r2, [r3, #36] + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2051 .loc 1 241 0 + 2052 0080 2123 movs r3, #33 + 2053 0082 FE3A subs r2, r2, #254 + 2054 0084 E254 strb r2, [r4, r3] + 2055 .L115: + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2056 .loc 1 245 0 + 2057 @ sp needed + 2058 .LVL215: + 2059 0086 70BD pop {r4, r5, r6, pc} + 2060 .LVL216: + 2061 .L119: + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2062 .loc 1 197 0 + 2063 0088 2033 adds r3, r3, #32 + ARM GAS /tmp/ccjtTCRz.s page 69 + + + 2064 008a 0022 movs r2, #0 + 2065 008c C254 strb r2, [r0, r3] + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2066 .loc 1 200 0 + 2067 008e FFF7FEFF bl HAL_RTC_MspInit + 2068 .LVL217: + 2069 0092 BCE7 b .L116 + 2070 .L120: + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2071 .loc 1 213 0 + 2072 0094 2368 ldr r3, [r4] + 2073 0096 FF22 movs r2, #255 + 2074 0098 5A62 str r2, [r3, #36] + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2075 .loc 1 216 0 + 2076 009a 2123 movs r3, #33 + 2077 009c FB3A subs r2, r2, #251 + 2078 009e E254 strb r2, [r4, r3] + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2079 .loc 1 218 0 + 2080 00a0 0120 movs r0, #1 + 2081 00a2 F0E7 b .L115 + 2082 .LVL218: + 2083 .L118: + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2084 .loc 1 181 0 + 2085 00a4 0120 movs r0, #1 + 2086 .LVL219: + 2087 00a6 EEE7 b .L115 + 2088 .L122: + 2089 .align 2 + 2090 .L121: + 2091 00a8 BFFF8FFF .word -7340097 + 2092 .cfi_endproc + 2093 .LFE39: + 2095 .section .text.HAL_RTC_DeInit,"ax",%progbits + 2096 .align 1 + 2097 .global HAL_RTC_DeInit + 2098 .syntax unified + 2099 .code 16 + 2100 .thumb_func + 2101 .fpu softvfp + 2103 HAL_RTC_DeInit: + 2104 .LFB40: + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tickstart = 0U; + 2105 .loc 1 254 0 + 2106 .cfi_startproc + 2107 @ args = 0, pretend = 0, frame = 0 + 2108 @ frame_needed = 0, uses_anonymous_args = 0 + 2109 .LVL220: + 2110 0000 70B5 push {r4, r5, r6, lr} + 2111 .LCFI11: + 2112 .cfi_def_cfa_offset 16 + 2113 .cfi_offset 4, -16 + 2114 .cfi_offset 5, -12 + 2115 .cfi_offset 6, -8 + 2116 .cfi_offset 14, -4 + ARM GAS /tmp/ccjtTCRz.s page 70 + + + 2117 0002 0400 movs r4, r0 + 2118 .LVL221: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2119 .loc 1 261 0 + 2120 0004 2123 movs r3, #33 + 2121 0006 0222 movs r2, #2 + 2122 0008 C254 strb r2, [r0, r3] + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2123 .loc 1 264 0 + 2124 000a 0368 ldr r3, [r0] + 2125 000c C832 adds r2, r2, #200 + 2126 000e 5A62 str r2, [r3, #36] + 2127 0010 0368 ldr r3, [r0] + 2128 0012 773A subs r2, r2, #119 + 2129 0014 5A62 str r2, [r3, #36] + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2130 .loc 1 267 0 + 2131 0016 FFF7FEFF bl RTC_EnterInitMode + 2132 .LVL222: + 2133 001a 051E subs r5, r0, #0 + 2134 001c 08D0 beq .L124 + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2135 .loc 1 270 0 + 2136 001e 2368 ldr r3, [r4] + 2137 0020 FF22 movs r2, #255 + 2138 0022 5A62 str r2, [r3, #36] + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2139 .loc 1 273 0 + 2140 0024 2123 movs r3, #33 + 2141 0026 FB3A subs r2, r2, #251 + 2142 0028 E254 strb r2, [r4, r3] + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2143 .loc 1 275 0 + 2144 002a 0125 movs r5, #1 + 2145 .LVL223: + 2146 .L125: + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2147 .loc 1 349 0 + 2148 002c 2800 movs r0, r5 + 2149 @ sp needed + 2150 .LVL224: + 2151 002e 70BD pop {r4, r5, r6, pc} + 2152 .LVL225: + 2153 .L124: + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + 2154 .loc 1 280 0 + 2155 0030 2368 ldr r3, [r4] + 2156 0032 0022 movs r2, #0 + 2157 0034 1A60 str r2, [r3] + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** /* Reset All CR bits except CR[2:0] */ + 2158 .loc 1 281 0 + 2159 0036 2368 ldr r3, [r4] + 2160 0038 2A4A ldr r2, .L131 + 2161 003a 5A60 str r2, [r3, #4] + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2162 .loc 1 283 0 + 2163 003c 2268 ldr r2, [r4] + ARM GAS /tmp/ccjtTCRz.s page 71 + + + 2164 003e 9168 ldr r1, [r2, #8] + 2165 0040 0723 movs r3, #7 + 2166 0042 0B40 ands r3, r1 + 2167 0044 9360 str r3, [r2, #8] + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2168 .loc 1 285 0 + 2169 0046 FFF7FEFF bl HAL_GetTick + 2170 .LVL226: + 2171 004a 0600 movs r6, r0 + 2172 .LVL227: + 2173 .L126: + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2174 .loc 1 288 0 + 2175 004c 2368 ldr r3, [r4] + 2176 004e DA68 ldr r2, [r3, #12] + 2177 0050 5207 lsls r2, r2, #29 + 2178 0052 0ED4 bmi .L129 + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2179 .loc 1 290 0 + 2180 0054 FFF7FEFF bl HAL_GetTick + 2181 .LVL228: + 2182 0058 801B subs r0, r0, r6 + 2183 005a FA23 movs r3, #250 + 2184 005c 9B00 lsls r3, r3, #2 + 2185 005e 9842 cmp r0, r3 + 2186 0060 F4D9 bls .L126 + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2187 .loc 1 293 0 + 2188 0062 2368 ldr r3, [r4] + 2189 0064 FF22 movs r2, #255 + 2190 0066 5A62 str r2, [r3, #36] + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2191 .loc 1 296 0 + 2192 0068 2123 movs r3, #33 + 2193 006a FC3A subs r2, r2, #252 + 2194 006c E254 strb r2, [r4, r3] + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2195 .loc 1 298 0 + 2196 006e 0325 movs r5, #3 + 2197 0070 DCE7 b .L125 + 2198 .L129: + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->WUTR = RTC_WUTR_WUT; + 2199 .loc 1 303 0 + 2200 0072 9A68 ldr r2, [r3, #8] + 2201 0074 0022 movs r2, #0 + 2202 0076 9A60 str r2, [r3, #8] + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + 2203 .loc 1 304 0 + 2204 0078 2368 ldr r3, [r4] + 2205 007a 1B49 ldr r1, .L131+4 + 2206 007c 5961 str r1, [r3, #20] + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMAR = (uint32_t)0x00000000U; + 2207 .loc 1 305 0 + 2208 007e 2368 ldr r3, [r4] + 2209 0080 1A49 ldr r1, .L131+8 + 2210 0082 1961 str r1, [r3, #16] + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBR = (uint32_t)0x00000000U; + ARM GAS /tmp/ccjtTCRz.s page 72 + + + 2211 .loc 1 306 0 + 2212 0084 2368 ldr r3, [r4] + 2213 0086 DA61 str r2, [r3, #28] + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->SHIFTR = (uint32_t)0x00000000U; + 2214 .loc 1 307 0 + 2215 0088 2368 ldr r3, [r4] + 2216 008a 1A62 str r2, [r3, #32] + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->CALR = (uint32_t)0x00000000U; + 2217 .loc 1 308 0 + 2218 008c 2368 ldr r3, [r4] + 2219 008e DA62 str r2, [r3, #44] + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U; + 2220 .loc 1 309 0 + 2221 0090 2368 ldr r3, [r4] + 2222 0092 DA63 str r2, [r3, #60] + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U; + 2223 .loc 1 310 0 + 2224 0094 2368 ldr r3, [r4] + 2225 0096 5A64 str r2, [r3, #68] + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2226 .loc 1 311 0 + 2227 0098 2368 ldr r3, [r4] + 2228 009a 9A64 str r2, [r3, #72] + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2229 .loc 1 314 0 + 2230 009c 2368 ldr r3, [r4] + 2231 009e DA60 str r2, [r3, #12] + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2232 .loc 1 317 0 + 2233 00a0 2368 ldr r3, [r4] + 2234 00a2 1A64 str r2, [r3, #64] + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2235 .loc 1 320 0 + 2236 00a4 2368 ldr r3, [r4] + 2237 00a6 DA64 str r2, [r3, #76] + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2238 .loc 1 323 0 + 2239 00a8 2368 ldr r3, [r4] + 2240 00aa 9B68 ldr r3, [r3, #8] + 2241 00ac 9B06 lsls r3, r3, #26 + 2242 00ae 04D4 bmi .L128 + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2243 .loc 1 325 0 + 2244 00b0 2000 movs r0, r4 + 2245 00b2 FFF7FEFF bl HAL_RTC_WaitForSynchro + 2246 .LVL229: + 2247 00b6 0028 cmp r0, #0 + 2248 00b8 0BD1 bne .L130 + 2249 .L128: + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2250 .loc 1 338 0 + 2251 00ba 2368 ldr r3, [r4] + 2252 00bc FF22 movs r2, #255 + 2253 00be 5A62 str r2, [r3, #36] + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2254 .loc 1 341 0 + 2255 00c0 2000 movs r0, r4 + ARM GAS /tmp/ccjtTCRz.s page 73 + + + 2256 00c2 FFF7FEFF bl HAL_RTC_MspDeInit + 2257 .LVL230: + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2258 .loc 1 343 0 + 2259 00c6 0023 movs r3, #0 + 2260 00c8 2122 movs r2, #33 + 2261 00ca A354 strb r3, [r4, r2] + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2262 .loc 1 346 0 + 2263 00cc 013A subs r2, r2, #1 + 2264 00ce A354 strb r3, [r4, r2] + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2265 .loc 1 348 0 + 2266 00d0 ACE7 b .L125 + 2267 .L130: + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2268 .loc 1 328 0 + 2269 00d2 2368 ldr r3, [r4] + 2270 00d4 FF22 movs r2, #255 + 2271 00d6 5A62 str r2, [r3, #36] + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2272 .loc 1 330 0 + 2273 00d8 2123 movs r3, #33 + 2274 00da FB3A subs r2, r2, #251 + 2275 00dc E254 strb r2, [r4, r3] + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2276 .loc 1 332 0 + 2277 00de 0125 movs r5, #1 + 2278 00e0 A4E7 b .L125 + 2279 .L132: + 2280 00e2 C046 .align 2 + 2281 .L131: + 2282 00e4 01210000 .word 8449 + 2283 00e8 FFFF0000 .word 65535 + 2284 00ec FF007F00 .word 8323327 + 2285 .cfi_endproc + 2286 .LFE40: + 2288 .section .text.HAL_RTC_SetTime,"ax",%progbits + 2289 .align 1 + 2290 .global HAL_RTC_SetTime + 2291 .syntax unified + 2292 .code 16 + 2293 .thumb_func + 2294 .fpu softvfp + 2296 HAL_RTC_SetTime: + 2297 .LFB43: + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmpreg = 0U; + 2298 .loc 1 410 0 + 2299 .cfi_startproc + 2300 @ args = 0, pretend = 0, frame = 0 + 2301 @ frame_needed = 0, uses_anonymous_args = 0 + 2302 .LVL231: + 2303 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 2304 .LCFI12: + 2305 .cfi_def_cfa_offset 24 + 2306 .cfi_offset 3, -24 + 2307 .cfi_offset 4, -20 + ARM GAS /tmp/ccjtTCRz.s page 74 + + + 2308 .cfi_offset 5, -16 + 2309 .cfi_offset 6, -12 + 2310 .cfi_offset 7, -8 + 2311 .cfi_offset 14, -4 + 2312 0002 0500 movs r5, r0 + 2313 0004 0E00 movs r6, r1 + 2314 .LVL232: + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2315 .loc 1 419 0 + 2316 0006 2023 movs r3, #32 + 2317 0008 C35C ldrb r3, [r0, r3] + 2318 000a 012B cmp r3, #1 + 2319 000c 00D1 bne .LCB2264 + 2320 000e 8FE0 b .L147 @long jump + 2321 .LCB2264: + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2322 .loc 1 419 0 is_stmt 0 discriminator 2 + 2323 0010 2023 movs r3, #32 + 2324 0012 0121 movs r1, #1 + 2325 .LVL233: + 2326 0014 C154 strb r1, [r0, r3] + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2327 .loc 1 421 0 is_stmt 1 discriminator 2 + 2328 0016 0133 adds r3, r3, #1 + 2329 0018 0131 adds r1, r1, #1 + 2330 001a C154 strb r1, [r0, r3] + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2331 .loc 1 423 0 discriminator 2 + 2332 001c 002A cmp r2, #0 + 2333 001e 5AD1 bne .L135 + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2334 .loc 1 425 0 + 2335 0020 0368 ldr r3, [r0] + 2336 0022 9B68 ldr r3, [r3, #8] + 2337 0024 5B06 lsls r3, r3, #25 + 2338 0026 01D4 bmi .L136 + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(sTime->Hours)); + 2339 .loc 1 432 0 + 2340 0028 0023 movs r3, #0 + 2341 002a F370 strb r3, [r6, #3] + 2342 .L136: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ + 2343 .loc 1 438 0 + 2344 002c 3378 ldrb r3, [r6] + 2345 .LVL234: + 2346 .LBB104: + 2347 .LBB105: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2348 .loc 1 1492 0 + 2349 002e 1400 movs r4, r2 + 2350 0030 02E0 b .L137 + 2351 .LVL235: + 2352 .L138: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2353 .loc 1 1496 0 + 2354 0032 0134 adds r4, r4, #1 + 2355 .LVL236: + ARM GAS /tmp/ccjtTCRz.s page 75 + + +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2356 .loc 1 1497 0 + 2357 0034 0A3B subs r3, r3, #10 + 2358 .LVL237: + 2359 0036 DBB2 uxtb r3, r3 + 2360 .LVL238: + 2361 .L137: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2362 .loc 1 1494 0 + 2363 0038 092B cmp r3, #9 + 2364 003a FAD8 bhi .L138 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2365 .loc 1 1500 0 + 2366 003c 2401 lsls r4, r4, #4 + 2367 .LVL239: + 2368 003e E4B2 uxtb r4, r4 + 2369 0040 2343 orrs r3, r4 + 2370 .LVL240: + 2371 .LBE105: + 2372 .LBE104: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ + 2373 .loc 1 438 0 + 2374 0042 1B04 lsls r3, r3, #16 + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 2375 .loc 1 439 0 + 2376 0044 7478 ldrb r4, [r6, #1] + 2377 .LVL241: + 2378 .LBB106: + 2379 .LBB107: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2380 .loc 1 1492 0 + 2381 0046 1100 movs r1, r2 + 2382 0048 02E0 b .L139 + 2383 .LVL242: + 2384 .L140: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2385 .loc 1 1496 0 + 2386 004a 0131 adds r1, r1, #1 + 2387 .LVL243: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2388 .loc 1 1497 0 + 2389 004c 0A3C subs r4, r4, #10 + 2390 .LVL244: + 2391 004e E4B2 uxtb r4, r4 + 2392 .LVL245: + 2393 .L139: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2394 .loc 1 1494 0 + 2395 0050 092C cmp r4, #9 + 2396 0052 FAD8 bhi .L140 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2397 .loc 1 1500 0 + 2398 0054 0901 lsls r1, r1, #4 + 2399 .LVL246: + 2400 0056 C9B2 uxtb r1, r1 + 2401 0058 0C43 orrs r4, r1 + 2402 .LVL247: + ARM GAS /tmp/ccjtTCRz.s page 76 + + + 2403 .LBE107: + 2404 .LBE106: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 2405 .loc 1 439 0 + 2406 005a 2402 lsls r4, r4, #8 + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ + 2407 .loc 1 438 0 + 2408 005c 2343 orrs r3, r4 + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sTime->TimeFormat) << 16U)); + 2409 .loc 1 440 0 + 2410 005e B478 ldrb r4, [r6, #2] + 2411 .LVL248: + 2412 0060 02E0 b .L141 + 2413 .LVL249: + 2414 .L142: + 2415 .LBB108: + 2416 .LBB109: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2417 .loc 1 1496 0 + 2418 0062 0132 adds r2, r2, #1 + 2419 .LVL250: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2420 .loc 1 1497 0 + 2421 0064 0A3C subs r4, r4, #10 + 2422 .LVL251: + 2423 0066 E4B2 uxtb r4, r4 + 2424 .LVL252: + 2425 .L141: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2426 .loc 1 1494 0 + 2427 0068 092C cmp r4, #9 + 2428 006a FAD8 bhi .L142 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2429 .loc 1 1500 0 + 2430 006c 1201 lsls r2, r2, #4 + 2431 .LVL253: + 2432 006e D2B2 uxtb r2, r2 + 2433 0070 1443 orrs r4, r2 + 2434 .LVL254: + 2435 .LBE109: + 2436 .LBE108: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 2437 .loc 1 439 0 + 2438 0072 1C43 orrs r4, r3 + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2439 .loc 1 441 0 + 2440 0074 F378 ldrb r3, [r6, #3] + 2441 0076 1B04 lsls r3, r3, #16 + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ + 2442 .loc 1 438 0 + 2443 0078 1C43 orrs r4, r3 + 2444 .LVL255: + 2445 .L143: + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2446 .loc 1 465 0 + 2447 007a 2B68 ldr r3, [r5] + 2448 007c CA22 movs r2, #202 + ARM GAS /tmp/ccjtTCRz.s page 77 + + + 2449 007e 5A62 str r2, [r3, #36] + 2450 0080 2B68 ldr r3, [r5] + 2451 0082 773A subs r2, r2, #119 + 2452 0084 5A62 str r2, [r3, #36] + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2453 .loc 1 468 0 + 2454 0086 2800 movs r0, r5 + 2455 .LVL256: + 2456 0088 FFF7FEFF bl RTC_EnterInitMode + 2457 .LVL257: + 2458 008c 071E subs r7, r0, #0 + 2459 008e 33D1 bne .L148 + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2460 .loc 1 484 0 + 2461 0090 2B68 ldr r3, [r5] + 2462 0092 284A ldr r2, .L150 + 2463 0094 1440 ands r4, r2 + 2464 .LVL258: + 2465 0096 1C60 str r4, [r3] + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2466 .loc 1 487 0 + 2467 0098 2A68 ldr r2, [r5] + 2468 009a 9368 ldr r3, [r2, #8] + 2469 009c 2649 ldr r1, .L150+4 + 2470 009e 0B40 ands r3, r1 + 2471 00a0 9360 str r3, [r2, #8] + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2472 .loc 1 490 0 + 2473 00a2 2968 ldr r1, [r5] + 2474 00a4 8B68 ldr r3, [r1, #8] + 2475 00a6 F268 ldr r2, [r6, #12] + 2476 00a8 3069 ldr r0, [r6, #16] + 2477 00aa 0243 orrs r2, r0 + 2478 00ac 1343 orrs r3, r2 + 2479 00ae 8B60 str r3, [r1, #8] + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2480 .loc 1 493 0 + 2481 00b0 2A68 ldr r2, [r5] + 2482 00b2 D368 ldr r3, [r2, #12] + 2483 00b4 8021 movs r1, #128 + 2484 00b6 8B43 bics r3, r1 + 2485 00b8 D360 str r3, [r2, #12] + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2486 .loc 1 496 0 + 2487 00ba 2B68 ldr r3, [r5] + 2488 00bc 9B68 ldr r3, [r3, #8] + 2489 00be 9B06 lsls r3, r3, #26 + 2490 00c0 26D5 bpl .L149 + 2491 .L146: + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2492 .loc 1 513 0 + 2493 00c2 2B68 ldr r3, [r5] + 2494 00c4 FF22 movs r2, #255 + 2495 00c6 5A62 str r2, [r3, #36] + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2496 .loc 1 515 0 + 2497 00c8 2123 movs r3, #33 + ARM GAS /tmp/ccjtTCRz.s page 78 + + + 2498 00ca FE3A subs r2, r2, #254 + 2499 00cc EA54 strb r2, [r5, r3] + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2500 .loc 1 517 0 + 2501 00ce 013B subs r3, r3, #1 + 2502 00d0 0022 movs r2, #0 + 2503 00d2 EA54 strb r2, [r5, r3] + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2504 .loc 1 519 0 + 2505 00d4 1AE0 b .L134 + 2506 .LVL259: + 2507 .L135: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2508 .loc 1 445 0 + 2509 00d6 0368 ldr r3, [r0] + 2510 00d8 9B68 ldr r3, [r3, #8] + 2511 00da 5B06 lsls r3, r3, #25 + 2512 00dc 01D4 bmi .L144 + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + 2513 .loc 1 453 0 + 2514 00de 0023 movs r3, #0 + 2515 00e0 F370 strb r3, [r6, #3] + 2516 .L144: + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->Minutes) << 8U) | \ + 2517 .loc 1 458 0 + 2518 00e2 3478 ldrb r4, [r6] + 2519 00e4 2404 lsls r4, r4, #16 + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sTime->Seconds) | \ + 2520 .loc 1 459 0 + 2521 00e6 7378 ldrb r3, [r6, #1] + 2522 00e8 1B02 lsls r3, r3, #8 + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->Minutes) << 8U) | \ + 2523 .loc 1 458 0 + 2524 00ea 1C43 orrs r4, r3 + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->TimeFormat) << 16U)); + 2525 .loc 1 460 0 + 2526 00ec B378 ldrb r3, [r6, #2] + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sTime->Seconds) | \ + 2527 .loc 1 459 0 + 2528 00ee 1C43 orrs r4, r3 + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2529 .loc 1 461 0 + 2530 00f0 F378 ldrb r3, [r6, #3] + 2531 00f2 1B04 lsls r3, r3, #16 + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)(sTime->Minutes) << 8U) | \ + 2532 .loc 1 458 0 + 2533 00f4 1C43 orrs r4, r3 + 2534 .LVL260: + 2535 00f6 C0E7 b .L143 + 2536 .LVL261: + 2537 .L148: + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2538 .loc 1 471 0 + 2539 00f8 2B68 ldr r3, [r5] + 2540 00fa FF22 movs r2, #255 + 2541 00fc 5A62 str r2, [r3, #36] + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 79 + + + 2542 .loc 1 474 0 + 2543 00fe 2123 movs r3, #33 + 2544 0100 FB3A subs r2, r2, #251 + 2545 0102 EA54 strb r2, [r5, r3] + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2546 .loc 1 477 0 + 2547 0104 013B subs r3, r3, #1 + 2548 0106 0022 movs r2, #0 + 2549 0108 EA54 strb r2, [r5, r3] + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2550 .loc 1 479 0 + 2551 010a 0127 movs r7, #1 + 2552 .LVL262: + 2553 .L134: + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2554 .loc 1 521 0 + 2555 010c 3800 movs r0, r7 + 2556 @ sp needed + 2557 .LVL263: + 2558 .LVL264: + 2559 010e F8BD pop {r3, r4, r5, r6, r7, pc} + 2560 .LVL265: + 2561 .L149: + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2562 .loc 1 498 0 + 2563 0110 2800 movs r0, r5 + 2564 0112 FFF7FEFF bl HAL_RTC_WaitForSynchro + 2565 .LVL266: + 2566 0116 0028 cmp r0, #0 + 2567 0118 D3D0 beq .L146 + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2568 .loc 1 501 0 + 2569 011a 2B68 ldr r3, [r5] + 2570 011c FF22 movs r2, #255 + 2571 011e 5A62 str r2, [r3, #36] + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2572 .loc 1 503 0 + 2573 0120 2123 movs r3, #33 + 2574 0122 FB3A subs r2, r2, #251 + 2575 0124 EA54 strb r2, [r5, r3] + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2576 .loc 1 506 0 + 2577 0126 013B subs r3, r3, #1 + 2578 0128 0022 movs r2, #0 + 2579 012a EA54 strb r2, [r5, r3] + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2580 .loc 1 508 0 + 2581 012c 0127 movs r7, #1 + 2582 012e EDE7 b .L134 + 2583 .LVL267: + 2584 .L147: + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2585 .loc 1 419 0 + 2586 0130 0227 movs r7, #2 + 2587 0132 EBE7 b .L134 + 2588 .L151: + 2589 .align 2 + ARM GAS /tmp/ccjtTCRz.s page 80 + + + 2590 .L150: + 2591 0134 7F7F7F00 .word 8355711 + 2592 0138 FFFFFBFF .word -262145 + 2593 .cfi_endproc + 2594 .LFE43: + 2596 .section .text.HAL_RTC_SetDate,"ax",%progbits + 2597 .align 1 + 2598 .global HAL_RTC_SetDate + 2599 .syntax unified + 2600 .code 16 + 2601 .thumb_func + 2602 .fpu softvfp + 2604 HAL_RTC_SetDate: + 2605 .LFB45: + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t datetmpreg = 0U; + 2606 .loc 1 589 0 + 2607 .cfi_startproc + 2608 @ args = 0, pretend = 0, frame = 0 + 2609 @ frame_needed = 0, uses_anonymous_args = 0 + 2610 .LVL268: + 2611 0000 70B5 push {r4, r5, r6, lr} + 2612 .LCFI13: + 2613 .cfi_def_cfa_offset 16 + 2614 .cfi_offset 4, -16 + 2615 .cfi_offset 5, -12 + 2616 .cfi_offset 6, -8 + 2617 .cfi_offset 14, -4 + 2618 0002 0500 movs r5, r0 + 2619 .LVL269: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2620 .loc 1 596 0 + 2621 0004 2023 movs r3, #32 + 2622 0006 C35C ldrb r3, [r0, r3] + 2623 0008 012B cmp r3, #1 + 2624 000a 00D1 bne .LCB2584 + 2625 000c 80E0 b .L165 @long jump + 2626 .LCB2584: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2627 .loc 1 596 0 is_stmt 0 discriminator 2 + 2628 000e 2023 movs r3, #32 + 2629 0010 0120 movs r0, #1 + 2630 .LVL270: + 2631 0012 E854 strb r0, [r5, r3] + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2632 .loc 1 598 0 is_stmt 1 discriminator 2 + 2633 0014 0133 adds r3, r3, #1 + 2634 0016 0130 adds r0, r0, #1 + 2635 0018 E854 strb r0, [r5, r3] + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2636 .loc 1 600 0 discriminator 2 + 2637 001a 002A cmp r2, #0 + 2638 001c 06D1 bne .L154 + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2639 .loc 1 600 0 is_stmt 0 discriminator 1 + 2640 001e 4B78 ldrb r3, [r1, #1] + 2641 0020 D806 lsls r0, r3, #27 + 2642 0022 03D5 bpl .L154 + ARM GAS /tmp/ccjtTCRz.s page 81 + + + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2643 .loc 1 602 0 is_stmt 1 + 2644 0024 1020 movs r0, #16 + 2645 0026 8343 bics r3, r0 + 2646 0028 0A33 adds r3, r3, #10 + 2647 002a 4B70 strb r3, [r1, #1] + 2648 .L154: + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2649 .loc 1 607 0 + 2650 002c 002A cmp r2, #0 + 2651 002e 48D1 bne .L155 + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 2652 .loc 1 613 0 + 2653 0030 CB78 ldrb r3, [r1, #3] + 2654 .LVL271: + 2655 .LBB110: + 2656 .LBB111: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2657 .loc 1 1492 0 + 2658 0032 1400 movs r4, r2 + 2659 0034 02E0 b .L156 + 2660 .LVL272: + 2661 .L157: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2662 .loc 1 1496 0 + 2663 0036 0134 adds r4, r4, #1 + 2664 .LVL273: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2665 .loc 1 1497 0 + 2666 0038 0A3B subs r3, r3, #10 + 2667 .LVL274: + 2668 003a DBB2 uxtb r3, r3 + 2669 .LVL275: + 2670 .L156: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2671 .loc 1 1494 0 + 2672 003c 092B cmp r3, #9 + 2673 003e FAD8 bhi .L157 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2674 .loc 1 1500 0 + 2675 0040 2401 lsls r4, r4, #4 + 2676 .LVL276: + 2677 0042 E4B2 uxtb r4, r4 + 2678 0044 2343 orrs r3, r4 + 2679 .LVL277: + 2680 .LBE111: + 2681 .LBE110: + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 2682 .loc 1 613 0 + 2683 0046 1B04 lsls r3, r3, #16 + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 2684 .loc 1 614 0 + 2685 0048 4C78 ldrb r4, [r1, #1] + 2686 .LVL278: + 2687 .LBB112: + 2688 .LBB113: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + ARM GAS /tmp/ccjtTCRz.s page 82 + + + 2689 .loc 1 1492 0 + 2690 004a 1000 movs r0, r2 + 2691 004c 02E0 b .L158 + 2692 .LVL279: + 2693 .L159: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2694 .loc 1 1496 0 + 2695 004e 0130 adds r0, r0, #1 + 2696 .LVL280: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2697 .loc 1 1497 0 + 2698 0050 0A3C subs r4, r4, #10 + 2699 .LVL281: + 2700 0052 E4B2 uxtb r4, r4 + 2701 .LVL282: + 2702 .L158: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2703 .loc 1 1494 0 + 2704 0054 092C cmp r4, #9 + 2705 0056 FAD8 bhi .L159 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2706 .loc 1 1500 0 + 2707 0058 0001 lsls r0, r0, #4 + 2708 .LVL283: + 2709 005a C0B2 uxtb r0, r0 + 2710 005c 0443 orrs r4, r0 + 2711 .LVL284: + 2712 .LBE113: + 2713 .LBE112: + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 2714 .loc 1 614 0 + 2715 005e 2402 lsls r4, r4, #8 + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 2716 .loc 1 613 0 + 2717 0060 2343 orrs r3, r4 + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sDate->WeekDay << 13U)); + 2718 .loc 1 615 0 + 2719 0062 8C78 ldrb r4, [r1, #2] + 2720 .LVL285: + 2721 0064 02E0 b .L160 + 2722 .LVL286: + 2723 .L161: + 2724 .LBB114: + 2725 .LBB115: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2726 .loc 1 1496 0 + 2727 0066 0132 adds r2, r2, #1 + 2728 .LVL287: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2729 .loc 1 1497 0 + 2730 0068 0A3C subs r4, r4, #10 + 2731 .LVL288: + 2732 006a E4B2 uxtb r4, r4 + 2733 .LVL289: + 2734 .L160: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2735 .loc 1 1494 0 + ARM GAS /tmp/ccjtTCRz.s page 83 + + + 2736 006c 092C cmp r4, #9 + 2737 006e FAD8 bhi .L161 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2738 .loc 1 1500 0 + 2739 0070 1201 lsls r2, r2, #4 + 2740 .LVL290: + 2741 0072 D2B2 uxtb r2, r2 + 2742 0074 1443 orrs r4, r2 + 2743 .LVL291: + 2744 .LBE115: + 2745 .LBE114: + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 2746 .loc 1 614 0 + 2747 0076 1C43 orrs r4, r3 + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2748 .loc 1 616 0 + 2749 0078 0B78 ldrb r3, [r1] + 2750 007a 5B03 lsls r3, r3, #13 + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 2751 .loc 1 613 0 + 2752 007c 1C43 orrs r4, r3 + 2753 .LVL292: + 2754 .L162: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2755 .loc 1 633 0 + 2756 007e 2B68 ldr r3, [r5] + 2757 0080 CA22 movs r2, #202 + 2758 0082 5A62 str r2, [r3, #36] + 2759 0084 2B68 ldr r3, [r5] + 2760 0086 773A subs r2, r2, #119 + 2761 0088 5A62 str r2, [r3, #36] + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2762 .loc 1 636 0 + 2763 008a 2800 movs r0, r5 + 2764 008c FFF7FEFF bl RTC_EnterInitMode + 2765 .LVL293: + 2766 0090 061E subs r6, r0, #0 + 2767 0092 21D1 bne .L166 + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2768 .loc 1 652 0 + 2769 0094 2B68 ldr r3, [r5] + 2770 0096 1F4A ldr r2, .L168 + 2771 0098 1440 ands r4, r2 + 2772 .LVL294: + 2773 009a 5C60 str r4, [r3, #4] + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2774 .loc 1 655 0 + 2775 009c 2A68 ldr r2, [r5] + 2776 009e D368 ldr r3, [r2, #12] + 2777 00a0 8021 movs r1, #128 + 2778 00a2 8B43 bics r3, r1 + 2779 00a4 D360 str r3, [r2, #12] + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2780 .loc 1 658 0 + 2781 00a6 2B68 ldr r3, [r5] + 2782 00a8 9B68 ldr r3, [r3, #8] + 2783 00aa 9B06 lsls r3, r3, #26 + ARM GAS /tmp/ccjtTCRz.s page 84 + + + 2784 00ac 20D5 bpl .L167 + 2785 .L164: + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2786 .loc 1 675 0 + 2787 00ae 2B68 ldr r3, [r5] + 2788 00b0 FF22 movs r2, #255 + 2789 00b2 5A62 str r2, [r3, #36] + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2790 .loc 1 677 0 + 2791 00b4 2123 movs r3, #33 + 2792 00b6 FE3A subs r2, r2, #254 + 2793 00b8 EA54 strb r2, [r5, r3] + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2794 .loc 1 680 0 + 2795 00ba 013B subs r3, r3, #1 + 2796 00bc 0022 movs r2, #0 + 2797 00be EA54 strb r2, [r5, r3] + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2798 .loc 1 682 0 + 2799 00c0 14E0 b .L153 + 2800 .LVL295: + 2801 .L155: + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_MONTH(datetmpreg)); + 2802 .loc 1 621 0 + 2803 00c2 4B78 ldrb r3, [r1, #1] + 2804 .LVL296: + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** assert_param(IS_RTC_DATE(datetmpreg)); + 2805 .loc 1 623 0 + 2806 00c4 8A78 ldrb r2, [r1, #2] + 2807 .LVL297: + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sDate->Month) << 8U) | \ + 2808 .loc 1 626 0 + 2809 00c6 CC78 ldrb r4, [r1, #3] + 2810 00c8 2404 lsls r4, r4, #16 + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sDate->Date) | \ + 2811 .loc 1 627 0 + 2812 00ca 1B02 lsls r3, r3, #8 + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sDate->Month) << 8U) | \ + 2813 .loc 1 626 0 + 2814 00cc 1C43 orrs r4, r3 + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** ((uint32_t)sDate->Date) | \ + 2815 .loc 1 627 0 + 2816 00ce 1443 orrs r4, r2 + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2817 .loc 1 629 0 + 2818 00d0 0B78 ldrb r3, [r1] + 2819 00d2 5B03 lsls r3, r3, #13 + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** (((uint32_t)sDate->Month) << 8U) | \ + 2820 .loc 1 626 0 + 2821 00d4 1C43 orrs r4, r3 + 2822 .LVL298: + 2823 00d6 D2E7 b .L162 + 2824 .LVL299: + 2825 .L166: + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2826 .loc 1 639 0 + 2827 00d8 2B68 ldr r3, [r5] + ARM GAS /tmp/ccjtTCRz.s page 85 + + + 2828 00da FF22 movs r2, #255 + 2829 00dc 5A62 str r2, [r3, #36] + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2830 .loc 1 642 0 + 2831 00de 2123 movs r3, #33 + 2832 00e0 FB3A subs r2, r2, #251 + 2833 00e2 EA54 strb r2, [r5, r3] + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2834 .loc 1 645 0 + 2835 00e4 013B subs r3, r3, #1 + 2836 00e6 0022 movs r2, #0 + 2837 00e8 EA54 strb r2, [r5, r3] + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2838 .loc 1 647 0 + 2839 00ea 0126 movs r6, #1 + 2840 .LVL300: + 2841 .L153: + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2842 .loc 1 684 0 + 2843 00ec 3000 movs r0, r6 + 2844 @ sp needed + 2845 .LVL301: + 2846 00ee 70BD pop {r4, r5, r6, pc} + 2847 .LVL302: + 2848 .L167: + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2849 .loc 1 660 0 + 2850 00f0 2800 movs r0, r5 + 2851 00f2 FFF7FEFF bl HAL_RTC_WaitForSynchro + 2852 .LVL303: + 2853 00f6 0028 cmp r0, #0 + 2854 00f8 D9D0 beq .L164 + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2855 .loc 1 663 0 + 2856 00fa 2B68 ldr r3, [r5] + 2857 00fc FF22 movs r2, #255 + 2858 00fe 5A62 str r2, [r3, #36] + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2859 .loc 1 665 0 + 2860 0100 2123 movs r3, #33 + 2861 0102 FB3A subs r2, r2, #251 + 2862 0104 EA54 strb r2, [r5, r3] + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2863 .loc 1 668 0 + 2864 0106 013B subs r3, r3, #1 + 2865 0108 0022 movs r2, #0 + 2866 010a EA54 strb r2, [r5, r3] + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2867 .loc 1 670 0 + 2868 010c 0126 movs r6, #1 + 2869 010e EDE7 b .L153 + 2870 .LVL304: + 2871 .L165: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2872 .loc 1 596 0 + 2873 0110 0226 movs r6, #2 + 2874 0112 EBE7 b .L153 + ARM GAS /tmp/ccjtTCRz.s page 86 + + + 2875 .L169: + 2876 .align 2 + 2877 .L168: + 2878 0114 3FFFFF00 .word 16777023 + 2879 .cfi_endproc + 2880 .LFE45: + 2882 .section .text.RTC_ByteToBcd2,"ax",%progbits + 2883 .align 1 + 2884 .global RTC_ByteToBcd2 + 2885 .syntax unified + 2886 .code 16 + 2887 .thumb_func + 2888 .fpu softvfp + 2890 RTC_ByteToBcd2: + 2891 .LFB57: +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t bcdhigh = 0U; + 2892 .loc 1 1491 0 + 2893 .cfi_startproc + 2894 @ args = 0, pretend = 0, frame = 0 + 2895 @ frame_needed = 0, uses_anonymous_args = 0 + 2896 @ link register save eliminated. + 2897 .LVL305: +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2898 .loc 1 1492 0 + 2899 0000 0023 movs r3, #0 +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2900 .loc 1 1494 0 + 2901 0002 02E0 b .L171 + 2902 .LVL306: + 2903 .L172: +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** Value -= 10U; + 2904 .loc 1 1496 0 + 2905 0004 0133 adds r3, r3, #1 + 2906 .LVL307: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2907 .loc 1 1497 0 + 2908 0006 0A38 subs r0, r0, #10 + 2909 .LVL308: + 2910 0008 C0B2 uxtb r0, r0 + 2911 .LVL309: + 2912 .L171: +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** { + 2913 .loc 1 1494 0 + 2914 000a 0928 cmp r0, #9 + 2915 000c FAD8 bhi .L172 +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2916 .loc 1 1500 0 + 2917 000e 1B01 lsls r3, r3, #4 + 2918 .LVL310: + 2919 0010 DBB2 uxtb r3, r3 + 2920 0012 1843 orrs r0, r3 + 2921 .LVL311: +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** + 2922 .loc 1 1501 0 + 2923 @ sp needed + 2924 0014 7047 bx lr + 2925 .cfi_endproc + ARM GAS /tmp/ccjtTCRz.s page 87 + + + 2926 .LFE57: + 2928 .section .text.RTC_Bcd2ToByte,"ax",%progbits + 2929 .align 1 + 2930 .global RTC_Bcd2ToByte + 2931 .syntax unified + 2932 .code 16 + 2933 .thumb_func + 2934 .fpu softvfp + 2936 RTC_Bcd2ToByte: + 2937 .LFB58: +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** uint32_t tmp = 0U; + 2938 .loc 1 1509 0 + 2939 .cfi_startproc + 2940 @ args = 0, pretend = 0, frame = 0 + 2941 @ frame_needed = 0, uses_anonymous_args = 0 + 2942 @ link register save eliminated. + 2943 .LVL312: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** return (tmp + (Value & (uint8_t)0x0FU)); + 2944 .loc 1 1511 0 + 2945 0000 0209 lsrs r2, r0, #4 + 2946 0002 9300 lsls r3, r2, #2 + 2947 0004 9B18 adds r3, r3, r2 + 2948 0006 5A00 lsls r2, r3, #1 + 2949 .LVL313: + 2950 .loc 1 1512 0 + 2951 0008 0F23 movs r3, #15 + 2952 000a 1840 ands r0, r3 + 2953 .LVL314: + 2954 000c 8018 adds r0, r0, r2 + 2955 000e C0B2 uxtb r0, r0 +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c **** } + 2956 .loc 1 1513 0 + 2957 @ sp needed + 2958 0010 7047 bx lr + 2959 .cfi_endproc + 2960 .LFE58: + 2962 .text + 2963 .Letext0: + 2964 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2965 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2966 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 2967 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 2968 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 2969 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 2970 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 2971 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 2972 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 2973 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 2974 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h" + 2975 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 2976 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h" + ARM GAS /tmp/ccjtTCRz.s page 88 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_rtc.c + /tmp/ccjtTCRz.s:16 .text.HAL_RTC_MspInit:0000000000000000 $t + /tmp/ccjtTCRz.s:23 .text.HAL_RTC_MspInit:0000000000000000 HAL_RTC_MspInit + /tmp/ccjtTCRz.s:39 .text.HAL_RTC_MspDeInit:0000000000000000 $t + /tmp/ccjtTCRz.s:46 .text.HAL_RTC_MspDeInit:0000000000000000 HAL_RTC_MspDeInit + /tmp/ccjtTCRz.s:61 .text.HAL_RTC_GetTime:0000000000000000 $t + /tmp/ccjtTCRz.s:68 .text.HAL_RTC_GetTime:0000000000000000 HAL_RTC_GetTime + /tmp/ccjtTCRz.s:185 .text.HAL_RTC_GetTime:0000000000000068 $d + /tmp/ccjtTCRz.s:190 .text.HAL_RTC_GetDate:0000000000000000 $t + /tmp/ccjtTCRz.s:197 .text.HAL_RTC_GetDate:0000000000000000 HAL_RTC_GetDate + /tmp/ccjtTCRz.s:304 .text.HAL_RTC_GetDate:0000000000000058 $d + /tmp/ccjtTCRz.s:309 .text.HAL_RTC_SetAlarm:0000000000000000 $t + /tmp/ccjtTCRz.s:316 .text.HAL_RTC_SetAlarm:0000000000000000 HAL_RTC_SetAlarm + /tmp/ccjtTCRz.s:720 .text.HAL_RTC_SetAlarm:00000000000001b8 $d + /tmp/ccjtTCRz.s:728 .text.HAL_RTC_SetAlarm_IT:0000000000000000 $t + /tmp/ccjtTCRz.s:735 .text.HAL_RTC_SetAlarm_IT:0000000000000000 HAL_RTC_SetAlarm_IT + /tmp/ccjtTCRz.s:1168 .text.HAL_RTC_SetAlarm_IT:00000000000001e8 $d + /tmp/ccjtTCRz.s:1177 .text.HAL_RTC_DeactivateAlarm:0000000000000000 $t + /tmp/ccjtTCRz.s:1184 .text.HAL_RTC_DeactivateAlarm:0000000000000000 HAL_RTC_DeactivateAlarm + /tmp/ccjtTCRz.s:1351 .text.HAL_RTC_DeactivateAlarm:00000000000000d4 $d + /tmp/ccjtTCRz.s:1359 .text.HAL_RTC_GetAlarm:0000000000000000 $t + /tmp/ccjtTCRz.s:1366 .text.HAL_RTC_GetAlarm:0000000000000000 HAL_RTC_GetAlarm + /tmp/ccjtTCRz.s:1587 .text.HAL_RTC_GetAlarm:00000000000000e0 $d + /tmp/ccjtTCRz.s:1592 .text.HAL_RTC_AlarmAEventCallback:0000000000000000 $t + /tmp/ccjtTCRz.s:1599 .text.HAL_RTC_AlarmAEventCallback:0000000000000000 HAL_RTC_AlarmAEventCallback + /tmp/ccjtTCRz.s:1614 .text.HAL_RTC_AlarmIRQHandler:0000000000000000 $t + /tmp/ccjtTCRz.s:1621 .text.HAL_RTC_AlarmIRQHandler:0000000000000000 HAL_RTC_AlarmIRQHandler + /tmp/ccjtTCRz.s:1699 .text.HAL_RTC_AlarmIRQHandler:000000000000005c $d + /tmp/ccjtTCRz.s:1706 .text.HAL_RTC_PollForAlarmAEvent:0000000000000000 $t + /tmp/ccjtTCRz.s:1713 .text.HAL_RTC_PollForAlarmAEvent:0000000000000000 HAL_RTC_PollForAlarmAEvent + /tmp/ccjtTCRz.s:1784 .text.HAL_RTC_PollForAlarmAEvent:0000000000000048 $d + /tmp/ccjtTCRz.s:1789 .text.HAL_RTC_WaitForSynchro:0000000000000000 $t + /tmp/ccjtTCRz.s:1796 .text.HAL_RTC_WaitForSynchro:0000000000000000 HAL_RTC_WaitForSynchro + /tmp/ccjtTCRz.s:1853 .text.HAL_RTC_GetState:0000000000000000 $t + /tmp/ccjtTCRz.s:1860 .text.HAL_RTC_GetState:0000000000000000 HAL_RTC_GetState + /tmp/ccjtTCRz.s:1880 .text.RTC_EnterInitMode:0000000000000000 $t + /tmp/ccjtTCRz.s:1887 .text.RTC_EnterInitMode:0000000000000000 RTC_EnterInitMode + /tmp/ccjtTCRz.s:1952 .text.HAL_RTC_Init:0000000000000000 $t + /tmp/ccjtTCRz.s:1959 .text.HAL_RTC_Init:0000000000000000 HAL_RTC_Init + /tmp/ccjtTCRz.s:2091 .text.HAL_RTC_Init:00000000000000a8 $d + /tmp/ccjtTCRz.s:2096 .text.HAL_RTC_DeInit:0000000000000000 $t + /tmp/ccjtTCRz.s:2103 .text.HAL_RTC_DeInit:0000000000000000 HAL_RTC_DeInit + /tmp/ccjtTCRz.s:2282 .text.HAL_RTC_DeInit:00000000000000e4 $d + /tmp/ccjtTCRz.s:2289 .text.HAL_RTC_SetTime:0000000000000000 $t + /tmp/ccjtTCRz.s:2296 .text.HAL_RTC_SetTime:0000000000000000 HAL_RTC_SetTime + /tmp/ccjtTCRz.s:2591 .text.HAL_RTC_SetTime:0000000000000134 $d + /tmp/ccjtTCRz.s:2597 .text.HAL_RTC_SetDate:0000000000000000 $t + /tmp/ccjtTCRz.s:2604 .text.HAL_RTC_SetDate:0000000000000000 HAL_RTC_SetDate + /tmp/ccjtTCRz.s:2878 .text.HAL_RTC_SetDate:0000000000000114 $d + /tmp/ccjtTCRz.s:2883 .text.RTC_ByteToBcd2:0000000000000000 $t + /tmp/ccjtTCRz.s:2890 .text.RTC_ByteToBcd2:0000000000000000 RTC_ByteToBcd2 + /tmp/ccjtTCRz.s:2929 .text.RTC_Bcd2ToByte:0000000000000000 $t + /tmp/ccjtTCRz.s:2936 .text.RTC_Bcd2ToByte:0000000000000000 RTC_Bcd2ToByte + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS + ARM GAS /tmp/ccjtTCRz.s page 89 + + +HAL_GetTick +HAL_RTCEx_AlarmBEventCallback diff --git a/build/stm32l0xx_hal_rtc_ex.d b/build/stm32l0xx_hal_rtc_ex.d new file mode 100644 index 0000000..20a4f94 --- /dev/null +++ b/build/stm32l0xx_hal_rtc_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_rtc_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_rtc_ex.lst b/build/stm32l0xx_hal_rtc_ex.lst new file mode 100644 index 0000000..beef114 --- /dev/null +++ b/build/stm32l0xx_hal_rtc_ex.lst @@ -0,0 +1,5596 @@ +ARM GAS /tmp/ccjDTEau.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_rtc_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_RTCEx_SetTimeStamp,"ax",%progbits + 16 .align 1 + 17 .global HAL_RTCEx_SetTimeStamp + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_RTCEx_SetTimeStamp: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @file stm32l0xx_hal_rtc_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Extended RTC HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This file provides firmware functions to manage the following + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * functionalities of the Real Time Clock (RTC) Extended peripheral: + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + RTC Time Stamp functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + RTC Tamper functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + RTC Wake-up functions + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + Extended Control functions + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + Extended RTC features functions + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @verbatim + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ============================================================================== + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ##### How to use this driver ##### + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ============================================================================== + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Enable the RTC domain access. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** format using the HAL_RTC_Init() function. + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** RTC Wakeup configuration *** + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ================================ + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. You can also configure the RTC Wakeup timer with interrupt mode + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** using the HAL_RTCEx_SetWakeUpTimer_IT() function. + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** Outputs configuration *** + ARM GAS /tmp/ccjDTEau.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ============================= + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] The RTC has 2 different outputs: + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** and WaKeUp signals. + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** To output the selected RTC signal, use the HAL_RTC_Init() function. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) RTC_CALIB: this output is 512Hz signal or 1Hz. + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) for STM32L05x/6x/7x/8x + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** and (PA2, PB14) for STM32L03x/4x managed on the RTC_OR register. + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** automatically configured in output alternate function. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** Smooth digital Calibration configuration *** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ================================================ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Configure the RTC Original Digital Calibration Value and the corresponding + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** TimeStamp configuration *** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================== + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** Tamper configuration *** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ============================ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** or Level according to the Tamper filter (if equal to 0 Edge else Level) + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) The default configuration of the Tamper erases the backup registers. To avoid + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** erase, enable the NoErase field on the RTC_TAMPCR register. + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *** Backup Data Registers configuration *** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =========================================== + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** function. + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @endverbatim + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ****************************************************************************** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @attention + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * are permitted provided that the following conditions are met: + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * this list of conditions and the following disclaimer. + ARM GAS /tmp/ccjDTEau.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * this list of conditions and the following disclaimer in the documentation + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * and/or other materials provided with the distribution. + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * may be used to endorse or promote products derived from this software + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * without specific prior written permission. + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ****************************************************************************** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #include "stm32l0xx_hal.h" + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief RTC Extended HAL module driver + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #ifdef HAL_RTC_MODULE_ENABLED + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Private define ------------------------------------------------------------*/ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Exported functions --------------------------------------------------------*/ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx_Exported_Functions + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx_Exported_Functions_Group1 + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief RTC TimeStamp and Tamper functions + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @verbatim + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ##### RTC TimeStamp and Tamper functions ##### + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] This section provides functions allowing to configure TimeStamp feature + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @endverbatim + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set TimeStamp. + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note This API must be called before enabling the TimeStamp feature. + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * activated. + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * rising edge of the related pin. + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * falling edge of the related pin. + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6 + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * and PA2 on STM32L03x/4x/2x/1x. + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 26 .loc 1 170 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F0B5 push {r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 20 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + 36 .cfi_offset 6, -12 + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 39 .LVL1: + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmpreg = 0U; + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 40 .loc 1 178 0 + 41 0002 2023 movs r3, #32 + 42 0004 C35C ldrb r3, [r0, r3] + 43 0006 012B cmp r3, #1 + 44 0008 1FD0 beq .L3 + 45 .loc 1 178 0 is_stmt 0 discriminator 2 + 46 000a 2022 movs r2, #32 + 47 .LVL2: + 48 000c 0125 movs r5, #1 + 49 000e 8554 strb r5, [r0, r2] + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + ARM GAS /tmp/ccjDTEau.s page 5 + + + 50 .loc 1 180 0 is_stmt 1 discriminator 2 + 51 0010 2124 movs r4, #33 + 52 0012 0223 movs r3, #2 + 53 0014 0355 strb r3, [r0, r4] + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the RTC_CR register and clear the bits to be configured */ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + 54 .loc 1 183 0 discriminator 2 + 55 0016 0668 ldr r6, [r0] + 56 0018 B368 ldr r3, [r6, #8] + 57 001a 0D4F ldr r7, .L4 + 58 001c 3B40 ands r3, r7 + 59 .LVL3: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg|= TimeStampEdge; + 60 .loc 1 185 0 discriminator 2 + 61 001e 1943 orrs r1, r3 + 62 .LVL4: + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 63 .loc 1 188 0 discriminator 2 + 64 0020 CA23 movs r3, #202 + 65 0022 7362 str r3, [r6, #36] + 66 0024 0368 ldr r3, [r0] + 67 0026 5326 movs r6, #83 + 68 0028 5E62 str r6, [r3, #36] + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Time Stamp TSEDGE and Enable bits */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR = (uint32_t)tmpreg; + 69 .loc 1 191 0 discriminator 2 + 70 002a 0368 ldr r3, [r0] + 71 002c 9960 str r1, [r3, #8] + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + 72 .loc 1 193 0 discriminator 2 + 73 002e 0168 ldr r1, [r0] + 74 .LVL5: + 75 0030 8E68 ldr r6, [r1, #8] + 76 0032 8023 movs r3, #128 + 77 .LVL6: + 78 0034 1B01 lsls r3, r3, #4 + 79 0036 3343 orrs r3, r6 + 80 0038 8B60 str r3, [r1, #8] + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 81 .loc 1 196 0 discriminator 2 + 82 003a 0368 ldr r3, [r0] + 83 003c FF21 movs r1, #255 + 84 003e 5962 str r1, [r3, #36] + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 85 .loc 1 199 0 discriminator 2 + 86 0040 0555 strb r5, [r0, r4] + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 6 + + + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 87 .loc 1 202 0 discriminator 2 + 88 0042 0023 movs r3, #0 + 89 0044 8354 strb r3, [r0, r2] + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 90 .loc 1 204 0 discriminator 2 + 91 0046 0020 movs r0, #0 + 92 .LVL7: + 93 .L2: + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 94 .loc 1 205 0 + 95 @ sp needed + 96 0048 F0BD pop {r4, r5, r6, r7, pc} + 97 .LVL8: + 98 .L3: + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 99 .loc 1 178 0 + 100 004a 0220 movs r0, #2 + 101 .LVL9: + 102 004c FCE7 b .L2 + 103 .L5: + 104 004e C046 .align 2 + 105 .L4: + 106 0050 F7F7FFFF .word -2057 + 107 .cfi_endproc + 108 .LFE39: + 110 .section .text.HAL_RTCEx_SetTimeStamp_IT,"ax",%progbits + 111 .align 1 + 112 .global HAL_RTCEx_SetTimeStamp_IT + 113 .syntax unified + 114 .code 16 + 115 .thumb_func + 116 .fpu softvfp + 118 HAL_RTCEx_SetTimeStamp_IT: + 119 .LFB40: + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set TimeStamp with Interrupt. + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note This API must be called before enabling the TimeStamp feature. + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * activated. + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * rising edge of the related pin. + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * falling edge of the related pin. + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6 + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * and PA2 on STM32L03x/4x/2x/1x. + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32 + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + ARM GAS /tmp/ccjDTEau.s page 7 + + + 120 .loc 1 225 0 + 121 .cfi_startproc + 122 @ args = 0, pretend = 0, frame = 0 + 123 @ frame_needed = 0, uses_anonymous_args = 0 + 124 .LVL10: + 125 0000 F0B5 push {r4, r5, r6, r7, lr} + 126 .LCFI1: + 127 .cfi_def_cfa_offset 20 + 128 .cfi_offset 4, -20 + 129 .cfi_offset 5, -16 + 130 .cfi_offset 6, -12 + 131 .cfi_offset 7, -8 + 132 .cfi_offset 14, -4 + 133 .LVL11: + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmpreg = 0U; + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 134 .loc 1 233 0 + 135 0002 2023 movs r3, #32 + 136 0004 C35C ldrb r3, [r0, r3] + 137 0006 012B cmp r3, #1 + 138 0008 2ED0 beq .L8 + 139 .loc 1 233 0 is_stmt 0 discriminator 2 + 140 000a 2024 movs r4, #32 + 141 000c 0126 movs r6, #1 + 142 000e 0655 strb r6, [r0, r4] + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 143 .loc 1 235 0 is_stmt 1 discriminator 2 + 144 0010 2125 movs r5, #33 + 145 0012 0223 movs r3, #2 + 146 0014 4355 strb r3, [r0, r5] + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the RTC_CR register and clear the bits to be configured */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + 147 .loc 1 238 0 discriminator 2 + 148 0016 0268 ldr r2, [r0] + 149 .LVL12: + 150 0018 9368 ldr r3, [r2, #8] + 151 001a 144F ldr r7, .L9 + 152 001c 3B40 ands r3, r7 + 153 .LVL13: + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg |= TimeStampEdge; + 154 .loc 1 240 0 discriminator 2 + 155 001e 1943 orrs r1, r3 + 156 .LVL14: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 157 .loc 1 243 0 discriminator 2 + 158 0020 CA23 movs r3, #202 + ARM GAS /tmp/ccjDTEau.s page 8 + + + 159 0022 5362 str r3, [r2, #36] + 160 0024 0368 ldr r3, [r0] + 161 0026 5322 movs r2, #83 + 162 0028 5A62 str r2, [r3, #36] + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Time Stamp TSEDGE and Enable bits */ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR = (uint32_t)tmpreg; + 163 .loc 1 246 0 discriminator 2 + 164 002a 0368 ldr r3, [r0] + 165 002c 9960 str r1, [r3, #8] + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + 166 .loc 1 248 0 discriminator 2 + 167 002e 0268 ldr r2, [r0] + 168 0030 9168 ldr r1, [r2, #8] + 169 .LVL15: + 170 0032 8023 movs r3, #128 + 171 .LVL16: + 172 0034 1B01 lsls r3, r3, #4 + 173 0036 0B43 orrs r3, r1 + 174 0038 9360 str r3, [r2, #8] + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable IT timestamp */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + 175 .loc 1 251 0 discriminator 2 + 176 003a 0268 ldr r2, [r0] + 177 003c 9168 ldr r1, [r2, #8] + 178 003e 8023 movs r3, #128 + 179 0040 1B02 lsls r3, r3, #8 + 180 0042 0B43 orrs r3, r1 + 181 0044 9360 str r3, [r2, #8] + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* RTC timestamp Interrupt Configuration: EXTI configuration */ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + 182 .loc 1 254 0 discriminator 2 + 183 0046 0A4B ldr r3, .L9+4 + 184 0048 1968 ldr r1, [r3] + 185 004a 8022 movs r2, #128 + 186 004c 1203 lsls r2, r2, #12 + 187 004e 1143 orrs r1, r2 + 188 0050 1960 str r1, [r3] + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); + 189 .loc 1 256 0 discriminator 2 + 190 0052 9968 ldr r1, [r3, #8] + 191 0054 0A43 orrs r2, r1 + 192 0056 9A60 str r2, [r3, #8] + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 193 .loc 1 259 0 discriminator 2 + 194 0058 0368 ldr r3, [r0] + 195 005a FF22 movs r2, #255 + 196 005c 5A62 str r2, [r3, #36] + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 197 .loc 1 261 0 discriminator 2 + ARM GAS /tmp/ccjDTEau.s page 9 + + + 198 005e 4655 strb r6, [r0, r5] + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 199 .loc 1 264 0 discriminator 2 + 200 0060 0023 movs r3, #0 + 201 0062 0355 strb r3, [r0, r4] + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 202 .loc 1 266 0 discriminator 2 + 203 0064 0020 movs r0, #0 + 204 .LVL17: + 205 .L7: + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 206 .loc 1 267 0 + 207 @ sp needed + 208 0066 F0BD pop {r4, r5, r6, r7, pc} + 209 .LVL18: + 210 .L8: + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 211 .loc 1 233 0 + 212 0068 0220 movs r0, #2 + 213 .LVL19: + 214 006a FCE7 b .L7 + 215 .L10: + 216 .align 2 + 217 .L9: + 218 006c F7F7FFFF .word -2057 + 219 0070 00040140 .word 1073808384 + 220 .cfi_endproc + 221 .LFE40: + 223 .section .text.HAL_RTCEx_DeactivateTimeStamp,"ax",%progbits + 224 .align 1 + 225 .global HAL_RTCEx_DeactivateTimeStamp + 226 .syntax unified + 227 .code 16 + 228 .thumb_func + 229 .fpu softvfp + 231 HAL_RTCEx_DeactivateTimeStamp: + 232 .LFB41: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Deactivate TimeStamp. + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 233 .loc 1 275 0 + 234 .cfi_startproc + 235 @ args = 0, pretend = 0, frame = 0 + 236 @ frame_needed = 0, uses_anonymous_args = 0 + 237 .LVL20: + 238 0000 70B5 push {r4, r5, r6, lr} + 239 .LCFI2: + 240 .cfi_def_cfa_offset 16 + 241 .cfi_offset 4, -16 + ARM GAS /tmp/ccjDTEau.s page 10 + + + 242 .cfi_offset 5, -12 + 243 .cfi_offset 6, -8 + 244 .cfi_offset 14, -4 + 245 .LVL21: + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmpreg = 0U; + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 246 .loc 1 279 0 + 247 0002 2023 movs r3, #32 + 248 0004 C35C ldrb r3, [r0, r3] + 249 0006 012B cmp r3, #1 + 250 0008 1DD0 beq .L13 + 251 .loc 1 279 0 is_stmt 0 discriminator 2 + 252 000a 2022 movs r2, #32 + 253 000c 0124 movs r4, #1 + 254 000e 8454 strb r4, [r0, r2] + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 255 .loc 1 281 0 is_stmt 1 discriminator 2 + 256 0010 2121 movs r1, #33 + 257 0012 0223 movs r3, #2 + 258 0014 4354 strb r3, [r0, r1] + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 259 .loc 1 284 0 discriminator 2 + 260 0016 0368 ldr r3, [r0] + 261 0018 CA25 movs r5, #202 + 262 001a 5D62 str r5, [r3, #36] + 263 001c 0368 ldr r3, [r0] + 264 001e 773D subs r5, r5, #119 + 265 0020 5D62 str r5, [r3, #36] + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); + 266 .loc 1 287 0 discriminator 2 + 267 0022 0568 ldr r5, [r0] + 268 0024 AB68 ldr r3, [r5, #8] + 269 0026 094E ldr r6, .L14 + 270 0028 3340 ands r3, r6 + 271 002a AB60 str r3, [r5, #8] + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the RTC_CR register and clear the bits to be configured */ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + 272 .loc 1 290 0 discriminator 2 + 273 002c 0568 ldr r5, [r0] + 274 002e AB68 ldr r3, [r5, #8] + 275 0030 074E ldr r6, .L14+4 + 276 0032 3340 ands r3, r6 + 277 .LVL22: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Time Stamp TSEDGE and Enable bits */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR = (uint32_t)tmpreg; + 278 .loc 1 293 0 discriminator 2 + 279 0034 AB60 str r3, [r5, #8] + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 11 + + + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 280 .loc 1 296 0 discriminator 2 + 281 0036 0368 ldr r3, [r0] + 282 .LVL23: + 283 0038 FF25 movs r5, #255 + 284 .LVL24: + 285 003a 5D62 str r5, [r3, #36] + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 286 .loc 1 298 0 discriminator 2 + 287 003c 4454 strb r4, [r0, r1] + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 288 .loc 1 301 0 discriminator 2 + 289 003e 0023 movs r3, #0 + 290 0040 8354 strb r3, [r0, r2] + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 291 .loc 1 303 0 discriminator 2 + 292 0042 0020 movs r0, #0 + 293 .LVL25: + 294 .L12: + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 295 .loc 1 304 0 + 296 @ sp needed + 297 0044 70BD pop {r4, r5, r6, pc} + 298 .LVL26: + 299 .L13: + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 300 .loc 1 279 0 + 301 0046 0220 movs r0, #2 + 302 .LVL27: + 303 0048 FCE7 b .L12 + 304 .L15: + 305 004a C046 .align 2 + 306 .L14: + 307 004c FF7FFFFF .word -32769 + 308 0050 F7F7FFFF .word -2057 + 309 .cfi_endproc + 310 .LFE41: + 312 .section .text.HAL_RTCEx_GetTimeStamp,"ax",%progbits + 313 .align 1 + 314 .global HAL_RTCEx_GetTimeStamp + 315 .syntax unified + 316 .code 16 + 317 .thumb_func + 318 .fpu softvfp + 320 HAL_RTCEx_GetTimeStamp: + 321 .LFB42: + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Get the RTC TimeStamp value. + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param sTimeStamp: Pointer to Time structure + ARM GAS /tmp/ccjDTEau.s page 12 + + + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param sTimeStampDate: Pointer to Date structure + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Format: specifies the format of the entered parameters. + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_FORMAT_BIN: Binary data format + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_FORMAT_BCD: BCD data format + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 322 .loc 1 319 0 + 323 .cfi_startproc + 324 @ args = 0, pretend = 0, frame = 0 + 325 @ frame_needed = 0, uses_anonymous_args = 0 + 326 .LVL28: + 327 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 328 .LCFI3: + 329 .cfi_def_cfa_offset 24 + 330 .cfi_offset 3, -24 + 331 .cfi_offset 4, -20 + 332 .cfi_offset 5, -16 + 333 .cfi_offset 6, -12 + 334 .cfi_offset 7, -8 + 335 .cfi_offset 14, -4 + 336 0002 CE46 mov lr, r9 + 337 0004 4746 mov r7, r8 + 338 0006 80B5 push {r7, lr} + 339 .LCFI4: + 340 .cfi_def_cfa_offset 32 + 341 .cfi_offset 8, -32 + 342 .cfi_offset 9, -28 + 343 0008 0600 movs r6, r0 + 344 000a 0C00 movs r4, r1 + 345 000c 1500 movs r5, r2 + 346 000e 9946 mov r9, r3 + 347 .LVL29: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmptime = 0U, tmpdate = 0U; + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_FORMAT(Format)); + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the TimeStamp time and date registers values */ + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); + 348 .loc 1 326 0 + 349 0010 0268 ldr r2, [r0] + 350 .LVL30: + 351 0012 106B ldr r0, [r2, #48] + 352 .LVL31: + 353 0014 2549 ldr r1, .L19 + 354 .LVL32: + 355 0016 0140 ands r1, r0 + 356 .LVL33: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); + 357 .loc 1 327 0 + 358 0018 506B ldr r0, [r2, #52] + 359 001a 254A ldr r2, .L19+4 + 360 001c 0240 ands r2, r0 + 361 .LVL34: + ARM GAS /tmp/ccjDTEau.s page 13 + + + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Fill the Time structure fields with the read parameters */ + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + 362 .loc 1 330 0 + 363 001e 0B0C lsrs r3, r1, #16 + 364 .LVL35: + 365 0020 9846 mov r8, r3 + 366 0022 3F20 movs r0, #63 + 367 0024 1F00 movs r7, r3 + 368 0026 0740 ands r7, r0 + 369 0028 2770 strb r7, [r4] + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); + 370 .loc 1 331 0 + 371 002a 0B0A lsrs r3, r1, #8 + 372 002c 7F27 movs r7, #127 + 373 002e 3B40 ands r3, r7 + 374 0030 6370 strb r3, [r4, #1] + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + 375 .loc 1 332 0 + 376 0032 3940 ands r1, r7 + 377 .LVL36: + 378 0034 A170 strb r1, [r4, #2] + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); + 379 .loc 1 333 0 + 380 0036 4021 movs r1, #64 + 381 0038 4346 mov r3, r8 + 382 003a 1940 ands r1, r3 + 383 003c E170 strb r1, [r4, #3] + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; + 384 .loc 1 334 0 + 385 003e 3168 ldr r1, [r6] + 386 0040 896B ldr r1, [r1, #56] + 387 0042 6160 str r1, [r4, #4] + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Fill the Date structure fields with the read parameters */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Year = 0U; + 388 .loc 1 337 0 + 389 0044 0021 movs r1, #0 + 390 0046 E970 strb r1, [r5, #3] + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); + 391 .loc 1 338 0 + 392 0048 170A lsrs r7, r2, #8 + 393 004a 1F31 adds r1, r1, #31 + 394 004c 3940 ands r1, r7 + 395 004e 6970 strb r1, [r5, #1] + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + 396 .loc 1 339 0 + 397 0050 1040 ands r0, r2 + 398 0052 A870 strb r0, [r5, #2] + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); + 399 .loc 1 340 0 + 400 0054 520B lsrs r2, r2, #13 + 401 .LVL37: + 402 0056 0721 movs r1, #7 + 403 0058 0A40 ands r2, r1 + 404 005a 2A70 strb r2, [r5] + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 14 + + + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the input parameters format */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Format == RTC_FORMAT_BIN) + 405 .loc 1 343 0 + 406 005c 4B46 mov r3, r9 + 407 005e 002B cmp r3, #0 + 408 0060 0BD0 beq .L18 + 409 .L17: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Convert the TimeStamp structure parameters to Binary format */ + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Convert the DateTimeStamp structure parameters to Binary format */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the TIMESTAMP Flag */ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + 410 .loc 1 357 0 + 411 0062 3168 ldr r1, [r6] + 412 0064 CA68 ldr r2, [r1, #12] + 413 0066 FF23 movs r3, #255 + 414 0068 1A40 ands r2, r3 + 415 006a 124B ldr r3, .L19+8 + 416 006c 1343 orrs r3, r2 + 417 006e CB60 str r3, [r1, #12] + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 418 .loc 1 360 0 + 419 0070 0020 movs r0, #0 + 420 @ sp needed + 421 .LVL38: + 422 .LVL39: + 423 .LVL40: + 424 .LVL41: + 425 0072 0CBC pop {r2, r3} + 426 0074 9046 mov r8, r2 + 427 0076 9946 mov r9, r3 + 428 0078 F8BD pop {r3, r4, r5, r6, r7, pc} + 429 .LVL42: + 430 .L18: + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + 431 .loc 1 346 0 + 432 007a 2078 ldrb r0, [r4] + 433 007c FFF7FEFF bl RTC_Bcd2ToByte + 434 .LVL43: + 435 0080 2070 strb r0, [r4] + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + 436 .loc 1 347 0 + 437 0082 6078 ldrb r0, [r4, #1] + 438 0084 FFF7FEFF bl RTC_Bcd2ToByte + 439 .LVL44: + 440 0088 6070 strb r0, [r4, #1] + ARM GAS /tmp/ccjDTEau.s page 15 + + + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 441 .loc 1 348 0 + 442 008a A078 ldrb r0, [r4, #2] + 443 008c FFF7FEFF bl RTC_Bcd2ToByte + 444 .LVL45: + 445 0090 A070 strb r0, [r4, #2] + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + 446 .loc 1 351 0 + 447 0092 6878 ldrb r0, [r5, #1] + 448 0094 FFF7FEFF bl RTC_Bcd2ToByte + 449 .LVL46: + 450 0098 6870 strb r0, [r5, #1] + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + 451 .loc 1 352 0 + 452 009a A878 ldrb r0, [r5, #2] + 453 009c FFF7FEFF bl RTC_Bcd2ToByte + 454 .LVL47: + 455 00a0 A870 strb r0, [r5, #2] + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 456 .loc 1 353 0 + 457 00a2 2878 ldrb r0, [r5] + 458 00a4 FFF7FEFF bl RTC_Bcd2ToByte + 459 .LVL48: + 460 00a8 2870 strb r0, [r5] + 461 00aa DAE7 b .L17 + 462 .L20: + 463 .align 2 + 464 .L19: + 465 00ac 7F7F7F00 .word 8355711 + 466 00b0 3FFFFF00 .word 16777023 + 467 00b4 7FF7FFFF .word -2177 + 468 .cfi_endproc + 469 .LFE42: + 471 .section .text.HAL_RTCEx_SetTamper,"ax",%progbits + 472 .align 1 + 473 .global HAL_RTCEx_SetTamper + 474 .syntax unified + 475 .code 16 + 476 .thumb_func + 477 .fpu softvfp + 479 HAL_RTCEx_SetTamper: + 480 .LFB43: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set Tamper + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note By calling this API we disable the tamper interrupt for all tampers. + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param sTamper: Pointer to Tamper Structure. + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 481 .loc 1 370 0 + 482 .cfi_startproc + 483 @ args = 0, pretend = 0, frame = 0 + 484 @ frame_needed = 0, uses_anonymous_args = 0 + 485 .LVL49: + ARM GAS /tmp/ccjDTEau.s page 16 + + + 486 0000 30B5 push {r4, r5, lr} + 487 .LCFI5: + 488 .cfi_def_cfa_offset 12 + 489 .cfi_offset 4, -12 + 490 .cfi_offset 5, -8 + 491 .cfi_offset 14, -4 + 492 .LVL50: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmpreg = 0U; + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param( IS_RTC_TAMPER(sTamper->Tamper)); + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 493 .loc 1 385 0 + 494 0002 2023 movs r3, #32 + 495 0004 C35C ldrb r3, [r0, r3] + 496 0006 012B cmp r3, #1 + 497 0008 62D0 beq .L30 + 498 .loc 1 385 0 is_stmt 0 discriminator 2 + 499 000a 2023 movs r3, #32 + 500 000c 0122 movs r2, #1 + 501 000e C254 strb r2, [r0, r3] + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 502 .loc 1 387 0 is_stmt 1 discriminator 2 + 503 0010 0133 adds r3, r3, #1 + 504 0012 0132 adds r2, r2, #1 + 505 0014 C254 strb r2, [r0, r3] + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the tamper trigger */ + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + 506 .loc 1 390 0 discriminator 2 + 507 0016 8B68 ldr r3, [r1, #8] + 508 0018 002B cmp r3, #0 + 509 001a 02D0 beq .L23 + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); + 510 .loc 1 392 0 + 511 001c 0B68 ldr r3, [r1] + 512 001e 5B00 lsls r3, r3, #1 + 513 0020 8B60 str r3, [r1, #8] + 514 .L23: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + 515 .loc 1 395 0 + 516 0022 CB68 ldr r3, [r1, #12] + 517 0024 002B cmp r3, #0 + ARM GAS /tmp/ccjDTEau.s page 17 + + + 518 0026 15D0 beq .L24 + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase = 0U; + 519 .loc 1 397 0 + 520 0028 0023 movs r3, #0 + 521 002a CB60 str r3, [r1, #12] + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + 522 .loc 1 404 0 + 523 002c 0B68 ldr r3, [r1] + 524 002e DA07 lsls r2, r3, #31 + 525 0030 02D5 bpl .L25 + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + 526 .loc 1 406 0 + 527 0032 8022 movs r2, #128 + 528 0034 9202 lsls r2, r2, #10 + 529 0036 CA60 str r2, [r1, #12] + 530 .L25: + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + 531 .loc 1 415 0 + 532 0038 1A07 lsls r2, r3, #28 + 533 003a 04D5 bpl .L26 + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + 534 .loc 1 417 0 + 535 003c 8022 movs r2, #128 + 536 003e 5203 lsls r2, r2, #13 + 537 0040 CC68 ldr r4, [r1, #12] + 538 0042 2243 orrs r2, r4 + 539 0044 CA60 str r2, [r1, #12] + 540 .L26: + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + 541 .loc 1 423 0 + 542 0046 9B06 lsls r3, r3, #26 + 543 0048 04D5 bpl .L24 + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + 544 .loc 1 425 0 + ARM GAS /tmp/ccjDTEau.s page 18 + + + 545 004a 8023 movs r3, #128 + 546 004c 1B04 lsls r3, r3, #16 + 547 004e CA68 ldr r2, [r1, #12] + 548 0050 1343 orrs r3, r2 + 549 0052 CB60 str r3, [r1, #12] + 550 .L24: + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + 551 .loc 1 433 0 + 552 0054 0B69 ldr r3, [r1, #16] + 553 0056 002B cmp r3, #0 + 554 0058 15D0 beq .L27 + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag = 0U; + 555 .loc 1 435 0 + 556 005a 0023 movs r3, #0 + 557 005c 0B61 str r3, [r1, #16] + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + 558 .loc 1 443 0 + 559 005e 0B68 ldr r3, [r1] + 560 0060 DA07 lsls r2, r3, #31 + 561 0062 02D5 bpl .L28 + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + 562 .loc 1 445 0 + 563 0064 8022 movs r2, #128 + 564 0066 D202 lsls r2, r2, #11 + 565 0068 0A61 str r2, [r1, #16] + 566 .L28: + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + 567 .loc 1 454 0 + 568 006a 1A07 lsls r2, r3, #28 + 569 006c 04D5 bpl .L29 + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + 570 .loc 1 456 0 + ARM GAS /tmp/ccjDTEau.s page 19 + + + 571 006e 8022 movs r2, #128 + 572 0070 9203 lsls r2, r2, #14 + 573 0072 0C69 ldr r4, [r1, #16] + 574 0074 2243 orrs r2, r4 + 575 0076 0A61 str r2, [r1, #16] + 576 .L29: + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + 577 .loc 1 462 0 + 578 0078 9B06 lsls r3, r3, #26 + 579 007a 04D5 bpl .L27 + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + 580 .loc 1 464 0 + 581 007c 8023 movs r3, #128 + 582 007e 5B04 lsls r3, r3, #17 + 583 0080 0A69 ldr r2, [r1, #16] + 584 0082 1343 orrs r3, r2 + 585 0084 0B61 str r3, [r1, #16] + 586 .L27: + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx)|| (STM3 + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the RTC_TAMPCR register */ + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper-> + 587 .loc 1 472 0 + 588 0086 0A68 ldr r2, [r1] + 589 0088 8B68 ldr r3, [r1, #8] + 590 008a 1343 orrs r3, r2 + 591 008c CC68 ldr r4, [r1, #12] + 592 008e 2343 orrs r3, r4 + 593 0090 0C69 ldr r4, [r1, #16] + 594 0092 2343 orrs r3, r4 + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFr + 595 .loc 1 473 0 + 596 0094 4C69 ldr r4, [r1, #20] + 597 0096 2343 orrs r3, r4 + 598 0098 8C69 ldr r4, [r1, #24] + 599 009a 2343 orrs r3, r4 + 600 009c CC69 ldr r4, [r1, #28] + 601 009e 2343 orrs r3, r4 + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTam + 602 .loc 1 474 0 + 603 00a0 0C6A ldr r4, [r1, #32] + 604 00a2 2343 orrs r3, r4 + 605 00a4 496A ldr r1, [r1, #36] + 606 .LVL51: + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFr + 607 .loc 1 472 0 + 608 00a6 0B43 orrs r3, r1 + ARM GAS /tmp/ccjDTEau.s page 20 + + + 609 .LVL52: + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMP + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_ + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF)); + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << + 610 .loc 1 487 0 + 611 00a8 0568 ldr r5, [r0] + 612 00aa 296C ldr r1, [r5, #64] + 613 00ac 5400 lsls r4, r2, #1 + 614 00ae 2243 orrs r2, r4 + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPP + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1 + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1N + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAM + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF)); + 615 .loc 1 492 0 + 616 00b0 084C ldr r4, .L31 + 617 00b2 2243 orrs r2, r4 + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPP + 618 .loc 1 487 0 + 619 00b4 9143 bics r1, r2 + 620 00b6 2964 str r1, [r5, #64] + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #elif defined (STM32L011xx) || defined (STM32L021xx) + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPP + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF)); + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L011xx) || (STM32L021xx) + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR |= tmpreg; + 621 .loc 1 505 0 + 622 00b8 0168 ldr r1, [r0] + 623 00ba 0A6C ldr r2, [r1, #64] + 624 00bc 1343 orrs r3, r2 + 625 .LVL53: + 626 00be 0B64 str r3, [r1, #64] + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 627 .loc 1 507 0 + 628 00c0 2123 movs r3, #33 + 629 00c2 0122 movs r2, #1 + 630 00c4 C254 strb r2, [r0, r3] + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 21 + + + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 631 .loc 1 510 0 + 632 00c6 013B subs r3, r3, #1 + 633 00c8 0022 movs r2, #0 + 634 00ca C254 strb r2, [r0, r3] + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 635 .loc 1 512 0 + 636 00cc 0020 movs r0, #0 + 637 .LVL54: + 638 .L22: + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 639 .loc 1 513 0 + 640 @ sp needed + 641 00ce 30BD pop {r4, r5, pc} + 642 .LVL55: + 643 .L30: + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 644 .loc 1 385 0 + 645 00d0 0220 movs r0, #2 + 646 .LVL56: + 647 00d2 FCE7 b .L22 + 648 .L32: + 649 .align 2 + 650 .L31: + 651 00d4 84FFFF01 .word 33554308 + 652 .cfi_endproc + 653 .LFE43: + 655 .section .text.HAL_RTCEx_SetTamper_IT,"ax",%progbits + 656 .align 1 + 657 .global HAL_RTCEx_SetTamper_IT + 658 .syntax unified + 659 .code 16 + 660 .thumb_func + 661 .fpu softvfp + 663 HAL_RTCEx_SetTamper_IT: + 664 .LFB44: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set Tamper with interrupt. + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note By calling this API we force the tamper interrupt for all tampers. + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param sTamper: Pointer to RTC Tamper. + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 665 .loc 1 523 0 + 666 .cfi_startproc + 667 @ args = 0, pretend = 0, frame = 0 + 668 @ frame_needed = 0, uses_anonymous_args = 0 + 669 .LVL57: + 670 0000 30B5 push {r4, r5, lr} + 671 .LCFI6: + 672 .cfi_def_cfa_offset 12 + 673 .cfi_offset 4, -12 + ARM GAS /tmp/ccjDTEau.s page 22 + + + 674 .cfi_offset 5, -8 + 675 .cfi_offset 14, -4 + 676 .LVL58: + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmpreg = 0U; + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param( IS_RTC_TAMPER(sTamper->Tamper)); + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 677 .loc 1 539 0 + 678 0002 2023 movs r3, #32 + 679 0004 C35C ldrb r3, [r0, r3] + 680 0006 012B cmp r3, #1 + 681 0008 00D1 bne .LCB637 + 682 000a 6DE0 b .L42 @long jump + 683 .LCB637: + 684 .loc 1 539 0 is_stmt 0 discriminator 2 + 685 000c 2023 movs r3, #32 + 686 000e 0122 movs r2, #1 + 687 0010 C254 strb r2, [r0, r3] + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 688 .loc 1 541 0 is_stmt 1 discriminator 2 + 689 0012 0133 adds r3, r3, #1 + 690 0014 0132 adds r2, r2, #1 + 691 0016 C254 strb r2, [r0, r3] + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the tamper trigger */ + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + 692 .loc 1 544 0 discriminator 2 + 693 0018 8B68 ldr r3, [r1, #8] + 694 001a 002B cmp r3, #0 + 695 001c 02D0 beq .L35 + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); + 696 .loc 1 546 0 + 697 001e 0B68 ldr r3, [r1] + 698 0020 5B00 lsls r3, r3, #1 + 699 0022 8B60 str r3, [r1, #8] + 700 .L35: + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + 701 .loc 1 549 0 + 702 0024 CB68 ldr r3, [r1, #12] + 703 0026 002B cmp r3, #0 + 704 0028 15D0 beq .L36 + ARM GAS /tmp/ccjDTEau.s page 23 + + + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase = 0U; + 705 .loc 1 551 0 + 706 002a 0023 movs r3, #0 + 707 002c CB60 str r3, [r1, #12] + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + 708 .loc 1 559 0 + 709 002e 0B68 ldr r3, [r1] + 710 0030 DA07 lsls r2, r3, #31 + 711 0032 02D5 bpl .L37 + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + 712 .loc 1 561 0 + 713 0034 8022 movs r2, #128 + 714 0036 9202 lsls r2, r2, #10 + 715 0038 CA60 str r2, [r1, #12] + 716 .L37: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + 717 .loc 1 571 0 + 718 003a 1A07 lsls r2, r3, #28 + 719 003c 04D5 bpl .L38 + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + 720 .loc 1 573 0 + 721 003e 8022 movs r2, #128 + 722 0040 5203 lsls r2, r2, #13 + 723 0042 CC68 ldr r4, [r1, #12] + 724 0044 2243 orrs r2, r4 + 725 0046 CA60 str r2, [r1, #12] + 726 .L38: + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + 727 .loc 1 579 0 + 728 0048 9B06 lsls r3, r3, #26 + 729 004a 04D5 bpl .L36 + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + ARM GAS /tmp/ccjDTEau.s page 24 + + + 730 .loc 1 581 0 + 731 004c 8023 movs r3, #128 + 732 004e 1B04 lsls r3, r3, #16 + 733 0050 CA68 ldr r2, [r1, #12] + 734 0052 1343 orrs r3, r2 + 735 0054 CB60 str r3, [r1, #12] + 736 .L36: + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + 737 .loc 1 588 0 + 738 0056 0B69 ldr r3, [r1, #16] + 739 0058 002B cmp r3, #0 + 740 005a 15D0 beq .L39 + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag = 0U; + 741 .loc 1 590 0 + 742 005c 0023 movs r3, #0 + 743 005e 0B61 str r3, [r1, #16] + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + 744 .loc 1 597 0 + 745 0060 0B68 ldr r3, [r1] + 746 0062 DA07 lsls r2, r3, #31 + 747 0064 02D5 bpl .L40 + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + 748 .loc 1 599 0 + 749 0066 8022 movs r2, #128 + 750 0068 D202 lsls r2, r2, #11 + 751 006a 0A61 str r2, [r1, #16] + 752 .L40: + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + 753 .loc 1 608 0 + 754 006c 1A07 lsls r2, r3, #28 + 755 006e 04D5 bpl .L41 + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + 756 .loc 1 610 0 + 757 0070 8022 movs r2, #128 + ARM GAS /tmp/ccjDTEau.s page 25 + + + 758 0072 9203 lsls r2, r2, #14 + 759 0074 0C69 ldr r4, [r1, #16] + 760 0076 2243 orrs r2, r4 + 761 0078 0A61 str r2, [r1, #16] + 762 .L41: + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + 763 .loc 1 616 0 + 764 007a 9B06 lsls r3, r3, #26 + 765 007c 04D5 bpl .L39 + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + 766 .loc 1 618 0 + 767 007e 8023 movs r3, #128 + 768 0080 5B04 lsls r3, r3, #17 + 769 0082 0A69 ldr r2, [r1, #16] + 770 0084 1343 orrs r3, r2 + 771 0086 0B61 str r3, [r1, #16] + 772 .L39: + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the RTC_TAMPCR register */ + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper- + 773 .loc 1 626 0 + 774 0088 0A68 ldr r2, [r1] + 775 008a 4B68 ldr r3, [r1, #4] + 776 008c 1343 orrs r3, r2 + 777 008e 8C68 ldr r4, [r1, #8] + 778 0090 2343 orrs r3, r4 + 779 0092 CC68 ldr r4, [r1, #12] + 780 0094 2343 orrs r3, r4 + 781 0096 0C69 ldr r4, [r1, #16] + 782 0098 2343 orrs r3, r4 + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFr + 783 .loc 1 627 0 + 784 009a 4C69 ldr r4, [r1, #20] + 785 009c 2343 orrs r3, r4 + 786 009e 8C69 ldr r4, [r1, #24] + 787 00a0 2343 orrs r3, r4 + 788 00a2 CC69 ldr r4, [r1, #28] + 789 00a4 2343 orrs r3, r4 + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTam + 790 .loc 1 628 0 + 791 00a6 0C6A ldr r4, [r1, #32] + 792 00a8 2343 orrs r3, r4 + 793 00aa 496A ldr r1, [r1, #36] + 794 .LVL59: + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFr + 795 .loc 1 626 0 + ARM GAS /tmp/ccjDTEau.s page 26 + + + 796 00ac 0B43 orrs r3, r1 + 797 .LVL60: + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1 + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPR + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1I + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TA + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF); + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1 + 798 .loc 1 641 0 + 799 00ae 0568 ldr r5, [r0] + 800 00b0 296C ldr r1, [r5, #64] + 801 00b2 5400 lsls r4, r2, #1 + 802 00b4 2243 orrs r2, r4 + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPR + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1I + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NO + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMP + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF); + 803 .loc 1 646 0 + 804 00b6 0D4C ldr r4, .L43 + 805 00b8 2243 orrs r2, r4 + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPR + 806 .loc 1 641 0 + 807 00ba 9143 bics r1, r2 + 808 00bc 2964 str r1, [r5, #64] + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #elif defined (STM32L011xx) || defined (STM32L021xx) + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1 + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPR + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF); + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L011xx) || (STM32L021xx) + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR |= tmpreg; + 809 .loc 1 659 0 + 810 00be 0168 ldr r1, [r0] + 811 00c0 0A6C ldr r2, [r1, #64] + 812 00c2 1343 orrs r3, r2 + 813 .LVL61: + 814 00c4 0B64 str r3, [r1, #64] + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* RTC Tamper Interrupt Configuration: EXTI configuration */ + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + 815 .loc 1 662 0 + 816 00c6 0A4B ldr r3, .L43+4 + 817 00c8 1968 ldr r1, [r3] + ARM GAS /tmp/ccjDTEau.s page 27 + + + 818 00ca 8022 movs r2, #128 + 819 00cc 1203 lsls r2, r2, #12 + 820 00ce 1143 orrs r1, r2 + 821 00d0 1960 str r1, [r3] + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); + 822 .loc 1 664 0 + 823 00d2 9968 ldr r1, [r3, #8] + 824 00d4 0A43 orrs r2, r1 + 825 00d6 9A60 str r2, [r3, #8] + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 826 .loc 1 666 0 + 827 00d8 2123 movs r3, #33 + 828 00da 0122 movs r2, #1 + 829 00dc C254 strb r2, [r0, r3] + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 830 .loc 1 669 0 + 831 00de 013B subs r3, r3, #1 + 832 00e0 0022 movs r2, #0 + 833 00e2 C254 strb r2, [r0, r3] + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 834 .loc 1 671 0 + 835 00e4 0020 movs r0, #0 + 836 .LVL62: + 837 .L34: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 838 .loc 1 672 0 + 839 @ sp needed + 840 00e6 30BD pop {r4, r5, pc} + 841 .LVL63: + 842 .L42: + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 843 .loc 1 539 0 + 844 00e8 0220 movs r0, #2 + 845 .LVL64: + 846 00ea FCE7 b .L34 + 847 .L44: + 848 .align 2 + 849 .L43: + 850 00ec 84FFFF01 .word 33554308 + 851 00f0 00040140 .word 1073808384 + 852 .cfi_endproc + 853 .LFE44: + 855 .section .text.HAL_RTCEx_DeactivateTamper,"ax",%progbits + 856 .align 1 + 857 .global HAL_RTCEx_DeactivateTamper + 858 .syntax unified + 859 .code 16 + 860 .thumb_func + 861 .fpu softvfp + 863 HAL_RTCEx_DeactivateTamper: + 864 .LFB45: + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 28 + + + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Deactivate Tamper. + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Tamper: Selected tamper pin. + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2 for STM32L05x/6x. + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 f + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 865 .loc 1 683 0 + 866 .cfi_startproc + 867 @ args = 0, pretend = 0, frame = 0 + 868 @ frame_needed = 0, uses_anonymous_args = 0 + 869 .LVL65: + 870 0000 10B5 push {r4, lr} + 871 .LCFI7: + 872 .cfi_def_cfa_offset 8 + 873 .cfi_offset 4, -8 + 874 .cfi_offset 14, -4 + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param( IS_RTC_TAMPER(Tamper)); + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 875 .loc 1 687 0 + 876 0002 2023 movs r3, #32 + 877 0004 C35C ldrb r3, [r0, r3] + 878 0006 012B cmp r3, #1 + 879 0008 26D0 beq .L50 + 880 .loc 1 687 0 is_stmt 0 discriminator 2 + 881 000a 0122 movs r2, #1 + 882 000c 2023 movs r3, #32 + 883 000e C254 strb r2, [r0, r3] + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 884 .loc 1 689 0 is_stmt 1 discriminator 2 + 885 0010 0133 adds r3, r3, #1 + 886 0012 0224 movs r4, #2 + 887 0014 C454 strb r4, [r0, r3] + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the selected Tamper pin */ + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); + 888 .loc 1 692 0 discriminator 2 + 889 0016 0468 ldr r4, [r0] + 890 0018 236C ldr r3, [r4, #64] + 891 001a 8B43 bics r3, r1 + 892 001c 2364 str r3, [r4, #64] + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if ((Tamper & RTC_TAMPER_1) != 0U) + 893 .loc 1 699 0 discriminator 2 + 894 001e 0A42 tst r2, r1 + 895 0020 04D0 beq .L47 + ARM GAS /tmp/ccjDTEau.s page 29 + + + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the Tamper1 interrupt */ + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); + 896 .loc 1 702 0 + 897 0022 0268 ldr r2, [r0] + 898 0024 136C ldr r3, [r2, #64] + 899 0026 0D4C ldr r4, .L51 + 900 0028 2340 ands r3, r4 + 901 002a 1364 str r3, [r2, #64] + 902 .L47: + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if ((Tamper & RTC_TAMPER_2) != 0U) + 903 .loc 1 712 0 + 904 002c 0B07 lsls r3, r1, #28 + 905 002e 04D5 bpl .L48 + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the Tamper2 interrupt */ + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); + 906 .loc 1 715 0 + 907 0030 0268 ldr r2, [r0] + 908 0032 136C ldr r3, [r2, #64] + 909 0034 0A4C ldr r4, .L51+4 + 910 0036 2340 ands r3, r4 + 911 0038 1364 str r3, [r2, #64] + 912 .L48: + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if ((Tamper & RTC_TAMPER_3) != 0U) + 913 .loc 1 722 0 + 914 003a 8B06 lsls r3, r1, #26 + 915 003c 04D5 bpl .L49 + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the Tamper3 interrupt */ + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); + 916 .loc 1 725 0 + 917 003e 0268 ldr r2, [r0] + 918 0040 136C ldr r3, [r2, #64] + 919 0042 0849 ldr r1, .L51+8 + 920 .LVL66: + 921 0044 0B40 ands r3, r1 + 922 0046 1364 str r3, [r2, #64] + 923 .L49: + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + ARM GAS /tmp/ccjDTEau.s page 30 + + + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L0 + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 924 .loc 1 732 0 + 925 0048 2123 movs r3, #33 + 926 004a 0122 movs r2, #1 + 927 004c C254 strb r2, [r0, r3] + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 928 .loc 1 735 0 + 929 004e 013B subs r3, r3, #1 + 930 0050 0022 movs r2, #0 + 931 0052 C254 strb r2, [r0, r3] + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 932 .loc 1 737 0 + 933 0054 0020 movs r0, #0 + 934 .LVL67: + 935 .L46: + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 936 .loc 1 738 0 + 937 @ sp needed + 938 0056 10BD pop {r4, pc} + 939 .LVL68: + 940 .L50: + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 941 .loc 1 687 0 + 942 0058 0220 movs r0, #2 + 943 .LVL69: + 944 005a FCE7 b .L46 + 945 .L52: + 946 .align 2 + 947 .L51: + 948 005c FBFFFEFF .word -65541 + 949 0060 FBFFF7FF .word -524293 + 950 0064 FBFFBFFF .word -4194309 + 951 .cfi_endproc + 952 .LFE45: + 954 .section .text.HAL_RTCEx_TimeStampEventCallback,"ax",%progbits + 955 .align 1 + 956 .weak HAL_RTCEx_TimeStampEventCallback + 957 .syntax unified + 958 .code 16 + 959 .thumb_func + 960 .fpu softvfp + 962 HAL_RTCEx_TimeStampEventCallback: + 963 .LFB47: + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle TimeStamp interrupt request. + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + ARM GAS /tmp/ccjDTEau.s page 31 + + + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the TimeStamp interrupt source enable status */ + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the TIMESTAMP Interrupt */ + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET) + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* TIMESTAMP callback */ + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_TimeStampEventCallback(hrtc); + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the TIMESTAMP interrupt pending bit */ + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the Tamper1 interrupts source enable status */ + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the Tamper1 Interrupt */ + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET) + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Tamper1 callback */ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_Tamper1EventCallback(hrtc); + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper1 interrupt pending bit */ + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the Tamper2 interrupts source enable status */ + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the Tamper2 Interrupt */ + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET) + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Tamper2 callback */ + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_Tamper2EventCallback(hrtc); + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper2 interrupt pending bit */ + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + ARM GAS /tmp/ccjDTEau.s page 32 + + + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the Tamper3 interrupts source enable status */ + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the Tamper3 Interrupt */ + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET) + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Tamper3 callback */ + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_Tamper3EventCallback(hrtc); + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper3 interrupt pending bit */ + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L011xx) || (STM32L021xx) + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief TimeStamp callback. + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 964 .loc 1 837 0 + 965 .cfi_startproc + 966 @ args = 0, pretend = 0, frame = 0 + 967 @ frame_needed = 0, uses_anonymous_args = 0 + 968 @ link register save eliminated. + 969 .LVL70: + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 970 .loc 1 844 0 + 971 @ sp needed + 972 0000 7047 bx lr + 973 .cfi_endproc + 974 .LFE47: + 976 .section .text.HAL_RTCEx_Tamper1EventCallback,"ax",%progbits + 977 .align 1 + 978 .weak HAL_RTCEx_Tamper1EventCallback + 979 .syntax unified + 980 .code 16 + ARM GAS /tmp/ccjDTEau.s page 33 + + + 981 .thumb_func + 982 .fpu softvfp + 984 HAL_RTCEx_Tamper1EventCallback: + 985 .LFB48: + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Tamper 1 callback. + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 986 .loc 1 852 0 + 987 .cfi_startproc + 988 @ args = 0, pretend = 0, frame = 0 + 989 @ frame_needed = 0, uses_anonymous_args = 0 + 990 @ link register save eliminated. + 991 .LVL71: + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 992 .loc 1 859 0 + 993 @ sp needed + 994 0000 7047 bx lr + 995 .cfi_endproc + 996 .LFE48: + 998 .section .text.HAL_RTCEx_Tamper2EventCallback,"ax",%progbits + 999 .align 1 + 1000 .weak HAL_RTCEx_Tamper2EventCallback + 1001 .syntax unified + 1002 .code 16 + 1003 .thumb_func + 1004 .fpu softvfp + 1006 HAL_RTCEx_Tamper2EventCallback: + 1007 .LFB49: + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Tamper 2 callback. + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1008 .loc 1 867 0 + 1009 .cfi_startproc + 1010 @ args = 0, pretend = 0, frame = 0 + 1011 @ frame_needed = 0, uses_anonymous_args = 0 + 1012 @ link register save eliminated. + 1013 .LVL72: + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + ARM GAS /tmp/ccjDTEau.s page 34 + + + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1014 .loc 1 874 0 + 1015 @ sp needed + 1016 0000 7047 bx lr + 1017 .cfi_endproc + 1018 .LFE49: + 1020 .section .text.HAL_RTCEx_Tamper3EventCallback,"ax",%progbits + 1021 .align 1 + 1022 .weak HAL_RTCEx_Tamper3EventCallback + 1023 .syntax unified + 1024 .code 16 + 1025 .thumb_func + 1026 .fpu softvfp + 1028 HAL_RTCEx_Tamper3EventCallback: + 1029 .LFB50: + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Tamper 3 callback. + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1030 .loc 1 887 0 + 1031 .cfi_startproc + 1032 @ args = 0, pretend = 0, frame = 0 + 1033 @ frame_needed = 0, uses_anonymous_args = 0 + 1034 @ link register save eliminated. + 1035 .LVL73: + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1036 .loc 1 894 0 + 1037 @ sp needed + 1038 0000 7047 bx lr + 1039 .cfi_endproc + 1040 .LFE50: + 1042 .section .text.HAL_RTCEx_TamperTimeStampIRQHandler,"ax",%progbits + 1043 .align 1 + 1044 .global HAL_RTCEx_TamperTimeStampIRQHandler + 1045 .syntax unified + 1046 .code 16 + 1047 .thumb_func + 1048 .fpu softvfp + 1050 HAL_RTCEx_TamperTimeStampIRQHandler: + 1051 .LFB46: + ARM GAS /tmp/ccjDTEau.s page 35 + + + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the TimeStamp interrupt source enable status */ + 1052 .loc 1 746 0 + 1053 .cfi_startproc + 1054 @ args = 0, pretend = 0, frame = 0 + 1055 @ frame_needed = 0, uses_anonymous_args = 0 + 1056 .LVL74: + 1057 0000 10B5 push {r4, lr} + 1058 .LCFI8: + 1059 .cfi_def_cfa_offset 8 + 1060 .cfi_offset 4, -8 + 1061 .cfi_offset 14, -4 + 1062 0002 0400 movs r4, r0 + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1063 .loc 1 748 0 + 1064 0004 0368 ldr r3, [r0] + 1065 0006 9A68 ldr r2, [r3, #8] + 1066 0008 1204 lsls r2, r2, #16 + 1067 000a 02D5 bpl .L58 + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1068 .loc 1 751 0 + 1069 000c DB68 ldr r3, [r3, #12] + 1070 000e 1B05 lsls r3, r3, #20 + 1071 0010 1FD4 bmi .L62 + 1072 .LVL75: + 1073 .L58: + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1074 .loc 1 768 0 + 1075 0012 2368 ldr r3, [r4] + 1076 0014 196C ldr r1, [r3, #64] + 1077 0016 244A ldr r2, .L66 + 1078 0018 1142 tst r1, r2 + 1079 001a 02D0 beq .L59 + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1080 .loc 1 771 0 + 1081 001c DB68 ldr r3, [r3, #12] + 1082 001e 9B04 lsls r3, r3, #18 + 1083 0020 21D4 bmi .L63 + 1084 .L59: + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1085 .loc 1 788 0 + 1086 0022 2368 ldr r3, [r4] + 1087 0024 196C ldr r1, [r3, #64] + 1088 0026 214A ldr r2, .L66+4 + 1089 0028 1142 tst r1, r2 + 1090 002a 02D0 beq .L60 + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1091 .loc 1 791 0 + 1092 002c DB68 ldr r3, [r3, #12] + 1093 002e 5B04 lsls r3, r3, #17 + 1094 0030 24D4 bmi .L64 + 1095 .L60: + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1096 .loc 1 806 0 + 1097 0032 2368 ldr r3, [r4] + 1098 0034 196C ldr r1, [r3, #64] + 1099 0036 1E4A ldr r2, .L66+8 + 1100 0038 1142 tst r1, r2 + ARM GAS /tmp/ccjDTEau.s page 36 + + + 1101 003a 02D0 beq .L61 + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1102 .loc 1 809 0 + 1103 003c DB68 ldr r3, [r3, #12] + 1104 003e 1B04 lsls r3, r3, #16 + 1105 0040 27D4 bmi .L65 + 1106 .L61: + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1107 .loc 1 825 0 + 1108 0042 1C4B ldr r3, .L66+12 + 1109 0044 8022 movs r2, #128 + 1110 0046 1203 lsls r2, r2, #12 + 1111 0048 5A61 str r2, [r3, #20] + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1112 .loc 1 828 0 + 1113 004a 2123 movs r3, #33 + 1114 004c 0122 movs r2, #1 + 1115 004e E254 strb r2, [r4, r3] + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1116 .loc 1 829 0 + 1117 @ sp needed + 1118 .LVL76: + 1119 0050 10BD pop {r4, pc} + 1120 .LVL77: + 1121 .L62: + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1122 .loc 1 754 0 + 1123 0052 FFF7FEFF bl HAL_RTCEx_TimeStampEventCallback + 1124 .LVL78: + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1125 .loc 1 757 0 + 1126 0056 2168 ldr r1, [r4] + 1127 0058 CA68 ldr r2, [r1, #12] + 1128 005a FF23 movs r3, #255 + 1129 005c 1A40 ands r2, r3 + 1130 005e 164B ldr r3, .L66+16 + 1131 0060 1343 orrs r3, r2 + 1132 0062 CB60 str r3, [r1, #12] + 1133 0064 D5E7 b .L58 + 1134 .L63: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1135 .loc 1 774 0 + 1136 0066 2000 movs r0, r4 + 1137 0068 FFF7FEFF bl HAL_RTCEx_Tamper1EventCallback + 1138 .LVL79: + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1139 .loc 1 777 0 + 1140 006c 2168 ldr r1, [r4] + 1141 006e CA68 ldr r2, [r1, #12] + 1142 0070 FF23 movs r3, #255 + 1143 0072 1A40 ands r2, r3 + 1144 0074 114B ldr r3, .L66+20 + 1145 0076 1343 orrs r3, r2 + 1146 0078 CB60 str r3, [r1, #12] + 1147 007a D2E7 b .L59 + 1148 .L64: + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 37 + + + 1149 .loc 1 794 0 + 1150 007c 2000 movs r0, r4 + 1151 007e FFF7FEFF bl HAL_RTCEx_Tamper2EventCallback + 1152 .LVL80: + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1153 .loc 1 797 0 + 1154 0082 2168 ldr r1, [r4] + 1155 0084 CA68 ldr r2, [r1, #12] + 1156 0086 FF23 movs r3, #255 + 1157 0088 1A40 ands r2, r3 + 1158 008a 0D4B ldr r3, .L66+24 + 1159 008c 1343 orrs r3, r2 + 1160 008e CB60 str r3, [r1, #12] + 1161 0090 CFE7 b .L60 + 1162 .L65: + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1163 .loc 1 812 0 + 1164 0092 2000 movs r0, r4 + 1165 0094 FFF7FEFF bl HAL_RTCEx_Tamper3EventCallback + 1166 .LVL81: + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1167 .loc 1 815 0 + 1168 0098 2168 ldr r1, [r4] + 1169 009a CA68 ldr r2, [r1, #12] + 1170 009c FF23 movs r3, #255 + 1171 009e 1A40 ands r2, r3 + 1172 00a0 084B ldr r3, .L66+28 + 1173 00a2 1343 orrs r3, r2 + 1174 00a4 CB60 str r3, [r1, #12] + 1175 00a6 CCE7 b .L61 + 1176 .L67: + 1177 .align 2 + 1178 .L66: + 1179 00a8 04000100 .word 65540 + 1180 00ac 04000800 .word 524292 + 1181 00b0 04004000 .word 4194308 + 1182 00b4 00040140 .word 1073808384 + 1183 00b8 7FF7FFFF .word -2177 + 1184 00bc 7FDFFFFF .word -8321 + 1185 00c0 7FBFFFFF .word -16513 + 1186 00c4 7F7FFFFF .word -32897 + 1187 .cfi_endproc + 1188 .LFE46: + 1190 .section .text.HAL_RTCEx_PollForTimeStampEvent,"ax",%progbits + 1191 .align 1 + 1192 .global HAL_RTCEx_PollForTimeStampEvent + 1193 .syntax unified + 1194 .code 16 + 1195 .thumb_func + 1196 .fpu softvfp + 1198 HAL_RTCEx_PollForTimeStampEvent: + 1199 .LFB51: + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L0 + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 38 + + + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle TimeStamp polling request. + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1200 .loc 1 908 0 + 1201 .cfi_startproc + 1202 @ args = 0, pretend = 0, frame = 0 + 1203 @ frame_needed = 0, uses_anonymous_args = 0 + 1204 .LVL82: + 1205 0000 70B5 push {r4, r5, r6, lr} + 1206 .LCFI9: + 1207 .cfi_def_cfa_offset 16 + 1208 .cfi_offset 4, -16 + 1209 .cfi_offset 5, -12 + 1210 .cfi_offset 6, -8 + 1211 .cfi_offset 14, -4 + 1212 0002 0500 movs r5, r0 + 1213 0004 0E00 movs r6, r1 + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 1214 .loc 1 909 0 + 1215 0006 FFF7FEFF bl HAL_GetTick + 1216 .LVL83: + 1217 000a 0400 movs r4, r0 + 1218 .LVL84: + 1219 .L72: + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + 1220 .loc 1 911 0 + 1221 000c 2B68 ldr r3, [r5] + 1222 000e DA68 ldr r2, [r3, #12] + 1223 0010 1205 lsls r2, r2, #20 + 1224 0012 1BD4 bmi .L75 + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + 1225 .loc 1 913 0 + 1226 0014 DA68 ldr r2, [r3, #12] + 1227 0016 D204 lsls r2, r2, #19 + 1228 0018 0DD4 bmi .L76 + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the TIMESTAMP OverRun Flag */ + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change TIMESTAMP state */ + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_ERROR; + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_ERROR; + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 1229 .loc 1 924 0 + 1230 001a 731C adds r3, r6, #1 + 1231 001c F6D0 beq .L72 + ARM GAS /tmp/ccjDTEau.s page 39 + + + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 1232 .loc 1 926 0 + 1233 001e 002E cmp r6, #0 + 1234 0020 04D0 beq .L73 + 1235 .loc 1 926 0 is_stmt 0 discriminator 1 + 1236 0022 FFF7FEFF bl HAL_GetTick + 1237 .LVL85: + 1238 0026 001B subs r0, r0, r4 + 1239 0028 B042 cmp r0, r6 + 1240 002a EFD9 bls .L72 + 1241 .L73: + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1242 .loc 1 928 0 is_stmt 1 + 1243 002c 2123 movs r3, #33 + 1244 002e 0322 movs r2, #3 + 1245 0030 EA54 strb r2, [r5, r3] + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1246 .loc 1 929 0 + 1247 0032 0320 movs r0, #3 + 1248 0034 0EE0 b .L71 + 1249 .L76: + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1250 .loc 1 916 0 + 1251 0036 D968 ldr r1, [r3, #12] + 1252 0038 FF22 movs r2, #255 + 1253 003a 1140 ands r1, r2 + 1254 003c 064A ldr r2, .L77 + 1255 003e 0A43 orrs r2, r1 + 1256 0040 DA60 str r2, [r3, #12] + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1257 .loc 1 919 0 + 1258 0042 2123 movs r3, #33 + 1259 0044 0422 movs r2, #4 + 1260 0046 EA54 strb r2, [r5, r3] + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1261 .loc 1 921 0 + 1262 0048 0120 movs r0, #1 + 1263 004a 03E0 b .L71 + 1264 .L75: + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1265 .loc 1 935 0 + 1266 004c 2123 movs r3, #33 + 1267 004e 0122 movs r2, #1 + 1268 0050 EA54 strb r2, [r5, r3] + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 1269 .loc 1 937 0 + 1270 0052 0020 movs r0, #0 + 1271 .L71: + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + ARM GAS /tmp/ccjDTEau.s page 40 + + + 1272 .loc 1 938 0 + 1273 @ sp needed + 1274 .LVL86: + 1275 .LVL87: + 1276 .LVL88: + 1277 0054 70BD pop {r4, r5, r6, pc} + 1278 .L78: + 1279 0056 C046 .align 2 + 1280 .L77: + 1281 0058 7FEFFFFF .word -4225 + 1282 .cfi_endproc + 1283 .LFE51: + 1285 .section .text.HAL_RTCEx_PollForTamper1Event,"ax",%progbits + 1286 .align 1 + 1287 .global HAL_RTCEx_PollForTamper1Event + 1288 .syntax unified + 1289 .code 16 + 1290 .thumb_func + 1291 .fpu softvfp + 1293 HAL_RTCEx_PollForTamper1Event: + 1294 .LFB52: + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Tamper 1 Polling. + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1295 .loc 1 952 0 + 1296 .cfi_startproc + 1297 @ args = 0, pretend = 0, frame = 0 + 1298 @ frame_needed = 0, uses_anonymous_args = 0 + 1299 .LVL89: + 1300 0000 70B5 push {r4, r5, r6, lr} + 1301 .LCFI10: + 1302 .cfi_def_cfa_offset 16 + 1303 .cfi_offset 4, -16 + 1304 .cfi_offset 5, -12 + 1305 .cfi_offset 6, -8 + 1306 .cfi_offset 14, -4 + 1307 0002 0400 movs r4, r0 + 1308 0004 0D00 movs r5, r1 + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 1309 .loc 1 953 0 + 1310 0006 FFF7FEFF bl HAL_GetTick + 1311 .LVL90: + 1312 000a 0600 movs r6, r0 + 1313 .LVL91: + 1314 .L81: + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 41 + + + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the status of the Interrupt */ + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) + 1315 .loc 1 956 0 + 1316 000c 2368 ldr r3, [r4] + 1317 000e DA68 ldr r2, [r3, #12] + 1318 0010 9204 lsls r2, r2, #18 + 1319 0012 0DD4 bmi .L85 + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 1320 .loc 1 958 0 + 1321 0014 6B1C adds r3, r5, #1 + 1322 0016 F9D0 beq .L81 + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 1323 .loc 1 960 0 + 1324 0018 002D cmp r5, #0 + 1325 001a 04D0 beq .L82 + 1326 .loc 1 960 0 is_stmt 0 discriminator 1 + 1327 001c FFF7FEFF bl HAL_GetTick + 1328 .LVL92: + 1329 0020 801B subs r0, r0, r6 + 1330 0022 A842 cmp r0, r5 + 1331 0024 F2D9 bls .L81 + 1332 .L82: + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1333 .loc 1 962 0 is_stmt 1 + 1334 0026 2123 movs r3, #33 + 1335 0028 0322 movs r2, #3 + 1336 002a E254 strb r2, [r4, r3] + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1337 .loc 1 963 0 + 1338 002c 0320 movs r0, #3 + 1339 002e 09E0 b .L83 + 1340 .L85: + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper Flag */ + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + 1341 .loc 1 969 0 + 1342 0030 D968 ldr r1, [r3, #12] + 1343 0032 FF22 movs r2, #255 + 1344 0034 1140 ands r1, r2 + 1345 0036 044A ldr r2, .L86 + 1346 0038 0A43 orrs r2, r1 + 1347 003a DA60 str r2, [r3, #12] + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1348 .loc 1 972 0 + 1349 003c 2123 movs r3, #33 + 1350 003e 0122 movs r2, #1 + 1351 0040 E254 strb r2, [r4, r3] + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + ARM GAS /tmp/ccjDTEau.s page 42 + + + 1352 .loc 1 974 0 + 1353 0042 0020 movs r0, #0 + 1354 .L83: + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1355 .loc 1 975 0 + 1356 @ sp needed + 1357 .LVL93: + 1358 .LVL94: + 1359 .LVL95: + 1360 0044 70BD pop {r4, r5, r6, pc} + 1361 .L87: + 1362 0046 C046 .align 2 + 1363 .L86: + 1364 0048 7FDFFFFF .word -8321 + 1365 .cfi_endproc + 1366 .LFE52: + 1368 .section .text.HAL_RTCEx_PollForTamper2Event,"ax",%progbits + 1369 .align 1 + 1370 .global HAL_RTCEx_PollForTamper2Event + 1371 .syntax unified + 1372 .code 16 + 1373 .thumb_func + 1374 .fpu softvfp + 1376 HAL_RTCEx_PollForTamper2Event: + 1377 .LFB53: + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L031xx) || (STM32L041xx) + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Tamper 2 Polling. + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1378 .loc 1 990 0 + 1379 .cfi_startproc + 1380 @ args = 0, pretend = 0, frame = 0 + 1381 @ frame_needed = 0, uses_anonymous_args = 0 + 1382 .LVL96: + 1383 0000 70B5 push {r4, r5, r6, lr} + 1384 .LCFI11: + 1385 .cfi_def_cfa_offset 16 + 1386 .cfi_offset 4, -16 + 1387 .cfi_offset 5, -12 + 1388 .cfi_offset 6, -8 + 1389 .cfi_offset 14, -4 + 1390 0002 0400 movs r4, r0 + 1391 0004 0D00 movs r5, r1 + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 1392 .loc 1 991 0 + 1393 0006 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccjDTEau.s page 43 + + + 1394 .LVL97: + 1395 000a 0600 movs r6, r0 + 1396 .LVL98: + 1397 .L90: + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the status of the Interrupt */ + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + 1398 .loc 1 994 0 + 1399 000c 2368 ldr r3, [r4] + 1400 000e DA68 ldr r2, [r3, #12] + 1401 0010 5204 lsls r2, r2, #17 + 1402 0012 0DD4 bmi .L94 + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 1403 .loc 1 996 0 + 1404 0014 6B1C adds r3, r5, #1 + 1405 0016 F9D0 beq .L90 + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 1406 .loc 1 998 0 + 1407 0018 002D cmp r5, #0 + 1408 001a 04D0 beq .L91 + 1409 .loc 1 998 0 is_stmt 0 discriminator 1 + 1410 001c FFF7FEFF bl HAL_GetTick + 1411 .LVL99: + 1412 0020 801B subs r0, r0, r6 + 1413 0022 A842 cmp r0, r5 + 1414 0024 F2D9 bls .L90 + 1415 .L91: + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1416 .loc 1 1000 0 is_stmt 1 + 1417 0026 2123 movs r3, #33 + 1418 0028 0322 movs r2, #3 + 1419 002a E254 strb r2, [r4, r3] +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1420 .loc 1 1001 0 + 1421 002c 0320 movs r0, #3 + 1422 002e 09E0 b .L92 + 1423 .L94: +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper Flag */ +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + 1424 .loc 1 1007 0 + 1425 0030 D968 ldr r1, [r3, #12] + 1426 0032 FF22 movs r2, #255 + 1427 0034 1140 ands r1, r2 + 1428 0036 044A ldr r2, .L95 + 1429 0038 0A43 orrs r2, r1 + 1430 003a DA60 str r2, [r3, #12] +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1431 .loc 1 1010 0 + ARM GAS /tmp/ccjDTEau.s page 44 + + + 1432 003c 2123 movs r3, #33 + 1433 003e 0122 movs r2, #1 + 1434 0040 E254 strb r2, [r4, r3] +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 1435 .loc 1 1012 0 + 1436 0042 0020 movs r0, #0 + 1437 .L92: +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1438 .loc 1 1013 0 + 1439 @ sp needed + 1440 .LVL100: + 1441 .LVL101: + 1442 .LVL102: + 1443 0044 70BD pop {r4, r5, r6, pc} + 1444 .L96: + 1445 0046 C046 .align 2 + 1446 .L95: + 1447 0048 7FBFFFFF .word -16513 + 1448 .cfi_endproc + 1449 .LFE53: + 1451 .section .text.HAL_RTCEx_PollForTamper3Event,"ax",%progbits + 1452 .align 1 + 1453 .global HAL_RTCEx_PollForTamper3Event + 1454 .syntax unified + 1455 .code 16 + 1456 .thumb_func + 1457 .fpu softvfp + 1459 HAL_RTCEx_PollForTamper3Event: + 1460 .LFB54: +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Tamper 3 Polling. +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1461 .loc 1 1027 0 + 1462 .cfi_startproc + 1463 @ args = 0, pretend = 0, frame = 0 + 1464 @ frame_needed = 0, uses_anonymous_args = 0 + 1465 .LVL103: + 1466 0000 70B5 push {r4, r5, r6, lr} + 1467 .LCFI12: + 1468 .cfi_def_cfa_offset 16 + 1469 .cfi_offset 4, -16 + 1470 .cfi_offset 5, -12 + 1471 .cfi_offset 6, -8 + 1472 .cfi_offset 14, -4 + 1473 0002 0400 movs r4, r0 + ARM GAS /tmp/ccjDTEau.s page 45 + + + 1474 0004 0D00 movs r5, r1 +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 1475 .loc 1 1028 0 + 1476 0006 FFF7FEFF bl HAL_GetTick + 1477 .LVL104: + 1478 000a 0600 movs r6, r0 + 1479 .LVL105: + 1480 .L99: +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the status of the Interrupt */ +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) + 1481 .loc 1 1031 0 + 1482 000c 2368 ldr r3, [r4] + 1483 000e DA68 ldr r2, [r3, #12] + 1484 0010 1204 lsls r2, r2, #16 + 1485 0012 0DD4 bmi .L103 +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 1486 .loc 1 1033 0 + 1487 0014 6B1C adds r3, r5, #1 + 1488 0016 F9D0 beq .L99 +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 1489 .loc 1 1035 0 + 1490 0018 002D cmp r5, #0 + 1491 001a 04D0 beq .L100 + 1492 .loc 1 1035 0 is_stmt 0 discriminator 1 + 1493 001c FFF7FEFF bl HAL_GetTick + 1494 .LVL106: + 1495 0020 801B subs r0, r0, r6 + 1496 0022 A842 cmp r0, r5 + 1497 0024 F2D9 bls .L99 + 1498 .L100: +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1499 .loc 1 1037 0 is_stmt 1 + 1500 0026 2123 movs r3, #33 + 1501 0028 0322 movs r2, #3 + 1502 002a E254 strb r2, [r4, r3] +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1503 .loc 1 1038 0 + 1504 002c 0320 movs r0, #3 + 1505 002e 09E0 b .L101 + 1506 .L103: +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Tamper Flag */ +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); + 1507 .loc 1 1044 0 + 1508 0030 D968 ldr r1, [r3, #12] + 1509 0032 FF22 movs r2, #255 + 1510 0034 1140 ands r1, r2 + 1511 0036 044A ldr r2, .L104 + 1512 0038 0A43 orrs r2, r1 + 1513 003a DA60 str r2, [r3, #12] + ARM GAS /tmp/ccjDTEau.s page 46 + + +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1514 .loc 1 1047 0 + 1515 003c 2123 movs r3, #33 + 1516 003e 0122 movs r2, #1 + 1517 0040 E254 strb r2, [r4, r3] +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 1518 .loc 1 1049 0 + 1519 0042 0020 movs r0, #0 + 1520 .L101: +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1521 .loc 1 1050 0 + 1522 @ sp needed + 1523 .LVL107: + 1524 .LVL108: + 1525 .LVL109: + 1526 0044 70BD pop {r4, r5, r6, pc} + 1527 .L105: + 1528 0046 C046 .align 2 + 1529 .L104: + 1530 0048 7F7FFFFF .word -32897 + 1531 .cfi_endproc + 1532 .LFE54: + 1534 .section .text.HAL_RTCEx_SetWakeUpTimer,"ax",%progbits + 1535 .align 1 + 1536 .global HAL_RTCEx_SetWakeUpTimer + 1537 .syntax unified + 1538 .code 16 + 1539 .thumb_func + 1540 .fpu softvfp + 1542 HAL_RTCEx_SetWakeUpTimer: + 1543 .LFB55: +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** #endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L0 +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @} +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx_Exported_Functions_Group2 +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief RTC Wake-up functions +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @verbatim +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ##### RTC Wake-up functions ##### +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] This section provides functions allowing to configure Wake-up feature +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @endverbatim +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** + ARM GAS /tmp/ccjDTEau.s page 47 + + +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set wake up timer. +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param WakeUpCounter: Wake up counter +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param WakeUpClock: Wake up clock +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_ +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1544 .loc 1 1081 0 + 1545 .cfi_startproc + 1546 @ args = 0, pretend = 0, frame = 0 + 1547 @ frame_needed = 0, uses_anonymous_args = 0 + 1548 .LVL110: + 1549 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1550 .LCFI13: + 1551 .cfi_def_cfa_offset 24 + 1552 .cfi_offset 3, -24 + 1553 .cfi_offset 4, -20 + 1554 .cfi_offset 5, -16 + 1555 .cfi_offset 6, -12 + 1556 .cfi_offset 7, -8 + 1557 .cfi_offset 14, -4 + 1558 0002 0400 movs r4, r0 + 1559 0004 0D00 movs r5, r1 + 1560 0006 1600 movs r6, r2 + 1561 .LVL111: +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = 0U; +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 1562 .loc 1 1089 0 + 1563 0008 2023 movs r3, #32 + 1564 000a C35C ldrb r3, [r0, r3] + 1565 000c 012B cmp r3, #1 + 1566 000e 61D0 beq .L113 + 1567 .loc 1 1089 0 is_stmt 0 discriminator 2 + 1568 0010 2023 movs r3, #32 + 1569 0012 0122 movs r2, #1 + 1570 .LVL112: + 1571 0014 C254 strb r2, [r0, r3] +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 1572 .loc 1 1091 0 is_stmt 1 discriminator 2 + 1573 0016 0133 adds r3, r3, #1 + 1574 0018 0132 adds r2, r2, #1 + 1575 001a C254 strb r2, [r0, r3] +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 1576 .loc 1 1094 0 discriminator 2 + 1577 001c 0368 ldr r3, [r0] + 1578 001e C832 adds r2, r2, #200 + 1579 0020 5A62 str r2, [r3, #36] + ARM GAS /tmp/ccjDTEau.s page 48 + + + 1580 0022 0368 ldr r3, [r0] + 1581 0024 773A subs r2, r2, #119 + 1582 0026 5A62 str r2, [r3, #36] +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){ + 1583 .loc 1 1097 0 discriminator 2 + 1584 0028 0368 ldr r3, [r0] + 1585 002a 9B68 ldr r3, [r3, #8] + 1586 002c 5B05 lsls r3, r3, #21 + 1587 002e 18D5 bpl .L108 +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 1588 .loc 1 1098 0 + 1589 0030 FFF7FEFF bl HAL_GetTick + 1590 .LVL113: + 1591 0034 0700 movs r7, r0 + 1592 .LVL114: + 1593 .L109: +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + 1594 .loc 1 1101 0 + 1595 0036 2368 ldr r3, [r4] + 1596 0038 DB68 ldr r3, [r3, #12] + 1597 003a 5B07 lsls r3, r3, #29 + 1598 003c 11D5 bpl .L108 +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 1599 .loc 1 1103 0 + 1600 003e FFF7FEFF bl HAL_GetTick + 1601 .LVL115: + 1602 0042 C01B subs r0, r0, r7 + 1603 0044 FA23 movs r3, #250 + 1604 0046 9B00 lsls r3, r3, #2 + 1605 0048 9842 cmp r0, r3 + 1606 004a F4D9 bls .L109 +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1607 .loc 1 1106 0 + 1608 004c 2368 ldr r3, [r4] + 1609 004e FF22 movs r2, #255 + 1610 0050 5A62 str r2, [r3, #36] +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1611 .loc 1 1108 0 + 1612 0052 2123 movs r3, #33 + 1613 0054 FC3A subs r2, r2, #252 + 1614 0056 E254 strb r2, [r4, r3] +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1615 .loc 1 1111 0 + 1616 0058 013B subs r3, r3, #1 + 1617 005a 0022 movs r2, #0 + 1618 005c E254 strb r2, [r4, r3] +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 49 + + +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1619 .loc 1 1113 0 + 1620 005e 0320 movs r0, #3 + 1621 0060 37E0 b .L107 + 1622 .LVL116: + 1623 .L108: +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + 1624 .loc 1 1118 0 + 1625 0062 2268 ldr r2, [r4] + 1626 0064 9368 ldr r3, [r2, #8] + 1627 0066 1C49 ldr r1, .L115 + 1628 0068 0B40 ands r3, r1 + 1629 006a 9360 str r3, [r2, #8] +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 1630 .loc 1 1120 0 + 1631 006c FFF7FEFF bl HAL_GetTick + 1632 .LVL117: + 1633 0070 0700 movs r7, r0 + 1634 .LVL118: + 1635 .L111: +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + 1636 .loc 1 1123 0 + 1637 0072 2368 ldr r3, [r4] + 1638 0074 DA68 ldr r2, [r3, #12] + 1639 0076 5207 lsls r2, r2, #29 + 1640 0078 11D4 bmi .L114 +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 1641 .loc 1 1125 0 + 1642 007a FFF7FEFF bl HAL_GetTick + 1643 .LVL119: + 1644 007e C01B subs r0, r0, r7 + 1645 0080 FA23 movs r3, #250 + 1646 0082 9B00 lsls r3, r3, #2 + 1647 0084 9842 cmp r0, r3 + 1648 0086 F4D9 bls .L111 +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1649 .loc 1 1128 0 + 1650 0088 2368 ldr r3, [r4] + 1651 008a FF22 movs r2, #255 + 1652 008c 5A62 str r2, [r3, #36] +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1653 .loc 1 1130 0 + 1654 008e 2123 movs r3, #33 + 1655 0090 FC3A subs r2, r2, #252 + 1656 0092 E254 strb r2, [r4, r3] +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 50 + + +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1657 .loc 1 1133 0 + 1658 0094 013B subs r3, r3, #1 + 1659 0096 0022 movs r2, #0 + 1660 0098 E254 strb r2, [r4, r3] +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1661 .loc 1 1135 0 + 1662 009a 0320 movs r0, #3 + 1663 009c 19E0 b .L107 + 1664 .L114: +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Wakeup Timer clock source bits in CR register */ +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + 1665 .loc 1 1140 0 + 1666 009e 9A68 ldr r2, [r3, #8] + 1667 00a0 0721 movs r1, #7 + 1668 00a2 8A43 bics r2, r1 + 1669 00a4 9A60 str r2, [r3, #8] +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the clock source */ +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR |= (uint32_t)WakeUpClock; + 1670 .loc 1 1143 0 + 1671 00a6 2268 ldr r2, [r4] + 1672 00a8 9368 ldr r3, [r2, #8] + 1673 00aa 1E43 orrs r6, r3 + 1674 .LVL120: + 1675 00ac 9660 str r6, [r2, #8] +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Wakeup Timer counter */ +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + 1676 .loc 1 1146 0 + 1677 00ae 2368 ldr r3, [r4] + 1678 00b0 5D61 str r5, [r3, #20] +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the Wakeup Timer */ +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + 1679 .loc 1 1149 0 + 1680 00b2 2268 ldr r2, [r4] + 1681 00b4 9168 ldr r1, [r2, #8] + 1682 00b6 8023 movs r3, #128 + 1683 00b8 DB00 lsls r3, r3, #3 + 1684 00ba 0B43 orrs r3, r1 + 1685 00bc 9360 str r3, [r2, #8] +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1686 .loc 1 1152 0 + 1687 00be 2368 ldr r3, [r4] + 1688 00c0 FF22 movs r2, #255 + 1689 00c2 5A62 str r2, [r3, #36] +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1690 .loc 1 1154 0 + ARM GAS /tmp/ccjDTEau.s page 51 + + + 1691 00c4 2123 movs r3, #33 + 1692 00c6 FE3A subs r2, r2, #254 + 1693 00c8 E254 strb r2, [r4, r3] +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1694 .loc 1 1157 0 + 1695 00ca 013B subs r3, r3, #1 + 1696 00cc 0022 movs r2, #0 + 1697 00ce E254 strb r2, [r4, r3] +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 1698 .loc 1 1159 0 + 1699 00d0 0020 movs r0, #0 + 1700 .LVL121: + 1701 .L107: +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1702 .loc 1 1160 0 + 1703 @ sp needed + 1704 .LVL122: + 1705 .LVL123: + 1706 00d2 F8BD pop {r3, r4, r5, r6, r7, pc} + 1707 .LVL124: + 1708 .L113: +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1709 .loc 1 1089 0 + 1710 00d4 0220 movs r0, #2 + 1711 .LVL125: + 1712 00d6 FCE7 b .L107 + 1713 .L116: + 1714 .align 2 + 1715 .L115: + 1716 00d8 FFFBFFFF .word -1025 + 1717 .cfi_endproc + 1718 .LFE55: + 1720 .section .text.HAL_RTCEx_SetWakeUpTimer_IT,"ax",%progbits + 1721 .align 1 + 1722 .global HAL_RTCEx_SetWakeUpTimer_IT + 1723 .syntax unified + 1724 .code 16 + 1725 .thumb_func + 1726 .fpu softvfp + 1728 HAL_RTCEx_SetWakeUpTimer_IT: + 1729 .LFB56: +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set wake up timer with interrupt. +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param WakeUpCounter: Wake up counter +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param WakeUpClock: Wake up clock +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1730 .loc 1 1170 0 + 1731 .cfi_startproc + 1732 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccjDTEau.s page 52 + + + 1733 @ frame_needed = 0, uses_anonymous_args = 0 + 1734 .LVL126: + 1735 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1736 .LCFI14: + 1737 .cfi_def_cfa_offset 24 + 1738 .cfi_offset 3, -24 + 1739 .cfi_offset 4, -20 + 1740 .cfi_offset 5, -16 + 1741 .cfi_offset 6, -12 + 1742 .cfi_offset 7, -8 + 1743 .cfi_offset 14, -4 + 1744 0002 0400 movs r4, r0 + 1745 0004 0E00 movs r6, r1 + 1746 0006 1500 movs r5, r2 + 1747 .LVL127: +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = 0U; +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 1748 .loc 1 1178 0 + 1749 0008 2023 movs r3, #32 + 1750 000a C35C ldrb r3, [r0, r3] + 1751 000c 012B cmp r3, #1 + 1752 000e 00D1 bne .LCB1658 + 1753 0010 77E0 b .L124 @long jump + 1754 .LCB1658: + 1755 .loc 1 1178 0 is_stmt 0 discriminator 2 + 1756 0012 2023 movs r3, #32 + 1757 0014 0122 movs r2, #1 + 1758 .LVL128: + 1759 0016 C254 strb r2, [r0, r3] +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 1760 .loc 1 1180 0 is_stmt 1 discriminator 2 + 1761 0018 0133 adds r3, r3, #1 + 1762 001a 0132 adds r2, r2, #1 + 1763 001c C254 strb r2, [r0, r3] +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 1764 .loc 1 1183 0 discriminator 2 + 1765 001e 0368 ldr r3, [r0] + 1766 0020 C832 adds r2, r2, #200 + 1767 0022 5A62 str r2, [r3, #36] + 1768 0024 0368 ldr r3, [r0] + 1769 0026 773A subs r2, r2, #119 + 1770 0028 5A62 str r2, [r3, #36] +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){ + 1771 .loc 1 1186 0 discriminator 2 + 1772 002a 0368 ldr r3, [r0] + 1773 002c 9B68 ldr r3, [r3, #8] + ARM GAS /tmp/ccjDTEau.s page 53 + + + 1774 002e 5B05 lsls r3, r3, #21 + 1775 0030 18D5 bpl .L119 +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 1776 .loc 1 1187 0 + 1777 0032 FFF7FEFF bl HAL_GetTick + 1778 .LVL129: + 1779 0036 0700 movs r7, r0 + 1780 .LVL130: + 1781 .L120: +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + 1782 .loc 1 1190 0 + 1783 0038 2368 ldr r3, [r4] + 1784 003a DB68 ldr r3, [r3, #12] + 1785 003c 5B07 lsls r3, r3, #29 + 1786 003e 11D5 bpl .L119 +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 1787 .loc 1 1192 0 + 1788 0040 FFF7FEFF bl HAL_GetTick + 1789 .LVL131: + 1790 0044 C01B subs r0, r0, r7 + 1791 0046 FA23 movs r3, #250 + 1792 0048 9B00 lsls r3, r3, #2 + 1793 004a 9842 cmp r0, r3 + 1794 004c F4D9 bls .L120 +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1795 .loc 1 1195 0 + 1796 004e 2368 ldr r3, [r4] + 1797 0050 FF22 movs r2, #255 + 1798 0052 5A62 str r2, [r3, #36] +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1799 .loc 1 1197 0 + 1800 0054 2123 movs r3, #33 + 1801 0056 FC3A subs r2, r2, #252 + 1802 0058 E254 strb r2, [r4, r3] +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1803 .loc 1 1200 0 + 1804 005a 013B subs r3, r3, #1 + 1805 005c 0022 movs r2, #0 + 1806 005e E254 strb r2, [r4, r3] +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1807 .loc 1 1202 0 + 1808 0060 0320 movs r0, #3 + 1809 0062 4DE0 b .L118 + 1810 .LVL132: + 1811 .L119: +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + ARM GAS /tmp/ccjDTEau.s page 54 + + +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the Wake-Up timer */ +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + 1812 .loc 1 1207 0 + 1813 0064 2268 ldr r2, [r4] + 1814 0066 9368 ldr r3, [r2, #8] + 1815 0068 2749 ldr r1, .L126 + 1816 006a 0B40 ands r3, r1 + 1817 006c 9360 str r3, [r2, #8] +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear flag Wake-Up */ +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + 1818 .loc 1 1210 0 + 1819 006e 2168 ldr r1, [r4] + 1820 0070 CA68 ldr r2, [r1, #12] + 1821 0072 FF23 movs r3, #255 + 1822 0074 1A40 ands r2, r3 + 1823 0076 254B ldr r3, .L126+4 + 1824 0078 1343 orrs r3, r2 + 1825 007a CB60 str r3, [r1, #12] +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 1826 .loc 1 1212 0 + 1827 007c FFF7FEFF bl HAL_GetTick + 1828 .LVL133: + 1829 0080 0700 movs r7, r0 + 1830 .LVL134: + 1831 .L122: +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + 1832 .loc 1 1215 0 + 1833 0082 2368 ldr r3, [r4] + 1834 0084 DA68 ldr r2, [r3, #12] + 1835 0086 5207 lsls r2, r2, #29 + 1836 0088 11D4 bmi .L125 +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 1837 .loc 1 1217 0 + 1838 008a FFF7FEFF bl HAL_GetTick + 1839 .LVL135: + 1840 008e C01B subs r0, r0, r7 + 1841 0090 FA23 movs r3, #250 + 1842 0092 9B00 lsls r3, r3, #2 + 1843 0094 9842 cmp r0, r3 + 1844 0096 F4D9 bls .L122 +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1845 .loc 1 1220 0 + 1846 0098 2368 ldr r3, [r4] + 1847 009a FF22 movs r2, #255 + 1848 009c 5A62 str r2, [r3, #36] +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 1849 .loc 1 1222 0 + 1850 009e 2123 movs r3, #33 + 1851 00a0 FC3A subs r2, r2, #252 + ARM GAS /tmp/ccjDTEau.s page 55 + + + 1852 00a2 E254 strb r2, [r4, r3] +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1853 .loc 1 1225 0 + 1854 00a4 013B subs r3, r3, #1 + 1855 00a6 0022 movs r2, #0 + 1856 00a8 E254 strb r2, [r4, r3] +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 1857 .loc 1 1227 0 + 1858 00aa 0320 movs r0, #3 + 1859 00ac 28E0 b .L118 + 1860 .L125: +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Wakeup Timer counter */ +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + 1861 .loc 1 1232 0 + 1862 00ae 5E61 str r6, [r3, #20] +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Wakeup Timer clock source bits in CR register */ +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + 1863 .loc 1 1235 0 + 1864 00b0 2268 ldr r2, [r4] + 1865 00b2 9368 ldr r3, [r2, #8] + 1866 00b4 0721 movs r1, #7 + 1867 00b6 8B43 bics r3, r1 + 1868 00b8 9360 str r3, [r2, #8] +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the clock source */ +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR |= (uint32_t)WakeUpClock; + 1869 .loc 1 1238 0 + 1870 00ba 2268 ldr r2, [r4] + 1871 00bc 9368 ldr r3, [r2, #8] + 1872 00be 1D43 orrs r5, r3 + 1873 .LVL136: + 1874 00c0 9560 str r5, [r2, #8] +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + 1875 .loc 1 1241 0 + 1876 00c2 134B ldr r3, .L126+8 + 1877 00c4 1968 ldr r1, [r3] + 1878 00c6 8022 movs r2, #128 + 1879 00c8 5203 lsls r2, r2, #13 + 1880 00ca 1143 orrs r1, r2 + 1881 00cc 1960 str r1, [r3] +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + 1882 .loc 1 1243 0 + 1883 00ce 9968 ldr r1, [r3, #8] + 1884 00d0 0A43 orrs r2, r1 + 1885 00d2 9A60 str r2, [r3, #8] +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Interrupt in the RTC_CR register */ + ARM GAS /tmp/ccjDTEau.s page 56 + + +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + 1886 .loc 1 1246 0 + 1887 00d4 2268 ldr r2, [r4] + 1888 00d6 9168 ldr r1, [r2, #8] + 1889 00d8 8023 movs r3, #128 + 1890 00da DB01 lsls r3, r3, #7 + 1891 00dc 0B43 orrs r3, r1 + 1892 00de 9360 str r3, [r2, #8] +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the Wakeup Timer */ +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + 1893 .loc 1 1249 0 + 1894 00e0 2268 ldr r2, [r4] + 1895 00e2 9168 ldr r1, [r2, #8] + 1896 00e4 8023 movs r3, #128 + 1897 00e6 DB00 lsls r3, r3, #3 + 1898 00e8 0B43 orrs r3, r1 + 1899 00ea 9360 str r3, [r2, #8] +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 1900 .loc 1 1252 0 + 1901 00ec 2368 ldr r3, [r4] + 1902 00ee FF22 movs r2, #255 + 1903 00f0 5A62 str r2, [r3, #36] +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 1904 .loc 1 1254 0 + 1905 00f2 2123 movs r3, #33 + 1906 00f4 FE3A subs r2, r2, #254 + 1907 00f6 E254 strb r2, [r4, r3] +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 1908 .loc 1 1257 0 + 1909 00f8 013B subs r3, r3, #1 + 1910 00fa 0022 movs r2, #0 + 1911 00fc E254 strb r2, [r4, r3] +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 1912 .loc 1 1259 0 + 1913 00fe 0020 movs r0, #0 + 1914 .LVL137: + 1915 .L118: +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 1916 .loc 1 1260 0 + 1917 @ sp needed + 1918 .LVL138: + 1919 .LVL139: + 1920 0100 F8BD pop {r3, r4, r5, r6, r7, pc} + 1921 .LVL140: + 1922 .L124: +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 1923 .loc 1 1178 0 + 1924 0102 0220 movs r0, #2 + 1925 .LVL141: + 1926 0104 FCE7 b .L118 + ARM GAS /tmp/ccjDTEau.s page 57 + + + 1927 .L127: + 1928 0106 C046 .align 2 + 1929 .L126: + 1930 0108 FFFBFFFF .word -1025 + 1931 010c 7FFBFFFF .word -1153 + 1932 0110 00040140 .word 1073808384 + 1933 .cfi_endproc + 1934 .LFE56: + 1936 .section .text.HAL_RTCEx_DeactivateWakeUpTimer,"ax",%progbits + 1937 .align 1 + 1938 .global HAL_RTCEx_DeactivateWakeUpTimer + 1939 .syntax unified + 1940 .code 16 + 1941 .thumb_func + 1942 .fpu softvfp + 1944 HAL_RTCEx_DeactivateWakeUpTimer: + 1945 .LFB57: +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Deactivate wake up timer counter. +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 1946 .loc 1 1268 0 + 1947 .cfi_startproc + 1948 @ args = 0, pretend = 0, frame = 0 + 1949 @ frame_needed = 0, uses_anonymous_args = 0 + 1950 .LVL142: + 1951 0000 70B5 push {r4, r5, r6, lr} + 1952 .LCFI15: + 1953 .cfi_def_cfa_offset 16 + 1954 .cfi_offset 4, -16 + 1955 .cfi_offset 5, -12 + 1956 .cfi_offset 6, -8 + 1957 .cfi_offset 14, -4 + 1958 0002 0400 movs r4, r0 + 1959 .LVL143: +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = 0U; +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 1960 .loc 1 1272 0 + 1961 0004 2023 movs r3, #32 + 1962 0006 C35C ldrb r3, [r0, r3] + 1963 0008 012B cmp r3, #1 + 1964 000a 38D0 beq .L132 + 1965 .loc 1 1272 0 is_stmt 0 discriminator 2 + 1966 000c 2023 movs r3, #32 + 1967 000e 0122 movs r2, #1 + 1968 0010 C254 strb r2, [r0, r3] +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 1969 .loc 1 1274 0 is_stmt 1 discriminator 2 + 1970 0012 0133 adds r3, r3, #1 + 1971 0014 0132 adds r2, r2, #1 + ARM GAS /tmp/ccjDTEau.s page 58 + + + 1972 0016 C254 strb r2, [r0, r3] +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 1973 .loc 1 1277 0 discriminator 2 + 1974 0018 0368 ldr r3, [r0] + 1975 001a C832 adds r2, r2, #200 + 1976 001c 5A62 str r2, [r3, #36] + 1977 001e 0368 ldr r3, [r0] + 1978 0020 773A subs r2, r2, #119 + 1979 0022 5A62 str r2, [r3, #36] +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the Wakeup Timer */ +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + 1980 .loc 1 1280 0 discriminator 2 + 1981 0024 0268 ldr r2, [r0] + 1982 0026 9368 ldr r3, [r2, #8] + 1983 0028 1649 ldr r1, .L134 + 1984 002a 0B40 ands r3, r1 + 1985 002c 9360 str r3, [r2, #8] +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* In case of interrupt mode is used, the interrupt source must disabled */ +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + 1986 .loc 1 1283 0 discriminator 2 + 1987 002e 0268 ldr r2, [r0] + 1988 0030 9368 ldr r3, [r2, #8] + 1989 0032 1549 ldr r1, .L134+4 + 1990 0034 0B40 ands r3, r1 + 1991 0036 9360 str r3, [r2, #8] +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 1992 .loc 1 1285 0 discriminator 2 + 1993 0038 FFF7FEFF bl HAL_GetTick + 1994 .LVL144: + 1995 003c 0500 movs r5, r0 + 1996 .LVL145: + 1997 .L130: +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + 1998 .loc 1 1287 0 + 1999 003e 2368 ldr r3, [r4] + 2000 0040 DA68 ldr r2, [r3, #12] + 2001 0042 5207 lsls r2, r2, #29 + 2002 0044 11D4 bmi .L133 +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 2003 .loc 1 1289 0 + 2004 0046 FFF7FEFF bl HAL_GetTick + 2005 .LVL146: + 2006 004a 401B subs r0, r0, r5 + 2007 004c FA23 movs r3, #250 + 2008 004e 9B00 lsls r3, r3, #2 + 2009 0050 9842 cmp r0, r3 + 2010 0052 F4D9 bls .L130 +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + ARM GAS /tmp/ccjDTEau.s page 59 + + + 2011 .loc 1 1292 0 + 2012 0054 2368 ldr r3, [r4] + 2013 0056 FF22 movs r2, #255 + 2014 0058 5A62 str r2, [r3, #36] +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 2015 .loc 1 1294 0 + 2016 005a 2123 movs r3, #33 + 2017 005c FC3A subs r2, r2, #252 + 2018 005e E254 strb r2, [r4, r3] +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2019 .loc 1 1297 0 + 2020 0060 013B subs r3, r3, #1 + 2021 0062 0022 movs r2, #0 + 2022 0064 E254 strb r2, [r4, r3] +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 2023 .loc 1 1299 0 + 2024 0066 0320 movs r0, #3 + 2025 0068 08E0 b .L128 + 2026 .L133: +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2027 .loc 1 1304 0 + 2028 006a FF22 movs r2, #255 + 2029 006c 5A62 str r2, [r3, #36] +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2030 .loc 1 1306 0 + 2031 006e 2123 movs r3, #33 + 2032 0070 FE3A subs r2, r2, #254 + 2033 0072 E254 strb r2, [r4, r3] +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2034 .loc 1 1309 0 + 2035 0074 013B subs r3, r3, #1 + 2036 0076 0022 movs r2, #0 + 2037 0078 E254 strb r2, [r4, r3] +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 2038 .loc 1 1311 0 + 2039 007a 0020 movs r0, #0 + 2040 .LVL147: + 2041 .L128: +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2042 .loc 1 1312 0 + 2043 @ sp needed + 2044 .LVL148: + 2045 007c 70BD pop {r4, r5, r6, pc} + 2046 .LVL149: + 2047 .L132: + ARM GAS /tmp/ccjDTEau.s page 60 + + +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2048 .loc 1 1272 0 + 2049 007e 0220 movs r0, #2 + 2050 .LVL150: + 2051 0080 FCE7 b .L128 + 2052 .L135: + 2053 0082 C046 .align 2 + 2054 .L134: + 2055 0084 FFFBFFFF .word -1025 + 2056 0088 FFBFFFFF .word -16385 + 2057 .cfi_endproc + 2058 .LFE57: + 2060 .section .text.HAL_RTCEx_GetWakeUpTimer,"ax",%progbits + 2061 .align 1 + 2062 .global HAL_RTCEx_GetWakeUpTimer + 2063 .syntax unified + 2064 .code 16 + 2065 .thumb_func + 2066 .fpu softvfp + 2068 HAL_RTCEx_GetWakeUpTimer: + 2069 .LFB58: +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Get wake up timer counter. +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval Counter value +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2070 .loc 1 1320 0 + 2071 .cfi_startproc + 2072 @ args = 0, pretend = 0, frame = 0 + 2073 @ frame_needed = 0, uses_anonymous_args = 0 + 2074 @ link register save eliminated. + 2075 .LVL151: +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the counter value */ +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); + 2076 .loc 1 1322 0 + 2077 0000 0368 ldr r3, [r0] + 2078 0002 5869 ldr r0, [r3, #20] + 2079 .LVL152: + 2080 0004 0004 lsls r0, r0, #16 + 2081 0006 000C lsrs r0, r0, #16 +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2082 .loc 1 1323 0 + 2083 @ sp needed + 2084 0008 7047 bx lr + 2085 .cfi_endproc + 2086 .LFE58: + 2088 .section .text.HAL_RTCEx_WakeUpTimerEventCallback,"ax",%progbits + 2089 .align 1 + 2090 .weak HAL_RTCEx_WakeUpTimerEventCallback + 2091 .syntax unified + 2092 .code 16 + 2093 .thumb_func + 2094 .fpu softvfp + 2096 HAL_RTCEx_WakeUpTimerEventCallback: + ARM GAS /tmp/ccjDTEau.s page 61 + + + 2097 .LFB60: +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Wake Up Timer interrupt request. +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the WAKEUPTIMER Interrupt */ +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* WAKEUPTIMER callback */ +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the WAKEUPTIMER interrupt pending bit */ +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the EXTI's line Flag for RTC WakeUpTimer */ +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Wake Up Timer callback. +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2098 .loc 1 1356 0 + 2099 .cfi_startproc + 2100 @ args = 0, pretend = 0, frame = 0 + 2101 @ frame_needed = 0, uses_anonymous_args = 0 + 2102 @ link register save eliminated. + 2103 .LVL153: +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2104 .loc 1 1363 0 + 2105 @ sp needed + 2106 0000 7047 bx lr + 2107 .cfi_endproc + 2108 .LFE60: + 2110 .section .text.HAL_RTCEx_WakeUpTimerIRQHandler,"ax",%progbits + 2111 .align 1 + 2112 .global HAL_RTCEx_WakeUpTimerIRQHandler + 2113 .syntax unified + 2114 .code 16 + ARM GAS /tmp/ccjDTEau.s page 62 + + + 2115 .thumb_func + 2116 .fpu softvfp + 2118 HAL_RTCEx_WakeUpTimerIRQHandler: + 2119 .LFB59: +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Get the pending status of the WAKEUPTIMER Interrupt */ + 2120 .loc 1 1331 0 + 2121 .cfi_startproc + 2122 @ args = 0, pretend = 0, frame = 0 + 2123 @ frame_needed = 0, uses_anonymous_args = 0 + 2124 .LVL154: + 2125 0000 10B5 push {r4, lr} + 2126 .LCFI16: + 2127 .cfi_def_cfa_offset 8 + 2128 .cfi_offset 4, -8 + 2129 .cfi_offset 14, -4 + 2130 0002 0400 movs r4, r0 +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2131 .loc 1 1333 0 + 2132 0004 0368 ldr r3, [r0] + 2133 0006 DB68 ldr r3, [r3, #12] + 2134 0008 5B05 lsls r3, r3, #21 + 2135 000a 07D4 bmi .L140 + 2136 .LVL155: + 2137 .L139: +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2138 .loc 1 1344 0 + 2139 000c 084B ldr r3, .L141 + 2140 000e 8022 movs r2, #128 + 2141 0010 5203 lsls r2, r2, #13 + 2142 0012 5A61 str r2, [r3, #20] +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2143 .loc 1 1347 0 + 2144 0014 2123 movs r3, #33 + 2145 0016 0122 movs r2, #1 + 2146 0018 E254 strb r2, [r4, r3] +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2147 .loc 1 1348 0 + 2148 @ sp needed + 2149 .LVL156: + 2150 001a 10BD pop {r4, pc} + 2151 .LVL157: + 2152 .L140: +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2153 .loc 1 1336 0 + 2154 001c FFF7FEFF bl HAL_RTCEx_WakeUpTimerEventCallback + 2155 .LVL158: +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2156 .loc 1 1339 0 + 2157 0020 2168 ldr r1, [r4] + 2158 0022 CA68 ldr r2, [r1, #12] + 2159 0024 FF23 movs r3, #255 + 2160 0026 1A40 ands r2, r3 + 2161 0028 024B ldr r3, .L141+4 + 2162 002a 1343 orrs r3, r2 + 2163 002c CB60 str r3, [r1, #12] + 2164 002e EDE7 b .L139 + 2165 .L142: + ARM GAS /tmp/ccjDTEau.s page 63 + + + 2166 .align 2 + 2167 .L141: + 2168 0030 00040140 .word 1073808384 + 2169 0034 7FFBFFFF .word -1153 + 2170 .cfi_endproc + 2171 .LFE59: + 2173 .section .text.HAL_RTCEx_PollForWakeUpTimerEvent,"ax",%progbits + 2174 .align 1 + 2175 .global HAL_RTCEx_PollForWakeUpTimerEvent + 2176 .syntax unified + 2177 .code 16 + 2178 .thumb_func + 2179 .fpu softvfp + 2181 HAL_RTCEx_PollForWakeUpTimerEvent: + 2182 .LFB61: +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Wake Up Timer Polling. +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2183 .loc 1 1373 0 + 2184 .cfi_startproc + 2185 @ args = 0, pretend = 0, frame = 0 + 2186 @ frame_needed = 0, uses_anonymous_args = 0 + 2187 .LVL159: + 2188 0000 70B5 push {r4, r5, r6, lr} + 2189 .LCFI17: + 2190 .cfi_def_cfa_offset 16 + 2191 .cfi_offset 4, -16 + 2192 .cfi_offset 5, -12 + 2193 .cfi_offset 6, -8 + 2194 .cfi_offset 14, -4 + 2195 0002 0400 movs r4, r0 + 2196 0004 0D00 movs r5, r1 +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 2197 .loc 1 1374 0 + 2198 0006 FFF7FEFF bl HAL_GetTick + 2199 .LVL160: + 2200 000a 0600 movs r6, r0 + 2201 .LVL161: + 2202 .L145: +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + 2203 .loc 1 1376 0 + 2204 000c 2368 ldr r3, [r4] + 2205 000e DA68 ldr r2, [r3, #12] + 2206 0010 5205 lsls r2, r2, #21 + 2207 0012 0DD4 bmi .L149 +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 2208 .loc 1 1378 0 + 2209 0014 6B1C adds r3, r5, #1 + ARM GAS /tmp/ccjDTEau.s page 64 + + + 2210 0016 F9D0 beq .L145 +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 2211 .loc 1 1380 0 + 2212 0018 002D cmp r5, #0 + 2213 001a 04D0 beq .L146 + 2214 .loc 1 1380 0 is_stmt 0 discriminator 1 + 2215 001c FFF7FEFF bl HAL_GetTick + 2216 .LVL162: + 2217 0020 801B subs r0, r0, r6 + 2218 0022 A842 cmp r0, r5 + 2219 0024 F2D9 bls .L145 + 2220 .L146: +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 2221 .loc 1 1382 0 is_stmt 1 + 2222 0026 2123 movs r3, #33 + 2223 0028 0322 movs r2, #3 + 2224 002a E254 strb r2, [r4, r3] +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 2225 .loc 1 1384 0 + 2226 002c 0320 movs r0, #3 + 2227 002e 09E0 b .L147 + 2228 .L149: +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the WAKEUPTIMER Flag */ +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + 2229 .loc 1 1390 0 + 2230 0030 D968 ldr r1, [r3, #12] + 2231 0032 FF22 movs r2, #255 + 2232 0034 1140 ands r1, r2 + 2233 0036 044A ldr r2, .L150 + 2234 0038 0A43 orrs r2, r1 + 2235 003a DA60 str r2, [r3, #12] +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2236 .loc 1 1393 0 + 2237 003c 2123 movs r3, #33 + 2238 003e 0122 movs r2, #1 + 2239 0040 E254 strb r2, [r4, r3] +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 2240 .loc 1 1395 0 + 2241 0042 0020 movs r0, #0 + 2242 .L147: +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2243 .loc 1 1396 0 + 2244 @ sp needed + 2245 .LVL163: + 2246 .LVL164: + 2247 .LVL165: + 2248 0044 70BD pop {r4, r5, r6, pc} + ARM GAS /tmp/ccjDTEau.s page 65 + + + 2249 .L151: + 2250 0046 C046 .align 2 + 2251 .L150: + 2252 0048 7FFBFFFF .word -1153 + 2253 .cfi_endproc + 2254 .LFE61: + 2256 .section .text.HAL_RTCEx_BKUPWrite,"ax",%progbits + 2257 .align 1 + 2258 .global HAL_RTCEx_BKUPWrite + 2259 .syntax unified + 2260 .code 16 + 2261 .thumb_func + 2262 .fpu softvfp + 2264 HAL_RTCEx_BKUPWrite: + 2265 .LFB62: +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @} +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx_Exported_Functions_Group3 +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Extended Peripheral Control functions +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @verbatim +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ##### Extended Peripheral Control functions ##### +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** This subsection provides functions allowing to +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Write a data in a specified RTC Backup data register +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Read a data in a specified RTC Backup data register +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Set the Coarse calibration parameters. +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Deactivate the Coarse calibration parameters +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Set the Smooth calibration parameters. +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Configure the Synchronization Shift Control Settings. +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Enable the RTC reference clock detection. +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Disable the RTC reference clock detection. +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Enable the Bypass Shadow feature. +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) Disable the Bypass Shadow feature. +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @endverbatim +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Write a data in a specified RTC Backup data register. +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param BackupRegister: RTC Backup data Register number. +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * specify the register. +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Data: Data to be written in the specified RTC Backup data register. +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) + ARM GAS /tmp/ccjDTEau.s page 66 + + +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2266 .loc 1 1439 0 + 2267 .cfi_startproc + 2268 @ args = 0, pretend = 0, frame = 0 + 2269 @ frame_needed = 0, uses_anonymous_args = 0 + 2270 @ link register save eliminated. + 2271 .LVL166: +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmp = 0U; +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_BKP(BackupRegister)); +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmp = (uint32_t)&(hrtc->Instance->BKP0R); + 2272 .loc 1 1445 0 + 2273 0000 0368 ldr r3, [r0] + 2274 0002 5033 adds r3, r3, #80 + 2275 .LVL167: +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmp += (BackupRegister * 4U); + 2276 .loc 1 1446 0 + 2277 0004 8900 lsls r1, r1, #2 + 2278 .LVL168: + 2279 0006 C918 adds r1, r1, r3 + 2280 .LVL169: +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Write the specified register */ +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** *(__IO uint32_t *)tmp = (uint32_t)Data; + 2281 .loc 1 1449 0 + 2282 0008 0A60 str r2, [r1] +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2283 .loc 1 1450 0 + 2284 @ sp needed + 2285 000a 7047 bx lr + 2286 .cfi_endproc + 2287 .LFE62: + 2289 .section .text.HAL_RTCEx_BKUPRead,"ax",%progbits + 2290 .align 1 + 2291 .global HAL_RTCEx_BKUPRead + 2292 .syntax unified + 2293 .code 16 + 2294 .thumb_func + 2295 .fpu softvfp + 2297 HAL_RTCEx_BKUPRead: + 2298 .LFB63: +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Reads data from the specified RTC Backup data Register. +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param BackupRegister: RTC Backup data Register number. +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * specify the register. +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval Read value +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2299 .loc 1 1461 0 + 2300 .cfi_startproc + 2301 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccjDTEau.s page 67 + + + 2302 @ frame_needed = 0, uses_anonymous_args = 0 + 2303 @ link register save eliminated. + 2304 .LVL170: +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tmp = 0U; +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_BKP(BackupRegister)); +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmp = (uint32_t)&(hrtc->Instance->BKP0R); + 2305 .loc 1 1467 0 + 2306 0000 0368 ldr r3, [r0] + 2307 0002 5033 adds r3, r3, #80 + 2308 .LVL171: +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tmp += (BackupRegister * 4U); + 2309 .loc 1 1468 0 + 2310 0004 8900 lsls r1, r1, #2 + 2311 .LVL172: + 2312 0006 C918 adds r1, r1, r3 + 2313 .LVL173: +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Read the specified register */ +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return (*(__IO uint32_t *)tmp); + 2314 .loc 1 1471 0 + 2315 0008 0868 ldr r0, [r1] + 2316 .LVL174: +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2317 .loc 1 1472 0 + 2318 @ sp needed + 2319 000a 7047 bx lr + 2320 .cfi_endproc + 2321 .LFE63: + 2323 .section .text.HAL_RTCEx_SetSmoothCalib,"ax",%progbits + 2324 .align 1 + 2325 .global HAL_RTCEx_SetSmoothCalib + 2326 .syntax unified + 2327 .code 16 + 2328 .thumb_func + 2329 .fpu softvfp + 2331 HAL_RTCEx_SetSmoothCalib: + 2332 .LFB64: +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Set the Smooth calibration parameters. +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param SmoothCalibPeriod: Select the Smooth Calibration Period. +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be can be one of the following values : +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one any value from 0 to 0x000001FF. +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + ARM GAS /tmp/ccjDTEau.s page 68 + + +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * SmoothCalibMinusPulsesValue mut be equal to 0. +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uin +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2333 .loc 1 1494 0 + 2334 .cfi_startproc + 2335 @ args = 0, pretend = 0, frame = 8 + 2336 @ frame_needed = 0, uses_anonymous_args = 0 + 2337 .LVL175: + 2338 0000 F0B5 push {r4, r5, r6, r7, lr} + 2339 .LCFI18: + 2340 .cfi_def_cfa_offset 20 + 2341 .cfi_offset 4, -20 + 2342 .cfi_offset 5, -16 + 2343 .cfi_offset 6, -12 + 2344 .cfi_offset 7, -8 + 2345 .cfi_offset 14, -4 + 2346 0002 83B0 sub sp, sp, #12 + 2347 .LCFI19: + 2348 .cfi_def_cfa_offset 32 + 2349 0004 0400 movs r4, r0 + 2350 0006 0D00 movs r5, r1 + 2351 0008 0192 str r2, [sp, #4] + 2352 000a 1E00 movs r6, r3 + 2353 .LVL176: +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = 0U; +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2354 .loc 1 1503 0 + 2355 000c 2023 movs r3, #32 + 2356 .LVL177: + 2357 000e C35C ldrb r3, [r0, r3] + 2358 0010 012B cmp r3, #1 + 2359 0012 39D0 beq .L159 + 2360 .loc 1 1503 0 is_stmt 0 discriminator 2 + 2361 0014 2023 movs r3, #32 + 2362 0016 0122 movs r2, #1 + 2363 .LVL178: + 2364 0018 C254 strb r2, [r0, r3] +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2365 .loc 1 1505 0 is_stmt 1 discriminator 2 + 2366 001a 0133 adds r3, r3, #1 + 2367 001c 0132 adds r2, r2, #1 + 2368 001e C254 strb r2, [r0, r3] +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2369 .loc 1 1508 0 discriminator 2 + 2370 0020 0368 ldr r3, [r0] + ARM GAS /tmp/ccjDTEau.s page 69 + + + 2371 0022 C832 adds r2, r2, #200 + 2372 0024 5A62 str r2, [r3, #36] + 2373 0026 0368 ldr r3, [r0] + 2374 0028 773A subs r2, r2, #119 + 2375 002a 5A62 str r2, [r3, #36] +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* check if a calibration is pending*/ +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + 2376 .loc 1 1511 0 discriminator 2 + 2377 002c 0368 ldr r3, [r0] + 2378 002e DB68 ldr r3, [r3, #12] + 2379 0030 DB03 lsls r3, r3, #15 + 2380 0032 10D4 bmi .L160 + 2381 .LVL179: + 2382 .L156: +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* check if a calibration is pending*/ +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Smooth calibration settings */ +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | + 2383 .loc 1 1535 0 + 2384 0034 019B ldr r3, [sp, #4] + 2385 0036 1D43 orrs r5, r3 + 2386 .LVL180: + 2387 0038 2368 ldr r3, [r4] + 2388 003a 2E43 orrs r6, r5 + 2389 .LVL181: + 2390 003c DE63 str r6, [r3, #60] +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2391 .loc 1 1538 0 + 2392 003e 2368 ldr r3, [r4] + 2393 0040 FF22 movs r2, #255 + 2394 0042 5A62 str r2, [r3, #36] +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + ARM GAS /tmp/ccjDTEau.s page 70 + + + 2395 .loc 1 1541 0 + 2396 0044 2123 movs r3, #33 + 2397 0046 FE3A subs r2, r2, #254 + 2398 0048 E254 strb r2, [r4, r3] +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2399 .loc 1 1544 0 + 2400 004a 013B subs r3, r3, #1 + 2401 004c 0022 movs r2, #0 + 2402 004e E254 strb r2, [r4, r3] +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 2403 .loc 1 1546 0 + 2404 0050 0020 movs r0, #0 + 2405 .L155: +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2406 .loc 1 1547 0 + 2407 0052 03B0 add sp, sp, #12 + 2408 @ sp needed + 2409 .LVL182: + 2410 0054 F0BD pop {r4, r5, r6, r7, pc} + 2411 .LVL183: + 2412 .L160: +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2413 .loc 1 1513 0 + 2414 0056 FFF7FEFF bl HAL_GetTick + 2415 .LVL184: + 2416 005a 0700 movs r7, r0 + 2417 .LVL185: + 2418 .L157: +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2419 .loc 1 1516 0 + 2420 005c 2368 ldr r3, [r4] + 2421 005e DB68 ldr r3, [r3, #12] + 2422 0060 DB03 lsls r3, r3, #15 + 2423 0062 E7D5 bpl .L156 +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2424 .loc 1 1518 0 + 2425 0064 FFF7FEFF bl HAL_GetTick + 2426 .LVL186: + 2427 0068 C01B subs r0, r0, r7 + 2428 006a FA23 movs r3, #250 + 2429 006c 9B00 lsls r3, r3, #2 + 2430 006e 9842 cmp r0, r3 + 2431 0070 F4D9 bls .L157 +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2432 .loc 1 1521 0 + 2433 0072 2368 ldr r3, [r4] + 2434 0074 FF22 movs r2, #255 + 2435 0076 5A62 str r2, [r3, #36] +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2436 .loc 1 1524 0 + 2437 0078 2123 movs r3, #33 + 2438 007a FC3A subs r2, r2, #252 + 2439 007c E254 strb r2, [r4, r3] +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 71 + + + 2440 .loc 1 1527 0 + 2441 007e 013B subs r3, r3, #1 + 2442 0080 0022 movs r2, #0 + 2443 0082 E254 strb r2, [r4, r3] +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2444 .loc 1 1529 0 + 2445 0084 0320 movs r0, #3 + 2446 0086 E4E7 b .L155 + 2447 .LVL187: + 2448 .L159: +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2449 .loc 1 1503 0 + 2450 0088 0220 movs r0, #2 + 2451 .LVL188: + 2452 008a E2E7 b .L155 + 2453 .cfi_endproc + 2454 .LFE64: + 2456 .section .text.HAL_RTCEx_SetSynchroShift,"ax",%progbits + 2457 .align 1 + 2458 .global HAL_RTCEx_SetSynchroShift + 2459 .syntax unified + 2460 .code 16 + 2461 .thumb_func + 2462 .fpu softvfp + 2464 HAL_RTCEx_SetSynchroShift: + 2465 .LFB65: +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Configure the Synchronization Shift Control Settings. +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note When REFCKON is set, firmware must not write to Shift control register. +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values : +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_SHIFTADD1S_RESET: No effect. +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param ShiftSubFS: Select the number of Second Fractions to substitute. +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one any value from 0 to 0x7FFF. +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2466 .loc 1 1562 0 + 2467 .cfi_startproc + 2468 @ args = 0, pretend = 0, frame = 0 + 2469 @ frame_needed = 0, uses_anonymous_args = 0 + 2470 .LVL189: + 2471 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 2472 .LCFI20: + 2473 .cfi_def_cfa_offset 24 + 2474 .cfi_offset 3, -24 + 2475 .cfi_offset 4, -20 + 2476 .cfi_offset 5, -16 + 2477 .cfi_offset 6, -12 + 2478 .cfi_offset 7, -8 + 2479 .cfi_offset 14, -4 + 2480 0002 0600 movs r6, r0 + 2481 0004 0D00 movs r5, r1 + ARM GAS /tmp/ccjDTEau.s page 72 + + + 2482 0006 1400 movs r4, r2 + 2483 .LVL190: +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = 0U; +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2484 .loc 1 1570 0 + 2485 0008 2023 movs r3, #32 + 2486 000a C35C ldrb r3, [r0, r3] + 2487 000c 012B cmp r3, #1 + 2488 000e 52D0 beq .L167 + 2489 .loc 1 1570 0 is_stmt 0 discriminator 2 + 2490 0010 2023 movs r3, #32 + 2491 0012 0122 movs r2, #1 + 2492 .LVL191: + 2493 0014 C254 strb r2, [r0, r3] +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2494 .loc 1 1572 0 is_stmt 1 discriminator 2 + 2495 0016 0133 adds r3, r3, #1 + 2496 0018 0132 adds r2, r2, #1 + 2497 001a C254 strb r2, [r0, r3] +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2498 .loc 1 1575 0 discriminator 2 + 2499 001c 0368 ldr r3, [r0] + 2500 001e C832 adds r2, r2, #200 + 2501 0020 5A62 str r2, [r3, #36] + 2502 0022 0368 ldr r3, [r0] + 2503 0024 773A subs r2, r2, #119 + 2504 0026 5A62 str r2, [r3, #36] +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** tickstart = HAL_GetTick(); + 2505 .loc 1 1577 0 discriminator 2 + 2506 0028 FFF7FEFF bl HAL_GetTick + 2507 .LVL192: + 2508 002c 0700 movs r7, r0 + 2509 .LVL193: + 2510 .L163: +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Wait until the shift is completed*/ +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + 2511 .loc 1 1580 0 + 2512 002e 3368 ldr r3, [r6] + 2513 0030 DA68 ldr r2, [r3, #12] + 2514 0032 1207 lsls r2, r2, #28 + 2515 0034 11D5 bpl .L168 +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 2516 .loc 1 1582 0 + 2517 0036 FFF7FEFF bl HAL_GetTick + 2518 .LVL194: + ARM GAS /tmp/ccjDTEau.s page 73 + + + 2519 003a C01B subs r0, r0, r7 + 2520 003c FA23 movs r3, #250 + 2521 003e 9B00 lsls r3, r3, #2 + 2522 0040 9842 cmp r0, r3 + 2523 0042 F4D9 bls .L163 +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2524 .loc 1 1585 0 + 2525 0044 3368 ldr r3, [r6] + 2526 0046 FF22 movs r2, #255 + 2527 0048 5A62 str r2, [r3, #36] +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 2528 .loc 1 1587 0 + 2529 004a 2123 movs r3, #33 + 2530 004c FC3A subs r2, r2, #252 + 2531 004e F254 strb r2, [r6, r3] +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2532 .loc 1 1590 0 + 2533 0050 013B subs r3, r3, #1 + 2534 0052 0022 movs r2, #0 + 2535 0054 F254 strb r2, [r6, r3] +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 2536 .loc 1 1592 0 + 2537 0056 0320 movs r0, #3 + 2538 .LVL195: + 2539 .L162: +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check if the reference clock detection is disabled */ +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the Shift settings */ +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_ERROR; +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_ERROR; +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + ARM GAS /tmp/ccjDTEau.s page 74 + + +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** else +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_ERROR; +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_ERROR; +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2540 .loc 1 1643 0 + 2541 @ sp needed + 2542 .LVL196: + 2543 .LVL197: + 2544 0058 F8BD pop {r3, r4, r5, r6, r7, pc} + 2545 .LVL198: + 2546 .L168: +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2547 .loc 1 1597 0 + 2548 005a 9A68 ldr r2, [r3, #8] + 2549 005c D206 lsls r2, r2, #27 + 2550 005e 20D4 bmi .L165 +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2551 .loc 1 1600 0 + 2552 0060 2C43 orrs r4, r5 + 2553 .LVL199: + 2554 0062 DC62 str r4, [r3, #44] +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2555 .loc 1 1603 0 + 2556 0064 3368 ldr r3, [r6] + 2557 0066 9B68 ldr r3, [r3, #8] + 2558 0068 9B06 lsls r3, r3, #26 + 2559 006a 0AD5 bpl .L169 + 2560 .L166: +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2561 .loc 1 1634 0 + 2562 006c 3368 ldr r3, [r6] + 2563 006e FF22 movs r2, #255 + 2564 0070 5A62 str r2, [r3, #36] +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2565 .loc 1 1637 0 + 2566 0072 2123 movs r3, #33 + ARM GAS /tmp/ccjDTEau.s page 75 + + + 2567 0074 FE3A subs r2, r2, #254 + 2568 0076 F254 strb r2, [r6, r3] +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2569 .loc 1 1640 0 + 2570 0078 013B subs r3, r3, #1 + 2571 007a 0022 movs r2, #0 + 2572 007c F254 strb r2, [r6, r3] +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2573 .loc 1 1642 0 + 2574 007e 0020 movs r0, #0 + 2575 0080 EAE7 b .L162 + 2576 .L169: +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2577 .loc 1 1605 0 + 2578 0082 3000 movs r0, r6 + 2579 0084 FFF7FEFF bl HAL_RTC_WaitForSynchro + 2580 .LVL200: + 2581 0088 0028 cmp r0, #0 + 2582 008a EFD0 beq .L166 +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2583 .loc 1 1608 0 + 2584 008c 3368 ldr r3, [r6] + 2585 008e FF22 movs r2, #255 + 2586 0090 5A62 str r2, [r3, #36] +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2587 .loc 1 1610 0 + 2588 0092 2123 movs r3, #33 + 2589 0094 FB3A subs r2, r2, #251 + 2590 0096 F254 strb r2, [r6, r3] +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2591 .loc 1 1613 0 + 2592 0098 013B subs r3, r3, #1 + 2593 009a 0022 movs r2, #0 + 2594 009c F254 strb r2, [r6, r3] +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2595 .loc 1 1615 0 + 2596 009e 0120 movs r0, #1 + 2597 00a0 DAE7 b .L162 + 2598 .LVL201: + 2599 .L165: +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2600 .loc 1 1622 0 + 2601 00a2 FF22 movs r2, #255 + 2602 00a4 5A62 str r2, [r3, #36] +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2603 .loc 1 1625 0 + 2604 00a6 2123 movs r3, #33 + 2605 00a8 FB3A subs r2, r2, #251 + 2606 00aa F254 strb r2, [r6, r3] +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2607 .loc 1 1628 0 + 2608 00ac 013B subs r3, r3, #1 + 2609 00ae 0022 movs r2, #0 + 2610 00b0 F254 strb r2, [r6, r3] +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2611 .loc 1 1630 0 + 2612 00b2 0120 movs r0, #1 + ARM GAS /tmp/ccjDTEau.s page 76 + + + 2613 00b4 D0E7 b .L162 + 2614 .LVL202: + 2615 .L167: +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2616 .loc 1 1570 0 + 2617 00b6 0220 movs r0, #2 + 2618 .LVL203: + 2619 00b8 CEE7 b .L162 + 2620 .cfi_endproc + 2621 .LFE65: + 2623 .section .text.HAL_RTCEx_SetCalibrationOutPut,"ax",%progbits + 2624 .align 1 + 2625 .global HAL_RTCEx_SetCalibrationOutPut + 2626 .syntax unified + 2627 .code 16 + 2628 .thumb_func + 2629 .fpu softvfp + 2631 HAL_RTCEx_SetCalibrationOutPut: + 2632 .LFB66: +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param CalibOutput : Select the Calibration output Selection . +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * This parameter can be one of the following values: +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2633 .loc 1 1655 0 + 2634 .cfi_startproc + 2635 @ args = 0, pretend = 0, frame = 0 + 2636 @ frame_needed = 0, uses_anonymous_args = 0 + 2637 .LVL204: + 2638 0000 F0B5 push {r4, r5, r6, r7, lr} + 2639 .LCFI21: + 2640 .cfi_def_cfa_offset 20 + 2641 .cfi_offset 4, -20 + 2642 .cfi_offset 5, -16 + 2643 .cfi_offset 6, -12 + 2644 .cfi_offset 7, -8 + 2645 .cfi_offset 14, -4 +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Check the parameters */ +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2646 .loc 1 1660 0 + 2647 0002 2023 movs r3, #32 + 2648 0004 C35C ldrb r3, [r0, r3] + 2649 0006 012B cmp r3, #1 + 2650 0008 22D0 beq .L172 + 2651 .loc 1 1660 0 is_stmt 0 discriminator 2 + 2652 000a 2022 movs r2, #32 + 2653 000c 0125 movs r5, #1 + ARM GAS /tmp/ccjDTEau.s page 77 + + + 2654 000e 8554 strb r5, [r0, r2] +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2655 .loc 1 1662 0 is_stmt 1 discriminator 2 + 2656 0010 2124 movs r4, #33 + 2657 0012 0223 movs r3, #2 + 2658 0014 0355 strb r3, [r0, r4] +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2659 .loc 1 1665 0 discriminator 2 + 2660 0016 0368 ldr r3, [r0] + 2661 0018 CA26 movs r6, #202 + 2662 001a 5E62 str r6, [r3, #36] + 2663 001c 0368 ldr r3, [r0] + 2664 001e 773E subs r6, r6, #119 + 2665 0020 5E62 str r6, [r3, #36] +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear flags before config */ +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + 2666 .loc 1 1668 0 discriminator 2 + 2667 0022 0668 ldr r6, [r0] + 2668 0024 B368 ldr r3, [r6, #8] + 2669 0026 0B4F ldr r7, .L173 + 2670 0028 3B40 ands r3, r7 + 2671 002a B360 str r3, [r6, #8] +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Configure the RTC_CR register */ +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR |= (uint32_t)CalibOutput; + 2672 .loc 1 1671 0 discriminator 2 + 2673 002c 0668 ldr r6, [r0] + 2674 002e B368 ldr r3, [r6, #8] + 2675 0030 1943 orrs r1, r3 + 2676 .LVL205: + 2677 0032 B160 str r1, [r6, #8] +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + 2678 .loc 1 1673 0 discriminator 2 + 2679 0034 0168 ldr r1, [r0] + 2680 0036 8E68 ldr r6, [r1, #8] + 2681 0038 8023 movs r3, #128 + 2682 003a 1B04 lsls r3, r3, #16 + 2683 003c 3343 orrs r3, r6 + 2684 003e 8B60 str r3, [r1, #8] +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2685 .loc 1 1676 0 discriminator 2 + 2686 0040 0368 ldr r3, [r0] + 2687 0042 FF21 movs r1, #255 + 2688 0044 5962 str r1, [r3, #36] +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2689 .loc 1 1679 0 discriminator 2 + 2690 0046 0555 strb r5, [r0, r4] +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 78 + + +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2691 .loc 1 1682 0 discriminator 2 + 2692 0048 0023 movs r3, #0 + 2693 004a 8354 strb r3, [r0, r2] +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 2694 .loc 1 1684 0 discriminator 2 + 2695 004c 0020 movs r0, #0 + 2696 .LVL206: + 2697 .L171: +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2698 .loc 1 1685 0 + 2699 @ sp needed + 2700 004e F0BD pop {r4, r5, r6, r7, pc} + 2701 .LVL207: + 2702 .L172: +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2703 .loc 1 1660 0 + 2704 0050 0220 movs r0, #2 + 2705 .LVL208: + 2706 0052 FCE7 b .L171 + 2707 .L174: + 2708 .align 2 + 2709 .L173: + 2710 0054 FFFFF7FF .word -524289 + 2711 .cfi_endproc + 2712 .LFE66: + 2714 .section .text.HAL_RTCEx_DeactivateCalibrationOutPut,"ax",%progbits + 2715 .align 1 + 2716 .global HAL_RTCEx_DeactivateCalibrationOutPut + 2717 .syntax unified + 2718 .code 16 + 2719 .thumb_func + 2720 .fpu softvfp + 2722 HAL_RTCEx_DeactivateCalibrationOutPut: + 2723 .LFB67: +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2724 .loc 1 1693 0 + 2725 .cfi_startproc + 2726 @ args = 0, pretend = 0, frame = 0 + 2727 @ frame_needed = 0, uses_anonymous_args = 0 + 2728 .LVL209: + 2729 0000 70B5 push {r4, r5, r6, lr} + 2730 .LCFI22: + 2731 .cfi_def_cfa_offset 16 + 2732 .cfi_offset 4, -16 + 2733 .cfi_offset 5, -12 + 2734 .cfi_offset 6, -8 + 2735 .cfi_offset 14, -4 + ARM GAS /tmp/ccjDTEau.s page 79 + + +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2736 .loc 1 1695 0 + 2737 0002 2023 movs r3, #32 + 2738 0004 C35C ldrb r3, [r0, r3] + 2739 0006 012B cmp r3, #1 + 2740 0008 18D0 beq .L177 + 2741 .loc 1 1695 0 is_stmt 0 discriminator 2 + 2742 000a 2022 movs r2, #32 + 2743 000c 0124 movs r4, #1 + 2744 000e 8454 strb r4, [r0, r2] +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2745 .loc 1 1697 0 is_stmt 1 discriminator 2 + 2746 0010 2121 movs r1, #33 + 2747 0012 0223 movs r3, #2 + 2748 0014 4354 strb r3, [r0, r1] +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2749 .loc 1 1700 0 discriminator 2 + 2750 0016 0368 ldr r3, [r0] + 2751 0018 CA25 movs r5, #202 + 2752 001a 5D62 str r5, [r3, #36] + 2753 001c 0368 ldr r3, [r0] + 2754 001e 773D subs r5, r5, #119 + 2755 0020 5D62 str r5, [r3, #36] +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + 2756 .loc 1 1702 0 discriminator 2 + 2757 0022 0568 ldr r5, [r0] + 2758 0024 AB68 ldr r3, [r5, #8] + 2759 0026 064E ldr r6, .L178 + 2760 0028 3340 ands r3, r6 + 2761 002a AB60 str r3, [r5, #8] +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2762 .loc 1 1705 0 discriminator 2 + 2763 002c 0368 ldr r3, [r0] + 2764 002e FF25 movs r5, #255 + 2765 0030 5D62 str r5, [r3, #36] +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2766 .loc 1 1708 0 discriminator 2 + 2767 0032 4454 strb r4, [r0, r1] +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2768 .loc 1 1711 0 discriminator 2 + 2769 0034 0023 movs r3, #0 + 2770 0036 8354 strb r3, [r0, r2] +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 2771 .loc 1 1713 0 discriminator 2 + 2772 0038 0020 movs r0, #0 + ARM GAS /tmp/ccjDTEau.s page 80 + + + 2773 .LVL210: + 2774 .L176: +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2775 .loc 1 1714 0 + 2776 @ sp needed + 2777 003a 70BD pop {r4, r5, r6, pc} + 2778 .LVL211: + 2779 .L177: +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2780 .loc 1 1695 0 + 2781 003c 0220 movs r0, #2 + 2782 .LVL212: + 2783 003e FCE7 b .L176 + 2784 .L179: + 2785 .align 2 + 2786 .L178: + 2787 0040 FFFF7FFF .word -8388609 + 2788 .cfi_endproc + 2789 .LFE67: + 2791 .section .text.HAL_RTCEx_SetRefClock,"ax",%progbits + 2792 .align 1 + 2793 .global HAL_RTCEx_SetRefClock + 2794 .syntax unified + 2795 .code 16 + 2796 .thumb_func + 2797 .fpu softvfp + 2799 HAL_RTCEx_SetRefClock: + 2800 .LFB68: +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Enable the RTC reference clock detection. +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2801 .loc 1 1722 0 + 2802 .cfi_startproc + 2803 @ args = 0, pretend = 0, frame = 0 + 2804 @ frame_needed = 0, uses_anonymous_args = 0 + 2805 .LVL213: + 2806 0000 10B5 push {r4, lr} + 2807 .LCFI23: + 2808 .cfi_def_cfa_offset 8 + 2809 .cfi_offset 4, -8 + 2810 .cfi_offset 14, -4 + 2811 0002 0400 movs r4, r0 +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2812 .loc 1 1724 0 + 2813 0004 2023 movs r3, #32 + 2814 0006 C35C ldrb r3, [r0, r3] + 2815 0008 012B cmp r3, #1 + 2816 000a 2ED0 beq .L183 + 2817 .loc 1 1724 0 is_stmt 0 discriminator 2 + 2818 000c 2023 movs r3, #32 + 2819 000e 0122 movs r2, #1 + ARM GAS /tmp/ccjDTEau.s page 81 + + + 2820 0010 C254 strb r2, [r0, r3] +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2821 .loc 1 1726 0 is_stmt 1 discriminator 2 + 2822 0012 0133 adds r3, r3, #1 + 2823 0014 0132 adds r2, r2, #1 + 2824 0016 C254 strb r2, [r0, r3] +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2825 .loc 1 1729 0 discriminator 2 + 2826 0018 0368 ldr r3, [r0] + 2827 001a C832 adds r2, r2, #200 + 2828 001c 5A62 str r2, [r3, #36] + 2829 001e 0368 ldr r3, [r0] + 2830 0020 773A subs r2, r2, #119 + 2831 0022 5A62 str r2, [r3, #36] +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Set Initialization mode */ +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 2832 .loc 1 1732 0 discriminator 2 + 2833 0024 FFF7FEFF bl RTC_EnterInitMode + 2834 .LVL214: + 2835 0028 0028 cmp r0, #0 + 2836 002a 13D1 bne .L184 +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Set RTC state*/ +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_ERROR; +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_ERROR; +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** else +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); + 2837 .loc 1 1747 0 + 2838 002c 2268 ldr r2, [r4] + 2839 002e 9368 ldr r3, [r2, #8] + 2840 0030 1021 movs r1, #16 + 2841 0032 0B43 orrs r3, r1 + 2842 0034 9360 str r3, [r2, #8] +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Exit Initialization mode */ +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 2843 .loc 1 1750 0 + 2844 0036 2268 ldr r2, [r4] + 2845 0038 D368 ldr r3, [r2, #12] + 2846 003a 7031 adds r1, r1, #112 + 2847 003c 8B43 bics r3, r1 + 2848 003e D360 str r3, [r2, #12] +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 82 + + +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2849 .loc 1 1754 0 + 2850 0040 2368 ldr r3, [r4] + 2851 0042 FF22 movs r2, #255 + 2852 0044 5A62 str r2, [r3, #36] +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2853 .loc 1 1757 0 + 2854 0046 2123 movs r3, #33 + 2855 0048 FE3A subs r2, r2, #254 + 2856 004a E254 strb r2, [r4, r3] +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2857 .loc 1 1760 0 + 2858 004c 013B subs r3, r3, #1 + 2859 004e 0022 movs r2, #0 + 2860 0050 E254 strb r2, [r4, r3] + 2861 .L181: +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2862 .loc 1 1763 0 + 2863 @ sp needed + 2864 .LVL215: + 2865 0052 10BD pop {r4, pc} + 2866 .LVL216: + 2867 .L184: +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2868 .loc 1 1735 0 + 2869 0054 2368 ldr r3, [r4] + 2870 0056 FF22 movs r2, #255 + 2871 0058 5A62 str r2, [r3, #36] +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2872 .loc 1 1738 0 + 2873 005a 2123 movs r3, #33 + 2874 005c FB3A subs r2, r2, #251 + 2875 005e E254 strb r2, [r4, r3] +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2876 .loc 1 1741 0 + 2877 0060 013B subs r3, r3, #1 + 2878 0062 0022 movs r2, #0 + 2879 0064 E254 strb r2, [r4, r3] +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2880 .loc 1 1743 0 + 2881 0066 0120 movs r0, #1 + 2882 0068 F3E7 b .L181 + 2883 .LVL217: + 2884 .L183: +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2885 .loc 1 1724 0 + 2886 006a 0220 movs r0, #2 + 2887 .LVL218: + 2888 006c F1E7 b .L181 + 2889 .cfi_endproc + ARM GAS /tmp/ccjDTEau.s page 83 + + + 2890 .LFE68: + 2892 .section .text.HAL_RTCEx_DeactivateRefClock,"ax",%progbits + 2893 .align 1 + 2894 .global HAL_RTCEx_DeactivateRefClock + 2895 .syntax unified + 2896 .code 16 + 2897 .thumb_func + 2898 .fpu softvfp + 2900 HAL_RTCEx_DeactivateRefClock: + 2901 .LFB69: +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Disable the RTC reference clock detection. +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 2902 .loc 1 1771 0 + 2903 .cfi_startproc + 2904 @ args = 0, pretend = 0, frame = 0 + 2905 @ frame_needed = 0, uses_anonymous_args = 0 + 2906 .LVL219: + 2907 0000 10B5 push {r4, lr} + 2908 .LCFI24: + 2909 .cfi_def_cfa_offset 8 + 2910 .cfi_offset 4, -8 + 2911 .cfi_offset 14, -4 + 2912 0002 0400 movs r4, r0 +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 2913 .loc 1 1773 0 + 2914 0004 2023 movs r3, #32 + 2915 0006 C35C ldrb r3, [r0, r3] + 2916 0008 012B cmp r3, #1 + 2917 000a 2ED0 beq .L188 + 2918 .loc 1 1773 0 is_stmt 0 discriminator 2 + 2919 000c 2023 movs r3, #32 + 2920 000e 0122 movs r2, #1 + 2921 0010 C254 strb r2, [r0, r3] +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 2922 .loc 1 1775 0 is_stmt 1 discriminator 2 + 2923 0012 0133 adds r3, r3, #1 + 2924 0014 0132 adds r2, r2, #1 + 2925 0016 C254 strb r2, [r0, r3] +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 2926 .loc 1 1778 0 discriminator 2 + 2927 0018 0368 ldr r3, [r0] + 2928 001a C832 adds r2, r2, #200 + 2929 001c 5A62 str r2, [r3, #36] + 2930 001e 0368 ldr r3, [r0] + 2931 0020 773A subs r2, r2, #119 + 2932 0022 5A62 str r2, [r3, #36] +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 84 + + +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Set Initialization mode */ +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(RTC_EnterInitMode(hrtc) != HAL_OK) + 2933 .loc 1 1781 0 discriminator 2 + 2934 0024 FFF7FEFF bl RTC_EnterInitMode + 2935 .LVL220: + 2936 0028 0028 cmp r0, #0 + 2937 002a 13D1 bne .L189 +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Set RTC state*/ +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_ERROR; +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_ERROR; +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** else +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + 2938 .loc 1 1796 0 + 2939 002c 2268 ldr r2, [r4] + 2940 002e 9368 ldr r3, [r2, #8] + 2941 0030 1021 movs r1, #16 + 2942 0032 8B43 bics r3, r1 + 2943 0034 9360 str r3, [r2, #8] +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Exit Initialization mode */ +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 2944 .loc 1 1799 0 + 2945 0036 2268 ldr r2, [r4] + 2946 0038 D368 ldr r3, [r2, #12] + 2947 003a 7031 adds r1, r1, #112 + 2948 003c 8B43 bics r3, r1 + 2949 003e D360 str r3, [r2, #12] +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 2950 .loc 1 1803 0 + 2951 0040 2368 ldr r3, [r4] + 2952 0042 FF22 movs r2, #255 + 2953 0044 5A62 str r2, [r3, #36] +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 2954 .loc 1 1806 0 + 2955 0046 2123 movs r3, #33 + 2956 0048 FE3A subs r2, r2, #254 + 2957 004a E254 strb r2, [r4, r3] +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 2958 .loc 1 1809 0 + 2959 004c 013B subs r3, r3, #1 + ARM GAS /tmp/ccjDTEau.s page 85 + + + 2960 004e 0022 movs r2, #0 + 2961 0050 E254 strb r2, [r4, r3] + 2962 .L186: +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2963 .loc 1 1812 0 + 2964 @ sp needed + 2965 .LVL221: + 2966 0052 10BD pop {r4, pc} + 2967 .LVL222: + 2968 .L189: +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2969 .loc 1 1784 0 + 2970 0054 2368 ldr r3, [r4] + 2971 0056 FF22 movs r2, #255 + 2972 0058 5A62 str r2, [r3, #36] +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2973 .loc 1 1787 0 + 2974 005a 2123 movs r3, #33 + 2975 005c FB3A subs r2, r2, #251 + 2976 005e E254 strb r2, [r4, r3] +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2977 .loc 1 1790 0 + 2978 0060 013B subs r3, r3, #1 + 2979 0062 0022 movs r2, #0 + 2980 0064 E254 strb r2, [r4, r3] +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 2981 .loc 1 1792 0 + 2982 0066 0120 movs r0, #1 + 2983 0068 F3E7 b .L186 + 2984 .LVL223: + 2985 .L188: +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 2986 .loc 1 1773 0 + 2987 006a 0220 movs r0, #2 + 2988 .LVL224: + 2989 006c F1E7 b .L186 + 2990 .cfi_endproc + 2991 .LFE69: + 2993 .section .text.HAL_RTCEx_EnableBypassShadow,"ax",%progbits + 2994 .align 1 + 2995 .global HAL_RTCEx_EnableBypassShadow + 2996 .syntax unified + 2997 .code 16 + 2998 .thumb_func + 2999 .fpu softvfp + 3001 HAL_RTCEx_EnableBypassShadow: + 3002 .LFB70: +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Enable the Bypass Shadow feature. +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note When the Bypass Shadow is enabled the calendar value are taken +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * directly from the Calendar counter. +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ + ARM GAS /tmp/ccjDTEau.s page 86 + + +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 3003 .loc 1 1822 0 + 3004 .cfi_startproc + 3005 @ args = 0, pretend = 0, frame = 0 + 3006 @ frame_needed = 0, uses_anonymous_args = 0 + 3007 .LVL225: + 3008 0000 30B5 push {r4, r5, lr} + 3009 .LCFI25: + 3010 .cfi_def_cfa_offset 12 + 3011 .cfi_offset 4, -12 + 3012 .cfi_offset 5, -8 + 3013 .cfi_offset 14, -4 +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 3014 .loc 1 1824 0 + 3015 0002 2023 movs r3, #32 + 3016 0004 C35C ldrb r3, [r0, r3] + 3017 0006 012B cmp r3, #1 + 3018 0008 17D0 beq .L192 + 3019 .loc 1 1824 0 is_stmt 0 discriminator 2 + 3020 000a 2023 movs r3, #32 + 3021 000c 0124 movs r4, #1 + 3022 000e C454 strb r4, [r0, r3] +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 3023 .loc 1 1826 0 is_stmt 1 discriminator 2 + 3024 0010 2121 movs r1, #33 + 3025 0012 0222 movs r2, #2 + 3026 0014 4254 strb r2, [r0, r1] +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 3027 .loc 1 1829 0 discriminator 2 + 3028 0016 0268 ldr r2, [r0] + 3029 0018 CA25 movs r5, #202 + 3030 001a 5562 str r5, [r2, #36] + 3031 001c 0268 ldr r2, [r0] + 3032 001e 773D subs r5, r5, #119 + 3033 0020 5562 str r5, [r2, #36] +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Set the BYPSHAD bit */ +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + 3034 .loc 1 1832 0 discriminator 2 + 3035 0022 0568 ldr r5, [r0] + 3036 0024 AA68 ldr r2, [r5, #8] + 3037 0026 1A43 orrs r2, r3 + 3038 0028 AA60 str r2, [r5, #8] +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 3039 .loc 1 1835 0 discriminator 2 + 3040 002a 0268 ldr r2, [r0] + 3041 002c FF25 movs r5, #255 + 3042 002e 5562 str r5, [r2, #36] +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ + ARM GAS /tmp/ccjDTEau.s page 87 + + +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 3043 .loc 1 1838 0 discriminator 2 + 3044 0030 4454 strb r4, [r0, r1] +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 3045 .loc 1 1841 0 discriminator 2 + 3046 0032 0022 movs r2, #0 + 3047 0034 C254 strb r2, [r0, r3] +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 3048 .loc 1 1843 0 discriminator 2 + 3049 0036 0020 movs r0, #0 + 3050 .LVL226: + 3051 .L191: +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 3052 .loc 1 1844 0 + 3053 @ sp needed + 3054 0038 30BD pop {r4, r5, pc} + 3055 .LVL227: + 3056 .L192: +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 3057 .loc 1 1824 0 + 3058 003a 0220 movs r0, #2 + 3059 .LVL228: + 3060 003c FCE7 b .L191 + 3061 .cfi_endproc + 3062 .LFE70: + 3064 .section .text.HAL_RTCEx_DisableBypassShadow,"ax",%progbits + 3065 .align 1 + 3066 .global HAL_RTCEx_DisableBypassShadow + 3067 .syntax unified + 3068 .code 16 + 3069 .thumb_func + 3070 .fpu softvfp + 3072 HAL_RTCEx_DisableBypassShadow: + 3073 .LFB71: +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Disable the Bypass Shadow feature. +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @note When the Bypass Shadow is enabled the calendar value are taken +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * directly from the Calendar counter. +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 3074 .loc 1 1854 0 + 3075 .cfi_startproc + 3076 @ args = 0, pretend = 0, frame = 0 + 3077 @ frame_needed = 0, uses_anonymous_args = 0 + 3078 .LVL229: + 3079 0000 70B5 push {r4, r5, r6, lr} + 3080 .LCFI26: + 3081 .cfi_def_cfa_offset 16 + 3082 .cfi_offset 4, -16 + 3083 .cfi_offset 5, -12 + ARM GAS /tmp/ccjDTEau.s page 88 + + + 3084 .cfi_offset 6, -8 + 3085 .cfi_offset 14, -4 +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Locked */ +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_LOCK(hrtc); + 3086 .loc 1 1856 0 + 3087 0002 2023 movs r3, #32 + 3088 0004 C35C ldrb r3, [r0, r3] + 3089 0006 012B cmp r3, #1 + 3090 0008 18D0 beq .L195 + 3091 .loc 1 1856 0 is_stmt 0 discriminator 2 + 3092 000a 2022 movs r2, #32 + 3093 000c 0124 movs r4, #1 + 3094 000e 8454 strb r4, [r0, r2] +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_BUSY; + 3095 .loc 1 1858 0 is_stmt 1 discriminator 2 + 3096 0010 2121 movs r1, #33 + 3097 0012 0223 movs r3, #2 + 3098 0014 4354 strb r3, [r0, r1] +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Disable the write protection for RTC registers */ +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 3099 .loc 1 1861 0 discriminator 2 + 3100 0016 0368 ldr r3, [r0] + 3101 0018 CA25 movs r5, #202 + 3102 001a 5D62 str r5, [r3, #36] + 3103 001c 0368 ldr r3, [r0] + 3104 001e 773D subs r5, r5, #119 + 3105 0020 5D62 str r5, [r3, #36] +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Reset the BYPSHAD bit */ +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + 3106 .loc 1 1864 0 discriminator 2 + 3107 0022 0568 ldr r5, [r0] + 3108 0024 AE68 ldr r6, [r5, #8] + 3109 0026 DF23 movs r3, #223 + 3110 0028 3340 ands r3, r6 + 3111 002a AB60 str r3, [r5, #8] +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Enable the write protection for RTC registers */ +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 3112 .loc 1 1867 0 discriminator 2 + 3113 002c 0368 ldr r3, [r0] + 3114 002e FF25 movs r5, #255 + 3115 0030 5D62 str r5, [r3, #36] +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 3116 .loc 1 1870 0 discriminator 2 + 3117 0032 4454 strb r4, [r0, r1] +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Process Unlocked */ +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_UNLOCK(hrtc); + 3118 .loc 1 1873 0 discriminator 2 + 3119 0034 0023 movs r3, #0 + 3120 0036 8354 strb r3, [r0, r2] +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + ARM GAS /tmp/ccjDTEau.s page 89 + + +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 3121 .loc 1 1875 0 discriminator 2 + 3122 0038 0020 movs r0, #0 + 3123 .LVL230: + 3124 .L194: +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 3125 .loc 1 1876 0 + 3126 @ sp needed + 3127 003a 70BD pop {r4, r5, r6, pc} + 3128 .LVL231: + 3129 .L195: +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** + 3130 .loc 1 1856 0 + 3131 003c 0220 movs r0, #2 + 3132 .LVL232: + 3133 003e FCE7 b .L194 + 3134 .cfi_endproc + 3135 .LFE71: + 3137 .section .text.HAL_RTCEx_AlarmBEventCallback,"ax",%progbits + 3138 .align 1 + 3139 .weak HAL_RTCEx_AlarmBEventCallback + 3140 .syntax unified + 3141 .code 16 + 3142 .thumb_func + 3143 .fpu softvfp + 3145 HAL_RTCEx_AlarmBEventCallback: + 3146 .LFB72: +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @} +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** @addtogroup RTCEx_Exported_Functions_Group4 +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Extended features functions +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @verbatim +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** ##### Extended features functions ##### +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** =============================================================================== +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** [..] This section provides functions allowing to: +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) RTC Alram B callback +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** (+) RTC Poll for Alarm B request +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** @endverbatim +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @{ +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Alarm B callback. +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval None +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 3147 .loc 1 1903 0 + 3148 .cfi_startproc + 3149 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccjDTEau.s page 90 + + + 3150 @ frame_needed = 0, uses_anonymous_args = 0 + 3151 @ link register save eliminated. + 3152 .LVL233: +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Prevent unused argument(s) compilation warning */ +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** UNUSED(hrtc); +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 3153 .loc 1 1910 0 + 3154 @ sp needed + 3155 0000 7047 bx lr + 3156 .cfi_endproc + 3157 .LFE72: + 3159 .section .text.HAL_RTCEx_PollForAlarmBEvent,"ax",%progbits + 3160 .align 1 + 3161 .global HAL_RTCEx_PollForAlarmBEvent + 3162 .syntax unified + 3163 .code 16 + 3164 .thumb_func + 3165 .fpu softvfp + 3167 HAL_RTCEx_PollForAlarmBEvent: + 3168 .LFB73: +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /** +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @brief Handle Alarm B Polling request. +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param hrtc: RTC handle +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @param Timeout: Timeout duration +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** * @retval HAL status +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** */ +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { + 3169 .loc 1 1919 0 + 3170 .cfi_startproc + 3171 @ args = 0, pretend = 0, frame = 0 + 3172 @ frame_needed = 0, uses_anonymous_args = 0 + 3173 .LVL234: + 3174 0000 70B5 push {r4, r5, r6, lr} + 3175 .LCFI27: + 3176 .cfi_def_cfa_offset 16 + 3177 .cfi_offset 4, -16 + 3178 .cfi_offset 5, -12 + 3179 .cfi_offset 6, -8 + 3180 .cfi_offset 14, -4 + 3181 0002 0400 movs r4, r0 + 3182 0004 0D00 movs r5, r1 +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** uint32_t tickstart = HAL_GetTick(); + 3183 .loc 1 1920 0 + 3184 0006 FFF7FEFF bl HAL_GetTick + 3185 .LVL235: + 3186 000a 0600 movs r6, r0 + 3187 .LVL236: + 3188 .L199: +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + 3189 .loc 1 1922 0 + ARM GAS /tmp/ccjDTEau.s page 91 + + + 3190 000c 2368 ldr r3, [r4] + 3191 000e DA68 ldr r2, [r3, #12] + 3192 0010 9205 lsls r2, r2, #22 + 3193 0012 0DD4 bmi .L203 +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 3194 .loc 1 1924 0 + 3195 0014 6B1C adds r3, r5, #1 + 3196 0016 F9D0 beq .L199 +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + 3197 .loc 1 1926 0 + 3198 0018 002D cmp r5, #0 + 3199 001a 04D0 beq .L200 + 3200 .loc 1 1926 0 is_stmt 0 discriminator 1 + 3201 001c FFF7FEFF bl HAL_GetTick + 3202 .LVL237: + 3203 0020 801B subs r0, r0, r6 + 3204 0022 A842 cmp r0, r5 + 3205 0024 F2D9 bls .L199 + 3206 .L200: +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** { +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_TIMEOUT; + 3207 .loc 1 1928 0 is_stmt 1 + 3208 0026 2123 movs r3, #33 + 3209 0028 0322 movs r2, #3 + 3210 002a E254 strb r2, [r4, r3] +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_TIMEOUT; + 3211 .loc 1 1929 0 + 3212 002c 0320 movs r0, #3 + 3213 002e 09E0 b .L201 + 3214 .L203: +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Clear the Alarm Flag */ +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + 3215 .loc 1 1935 0 + 3216 0030 D968 ldr r1, [r3, #12] + 3217 0032 FF22 movs r2, #255 + 3218 0034 1140 ands r1, r2 + 3219 0036 044A ldr r2, .L204 + 3220 0038 0A43 orrs r2, r1 + 3221 003a DA60 str r2, [r3, #12] +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** /* Change RTC state */ +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** hrtc->State = HAL_RTC_STATE_READY; + 3222 .loc 1 1938 0 + 3223 003c 2123 movs r3, #33 + 3224 003e 0122 movs r2, #1 + 3225 0040 E254 strb r2, [r4, r3] +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** return HAL_OK; + 3226 .loc 1 1940 0 + 3227 0042 0020 movs r0, #0 + 3228 .L201: + ARM GAS /tmp/ccjDTEau.s page 92 + + +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c **** } + 3229 .loc 1 1941 0 + 3230 @ sp needed + 3231 .LVL238: + 3232 .LVL239: + 3233 .LVL240: + 3234 0044 70BD pop {r4, r5, r6, pc} + 3235 .L205: + 3236 0046 C046 .align 2 + 3237 .L204: + 3238 0048 7FFDFFFF .word -641 + 3239 .cfi_endproc + 3240 .LFE73: + 3242 .text + 3243 .Letext0: + 3244 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3245 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3246 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 3247 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 3248 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 3249 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 3250 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 3251 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 3252 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 3253 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 3254 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h" + 3255 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h" + 3256 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccjDTEau.s page 93 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_rtc_ex.c + /tmp/ccjDTEau.s:16 .text.HAL_RTCEx_SetTimeStamp:0000000000000000 $t + /tmp/ccjDTEau.s:23 .text.HAL_RTCEx_SetTimeStamp:0000000000000000 HAL_RTCEx_SetTimeStamp + /tmp/ccjDTEau.s:106 .text.HAL_RTCEx_SetTimeStamp:0000000000000050 $d + /tmp/ccjDTEau.s:111 .text.HAL_RTCEx_SetTimeStamp_IT:0000000000000000 $t + /tmp/ccjDTEau.s:118 .text.HAL_RTCEx_SetTimeStamp_IT:0000000000000000 HAL_RTCEx_SetTimeStamp_IT + /tmp/ccjDTEau.s:218 .text.HAL_RTCEx_SetTimeStamp_IT:000000000000006c $d + /tmp/ccjDTEau.s:224 .text.HAL_RTCEx_DeactivateTimeStamp:0000000000000000 $t + /tmp/ccjDTEau.s:231 .text.HAL_RTCEx_DeactivateTimeStamp:0000000000000000 HAL_RTCEx_DeactivateTimeStamp + /tmp/ccjDTEau.s:307 .text.HAL_RTCEx_DeactivateTimeStamp:000000000000004c $d + /tmp/ccjDTEau.s:313 .text.HAL_RTCEx_GetTimeStamp:0000000000000000 $t + /tmp/ccjDTEau.s:320 .text.HAL_RTCEx_GetTimeStamp:0000000000000000 HAL_RTCEx_GetTimeStamp + /tmp/ccjDTEau.s:465 .text.HAL_RTCEx_GetTimeStamp:00000000000000ac $d + /tmp/ccjDTEau.s:472 .text.HAL_RTCEx_SetTamper:0000000000000000 $t + /tmp/ccjDTEau.s:479 .text.HAL_RTCEx_SetTamper:0000000000000000 HAL_RTCEx_SetTamper + /tmp/ccjDTEau.s:651 .text.HAL_RTCEx_SetTamper:00000000000000d4 $d + /tmp/ccjDTEau.s:656 .text.HAL_RTCEx_SetTamper_IT:0000000000000000 $t + /tmp/ccjDTEau.s:663 .text.HAL_RTCEx_SetTamper_IT:0000000000000000 HAL_RTCEx_SetTamper_IT + /tmp/ccjDTEau.s:850 .text.HAL_RTCEx_SetTamper_IT:00000000000000ec $d + /tmp/ccjDTEau.s:856 .text.HAL_RTCEx_DeactivateTamper:0000000000000000 $t + /tmp/ccjDTEau.s:863 .text.HAL_RTCEx_DeactivateTamper:0000000000000000 HAL_RTCEx_DeactivateTamper + /tmp/ccjDTEau.s:948 .text.HAL_RTCEx_DeactivateTamper:000000000000005c $d + /tmp/ccjDTEau.s:955 .text.HAL_RTCEx_TimeStampEventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:962 .text.HAL_RTCEx_TimeStampEventCallback:0000000000000000 HAL_RTCEx_TimeStampEventCallback + /tmp/ccjDTEau.s:977 .text.HAL_RTCEx_Tamper1EventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:984 .text.HAL_RTCEx_Tamper1EventCallback:0000000000000000 HAL_RTCEx_Tamper1EventCallback + /tmp/ccjDTEau.s:999 .text.HAL_RTCEx_Tamper2EventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:1006 .text.HAL_RTCEx_Tamper2EventCallback:0000000000000000 HAL_RTCEx_Tamper2EventCallback + /tmp/ccjDTEau.s:1021 .text.HAL_RTCEx_Tamper3EventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:1028 .text.HAL_RTCEx_Tamper3EventCallback:0000000000000000 HAL_RTCEx_Tamper3EventCallback + /tmp/ccjDTEau.s:1043 .text.HAL_RTCEx_TamperTimeStampIRQHandler:0000000000000000 $t + /tmp/ccjDTEau.s:1050 .text.HAL_RTCEx_TamperTimeStampIRQHandler:0000000000000000 HAL_RTCEx_TamperTimeStampIRQHandler + /tmp/ccjDTEau.s:1179 .text.HAL_RTCEx_TamperTimeStampIRQHandler:00000000000000a8 $d + /tmp/ccjDTEau.s:1191 .text.HAL_RTCEx_PollForTimeStampEvent:0000000000000000 $t + /tmp/ccjDTEau.s:1198 .text.HAL_RTCEx_PollForTimeStampEvent:0000000000000000 HAL_RTCEx_PollForTimeStampEvent + /tmp/ccjDTEau.s:1281 .text.HAL_RTCEx_PollForTimeStampEvent:0000000000000058 $d + /tmp/ccjDTEau.s:1286 .text.HAL_RTCEx_PollForTamper1Event:0000000000000000 $t + /tmp/ccjDTEau.s:1293 .text.HAL_RTCEx_PollForTamper1Event:0000000000000000 HAL_RTCEx_PollForTamper1Event + /tmp/ccjDTEau.s:1364 .text.HAL_RTCEx_PollForTamper1Event:0000000000000048 $d + /tmp/ccjDTEau.s:1369 .text.HAL_RTCEx_PollForTamper2Event:0000000000000000 $t + /tmp/ccjDTEau.s:1376 .text.HAL_RTCEx_PollForTamper2Event:0000000000000000 HAL_RTCEx_PollForTamper2Event + /tmp/ccjDTEau.s:1447 .text.HAL_RTCEx_PollForTamper2Event:0000000000000048 $d + /tmp/ccjDTEau.s:1452 .text.HAL_RTCEx_PollForTamper3Event:0000000000000000 $t + /tmp/ccjDTEau.s:1459 .text.HAL_RTCEx_PollForTamper3Event:0000000000000000 HAL_RTCEx_PollForTamper3Event + /tmp/ccjDTEau.s:1530 .text.HAL_RTCEx_PollForTamper3Event:0000000000000048 $d + /tmp/ccjDTEau.s:1535 .text.HAL_RTCEx_SetWakeUpTimer:0000000000000000 $t + /tmp/ccjDTEau.s:1542 .text.HAL_RTCEx_SetWakeUpTimer:0000000000000000 HAL_RTCEx_SetWakeUpTimer + /tmp/ccjDTEau.s:1716 .text.HAL_RTCEx_SetWakeUpTimer:00000000000000d8 $d + /tmp/ccjDTEau.s:1721 .text.HAL_RTCEx_SetWakeUpTimer_IT:0000000000000000 $t + /tmp/ccjDTEau.s:1728 .text.HAL_RTCEx_SetWakeUpTimer_IT:0000000000000000 HAL_RTCEx_SetWakeUpTimer_IT + /tmp/ccjDTEau.s:1930 .text.HAL_RTCEx_SetWakeUpTimer_IT:0000000000000108 $d + /tmp/ccjDTEau.s:1937 .text.HAL_RTCEx_DeactivateWakeUpTimer:0000000000000000 $t + /tmp/ccjDTEau.s:1944 .text.HAL_RTCEx_DeactivateWakeUpTimer:0000000000000000 HAL_RTCEx_DeactivateWakeUpTimer + /tmp/ccjDTEau.s:2055 .text.HAL_RTCEx_DeactivateWakeUpTimer:0000000000000084 $d + /tmp/ccjDTEau.s:2061 .text.HAL_RTCEx_GetWakeUpTimer:0000000000000000 $t + /tmp/ccjDTEau.s:2068 .text.HAL_RTCEx_GetWakeUpTimer:0000000000000000 HAL_RTCEx_GetWakeUpTimer + ARM GAS /tmp/ccjDTEau.s page 94 + + + /tmp/ccjDTEau.s:2089 .text.HAL_RTCEx_WakeUpTimerEventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:2096 .text.HAL_RTCEx_WakeUpTimerEventCallback:0000000000000000 HAL_RTCEx_WakeUpTimerEventCallback + /tmp/ccjDTEau.s:2111 .text.HAL_RTCEx_WakeUpTimerIRQHandler:0000000000000000 $t + /tmp/ccjDTEau.s:2118 .text.HAL_RTCEx_WakeUpTimerIRQHandler:0000000000000000 HAL_RTCEx_WakeUpTimerIRQHandler + /tmp/ccjDTEau.s:2168 .text.HAL_RTCEx_WakeUpTimerIRQHandler:0000000000000030 $d + /tmp/ccjDTEau.s:2174 .text.HAL_RTCEx_PollForWakeUpTimerEvent:0000000000000000 $t + /tmp/ccjDTEau.s:2181 .text.HAL_RTCEx_PollForWakeUpTimerEvent:0000000000000000 HAL_RTCEx_PollForWakeUpTimerEvent + /tmp/ccjDTEau.s:2252 .text.HAL_RTCEx_PollForWakeUpTimerEvent:0000000000000048 $d + /tmp/ccjDTEau.s:2257 .text.HAL_RTCEx_BKUPWrite:0000000000000000 $t + /tmp/ccjDTEau.s:2264 .text.HAL_RTCEx_BKUPWrite:0000000000000000 HAL_RTCEx_BKUPWrite + /tmp/ccjDTEau.s:2290 .text.HAL_RTCEx_BKUPRead:0000000000000000 $t + /tmp/ccjDTEau.s:2297 .text.HAL_RTCEx_BKUPRead:0000000000000000 HAL_RTCEx_BKUPRead + /tmp/ccjDTEau.s:2324 .text.HAL_RTCEx_SetSmoothCalib:0000000000000000 $t + /tmp/ccjDTEau.s:2331 .text.HAL_RTCEx_SetSmoothCalib:0000000000000000 HAL_RTCEx_SetSmoothCalib + /tmp/ccjDTEau.s:2457 .text.HAL_RTCEx_SetSynchroShift:0000000000000000 $t + /tmp/ccjDTEau.s:2464 .text.HAL_RTCEx_SetSynchroShift:0000000000000000 HAL_RTCEx_SetSynchroShift + /tmp/ccjDTEau.s:2624 .text.HAL_RTCEx_SetCalibrationOutPut:0000000000000000 $t + /tmp/ccjDTEau.s:2631 .text.HAL_RTCEx_SetCalibrationOutPut:0000000000000000 HAL_RTCEx_SetCalibrationOutPut + /tmp/ccjDTEau.s:2710 .text.HAL_RTCEx_SetCalibrationOutPut:0000000000000054 $d + /tmp/ccjDTEau.s:2715 .text.HAL_RTCEx_DeactivateCalibrationOutPut:0000000000000000 $t + /tmp/ccjDTEau.s:2722 .text.HAL_RTCEx_DeactivateCalibrationOutPut:0000000000000000 HAL_RTCEx_DeactivateCalibrationOutPut + /tmp/ccjDTEau.s:2787 .text.HAL_RTCEx_DeactivateCalibrationOutPut:0000000000000040 $d + /tmp/ccjDTEau.s:2792 .text.HAL_RTCEx_SetRefClock:0000000000000000 $t + /tmp/ccjDTEau.s:2799 .text.HAL_RTCEx_SetRefClock:0000000000000000 HAL_RTCEx_SetRefClock + /tmp/ccjDTEau.s:2893 .text.HAL_RTCEx_DeactivateRefClock:0000000000000000 $t + /tmp/ccjDTEau.s:2900 .text.HAL_RTCEx_DeactivateRefClock:0000000000000000 HAL_RTCEx_DeactivateRefClock + /tmp/ccjDTEau.s:2994 .text.HAL_RTCEx_EnableBypassShadow:0000000000000000 $t + /tmp/ccjDTEau.s:3001 .text.HAL_RTCEx_EnableBypassShadow:0000000000000000 HAL_RTCEx_EnableBypassShadow + /tmp/ccjDTEau.s:3065 .text.HAL_RTCEx_DisableBypassShadow:0000000000000000 $t + /tmp/ccjDTEau.s:3072 .text.HAL_RTCEx_DisableBypassShadow:0000000000000000 HAL_RTCEx_DisableBypassShadow + /tmp/ccjDTEau.s:3138 .text.HAL_RTCEx_AlarmBEventCallback:0000000000000000 $t + /tmp/ccjDTEau.s:3145 .text.HAL_RTCEx_AlarmBEventCallback:0000000000000000 HAL_RTCEx_AlarmBEventCallback + /tmp/ccjDTEau.s:3160 .text.HAL_RTCEx_PollForAlarmBEvent:0000000000000000 $t + /tmp/ccjDTEau.s:3167 .text.HAL_RTCEx_PollForAlarmBEvent:0000000000000000 HAL_RTCEx_PollForAlarmBEvent + /tmp/ccjDTEau.s:3238 .text.HAL_RTCEx_PollForAlarmBEvent:0000000000000048 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +RTC_Bcd2ToByte +HAL_GetTick +HAL_RTC_WaitForSynchro +RTC_EnterInitMode diff --git a/build/stm32l0xx_hal_smartcard.d b/build/stm32l0xx_hal_smartcard.d new file mode 100644 index 0000000..d087fa3 --- /dev/null +++ b/build/stm32l0xx_hal_smartcard.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_smartcard.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_smartcard.lst b/build/stm32l0xx_hal_smartcard.lst new file mode 100644 index 0000000..a10cde1 --- /dev/null +++ b/build/stm32l0xx_hal_smartcard.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cctJvedr.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_smartcard.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cctJvedr.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_smartcard.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_smartcard_ex.d b/build/stm32l0xx_hal_smartcard_ex.d new file mode 100644 index 0000000..4384659 --- /dev/null +++ b/build/stm32l0xx_hal_smartcard_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_smartcard_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_smartcard_ex.lst b/build/stm32l0xx_hal_smartcard_ex.lst new file mode 100644 index 0000000..ad1bf35 --- /dev/null +++ b/build/stm32l0xx_hal_smartcard_ex.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccB1sFsm.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_smartcard_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccB1sFsm.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_smartcard_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_smbus.d b/build/stm32l0xx_hal_smbus.d new file mode 100644 index 0000000..6cf546e --- /dev/null +++ b/build/stm32l0xx_hal_smbus.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_smbus.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_smbus.lst b/build/stm32l0xx_hal_smbus.lst new file mode 100644 index 0000000..6ab1d6d --- /dev/null +++ b/build/stm32l0xx_hal_smbus.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cczp6tbw.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_smbus.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cczp6tbw.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_smbus.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_spi.d b/build/stm32l0xx_hal_spi.d new file mode 100644 index 0000000..9b01eda --- /dev/null +++ b/build/stm32l0xx_hal_spi.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_spi.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_spi.lst b/build/stm32l0xx_hal_spi.lst new file mode 100644 index 0000000..4109025 --- /dev/null +++ b/build/stm32l0xx_hal_spi.lst @@ -0,0 +1,8540 @@ +ARM GAS /tmp/ccApM0GN.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_spi.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SPI_WaitOnFlagUntilTimeout,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 SPI_WaitOnFlagUntilTimeout: + 23 .LFB77: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @file stm32l0xx_hal_spi.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * This file provides firmware functions to manage the following + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * functionalities of the Serial Peripheral Interface (SPI) peripheral: + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + Initialization and de-initialization functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + IO operation functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + Peripheral Control functions + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + Peripheral State functions + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @verbatim + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ##### How to use this driver ##### + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ============================================================================== + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** [..] + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** The SPI HAL driver can be used as follows: + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Declare a SPI_HandleTypeDef handle structure, for example: + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef hspi; + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) Enable the SPIx interface clock + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) SPI pins configuration + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Enable the clock for the SPI GPIOs + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Configure these SPI pins as alternate function push-pull + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) NVIC configuration if you need to use interrupt process + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Configure the SPIx interrupt priority + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Enable the NVIC SPI IRQ handle + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) DMA Configuration if you need to use DMA process + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channe + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Enable the DMAx clock + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Configure the DMA handle parameters + ARM GAS /tmp/ccApM0GN.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Configure the DMA Tx or Rx Channel + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) ha + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init str + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** by calling the customed HAL_SPI_MspInit() API. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** [..] + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** Circular mode restriction: + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) Master 2Lines RxOnly + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (##) Master 1Line Rx + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) The CRC feature is not managed when the DMA circular mode is enabled + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @note + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_Tran + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @endverbatim + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ****************************************************************************** + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @attention + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * Redistribution and use in source and binary forms, with or without modification, + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * are permitted provided that the following conditions are met: + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * 1. Redistributions of source code must retain the above copyright notice, + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * this list of conditions and the following disclaimer. + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * this list of conditions and the following disclaimer in the documentation + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * and/or other materials provided with the distribution. + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * may be used to endorse or promote products derived from this software + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * without specific prior written permission. + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ****************************************************************************** + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** Additional Table: + ARM GAS /tmp/ccApM0GN.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI M + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the following table resume the max SPI frequency reached with data size 8bits/16bits, + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** DataSize = SPI_DATASIZE_8BIT: + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +----------------------------------------------------------------------------------------------+ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | Process | Tranfert mode |---------------------|----------------------|----------------------| + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave | + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |==============================================================================================| + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | / | Interrupt | Fpclk/64 | Fpclk/64 | NA | NA | NA | NA | + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|----------| + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA | + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|==========| + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | Polling | Fpclk/2 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|----------| + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | R | Interrupt | Fpclk/64 | Fpclk/32 | Fpclk/32 | Fpclk/16 | Fpclk/32 | Fpclk/32 | + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | Fpclk/2 | + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|==========| + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | Polling | Fpclk/8 | Fpclk/8 | NA | NA | Fpclk/4 | Fpclk/16 | + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|----------| + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | T | Interrupt | Fpclk/8 | Fpclk/32 | NA | NA | Fpclk/8 | Fpclk/16 | + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 | + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +----------------------------------------------------------------------------------------------+ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** DataSize = SPI_DATASIZE_16BIT: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +---------------------------------------------------------------------------------------------- + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | Process | Tranfert mode |---------------------|----------------------|----------------------| + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave | + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |==============================================================================================| + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | / | Interrupt | Fpclk/32 | Fpclk/16 | NA | NA | NA | NA | + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|----------| + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA | + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|==========| + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | Polling | Fpclk/2 | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/2 | Fpclk/8 | + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|----------| + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | R | Interrupt | Fpclk/32 | Fpclk/8 | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/8 | + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 | Fpclk/2 | + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|==========| + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | Polling | Fpclk/4 | Fpclk/4 | NA | NA | Fpclk/4 | Fpclk/8 | + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|----------| + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | T | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | Fpclk/8 | Fpclk/8 | + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|----------| + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 | + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +----------------------------------------------------------------------------------------------+ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @note The max SPI frequency depend on SPI data size (8bits, 16bits), + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, D + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + ARM GAS /tmp/ccApM0GN.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Includes ------------------------------------------------------------------*/ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #include "stm32l0xx_hal.h" + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup STM32L0xx_HAL_Driver + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #ifdef HAL_SPI_MODULE_ENABLED + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI HAL module driver + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Private typedef -----------------------------------------------------------*/ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Private define ------------------------------------------------------------*/ + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Private + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #define SPI_TIMEOUT_VALUE 10U + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Private macro -------------------------------------------------------------*/ + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Private variables ---------------------------------------------------------*/ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_TxISR(SPI_HandleTypeDef *hspi); + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_RxISR(SPI_HandleTypeDef *hspi); + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma); + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagSta + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @} + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Exported functions ---------------------------------------------------------*/ + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Exported_Functions SPI Exported Functions + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Initialization and Configuration functions + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @verbatim + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** =============================================================================== + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ##### Initialization and de-initialization functions ##### + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** =============================================================================== + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** [..] This subsection provides a set of functions allowing to initialize and + ARM GAS /tmp/ccApM0GN.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** de-initialiaze the SPIx peripheral: + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+) User must implement HAL_SPI_MspInit() function in which he configures + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+) Call the function HAL_SPI_Init() to configure the selected device with + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the selected configuration: + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) Mode + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) Direction + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) Data Size + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) Clock Polarity and Phase + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) NSS Management + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) BaudRate Prescaler + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) FirstBit + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) TIMode + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) CRC Calculation + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) CRC Polynomial if CRC enabled + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+) Call the function HAL_SPI_DeInit() to restore the default configuration + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** of the selected SPIx periperal. + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @endverbatim + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Initializes the SPI according to the specified parameters + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * in the SPI_InitTypeDef and create the associated handle. + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the SPI handle allocation */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi == NULL) + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_MODE(hspi->Init.Mode)); + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_NSS(hspi->Init.NSS)); + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_RESET) + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Allocate lock resource and initialize it */ + ARM GAS /tmp/ccApM0GN.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Lock = HAL_UNLOCKED; + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_MspInit(hspi); + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disble the selected SPI peripheral */ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** Communication speed, First bit and CRC calculation state */ + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init. + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure : NSS management */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure : CRC Polynomial */ + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #endif + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DeInitializes the SPI peripheral + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the SPI handle allocation */ + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi == NULL) + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable the SPI Peripheral Clock */ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_MspDeInit(hspi); + ARM GAS /tmp/ccApM0GN.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Release Lock */ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI MSP Init + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_MspInit could be implenetd in the user file + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI MSP DeInit + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_MspDeInit could be implenetd in the user file + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @} + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Exported_Functions_Group2 + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Data transfers functions + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @verbatim + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ============================================================================== + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ##### IO operation functions ##### + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** =============================================================================== + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** This subsection provides a set of functions allowing to manage the SPI + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** data transfers. + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** [..] The SPI supports master and slave mode : + ARM GAS /tmp/ccApM0GN.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) There are two modes of transfer: + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) Blocking mode: The communication is performed in polling mode. + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** The HAL status of all data processing is returned by the same function + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** after finishing transfer. + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) No-Blocking mode: The communication is performed using Interrupts + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** or DMA, These APIs return the HAL status. + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** The end of the data processing will be indicated through the + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** using DMA mode. + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() us + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** will be executed respectivelly at the end of the transmit or Receive process + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Blocking mode APIs are : + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TransmitReceive() in full duplex mode + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Non Blocking mode API's with Interrupt are : + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TransmitReceive_IT()in full duplex mode + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_IRQHandler() + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) Non Blocking mode functions with DMA are : + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TxCpltCallback() + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_RxCpltCallback() + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TxRxCpltCallback() + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TxHalfCpltCallback() + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_RxHalfCpltCallback() + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_TxRxHalfCpltCallback() + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (++) HAL_SPI_ErrorCallback() + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @endverbatim + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit an amount of data in blocking mode + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Timeout: Timeout duration + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL ) || (Size == 0U)) + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pData; + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = NULL; + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01U)) + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = (*hspi->pTxBuffPtr++); + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->TxXferCount > 0U) + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + ARM GAS /tmp/ccApM0GN.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = (*hspi->pTxBuffPtr++); + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->TxXferCount > 0U) + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until Busy flag is reset before disabling SPI */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + ARM GAS /tmp/ccApM0GN.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Receive an amount of data in blocking mode + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Timeout: Timeout duration + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL ) || (Size == 0U)) + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pData; + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = NULL; + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + ARM GAS /tmp/ccApM0GN.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK lin + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 8 Bit mode */ + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->RxXferCount > 1U) + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Reception */ + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 16 Bit mode */ + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->RxXferCount > 1U) + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set to read data */ + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Reception */ + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive last data in 8 Bit mode */ + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive last data in 16 Bit mode */ + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* If CRC computation is enabled */ + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set: CRC Received */ + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC to clear RXNE flag */ + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tmpreg = hspi->Instance->DR; + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi- + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable SPI peripheral */ + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC error occurred */ + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FL + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + ARM GAS /tmp/ccApM0GN.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in blocking mode + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pTxData: pointer to transmission data buffer + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pRxData: pointer to reception data buffer to be + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Timeout: Timeout duration + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxDa + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pRxData; + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pTxData; + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit and Receive data in 16 Bit mode */ + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxX + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->TxXferCount == 0U) + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->TxXferCount > 0U) + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + ARM GAS /tmp/ccApM0GN.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive the last byte */ + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Mode == SPI_MODE_SLAVE) + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit and Receive data in 8 Bit mode */ + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxX + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = (*hspi->pTxBuffPtr++); + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->TxXferCount == 0U) + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + ARM GAS /tmp/ccApM0GN.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr) = hspi->Instance->DR; + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(hspi->TxXferCount > 0U) + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = (*hspi->pTxBuffPtr++); + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Mode == SPI_MODE_SLAVE) + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC from DR to close CRC calculation process */ + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set */ + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + ARM GAS /tmp/ccApM0GN.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC */ + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tmpreg = hspi->Instance->DR; + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until Busy flag is reset before disabling SPI */ + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC error occurred */ + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FL + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit an amount of data in no-blocking mode with Interrupt + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL) || (Size == 0U)) +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = &SPI_TxISR; +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pData; +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = NULL; +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_TX(hspi); +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + ARM GAS /tmp/ccApM0GN.s page 20 + + +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Receive an amount of data in no-blocking mode with Interrupt +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL) || (Size == 0U)) +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = &SPI_RxISR; +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pData; +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size ; +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = NULL; +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_RX(hspi); +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK lin +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 21 + + +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Note : The SPI must be enabled after unlocking current process +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** to avoid the risk of SPI interrupt handle execution before current +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** process unlock */ +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pTxData: pointer to transmission data buffer +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pRxData: pointer to reception data buffer to be +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pR +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->State == HAL_SPI_STATE_READY) || \ +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process locked */ +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State != HAL_SPI_STATE_BUSY_RX) +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 22 + + +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = &SPI_TxISR; +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pTxData; +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = &SPI_2LinesRxISR; +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pRxData; +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable TXE, RXNE and ERR interrupt */ +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit an amount of data in no-blocking mode with DMA +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL) || (Size == 0U)) +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + ARM GAS /tmp/ccApM0GN.s page 23 + + +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t*)pData; +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = NULL; +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_TX(hspi); +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI TxDMA Half transfer complete callback */ +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI TxDMA transfer complete callback */ +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the DMA error callback */ +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = SPI_DMAError; +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset content of SPI RxDMA descriptor */ +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable the Tx DMA Channel */ +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi- +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable Tx DMA Request */ +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 24 + + +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Receive an amount of data in no-blocking mode with DMA +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pData: pointer to data buffer +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @note When the CRC feature is enabled the pData Length must be Size + 1. +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pData == NULL) || (Size == 0U)) +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t*)pData; +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = NULL; +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; + ARM GAS /tmp/ccApM0GN.s page 25 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_1LINE) +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_1LINE_RX(hspi); +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK lin +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI RxDMA Half transfer complete callback */ +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI Rx DMA transfer complete callback */ +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the DMA error callback */ +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset content of SPI TxDMA descriptor */ +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable the Rx DMA Channel */ +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi- +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable Rx DMA Request */ +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ + ARM GAS /tmp/ccApM0GN.s page 26 + + +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in no-blocking mode with DMA +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pTxData: pointer to transmission data buffer +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param pRxData: pointer to reception data buffer +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @note When the CRC feature is enabled the pRxData Length must be Size + 1 +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Size: amount of data to be sent +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *p +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->State == HAL_SPI_STATE_READY) || \ +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the parameters */ +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process locked */ +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State != HAL_SPI_STATE_BUSY_RX) +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Configure communication */ +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t*)pTxData; +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t*)pRxData; +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /*Init field not used in handle to zero */ +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 27 + + +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_BUSY_RX) +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI Rx DMA Half transfer complete callback */ +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI Tx/Rx DMA Half transfer complete callback */ +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the DMA error callback */ +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable the Rx DMA Channel */ +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi- +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable Rx DMA Request */ +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** is performed in DMA reception complete callback */ +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set the DMA error callback */ +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = SPI_DMAError; +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable the Tx DMA Channel */ +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi- +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable SPI peripheral */ +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable Tx DMA Request */ +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 28 + + +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Pauses the DMA Transfer. +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified SPI module. +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Resumes the DMA Transfer. +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified SPI module. +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_LOCK(hspi); +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable the SPI DMA Tx & Rx requests */ +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Stops the DMA Transfer. +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified SPI module. +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() o +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + ARM GAS /tmp/ccApM0GN.s page 29 + + +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Abort the SPI DMA tx Channel */ +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->hdmatx != NULL) +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Abort(hspi->hdmatx); +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Abort the SPI DMA rx Channel */ +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->hdmarx != NULL) +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_DMA_Abort(hspi->hdmarx); +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief This function handles SPI interrupt request. +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RX +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR(hspi); +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return; +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI in mode Tramitter ---------------------------------------------------*/ +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR(hspi); +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return; +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI CRC error interrupt occurred ---------------------------------------*/ +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI Mode Fault error interrupt occurred --------------------------------*/ +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_MODFFLAG(hspi); +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 30 + + +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI Overrun error interrupt occurred -----------------------------------*/ +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State != HAL_SPI_STATE_BUSY_TX) +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI Frame error interrupt occurred -------------------------------------*/ +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call the Error call Back in case of Errors */ +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Tx Transfer completed callbacks +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_TxCpltCallback could be implenetd in the user file +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Rx Transfer completed callbacks +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_RxCpltCallback() could be implenetd in the user file + ARM GAS /tmp/ccApM0GN.s page 31 + + +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Tx and Rx Transfer completed callbacks +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Tx Half Transfer completed callbacks +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Rx Half Transfer completed callbacks +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Tx and Rx Transfer completed callbacks +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ + ARM GAS /tmp/ccApM0GN.s page 32 + + +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI error callbacks +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(hspi); +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* NOTE : - This function Should not be modified, when the callback is needed, +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** the HAL_SPI_ErrorCallback() could be implenetd in the user file. +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** - The ErrorCode parameter in the hspi handle is updated by the SPI processes +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** and user can use HAL_SPI_GetError() API to check the latest error occurred. +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @} +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief SPI control functions +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @verbatim +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** =============================================================================== +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ##### Peripheral State and Errors functions ##### +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** =============================================================================== +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** [..] +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** This subsection provides a set of functions allowing to control the SPI. +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** @endverbatim +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Return the SPI state +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval SPI state +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return hspi->State; +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 33 + + +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Return the SPI error code +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval SPI Error Code +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return hspi->ErrorCode; +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @} +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @} +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** @addtogroup SPI_Private +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @{ +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Interrupt Handler to close Tx transfer +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval void +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable TXE interrupt */ +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable ERR interrupt if Receive process is finished */ +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until Busy flag is reset before disabling SPI */ +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + ARM GAS /tmp/ccApM0GN.s page 34 + + +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if Errors has been detected during transfer */ +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if we are in Tx or in Rx/Tx Mode */ +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call Error call back in case of Error */ +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Interrupt Handler to transmit amount of data in no-blocking mode +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval void +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_TxISR(SPI_HandleTypeDef *hspi) +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = (*hspi->pTxBuffPtr++); +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->TxXferCount == 0U) +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* calculate and transfer CRC on Tx line */ + ARM GAS /tmp/ccApM0GN.s page 35 + + +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_TxCloseIRQHandler(hspi); +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Interrupt Handler to close Rx transfer +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval void +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set to read CRC data */ +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC to reset RXNE flag */ +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tmpreg = hspi->Instance->DR; +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is reset */ +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) +1946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC error occurred */ +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable RXNE interrupt */ +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* if Transmit process is finished */ +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable ERR interrupt */ +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi- +1970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable SPI peripheral */ +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + ARM GAS /tmp/ccApM0GN.s page 36 + + +1973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if Errors has been detected during transfer */ +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if we are in Rx or in Rx/Tx Mode */ +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +1990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +1994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set state to READY before run the Callback Complete */ +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call Error call back in case of Error */ +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +1998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +1999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Interrupt Handler to receive amount of data in 2Lines mode +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval void +2007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 16 Bit mode */ +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; +2022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->RxXferCount==0U) +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RxCloseIRQHandler(hspi); +2026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** + ARM GAS /tmp/ccApM0GN.s page 37 + + +2030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief Interrupt Handler to receive amount of data in no-blocking mode +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +2033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval void +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_RxISR(SPI_HandleTypeDef *hspi) +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** (*hspi->pRxBuffPtr++) = hspi->Instance->DR; +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 16 Bit mode */ +2043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; +2047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; +2049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Enable CRC Transmission */ +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +2052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Set CRC Next to calculate CRC on Rx side */ +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->RxXferCount == 0U) +2058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RxCloseIRQHandler(hspi); +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI transmit process complete callback +2065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* DMA Normal Mode */ +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) +2076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable Tx DMA Request */ +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until Busy flag is reset before disabling SPI */ + ARM GAS /tmp/ccApM0GN.s page 38 + + +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.Direction == SPI_DIRECTION_2LINES) +2098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +2100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if Errors has been detected during transfer */ +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +2106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI receive process complete callback +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* DMA Normal mode */ +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) +2127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable Rx DMA Request */ +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +2130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* CRC Calculation handling */ +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set (CRC ready) */ +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +2139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC */ + ARM GAS /tmp/ccApM0GN.s page 39 + + +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tmpreg = hspi->Instance->DR; +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ +2146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is reset */ +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC error occurred */ +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi- +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable SPI peripheral */ +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if Errors has been detected during transfer */ +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI transmit receive process complete callback +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) +2198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* CRC Calculation handling */ +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + ARM GAS /tmp/ccApM0GN.s page 40 + + +2201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC is done on going (RXNE flag set) */ +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) +2204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until RXNE flag is set to send data */ +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +2207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Read CRC */ +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tmpreg = hspi->Instance->DR; +2213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if CRC error occurred */ +2216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +2217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +2220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) +2225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable Tx DMA Request */ +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +2231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until Busy flag is reset before disabling SPI */ +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) +2234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +2236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable Rx DMA Request */ +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +2240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check if Errors has been detected during transfer */ +2247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +2250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 41 + + +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +2259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI half transmit process complete callback +2264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxHalfCpltCallback(hspi); +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI half receive process complete callback +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_RxHalfCpltCallback(hspi); +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI Half transmit receive process complete callback +2290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxHalfCpltCallback(hspi); +2299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief DMA SPI communication error callback +2303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for the specified DMA module. +2305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval None +2306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma) +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State= HAL_SPI_STATE_READY; +2313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + ARM GAS /tmp/ccApM0GN.s page 42 + + +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /** +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @brief This function handles SPI Communication Timeout. +2319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param hspi: pointer to a SPI_HandleTypeDef structure that contains +2320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * the configuration information for SPI module. +2321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Flag: SPI flag to check +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Status: Flag status to check: RESET or set +2323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @param Timeout: Timeout duration +2324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** * @retval HAL status +2325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** */ +2326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagSta +2327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 25 .loc 1 2327 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 F0B5 push {r4, r5, r6, r7, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 20 + 33 .cfi_offset 4, -20 + 34 .cfi_offset 5, -16 + 35 .cfi_offset 6, -12 + 36 .cfi_offset 7, -8 + 37 .cfi_offset 14, -4 + 38 0002 C646 mov lr, r8 + 39 0004 00B5 push {lr} + 40 .LCFI1: + 41 .cfi_def_cfa_offset 24 + 42 .cfi_offset 8, -24 + 43 0006 0600 movs r6, r0 + 44 0008 0C00 movs r4, r1 + 45 000a 1700 movs r7, r2 + 46 000c 1D00 movs r5, r3 + 47 .LVL1: +2328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** uint32_t tickstart = 0U; +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Get tick */ +2331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** tickstart = HAL_GetTick(); + 48 .loc 1 2331 0 + 49 000e FFF7FEFF bl HAL_GetTick + 50 .LVL2: + 51 0012 8046 mov r8, r0 + 52 .LVL3: +2332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Wait until flag is set */ +2334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(Status == RESET) + 53 .loc 1 2334 0 + 54 0014 002F cmp r7, #0 + 55 0016 31D0 beq .L4 + 56 .LVL4: + 57 .L9: +2335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) +2337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(Timeout != HAL_MAX_DELAY) + ARM GAS /tmp/ccApM0GN.s page 43 + + +2339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) +2341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared +2343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master +2344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** and slave for their respective CRC calculation */ +2345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +2347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +2348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable SPI peripheral */ +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +2351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +2353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State= HAL_SPI_STATE_READY; +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); +2362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** else +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + 58 .loc 1 2370 0 + 59 0018 3368 ldr r3, [r6] + 60 001a 9B68 ldr r3, [r3, #8] + 61 001c 2340 ands r3, r4 + 62 001e A342 cmp r3, r4 + 63 0020 62D1 bne .L13 +2371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(Timeout != HAL_MAX_DELAY) + 64 .loc 1 2372 0 + 65 0022 6B1C adds r3, r5, #1 + 66 0024 F8D0 beq .L9 +2373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + 67 .loc 1 2374 0 + 68 0026 002D cmp r5, #0 + 69 0028 05D0 beq .L10 + 70 .loc 1 2374 0 is_stmt 0 discriminator 1 + 71 002a FFF7FEFF bl HAL_GetTick + 72 .LVL5: + 73 002e 4346 mov r3, r8 + 74 0030 C01A subs r0, r0, r3 + 75 0032 A842 cmp r0, r5 + 76 0034 F0D9 bls .L9 + 77 .L10: +2375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 44 + + +2376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master +2378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** and slave for their respective CRC calculation */ +2379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 78 .loc 1 2381 0 is_stmt 1 + 79 0036 3268 ldr r2, [r6] + 80 0038 5368 ldr r3, [r2, #4] + 81 003a E021 movs r1, #224 + 82 003c 8B43 bics r3, r1 + 83 003e 5360 str r3, [r2, #4] +2382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Disable SPI peripheral */ +2384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 84 .loc 1 2384 0 + 85 0040 3268 ldr r2, [r6] + 86 0042 1368 ldr r3, [r2] + 87 0044 A039 subs r1, r1, #160 + 88 0046 8B43 bics r3, r1 + 89 0048 1360 str r3, [r2] +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Reset CRC Calculation */ +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 90 .loc 1 2387 0 + 91 004a 8023 movs r3, #128 + 92 004c 9B01 lsls r3, r3, #6 + 93 004e B26A ldr r2, [r6, #40] + 94 0050 9A42 cmp r2, r3 + 95 0052 3DD0 beq .L14 + 96 .L11: +2388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State= HAL_SPI_STATE_READY; + 97 .loc 1 2392 0 + 98 0054 5123 movs r3, #81 + 99 0056 0122 movs r2, #1 + 100 0058 F254 strb r2, [r6, r3] +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Unlocked */ +2395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 101 .loc 1 2395 0 + 102 005a 013B subs r3, r3, #1 + 103 005c 0022 movs r2, #0 + 104 005e F254 strb r2, [r6, r3] +2396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 105 .loc 1 2397 0 + 106 0060 0320 movs r0, #3 + 107 0062 32E0 b .L7 + 108 .L16: +2355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 109 .loc 1 2355 0 + 110 0064 3268 ldr r2, [r6] + 111 0066 1368 ldr r3, [r2] + ARM GAS /tmp/ccApM0GN.s page 45 + + + 112 0068 2049 ldr r1, .L17 + 113 006a 0B40 ands r3, r1 + 114 006c 1360 str r3, [r2] + 115 006e 3268 ldr r2, [r6] + 116 0070 1168 ldr r1, [r2] + 117 0072 8023 movs r3, #128 + 118 0074 9B01 lsls r3, r3, #6 + 119 0076 0B43 orrs r3, r1 + 120 0078 1360 str r3, [r2] + 121 007a 1DE0 b .L6 + 122 .L4: +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 123 .loc 1 2336 0 + 124 007c 3368 ldr r3, [r6] + 125 007e 9B68 ldr r3, [r3, #8] + 126 0080 2340 ands r3, r4 + 127 0082 A342 cmp r3, r4 + 128 0084 20D0 beq .L15 +2338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 129 .loc 1 2338 0 + 130 0086 6B1C adds r3, r5, #1 + 131 0088 F8D0 beq .L4 +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 132 .loc 1 2340 0 + 133 008a 002D cmp r5, #0 + 134 008c 05D0 beq .L5 +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 135 .loc 1 2340 0 is_stmt 0 discriminator 1 + 136 008e FFF7FEFF bl HAL_GetTick + 137 .LVL6: + 138 0092 4346 mov r3, r8 + 139 0094 C01A subs r0, r0, r3 + 140 0096 A842 cmp r0, r5 + 141 0098 F0D9 bls .L4 + 142 .L5: +2347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 143 .loc 1 2347 0 is_stmt 1 + 144 009a 3268 ldr r2, [r6] + 145 009c 5368 ldr r3, [r2, #4] + 146 009e E021 movs r1, #224 + 147 00a0 8B43 bics r3, r1 + 148 00a2 5360 str r3, [r2, #4] +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 149 .loc 1 2350 0 + 150 00a4 3268 ldr r2, [r6] + 151 00a6 1368 ldr r3, [r2] + 152 00a8 A039 subs r1, r1, #160 + 153 00aa 8B43 bics r3, r1 + 154 00ac 1360 str r3, [r2] +2353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 155 .loc 1 2353 0 + 156 00ae 8023 movs r3, #128 + 157 00b0 9B01 lsls r3, r3, #6 + 158 00b2 B26A ldr r2, [r6, #40] + 159 00b4 9A42 cmp r2, r3 + 160 00b6 D5D0 beq .L16 + 161 .L6: + ARM GAS /tmp/ccApM0GN.s page 46 + + +2358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 162 .loc 1 2358 0 + 163 00b8 5123 movs r3, #81 + 164 00ba 0122 movs r2, #1 + 165 00bc F254 strb r2, [r6, r3] +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 166 .loc 1 2361 0 + 167 00be 013B subs r3, r3, #1 + 168 00c0 0022 movs r2, #0 + 169 00c2 F254 strb r2, [r6, r3] +2363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 170 .loc 1 2363 0 + 171 00c4 0320 movs r0, #3 + 172 00c6 00E0 b .L7 + 173 .L15: +2398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_OK; + 174 .loc 1 2402 0 + 175 00c8 0020 movs r0, #0 + 176 .L7: +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 177 .loc 1 2403 0 + 178 @ sp needed + 179 .LVL7: + 180 .LVL8: + 181 .LVL9: + 182 .LVL10: + 183 00ca 04BC pop {r2} + 184 00cc 9046 mov r8, r2 + 185 00ce F0BD pop {r4, r5, r6, r7, pc} + 186 .LVL11: + 187 .L14: +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 188 .loc 1 2389 0 + 189 00d0 3268 ldr r2, [r6] + 190 00d2 1368 ldr r3, [r2] + 191 00d4 0549 ldr r1, .L17 + 192 00d6 0B40 ands r3, r1 + 193 00d8 1360 str r3, [r2] + 194 00da 3268 ldr r2, [r6] + 195 00dc 1168 ldr r1, [r2] + 196 00de 8023 movs r3, #128 + 197 00e0 9B01 lsls r3, r3, #6 + 198 00e2 0B43 orrs r3, r1 + 199 00e4 1360 str r3, [r2] + 200 00e6 B5E7 b .L11 + 201 .L13: +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 202 .loc 1 2402 0 + 203 00e8 0020 movs r0, #0 + 204 00ea EEE7 b .L7 + 205 .L18: + 206 .align 2 + 207 .L17: + ARM GAS /tmp/ccApM0GN.s page 47 + + + 208 00ec FFDFFFFF .word -8193 + 209 .cfi_endproc + 210 .LFE77: + 212 .section .text.HAL_SPI_MspInit,"ax",%progbits + 213 .align 1 + 214 .weak HAL_SPI_MspInit + 215 .syntax unified + 216 .code 16 + 217 .thumb_func + 218 .fpu softvfp + 220 HAL_SPI_MspInit: + 221 .LFB41: + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 222 .loc 1 337 0 + 223 .cfi_startproc + 224 @ args = 0, pretend = 0, frame = 0 + 225 @ frame_needed = 0, uses_anonymous_args = 0 + 226 @ link register save eliminated. + 227 .LVL12: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 228 .loc 1 344 0 + 229 @ sp needed + 230 0000 7047 bx lr + 231 .cfi_endproc + 232 .LFE41: + 234 .section .text.HAL_SPI_Init,"ax",%progbits + 235 .align 1 + 236 .global HAL_SPI_Init + 237 .syntax unified + 238 .code 16 + 239 .thumb_func + 240 .fpu softvfp + 242 HAL_SPI_Init: + 243 .LFB39: + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the SPI handle allocation */ + 244 .loc 1 239 0 + 245 .cfi_startproc + 246 @ args = 0, pretend = 0, frame = 0 + 247 @ frame_needed = 0, uses_anonymous_args = 0 + 248 .LVL13: + 249 0000 10B5 push {r4, lr} + 250 .LCFI2: + 251 .cfi_def_cfa_offset 8 + 252 .cfi_offset 4, -8 + 253 .cfi_offset 14, -4 + 254 0002 041E subs r4, r0, #0 + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 255 .loc 1 241 0 + 256 0004 3CD0 beq .L23 + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 257 .loc 1 260 0 + 258 0006 5123 movs r3, #81 + 259 0008 C35C ldrb r3, [r0, r3] + 260 000a 002B cmp r3, #0 + 261 000c 32D0 beq .L24 + 262 .LVL14: + 263 .L22: + ARM GAS /tmp/ccApM0GN.s page 48 + + + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 264 .loc 1 269 0 + 265 000e 5122 movs r2, #81 + 266 0010 0223 movs r3, #2 + 267 0012 A354 strb r3, [r4, r2] + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 268 .loc 1 272 0 + 269 0014 2168 ldr r1, [r4] + 270 0016 0B68 ldr r3, [r1] + 271 0018 4020 movs r0, #64 + 272 001a 8343 bics r3, r0 + 273 001c 0B60 str r3, [r1] + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & + 274 .loc 1 277 0 + 275 001e 6368 ldr r3, [r4, #4] + 276 0020 A168 ldr r1, [r4, #8] + 277 0022 0B43 orrs r3, r1 + 278 0024 E168 ldr r1, [r4, #12] + 279 0026 0B43 orrs r3, r1 + 280 0028 2169 ldr r1, [r4, #16] + 281 002a 0B43 orrs r3, r1 + 282 002c 6169 ldr r1, [r4, #20] + 283 002e 0B43 orrs r3, r1 + 284 0030 8021 movs r1, #128 + 285 0032 8900 lsls r1, r1, #2 + 286 0034 A069 ldr r0, [r4, #24] + 287 0036 0140 ands r1, r0 + 288 0038 0B43 orrs r3, r1 + 289 003a E169 ldr r1, [r4, #28] + 290 003c 0B43 orrs r3, r1 + 291 003e 216A ldr r1, [r4, #32] + 292 0040 0B43 orrs r3, r1 + 293 0042 2168 ldr r1, [r4] + 294 0044 A06A ldr r0, [r4, #40] + 295 0046 0343 orrs r3, r0 + 296 0048 0B60 str r3, [r1] + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 297 .loc 1 282 0 + 298 004a 618B ldrh r1, [r4, #26] + 299 004c 0423 movs r3, #4 + 300 004e 0B40 ands r3, r1 + 301 0050 2168 ldr r1, [r4] + 302 0052 606A ldr r0, [r4, #36] + 303 0054 0343 orrs r3, r0 + 304 0056 4B60 str r3, [r1, #4] + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 305 .loc 1 286 0 + 306 0058 2368 ldr r3, [r4] + 307 005a E16A ldr r1, [r4, #44] + 308 005c 1961 str r1, [r3, #16] + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** #endif + 309 .loc 1 290 0 + 310 005e 2168 ldr r1, [r4] + 311 0060 CB69 ldr r3, [r1, #28] + 312 0062 0848 ldr r0, .L25 + 313 0064 0340 ands r3, r0 + 314 0066 CB61 str r3, [r1, #28] + ARM GAS /tmp/ccApM0GN.s page 49 + + + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 315 .loc 1 293 0 + 316 0068 0023 movs r3, #0 + 317 006a 6365 str r3, [r4, #84] + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 318 .loc 1 294 0 + 319 006c 0133 adds r3, r3, #1 + 320 006e A354 strb r3, [r4, r2] + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 321 .loc 1 296 0 + 322 0070 0020 movs r0, #0 + 323 .L21: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 324 .loc 1 297 0 + 325 @ sp needed + 326 .LVL15: + 327 0072 10BD pop {r4, pc} + 328 .LVL16: + 329 .L24: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 330 .loc 1 263 0 + 331 0074 5033 adds r3, r3, #80 + 332 0076 0022 movs r2, #0 + 333 0078 C254 strb r2, [r0, r3] + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 334 .loc 1 266 0 + 335 007a FFF7FEFF bl HAL_SPI_MspInit + 336 .LVL17: + 337 007e C6E7 b .L22 + 338 .LVL18: + 339 .L23: + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 340 .loc 1 243 0 + 341 0080 0120 movs r0, #1 + 342 .LVL19: + 343 0082 F6E7 b .L21 + 344 .L26: + 345 .align 2 + 346 .L25: + 347 0084 FFF7FFFF .word -2049 + 348 .cfi_endproc + 349 .LFE39: + 351 .section .text.HAL_SPI_MspDeInit,"ax",%progbits + 352 .align 1 + 353 .weak HAL_SPI_MspDeInit + 354 .syntax unified + 355 .code 16 + 356 .thumb_func + 357 .fpu softvfp + 359 HAL_SPI_MspDeInit: + 360 .LFB42: + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 361 .loc 1 353 0 + 362 .cfi_startproc + 363 @ args = 0, pretend = 0, frame = 0 + 364 @ frame_needed = 0, uses_anonymous_args = 0 + 365 @ link register save eliminated. + ARM GAS /tmp/ccApM0GN.s page 50 + + + 366 .LVL20: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 367 .loc 1 360 0 + 368 @ sp needed + 369 0000 7047 bx lr + 370 .cfi_endproc + 371 .LFE42: + 373 .section .text.HAL_SPI_DeInit,"ax",%progbits + 374 .align 1 + 375 .global HAL_SPI_DeInit + 376 .syntax unified + 377 .code 16 + 378 .thumb_func + 379 .fpu softvfp + 381 HAL_SPI_DeInit: + 382 .LFB40: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Check the SPI handle allocation */ + 383 .loc 1 306 0 + 384 .cfi_startproc + 385 @ args = 0, pretend = 0, frame = 0 + 386 @ frame_needed = 0, uses_anonymous_args = 0 + 387 .LVL21: + 388 0000 70B5 push {r4, r5, r6, lr} + 389 .LCFI3: + 390 .cfi_def_cfa_offset 16 + 391 .cfi_offset 4, -16 + 392 .cfi_offset 5, -12 + 393 .cfi_offset 6, -8 + 394 .cfi_offset 14, -4 + 395 0002 041E subs r4, r0, #0 + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 396 .loc 1 308 0 + 397 0004 10D0 beq .L30 + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 398 .loc 1 313 0 + 399 0006 5125 movs r5, #81 + 400 0008 0223 movs r3, #2 + 401 000a 4355 strb r3, [r0, r5] + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 402 .loc 1 316 0 + 403 000c 0268 ldr r2, [r0] + 404 000e 1368 ldr r3, [r2] + 405 0010 4021 movs r1, #64 + 406 0012 8B43 bics r3, r1 + 407 0014 1360 str r3, [r2] + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 408 .loc 1 319 0 + 409 0016 FFF7FEFF bl HAL_SPI_MspDeInit + 410 .LVL22: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 411 .loc 1 321 0 + 412 001a 0023 movs r3, #0 + 413 001c 6365 str r3, [r4, #84] + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 414 .loc 1 322 0 + 415 001e 6355 strb r3, [r4, r5] + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 51 + + + 416 .loc 1 325 0 + 417 0020 5022 movs r2, #80 + 418 0022 A354 strb r3, [r4, r2] + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 419 .loc 1 327 0 + 420 0024 0020 movs r0, #0 + 421 .L29: + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 422 .loc 1 328 0 + 423 @ sp needed + 424 .LVL23: + 425 0026 70BD pop {r4, r5, r6, pc} + 426 .LVL24: + 427 .L30: + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 428 .loc 1 310 0 + 429 0028 0120 movs r0, #1 + 430 .LVL25: + 431 002a FCE7 b .L29 + 432 .cfi_endproc + 433 .LFE40: + 435 .section .text.HAL_SPI_Transmit,"ax",%progbits + 436 .align 1 + 437 .global HAL_SPI_Transmit + 438 .syntax unified + 439 .code 16 + 440 .thumb_func + 441 .fpu softvfp + 443 HAL_SPI_Transmit: + 444 .LFB43: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 445 .loc 1 430 0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 8 + 448 @ frame_needed = 0, uses_anonymous_args = 0 + 449 .LVL26: + 450 0000 30B5 push {r4, r5, lr} + 451 .LCFI4: + 452 .cfi_def_cfa_offset 12 + 453 .cfi_offset 4, -12 + 454 .cfi_offset 5, -8 + 455 .cfi_offset 14, -4 + 456 0002 83B0 sub sp, sp, #12 + 457 .LCFI5: + 458 .cfi_def_cfa_offset 24 + 459 0004 0400 movs r4, r0 + 460 0006 1D00 movs r5, r3 + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 461 .loc 1 432 0 + 462 0008 5123 movs r3, #81 + 463 .LVL27: + 464 000a C35C ldrb r3, [r0, r3] + 465 000c 012B cmp r3, #1 + 466 000e 00D0 beq .LCB412 + 467 0010 D9E0 b .L49 @long jump + 468 .LCB412: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 52 + + + 469 .loc 1 434 0 + 470 0012 0029 cmp r1, #0 + 471 0014 00D1 bne .LCB414 + 472 0016 D9E0 b .L50 @long jump + 473 .LCB414: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 474 .loc 1 434 0 is_stmt 0 discriminator 1 + 475 0018 002A cmp r2, #0 + 476 001a 00D1 bne .LCB416 + 477 001c D8E0 b .L51 @long jump + 478 .LCB416: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 479 .loc 1 443 0 is_stmt 1 + 480 001e 4F33 adds r3, r3, #79 + 481 0020 C35C ldrb r3, [r0, r3] + 482 0022 012B cmp r3, #1 + 483 0024 00D1 bne .LCB420 + 484 0026 D5E0 b .L52 @long jump + 485 .LCB420: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 486 .loc 1 443 0 is_stmt 0 discriminator 2 + 487 0028 5023 movs r3, #80 + 488 002a 0120 movs r0, #1 + 489 .LVL28: + 490 002c E054 strb r0, [r4, r3] + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 491 .loc 1 446 0 is_stmt 1 discriminator 2 + 492 002e 0133 adds r3, r3, #1 + 493 0030 1130 adds r0, r0, #17 + 494 0032 E054 strb r0, [r4, r3] + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 495 .loc 1 447 0 discriminator 2 + 496 0034 0023 movs r3, #0 + 497 0036 6365 str r3, [r4, #84] + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 498 .loc 1 449 0 discriminator 2 + 499 0038 2163 str r1, [r4, #48] + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 500 .loc 1 450 0 discriminator 2 + 501 003a A286 strh r2, [r4, #52] + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 502 .loc 1 451 0 discriminator 2 + 503 003c E286 strh r2, [r4, #54] + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; + 504 .loc 1 454 0 discriminator 2 + 505 003e E364 str r3, [r4, #76] + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = NULL; + 506 .loc 1 455 0 discriminator 2 + 507 0040 A364 str r3, [r4, #72] + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; + 508 .loc 1 456 0 discriminator 2 + 509 0042 A363 str r3, [r4, #56] + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 510 .loc 1 457 0 discriminator 2 + 511 0044 A387 strh r3, [r4, #60] + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 512 .loc 1 458 0 discriminator 2 + ARM GAS /tmp/ccApM0GN.s page 53 + + + 513 0046 E387 strh r3, [r4, #62] + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 514 .loc 1 461 0 discriminator 2 + 515 0048 8023 movs r3, #128 + 516 004a 9B01 lsls r3, r3, #6 + 517 004c A26A ldr r2, [r4, #40] + 518 .LVL29: + 519 004e 9A42 cmp r2, r3 + 520 0050 38D0 beq .L55 + 521 .LVL30: + 522 .L33: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 523 .loc 1 466 0 + 524 0052 8023 movs r3, #128 + 525 0054 1B02 lsls r3, r3, #8 + 526 0056 A268 ldr r2, [r4, #8] + 527 0058 9A42 cmp r2, r3 + 528 005a 3FD0 beq .L56 + 529 .L34: + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 530 .loc 1 473 0 + 531 005c 2368 ldr r3, [r4] + 532 005e 1A68 ldr r2, [r3] + 533 0060 5206 lsls r2, r2, #25 + 534 0062 03D4 bmi .L35 + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 535 .loc 1 476 0 + 536 0064 1A68 ldr r2, [r3] + 537 0066 4021 movs r1, #64 + 538 0068 0A43 orrs r2, r1 + 539 006a 1A60 str r2, [r3] + 540 .L35: + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 541 .loc 1 480 0 + 542 006c E368 ldr r3, [r4, #12] + 543 006e 002B cmp r3, #0 + 544 0070 67D1 bne .L36 + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 545 .loc 1 482 0 + 546 0072 6368 ldr r3, [r4, #4] + 547 0074 002B cmp r3, #0 + 548 0076 03D0 beq .L37 + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 549 .loc 1 482 0 is_stmt 0 discriminator 1 + 550 0078 E38E ldrh r3, [r4, #54] + 551 007a 9BB2 uxth r3, r3 + 552 007c 012B cmp r3, #1 + 553 007e 09D1 bne .L39 + 554 .L37: + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 555 .loc 1 484 0 is_stmt 1 + 556 0080 236B ldr r3, [r4, #48] + 557 0082 5A1C adds r2, r3, #1 + 558 0084 2263 str r2, [r4, #48] + 559 0086 2268 ldr r2, [r4] + 560 0088 1B78 ldrb r3, [r3] + 561 008a D360 str r3, [r2, #12] + ARM GAS /tmp/ccApM0GN.s page 54 + + + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 562 .loc 1 485 0 + 563 008c E38E ldrh r3, [r4, #54] + 564 008e 013B subs r3, r3, #1 + 565 0090 9BB2 uxth r3, r3 + 566 0092 E386 strh r3, [r4, #54] + 567 .L39: + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 568 .loc 1 488 0 + 569 0094 E38E ldrh r3, [r4, #54] + 570 0096 9BB2 uxth r3, r3 + 571 0098 002B cmp r3, #0 + 572 009a 26D0 beq .L57 + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 573 .loc 1 491 0 + 574 009c 2B00 movs r3, r5 + 575 009e 0022 movs r2, #0 + 576 00a0 0221 movs r1, #2 + 577 00a2 2000 movs r0, r4 + 578 00a4 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 579 .LVL31: + 580 00a8 0028 cmp r0, #0 + 581 00aa 00D0 beq .LCB505 + 582 00ac 94E0 b .L53 @long jump + 583 .LCB505: + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 584 .loc 1 495 0 + 585 00ae 236B ldr r3, [r4, #48] + 586 00b0 5A1C adds r2, r3, #1 + 587 00b2 2263 str r2, [r4, #48] + 588 00b4 2268 ldr r2, [r4] + 589 00b6 1B78 ldrb r3, [r3] + 590 00b8 D360 str r3, [r2, #12] + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 591 .loc 1 496 0 + 592 00ba E38E ldrh r3, [r4, #54] + 593 00bc 013B subs r3, r3, #1 + 594 00be 9BB2 uxth r3, r3 + 595 00c0 E386 strh r3, [r4, #54] + 596 00c2 E7E7 b .L39 + 597 .LVL32: + 598 .L55: + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 599 .loc 1 463 0 + 600 00c4 2268 ldr r2, [r4] + 601 00c6 1368 ldr r3, [r2] + 602 00c8 4549 ldr r1, .L62 + 603 .LVL33: + 604 00ca 0B40 ands r3, r1 + 605 00cc 1360 str r3, [r2] + 606 .LVL34: + 607 00ce 2268 ldr r2, [r4] + 608 00d0 1168 ldr r1, [r2] + 609 00d2 8023 movs r3, #128 + 610 00d4 9B01 lsls r3, r3, #6 + 611 00d6 0B43 orrs r3, r1 + 612 00d8 1360 str r3, [r2] + ARM GAS /tmp/ccApM0GN.s page 55 + + + 613 00da BAE7 b .L33 + 614 .L56: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 615 .loc 1 469 0 + 616 00dc 2268 ldr r2, [r4] + 617 00de 1168 ldr r1, [r2] + 618 00e0 8023 movs r3, #128 + 619 00e2 DB01 lsls r3, r3, #7 + 620 00e4 0B43 orrs r3, r1 + 621 00e6 1360 str r3, [r2] + 622 00e8 B8E7 b .L34 + 623 .L57: + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 624 .loc 1 499 0 + 625 00ea 8023 movs r3, #128 + 626 00ec 9B01 lsls r3, r3, #6 + 627 00ee A26A ldr r2, [r4, #40] + 628 00f0 9A42 cmp r2, r3 + 629 00f2 1FD0 beq .L58 + 630 .L41: + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 631 .loc 1 533 0 + 632 00f4 2B00 movs r3, r5 + 633 00f6 0022 movs r2, #0 + 634 00f8 0221 movs r1, #2 + 635 00fa 2000 movs r0, r4 + 636 00fc FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 637 .LVL35: + 638 0100 0028 cmp r0, #0 + 639 0102 54D1 bne .L59 + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 640 .loc 1 540 0 + 641 0104 2B00 movs r3, r5 + 642 0106 0122 movs r2, #1 + 643 0108 8021 movs r1, #128 + 644 010a 2000 movs r0, r4 + 645 010c FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 646 .LVL36: + 647 0110 0028 cmp r0, #0 + 648 0112 52D1 bne .L60 + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 649 .loc 1 547 0 + 650 0114 A368 ldr r3, [r4, #8] + 651 0116 002B cmp r3, #0 + 652 0118 05D1 bne .L48 + 653 .LBB2: + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 654 .loc 1 549 0 + 655 011a 2368 ldr r3, [r4] + 656 011c DA68 ldr r2, [r3, #12] + 657 011e 0192 str r2, [sp, #4] + 658 0120 9B68 ldr r3, [r3, #8] + 659 0122 0193 str r3, [sp, #4] + 660 0124 019B ldr r3, [sp, #4] + 661 .L48: + 662 .LBE2: + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 56 + + + 663 .loc 1 552 0 + 664 0126 5123 movs r3, #81 + 665 0128 0122 movs r2, #1 + 666 012a E254 strb r2, [r4, r3] + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 667 .loc 1 555 0 + 668 012c 013B subs r3, r3, #1 + 669 012e 0022 movs r2, #0 + 670 0130 E254 strb r2, [r4, r3] + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 671 .loc 1 557 0 + 672 0132 49E0 b .L32 + 673 .L58: + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 674 .loc 1 501 0 + 675 0134 2268 ldr r2, [r4] + 676 0136 1168 ldr r1, [r2] + 677 0138 8023 movs r3, #128 + 678 013a 5B01 lsls r3, r3, #5 + 679 013c 0B43 orrs r3, r1 + 680 013e 1360 str r3, [r2] + 681 0140 D8E7 b .L41 + 682 .L36: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 683 .loc 1 507 0 + 684 0142 6368 ldr r3, [r4, #4] + 685 0144 002B cmp r3, #0 + 686 0146 03D0 beq .L42 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 687 .loc 1 507 0 is_stmt 0 discriminator 1 + 688 0148 E38E ldrh r3, [r4, #54] + 689 014a 9BB2 uxth r3, r3 + 690 014c 012B cmp r3, #1 + 691 014e 0AD1 bne .L44 + 692 .L42: + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 693 .loc 1 509 0 is_stmt 1 + 694 0150 2368 ldr r3, [r4] + 695 0152 226B ldr r2, [r4, #48] + 696 0154 1288 ldrh r2, [r2] + 697 0156 DA60 str r2, [r3, #12] + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 698 .loc 1 510 0 + 699 0158 236B ldr r3, [r4, #48] + 700 015a 0233 adds r3, r3, #2 + 701 015c 2363 str r3, [r4, #48] + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 702 .loc 1 511 0 + 703 015e E38E ldrh r3, [r4, #54] + 704 0160 013B subs r3, r3, #1 + 705 0162 9BB2 uxth r3, r3 + 706 0164 E386 strh r3, [r4, #54] + 707 .L44: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 708 .loc 1 514 0 + 709 0166 E38E ldrh r3, [r4, #54] + 710 0168 9BB2 uxth r3, r3 + ARM GAS /tmp/ccApM0GN.s page 57 + + + 711 016a 002B cmp r3, #0 + 712 016c 13D0 beq .L61 + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 713 .loc 1 517 0 + 714 016e 2B00 movs r3, r5 + 715 0170 0022 movs r2, #0 + 716 0172 0221 movs r1, #2 + 717 0174 2000 movs r0, r4 + 718 0176 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 719 .LVL37: + 720 017a 0028 cmp r0, #0 + 721 017c 2ED1 bne .L54 + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 722 .loc 1 521 0 + 723 017e 2368 ldr r3, [r4] + 724 0180 226B ldr r2, [r4, #48] + 725 0182 1288 ldrh r2, [r2] + 726 0184 DA60 str r2, [r3, #12] + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 727 .loc 1 522 0 + 728 0186 236B ldr r3, [r4, #48] + 729 0188 0233 adds r3, r3, #2 + 730 018a 2363 str r3, [r4, #48] + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 731 .loc 1 523 0 + 732 018c E38E ldrh r3, [r4, #54] + 733 018e 013B subs r3, r3, #1 + 734 0190 9BB2 uxth r3, r3 + 735 0192 E386 strh r3, [r4, #54] + 736 0194 E7E7 b .L44 + 737 .L61: + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 738 .loc 1 526 0 + 739 0196 8023 movs r3, #128 + 740 0198 9B01 lsls r3, r3, #6 + 741 019a A26A ldr r2, [r4, #40] + 742 019c 9A42 cmp r2, r3 + 743 019e A9D1 bne .L41 + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 744 .loc 1 528 0 + 745 01a0 2268 ldr r2, [r4] + 746 01a2 1168 ldr r1, [r2] + 747 01a4 8023 movs r3, #128 + 748 01a6 5B01 lsls r3, r3, #5 + 749 01a8 0B43 orrs r3, r1 + 750 01aa 1360 str r3, [r2] + 751 01ac A2E7 b .L41 + 752 .L59: + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 753 .loc 1 535 0 + 754 01ae 636D ldr r3, [r4, #84] + 755 01b0 2022 movs r2, #32 + 756 01b2 1343 orrs r3, r2 + 757 01b4 6365 str r3, [r4, #84] + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 758 .loc 1 536 0 + 759 01b6 0320 movs r0, #3 + ARM GAS /tmp/ccApM0GN.s page 58 + + + 760 01b8 06E0 b .L32 + 761 .L60: + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 762 .loc 1 542 0 + 763 01ba 636D ldr r3, [r4, #84] + 764 01bc 2022 movs r2, #32 + 765 01be 1343 orrs r3, r2 + 766 01c0 6365 str r3, [r4, #84] + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 767 .loc 1 543 0 + 768 01c2 0320 movs r0, #3 + 769 01c4 00E0 b .L32 + 770 .LVL38: + 771 .L49: + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 772 .loc 1 561 0 + 773 01c6 0220 movs r0, #2 + 774 .LVL39: + 775 .L32: + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 776 .loc 1 563 0 + 777 01c8 03B0 add sp, sp, #12 + 778 @ sp needed + 779 .LVL40: + 780 .LVL41: + 781 01ca 30BD pop {r4, r5, pc} + 782 .LVL42: + 783 .L50: + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 784 .loc 1 436 0 + 785 01cc 0120 movs r0, #1 + 786 .LVL43: + 787 01ce FBE7 b .L32 + 788 .LVL44: + 789 .L51: + 790 01d0 0120 movs r0, #1 + 791 .LVL45: + 792 01d2 F9E7 b .L32 + 793 .LVL46: + 794 .L52: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 795 .loc 1 443 0 + 796 01d4 0220 movs r0, #2 + 797 .LVL47: + 798 01d6 F7E7 b .L32 + 799 .LVL48: + 800 .L53: + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 801 .loc 1 493 0 + 802 01d8 0320 movs r0, #3 + 803 01da F5E7 b .L32 + 804 .L54: + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 805 .loc 1 519 0 + 806 01dc 0320 movs r0, #3 + 807 01de F3E7 b .L32 + 808 .L63: + ARM GAS /tmp/ccApM0GN.s page 59 + + + 809 .align 2 + 810 .L62: + 811 01e0 FFDFFFFF .word -8193 + 812 .cfi_endproc + 813 .LFE43: + 815 .section .text.HAL_SPI_TransmitReceive,"ax",%progbits + 816 .align 1 + 817 .global HAL_SPI_TransmitReceive + 818 .syntax unified + 819 .code 16 + 820 .thumb_func + 821 .fpu softvfp + 823 HAL_SPI_TransmitReceive: + 824 .LFB45: + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 825 .loc 1 751 0 + 826 .cfi_startproc + 827 @ args = 4, pretend = 0, frame = 8 + 828 @ frame_needed = 0, uses_anonymous_args = 0 + 829 .LVL49: + 830 0000 30B5 push {r4, r5, lr} + 831 .LCFI6: + 832 .cfi_def_cfa_offset 12 + 833 .cfi_offset 4, -12 + 834 .cfi_offset 5, -8 + 835 .cfi_offset 14, -4 + 836 0002 83B0 sub sp, sp, #12 + 837 .LCFI7: + 838 .cfi_def_cfa_offset 24 + 839 0004 0400 movs r4, r0 + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 840 .loc 1 752 0 + 841 0006 6846 mov r0, sp + 842 .LVL50: + 843 0008 0025 movs r5, #0 + 844 000a C580 strh r5, [r0, #6] + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 845 .loc 1 754 0 + 846 000c 5120 movs r0, #81 + 847 000e 205C ldrb r0, [r4, r0] + 848 0010 0128 cmp r0, #1 + 849 0012 04D0 beq .L65 + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 850 .loc 1 754 0 is_stmt 0 discriminator 1 + 851 0014 5120 movs r0, #81 + 852 0016 205C ldrb r0, [r4, r0] + 853 0018 2228 cmp r0, #34 + 854 001a 00D0 beq .LCB812 + 855 001c A8E1 b .L88 @long jump + 856 .LCB812: + 857 .L65: + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 858 .loc 1 756 0 is_stmt 1 + 859 001e 0029 cmp r1, #0 + 860 0020 00D1 bne .LCB815 + 861 0022 A8E1 b .L89 @long jump + 862 .LCB815: + ARM GAS /tmp/ccApM0GN.s page 60 + + + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 863 .loc 1 756 0 is_stmt 0 discriminator 1 + 864 0024 002A cmp r2, #0 + 865 0026 00D1 bne .LCB817 + 866 0028 A7E1 b .L90 @long jump + 867 .LCB817: + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 868 .loc 1 756 0 discriminator 2 + 869 002a 002B cmp r3, #0 + 870 002c 00D1 bne .LCB819 + 871 002e A6E1 b .L91 @long jump + 872 .LCB819: + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 873 .loc 1 765 0 is_stmt 1 + 874 0030 5020 movs r0, #80 + 875 0032 205C ldrb r0, [r4, r0] + 876 0034 0128 cmp r0, #1 + 877 0036 00D1 bne .LCB823 + 878 0038 A3E1 b .L92 @long jump + 879 .LCB823: + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 880 .loc 1 765 0 is_stmt 0 discriminator 2 + 881 003a 5020 movs r0, #80 + 882 003c 0125 movs r5, #1 + 883 003e 2554 strb r5, [r4, r0] + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 884 .loc 1 768 0 is_stmt 1 discriminator 2 + 885 0040 0130 adds r0, r0, #1 + 886 0042 205C ldrb r0, [r4, r0] + 887 0044 0128 cmp r0, #1 + 888 0046 68D0 beq .L101 + 889 .L67: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 890 .loc 1 774 0 + 891 0048 0020 movs r0, #0 + 892 004a 6065 str r0, [r4, #84] + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 893 .loc 1 776 0 + 894 004c A263 str r2, [r4, #56] + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 895 .loc 1 777 0 + 896 004e A387 strh r3, [r4, #60] + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 897 .loc 1 778 0 + 898 0050 E387 strh r3, [r4, #62] + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 899 .loc 1 780 0 + 900 0052 2163 str r1, [r4, #48] + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 901 .loc 1 781 0 + 902 0054 A386 strh r3, [r4, #52] + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 903 .loc 1 782 0 + 904 0056 E386 strh r3, [r4, #54] + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 905 .loc 1 785 0 + 906 0058 A064 str r0, [r4, #72] + ARM GAS /tmp/ccApM0GN.s page 61 + + + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 907 .loc 1 786 0 + 908 005a E064 str r0, [r4, #76] + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 909 .loc 1 789 0 + 910 005c 8023 movs r3, #128 + 911 .LVL51: + 912 005e 9B01 lsls r3, r3, #6 + 913 0060 A26A ldr r2, [r4, #40] + 914 .LVL52: + 915 0062 9A42 cmp r2, r3 + 916 0064 5DD0 beq .L102 + 917 .LVL53: + 918 .L68: + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 919 .loc 1 795 0 + 920 0066 2368 ldr r3, [r4] + 921 0068 1A68 ldr r2, [r3] + 922 006a 5206 lsls r2, r2, #25 + 923 006c 03D4 bmi .L69 + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 924 .loc 1 798 0 + 925 006e 1A68 ldr r2, [r3] + 926 0070 4021 movs r1, #64 + 927 0072 0A43 orrs r2, r1 + 928 0074 1A60 str r2, [r3] + 929 .L69: + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 930 .loc 1 802 0 + 931 0076 8023 movs r3, #128 + 932 0078 1B01 lsls r3, r3, #4 + 933 007a E268 ldr r2, [r4, #12] + 934 007c 9A42 cmp r2, r3 + 935 007e 5CD0 beq .L103 + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 936 .loc 1 876 0 + 937 0080 6368 ldr r3, [r4, #4] + 938 0082 002B cmp r3, #0 + 939 0084 07D0 beq .L78 + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 940 .loc 1 876 0 is_stmt 0 discriminator 1 + 941 0086 8222 movs r2, #130 + 942 0088 5200 lsls r2, r2, #1 + 943 008a 9342 cmp r3, r2 + 944 008c 0DD1 bne .L79 + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 945 .loc 1 876 0 discriminator 2 + 946 008e E38E ldrh r3, [r4, #54] + 947 0090 9BB2 uxth r3, r3 + 948 0092 012B cmp r3, #1 + 949 0094 09D1 bne .L79 + 950 .L78: + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 951 .loc 1 878 0 is_stmt 1 + 952 0096 236B ldr r3, [r4, #48] + 953 0098 5A1C adds r2, r3, #1 + 954 009a 2263 str r2, [r4, #48] + ARM GAS /tmp/ccApM0GN.s page 62 + + + 955 009c 2268 ldr r2, [r4] + 956 009e 1B78 ldrb r3, [r3] + 957 00a0 D360 str r3, [r2, #12] + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 958 .loc 1 879 0 + 959 00a2 E38E ldrh r3, [r4, #54] + 960 00a4 013B subs r3, r3, #1 + 961 00a6 9BB2 uxth r3, r3 + 962 00a8 E386 strh r3, [r4, #54] + 963 .L79: + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 964 .loc 1 881 0 + 965 00aa E38E ldrh r3, [r4, #54] + 966 00ac 9BB2 uxth r3, r3 + 967 00ae 002B cmp r3, #0 + 968 00b0 00D0 beq .LCB902 + 969 00b2 ECE0 b .L80 @long jump + 970 .LCB902: + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 971 .loc 1 884 0 + 972 00b4 8023 movs r3, #128 + 973 00b6 9B01 lsls r3, r3, #6 + 974 00b8 A26A ldr r2, [r4, #40] + 975 00ba 9A42 cmp r2, r3 + 976 00bc 00D1 bne .LCB908 + 977 00be CCE0 b .L104 @long jump + 978 .LCB908: + 979 .L81: + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 980 .loc 1 890 0 + 981 00c0 069B ldr r3, [sp, #24] + 982 00c2 0022 movs r2, #0 + 983 00c4 0121 movs r1, #1 + 984 00c6 2000 movs r0, r4 + 985 00c8 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 986 .LVL54: + 987 00cc 0028 cmp r0, #0 + 988 00ce 00D0 beq .LCB917 + 989 00d0 61E1 b .L97 @long jump + 990 .LCB917: + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 991 .loc 1 895 0 + 992 00d2 2368 ldr r3, [r4] + 993 00d4 DB68 ldr r3, [r3, #12] + 994 00d6 A26B ldr r2, [r4, #56] + 995 00d8 1370 strb r3, [r2] + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 996 .loc 1 896 0 + 997 00da E38F ldrh r3, [r4, #62] + 998 00dc 013B subs r3, r3, #1 + 999 00de 9BB2 uxth r3, r3 + 1000 00e0 E387 strh r3, [r4, #62] + 1001 .L75: + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1002 .loc 1 941 0 + 1003 00e2 8023 movs r3, #128 + 1004 00e4 9B01 lsls r3, r3, #6 + ARM GAS /tmp/ccApM0GN.s page 63 + + + 1005 00e6 A26A ldr r2, [r4, #40] + 1006 00e8 9A42 cmp r2, r3 + 1007 00ea 00D1 bne .LCB936 + 1008 00ec 0DE1 b .L105 @long jump + 1009 .LCB936: + 1010 .L84: + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1011 .loc 1 955 0 + 1012 00ee 069B ldr r3, [sp, #24] + 1013 00f0 0122 movs r2, #1 + 1014 00f2 8021 movs r1, #128 + 1015 00f4 2000 movs r0, r4 + 1016 00f6 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1017 .LVL55: + 1018 00fa 0028 cmp r0, #0 + 1019 00fc 00D0 beq .LCB945 + 1020 00fe 19E1 b .L106 @long jump + 1021 .LCB945: + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1022 .loc 1 961 0 + 1023 0100 5123 movs r3, #81 + 1024 0102 0122 movs r2, #1 + 1025 0104 E254 strb r2, [r4, r3] + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1026 .loc 1 964 0 + 1027 0106 8023 movs r3, #128 + 1028 0108 9B01 lsls r3, r3, #6 + 1029 010a A26A ldr r2, [r4, #40] + 1030 010c 9A42 cmp r2, r3 + 1031 010e 00D1 bne .LCB954 + 1032 0110 16E1 b .L107 @long jump + 1033 .LCB954: + 1034 .L87: + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1035 .loc 1 977 0 + 1036 0112 5023 movs r3, #80 + 1037 0114 0022 movs r2, #0 + 1038 0116 E254 strb r2, [r4, r3] + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1039 .loc 1 979 0 + 1040 0118 2BE1 b .L66 + 1041 .LVL56: + 1042 .L101: + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1043 .loc 1 770 0 + 1044 011a 5030 adds r0, r0, #80 + 1045 011c 3135 adds r5, r5, #49 + 1046 011e 2554 strb r5, [r4, r0] + 1047 0120 92E7 b .L67 + 1048 .LVL57: + 1049 .L102: + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1050 .loc 1 791 0 + 1051 0122 2268 ldr r2, [r4] + 1052 0124 1368 ldr r3, [r2] + 1053 0126 A049 ldr r1, .L112 + 1054 .LVL58: + ARM GAS /tmp/ccApM0GN.s page 64 + + + 1055 0128 0B40 ands r3, r1 + 1056 012a 1360 str r3, [r2] + 1057 .LVL59: + 1058 012c 2268 ldr r2, [r4] + 1059 012e 1168 ldr r1, [r2] + 1060 0130 8023 movs r3, #128 + 1061 0132 9B01 lsls r3, r3, #6 + 1062 0134 0B43 orrs r3, r1 + 1063 0136 1360 str r3, [r2] + 1064 0138 95E7 b .L68 + 1065 .L103: + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1066 .loc 1 804 0 + 1067 013a 6368 ldr r3, [r4, #4] + 1068 013c 002B cmp r3, #0 + 1069 013e 07D0 beq .L71 + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1070 .loc 1 804 0 is_stmt 0 discriminator 1 + 1071 0140 8222 movs r2, #130 + 1072 0142 5200 lsls r2, r2, #1 + 1073 0144 9342 cmp r3, r2 + 1074 0146 0ED1 bne .L72 + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1075 .loc 1 804 0 discriminator 2 + 1076 0148 E38E ldrh r3, [r4, #54] + 1077 014a 9BB2 uxth r3, r3 + 1078 014c 012B cmp r3, #1 + 1079 014e 0AD1 bne .L72 + 1080 .L71: + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 1081 .loc 1 806 0 is_stmt 1 + 1082 0150 2368 ldr r3, [r4] + 1083 0152 226B ldr r2, [r4, #48] + 1084 0154 1288 ldrh r2, [r2] + 1085 0156 DA60 str r2, [r3, #12] + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 1086 .loc 1 807 0 + 1087 0158 236B ldr r3, [r4, #48] + 1088 015a 0233 adds r3, r3, #2 + 1089 015c 2363 str r3, [r4, #48] + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1090 .loc 1 808 0 + 1091 015e E38E ldrh r3, [r4, #54] + 1092 0160 013B subs r3, r3, #1 + 1093 0162 9BB2 uxth r3, r3 + 1094 0164 E386 strh r3, [r4, #54] + 1095 .L72: + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1096 .loc 1 810 0 + 1097 0166 E38E ldrh r3, [r4, #54] + 1098 0168 9BB2 uxth r3, r3 + 1099 016a 002B cmp r3, #0 + 1100 016c 34D1 bne .L73 + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1101 .loc 1 813 0 + 1102 016e 8023 movs r3, #128 + 1103 0170 9B01 lsls r3, r3, #6 + ARM GAS /tmp/ccApM0GN.s page 65 + + + 1104 0172 A26A ldr r2, [r4, #40] + 1105 0174 9A42 cmp r2, r3 + 1106 0176 14D0 beq .L108 + 1107 .L74: + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1108 .loc 1 819 0 + 1109 0178 069B ldr r3, [sp, #24] + 1110 017a 0022 movs r2, #0 + 1111 017c 0121 movs r1, #1 + 1112 017e 2000 movs r0, r4 + 1113 0180 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1114 .LVL60: + 1115 0184 0028 cmp r0, #0 + 1116 0186 00D0 beq .LCB1046 + 1117 0188 FDE0 b .L93 @long jump + 1118 .LCB1046: + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 1119 .loc 1 824 0 + 1120 018a 2368 ldr r3, [r4] + 1121 018c DB68 ldr r3, [r3, #12] + 1122 018e A26B ldr r2, [r4, #56] + 1123 0190 1380 strh r3, [r2] + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1124 .loc 1 825 0 + 1125 0192 A36B ldr r3, [r4, #56] + 1126 0194 0233 adds r3, r3, #2 + 1127 0196 A363 str r3, [r4, #56] + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1128 .loc 1 826 0 + 1129 0198 E38F ldrh r3, [r4, #62] + 1130 019a 013B subs r3, r3, #1 + 1131 019c 9BB2 uxth r3, r3 + 1132 019e E387 strh r3, [r4, #62] + 1133 01a0 9FE7 b .L75 + 1134 .L108: + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1135 .loc 1 815 0 + 1136 01a2 2268 ldr r2, [r4] + 1137 01a4 1168 ldr r1, [r2] + 1138 01a6 8023 movs r3, #128 + 1139 01a8 5B01 lsls r3, r3, #5 + 1140 01aa 0B43 orrs r3, r1 + 1141 01ac 1360 str r3, [r2] + 1142 01ae E3E7 b .L74 + 1143 .L76: + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1144 .loc 1 849 0 + 1145 01b0 069B ldr r3, [sp, #24] + 1146 01b2 0022 movs r2, #0 + 1147 01b4 0121 movs r1, #1 + 1148 01b6 2000 movs r0, r4 + 1149 01b8 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1150 .LVL61: + 1151 01bc 0028 cmp r0, #0 + 1152 01be 00D0 beq .LCB1086 + 1153 01c0 E5E0 b .L95 @long jump + 1154 .LCB1086: + ARM GAS /tmp/ccApM0GN.s page 66 + + + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 1155 .loc 1 854 0 + 1156 01c2 2368 ldr r3, [r4] + 1157 01c4 DB68 ldr r3, [r3, #12] + 1158 01c6 A26B ldr r2, [r4, #56] + 1159 01c8 1380 strh r3, [r2] + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1160 .loc 1 855 0 + 1161 01ca A36B ldr r3, [r4, #56] + 1162 01cc 0233 adds r3, r3, #2 + 1163 01ce A363 str r3, [r4, #56] + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1164 .loc 1 856 0 + 1165 01d0 E38F ldrh r3, [r4, #62] + 1166 01d2 013B subs r3, r3, #1 + 1167 01d4 9BB2 uxth r3, r3 + 1168 01d6 E387 strh r3, [r4, #62] + 1169 .L73: + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1170 .loc 1 830 0 + 1171 01d8 E38E ldrh r3, [r4, #54] + 1172 01da 9BB2 uxth r3, r3 + 1173 01dc 002B cmp r3, #0 + 1174 01de 23D0 beq .L109 + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1175 .loc 1 833 0 + 1176 01e0 069B ldr r3, [sp, #24] + 1177 01e2 0022 movs r2, #0 + 1178 01e4 0221 movs r1, #2 + 1179 01e6 2000 movs r0, r4 + 1180 01e8 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1181 .LVL62: + 1182 01ec 0028 cmp r0, #0 + 1183 01ee 00D0 beq .LCB1115 + 1184 01f0 CBE0 b .L94 @long jump + 1185 .LCB1115: + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 1186 .loc 1 838 0 + 1187 01f2 2368 ldr r3, [r4] + 1188 01f4 226B ldr r2, [r4, #48] + 1189 01f6 1288 ldrh r2, [r2] + 1190 01f8 DA60 str r2, [r3, #12] + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 1191 .loc 1 839 0 + 1192 01fa 236B ldr r3, [r4, #48] + 1193 01fc 0233 adds r3, r3, #2 + 1194 01fe 2363 str r3, [r4, #48] + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1195 .loc 1 840 0 + 1196 0200 E38E ldrh r3, [r4, #54] + 1197 0202 013B subs r3, r3, #1 + 1198 0204 9BB2 uxth r3, r3 + 1199 0206 E386 strh r3, [r4, #54] + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1200 .loc 1 843 0 + 1201 0208 E38E ldrh r3, [r4, #54] + 1202 020a 9BB2 uxth r3, r3 + ARM GAS /tmp/ccApM0GN.s page 67 + + + 1203 020c 002B cmp r3, #0 + 1204 020e CFD1 bne .L76 + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1205 .loc 1 843 0 is_stmt 0 discriminator 1 + 1206 0210 8023 movs r3, #128 + 1207 0212 9B01 lsls r3, r3, #6 + 1208 0214 A26A ldr r2, [r4, #40] + 1209 0216 9A42 cmp r2, r3 + 1210 0218 CAD1 bne .L76 + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1211 .loc 1 845 0 is_stmt 1 + 1212 021a 2268 ldr r2, [r4] + 1213 021c 1168 ldr r1, [r2] + 1214 021e 8023 movs r3, #128 + 1215 0220 5B01 lsls r3, r3, #5 + 1216 0222 0B43 orrs r3, r1 + 1217 0224 1360 str r3, [r2] + 1218 0226 C3E7 b .L76 + 1219 .L109: + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1220 .loc 1 859 0 + 1221 0228 6368 ldr r3, [r4, #4] + 1222 022a 002B cmp r3, #0 + 1223 022c 00D0 beq .LCB1154 + 1224 022e 58E7 b .L75 @long jump + 1225 .LCB1154: + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1226 .loc 1 862 0 + 1227 0230 069B ldr r3, [sp, #24] + 1228 0232 0022 movs r2, #0 + 1229 0234 0121 movs r1, #1 + 1230 0236 2000 movs r0, r4 + 1231 0238 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1232 .LVL63: + 1233 023c 0028 cmp r0, #0 + 1234 023e 00D0 beq .LCB1162 + 1235 0240 A7E0 b .L96 @long jump + 1236 .LCB1162: + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 1237 .loc 1 867 0 + 1238 0242 2368 ldr r3, [r4] + 1239 0244 DB68 ldr r3, [r3, #12] + 1240 0246 A26B ldr r2, [r4, #56] + 1241 0248 1380 strh r3, [r2] + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1242 .loc 1 868 0 + 1243 024a A36B ldr r3, [r4, #56] + 1244 024c 0233 adds r3, r3, #2 + 1245 024e A363 str r3, [r4, #56] + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1246 .loc 1 869 0 + 1247 0250 E38F ldrh r3, [r4, #62] + 1248 0252 013B subs r3, r3, #1 + 1249 0254 9BB2 uxth r3, r3 + 1250 0256 E387 strh r3, [r4, #62] + 1251 0258 43E7 b .L75 + 1252 .L104: + ARM GAS /tmp/ccApM0GN.s page 68 + + + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1253 .loc 1 886 0 + 1254 025a 2268 ldr r2, [r4] + 1255 025c 1168 ldr r1, [r2] + 1256 025e 8023 movs r3, #128 + 1257 0260 5B01 lsls r3, r3, #5 + 1258 0262 0B43 orrs r3, r1 + 1259 0264 1360 str r3, [r2] + 1260 0266 2BE7 b .L81 + 1261 .L82: + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1262 .loc 1 918 0 + 1263 0268 069B ldr r3, [sp, #24] + 1264 026a 0022 movs r2, #0 + 1265 026c 0121 movs r1, #1 + 1266 026e 2000 movs r0, r4 + 1267 0270 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1268 .LVL64: + 1269 0274 0028 cmp r0, #0 + 1270 0276 00D0 beq .LCB1202 + 1271 0278 91E0 b .L99 @long jump + 1272 .LCB1202: + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1273 .loc 1 923 0 + 1274 027a 2368 ldr r3, [r4] + 1275 027c DA68 ldr r2, [r3, #12] + 1276 027e A36B ldr r3, [r4, #56] + 1277 0280 591C adds r1, r3, #1 + 1278 0282 A163 str r1, [r4, #56] + 1279 0284 1A70 strb r2, [r3] + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1280 .loc 1 924 0 + 1281 0286 E38F ldrh r3, [r4, #62] + 1282 0288 013B subs r3, r3, #1 + 1283 028a 9BB2 uxth r3, r3 + 1284 028c E387 strh r3, [r4, #62] + 1285 .L80: + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1286 .loc 1 900 0 + 1287 028e E38E ldrh r3, [r4, #54] + 1288 0290 9BB2 uxth r3, r3 + 1289 0292 002B cmp r3, #0 + 1290 0294 22D0 beq .L110 + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1291 .loc 1 903 0 + 1292 0296 069B ldr r3, [sp, #24] + 1293 0298 0022 movs r2, #0 + 1294 029a 0221 movs r1, #2 + 1295 029c 2000 movs r0, r4 + 1296 029e FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1297 .LVL65: + 1298 02a2 0028 cmp r0, #0 + 1299 02a4 00D0 beq .LCB1228 + 1300 02a6 78E0 b .L98 @long jump + 1301 .LCB1228: + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount--; + 1302 .loc 1 908 0 + ARM GAS /tmp/ccApM0GN.s page 69 + + + 1303 02a8 236B ldr r3, [r4, #48] + 1304 02aa 5A1C adds r2, r3, #1 + 1305 02ac 2263 str r2, [r4, #48] + 1306 02ae 2268 ldr r2, [r4] + 1307 02b0 1B78 ldrb r3, [r3] + 1308 02b2 D360 str r3, [r2, #12] + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1309 .loc 1 909 0 + 1310 02b4 E38E ldrh r3, [r4, #54] + 1311 02b6 013B subs r3, r3, #1 + 1312 02b8 9BB2 uxth r3, r3 + 1313 02ba E386 strh r3, [r4, #54] + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1314 .loc 1 912 0 + 1315 02bc E38E ldrh r3, [r4, #54] + 1316 02be 9BB2 uxth r3, r3 + 1317 02c0 002B cmp r3, #0 + 1318 02c2 D1D1 bne .L82 + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1319 .loc 1 912 0 is_stmt 0 discriminator 1 + 1320 02c4 8023 movs r3, #128 + 1321 02c6 9B01 lsls r3, r3, #6 + 1322 02c8 A26A ldr r2, [r4, #40] + 1323 02ca 9A42 cmp r2, r3 + 1324 02cc CCD1 bne .L82 + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1325 .loc 1 914 0 is_stmt 1 + 1326 02ce 2268 ldr r2, [r4] + 1327 02d0 1168 ldr r1, [r2] + 1328 02d2 8023 movs r3, #128 + 1329 02d4 5B01 lsls r3, r3, #5 + 1330 02d6 0B43 orrs r3, r1 + 1331 02d8 1360 str r3, [r2] + 1332 02da C5E7 b .L82 + 1333 .L110: + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1334 .loc 1 926 0 + 1335 02dc 6368 ldr r3, [r4, #4] + 1336 02de 002B cmp r3, #0 + 1337 02e0 00D0 beq .LCB1264 + 1338 02e2 FEE6 b .L75 @long jump + 1339 .LCB1264: + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1340 .loc 1 929 0 + 1341 02e4 069B ldr r3, [sp, #24] + 1342 02e6 0022 movs r2, #0 + 1343 02e8 0121 movs r1, #1 + 1344 02ea 2000 movs r0, r4 + 1345 02ec FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1346 .LVL66: + 1347 02f0 0028 cmp r0, #0 + 1348 02f2 56D1 bne .L100 + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1349 .loc 1 934 0 + 1350 02f4 2368 ldr r3, [r4] + 1351 02f6 DA68 ldr r2, [r3, #12] + 1352 02f8 A36B ldr r3, [r4, #56] + ARM GAS /tmp/ccApM0GN.s page 70 + + + 1353 02fa 591C adds r1, r3, #1 + 1354 02fc A163 str r1, [r4, #56] + 1355 02fe 1A70 strb r2, [r3] + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1356 .loc 1 935 0 + 1357 0300 E38F ldrh r3, [r4, #62] + 1358 0302 013B subs r3, r3, #1 + 1359 0304 9BB2 uxth r3, r3 + 1360 0306 E387 strh r3, [r4, #62] + 1361 0308 EBE6 b .L75 + 1362 .L105: + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1363 .loc 1 944 0 + 1364 030a 069B ldr r3, [sp, #24] + 1365 030c 0022 movs r2, #0 + 1366 030e 0121 movs r1, #1 + 1367 0310 2000 movs r0, r4 + 1368 0312 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1369 .LVL67: + 1370 0316 0028 cmp r0, #0 + 1371 0318 06D1 bne .L111 + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + 1372 .loc 1 950 0 + 1373 031a 2368 ldr r3, [r4] + 1374 031c DB68 ldr r3, [r3, #12] + 1375 031e 9BB2 uxth r3, r3 + 1376 0320 6A46 mov r2, sp + 1377 0322 D380 strh r3, [r2, #6] + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1378 .loc 1 951 0 + 1379 0324 D388 ldrh r3, [r2, #6] + 1380 0326 E2E6 b .L84 + 1381 .L111: + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 1382 .loc 1 946 0 + 1383 0328 636D ldr r3, [r4, #84] + 1384 032a 0222 movs r2, #2 + 1385 032c 1343 orrs r3, r2 + 1386 032e 6365 str r3, [r4, #84] + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1387 .loc 1 947 0 + 1388 0330 0320 movs r0, #3 + 1389 0332 1EE0 b .L66 + 1390 .L106: + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 1391 .loc 1 957 0 + 1392 0334 636D ldr r3, [r4, #84] + 1393 0336 2022 movs r2, #32 + 1394 0338 1343 orrs r3, r2 + 1395 033a 6365 str r3, [r4, #84] + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1396 .loc 1 958 0 + 1397 033c 0320 movs r0, #3 + 1398 033e 18E0 b .L66 + 1399 .L107: + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1400 .loc 1 964 0 discriminator 1 + ARM GAS /tmp/ccApM0GN.s page 71 + + + 1401 0340 2368 ldr r3, [r4] + 1402 0342 9A68 ldr r2, [r3, #8] + 1403 0344 D206 lsls r2, r2, #27 + 1404 0346 00D4 bmi .LCB1332 + 1405 0348 E3E6 b .L87 @long jump + 1406 .LCB1332: + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1407 .loc 1 966 0 + 1408 034a 626D ldr r2, [r4, #84] + 1409 034c 0221 movs r1, #2 + 1410 034e 0A43 orrs r2, r1 + 1411 0350 6265 str r2, [r4, #84] + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1412 .loc 1 968 0 + 1413 0352 1A68 ldr r2, [r3] + 1414 0354 1449 ldr r1, .L112 + 1415 0356 0A40 ands r2, r1 + 1416 0358 1A60 str r2, [r3] + 1417 035a 2268 ldr r2, [r4] + 1418 035c 1168 ldr r1, [r2] + 1419 035e 8023 movs r3, #128 + 1420 0360 9B01 lsls r3, r3, #6 + 1421 0362 0B43 orrs r3, r1 + 1422 0364 1360 str r3, [r2] + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1423 .loc 1 971 0 + 1424 0366 5023 movs r3, #80 + 1425 0368 0022 movs r2, #0 + 1426 036a E254 strb r2, [r4, r3] + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1427 .loc 1 973 0 + 1428 036c 0120 movs r0, #1 + 1429 036e 00E0 b .L66 + 1430 .LVL68: + 1431 .L88: + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1432 .loc 1 983 0 + 1433 0370 0220 movs r0, #2 + 1434 .LVL69: + 1435 .L66: + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1436 .loc 1 985 0 + 1437 0372 03B0 add sp, sp, #12 + 1438 @ sp needed + 1439 .LVL70: + 1440 0374 30BD pop {r4, r5, pc} + 1441 .LVL71: + 1442 .L89: + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1443 .loc 1 758 0 + 1444 0376 0120 movs r0, #1 + 1445 0378 FBE7 b .L66 + 1446 .L90: + 1447 037a 0120 movs r0, #1 + 1448 037c F9E7 b .L66 + 1449 .L91: + 1450 037e 0120 movs r0, #1 + ARM GAS /tmp/ccApM0GN.s page 72 + + + 1451 0380 F7E7 b .L66 + 1452 .L92: + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1453 .loc 1 765 0 + 1454 0382 0220 movs r0, #2 + 1455 0384 F5E7 b .L66 + 1456 .LVL72: + 1457 .L93: + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1458 .loc 1 821 0 + 1459 0386 0320 movs r0, #3 + 1460 0388 F3E7 b .L66 + 1461 .L94: + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1462 .loc 1 835 0 + 1463 038a 0320 movs r0, #3 + 1464 038c F1E7 b .L66 + 1465 .L95: + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1466 .loc 1 851 0 + 1467 038e 0320 movs r0, #3 + 1468 0390 EFE7 b .L66 + 1469 .L96: + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1470 .loc 1 864 0 + 1471 0392 0320 movs r0, #3 + 1472 0394 EDE7 b .L66 + 1473 .L97: + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1474 .loc 1 892 0 + 1475 0396 0320 movs r0, #3 + 1476 0398 EBE7 b .L66 + 1477 .L98: + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1478 .loc 1 905 0 + 1479 039a 0320 movs r0, #3 + 1480 039c E9E7 b .L66 + 1481 .L99: + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1482 .loc 1 920 0 + 1483 039e 0320 movs r0, #3 + 1484 03a0 E7E7 b .L66 + 1485 .L100: + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1486 .loc 1 931 0 + 1487 03a2 0320 movs r0, #3 + 1488 03a4 E5E7 b .L66 + 1489 .L113: + 1490 03a6 C046 .align 2 + 1491 .L112: + 1492 03a8 FFDFFFFF .word -8193 + 1493 .cfi_endproc + 1494 .LFE45: + 1496 .section .text.HAL_SPI_Receive,"ax",%progbits + 1497 .align 1 + 1498 .global HAL_SPI_Receive + 1499 .syntax unified + ARM GAS /tmp/ccApM0GN.s page 73 + + + 1500 .code 16 + 1501 .thumb_func + 1502 .fpu softvfp + 1504 HAL_SPI_Receive: + 1505 .LFB44: + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 1506 .loc 1 575 0 + 1507 .cfi_startproc + 1508 @ args = 0, pretend = 0, frame = 8 + 1509 @ frame_needed = 0, uses_anonymous_args = 0 + 1510 .LVL73: + 1511 0000 70B5 push {r4, r5, r6, lr} + 1512 .LCFI8: + 1513 .cfi_def_cfa_offset 16 + 1514 .cfi_offset 4, -16 + 1515 .cfi_offset 5, -12 + 1516 .cfi_offset 6, -8 + 1517 .cfi_offset 14, -4 + 1518 0002 84B0 sub sp, sp, #16 + 1519 .LCFI9: + 1520 .cfi_def_cfa_offset 32 + 1521 0004 0400 movs r4, r0 + 1522 0006 1D00 movs r5, r3 + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1523 .loc 1 576 0 + 1524 0008 0E23 movs r3, #14 + 1525 .LVL74: + 1526 000a 6B44 add r3, r3, sp + 1527 000c 0020 movs r0, #0 + 1528 .LVL75: + 1529 000e 1880 strh r0, [r3] + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1530 .loc 1 578 0 + 1531 0010 5123 movs r3, #81 + 1532 0012 E35C ldrb r3, [r4, r3] + 1533 0014 012B cmp r3, #1 + 1534 0016 00D0 beq .LCB1492 + 1535 0018 0EE1 b .L132 @long jump + 1536 .LCB1492: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1537 .loc 1 580 0 + 1538 001a 0029 cmp r1, #0 + 1539 001c 00D1 bne .LCB1494 + 1540 001e 0FE1 b .L133 @long jump + 1541 .LCB1494: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1542 .loc 1 580 0 is_stmt 0 discriminator 1 + 1543 0020 002A cmp r2, #0 + 1544 0022 00D1 bne .LCB1496 + 1545 0024 0EE1 b .L134 @long jump + 1546 .LCB1496: + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1547 .loc 1 586 0 is_stmt 1 + 1548 0026 4F33 adds r3, r3, #79 + 1549 0028 E35C ldrb r3, [r4, r3] + 1550 002a 012B cmp r3, #1 + 1551 002c 00D1 bne .LCB1500 + ARM GAS /tmp/ccApM0GN.s page 74 + + + 1552 002e 0BE1 b .L135 @long jump + 1553 .LCB1500: + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1554 .loc 1 586 0 is_stmt 0 discriminator 2 + 1555 0030 5023 movs r3, #80 + 1556 0032 0130 adds r0, r0, #1 + 1557 0034 E054 strb r0, [r4, r3] + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1558 .loc 1 589 0 is_stmt 1 discriminator 2 + 1559 0036 0133 adds r3, r3, #1 + 1560 0038 2130 adds r0, r0, #33 + 1561 003a E054 strb r0, [r4, r3] + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1562 .loc 1 590 0 discriminator 2 + 1563 003c 0023 movs r3, #0 + 1564 003e 6365 str r3, [r4, #84] + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 1565 .loc 1 592 0 discriminator 2 + 1566 0040 A163 str r1, [r4, #56] + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 1567 .loc 1 593 0 discriminator 2 + 1568 0042 A287 strh r2, [r4, #60] + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1569 .loc 1 594 0 discriminator 2 + 1570 0044 E287 strh r2, [r4, #62] + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 1571 .loc 1 597 0 discriminator 2 + 1572 0046 A364 str r3, [r4, #72] + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = NULL; + 1573 .loc 1 598 0 discriminator 2 + 1574 0048 E364 str r3, [r4, #76] + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; + 1575 .loc 1 599 0 discriminator 2 + 1576 004a 2363 str r3, [r4, #48] + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; + 1577 .loc 1 600 0 discriminator 2 + 1578 004c A386 strh r3, [r4, #52] + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1579 .loc 1 601 0 discriminator 2 + 1580 004e E386 strh r3, [r4, #54] + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1581 .loc 1 604 0 discriminator 2 + 1582 0050 8023 movs r3, #128 + 1583 0052 1B02 lsls r3, r3, #8 + 1584 0054 A068 ldr r0, [r4, #8] + 1585 0056 9842 cmp r0, r3 + 1586 0058 2ED0 beq .L139 + 1587 .L116: + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1588 .loc 1 610 0 + 1589 005a 8023 movs r3, #128 + 1590 005c 9B01 lsls r3, r3, #6 + 1591 005e A06A ldr r0, [r4, #40] + 1592 0060 9842 cmp r0, r3 + 1593 0062 2FD0 beq .L140 + 1594 .L117: + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 75 + + + 1595 .loc 1 615 0 + 1596 0064 8223 movs r3, #130 + 1597 0066 5B00 lsls r3, r3, #1 + 1598 0068 6068 ldr r0, [r4, #4] + 1599 006a 9842 cmp r0, r3 + 1600 006c 36D0 beq .L141 + 1601 .L118: + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1602 .loc 1 625 0 + 1603 006e 2368 ldr r3, [r4] + 1604 0070 1A68 ldr r2, [r3] + 1605 .LVL76: + 1606 0072 5206 lsls r2, r2, #25 + 1607 0074 03D4 bmi .L119 + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1608 .loc 1 628 0 + 1609 0076 1A68 ldr r2, [r3] + 1610 0078 4021 movs r1, #64 + 1611 .LVL77: + 1612 007a 0A43 orrs r2, r1 + 1613 007c 1A60 str r2, [r3] + 1614 .L119: + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1615 .loc 1 632 0 + 1616 007e E368 ldr r3, [r4, #12] + 1617 0080 002B cmp r3, #0 + 1618 0082 39D0 beq .L120 + 1619 .L121: + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1620 .loc 1 654 0 + 1621 0084 E38F ldrh r3, [r4, #62] + 1622 0086 9BB2 uxth r3, r3 + 1623 0088 012B cmp r3, #1 + 1624 008a 00D8 bhi .LCB1562 + 1625 008c 84E0 b .L142 @long jump + 1626 .LCB1562: + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1627 .loc 1 657 0 + 1628 008e 2B00 movs r3, r5 + 1629 0090 0022 movs r2, #0 + 1630 0092 0121 movs r1, #1 + 1631 0094 2000 movs r0, r4 + 1632 0096 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1633 .LVL78: + 1634 009a 0028 cmp r0, #0 + 1635 009c 00D0 beq .LCB1570 + 1636 009e D7E0 b .L137 @long jump + 1637 .LCB1570: + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 1638 .loc 1 662 0 + 1639 00a0 2368 ldr r3, [r4] + 1640 00a2 DB68 ldr r3, [r3, #12] + 1641 00a4 A26B ldr r2, [r4, #56] + 1642 00a6 1380 strh r3, [r2] + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1643 .loc 1 663 0 + 1644 00a8 A36B ldr r3, [r4, #56] + ARM GAS /tmp/ccApM0GN.s page 76 + + + 1645 00aa 0233 adds r3, r3, #2 + 1646 00ac A363 str r3, [r4, #56] + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1647 .loc 1 664 0 + 1648 00ae E38F ldrh r3, [r4, #62] + 1649 00b0 013B subs r3, r3, #1 + 1650 00b2 9BB2 uxth r3, r3 + 1651 00b4 E387 strh r3, [r4, #62] + 1652 00b6 E5E7 b .L121 + 1653 .LVL79: + 1654 .L139: + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1655 .loc 1 606 0 + 1656 00b8 2068 ldr r0, [r4] + 1657 00ba 0368 ldr r3, [r0] + 1658 00bc 664E ldr r6, .L149 + 1659 00be 3340 ands r3, r6 + 1660 00c0 0360 str r3, [r0] + 1661 00c2 CAE7 b .L116 + 1662 .L140: + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1663 .loc 1 612 0 + 1664 00c4 2068 ldr r0, [r4] + 1665 00c6 0368 ldr r3, [r0] + 1666 00c8 644E ldr r6, .L149+4 + 1667 00ca 3340 ands r3, r6 + 1668 00cc 0360 str r3, [r0] + 1669 00ce 2068 ldr r0, [r4] + 1670 00d0 0668 ldr r6, [r0] + 1671 00d2 8023 movs r3, #128 + 1672 00d4 9B01 lsls r3, r3, #6 + 1673 00d6 3343 orrs r3, r6 + 1674 00d8 0360 str r3, [r0] + 1675 00da C3E7 b .L117 + 1676 .L141: + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1677 .loc 1 615 0 discriminator 1 + 1678 00dc A368 ldr r3, [r4, #8] + 1679 00de 002B cmp r3, #0 + 1680 00e0 C5D1 bne .L118 + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1681 .loc 1 618 0 + 1682 00e2 5033 adds r3, r3, #80 + 1683 00e4 0020 movs r0, #0 + 1684 00e6 E054 strb r0, [r4, r3] + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1685 .loc 1 621 0 + 1686 00e8 0095 str r5, [sp] + 1687 00ea 1300 movs r3, r2 + 1688 00ec 0A00 movs r2, r1 + 1689 .LVL80: + 1690 00ee 2000 movs r0, r4 + 1691 00f0 FFF7FEFF bl HAL_SPI_TransmitReceive + 1692 .LVL81: + 1693 00f4 0600 movs r6, r0 + 1694 00f6 A0E0 b .L115 + 1695 .L120: + ARM GAS /tmp/ccApM0GN.s page 77 + + + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1696 .loc 1 634 0 + 1697 00f8 E38F ldrh r3, [r4, #62] + 1698 00fa 9BB2 uxth r3, r3 + 1699 00fc 012B cmp r3, #1 + 1700 00fe 13D9 bls .L143 + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1701 .loc 1 637 0 + 1702 0100 2B00 movs r3, r5 + 1703 0102 0022 movs r2, #0 + 1704 0104 0121 movs r1, #1 + 1705 0106 2000 movs r0, r4 + 1706 0108 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1707 .LVL82: + 1708 010c 0028 cmp r0, #0 + 1709 010e 00D0 beq .LCB1653 + 1710 0110 9CE0 b .L136 @long jump + 1711 .LCB1653: + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount--; + 1712 .loc 1 642 0 + 1713 0112 2368 ldr r3, [r4] + 1714 0114 DA68 ldr r2, [r3, #12] + 1715 0116 A36B ldr r3, [r4, #56] + 1716 0118 591C adds r1, r3, #1 + 1717 011a A163 str r1, [r4, #56] + 1718 011c 1A70 strb r2, [r3] + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1719 .loc 1 643 0 + 1720 011e E38F ldrh r3, [r4, #62] + 1721 0120 013B subs r3, r3, #1 + 1722 0122 9BB2 uxth r3, r3 + 1723 0124 E387 strh r3, [r4, #62] + 1724 0126 E7E7 b .L120 + 1725 .L143: + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1726 .loc 1 646 0 + 1727 0128 8023 movs r3, #128 + 1728 012a 9B01 lsls r3, r3, #6 + 1729 012c A26A ldr r2, [r4, #40] + 1730 012e 9A42 cmp r2, r3 + 1731 0130 2BD0 beq .L144 + 1732 .L123: + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1733 .loc 1 674 0 + 1734 0132 2B00 movs r3, r5 + 1735 0134 0022 movs r2, #0 + 1736 0136 0121 movs r1, #1 + 1737 0138 2000 movs r0, r4 + 1738 013a FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1739 .LVL83: + 1740 013e 061E subs r6, r0, #0 + 1741 0140 00D0 beq .LCB1687 + 1742 0142 87E0 b .L138 @long jump + 1743 .LCB1687: + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1744 .loc 1 680 0 + 1745 0144 E368 ldr r3, [r4, #12] + ARM GAS /tmp/ccApM0GN.s page 78 + + + 1746 0146 002B cmp r3, #0 + 1747 0148 32D1 bne .L125 + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1748 .loc 1 682 0 + 1749 014a 2368 ldr r3, [r4] + 1750 014c DA68 ldr r2, [r3, #12] + 1751 014e A36B ldr r3, [r4, #56] + 1752 0150 591C adds r1, r3, #1 + 1753 0152 A163 str r1, [r4, #56] + 1754 0154 1A70 strb r2, [r3] + 1755 .L126: + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1756 .loc 1 690 0 + 1757 0156 E38F ldrh r3, [r4, #62] + 1758 0158 013B subs r3, r3, #1 + 1759 015a 9BB2 uxth r3, r3 + 1760 015c E387 strh r3, [r4, #62] + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1761 .loc 1 693 0 + 1762 015e 8023 movs r3, #128 + 1763 0160 9B01 lsls r3, r3, #6 + 1764 0162 A26A ldr r2, [r4, #40] + 1765 0164 9A42 cmp r2, r3 + 1766 0166 2BD0 beq .L145 + 1767 .L127: + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1768 .loc 1 707 0 + 1769 0168 8223 movs r3, #130 + 1770 016a 5B00 lsls r3, r3, #1 + 1771 016c 6268 ldr r2, [r4, #4] + 1772 016e 9A42 cmp r2, r3 + 1773 0170 3CD0 beq .L146 + 1774 .L129: + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1775 .loc 1 713 0 + 1776 0172 5123 movs r3, #81 + 1777 0174 0122 movs r2, #1 + 1778 0176 E254 strb r2, [r4, r3] + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1779 .loc 1 716 0 + 1780 0178 8023 movs r3, #128 + 1781 017a 9B01 lsls r3, r3, #6 + 1782 017c A26A ldr r2, [r4, #40] + 1783 017e 9A42 cmp r2, r3 + 1784 0180 43D0 beq .L147 + 1785 .L131: + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1786 .loc 1 730 0 + 1787 0182 5023 movs r3, #80 + 1788 0184 0022 movs r2, #0 + 1789 0186 E254 strb r2, [r4, r3] + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1790 .loc 1 732 0 + 1791 0188 57E0 b .L115 + 1792 .L144: + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1793 .loc 1 648 0 + ARM GAS /tmp/ccApM0GN.s page 79 + + + 1794 018a 2268 ldr r2, [r4] + 1795 018c 1168 ldr r1, [r2] + 1796 018e 8023 movs r3, #128 + 1797 0190 5B01 lsls r3, r3, #5 + 1798 0192 0B43 orrs r3, r1 + 1799 0194 1360 str r3, [r2] + 1800 0196 CCE7 b .L123 + 1801 .L142: + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1802 .loc 1 667 0 + 1803 0198 8023 movs r3, #128 + 1804 019a 9B01 lsls r3, r3, #6 + 1805 019c A26A ldr r2, [r4, #40] + 1806 019e 9A42 cmp r2, r3 + 1807 01a0 C7D1 bne .L123 + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1808 .loc 1 669 0 + 1809 01a2 2268 ldr r2, [r4] + 1810 01a4 1168 ldr r1, [r2] + 1811 01a6 8023 movs r3, #128 + 1812 01a8 5B01 lsls r3, r3, #5 + 1813 01aa 0B43 orrs r3, r1 + 1814 01ac 1360 str r3, [r2] + 1815 01ae C0E7 b .L123 + 1816 .L125: + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 1817 .loc 1 687 0 + 1818 01b0 2368 ldr r3, [r4] + 1819 01b2 DB68 ldr r3, [r3, #12] + 1820 01b4 A26B ldr r2, [r4, #56] + 1821 01b6 1380 strh r3, [r2] + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1822 .loc 1 688 0 + 1823 01b8 A36B ldr r3, [r4, #56] + 1824 01ba 0233 adds r3, r3, #2 + 1825 01bc A363 str r3, [r4, #56] + 1826 01be CAE7 b .L126 + 1827 .L145: + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1828 .loc 1 696 0 + 1829 01c0 2B00 movs r3, r5 + 1830 01c2 0022 movs r2, #0 + 1831 01c4 0121 movs r1, #1 + 1832 01c6 2000 movs r0, r4 + 1833 01c8 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 1834 .LVL84: + 1835 01cc 0028 cmp r0, #0 + 1836 01ce 07D1 bne .L148 + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + 1837 .loc 1 703 0 + 1838 01d0 2368 ldr r3, [r4] + 1839 01d2 DB68 ldr r3, [r3, #12] + 1840 01d4 9BB2 uxth r3, r3 + 1841 01d6 0E22 movs r2, #14 + 1842 01d8 6A44 add r2, r2, sp + 1843 01da 1380 strh r3, [r2] + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 80 + + + 1844 .loc 1 704 0 + 1845 01dc 1388 ldrh r3, [r2] + 1846 01de C3E7 b .L127 + 1847 .L148: + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_TIMEOUT; + 1848 .loc 1 698 0 + 1849 01e0 636D ldr r3, [r4, #84] + 1850 01e2 0222 movs r2, #2 + 1851 01e4 1343 orrs r3, r2 + 1852 01e6 6365 str r3, [r4, #84] + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1853 .loc 1 699 0 + 1854 01e8 0326 movs r6, #3 + 1855 01ea 26E0 b .L115 + 1856 .L146: + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1857 .loc 1 707 0 discriminator 1 + 1858 01ec A368 ldr r3, [r4, #8] + 1859 01ee 8022 movs r2, #128 + 1860 01f0 1202 lsls r2, r2, #8 + 1861 01f2 9342 cmp r3, r2 + 1862 01f4 03D0 beq .L130 + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1863 .loc 1 707 0 is_stmt 0 discriminator 2 + 1864 01f6 8022 movs r2, #128 + 1865 01f8 D200 lsls r2, r2, #3 + 1866 01fa 9342 cmp r3, r2 + 1867 01fc B9D1 bne .L129 + 1868 .L130: + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1869 .loc 1 710 0 is_stmt 1 + 1870 01fe 2268 ldr r2, [r4] + 1871 0200 1368 ldr r3, [r2] + 1872 0202 4021 movs r1, #64 + 1873 0204 8B43 bics r3, r1 + 1874 0206 1360 str r3, [r2] + 1875 0208 B3E7 b .L129 + 1876 .L147: + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1877 .loc 1 716 0 discriminator 1 + 1878 020a 2368 ldr r3, [r4] + 1879 020c 9A68 ldr r2, [r3, #8] + 1880 020e D206 lsls r2, r2, #27 + 1881 0210 B7D5 bpl .L131 + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1882 .loc 1 718 0 + 1883 0212 626D ldr r2, [r4, #84] + 1884 0214 0221 movs r1, #2 + 1885 0216 0A43 orrs r2, r1 + 1886 0218 6265 str r2, [r4, #84] + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1887 .loc 1 721 0 + 1888 021a 1A68 ldr r2, [r3] + 1889 021c 0F49 ldr r1, .L149+4 + 1890 021e 0A40 ands r2, r1 + 1891 0220 1A60 str r2, [r3] + 1892 0222 2268 ldr r2, [r4] + ARM GAS /tmp/ccApM0GN.s page 81 + + + 1893 0224 1168 ldr r1, [r2] + 1894 0226 8023 movs r3, #128 + 1895 0228 9B01 lsls r3, r3, #6 + 1896 022a 0B43 orrs r3, r1 + 1897 022c 1360 str r3, [r2] + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1898 .loc 1 724 0 + 1899 022e 5023 movs r3, #80 + 1900 0230 0022 movs r2, #0 + 1901 0232 E254 strb r2, [r4, r3] + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1902 .loc 1 726 0 + 1903 0234 0126 movs r6, #1 + 1904 0236 00E0 b .L115 + 1905 .LVL85: + 1906 .L132: + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1907 .loc 1 736 0 + 1908 0238 0226 movs r6, #2 + 1909 .LVL86: + 1910 .L115: + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1911 .loc 1 738 0 + 1912 023a 3000 movs r0, r6 + 1913 023c 04B0 add sp, sp, #16 + 1914 @ sp needed + 1915 .LVL87: + 1916 .LVL88: + 1917 023e 70BD pop {r4, r5, r6, pc} + 1918 .LVL89: + 1919 .L133: + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1920 .loc 1 582 0 + 1921 0240 0126 movs r6, #1 + 1922 0242 FAE7 b .L115 + 1923 .L134: + 1924 0244 0126 movs r6, #1 + 1925 0246 F8E7 b .L115 + 1926 .L135: + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1927 .loc 1 586 0 + 1928 0248 0226 movs r6, #2 + 1929 024a F6E7 b .L115 + 1930 .LVL90: + 1931 .L136: + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1932 .loc 1 639 0 + 1933 024c 0326 movs r6, #3 + 1934 024e F4E7 b .L115 + 1935 .L137: + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1936 .loc 1 659 0 + 1937 0250 0326 movs r6, #3 + 1938 0252 F2E7 b .L115 + 1939 .L138: + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 1940 .loc 1 676 0 + ARM GAS /tmp/ccApM0GN.s page 82 + + + 1941 0254 0326 movs r6, #3 + 1942 0256 F0E7 b .L115 + 1943 .L150: + 1944 .align 2 + 1945 .L149: + 1946 0258 FFBFFFFF .word -16385 + 1947 025c FFDFFFFF .word -8193 + 1948 .cfi_endproc + 1949 .LFE44: + 1951 .section .text.HAL_SPI_Transmit_IT,"ax",%progbits + 1952 .align 1 + 1953 .global HAL_SPI_Transmit_IT + 1954 .syntax unified + 1955 .code 16 + 1956 .thumb_func + 1957 .fpu softvfp + 1959 HAL_SPI_Transmit_IT: + 1960 .LFB46: + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 1961 .loc 1 996 0 + 1962 .cfi_startproc + 1963 @ args = 0, pretend = 0, frame = 0 + 1964 @ frame_needed = 0, uses_anonymous_args = 0 + 1965 .LVL91: + 1966 0000 10B5 push {r4, lr} + 1967 .LCFI10: + 1968 .cfi_def_cfa_offset 8 + 1969 .cfi_offset 4, -8 + 1970 .cfi_offset 14, -4 + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1971 .loc 1 997 0 + 1972 0002 5123 movs r3, #81 + 1973 0004 C35C ldrb r3, [r0, r3] + 1974 0006 012B cmp r3, #1 + 1975 0008 50D1 bne .L157 + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1976 .loc 1 999 0 + 1977 000a 0029 cmp r1, #0 + 1978 000c 50D0 beq .L158 + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 1979 .loc 1 999 0 is_stmt 0 discriminator 1 + 1980 000e 002A cmp r2, #0 + 1981 0010 50D0 beq .L159 +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1982 .loc 1 1008 0 is_stmt 1 + 1983 0012 4F33 adds r3, r3, #79 + 1984 0014 C35C ldrb r3, [r0, r3] + 1985 0016 012B cmp r3, #1 + 1986 0018 4ED0 beq .L160 +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1987 .loc 1 1008 0 is_stmt 0 discriminator 2 + 1988 001a 5023 movs r3, #80 + 1989 001c 0124 movs r4, #1 + 1990 001e C454 strb r4, [r0, r3] +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1991 .loc 1 1011 0 is_stmt 1 discriminator 2 + 1992 0020 0133 adds r3, r3, #1 + ARM GAS /tmp/ccApM0GN.s page 83 + + + 1993 0022 1134 adds r4, r4, #17 + 1994 0024 C454 strb r4, [r0, r3] +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 1995 .loc 1 1012 0 discriminator 2 + 1996 0026 0023 movs r3, #0 + 1997 0028 4365 str r3, [r0, #84] +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pData; + 1998 .loc 1 1014 0 discriminator 2 + 1999 002a 254C ldr r4, .L164 + 2000 002c C464 str r4, [r0, #76] +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 2001 .loc 1 1015 0 discriminator 2 + 2002 002e 0163 str r1, [r0, #48] +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 2003 .loc 1 1016 0 discriminator 2 + 2004 0030 8286 strh r2, [r0, #52] +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2005 .loc 1 1017 0 discriminator 2 + 2006 0032 C286 strh r2, [r0, #54] +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = NULL; + 2007 .loc 1 1020 0 discriminator 2 + 2008 0034 8364 str r3, [r0, #72] +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2009 .loc 1 1021 0 discriminator 2 + 2010 0036 8363 str r3, [r0, #56] +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2011 .loc 1 1022 0 discriminator 2 + 2012 0038 8387 strh r3, [r0, #60] +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2013 .loc 1 1023 0 discriminator 2 + 2014 003a C387 strh r3, [r0, #62] +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2015 .loc 1 1026 0 discriminator 2 + 2016 003c 8023 movs r3, #128 + 2017 003e 1B02 lsls r3, r3, #8 + 2018 0040 8268 ldr r2, [r0, #8] + 2019 .LVL92: + 2020 0042 9A42 cmp r2, r3 + 2021 0044 19D0 beq .L162 + 2022 .LVL93: + 2023 .L153: +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2024 .loc 1 1032 0 + 2025 0046 8023 movs r3, #128 + 2026 0048 9B01 lsls r3, r3, #6 + 2027 004a 826A ldr r2, [r0, #40] + 2028 004c 9A42 cmp r2, r3 + 2029 004e 1BD0 beq .L163 + 2030 .L154: +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2031 .loc 1 1037 0 + 2032 0050 8368 ldr r3, [r0, #8] + 2033 0052 002B cmp r3, #0 + 2034 0054 24D1 bne .L155 +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2035 .loc 1 1039 0 + 2036 0056 0268 ldr r2, [r0] + ARM GAS /tmp/ccApM0GN.s page 84 + + + 2037 0058 5368 ldr r3, [r2, #4] + 2038 005a 8021 movs r1, #128 + 2039 005c 0B43 orrs r3, r1 + 2040 005e 5360 str r3, [r2, #4] + 2041 .L156: +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2042 .loc 1 1047 0 + 2043 0060 5023 movs r3, #80 + 2044 0062 0022 movs r2, #0 + 2045 0064 C254 strb r2, [r0, r3] +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2046 .loc 1 1050 0 + 2047 0066 0368 ldr r3, [r0] + 2048 0068 1A68 ldr r2, [r3] + 2049 006a 5206 lsls r2, r2, #25 + 2050 006c 26D4 bmi .L161 +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2051 .loc 1 1053 0 + 2052 006e 1A68 ldr r2, [r3] + 2053 0070 4021 movs r1, #64 + 2054 0072 0A43 orrs r2, r1 + 2055 0074 1A60 str r2, [r3] +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2056 .loc 1 1056 0 + 2057 0076 0020 movs r0, #0 + 2058 .LVL94: + 2059 0078 19E0 b .L152 + 2060 .LVL95: + 2061 .L162: +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2062 .loc 1 1028 0 + 2063 007a 0268 ldr r2, [r0] + 2064 007c 1168 ldr r1, [r2] + 2065 .LVL96: + 2066 007e 8023 movs r3, #128 + 2067 0080 DB01 lsls r3, r3, #7 + 2068 0082 0B43 orrs r3, r1 + 2069 0084 1360 str r3, [r2] + 2070 .LVL97: + 2071 0086 DEE7 b .L153 + 2072 .L163: +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2073 .loc 1 1034 0 + 2074 0088 0268 ldr r2, [r0] + 2075 008a 1368 ldr r3, [r2] + 2076 008c 0D49 ldr r1, .L164+4 + 2077 008e 0B40 ands r3, r1 + 2078 0090 1360 str r3, [r2] + 2079 0092 0268 ldr r2, [r0] + 2080 0094 1168 ldr r1, [r2] + 2081 0096 8023 movs r3, #128 + 2082 0098 9B01 lsls r3, r3, #6 + 2083 009a 0B43 orrs r3, r1 + 2084 009c 1360 str r3, [r2] + 2085 009e D7E7 b .L154 + 2086 .L155: +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 85 + + + 2087 .loc 1 1044 0 + 2088 00a0 0268 ldr r2, [r0] + 2089 00a2 5368 ldr r3, [r2, #4] + 2090 00a4 A021 movs r1, #160 + 2091 00a6 0B43 orrs r3, r1 + 2092 00a8 5360 str r3, [r2, #4] + 2093 00aa D9E7 b .L156 + 2094 .LVL98: + 2095 .L157: +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2096 .loc 1 1060 0 + 2097 00ac 0220 movs r0, #2 + 2098 .LVL99: + 2099 .L152: +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2100 .loc 1 1062 0 + 2101 @ sp needed + 2102 00ae 10BD pop {r4, pc} + 2103 .LVL100: + 2104 .L158: +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2105 .loc 1 1001 0 + 2106 00b0 0120 movs r0, #1 + 2107 .LVL101: + 2108 00b2 FCE7 b .L152 + 2109 .LVL102: + 2110 .L159: + 2111 00b4 0120 movs r0, #1 + 2112 .LVL103: + 2113 00b6 FAE7 b .L152 + 2114 .LVL104: + 2115 .L160: +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2116 .loc 1 1008 0 + 2117 00b8 0220 movs r0, #2 + 2118 .LVL105: + 2119 00ba F8E7 b .L152 + 2120 .LVL106: + 2121 .L161: +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2122 .loc 1 1056 0 + 2123 00bc 0020 movs r0, #0 + 2124 .LVL107: + 2125 00be F6E7 b .L152 + 2126 .L165: + 2127 .align 2 + 2128 .L164: + 2129 00c0 00000000 .word SPI_TxISR + 2130 00c4 FFDFFFFF .word -8193 + 2131 .cfi_endproc + 2132 .LFE46: + 2134 .section .text.HAL_SPI_TransmitReceive_IT,"ax",%progbits + 2135 .align 1 + 2136 .global HAL_SPI_TransmitReceive_IT + 2137 .syntax unified + 2138 .code 16 + 2139 .thumb_func + ARM GAS /tmp/ccApM0GN.s page 86 + + + 2140 .fpu softvfp + 2142 HAL_SPI_TransmitReceive_IT: + 2143 .LFB48: +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2144 .loc 1 1154 0 + 2145 .cfi_startproc + 2146 @ args = 0, pretend = 0, frame = 0 + 2147 @ frame_needed = 0, uses_anonymous_args = 0 + 2148 .LVL108: + 2149 0000 30B5 push {r4, r5, lr} + 2150 .LCFI11: + 2151 .cfi_def_cfa_offset 12 + 2152 .cfi_offset 4, -12 + 2153 .cfi_offset 5, -8 + 2154 .cfi_offset 14, -4 +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs + 2155 .loc 1 1156 0 + 2156 0002 5124 movs r4, #81 + 2157 0004 045D ldrb r4, [r0, r4] + 2158 0006 012C cmp r4, #1 + 2159 0008 0BD0 beq .L167 +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs + 2160 .loc 1 1156 0 is_stmt 0 discriminator 1 + 2161 000a 8224 movs r4, #130 + 2162 000c 6400 lsls r4, r4, #1 + 2163 000e 4568 ldr r5, [r0, #4] + 2164 0010 A542 cmp r5, r4 + 2165 0012 49D1 bne .L171 +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2166 .loc 1 1157 0 is_stmt 1 + 2167 0014 8468 ldr r4, [r0, #8] + 2168 0016 002C cmp r4, #0 + 2169 0018 48D1 bne .L172 +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2170 .loc 1 1157 0 is_stmt 0 discriminator 1 + 2171 001a 5134 adds r4, r4, #81 + 2172 001c 045D ldrb r4, [r0, r4] + 2173 001e 222C cmp r4, #34 + 2174 0020 46D1 bne .L173 + 2175 .L167: +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2176 .loc 1 1159 0 is_stmt 1 + 2177 0022 0029 cmp r1, #0 + 2178 0024 46D0 beq .L174 +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2179 .loc 1 1159 0 is_stmt 0 discriminator 1 + 2180 0026 002A cmp r2, #0 + 2181 0028 46D0 beq .L175 +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2182 .loc 1 1159 0 discriminator 2 + 2183 002a 002B cmp r3, #0 + 2184 002c 46D0 beq .L176 +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2185 .loc 1 1168 0 is_stmt 1 + 2186 002e 5024 movs r4, #80 + 2187 0030 045D ldrb r4, [r0, r4] + 2188 0032 012C cmp r4, #1 + ARM GAS /tmp/ccApM0GN.s page 87 + + + 2189 0034 44D0 beq .L177 +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2190 .loc 1 1168 0 is_stmt 0 discriminator 2 + 2191 0036 5024 movs r4, #80 + 2192 0038 0125 movs r5, #1 + 2193 003a 0555 strb r5, [r0, r4] +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2194 .loc 1 1171 0 is_stmt 1 discriminator 2 + 2195 003c 0134 adds r4, r4, #1 + 2196 003e 045D ldrb r4, [r0, r4] + 2197 0040 222C cmp r4, #34 + 2198 0042 02D0 beq .L169 +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2199 .loc 1 1173 0 + 2200 0044 5124 movs r4, #81 + 2201 0046 3135 adds r5, r5, #49 + 2202 0048 0555 strb r5, [r0, r4] + 2203 .L169: +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2204 .loc 1 1177 0 + 2205 004a 0024 movs r4, #0 + 2206 004c 4465 str r4, [r0, #84] +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = pTxData; + 2207 .loc 1 1179 0 + 2208 004e 1E4C ldr r4, .L180 + 2209 0050 C464 str r4, [r0, #76] +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 2210 .loc 1 1180 0 + 2211 0052 0163 str r1, [r0, #48] +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 2212 .loc 1 1181 0 + 2213 0054 8386 strh r3, [r0, #52] +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2214 .loc 1 1182 0 + 2215 0056 C386 strh r3, [r0, #54] +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pRxData; + 2216 .loc 1 1184 0 + 2217 0058 1C49 ldr r1, .L180+4 + 2218 .LVL109: + 2219 005a 8164 str r1, [r0, #72] +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 2220 .loc 1 1185 0 + 2221 005c 8263 str r2, [r0, #56] +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 2222 .loc 1 1186 0 + 2223 005e 8387 strh r3, [r0, #60] +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2224 .loc 1 1187 0 + 2225 0060 C387 strh r3, [r0, #62] +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2226 .loc 1 1190 0 + 2227 0062 8023 movs r3, #128 + 2228 .LVL110: + 2229 0064 9B01 lsls r3, r3, #6 + 2230 0066 826A ldr r2, [r0, #40] + 2231 .LVL111: + 2232 0068 9A42 cmp r2, r3 + ARM GAS /tmp/ccApM0GN.s page 88 + + + 2233 006a 11D0 beq .L179 + 2234 .LVL112: + 2235 .L170: +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2236 .loc 1 1196 0 + 2237 006c 0268 ldr r2, [r0] + 2238 006e 5368 ldr r3, [r2, #4] + 2239 0070 E021 movs r1, #224 + 2240 0072 0B43 orrs r3, r1 + 2241 0074 5360 str r3, [r2, #4] +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2242 .loc 1 1199 0 + 2243 0076 5023 movs r3, #80 + 2244 0078 0022 movs r2, #0 + 2245 007a C254 strb r2, [r0, r3] +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2246 .loc 1 1202 0 + 2247 007c 0368 ldr r3, [r0] + 2248 007e 1A68 ldr r2, [r3] + 2249 0080 5206 lsls r2, r2, #25 + 2250 0082 1FD4 bmi .L178 +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2251 .loc 1 1205 0 + 2252 0084 1A68 ldr r2, [r3] + 2253 0086 A039 subs r1, r1, #160 + 2254 0088 0A43 orrs r2, r1 + 2255 008a 1A60 str r2, [r3] +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2256 .loc 1 1208 0 + 2257 008c 0020 movs r0, #0 + 2258 .LVL113: + 2259 008e 0CE0 b .L168 + 2260 .LVL114: + 2261 .L179: +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2262 .loc 1 1192 0 + 2263 0090 0268 ldr r2, [r0] + 2264 0092 1368 ldr r3, [r2] + 2265 0094 0E49 ldr r1, .L180+8 + 2266 0096 0B40 ands r3, r1 + 2267 0098 1360 str r3, [r2] + 2268 .LVL115: + 2269 009a 0268 ldr r2, [r0] + 2270 009c 1168 ldr r1, [r2] + 2271 009e 8023 movs r3, #128 + 2272 00a0 9B01 lsls r3, r3, #6 + 2273 00a2 0B43 orrs r3, r1 + 2274 00a4 1360 str r3, [r2] + 2275 00a6 E1E7 b .L170 + 2276 .LVL116: + 2277 .L171: +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2278 .loc 1 1212 0 + 2279 00a8 0220 movs r0, #2 + 2280 .LVL117: + 2281 .L168: +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 89 + + + 2282 .loc 1 1214 0 + 2283 @ sp needed + 2284 00aa 30BD pop {r4, r5, pc} + 2285 .LVL118: + 2286 .L172: +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2287 .loc 1 1212 0 + 2288 00ac 0220 movs r0, #2 + 2289 .LVL119: + 2290 00ae FCE7 b .L168 + 2291 .LVL120: + 2292 .L173: + 2293 00b0 0220 movs r0, #2 + 2294 .LVL121: + 2295 00b2 FAE7 b .L168 + 2296 .LVL122: + 2297 .L174: +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2298 .loc 1 1161 0 + 2299 00b4 0120 movs r0, #1 + 2300 .LVL123: + 2301 00b6 F8E7 b .L168 + 2302 .LVL124: + 2303 .L175: + 2304 00b8 0120 movs r0, #1 + 2305 .LVL125: + 2306 00ba F6E7 b .L168 + 2307 .LVL126: + 2308 .L176: + 2309 00bc 0120 movs r0, #1 + 2310 .LVL127: + 2311 00be F4E7 b .L168 + 2312 .LVL128: + 2313 .L177: +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2314 .loc 1 1168 0 + 2315 00c0 0220 movs r0, #2 + 2316 .LVL129: + 2317 00c2 F2E7 b .L168 + 2318 .LVL130: + 2319 .L178: +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2320 .loc 1 1208 0 + 2321 00c4 0020 movs r0, #0 + 2322 .LVL131: + 2323 00c6 F0E7 b .L168 + 2324 .L181: + 2325 .align 2 + 2326 .L180: + 2327 00c8 00000000 .word SPI_TxISR + 2328 00cc 00000000 .word SPI_2LinesRxISR + 2329 00d0 FFDFFFFF .word -8193 + 2330 .cfi_endproc + 2331 .LFE48: + 2333 .section .text.HAL_SPI_Receive_IT,"ax",%progbits + 2334 .align 1 + 2335 .global HAL_SPI_Receive_IT + ARM GAS /tmp/ccApM0GN.s page 90 + + + 2336 .syntax unified + 2337 .code 16 + 2338 .thumb_func + 2339 .fpu softvfp + 2341 HAL_SPI_Receive_IT: + 2342 .LFB47: +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 2343 .loc 1 1073 0 + 2344 .cfi_startproc + 2345 @ args = 0, pretend = 0, frame = 0 + 2346 @ frame_needed = 0, uses_anonymous_args = 0 + 2347 .LVL132: + 2348 0000 10B5 push {r4, lr} + 2349 .LCFI12: + 2350 .cfi_def_cfa_offset 8 + 2351 .cfi_offset 4, -8 + 2352 .cfi_offset 14, -4 +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2353 .loc 1 1074 0 + 2354 0002 5124 movs r4, #81 + 2355 0004 045D ldrb r4, [r0, r4] + 2356 0006 012C cmp r4, #1 + 2357 0008 53D1 bne .L187 +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2358 .loc 1 1076 0 + 2359 000a 0029 cmp r1, #0 + 2360 000c 53D0 beq .L188 +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2361 .loc 1 1076 0 is_stmt 0 discriminator 1 + 2362 000e 002A cmp r2, #0 + 2363 0010 53D0 beq .L189 +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2364 .loc 1 1082 0 is_stmt 1 + 2365 0012 5023 movs r3, #80 + 2366 0014 C35C ldrb r3, [r0, r3] + 2367 0016 012B cmp r3, #1 + 2368 0018 51D0 beq .L190 +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2369 .loc 1 1082 0 is_stmt 0 discriminator 2 + 2370 001a 5023 movs r3, #80 + 2371 001c C454 strb r4, [r0, r3] +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2372 .loc 1 1085 0 is_stmt 1 discriminator 2 + 2373 001e 0133 adds r3, r3, #1 + 2374 0020 2134 adds r4, r4, #33 + 2375 0022 C454 strb r4, [r0, r3] +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2376 .loc 1 1086 0 discriminator 2 + 2377 0024 0023 movs r3, #0 + 2378 0026 4365 str r3, [r0, #84] +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr = pData; + 2379 .loc 1 1088 0 discriminator 2 + 2380 0028 274C ldr r4, .L194 + 2381 002a 8464 str r4, [r0, #72] +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 2382 .loc 1 1089 0 discriminator 2 + 2383 002c 8163 str r1, [r0, #56] + ARM GAS /tmp/ccApM0GN.s page 91 + + +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size ; + 2384 .loc 1 1090 0 discriminator 2 + 2385 002e 8287 strh r2, [r0, #60] +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2386 .loc 1 1091 0 discriminator 2 + 2387 0030 C287 strh r2, [r0, #62] +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr = NULL; + 2388 .loc 1 1094 0 discriminator 2 + 2389 0032 C364 str r3, [r0, #76] +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; + 2390 .loc 1 1095 0 discriminator 2 + 2391 0034 0363 str r3, [r0, #48] +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; + 2392 .loc 1 1096 0 discriminator 2 + 2393 0036 8386 strh r3, [r0, #52] +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2394 .loc 1 1097 0 discriminator 2 + 2395 0038 C386 strh r3, [r0, #54] +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2396 .loc 1 1100 0 discriminator 2 + 2397 003a 8368 ldr r3, [r0, #8] + 2398 003c 8024 movs r4, #128 + 2399 003e 2402 lsls r4, r4, #8 + 2400 0040 A342 cmp r3, r4 + 2401 0042 0ED0 beq .L192 +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2402 .loc 1 1104 0 + 2403 0044 002B cmp r3, #0 + 2404 0046 11D1 bne .L185 +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2405 .loc 1 1104 0 is_stmt 0 discriminator 1 + 2406 0048 0533 adds r3, r3, #5 + 2407 004a FF33 adds r3, r3, #255 + 2408 004c 4468 ldr r4, [r0, #4] + 2409 004e 9C42 cmp r4, r3 + 2410 0050 0CD1 bne .L185 +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2411 .loc 1 1107 0 is_stmt 1 + 2412 0052 B43B subs r3, r3, #180 + 2413 0054 0024 movs r4, #0 + 2414 0056 C454 strb r4, [r0, r3] +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2415 .loc 1 1110 0 + 2416 0058 1300 movs r3, r2 + 2417 005a 0A00 movs r2, r1 + 2418 .LVL133: + 2419 005c FFF7FEFF bl HAL_SPI_TransmitReceive_IT + 2420 .LVL134: + 2421 0060 28E0 b .L183 + 2422 .LVL135: + 2423 .L192: +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2424 .loc 1 1102 0 + 2425 0062 0268 ldr r2, [r0] + 2426 .LVL136: + 2427 0064 1368 ldr r3, [r2] + 2428 0066 1949 ldr r1, .L194+4 + ARM GAS /tmp/ccApM0GN.s page 92 + + + 2429 .LVL137: + 2430 0068 0B40 ands r3, r1 + 2431 006a 1360 str r3, [r2] + 2432 .LVL138: + 2433 .L185: +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2434 .loc 1 1114 0 + 2435 006c 8023 movs r3, #128 + 2436 006e 9B01 lsls r3, r3, #6 + 2437 0070 826A ldr r2, [r0, #40] + 2438 0072 9A42 cmp r2, r3 + 2439 0074 11D0 beq .L193 + 2440 .L186: +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2441 .loc 1 1120 0 + 2442 0076 0268 ldr r2, [r0] + 2443 0078 5368 ldr r3, [r2, #4] + 2444 007a 6021 movs r1, #96 + 2445 007c 0B43 orrs r3, r1 + 2446 007e 5360 str r3, [r2, #4] +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2447 .loc 1 1123 0 + 2448 0080 5023 movs r3, #80 + 2449 0082 0022 movs r2, #0 + 2450 0084 C254 strb r2, [r0, r3] +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2451 .loc 1 1130 0 + 2452 0086 0368 ldr r3, [r0] + 2453 0088 1A68 ldr r2, [r3] + 2454 008a 5206 lsls r2, r2, #25 + 2455 008c 19D4 bmi .L191 +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2456 .loc 1 1133 0 + 2457 008e 1A68 ldr r2, [r3] + 2458 0090 2039 subs r1, r1, #32 + 2459 0092 0A43 orrs r2, r1 + 2460 0094 1A60 str r2, [r3] +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2461 .loc 1 1136 0 + 2462 0096 0020 movs r0, #0 + 2463 .LVL139: + 2464 0098 0CE0 b .L183 + 2465 .LVL140: + 2466 .L193: +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2467 .loc 1 1116 0 + 2468 009a 0268 ldr r2, [r0] + 2469 009c 1368 ldr r3, [r2] + 2470 009e 0C49 ldr r1, .L194+8 + 2471 00a0 0B40 ands r3, r1 + 2472 00a2 1360 str r3, [r2] + 2473 00a4 0268 ldr r2, [r0] + 2474 00a6 1168 ldr r1, [r2] + 2475 00a8 8023 movs r3, #128 + 2476 00aa 9B01 lsls r3, r3, #6 + 2477 00ac 0B43 orrs r3, r1 + 2478 00ae 1360 str r3, [r2] + ARM GAS /tmp/ccApM0GN.s page 93 + + + 2479 00b0 E1E7 b .L186 + 2480 .LVL141: + 2481 .L187: +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2482 .loc 1 1140 0 + 2483 00b2 0220 movs r0, #2 + 2484 .LVL142: + 2485 .L183: +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2486 .loc 1 1142 0 + 2487 @ sp needed + 2488 00b4 10BD pop {r4, pc} + 2489 .LVL143: + 2490 .L188: +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2491 .loc 1 1078 0 + 2492 00b6 0120 movs r0, #1 + 2493 .LVL144: + 2494 00b8 FCE7 b .L183 + 2495 .LVL145: + 2496 .L189: + 2497 00ba 0120 movs r0, #1 + 2498 .LVL146: + 2499 00bc FAE7 b .L183 + 2500 .LVL147: + 2501 .L190: +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2502 .loc 1 1082 0 + 2503 00be 0220 movs r0, #2 + 2504 .LVL148: + 2505 00c0 F8E7 b .L183 + 2506 .LVL149: + 2507 .L191: +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2508 .loc 1 1136 0 + 2509 00c2 0020 movs r0, #0 + 2510 .LVL150: + 2511 00c4 F6E7 b .L183 + 2512 .L195: + 2513 00c6 C046 .align 2 + 2514 .L194: + 2515 00c8 00000000 .word SPI_RxISR + 2516 00cc FFBFFFFF .word -16385 + 2517 00d0 FFDFFFFF .word -8193 + 2518 .cfi_endproc + 2519 .LFE47: + 2521 .section .text.HAL_SPI_Transmit_DMA,"ax",%progbits + 2522 .align 1 + 2523 .global HAL_SPI_Transmit_DMA + 2524 .syntax unified + 2525 .code 16 + 2526 .thumb_func + 2527 .fpu softvfp + 2529 HAL_SPI_Transmit_DMA: + 2530 .LFB49: +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 2531 .loc 1 1225 0 + ARM GAS /tmp/ccApM0GN.s page 94 + + + 2532 .cfi_startproc + 2533 @ args = 0, pretend = 0, frame = 0 + 2534 @ frame_needed = 0, uses_anonymous_args = 0 + 2535 .LVL151: + 2536 0000 70B5 push {r4, r5, r6, lr} + 2537 .LCFI13: + 2538 .cfi_def_cfa_offset 16 + 2539 .cfi_offset 4, -16 + 2540 .cfi_offset 5, -12 + 2541 .cfi_offset 6, -8 + 2542 .cfi_offset 14, -4 + 2543 0002 0400 movs r4, r0 +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2544 .loc 1 1226 0 + 2545 0004 5123 movs r3, #81 + 2546 0006 C35C ldrb r3, [r0, r3] + 2547 0008 012B cmp r3, #1 + 2548 000a 62D1 bne .L197 +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2549 .loc 1 1228 0 + 2550 000c 0029 cmp r1, #0 + 2551 000e 48D0 beq .L198 +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2552 .loc 1 1228 0 is_stmt 0 discriminator 1 + 2553 0010 002A cmp r2, #0 + 2554 0012 46D0 beq .L198 +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2555 .loc 1 1239 0 is_stmt 1 + 2556 0014 5023 movs r3, #80 + 2557 0016 C35C ldrb r3, [r0, r3] + 2558 0018 012B cmp r3, #1 + 2559 001a 5FD0 beq .L203 +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2560 .loc 1 1239 0 is_stmt 0 discriminator 2 + 2561 001c 5023 movs r3, #80 + 2562 001e 0120 movs r0, #1 + 2563 .LVL152: + 2564 0020 E054 strb r0, [r4, r3] +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2565 .loc 1 1242 0 is_stmt 1 discriminator 2 + 2566 0022 0133 adds r3, r3, #1 + 2567 0024 1130 adds r0, r0, #17 + 2568 0026 E054 strb r0, [r4, r3] +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2569 .loc 1 1243 0 discriminator 2 + 2570 0028 0023 movs r3, #0 + 2571 002a 6365 str r3, [r4, #84] +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 2572 .loc 1 1245 0 discriminator 2 + 2573 002c 2163 str r1, [r4, #48] +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 2574 .loc 1 1246 0 discriminator 2 + 2575 002e A286 strh r2, [r4, #52] +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2576 .loc 1 1247 0 discriminator 2 + 2577 0030 E286 strh r2, [r4, #54] +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxISR = 0U; + ARM GAS /tmp/ccApM0GN.s page 95 + + + 2578 .loc 1 1250 0 discriminator 2 + 2579 0032 E364 str r3, [r4, #76] +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2580 .loc 1 1251 0 discriminator 2 + 2581 0034 A364 str r3, [r4, #72] +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2582 .loc 1 1253 0 discriminator 2 + 2583 0036 A363 str r3, [r4, #56] +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2584 .loc 1 1254 0 discriminator 2 + 2585 0038 A387 strh r3, [r4, #60] +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2586 .loc 1 1255 0 discriminator 2 + 2587 003a E387 strh r3, [r4, #62] +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2588 .loc 1 1258 0 discriminator 2 + 2589 003c 8023 movs r3, #128 + 2590 003e 1B02 lsls r3, r3, #8 + 2591 0040 A268 ldr r2, [r4, #8] + 2592 .LVL153: + 2593 0042 9A42 cmp r2, r3 + 2594 0044 32D0 beq .L205 + 2595 .LVL154: + 2596 .L201: +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2597 .loc 1 1264 0 + 2598 0046 8023 movs r3, #128 + 2599 0048 9B01 lsls r3, r3, #6 + 2600 004a A26A ldr r2, [r4, #40] + 2601 004c 9A42 cmp r2, r3 + 2602 004e 34D0 beq .L206 + 2603 .L202: +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2604 .loc 1 1270 0 + 2605 0050 236C ldr r3, [r4, #64] + 2606 0052 244A ldr r2, .L207 + 2607 0054 1A63 str r2, [r3, #48] +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2608 .loc 1 1273 0 + 2609 0056 236C ldr r3, [r4, #64] + 2610 0058 234A ldr r2, .L207+4 + 2611 005a DA62 str r2, [r3, #44] +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2612 .loc 1 1276 0 + 2613 005c 236C ldr r3, [r4, #64] + 2614 005e 234A ldr r2, .L207+8 + 2615 0060 5A63 str r2, [r3, #52] +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + 2616 .loc 1 1279 0 + 2617 0062 636C ldr r3, [r4, #68] + 2618 0064 0025 movs r5, #0 + 2619 0066 1D63 str r5, [r3, #48] +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; + 2620 .loc 1 1280 0 + 2621 0068 636C ldr r3, [r4, #68] + 2622 006a DD62 str r5, [r3, #44] +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 96 + + + 2623 .loc 1 1281 0 + 2624 006c 636C ldr r3, [r4, #68] + 2625 006e 5D63 str r5, [r3, #52] +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2626 .loc 1 1284 0 + 2627 0070 2268 ldr r2, [r4] + 2628 0072 0C32 adds r2, r2, #12 + 2629 0074 E38E ldrh r3, [r4, #54] + 2630 0076 9BB2 uxth r3, r3 + 2631 0078 216B ldr r1, [r4, #48] + 2632 007a 206C ldr r0, [r4, #64] + 2633 007c FFF7FEFF bl HAL_DMA_Start_IT + 2634 .LVL155: +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2635 .loc 1 1287 0 + 2636 0080 2268 ldr r2, [r4] + 2637 0082 5368 ldr r3, [r2, #4] + 2638 0084 0221 movs r1, #2 + 2639 0086 0B43 orrs r3, r1 + 2640 0088 5360 str r3, [r2, #4] +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2641 .loc 1 1290 0 + 2642 008a 5023 movs r3, #80 + 2643 008c E554 strb r5, [r4, r3] +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2644 .loc 1 1293 0 + 2645 008e 2368 ldr r3, [r4] + 2646 0090 1A68 ldr r2, [r3] + 2647 0092 5206 lsls r2, r2, #25 + 2648 0094 24D4 bmi .L204 +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2649 .loc 1 1296 0 + 2650 0096 1A68 ldr r2, [r3] + 2651 0098 3E31 adds r1, r1, #62 + 2652 009a 0A43 orrs r2, r1 + 2653 009c 1A60 str r2, [r3] +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2654 .loc 1 1299 0 + 2655 009e 0020 movs r0, #0 + 2656 00a0 1BE0 b .L200 + 2657 .LVL156: + 2658 .L198: +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 2659 .loc 1 1231 0 + 2660 00a2 5023 movs r3, #80 + 2661 00a4 0022 movs r2, #0 + 2662 .LVL157: + 2663 00a6 E254 strb r2, [r4, r3] +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2664 .loc 1 1232 0 + 2665 00a8 0120 movs r0, #1 + 2666 .LVL158: + 2667 00aa 16E0 b .L200 + 2668 .LVL159: + 2669 .L205: +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2670 .loc 1 1260 0 + ARM GAS /tmp/ccApM0GN.s page 97 + + + 2671 00ac 2268 ldr r2, [r4] + 2672 00ae 1168 ldr r1, [r2] + 2673 .LVL160: + 2674 00b0 8023 movs r3, #128 + 2675 00b2 DB01 lsls r3, r3, #7 + 2676 00b4 0B43 orrs r3, r1 + 2677 00b6 1360 str r3, [r2] + 2678 .LVL161: + 2679 00b8 C5E7 b .L201 + 2680 .L206: +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2681 .loc 1 1266 0 + 2682 00ba 2268 ldr r2, [r4] + 2683 00bc 1368 ldr r3, [r2] + 2684 00be 0C49 ldr r1, .L207+12 + 2685 00c0 0B40 ands r3, r1 + 2686 00c2 1360 str r3, [r2] + 2687 00c4 2268 ldr r2, [r4] + 2688 00c6 1168 ldr r1, [r2] + 2689 00c8 8023 movs r3, #128 + 2690 00ca 9B01 lsls r3, r3, #6 + 2691 00cc 0B43 orrs r3, r1 + 2692 00ce 1360 str r3, [r2] + 2693 00d0 BEE7 b .L202 + 2694 .LVL162: + 2695 .L197: +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + 2696 .loc 1 1304 0 + 2697 00d2 5023 movs r3, #80 + 2698 00d4 0022 movs r2, #0 + 2699 .LVL163: + 2700 00d6 C254 strb r2, [r0, r3] +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2701 .loc 1 1305 0 + 2702 00d8 0220 movs r0, #2 + 2703 .LVL164: + 2704 .L200: +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2705 .loc 1 1307 0 + 2706 @ sp needed + 2707 .LVL165: + 2708 00da 70BD pop {r4, r5, r6, pc} + 2709 .LVL166: + 2710 .L203: +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2711 .loc 1 1239 0 + 2712 00dc 0220 movs r0, #2 + 2713 .LVL167: + 2714 00de FCE7 b .L200 + 2715 .LVL168: + 2716 .L204: +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2717 .loc 1 1299 0 + 2718 00e0 0020 movs r0, #0 + 2719 00e2 FAE7 b .L200 + 2720 .L208: + 2721 .align 2 + ARM GAS /tmp/ccApM0GN.s page 98 + + + 2722 .L207: + 2723 00e4 00000000 .word SPI_DMAHalfTransmitCplt + 2724 00e8 00000000 .word SPI_DMATransmitCplt + 2725 00ec 00000000 .word SPI_DMAError + 2726 00f0 FFDFFFFF .word -8193 + 2727 .cfi_endproc + 2728 .LFE49: + 2730 .section .text.HAL_SPI_TransmitReceive_DMA,"ax",%progbits + 2731 .align 1 + 2732 .global HAL_SPI_TransmitReceive_DMA + 2733 .syntax unified + 2734 .code 16 + 2735 .thumb_func + 2736 .fpu softvfp + 2738 HAL_SPI_TransmitReceive_DMA: + 2739 .LFB51: +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hspi->State == HAL_SPI_STATE_READY) || \ + 2740 .loc 1 1419 0 + 2741 .cfi_startproc + 2742 @ args = 0, pretend = 0, frame = 0 + 2743 @ frame_needed = 0, uses_anonymous_args = 0 + 2744 .LVL169: + 2745 0000 70B5 push {r4, r5, r6, lr} + 2746 .LCFI14: + 2747 .cfi_def_cfa_offset 16 + 2748 .cfi_offset 4, -16 + 2749 .cfi_offset 5, -12 + 2750 .cfi_offset 6, -8 + 2751 .cfi_offset 14, -4 + 2752 0002 0400 movs r4, r0 +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs + 2753 .loc 1 1420 0 + 2754 0004 5120 movs r0, #81 + 2755 .LVL170: + 2756 0006 205C ldrb r0, [r4, r0] + 2757 0008 0128 cmp r0, #1 + 2758 000a 0DD0 beq .L210 +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hs + 2759 .loc 1 1420 0 is_stmt 0 discriminator 1 + 2760 000c 8220 movs r0, #130 + 2761 000e 4000 lsls r0, r0, #1 + 2762 0010 6568 ldr r5, [r4, #4] + 2763 0012 8542 cmp r5, r0 + 2764 0014 7DD1 bne .L217 +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2765 .loc 1 1421 0 is_stmt 1 + 2766 0016 A068 ldr r0, [r4, #8] + 2767 0018 0028 cmp r0, #0 + 2768 001a 00D0 beq .LCB2751 + 2769 001c 7BE0 b .L218 @long jump + 2770 .LCB2751: +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2771 .loc 1 1421 0 is_stmt 0 discriminator 1 + 2772 001e 5130 adds r0, r0, #81 + 2773 0020 205C ldrb r0, [r4, r0] + 2774 0022 2228 cmp r0, #34 + 2775 0024 00D0 beq .LCB2756 + ARM GAS /tmp/ccApM0GN.s page 99 + + + 2776 0026 78E0 b .L219 @long jump + 2777 .LCB2756: + 2778 .L210: +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2779 .loc 1 1423 0 is_stmt 1 + 2780 0028 0029 cmp r1, #0 + 2781 002a 00D1 bne .LCB2759 + 2782 002c 77E0 b .L220 @long jump + 2783 .LCB2759: +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2784 .loc 1 1423 0 is_stmt 0 discriminator 1 + 2785 002e 002A cmp r2, #0 + 2786 0030 00D1 bne .LCB2761 + 2787 0032 76E0 b .L221 @long jump + 2788 .LCB2761: +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2789 .loc 1 1423 0 discriminator 2 + 2790 0034 002B cmp r3, #0 + 2791 0036 00D1 bne .LCB2763 + 2792 0038 75E0 b .L222 @long jump + 2793 .LCB2763: +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2794 .loc 1 1432 0 is_stmt 1 + 2795 003a 5020 movs r0, #80 + 2796 003c 205C ldrb r0, [r4, r0] + 2797 003e 0128 cmp r0, #1 + 2798 0040 00D1 bne .LCB2767 + 2799 0042 72E0 b .L223 @long jump + 2800 .LCB2767: +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2801 .loc 1 1432 0 is_stmt 0 discriminator 2 + 2802 0044 5020 movs r0, #80 + 2803 0046 0125 movs r5, #1 + 2804 0048 2554 strb r5, [r4, r0] +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2805 .loc 1 1435 0 is_stmt 1 discriminator 2 + 2806 004a 0130 adds r0, r0, #1 + 2807 004c 205C ldrb r0, [r4, r0] + 2808 004e 2228 cmp r0, #34 + 2809 0050 02D0 beq .L212 +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2810 .loc 1 1437 0 + 2811 0052 5120 movs r0, #81 + 2812 0054 3135 adds r5, r5, #49 + 2813 0056 2554 strb r5, [r4, r0] + 2814 .L212: +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2815 .loc 1 1441 0 + 2816 0058 0020 movs r0, #0 + 2817 005a 6065 str r0, [r4, #84] +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = Size; + 2818 .loc 1 1443 0 + 2819 005c 2163 str r1, [r4, #48] +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = Size; + 2820 .loc 1 1444 0 + 2821 005e A386 strh r3, [r4, #52] +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 100 + + + 2822 .loc 1 1445 0 + 2823 0060 E386 strh r3, [r4, #54] +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 2824 .loc 1 1447 0 + 2825 0062 A263 str r2, [r4, #56] +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 2826 .loc 1 1448 0 + 2827 0064 A387 strh r3, [r4, #60] +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2828 .loc 1 1449 0 + 2829 0066 E387 strh r3, [r4, #62] +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 2830 .loc 1 1452 0 + 2831 0068 A064 str r0, [r4, #72] +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2832 .loc 1 1453 0 + 2833 006a E064 str r0, [r4, #76] +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2834 .loc 1 1456 0 + 2835 006c 8023 movs r3, #128 + 2836 .LVL171: + 2837 006e 9B01 lsls r3, r3, #6 + 2838 0070 A26A ldr r2, [r4, #40] + 2839 .LVL172: + 2840 0072 9A42 cmp r2, r3 + 2841 0074 3AD0 beq .L224 + 2842 .LVL173: + 2843 .L213: +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2844 .loc 1 1462 0 + 2845 0076 5123 movs r3, #81 + 2846 0078 E35C ldrb r3, [r4, r3] + 2847 007a 222B cmp r3, #34 + 2848 007c 42D0 beq .L225 +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2849 .loc 1 1472 0 + 2850 007e 636C ldr r3, [r4, #68] + 2851 0080 2B4A ldr r2, .L226 + 2852 0082 1A63 str r2, [r3, #48] +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2853 .loc 1 1474 0 + 2854 0084 636C ldr r3, [r4, #68] + 2855 0086 2B4A ldr r2, .L226+4 + 2856 0088 DA62 str r2, [r3, #44] + 2857 .L215: +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2858 .loc 1 1478 0 + 2859 008a 636C ldr r3, [r4, #68] + 2860 008c 2A4D ldr r5, .L226+8 + 2861 008e 5D63 str r5, [r3, #52] +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2862 .loc 1 1481 0 + 2863 0090 2168 ldr r1, [r4] + 2864 0092 0C31 adds r1, r1, #12 + 2865 0094 E38F ldrh r3, [r4, #62] + 2866 0096 9BB2 uxth r3, r3 + 2867 0098 A26B ldr r2, [r4, #56] + ARM GAS /tmp/ccApM0GN.s page 101 + + + 2868 009a 606C ldr r0, [r4, #68] + 2869 009c FFF7FEFF bl HAL_DMA_Start_IT + 2870 .LVL174: +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2871 .loc 1 1484 0 + 2872 00a0 2268 ldr r2, [r4] + 2873 00a2 5368 ldr r3, [r2, #4] + 2874 00a4 0121 movs r1, #1 + 2875 00a6 0B43 orrs r3, r1 + 2876 00a8 5360 str r3, [r2, #4] +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + 2877 .loc 1 1488 0 + 2878 00aa 226C ldr r2, [r4, #64] + 2879 00ac 0023 movs r3, #0 + 2880 00ae 1363 str r3, [r2, #48] +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2881 .loc 1 1489 0 + 2882 00b0 226C ldr r2, [r4, #64] + 2883 00b2 D362 str r3, [r2, #44] +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2884 .loc 1 1492 0 + 2885 00b4 236C ldr r3, [r4, #64] + 2886 00b6 5D63 str r5, [r3, #52] +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2887 .loc 1 1495 0 + 2888 00b8 2268 ldr r2, [r4] + 2889 00ba 0C32 adds r2, r2, #12 + 2890 00bc E38E ldrh r3, [r4, #54] + 2891 00be 9BB2 uxth r3, r3 + 2892 00c0 216B ldr r1, [r4, #48] + 2893 00c2 206C ldr r0, [r4, #64] + 2894 00c4 FFF7FEFF bl HAL_DMA_Start_IT + 2895 .LVL175: +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 2896 .loc 1 1498 0 + 2897 00c8 2368 ldr r3, [r4] + 2898 00ca 1A68 ldr r2, [r3] + 2899 00cc 5206 lsls r2, r2, #25 + 2900 00ce 03D4 bmi .L216 +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2901 .loc 1 1501 0 + 2902 00d0 1A68 ldr r2, [r3] + 2903 00d2 4021 movs r1, #64 + 2904 00d4 0A43 orrs r2, r1 + 2905 00d6 1A60 str r2, [r3] + 2906 .L216: +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2907 .loc 1 1505 0 + 2908 00d8 2268 ldr r2, [r4] + 2909 00da 5368 ldr r3, [r2, #4] + 2910 00dc 0221 movs r1, #2 + 2911 00de 0B43 orrs r3, r1 + 2912 00e0 5360 str r3, [r2, #4] +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2913 .loc 1 1508 0 + 2914 00e2 5023 movs r3, #80 + 2915 00e4 0022 movs r2, #0 + ARM GAS /tmp/ccApM0GN.s page 102 + + + 2916 00e6 E254 strb r2, [r4, r3] +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2917 .loc 1 1510 0 + 2918 00e8 0020 movs r0, #0 + 2919 00ea 13E0 b .L211 + 2920 .LVL176: + 2921 .L224: +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2922 .loc 1 1458 0 + 2923 00ec 2268 ldr r2, [r4] + 2924 00ee 1368 ldr r3, [r2] + 2925 00f0 1249 ldr r1, .L226+12 + 2926 .LVL177: + 2927 00f2 0B40 ands r3, r1 + 2928 00f4 1360 str r3, [r2] + 2929 .LVL178: + 2930 00f6 2268 ldr r2, [r4] + 2931 00f8 1168 ldr r1, [r2] + 2932 00fa 8023 movs r3, #128 + 2933 00fc 9B01 lsls r3, r3, #6 + 2934 00fe 0B43 orrs r3, r1 + 2935 0100 1360 str r3, [r2] + 2936 0102 B8E7 b .L213 + 2937 .L225: +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2938 .loc 1 1465 0 + 2939 0104 636C ldr r3, [r4, #68] + 2940 0106 0E4A ldr r2, .L226+16 + 2941 0108 1A63 str r2, [r3, #48] +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2942 .loc 1 1467 0 + 2943 010a 636C ldr r3, [r4, #68] + 2944 010c 0D4A ldr r2, .L226+20 + 2945 010e DA62 str r2, [r3, #44] + 2946 0110 BBE7 b .L215 + 2947 .LVL179: + 2948 .L217: +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2949 .loc 1 1514 0 + 2950 0112 0220 movs r0, #2 + 2951 .LVL180: + 2952 .L211: +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2953 .loc 1 1516 0 + 2954 @ sp needed + 2955 .LVL181: + 2956 0114 70BD pop {r4, r5, r6, pc} + 2957 .LVL182: + 2958 .L218: +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2959 .loc 1 1514 0 + 2960 0116 0220 movs r0, #2 + 2961 0118 FCE7 b .L211 + 2962 .L219: + 2963 011a 0220 movs r0, #2 + 2964 011c FAE7 b .L211 + 2965 .L220: + ARM GAS /tmp/ccApM0GN.s page 103 + + +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 2966 .loc 1 1425 0 + 2967 011e 0120 movs r0, #1 + 2968 0120 F8E7 b .L211 + 2969 .L221: + 2970 0122 0120 movs r0, #1 + 2971 0124 F6E7 b .L211 + 2972 .L222: + 2973 0126 0120 movs r0, #1 + 2974 0128 F4E7 b .L211 + 2975 .L223: +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 2976 .loc 1 1432 0 + 2977 012a 0220 movs r0, #2 + 2978 012c F2E7 b .L211 + 2979 .L227: + 2980 012e C046 .align 2 + 2981 .L226: + 2982 0130 00000000 .word SPI_DMAHalfTransmitReceiveCplt + 2983 0134 00000000 .word SPI_DMATransmitReceiveCplt + 2984 0138 00000000 .word SPI_DMAError + 2985 013c FFDFFFFF .word -8193 + 2986 0140 00000000 .word SPI_DMAHalfReceiveCplt + 2987 0144 00000000 .word SPI_DMAReceiveCplt + 2988 .cfi_endproc + 2989 .LFE51: + 2991 .section .text.HAL_SPI_Receive_DMA,"ax",%progbits + 2992 .align 1 + 2993 .global HAL_SPI_Receive_DMA + 2994 .syntax unified + 2995 .code 16 + 2996 .thumb_func + 2997 .fpu softvfp + 2999 HAL_SPI_Receive_DMA: + 3000 .LFB50: +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if(hspi->State == HAL_SPI_STATE_READY) + 3001 .loc 1 1319 0 + 3002 .cfi_startproc + 3003 @ args = 0, pretend = 0, frame = 0 + 3004 @ frame_needed = 0, uses_anonymous_args = 0 + 3005 .LVL183: + 3006 0000 70B5 push {r4, r5, r6, lr} + 3007 .LCFI15: + 3008 .cfi_def_cfa_offset 16 + 3009 .cfi_offset 4, -16 + 3010 .cfi_offset 5, -12 + 3011 .cfi_offset 6, -8 + 3012 .cfi_offset 14, -4 + 3013 0002 0400 movs r4, r0 +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3014 .loc 1 1320 0 + 3015 0004 5120 movs r0, #81 + 3016 .LVL184: + 3017 0006 205C ldrb r0, [r4, r0] + 3018 0008 0128 cmp r0, #1 + 3019 000a 71D1 bne .L229 +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 104 + + + 3020 .loc 1 1322 0 + 3021 000c 0029 cmp r1, #0 + 3022 000e 2BD0 beq .L230 +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3023 .loc 1 1322 0 is_stmt 0 discriminator 1 + 3024 0010 002A cmp r2, #0 + 3025 0012 29D0 beq .L230 +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3026 .loc 1 1330 0 is_stmt 1 + 3027 0014 5023 movs r3, #80 + 3028 0016 E35C ldrb r3, [r4, r3] + 3029 0018 012B cmp r3, #1 + 3030 001a 00D1 bne .LCB3006 + 3031 001c 6DE0 b .L236 @long jump + 3032 .LCB3006: +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3033 .loc 1 1330 0 is_stmt 0 discriminator 2 + 3034 001e 5023 movs r3, #80 + 3035 0020 0120 movs r0, #1 + 3036 0022 E054 strb r0, [r4, r3] +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3037 .loc 1 1333 0 is_stmt 1 discriminator 2 + 3038 0024 0133 adds r3, r3, #1 + 3039 0026 2130 adds r0, r0, #33 + 3040 0028 E054 strb r0, [r4, r3] +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3041 .loc 1 1334 0 discriminator 2 + 3042 002a 0023 movs r3, #0 + 3043 002c 6365 str r3, [r4, #84] +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferSize = Size; + 3044 .loc 1 1336 0 discriminator 2 + 3045 002e A163 str r1, [r4, #56] +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = Size; + 3046 .loc 1 1337 0 discriminator 2 + 3047 0030 A287 strh r2, [r4, #60] +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3048 .loc 1 1338 0 discriminator 2 + 3049 0032 E287 strh r2, [r4, #62] +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxISR = 0U; + 3050 .loc 1 1341 0 discriminator 2 + 3051 0034 A364 str r3, [r4, #72] +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3052 .loc 1 1342 0 discriminator 2 + 3053 0036 E364 str r3, [r4, #76] +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferSize = 0U; + 3054 .loc 1 1344 0 discriminator 2 + 3055 0038 2363 str r3, [r4, #48] +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; + 3056 .loc 1 1345 0 discriminator 2 + 3057 003a A386 strh r3, [r4, #52] +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3058 .loc 1 1346 0 discriminator 2 + 3059 003c E386 strh r3, [r4, #54] +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3060 .loc 1 1349 0 discriminator 2 + 3061 003e A368 ldr r3, [r4, #8] + 3062 0040 8020 movs r0, #128 + ARM GAS /tmp/ccApM0GN.s page 105 + + + 3063 0042 0002 lsls r0, r0, #8 + 3064 0044 8342 cmp r3, r0 + 3065 0046 14D0 beq .L238 +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3066 .loc 1 1353 0 + 3067 0048 002B cmp r3, #0 + 3068 004a 17D1 bne .L234 +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3069 .loc 1 1353 0 is_stmt 0 discriminator 1 + 3070 004c 0533 adds r3, r3, #5 + 3071 004e FF33 adds r3, r3, #255 + 3072 0050 6068 ldr r0, [r4, #4] + 3073 0052 9842 cmp r0, r3 + 3074 0054 12D1 bne .L234 +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3075 .loc 1 1356 0 is_stmt 1 + 3076 0056 B43B subs r3, r3, #180 + 3077 0058 0020 movs r0, #0 + 3078 005a E054 strb r0, [r4, r3] +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3079 .loc 1 1359 0 + 3080 005c 1300 movs r3, r2 + 3081 005e 0A00 movs r2, r1 + 3082 .LVL185: + 3083 0060 2000 movs r0, r4 + 3084 0062 FFF7FEFF bl HAL_SPI_TransmitReceive_DMA + 3085 .LVL186: + 3086 0066 47E0 b .L232 + 3087 .LVL187: + 3088 .L230: +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_ERROR; + 3089 .loc 1 1325 0 + 3090 0068 5023 movs r3, #80 + 3091 006a 0022 movs r2, #0 + 3092 .LVL188: + 3093 006c E254 strb r2, [r4, r3] +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3094 .loc 1 1326 0 + 3095 006e 0120 movs r0, #1 + 3096 0070 42E0 b .L232 + 3097 .LVL189: + 3098 .L238: +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3099 .loc 1 1351 0 + 3100 0072 2268 ldr r2, [r4] + 3101 .LVL190: + 3102 0074 1368 ldr r3, [r2] + 3103 0076 2349 ldr r1, .L240 + 3104 .LVL191: + 3105 0078 0B40 ands r3, r1 + 3106 007a 1360 str r3, [r2] + 3107 .LVL192: + 3108 .L234: +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3109 .loc 1 1363 0 + 3110 007c 8023 movs r3, #128 + 3111 007e 9B01 lsls r3, r3, #6 + ARM GAS /tmp/ccApM0GN.s page 106 + + + 3112 0080 A26A ldr r2, [r4, #40] + 3113 0082 9A42 cmp r2, r3 + 3114 0084 28D0 beq .L239 + 3115 .L235: +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3116 .loc 1 1369 0 + 3117 0086 636C ldr r3, [r4, #68] + 3118 0088 1F4A ldr r2, .L240+4 + 3119 008a 1A63 str r2, [r3, #48] +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3120 .loc 1 1372 0 + 3121 008c 636C ldr r3, [r4, #68] + 3122 008e 1F4A ldr r2, .L240+8 + 3123 0090 DA62 str r2, [r3, #44] +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3124 .loc 1 1375 0 + 3125 0092 636C ldr r3, [r4, #68] + 3126 0094 1E4A ldr r2, .L240+12 + 3127 0096 5A63 str r2, [r3, #52] +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + 3128 .loc 1 1378 0 + 3129 0098 236C ldr r3, [r4, #64] + 3130 009a 0025 movs r5, #0 + 3131 009c 1D63 str r5, [r3, #48] +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; + 3132 .loc 1 1379 0 + 3133 009e 236C ldr r3, [r4, #64] + 3134 00a0 DD62 str r5, [r3, #44] +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3135 .loc 1 1380 0 + 3136 00a2 236C ldr r3, [r4, #64] + 3137 00a4 5D63 str r5, [r3, #52] +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3138 .loc 1 1383 0 + 3139 00a6 2168 ldr r1, [r4] + 3140 00a8 0C31 adds r1, r1, #12 + 3141 00aa E38F ldrh r3, [r4, #62] + 3142 00ac 9BB2 uxth r3, r3 + 3143 00ae A26B ldr r2, [r4, #56] + 3144 00b0 606C ldr r0, [r4, #68] + 3145 00b2 FFF7FEFF bl HAL_DMA_Start_IT + 3146 .LVL193: +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3147 .loc 1 1386 0 + 3148 00b6 2268 ldr r2, [r4] + 3149 00b8 5368 ldr r3, [r2, #4] + 3150 00ba 0121 movs r1, #1 + 3151 00bc 0B43 orrs r3, r1 + 3152 00be 5360 str r3, [r2, #4] +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3153 .loc 1 1389 0 + 3154 00c0 5023 movs r3, #80 + 3155 00c2 E554 strb r5, [r4, r3] +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3156 .loc 1 1392 0 + 3157 00c4 2368 ldr r3, [r4] + 3158 00c6 1A68 ldr r2, [r3] + ARM GAS /tmp/ccApM0GN.s page 107 + + + 3159 00c8 5206 lsls r2, r2, #25 + 3160 00ca 18D4 bmi .L237 +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3161 .loc 1 1395 0 + 3162 00cc 1A68 ldr r2, [r3] + 3163 00ce 3F31 adds r1, r1, #63 + 3164 00d0 0A43 orrs r2, r1 + 3165 00d2 1A60 str r2, [r3] +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3166 .loc 1 1398 0 + 3167 00d4 0020 movs r0, #0 + 3168 00d6 0FE0 b .L232 + 3169 .L239: +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3170 .loc 1 1365 0 + 3171 00d8 2268 ldr r2, [r4] + 3172 00da 1368 ldr r3, [r2] + 3173 00dc 0D49 ldr r1, .L240+16 + 3174 00de 0B40 ands r3, r1 + 3175 00e0 1360 str r3, [r2] + 3176 00e2 2268 ldr r2, [r4] + 3177 00e4 1168 ldr r1, [r2] + 3178 00e6 8023 movs r3, #128 + 3179 00e8 9B01 lsls r3, r3, #6 + 3180 00ea 0B43 orrs r3, r1 + 3181 00ec 1360 str r3, [r2] + 3182 00ee CAE7 b .L235 + 3183 .LVL194: + 3184 .L229: +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return HAL_BUSY; + 3185 .loc 1 1403 0 + 3186 00f0 5023 movs r3, #80 + 3187 00f2 0022 movs r2, #0 + 3188 .LVL195: + 3189 00f4 E254 strb r2, [r4, r3] +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3190 .loc 1 1404 0 + 3191 00f6 0220 movs r0, #2 + 3192 .LVL196: + 3193 .L232: +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3194 .loc 1 1406 0 + 3195 @ sp needed + 3196 .LVL197: + 3197 00f8 70BD pop {r4, r5, r6, pc} + 3198 .LVL198: + 3199 .L236: +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3200 .loc 1 1330 0 + 3201 00fa 0220 movs r0, #2 + 3202 00fc FCE7 b .L232 + 3203 .LVL199: + 3204 .L237: +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3205 .loc 1 1398 0 + 3206 00fe 0020 movs r0, #0 + 3207 0100 FAE7 b .L232 + ARM GAS /tmp/ccApM0GN.s page 108 + + + 3208 .L241: + 3209 0102 C046 .align 2 + 3210 .L240: + 3211 0104 FFBFFFFF .word -16385 + 3212 0108 00000000 .word SPI_DMAHalfReceiveCplt + 3213 010c 00000000 .word SPI_DMAReceiveCplt + 3214 0110 00000000 .word SPI_DMAError + 3215 0114 FFDFFFFF .word -8193 + 3216 .cfi_endproc + 3217 .LFE50: + 3219 .section .text.HAL_SPI_DMAPause,"ax",%progbits + 3220 .align 1 + 3221 .global HAL_SPI_DMAPause + 3222 .syntax unified + 3223 .code 16 + 3224 .thumb_func + 3225 .fpu softvfp + 3227 HAL_SPI_DMAPause: + 3228 .LFB52: +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ + 3229 .loc 1 1526 0 + 3230 .cfi_startproc + 3231 @ args = 0, pretend = 0, frame = 0 + 3232 @ frame_needed = 0, uses_anonymous_args = 0 + 3233 .LVL200: + 3234 0000 30B5 push {r4, r5, lr} + 3235 .LCFI16: + 3236 .cfi_def_cfa_offset 12 + 3237 .cfi_offset 4, -12 + 3238 .cfi_offset 5, -8 + 3239 .cfi_offset 14, -4 +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3240 .loc 1 1528 0 + 3241 0002 5023 movs r3, #80 + 3242 0004 C35C ldrb r3, [r0, r3] + 3243 0006 012B cmp r3, #1 + 3244 0008 0FD0 beq .L244 +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3245 .loc 1 1528 0 is_stmt 0 discriminator 2 + 3246 000a 5022 movs r2, #80 + 3247 000c 0124 movs r4, #1 + 3248 000e 8454 strb r4, [r0, r2] +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 3249 .loc 1 1531 0 is_stmt 1 discriminator 2 + 3250 0010 0168 ldr r1, [r0] + 3251 0012 4B68 ldr r3, [r1, #4] + 3252 0014 0225 movs r5, #2 + 3253 0016 AB43 bics r3, r5 + 3254 0018 4B60 str r3, [r1, #4] +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3255 .loc 1 1532 0 discriminator 2 + 3256 001a 0168 ldr r1, [r0] + 3257 001c 4B68 ldr r3, [r1, #4] + 3258 001e A343 bics r3, r4 + 3259 0020 4B60 str r3, [r1, #4] +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3260 .loc 1 1535 0 discriminator 2 + ARM GAS /tmp/ccApM0GN.s page 109 + + + 3261 0022 0023 movs r3, #0 + 3262 0024 8354 strb r3, [r0, r2] +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3263 .loc 1 1537 0 discriminator 2 + 3264 0026 0020 movs r0, #0 + 3265 .LVL201: + 3266 .L243: +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3267 .loc 1 1538 0 + 3268 @ sp needed + 3269 0028 30BD pop {r4, r5, pc} + 3270 .LVL202: + 3271 .L244: +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3272 .loc 1 1528 0 + 3273 002a 0220 movs r0, #2 + 3274 .LVL203: + 3275 002c FCE7 b .L243 + 3276 .cfi_endproc + 3277 .LFE52: + 3279 .section .text.HAL_SPI_DMAResume,"ax",%progbits + 3280 .align 1 + 3281 .global HAL_SPI_DMAResume + 3282 .syntax unified + 3283 .code 16 + 3284 .thumb_func + 3285 .fpu softvfp + 3287 HAL_SPI_DMAResume: + 3288 .LFB53: +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Process Locked */ + 3289 .loc 1 1547 0 + 3290 .cfi_startproc + 3291 @ args = 0, pretend = 0, frame = 0 + 3292 @ frame_needed = 0, uses_anonymous_args = 0 + 3293 .LVL204: + 3294 0000 30B5 push {r4, r5, lr} + 3295 .LCFI17: + 3296 .cfi_def_cfa_offset 12 + 3297 .cfi_offset 4, -12 + 3298 .cfi_offset 5, -8 + 3299 .cfi_offset 14, -4 +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3300 .loc 1 1549 0 + 3301 0002 5023 movs r3, #80 + 3302 0004 C35C ldrb r3, [r0, r3] + 3303 0006 012B cmp r3, #1 + 3304 0008 0FD0 beq .L247 +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3305 .loc 1 1549 0 is_stmt 0 discriminator 2 + 3306 000a 5021 movs r1, #80 + 3307 000c 0124 movs r4, #1 + 3308 000e 4454 strb r4, [r0, r1] +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 3309 .loc 1 1552 0 is_stmt 1 discriminator 2 + 3310 0010 0368 ldr r3, [r0] + 3311 0012 5A68 ldr r2, [r3, #4] + 3312 0014 0225 movs r5, #2 + ARM GAS /tmp/ccApM0GN.s page 110 + + + 3313 0016 2A43 orrs r2, r5 + 3314 0018 5A60 str r2, [r3, #4] +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3315 .loc 1 1553 0 discriminator 2 + 3316 001a 0268 ldr r2, [r0] + 3317 001c 5368 ldr r3, [r2, #4] + 3318 001e 2343 orrs r3, r4 + 3319 0020 5360 str r3, [r2, #4] +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3320 .loc 1 1556 0 discriminator 2 + 3321 0022 0023 movs r3, #0 + 3322 0024 4354 strb r3, [r0, r1] +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3323 .loc 1 1558 0 discriminator 2 + 3324 0026 0020 movs r0, #0 + 3325 .LVL205: + 3326 .L246: +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3327 .loc 1 1559 0 + 3328 @ sp needed + 3329 0028 30BD pop {r4, r5, pc} + 3330 .LVL206: + 3331 .L247: +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3332 .loc 1 1549 0 + 3333 002a 0220 movs r0, #2 + 3334 .LVL207: + 3335 002c FCE7 b .L246 + 3336 .cfi_endproc + 3337 .LFE53: + 3339 .section .text.HAL_SPI_DMAStop,"ax",%progbits + 3340 .align 1 + 3341 .global HAL_SPI_DMAStop + 3342 .syntax unified + 3343 .code 16 + 3344 .thumb_func + 3345 .fpu softvfp + 3347 HAL_SPI_DMAStop: + 3348 .LFB54: +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application + 3349 .loc 1 1568 0 + 3350 .cfi_startproc + 3351 @ args = 0, pretend = 0, frame = 0 + 3352 @ frame_needed = 0, uses_anonymous_args = 0 + 3353 .LVL208: + 3354 0000 10B5 push {r4, lr} + 3355 .LCFI18: + 3356 .cfi_def_cfa_offset 8 + 3357 .cfi_offset 4, -8 + 3358 .cfi_offset 14, -4 + 3359 0002 0400 movs r4, r0 +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3360 .loc 1 1576 0 + 3361 0004 006C ldr r0, [r0, #64] + 3362 .LVL209: + 3363 0006 0028 cmp r0, #0 + 3364 0008 01D0 beq .L249 + ARM GAS /tmp/ccApM0GN.s page 111 + + +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3365 .loc 1 1578 0 + 3366 000a FFF7FEFF bl HAL_DMA_Abort + 3367 .LVL210: + 3368 .L249: +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3369 .loc 1 1581 0 + 3370 000e 606C ldr r0, [r4, #68] + 3371 0010 0028 cmp r0, #0 + 3372 0012 01D0 beq .L250 +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3373 .loc 1 1583 0 + 3374 0014 FFF7FEFF bl HAL_DMA_Abort + 3375 .LVL211: + 3376 .L250: +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 3377 .loc 1 1587 0 + 3378 0018 2268 ldr r2, [r4] + 3379 001a 5368 ldr r3, [r2, #4] + 3380 001c 0221 movs r1, #2 + 3381 001e 8B43 bics r3, r1 + 3382 0020 5360 str r3, [r2, #4] +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3383 .loc 1 1588 0 + 3384 0022 2168 ldr r1, [r4] + 3385 0024 4B68 ldr r3, [r1, #4] + 3386 0026 0122 movs r2, #1 + 3387 0028 9343 bics r3, r2 + 3388 002a 4B60 str r3, [r1, #4] +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3389 .loc 1 1590 0 + 3390 002c 5123 movs r3, #81 + 3391 002e E254 strb r2, [r4, r3] +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3392 .loc 1 1593 0 + 3393 0030 0020 movs r0, #0 + 3394 @ sp needed + 3395 .LVL212: + 3396 0032 10BD pop {r4, pc} + 3397 .cfi_endproc + 3398 .LFE54: + 3400 .section .text.HAL_SPI_TxCpltCallback,"ax",%progbits + 3401 .align 1 + 3402 .weak HAL_SPI_TxCpltCallback + 3403 .syntax unified + 3404 .code 16 + 3405 .thumb_func + 3406 .fpu softvfp + 3408 HAL_SPI_TxCpltCallback: + 3409 .LFB56: +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3410 .loc 1 1666 0 + 3411 .cfi_startproc + 3412 @ args = 0, pretend = 0, frame = 0 + 3413 @ frame_needed = 0, uses_anonymous_args = 0 + 3414 @ link register save eliminated. + 3415 .LVL213: + ARM GAS /tmp/ccApM0GN.s page 112 + + +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3416 .loc 1 1673 0 + 3417 @ sp needed + 3418 0000 7047 bx lr + 3419 .cfi_endproc + 3420 .LFE56: + 3422 .section .text.HAL_SPI_RxCpltCallback,"ax",%progbits + 3423 .align 1 + 3424 .weak HAL_SPI_RxCpltCallback + 3425 .syntax unified + 3426 .code 16 + 3427 .thumb_func + 3428 .fpu softvfp + 3430 HAL_SPI_RxCpltCallback: + 3431 .LFB57: +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3432 .loc 1 1682 0 + 3433 .cfi_startproc + 3434 @ args = 0, pretend = 0, frame = 0 + 3435 @ frame_needed = 0, uses_anonymous_args = 0 + 3436 @ link register save eliminated. + 3437 .LVL214: +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3438 .loc 1 1689 0 + 3439 @ sp needed + 3440 0000 7047 bx lr + 3441 .cfi_endproc + 3442 .LFE57: + 3444 .section .text.HAL_SPI_TxRxCpltCallback,"ax",%progbits + 3445 .align 1 + 3446 .weak HAL_SPI_TxRxCpltCallback + 3447 .syntax unified + 3448 .code 16 + 3449 .thumb_func + 3450 .fpu softvfp + 3452 HAL_SPI_TxRxCpltCallback: + 3453 .LFB58: +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3454 .loc 1 1698 0 + 3455 .cfi_startproc + 3456 @ args = 0, pretend = 0, frame = 0 + 3457 @ frame_needed = 0, uses_anonymous_args = 0 + 3458 @ link register save eliminated. + 3459 .LVL215: +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3460 .loc 1 1705 0 + 3461 @ sp needed + 3462 0000 7047 bx lr + 3463 .cfi_endproc + 3464 .LFE58: + 3466 .section .text.HAL_SPI_TxHalfCpltCallback,"ax",%progbits + 3467 .align 1 + 3468 .weak HAL_SPI_TxHalfCpltCallback + 3469 .syntax unified + 3470 .code 16 + 3471 .thumb_func + 3472 .fpu softvfp + ARM GAS /tmp/ccApM0GN.s page 113 + + + 3474 HAL_SPI_TxHalfCpltCallback: + 3475 .LFB59: +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3476 .loc 1 1714 0 + 3477 .cfi_startproc + 3478 @ args = 0, pretend = 0, frame = 0 + 3479 @ frame_needed = 0, uses_anonymous_args = 0 + 3480 @ link register save eliminated. + 3481 .LVL216: +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3482 .loc 1 1721 0 + 3483 @ sp needed + 3484 0000 7047 bx lr + 3485 .cfi_endproc + 3486 .LFE59: + 3488 .section .text.SPI_DMAHalfTransmitCplt,"ax",%progbits + 3489 .align 1 + 3490 .syntax unified + 3491 .code 16 + 3492 .thumb_func + 3493 .fpu softvfp + 3495 SPI_DMAHalfTransmitCplt: + 3496 .LFB73: +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 3497 .loc 1 2269 0 + 3498 .cfi_startproc + 3499 @ args = 0, pretend = 0, frame = 0 + 3500 @ frame_needed = 0, uses_anonymous_args = 0 + 3501 .LVL217: + 3502 0000 10B5 push {r4, lr} + 3503 .LCFI19: + 3504 .cfi_def_cfa_offset 8 + 3505 .cfi_offset 4, -8 + 3506 .cfi_offset 14, -4 +2270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3507 .loc 1 2270 0 + 3508 0002 806A ldr r0, [r0, #40] + 3509 .LVL218: +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3510 .loc 1 2272 0 + 3511 0004 FFF7FEFF bl HAL_SPI_TxHalfCpltCallback + 3512 .LVL219: +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3513 .loc 1 2273 0 + 3514 @ sp needed + 3515 0008 10BD pop {r4, pc} + 3516 .cfi_endproc + 3517 .LFE73: + 3519 .section .text.HAL_SPI_RxHalfCpltCallback,"ax",%progbits + 3520 .align 1 + 3521 .weak HAL_SPI_RxHalfCpltCallback + 3522 .syntax unified + 3523 .code 16 + 3524 .thumb_func + 3525 .fpu softvfp + 3527 HAL_SPI_RxHalfCpltCallback: + 3528 .LFB60: + ARM GAS /tmp/ccApM0GN.s page 114 + + +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3529 .loc 1 1730 0 + 3530 .cfi_startproc + 3531 @ args = 0, pretend = 0, frame = 0 + 3532 @ frame_needed = 0, uses_anonymous_args = 0 + 3533 @ link register save eliminated. + 3534 .LVL220: +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3535 .loc 1 1737 0 + 3536 @ sp needed + 3537 0000 7047 bx lr + 3538 .cfi_endproc + 3539 .LFE60: + 3541 .section .text.SPI_DMAHalfReceiveCplt,"ax",%progbits + 3542 .align 1 + 3543 .syntax unified + 3544 .code 16 + 3545 .thumb_func + 3546 .fpu softvfp + 3548 SPI_DMAHalfReceiveCplt: + 3549 .LFB74: +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 3550 .loc 1 2282 0 + 3551 .cfi_startproc + 3552 @ args = 0, pretend = 0, frame = 0 + 3553 @ frame_needed = 0, uses_anonymous_args = 0 + 3554 .LVL221: + 3555 0000 10B5 push {r4, lr} + 3556 .LCFI20: + 3557 .cfi_def_cfa_offset 8 + 3558 .cfi_offset 4, -8 + 3559 .cfi_offset 14, -4 +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3560 .loc 1 2283 0 + 3561 0002 806A ldr r0, [r0, #40] + 3562 .LVL222: +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3563 .loc 1 2285 0 + 3564 0004 FFF7FEFF bl HAL_SPI_RxHalfCpltCallback + 3565 .LVL223: +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3566 .loc 1 2286 0 + 3567 @ sp needed + 3568 0008 10BD pop {r4, pc} + 3569 .cfi_endproc + 3570 .LFE74: + 3572 .section .text.HAL_SPI_TxRxHalfCpltCallback,"ax",%progbits + 3573 .align 1 + 3574 .weak HAL_SPI_TxRxHalfCpltCallback + 3575 .syntax unified + 3576 .code 16 + 3577 .thumb_func + 3578 .fpu softvfp + 3580 HAL_SPI_TxRxHalfCpltCallback: + 3581 .LFB61: +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3582 .loc 1 1746 0 + ARM GAS /tmp/ccApM0GN.s page 115 + + + 3583 .cfi_startproc + 3584 @ args = 0, pretend = 0, frame = 0 + 3585 @ frame_needed = 0, uses_anonymous_args = 0 + 3586 @ link register save eliminated. + 3587 .LVL224: +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3588 .loc 1 1753 0 + 3589 @ sp needed + 3590 0000 7047 bx lr + 3591 .cfi_endproc + 3592 .LFE61: + 3594 .section .text.SPI_DMAHalfTransmitReceiveCplt,"ax",%progbits + 3595 .align 1 + 3596 .syntax unified + 3597 .code 16 + 3598 .thumb_func + 3599 .fpu softvfp + 3601 SPI_DMAHalfTransmitReceiveCplt: + 3602 .LFB75: +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 3603 .loc 1 2295 0 + 3604 .cfi_startproc + 3605 @ args = 0, pretend = 0, frame = 0 + 3606 @ frame_needed = 0, uses_anonymous_args = 0 + 3607 .LVL225: + 3608 0000 10B5 push {r4, lr} + 3609 .LCFI21: + 3610 .cfi_def_cfa_offset 8 + 3611 .cfi_offset 4, -8 + 3612 .cfi_offset 14, -4 +2296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3613 .loc 1 2296 0 + 3614 0002 806A ldr r0, [r0, #40] + 3615 .LVL226: +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3616 .loc 1 2298 0 + 3617 0004 FFF7FEFF bl HAL_SPI_TxRxHalfCpltCallback + 3618 .LVL227: +2299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3619 .loc 1 2299 0 + 3620 @ sp needed + 3621 0008 10BD pop {r4, pc} + 3622 .cfi_endproc + 3623 .LFE75: + 3625 .section .text.HAL_SPI_ErrorCallback,"ax",%progbits + 3626 .align 1 + 3627 .weak HAL_SPI_ErrorCallback + 3628 .syntax unified + 3629 .code 16 + 3630 .thumb_func + 3631 .fpu softvfp + 3633 HAL_SPI_ErrorCallback: + 3634 .LFB62: +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 3635 .loc 1 1762 0 + 3636 .cfi_startproc + 3637 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccApM0GN.s page 116 + + + 3638 @ frame_needed = 0, uses_anonymous_args = 0 + 3639 @ link register save eliminated. + 3640 .LVL228: +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3641 .loc 1 1771 0 + 3642 @ sp needed + 3643 0000 7047 bx lr + 3644 .cfi_endproc + 3645 .LFE62: + 3647 .section .text.SPI_TxISR,"ax",%progbits + 3648 .align 1 + 3649 .syntax unified + 3650 .code 16 + 3651 .thumb_func + 3652 .fpu softvfp + 3654 SPI_TxISR: + 3655 .LFB66: +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ + 3656 .loc 1 1897 0 + 3657 .cfi_startproc + 3658 @ args = 0, pretend = 0, frame = 8 + 3659 @ frame_needed = 0, uses_anonymous_args = 0 + 3660 .LVL229: + 3661 0000 10B5 push {r4, lr} + 3662 .LCFI22: + 3663 .cfi_def_cfa_offset 8 + 3664 .cfi_offset 4, -8 + 3665 .cfi_offset 14, -4 + 3666 0002 82B0 sub sp, sp, #8 + 3667 .LCFI23: + 3668 .cfi_def_cfa_offset 16 + 3669 0004 0400 movs r4, r0 +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3670 .loc 1 1899 0 + 3671 0006 C368 ldr r3, [r0, #12] + 3672 0008 002B cmp r3, #0 + 3673 000a 29D1 bne .L262 +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3674 .loc 1 1901 0 + 3675 000c 036B ldr r3, [r0, #48] + 3676 000e 5A1C adds r2, r3, #1 + 3677 0010 0263 str r2, [r0, #48] + 3678 0012 0268 ldr r2, [r0] + 3679 0014 1B78 ldrb r3, [r3] + 3680 0016 D360 str r3, [r2, #12] + 3681 .L263: +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3682 .loc 1 1909 0 + 3683 0018 E38E ldrh r3, [r4, #54] + 3684 001a 013B subs r3, r3, #1 + 3685 001c 9BB2 uxth r3, r3 + 3686 001e E386 strh r3, [r4, #54] +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3687 .loc 1 1911 0 + 3688 0020 E38E ldrh r3, [r4, #54] + 3689 0022 9BB2 uxth r3, r3 + 3690 0024 002B cmp r3, #0 + ARM GAS /tmp/ccApM0GN.s page 117 + + + 3691 0026 19D1 bne .L261 +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3692 .loc 1 1913 0 + 3693 0028 8023 movs r3, #128 + 3694 002a 9B01 lsls r3, r3, #6 + 3695 002c A26A ldr r2, [r4, #40] + 3696 002e 9A42 cmp r2, r3 + 3697 0030 1ED0 beq .L271 + 3698 .L265: + 3699 .LVL230: + 3700 .LBB6: + 3701 .LBB7: +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3702 .loc 1 1838 0 + 3703 0032 0A23 movs r3, #10 + 3704 0034 0022 movs r2, #0 + 3705 0036 0221 movs r1, #2 + 3706 0038 2000 movs r0, r4 + 3707 .LVL231: + 3708 003a FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 3709 .LVL232: + 3710 003e 0028 cmp r0, #0 + 3711 0040 03D0 beq .L266 +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3712 .loc 1 1840 0 + 3713 0042 636D ldr r3, [r4, #84] + 3714 0044 2022 movs r2, #32 + 3715 0046 1343 orrs r3, r2 + 3716 0048 6365 str r3, [r4, #84] + 3717 .L266: +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3718 .loc 1 1844 0 + 3719 004a 2268 ldr r2, [r4] + 3720 004c 5368 ldr r3, [r2, #4] + 3721 004e 8021 movs r1, #128 + 3722 0050 8B43 bics r3, r1 + 3723 0052 5360 str r3, [r2, #4] +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3724 .loc 1 1847 0 + 3725 0054 2368 ldr r3, [r4] + 3726 0056 5A68 ldr r2, [r3, #4] + 3727 0058 5206 lsls r2, r2, #25 + 3728 005a 10D5 bpl .L272 + 3729 .LVL233: + 3730 .L261: + 3731 .LBE7: + 3732 .LBE6: +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3733 .loc 1 1920 0 + 3734 005c 02B0 add sp, sp, #8 + 3735 @ sp needed + 3736 .LVL234: + 3737 005e 10BD pop {r4, pc} + 3738 .LVL235: + 3739 .L262: +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pTxBuffPtr+=2U; + 3740 .loc 1 1906 0 + ARM GAS /tmp/ccApM0GN.s page 118 + + + 3741 0060 0368 ldr r3, [r0] + 3742 0062 026B ldr r2, [r0, #48] + 3743 0064 1288 ldrh r2, [r2] + 3744 0066 DA60 str r2, [r3, #12] +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3745 .loc 1 1907 0 + 3746 0068 036B ldr r3, [r0, #48] + 3747 006a 0233 adds r3, r3, #2 + 3748 006c 0363 str r3, [r0, #48] + 3749 006e D3E7 b .L263 + 3750 .L271: +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3751 .loc 1 1916 0 + 3752 0070 2268 ldr r2, [r4] + 3753 0072 1168 ldr r1, [r2] + 3754 0074 8023 movs r3, #128 + 3755 0076 5B01 lsls r3, r3, #5 + 3756 0078 0B43 orrs r3, r1 + 3757 007a 1360 str r3, [r2] + 3758 007c D9E7 b .L265 + 3759 .LVL236: + 3760 .L272: + 3761 .LBB10: + 3762 .LBB9: +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3763 .loc 1 1849 0 + 3764 007e 5A68 ldr r2, [r3, #4] + 3765 0080 6039 subs r1, r1, #96 + 3766 0082 8A43 bics r2, r1 + 3767 0084 5A60 str r2, [r3, #4] +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3768 .loc 1 1852 0 + 3769 0086 0A23 movs r3, #10 + 3770 0088 0122 movs r2, #1 + 3771 008a 6031 adds r1, r1, #96 + 3772 008c 2000 movs r0, r4 + 3773 008e FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 3774 .LVL237: + 3775 0092 0028 cmp r0, #0 + 3776 0094 03D0 beq .L267 +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3777 .loc 1 1854 0 + 3778 0096 636D ldr r3, [r4, #84] + 3779 0098 2022 movs r2, #32 + 3780 009a 1343 orrs r3, r2 + 3781 009c 6365 str r3, [r4, #84] + 3782 .L267: +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3783 .loc 1 1858 0 + 3784 009e A368 ldr r3, [r4, #8] + 3785 00a0 002B cmp r3, #0 + 3786 00a2 05D1 bne .L268 + 3787 .LBB8: +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3788 .loc 1 1860 0 + 3789 00a4 2368 ldr r3, [r4] + 3790 00a6 DA68 ldr r2, [r3, #12] + ARM GAS /tmp/ccApM0GN.s page 119 + + + 3791 00a8 0192 str r2, [sp, #4] + 3792 00aa 9B68 ldr r3, [r3, #8] + 3793 00ac 0193 str r3, [sp, #4] + 3794 00ae 019B ldr r3, [sp, #4] + 3795 .L268: + 3796 .LBE8: +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3797 .loc 1 1864 0 + 3798 00b0 636D ldr r3, [r4, #84] + 3799 00b2 002B cmp r3, #0 + 3800 00b4 11D1 bne .L269 +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3801 .loc 1 1867 0 + 3802 00b6 5133 adds r3, r3, #81 + 3803 00b8 E35C ldrb r3, [r4, r3] + 3804 00ba 322B cmp r3, #50 + 3805 00bc 06D0 beq .L273 +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); + 3806 .loc 1 1876 0 + 3807 00be 5123 movs r3, #81 + 3808 00c0 0122 movs r2, #1 + 3809 00c2 E254 strb r2, [r4, r3] +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3810 .loc 1 1877 0 + 3811 00c4 2000 movs r0, r4 + 3812 00c6 FFF7FEFF bl HAL_SPI_TxCpltCallback + 3813 .LVL238: + 3814 00ca C7E7 b .L261 + 3815 .L273: +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); + 3816 .loc 1 1870 0 + 3817 00cc 1F33 adds r3, r3, #31 + 3818 00ce 0122 movs r2, #1 + 3819 00d0 E254 strb r2, [r4, r3] +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3820 .loc 1 1871 0 + 3821 00d2 2000 movs r0, r4 + 3822 00d4 FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 3823 .LVL239: + 3824 00d8 C0E7 b .L261 + 3825 .L269: +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call Error call back in case of Error */ + 3826 .loc 1 1883 0 + 3827 00da 5123 movs r3, #81 + 3828 00dc 0122 movs r2, #1 + 3829 00de E254 strb r2, [r4, r3] +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3830 .loc 1 1885 0 + 3831 00e0 2000 movs r0, r4 + 3832 00e2 FFF7FEFF bl HAL_SPI_ErrorCallback + 3833 .LVL240: + 3834 .LBE9: + 3835 .LBE10: +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3836 .loc 1 1920 0 + 3837 00e6 B9E7 b .L261 + 3838 .cfi_endproc + ARM GAS /tmp/ccApM0GN.s page 120 + + + 3839 .LFE66: + 3841 .section .text.SPI_RxCloseIRQHandler,"ax",%progbits + 3842 .align 1 + 3843 .syntax unified + 3844 .code 16 + 3845 .thumb_func + 3846 .fpu softvfp + 3848 SPI_RxCloseIRQHandler: + 3849 .LFB67: +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 3850 .loc 1 1929 0 + 3851 .cfi_startproc + 3852 @ args = 0, pretend = 0, frame = 8 + 3853 @ frame_needed = 0, uses_anonymous_args = 0 + 3854 .LVL241: + 3855 0000 10B5 push {r4, lr} + 3856 .LCFI24: + 3857 .cfi_def_cfa_offset 8 + 3858 .cfi_offset 4, -8 + 3859 .cfi_offset 14, -4 + 3860 0002 82B0 sub sp, sp, #8 + 3861 .LCFI25: + 3862 .cfi_def_cfa_offset 16 + 3863 0004 0400 movs r4, r0 +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3864 .loc 1 1930 0 + 3865 0006 6B46 mov r3, sp + 3866 0008 0022 movs r2, #0 + 3867 000a DA80 strh r2, [r3, #6] +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3868 .loc 1 1932 0 + 3869 000c 8023 movs r3, #128 + 3870 000e 9B01 lsls r3, r3, #6 + 3871 0010 826A ldr r2, [r0, #40] + 3872 0012 9A42 cmp r2, r3 + 3873 0014 20D0 beq .L283 + 3874 .LVL242: + 3875 .L275: +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3876 .loc 1 1961 0 + 3877 0016 2268 ldr r2, [r4] + 3878 0018 5368 ldr r3, [r2, #4] + 3879 001a 4021 movs r1, #64 + 3880 001c 8B43 bics r3, r1 + 3881 001e 5360 str r3, [r2, #4] +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3882 .loc 1 1964 0 + 3883 0020 2368 ldr r3, [r4] + 3884 0022 5A68 ldr r2, [r3, #4] + 3885 0024 1206 lsls r2, r2, #24 + 3886 0026 15D4 bmi .L274 +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3887 .loc 1 1967 0 + 3888 0028 5A68 ldr r2, [r3, #4] + 3889 002a 2039 subs r1, r1, #32 + 3890 002c 8A43 bics r2, r1 + 3891 002e 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccApM0GN.s page 121 + + +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3892 .loc 1 1969 0 + 3893 0030 8223 movs r3, #130 + 3894 0032 5B00 lsls r3, r3, #1 + 3895 0034 6268 ldr r2, [r4, #4] + 3896 0036 9A42 cmp r2, r3 + 3897 0038 3ED0 beq .L284 + 3898 .L279: +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3899 .loc 1 1976 0 + 3900 003a 636D ldr r3, [r4, #84] + 3901 003c 002B cmp r3, #0 + 3902 003e 51D1 bne .L281 +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3903 .loc 1 1979 0 + 3904 0040 5133 adds r3, r3, #81 + 3905 0042 E35C ldrb r3, [r4, r3] + 3906 0044 322B cmp r3, #50 + 3907 0046 46D0 beq .L285 +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); + 3908 .loc 1 1988 0 + 3909 0048 5123 movs r3, #81 + 3910 004a 0122 movs r2, #1 + 3911 004c E254 strb r2, [r4, r3] +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3912 .loc 1 1989 0 + 3913 004e 2000 movs r0, r4 + 3914 0050 FFF7FEFF bl HAL_SPI_RxCpltCallback + 3915 .LVL243: + 3916 .L274: +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3917 .loc 1 2000 0 + 3918 0054 02B0 add sp, sp, #8 + 3919 @ sp needed + 3920 .LVL244: + 3921 0056 10BD pop {r4, pc} + 3922 .LVL245: + 3923 .L283: +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3924 .loc 1 1935 0 + 3925 0058 0A23 movs r3, #10 + 3926 005a 0022 movs r2, #0 + 3927 005c 0121 movs r1, #1 + 3928 005e FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 3929 .LVL246: + 3930 0062 0028 cmp r0, #0 + 3931 0064 03D0 beq .L276 +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3932 .loc 1 1937 0 + 3933 0066 636D ldr r3, [r4, #84] + 3934 0068 2022 movs r2, #32 + 3935 006a 1343 orrs r3, r2 + 3936 006c 6365 str r3, [r4, #84] + 3937 .L276: +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ + 3938 .loc 1 1941 0 + 3939 006e 2368 ldr r3, [r4] + ARM GAS /tmp/ccApM0GN.s page 122 + + + 3940 0070 DB68 ldr r3, [r3, #12] + 3941 0072 9BB2 uxth r3, r3 + 3942 0074 6A46 mov r2, sp + 3943 0076 D380 strh r3, [r2, #6] +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3944 .loc 1 1942 0 + 3945 0078 D388 ldrh r3, [r2, #6] +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3946 .loc 1 1945 0 + 3947 007a 0A23 movs r3, #10 + 3948 007c 0122 movs r2, #1 + 3949 007e 0121 movs r1, #1 + 3950 0080 2000 movs r0, r4 + 3951 0082 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 3952 .LVL247: + 3953 0086 0028 cmp r0, #0 + 3954 0088 03D0 beq .L277 +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3955 .loc 1 1947 0 + 3956 008a 636D ldr r3, [r4, #84] + 3957 008c 2022 movs r2, #32 + 3958 008e 1343 orrs r3, r2 + 3959 0090 6365 str r3, [r4, #84] + 3960 .L277: +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3961 .loc 1 1951 0 + 3962 0092 2368 ldr r3, [r4] + 3963 0094 9A68 ldr r2, [r3, #8] + 3964 0096 D206 lsls r2, r2, #27 + 3965 0098 BDD5 bpl .L275 +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 3966 .loc 1 1953 0 + 3967 009a 626D ldr r2, [r4, #84] + 3968 009c 0221 movs r1, #2 + 3969 009e 0A43 orrs r2, r1 + 3970 00a0 6265 str r2, [r4, #84] +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3971 .loc 1 1956 0 + 3972 00a2 1A68 ldr r2, [r3] + 3973 00a4 1349 ldr r1, .L286 + 3974 00a6 0A40 ands r2, r1 + 3975 00a8 1A60 str r2, [r3] + 3976 00aa 2268 ldr r2, [r4] + 3977 00ac 1168 ldr r1, [r2] + 3978 00ae 8023 movs r3, #128 + 3979 00b0 9B01 lsls r3, r3, #6 + 3980 00b2 0B43 orrs r3, r1 + 3981 00b4 1360 str r3, [r2] + 3982 00b6 AEE7 b .L275 + 3983 .L284: +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3984 .loc 1 1969 0 discriminator 1 + 3985 00b8 A368 ldr r3, [r4, #8] + 3986 00ba 8022 movs r2, #128 + 3987 00bc 1202 lsls r2, r2, #8 + 3988 00be 9342 cmp r3, r2 + 3989 00c0 03D0 beq .L280 + ARM GAS /tmp/ccApM0GN.s page 123 + + +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 3990 .loc 1 1969 0 is_stmt 0 discriminator 2 + 3991 00c2 8022 movs r2, #128 + 3992 00c4 D200 lsls r2, r2, #3 + 3993 00c6 9342 cmp r3, r2 + 3994 00c8 B7D1 bne .L279 + 3995 .L280: +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 3996 .loc 1 1972 0 is_stmt 1 + 3997 00ca 2268 ldr r2, [r4] + 3998 00cc 1368 ldr r3, [r2] + 3999 00ce 4021 movs r1, #64 + 4000 00d0 8B43 bics r3, r1 + 4001 00d2 1360 str r3, [r2] + 4002 00d4 B1E7 b .L279 + 4003 .L285: +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); + 4004 .loc 1 1982 0 + 4005 00d6 1F33 adds r3, r3, #31 + 4006 00d8 0122 movs r2, #1 + 4007 00da E254 strb r2, [r4, r3] +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4008 .loc 1 1983 0 + 4009 00dc 2000 movs r0, r4 + 4010 00de FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 4011 .LVL248: + 4012 00e2 B7E7 b .L274 + 4013 .L281: +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Call Error call back in case of Error */ + 4014 .loc 1 1995 0 + 4015 00e4 5123 movs r3, #81 + 4016 00e6 0122 movs r2, #1 + 4017 00e8 E254 strb r2, [r4, r3] +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4018 .loc 1 1997 0 + 4019 00ea 2000 movs r0, r4 + 4020 00ec FFF7FEFF bl HAL_SPI_ErrorCallback + 4021 .LVL249: +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4022 .loc 1 2000 0 + 4023 00f0 B0E7 b .L274 + 4024 .L287: + 4025 00f2 C046 .align 2 + 4026 .L286: + 4027 00f4 FFDFFFFF .word -8193 + 4028 .cfi_endproc + 4029 .LFE67: + 4031 .section .text.SPI_RxISR,"ax",%progbits + 4032 .align 1 + 4033 .syntax unified + 4034 .code 16 + 4035 .thumb_func + 4036 .fpu softvfp + 4038 SPI_RxISR: + 4039 .LFB69: +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 8 Bit mode */ + 4040 .loc 1 2036 0 + ARM GAS /tmp/ccApM0GN.s page 124 + + + 4041 .cfi_startproc + 4042 @ args = 0, pretend = 0, frame = 0 + 4043 @ frame_needed = 0, uses_anonymous_args = 0 + 4044 .LVL250: + 4045 0000 10B5 push {r4, lr} + 4046 .LCFI26: + 4047 .cfi_def_cfa_offset 8 + 4048 .cfi_offset 4, -8 + 4049 .cfi_offset 14, -4 +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4050 .loc 1 2038 0 + 4051 0002 C368 ldr r3, [r0, #12] + 4052 0004 002B cmp r3, #0 + 4053 0006 12D1 bne .L289 +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4054 .loc 1 2040 0 + 4055 0008 0368 ldr r3, [r0] + 4056 000a DA68 ldr r2, [r3, #12] + 4057 000c 836B ldr r3, [r0, #56] + 4058 000e 591C adds r1, r3, #1 + 4059 0010 8163 str r1, [r0, #56] + 4060 0012 1A70 strb r2, [r3] + 4061 .L290: +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4062 .loc 1 2048 0 + 4063 0014 C38F ldrh r3, [r0, #62] + 4064 0016 013B subs r3, r3, #1 + 4065 0018 9BB2 uxth r3, r3 + 4066 001a C387 strh r3, [r0, #62] +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4067 .loc 1 2051 0 + 4068 001c C38F ldrh r3, [r0, #62] + 4069 001e 9BB2 uxth r3, r3 + 4070 0020 012B cmp r3, #1 + 4071 0022 0CD0 beq .L293 + 4072 .L291: +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4073 .loc 1 2057 0 + 4074 0024 C38F ldrh r3, [r0, #62] + 4075 0026 9BB2 uxth r3, r3 + 4076 0028 002B cmp r3, #0 + 4077 002a 14D0 beq .L294 + 4078 .LVL251: + 4079 .L288: +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4080 .loc 1 2061 0 + 4081 @ sp needed + 4082 002c 10BD pop {r4, pc} + 4083 .LVL252: + 4084 .L289: +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 4085 .loc 1 2045 0 + 4086 002e 0368 ldr r3, [r0] + 4087 0030 DB68 ldr r3, [r3, #12] + 4088 0032 826B ldr r2, [r0, #56] + 4089 0034 1380 strh r3, [r2] +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 125 + + + 4090 .loc 1 2046 0 + 4091 0036 836B ldr r3, [r0, #56] + 4092 0038 0233 adds r3, r3, #2 + 4093 003a 8363 str r3, [r0, #56] + 4094 003c EAE7 b .L290 + 4095 .L293: +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4096 .loc 1 2051 0 discriminator 1 + 4097 003e 8023 movs r3, #128 + 4098 0040 9B01 lsls r3, r3, #6 + 4099 0042 826A ldr r2, [r0, #40] + 4100 0044 9A42 cmp r2, r3 + 4101 0046 EDD1 bne .L291 +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4102 .loc 1 2054 0 + 4103 0048 0268 ldr r2, [r0] + 4104 004a 1168 ldr r1, [r2] + 4105 004c 8023 movs r3, #128 + 4106 004e 5B01 lsls r3, r3, #5 + 4107 0050 0B43 orrs r3, r1 + 4108 0052 1360 str r3, [r2] + 4109 0054 E6E7 b .L291 + 4110 .L294: +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4111 .loc 1 2059 0 + 4112 0056 FFF7FEFF bl SPI_RxCloseIRQHandler + 4113 .LVL253: +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4114 .loc 1 2061 0 + 4115 005a E7E7 b .L288 + 4116 .cfi_endproc + 4117 .LFE69: + 4119 .section .text.SPI_2LinesRxISR,"ax",%progbits + 4120 .align 1 + 4121 .syntax unified + 4122 .code 16 + 4123 .thumb_func + 4124 .fpu softvfp + 4126 SPI_2LinesRxISR: + 4127 .LFB68: +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* Receive data in 8 Bit mode */ + 4128 .loc 1 2009 0 + 4129 .cfi_startproc + 4130 @ args = 0, pretend = 0, frame = 0 + 4131 @ frame_needed = 0, uses_anonymous_args = 0 + 4132 .LVL254: + 4133 0000 10B5 push {r4, lr} + 4134 .LCFI27: + 4135 .cfi_def_cfa_offset 8 + 4136 .cfi_offset 4, -8 + 4137 .cfi_offset 14, -4 +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4138 .loc 1 2011 0 + 4139 0002 C368 ldr r3, [r0, #12] + 4140 0004 002B cmp r3, #0 + 4141 0006 0ED1 bne .L296 +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 126 + + + 4142 .loc 1 2013 0 + 4143 0008 0368 ldr r3, [r0] + 4144 000a DA68 ldr r2, [r3, #12] + 4145 000c 836B ldr r3, [r0, #56] + 4146 000e 591C adds r1, r3, #1 + 4147 0010 8163 str r1, [r0, #56] + 4148 0012 1A70 strb r2, [r3] + 4149 .L297: +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4150 .loc 1 2021 0 + 4151 0014 C38F ldrh r3, [r0, #62] + 4152 0016 013B subs r3, r3, #1 + 4153 0018 9BB2 uxth r3, r3 + 4154 001a C387 strh r3, [r0, #62] +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4155 .loc 1 2023 0 + 4156 001c C38F ldrh r3, [r0, #62] + 4157 001e 9BB2 uxth r3, r3 + 4158 0020 002B cmp r3, #0 + 4159 0022 08D0 beq .L299 + 4160 .LVL255: + 4161 .L295: +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4162 .loc 1 2027 0 + 4163 @ sp needed + 4164 0024 10BD pop {r4, pc} + 4165 .LVL256: + 4166 .L296: +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->pRxBuffPtr+=2U; + 4167 .loc 1 2018 0 + 4168 0026 0368 ldr r3, [r0] + 4169 0028 DB68 ldr r3, [r3, #12] + 4170 002a 826B ldr r2, [r0, #56] + 4171 002c 1380 strh r3, [r2] +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4172 .loc 1 2019 0 + 4173 002e 836B ldr r3, [r0, #56] + 4174 0030 0233 adds r3, r3, #2 + 4175 0032 8363 str r3, [r0, #56] + 4176 0034 EEE7 b .L297 + 4177 .L299: +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4178 .loc 1 2025 0 + 4179 0036 FFF7FEFF bl SPI_RxCloseIRQHandler + 4180 .LVL257: +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4181 .loc 1 2027 0 + 4182 003a F3E7 b .L295 + 4183 .cfi_endproc + 4184 .LFE68: + 4186 .section .text.SPI_DMAError,"ax",%progbits + 4187 .align 1 + 4188 .syntax unified + 4189 .code 16 + 4190 .thumb_func + 4191 .fpu softvfp + 4193 SPI_DMAError: + ARM GAS /tmp/ccApM0GN.s page 127 + + + 4194 .LFB76: +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 4195 .loc 1 2308 0 + 4196 .cfi_startproc + 4197 @ args = 0, pretend = 0, frame = 0 + 4198 @ frame_needed = 0, uses_anonymous_args = 0 + 4199 .LVL258: + 4200 0000 10B5 push {r4, lr} + 4201 .LCFI28: + 4202 .cfi_def_cfa_offset 8 + 4203 .cfi_offset 4, -8 + 4204 .cfi_offset 14, -4 +2309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4205 .loc 1 2309 0 + 4206 0002 806A ldr r0, [r0, #40] + 4207 .LVL259: +2310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 4208 .loc 1 2310 0 + 4209 0004 0023 movs r3, #0 + 4210 0006 C386 strh r3, [r0, #54] +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State= HAL_SPI_STATE_READY; + 4211 .loc 1 2311 0 + 4212 0008 C387 strh r3, [r0, #62] +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 4213 .loc 1 2312 0 + 4214 000a 5133 adds r3, r3, #81 + 4215 000c 0122 movs r2, #1 + 4216 000e C254 strb r2, [r0, r3] +2313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 4217 .loc 1 2313 0 + 4218 0010 436D ldr r3, [r0, #84] + 4219 0012 0F32 adds r2, r2, #15 + 4220 0014 1343 orrs r3, r2 + 4221 0016 4365 str r3, [r0, #84] +2314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4222 .loc 1 2314 0 + 4223 0018 FFF7FEFF bl HAL_SPI_ErrorCallback + 4224 .LVL260: +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4225 .loc 1 2315 0 + 4226 @ sp needed + 4227 001c 10BD pop {r4, pc} + 4228 .cfi_endproc + 4229 .LFE76: + 4231 .section .text.SPI_DMATransmitCplt,"ax",%progbits + 4232 .align 1 + 4233 .syntax unified + 4234 .code 16 + 4235 .thumb_func + 4236 .fpu softvfp + 4238 SPI_DMATransmitCplt: + 4239 .LFB70: +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 4240 .loc 1 2070 0 + 4241 .cfi_startproc + 4242 @ args = 0, pretend = 0, frame = 8 + 4243 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccApM0GN.s page 128 + + + 4244 .LVL261: + 4245 0000 10B5 push {r4, lr} + 4246 .LCFI29: + 4247 .cfi_def_cfa_offset 8 + 4248 .cfi_offset 4, -8 + 4249 .cfi_offset 14, -4 + 4250 0002 82B0 sub sp, sp, #8 + 4251 .LCFI30: + 4252 .cfi_def_cfa_offset 16 +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4253 .loc 1 2071 0 + 4254 0004 846A ldr r4, [r0, #40] + 4255 .LVL262: +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4256 .loc 1 2075 0 + 4257 0006 0368 ldr r3, [r0] + 4258 0008 1B68 ldr r3, [r3] + 4259 000a 9B06 lsls r3, r3, #26 + 4260 000c 10D5 bpl .L308 + 4261 .LVL263: + 4262 .L302: +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4263 .loc 1 2097 0 + 4264 000e A368 ldr r3, [r4, #8] + 4265 0010 002B cmp r3, #0 + 4266 0012 05D1 bne .L305 + 4267 .LBB11: +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4268 .loc 1 2099 0 + 4269 0014 2368 ldr r3, [r4] + 4270 0016 DA68 ldr r2, [r3, #12] + 4271 0018 0192 str r2, [sp, #4] + 4272 001a 9B68 ldr r3, [r3, #8] + 4273 001c 0193 str r3, [sp, #4] + 4274 001e 019B ldr r3, [sp, #4] + 4275 .L305: + 4276 .LBE11: +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4277 .loc 1 2103 0 + 4278 0020 636D ldr r3, [r4, #84] + 4279 0022 002B cmp r3, #0 + 4280 0024 27D1 bne .L309 +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4281 .loc 1 2109 0 + 4282 0026 2000 movs r0, r4 + 4283 0028 FFF7FEFF bl HAL_SPI_TxCpltCallback + 4284 .LVL264: + 4285 .L301: +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4286 .loc 1 2111 0 + 4287 002c 02B0 add sp, sp, #8 + 4288 @ sp needed + 4289 .LVL265: + 4290 002e 10BD pop {r4, pc} + 4291 .LVL266: + 4292 .L308: +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 129 + + + 4293 .loc 1 2078 0 + 4294 0030 0A23 movs r3, #10 + 4295 0032 0022 movs r2, #0 + 4296 0034 0221 movs r1, #2 + 4297 0036 2000 movs r0, r4 + 4298 .LVL267: + 4299 0038 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4300 .LVL268: + 4301 003c 0028 cmp r0, #0 + 4302 003e 03D0 beq .L303 +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4303 .loc 1 2080 0 + 4304 0040 636D ldr r3, [r4, #84] + 4305 0042 2022 movs r2, #32 + 4306 0044 1343 orrs r3, r2 + 4307 0046 6365 str r3, [r4, #84] + 4308 .L303: +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4309 .loc 1 2084 0 + 4310 0048 2268 ldr r2, [r4] + 4311 004a 5368 ldr r3, [r2, #4] + 4312 004c 0221 movs r1, #2 + 4313 004e 8B43 bics r3, r1 + 4314 0050 5360 str r3, [r2, #4] +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4315 .loc 1 2087 0 + 4316 0052 0A23 movs r3, #10 + 4317 0054 0122 movs r2, #1 + 4318 0056 7E31 adds r1, r1, #126 + 4319 0058 2000 movs r0, r4 + 4320 005a FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4321 .LVL269: + 4322 005e 0028 cmp r0, #0 + 4323 0060 03D0 beq .L304 +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4324 .loc 1 2089 0 + 4325 0062 636D ldr r3, [r4, #84] + 4326 0064 2022 movs r2, #32 + 4327 0066 1343 orrs r3, r2 + 4328 0068 6365 str r3, [r4, #84] + 4329 .L304: +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4330 .loc 1 2092 0 + 4331 006a 0023 movs r3, #0 + 4332 006c E386 strh r3, [r4, #54] +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4333 .loc 1 2093 0 + 4334 006e 5133 adds r3, r3, #81 + 4335 0070 0122 movs r2, #1 + 4336 0072 E254 strb r2, [r4, r3] + 4337 0074 CBE7 b .L302 + 4338 .L309: +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4339 .loc 1 2105 0 + 4340 0076 2000 movs r0, r4 + 4341 0078 FFF7FEFF bl HAL_SPI_ErrorCallback + 4342 .LVL270: + ARM GAS /tmp/ccApM0GN.s page 130 + + + 4343 007c D6E7 b .L301 + 4344 .cfi_endproc + 4345 .LFE70: + 4347 .section .text.SPI_DMAReceiveCplt,"ax",%progbits + 4348 .align 1 + 4349 .syntax unified + 4350 .code 16 + 4351 .thumb_func + 4352 .fpu softvfp + 4354 SPI_DMAReceiveCplt: + 4355 .LFB71: +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 4356 .loc 1 2120 0 + 4357 .cfi_startproc + 4358 @ args = 0, pretend = 0, frame = 8 + 4359 @ frame_needed = 0, uses_anonymous_args = 0 + 4360 .LVL271: + 4361 0000 10B5 push {r4, lr} + 4362 .LCFI31: + 4363 .cfi_def_cfa_offset 8 + 4364 .cfi_offset 4, -8 + 4365 .cfi_offset 14, -4 + 4366 0002 82B0 sub sp, sp, #8 + 4367 .LCFI32: + 4368 .cfi_def_cfa_offset 16 +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4369 .loc 1 2121 0 + 4370 0004 6B46 mov r3, sp + 4371 0006 0022 movs r2, #0 + 4372 0008 DA80 strh r2, [r3, #6] +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4373 .loc 1 2123 0 + 4374 000a 846A ldr r4, [r0, #40] + 4375 .LVL272: +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4376 .loc 1 2126 0 + 4377 000c 0368 ldr r3, [r0] + 4378 000e 1B68 ldr r3, [r3] + 4379 0010 9B06 lsls r3, r3, #26 + 4380 0012 5DD4 bmi .L311 +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4381 .loc 1 2129 0 + 4382 0014 2268 ldr r2, [r4] + 4383 0016 5368 ldr r3, [r2, #4] + 4384 0018 0121 movs r1, #1 + 4385 001a 8B43 bics r3, r1 + 4386 001c 5360 str r3, [r2, #4] +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4387 .loc 1 2132 0 + 4388 001e 2268 ldr r2, [r4] + 4389 0020 5368 ldr r3, [r2, #4] + 4390 0022 0131 adds r1, r1, #1 + 4391 0024 8B43 bics r3, r1 + 4392 0026 5360 str r3, [r2, #4] +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4393 .loc 1 2135 0 + 4394 0028 8023 movs r3, #128 + ARM GAS /tmp/ccApM0GN.s page 131 + + + 4395 002a 9B01 lsls r3, r3, #6 + 4396 002c A26A ldr r2, [r4, #40] + 4397 002e 9A42 cmp r2, r3 + 4398 0030 11D0 beq .L319 + 4399 .LVL273: + 4400 .L312: +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4401 .loc 1 2161 0 + 4402 0032 8223 movs r3, #130 + 4403 0034 5B00 lsls r3, r3, #1 + 4404 0036 6268 ldr r2, [r4, #4] + 4405 0038 9A42 cmp r2, r3 + 4406 003a 36D0 beq .L320 + 4407 .L315: +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4408 .loc 1 2167 0 + 4409 003c 0023 movs r3, #0 + 4410 003e E387 strh r3, [r4, #62] +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4411 .loc 1 2168 0 + 4412 0040 5133 adds r3, r3, #81 + 4413 0042 0122 movs r2, #1 + 4414 0044 E254 strb r2, [r4, r3] +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4415 .loc 1 2171 0 + 4416 0046 636D ldr r3, [r4, #84] + 4417 0048 002B cmp r3, #0 + 4418 004a 3DD0 beq .L317 +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4419 .loc 1 2173 0 + 4420 004c 2000 movs r0, r4 + 4421 004e FFF7FEFF bl HAL_SPI_ErrorCallback + 4422 .LVL274: + 4423 .L310: +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4424 .loc 1 2184 0 + 4425 0052 02B0 add sp, sp, #8 + 4426 @ sp needed + 4427 .LVL275: + 4428 0054 10BD pop {r4, pc} + 4429 .LVL276: + 4430 .L319: +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4431 .loc 1 2138 0 + 4432 0056 0A23 movs r3, #10 + 4433 0058 0022 movs r2, #0 + 4434 005a 0139 subs r1, r1, #1 + 4435 005c 2000 movs r0, r4 + 4436 .LVL277: + 4437 005e FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4438 .LVL278: + 4439 0062 0028 cmp r0, #0 + 4440 0064 03D0 beq .L313 +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4441 .loc 1 2140 0 + 4442 0066 636D ldr r3, [r4, #84] + 4443 0068 2022 movs r2, #32 + ARM GAS /tmp/ccApM0GN.s page 132 + + + 4444 006a 1343 orrs r3, r2 + 4445 006c 6365 str r3, [r4, #84] + 4446 .L313: +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ + 4447 .loc 1 2144 0 + 4448 006e 2368 ldr r3, [r4] + 4449 0070 DB68 ldr r3, [r3, #12] + 4450 0072 9BB2 uxth r3, r3 + 4451 0074 6A46 mov r2, sp + 4452 0076 D380 strh r3, [r2, #6] +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4453 .loc 1 2145 0 + 4454 0078 D388 ldrh r3, [r2, #6] +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4455 .loc 1 2148 0 + 4456 007a 0A23 movs r3, #10 + 4457 007c 0122 movs r2, #1 + 4458 007e 0121 movs r1, #1 + 4459 0080 2000 movs r0, r4 + 4460 0082 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4461 .LVL279: + 4462 0086 0028 cmp r0, #0 + 4463 0088 03D0 beq .L314 +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4464 .loc 1 2150 0 + 4465 008a 636D ldr r3, [r4, #84] + 4466 008c 2022 movs r2, #32 + 4467 008e 1343 orrs r3, r2 + 4468 0090 6365 str r3, [r4, #84] + 4469 .L314: +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4470 .loc 1 2154 0 + 4471 0092 2368 ldr r3, [r4] + 4472 0094 9A68 ldr r2, [r3, #8] + 4473 0096 D206 lsls r2, r2, #27 + 4474 0098 CBD5 bpl .L312 +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + 4475 .loc 1 2156 0 + 4476 009a 626D ldr r2, [r4, #84] + 4477 009c 0221 movs r1, #2 + 4478 009e 0A43 orrs r2, r1 + 4479 00a0 6265 str r2, [r4, #84] +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4480 .loc 1 2157 0 + 4481 00a2 1122 movs r2, #17 + 4482 00a4 5242 rsbs r2, r2, #0 + 4483 00a6 9A60 str r2, [r3, #8] + 4484 00a8 C3E7 b .L312 + 4485 .L320: +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4486 .loc 1 2161 0 discriminator 1 + 4487 00aa A368 ldr r3, [r4, #8] + 4488 00ac 8022 movs r2, #128 + 4489 00ae 1202 lsls r2, r2, #8 + 4490 00b0 9342 cmp r3, r2 + 4491 00b2 03D0 beq .L316 +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + ARM GAS /tmp/ccApM0GN.s page 133 + + + 4492 .loc 1 2161 0 is_stmt 0 discriminator 2 + 4493 00b4 8022 movs r2, #128 + 4494 00b6 D200 lsls r2, r2, #3 + 4495 00b8 9342 cmp r3, r2 + 4496 00ba BFD1 bne .L315 + 4497 .L316: +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4498 .loc 1 2164 0 is_stmt 1 + 4499 00bc 2268 ldr r2, [r4] + 4500 00be 1368 ldr r3, [r2] + 4501 00c0 4021 movs r1, #64 + 4502 00c2 8B43 bics r3, r1 + 4503 00c4 1360 str r3, [r2] + 4504 00c6 B9E7 b .L315 + 4505 .L317: +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4506 .loc 1 2177 0 + 4507 00c8 2000 movs r0, r4 + 4508 00ca FFF7FEFF bl HAL_SPI_RxCpltCallback + 4509 .LVL280: + 4510 00ce C0E7 b .L310 + 4511 .LVL281: + 4512 .L311: +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4513 .loc 1 2182 0 + 4514 00d0 2000 movs r0, r4 + 4515 .LVL282: + 4516 00d2 FFF7FEFF bl HAL_SPI_RxCpltCallback + 4517 .LVL283: +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4518 .loc 1 2184 0 + 4519 00d6 BCE7 b .L310 + 4520 .cfi_endproc + 4521 .LFE71: + 4523 .section .text.SPI_DMATransmitReceiveCplt,"ax",%progbits + 4524 .align 1 + 4525 .syntax unified + 4526 .code 16 + 4527 .thumb_func + 4528 .fpu softvfp + 4530 SPI_DMATransmitReceiveCplt: + 4531 .LFB72: +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __IO uint16_t tmpreg = 0U; + 4532 .loc 1 2193 0 + 4533 .cfi_startproc + 4534 @ args = 0, pretend = 0, frame = 8 + 4535 @ frame_needed = 0, uses_anonymous_args = 0 + 4536 .LVL284: + 4537 0000 10B5 push {r4, lr} + 4538 .LCFI33: + 4539 .cfi_def_cfa_offset 8 + 4540 .cfi_offset 4, -8 + 4541 .cfi_offset 14, -4 + 4542 0002 82B0 sub sp, sp, #8 + 4543 .LCFI34: + 4544 .cfi_def_cfa_offset 16 +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + ARM GAS /tmp/ccApM0GN.s page 134 + + + 4545 .loc 1 2194 0 + 4546 0004 6B46 mov r3, sp + 4547 0006 0022 movs r2, #0 + 4548 0008 DA80 strh r2, [r3, #6] +2196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 4549 .loc 1 2196 0 + 4550 000a 846A ldr r4, [r0, #40] + 4551 .LVL285: +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4552 .loc 1 2197 0 + 4553 000c 0368 ldr r3, [r0] + 4554 000e 1B68 ldr r3, [r3] + 4555 0010 9B06 lsls r3, r3, #26 + 4556 0012 5DD4 bmi .L322 +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4557 .loc 1 2200 0 + 4558 0014 8023 movs r3, #128 + 4559 0016 9B01 lsls r3, r3, #6 + 4560 0018 A26A ldr r2, [r4, #40] + 4561 001a 9A42 cmp r2, r3 + 4562 001c 2ED0 beq .L329 + 4563 .LVL286: + 4564 .L323: +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4565 .loc 1 2224 0 + 4566 001e 0A23 movs r3, #10 + 4567 0020 0022 movs r2, #0 + 4568 0022 0221 movs r1, #2 + 4569 0024 2000 movs r0, r4 + 4570 0026 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4571 .LVL287: + 4572 002a 0028 cmp r0, #0 + 4573 002c 03D0 beq .L325 +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4574 .loc 1 2226 0 + 4575 002e 636D ldr r3, [r4, #84] + 4576 0030 2022 movs r2, #32 + 4577 0032 1343 orrs r3, r2 + 4578 0034 6365 str r3, [r4, #84] + 4579 .L325: +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4580 .loc 1 2230 0 + 4581 0036 2268 ldr r2, [r4] + 4582 0038 5368 ldr r3, [r2, #4] + 4583 003a 0221 movs r1, #2 + 4584 003c 8B43 bics r3, r1 + 4585 003e 5360 str r3, [r2, #4] +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4586 .loc 1 2233 0 + 4587 0040 0A23 movs r3, #10 + 4588 0042 0122 movs r2, #1 + 4589 0044 7E31 adds r1, r1, #126 + 4590 0046 2000 movs r0, r4 + 4591 0048 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4592 .LVL288: + 4593 004c 0028 cmp r0, #0 + 4594 004e 03D0 beq .L326 + ARM GAS /tmp/ccApM0GN.s page 135 + + +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4595 .loc 1 2235 0 + 4596 0050 636D ldr r3, [r4, #84] + 4597 0052 2022 movs r2, #32 + 4598 0054 1343 orrs r3, r2 + 4599 0056 6365 str r3, [r4, #84] + 4600 .L326: +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4601 .loc 1 2239 0 + 4602 0058 2168 ldr r1, [r4] + 4603 005a 4B68 ldr r3, [r1, #4] + 4604 005c 0122 movs r2, #1 + 4605 005e 9343 bics r3, r2 + 4606 0060 4B60 str r3, [r1, #4] +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->RxXferCount = 0U; + 4607 .loc 1 2241 0 + 4608 0062 0023 movs r3, #0 + 4609 0064 E386 strh r3, [r4, #54] +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4610 .loc 1 2242 0 + 4611 0066 E387 strh r3, [r4, #62] +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4612 .loc 1 2244 0 + 4613 0068 5133 adds r3, r3, #81 + 4614 006a E254 strb r2, [r4, r3] +2247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4615 .loc 1 2247 0 + 4616 006c 636D ldr r3, [r4, #84] + 4617 006e 002B cmp r3, #0 + 4618 0070 2AD0 beq .L327 +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4619 .loc 1 2249 0 + 4620 0072 2000 movs r0, r4 + 4621 0074 FFF7FEFF bl HAL_SPI_ErrorCallback + 4622 .LVL289: + 4623 .L321: +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4624 .loc 1 2260 0 + 4625 0078 02B0 add sp, sp, #8 + 4626 @ sp needed + 4627 .LVL290: + 4628 007a 10BD pop {r4, pc} + 4629 .LVL291: + 4630 .L329: +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4631 .loc 1 2203 0 + 4632 007c 0A23 movs r3, #10 + 4633 007e 0122 movs r2, #1 + 4634 0080 0121 movs r1, #1 + 4635 0082 2000 movs r0, r4 + 4636 .LVL292: + 4637 0084 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4638 .LVL293: + 4639 0088 0028 cmp r0, #0 + 4640 008a 10D0 beq .L330 + 4641 .L324: +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ + ARM GAS /tmp/ccApM0GN.s page 136 + + + 4642 .loc 1 2212 0 + 4643 008c 2268 ldr r2, [r4] + 4644 008e D368 ldr r3, [r2, #12] + 4645 0090 9BB2 uxth r3, r3 + 4646 0092 6946 mov r1, sp + 4647 0094 CB80 strh r3, [r1, #6] +2213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4648 .loc 1 2213 0 + 4649 0096 CB88 ldrh r3, [r1, #6] +2216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4650 .loc 1 2216 0 + 4651 0098 9368 ldr r3, [r2, #8] + 4652 009a DB06 lsls r3, r3, #27 + 4653 009c BFD5 bpl .L323 +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + 4654 .loc 1 2218 0 + 4655 009e 636D ldr r3, [r4, #84] + 4656 00a0 0221 movs r1, #2 + 4657 00a2 0B43 orrs r3, r1 + 4658 00a4 6365 str r3, [r4, #84] +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4659 .loc 1 2219 0 + 4660 00a6 1123 movs r3, #17 + 4661 00a8 5B42 rsbs r3, r3, #0 + 4662 00aa 9360 str r3, [r2, #8] + 4663 00ac B7E7 b .L323 + 4664 .L330: +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4665 .loc 1 2206 0 + 4666 00ae 0A23 movs r3, #10 + 4667 00b0 0022 movs r2, #0 + 4668 00b2 0121 movs r1, #1 + 4669 00b4 2000 movs r0, r4 + 4670 00b6 FFF7FEFF bl SPI_WaitOnFlagUntilTimeout + 4671 .LVL294: + 4672 00ba 0028 cmp r0, #0 + 4673 00bc E6D0 beq .L324 +2208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4674 .loc 1 2208 0 + 4675 00be 636D ldr r3, [r4, #84] + 4676 00c0 2022 movs r2, #32 + 4677 00c2 1343 orrs r3, r2 + 4678 00c4 6365 str r3, [r4, #84] + 4679 00c6 E1E7 b .L324 + 4680 .L327: +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4681 .loc 1 2253 0 + 4682 00c8 2000 movs r0, r4 + 4683 00ca FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 4684 .LVL295: + 4685 00ce D3E7 b .L321 + 4686 .LVL296: + 4687 .L322: +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4688 .loc 1 2258 0 + 4689 00d0 2000 movs r0, r4 + 4690 .LVL297: + ARM GAS /tmp/ccApM0GN.s page 137 + + + 4691 00d2 FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 4692 .LVL298: +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4693 .loc 1 2260 0 + 4694 00d6 CFE7 b .L321 + 4695 .cfi_endproc + 4696 .LFE72: + 4698 .section .text.HAL_SPI_IRQHandler,"ax",%progbits + 4699 .align 1 + 4700 .global HAL_SPI_IRQHandler + 4701 .syntax unified + 4702 .code 16 + 4703 .thumb_func + 4704 .fpu softvfp + 4706 HAL_SPI_IRQHandler: + 4707 .LFB55: +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + 4708 .loc 1 1602 0 + 4709 .cfi_startproc + 4710 @ args = 0, pretend = 0, frame = 16 + 4711 @ frame_needed = 0, uses_anonymous_args = 0 + 4712 .LVL299: + 4713 0000 00B5 push {lr} + 4714 .LCFI35: + 4715 .cfi_def_cfa_offset 4 + 4716 .cfi_offset 14, -4 + 4717 0002 85B0 sub sp, sp, #20 + 4718 .LCFI36: + 4719 .cfi_def_cfa_offset 24 +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4720 .loc 1 1604 0 + 4721 0004 0368 ldr r3, [r0] + 4722 0006 5A68 ldr r2, [r3, #4] + 4723 0008 5206 lsls r2, r2, #25 + 4724 000a 08D5 bpl .L332 +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4725 .loc 1 1604 0 is_stmt 0 discriminator 1 + 4726 000c 9A68 ldr r2, [r3, #8] + 4727 000e D207 lsls r2, r2, #31 + 4728 0010 05D5 bpl .L332 +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4729 .loc 1 1604 0 discriminator 2 + 4730 0012 9A68 ldr r2, [r3, #8] + 4731 0014 5206 lsls r2, r2, #25 + 4732 0016 02D4 bmi .L332 +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return; + 4733 .loc 1 1606 0 is_stmt 1 + 4734 0018 836C ldr r3, [r0, #72] + 4735 001a 9847 blx r3 + 4736 .LVL300: +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4737 .loc 1 1607 0 + 4738 001c 07E0 b .L331 + 4739 .LVL301: + 4740 .L332: +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4741 .loc 1 1611 0 + ARM GAS /tmp/ccApM0GN.s page 138 + + + 4742 001e 5A68 ldr r2, [r3, #4] + 4743 0020 1206 lsls r2, r2, #24 + 4744 0022 06D5 bpl .L334 +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4745 .loc 1 1611 0 is_stmt 0 discriminator 1 + 4746 0024 9A68 ldr r2, [r3, #8] + 4747 0026 9207 lsls r2, r2, #30 + 4748 0028 03D5 bpl .L334 +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return; + 4749 .loc 1 1613 0 is_stmt 1 + 4750 002a C36C ldr r3, [r0, #76] + 4751 002c 9847 blx r3 + 4752 .LVL302: + 4753 .L331: +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4754 .loc 1 1657 0 + 4755 002e 05B0 add sp, sp, #20 + 4756 @ sp needed + 4757 0030 00BD pop {pc} + 4758 .LVL303: + 4759 .L334: +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4760 .loc 1 1617 0 + 4761 0032 5A68 ldr r2, [r3, #4] + 4762 0034 9206 lsls r2, r2, #26 + 4763 0036 FAD5 bpl .L331 +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4764 .loc 1 1620 0 + 4765 0038 9A68 ldr r2, [r3, #8] + 4766 003a D206 lsls r2, r2, #27 + 4767 003c 06D5 bpl .L335 +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + 4768 .loc 1 1622 0 + 4769 003e 426D ldr r2, [r0, #84] + 4770 0040 0221 movs r1, #2 + 4771 0042 0A43 orrs r2, r1 + 4772 0044 4265 str r2, [r0, #84] +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4773 .loc 1 1623 0 + 4774 0046 1122 movs r2, #17 + 4775 0048 5242 rsbs r2, r2, #0 + 4776 004a 9A60 str r2, [r3, #8] + 4777 .L335: +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4778 .loc 1 1626 0 + 4779 004c 0368 ldr r3, [r0] + 4780 004e 9A68 ldr r2, [r3, #8] + 4781 0050 9206 lsls r2, r2, #26 + 4782 0052 0AD5 bpl .L336 +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_MODFFLAG(hspi); + 4783 .loc 1 1628 0 + 4784 0054 426D ldr r2, [r0, #84] + 4785 0056 0121 movs r1, #1 + 4786 0058 0A43 orrs r2, r1 + 4787 005a 4265 str r2, [r0, #84] + 4788 .LBB12: +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + ARM GAS /tmp/ccApM0GN.s page 139 + + + 4789 .loc 1 1629 0 + 4790 005c 9A68 ldr r2, [r3, #8] + 4791 005e 0192 str r2, [sp, #4] + 4792 0060 1A68 ldr r2, [r3] + 4793 0062 3F31 adds r1, r1, #63 + 4794 0064 8A43 bics r2, r1 + 4795 0066 1A60 str r2, [r3] + 4796 0068 019B ldr r3, [sp, #4] + 4797 .L336: + 4798 .LBE12: +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4799 .loc 1 1633 0 + 4800 006a 0368 ldr r3, [r0] + 4801 006c 9A68 ldr r2, [r3, #8] + 4802 006e 5206 lsls r2, r2, #25 + 4803 0070 0CD5 bpl .L337 +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4804 .loc 1 1635 0 + 4805 0072 5122 movs r2, #81 + 4806 0074 825C ldrb r2, [r0, r2] + 4807 0076 122A cmp r2, #18 + 4808 0078 08D0 beq .L337 +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 4809 .loc 1 1637 0 + 4810 007a 426D ldr r2, [r0, #84] + 4811 007c 0421 movs r1, #4 + 4812 007e 0A43 orrs r2, r1 + 4813 0080 4265 str r2, [r0, #84] + 4814 .LBB13: +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4815 .loc 1 1638 0 + 4816 0082 DA68 ldr r2, [r3, #12] + 4817 0084 0292 str r2, [sp, #8] + 4818 0086 9A68 ldr r2, [r3, #8] + 4819 0088 0292 str r2, [sp, #8] + 4820 008a 029A ldr r2, [sp, #8] + 4821 .L337: + 4822 .LBE13: +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4823 .loc 1 1643 0 + 4824 008c 9A68 ldr r2, [r3, #8] + 4825 008e D205 lsls r2, r2, #23 + 4826 0090 06D5 bpl .L338 +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4827 .loc 1 1645 0 + 4828 0092 426D ldr r2, [r0, #84] + 4829 0094 0821 movs r1, #8 + 4830 0096 0A43 orrs r2, r1 + 4831 0098 4265 str r2, [r0, #84] + 4832 .LBB14: +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4833 .loc 1 1646 0 + 4834 009a 9A68 ldr r2, [r3, #8] + 4835 009c 0392 str r2, [sp, #12] + 4836 009e 039A ldr r2, [sp, #12] + 4837 .L338: + 4838 .LBE14: + ARM GAS /tmp/ccApM0GN.s page 140 + + +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** { + 4839 .loc 1 1650 0 + 4840 00a0 426D ldr r2, [r0, #84] + 4841 00a2 002A cmp r2, #0 + 4842 00a4 C3D0 beq .L331 +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4843 .loc 1 1652 0 + 4844 00a6 5A68 ldr r2, [r3, #4] + 4845 00a8 E021 movs r1, #224 + 4846 00aa 8A43 bics r2, r1 + 4847 00ac 5A60 str r2, [r3, #4] +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 4848 .loc 1 1653 0 + 4849 00ae 5123 movs r3, #81 + 4850 00b0 0122 movs r2, #1 + 4851 00b2 C254 strb r2, [r0, r3] +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4852 .loc 1 1654 0 + 4853 00b4 FFF7FEFF bl HAL_SPI_ErrorCallback + 4854 .LVL304: + 4855 00b8 B9E7 b .L331 + 4856 .cfi_endproc + 4857 .LFE55: + 4859 .section .text.HAL_SPI_GetState,"ax",%progbits + 4860 .align 1 + 4861 .global HAL_SPI_GetState + 4862 .syntax unified + 4863 .code 16 + 4864 .thumb_func + 4865 .fpu softvfp + 4867 HAL_SPI_GetState: + 4868 .LFB63: +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return hspi->State; + 4869 .loc 1 1799 0 + 4870 .cfi_startproc + 4871 @ args = 0, pretend = 0, frame = 0 + 4872 @ frame_needed = 0, uses_anonymous_args = 0 + 4873 @ link register save eliminated. + 4874 .LVL305: +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4875 .loc 1 1800 0 + 4876 0000 5123 movs r3, #81 + 4877 0002 C05C ldrb r0, [r0, r3] + 4878 .LVL306: + 4879 0004 C0B2 uxtb r0, r0 +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4880 .loc 1 1801 0 + 4881 @ sp needed + 4882 0006 7047 bx lr + 4883 .cfi_endproc + 4884 .LFE63: + 4886 .section .text.HAL_SPI_GetError,"ax",%progbits + 4887 .align 1 + 4888 .global HAL_SPI_GetError + 4889 .syntax unified + 4890 .code 16 + 4891 .thumb_func + ARM GAS /tmp/ccApM0GN.s page 141 + + + 4892 .fpu softvfp + 4894 HAL_SPI_GetError: + 4895 .LFB64: +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** return hspi->ErrorCode; + 4896 .loc 1 1810 0 + 4897 .cfi_startproc + 4898 @ args = 0, pretend = 0, frame = 0 + 4899 @ frame_needed = 0, uses_anonymous_args = 0 + 4900 @ link register save eliminated. + 4901 .LVL307: +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** } + 4902 .loc 1 1811 0 + 4903 0000 406D ldr r0, [r0, #84] + 4904 .LVL308: +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c **** + 4905 .loc 1 1812 0 + 4906 @ sp needed + 4907 0002 7047 bx lr + 4908 .cfi_endproc + 4909 .LFE64: + 4911 .text + 4912 .Letext0: + 4913 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 4914 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 4915 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 4916 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 4917 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 4918 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 4919 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 4920 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 4921 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 4922 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 4923 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 4924 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h" + 4925 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccApM0GN.s page 142 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_spi.c + /tmp/ccApM0GN.s:16 .text.SPI_WaitOnFlagUntilTimeout:0000000000000000 $t + /tmp/ccApM0GN.s:22 .text.SPI_WaitOnFlagUntilTimeout:0000000000000000 SPI_WaitOnFlagUntilTimeout + /tmp/ccApM0GN.s:208 .text.SPI_WaitOnFlagUntilTimeout:00000000000000ec $d + /tmp/ccApM0GN.s:213 .text.HAL_SPI_MspInit:0000000000000000 $t + /tmp/ccApM0GN.s:220 .text.HAL_SPI_MspInit:0000000000000000 HAL_SPI_MspInit + /tmp/ccApM0GN.s:235 .text.HAL_SPI_Init:0000000000000000 $t + /tmp/ccApM0GN.s:242 .text.HAL_SPI_Init:0000000000000000 HAL_SPI_Init + /tmp/ccApM0GN.s:347 .text.HAL_SPI_Init:0000000000000084 $d + /tmp/ccApM0GN.s:352 .text.HAL_SPI_MspDeInit:0000000000000000 $t + /tmp/ccApM0GN.s:359 .text.HAL_SPI_MspDeInit:0000000000000000 HAL_SPI_MspDeInit + /tmp/ccApM0GN.s:374 .text.HAL_SPI_DeInit:0000000000000000 $t + /tmp/ccApM0GN.s:381 .text.HAL_SPI_DeInit:0000000000000000 HAL_SPI_DeInit + /tmp/ccApM0GN.s:436 .text.HAL_SPI_Transmit:0000000000000000 $t + /tmp/ccApM0GN.s:443 .text.HAL_SPI_Transmit:0000000000000000 HAL_SPI_Transmit + /tmp/ccApM0GN.s:811 .text.HAL_SPI_Transmit:00000000000001e0 $d + /tmp/ccApM0GN.s:816 .text.HAL_SPI_TransmitReceive:0000000000000000 $t + /tmp/ccApM0GN.s:823 .text.HAL_SPI_TransmitReceive:0000000000000000 HAL_SPI_TransmitReceive + /tmp/ccApM0GN.s:1492 .text.HAL_SPI_TransmitReceive:00000000000003a8 $d + /tmp/ccApM0GN.s:1497 .text.HAL_SPI_Receive:0000000000000000 $t + /tmp/ccApM0GN.s:1504 .text.HAL_SPI_Receive:0000000000000000 HAL_SPI_Receive + /tmp/ccApM0GN.s:1946 .text.HAL_SPI_Receive:0000000000000258 $d + /tmp/ccApM0GN.s:1952 .text.HAL_SPI_Transmit_IT:0000000000000000 $t + /tmp/ccApM0GN.s:1959 .text.HAL_SPI_Transmit_IT:0000000000000000 HAL_SPI_Transmit_IT + /tmp/ccApM0GN.s:2129 .text.HAL_SPI_Transmit_IT:00000000000000c0 $d + /tmp/ccApM0GN.s:3654 .text.SPI_TxISR:0000000000000000 SPI_TxISR + /tmp/ccApM0GN.s:2135 .text.HAL_SPI_TransmitReceive_IT:0000000000000000 $t + /tmp/ccApM0GN.s:2142 .text.HAL_SPI_TransmitReceive_IT:0000000000000000 HAL_SPI_TransmitReceive_IT + /tmp/ccApM0GN.s:2327 .text.HAL_SPI_TransmitReceive_IT:00000000000000c8 $d + /tmp/ccApM0GN.s:4126 .text.SPI_2LinesRxISR:0000000000000000 SPI_2LinesRxISR + /tmp/ccApM0GN.s:2334 .text.HAL_SPI_Receive_IT:0000000000000000 $t + /tmp/ccApM0GN.s:2341 .text.HAL_SPI_Receive_IT:0000000000000000 HAL_SPI_Receive_IT + /tmp/ccApM0GN.s:2515 .text.HAL_SPI_Receive_IT:00000000000000c8 $d + /tmp/ccApM0GN.s:4038 .text.SPI_RxISR:0000000000000000 SPI_RxISR + /tmp/ccApM0GN.s:2522 .text.HAL_SPI_Transmit_DMA:0000000000000000 $t + /tmp/ccApM0GN.s:2529 .text.HAL_SPI_Transmit_DMA:0000000000000000 HAL_SPI_Transmit_DMA + /tmp/ccApM0GN.s:2723 .text.HAL_SPI_Transmit_DMA:00000000000000e4 $d + /tmp/ccApM0GN.s:3495 .text.SPI_DMAHalfTransmitCplt:0000000000000000 SPI_DMAHalfTransmitCplt + /tmp/ccApM0GN.s:4238 .text.SPI_DMATransmitCplt:0000000000000000 SPI_DMATransmitCplt + /tmp/ccApM0GN.s:4193 .text.SPI_DMAError:0000000000000000 SPI_DMAError + /tmp/ccApM0GN.s:2731 .text.HAL_SPI_TransmitReceive_DMA:0000000000000000 $t + /tmp/ccApM0GN.s:2738 .text.HAL_SPI_TransmitReceive_DMA:0000000000000000 HAL_SPI_TransmitReceive_DMA + /tmp/ccApM0GN.s:2982 .text.HAL_SPI_TransmitReceive_DMA:0000000000000130 $d + /tmp/ccApM0GN.s:3601 .text.SPI_DMAHalfTransmitReceiveCplt:0000000000000000 SPI_DMAHalfTransmitReceiveCplt + /tmp/ccApM0GN.s:4530 .text.SPI_DMATransmitReceiveCplt:0000000000000000 SPI_DMATransmitReceiveCplt + /tmp/ccApM0GN.s:3548 .text.SPI_DMAHalfReceiveCplt:0000000000000000 SPI_DMAHalfReceiveCplt + /tmp/ccApM0GN.s:4354 .text.SPI_DMAReceiveCplt:0000000000000000 SPI_DMAReceiveCplt + /tmp/ccApM0GN.s:2992 .text.HAL_SPI_Receive_DMA:0000000000000000 $t + /tmp/ccApM0GN.s:2999 .text.HAL_SPI_Receive_DMA:0000000000000000 HAL_SPI_Receive_DMA + /tmp/ccApM0GN.s:3211 .text.HAL_SPI_Receive_DMA:0000000000000104 $d + /tmp/ccApM0GN.s:3220 .text.HAL_SPI_DMAPause:0000000000000000 $t + /tmp/ccApM0GN.s:3227 .text.HAL_SPI_DMAPause:0000000000000000 HAL_SPI_DMAPause + /tmp/ccApM0GN.s:3280 .text.HAL_SPI_DMAResume:0000000000000000 $t + /tmp/ccApM0GN.s:3287 .text.HAL_SPI_DMAResume:0000000000000000 HAL_SPI_DMAResume + /tmp/ccApM0GN.s:3340 .text.HAL_SPI_DMAStop:0000000000000000 $t + /tmp/ccApM0GN.s:3347 .text.HAL_SPI_DMAStop:0000000000000000 HAL_SPI_DMAStop + ARM GAS /tmp/ccApM0GN.s page 143 + + + /tmp/ccApM0GN.s:3401 .text.HAL_SPI_TxCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3408 .text.HAL_SPI_TxCpltCallback:0000000000000000 HAL_SPI_TxCpltCallback + /tmp/ccApM0GN.s:3423 .text.HAL_SPI_RxCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3430 .text.HAL_SPI_RxCpltCallback:0000000000000000 HAL_SPI_RxCpltCallback + /tmp/ccApM0GN.s:3445 .text.HAL_SPI_TxRxCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3452 .text.HAL_SPI_TxRxCpltCallback:0000000000000000 HAL_SPI_TxRxCpltCallback + /tmp/ccApM0GN.s:3467 .text.HAL_SPI_TxHalfCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3474 .text.HAL_SPI_TxHalfCpltCallback:0000000000000000 HAL_SPI_TxHalfCpltCallback + /tmp/ccApM0GN.s:3489 .text.SPI_DMAHalfTransmitCplt:0000000000000000 $t + /tmp/ccApM0GN.s:3520 .text.HAL_SPI_RxHalfCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3527 .text.HAL_SPI_RxHalfCpltCallback:0000000000000000 HAL_SPI_RxHalfCpltCallback + /tmp/ccApM0GN.s:3542 .text.SPI_DMAHalfReceiveCplt:0000000000000000 $t + /tmp/ccApM0GN.s:3573 .text.HAL_SPI_TxRxHalfCpltCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3580 .text.HAL_SPI_TxRxHalfCpltCallback:0000000000000000 HAL_SPI_TxRxHalfCpltCallback + /tmp/ccApM0GN.s:3595 .text.SPI_DMAHalfTransmitReceiveCplt:0000000000000000 $t + /tmp/ccApM0GN.s:3626 .text.HAL_SPI_ErrorCallback:0000000000000000 $t + /tmp/ccApM0GN.s:3633 .text.HAL_SPI_ErrorCallback:0000000000000000 HAL_SPI_ErrorCallback + /tmp/ccApM0GN.s:3648 .text.SPI_TxISR:0000000000000000 $t + /tmp/ccApM0GN.s:3842 .text.SPI_RxCloseIRQHandler:0000000000000000 $t + /tmp/ccApM0GN.s:3848 .text.SPI_RxCloseIRQHandler:0000000000000000 SPI_RxCloseIRQHandler + /tmp/ccApM0GN.s:4027 .text.SPI_RxCloseIRQHandler:00000000000000f4 $d + /tmp/ccApM0GN.s:4032 .text.SPI_RxISR:0000000000000000 $t + /tmp/ccApM0GN.s:4120 .text.SPI_2LinesRxISR:0000000000000000 $t + /tmp/ccApM0GN.s:4187 .text.SPI_DMAError:0000000000000000 $t + /tmp/ccApM0GN.s:4232 .text.SPI_DMATransmitCplt:0000000000000000 $t + /tmp/ccApM0GN.s:4348 .text.SPI_DMAReceiveCplt:0000000000000000 $t + /tmp/ccApM0GN.s:4524 .text.SPI_DMATransmitReceiveCplt:0000000000000000 $t + /tmp/ccApM0GN.s:4699 .text.HAL_SPI_IRQHandler:0000000000000000 $t + /tmp/ccApM0GN.s:4706 .text.HAL_SPI_IRQHandler:0000000000000000 HAL_SPI_IRQHandler + /tmp/ccApM0GN.s:4860 .text.HAL_SPI_GetState:0000000000000000 $t + /tmp/ccApM0GN.s:4867 .text.HAL_SPI_GetState:0000000000000000 HAL_SPI_GetState + /tmp/ccApM0GN.s:4887 .text.HAL_SPI_GetError:0000000000000000 $t + /tmp/ccApM0GN.s:4894 .text.HAL_SPI_GetError:0000000000000000 HAL_SPI_GetError + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort diff --git a/build/stm32l0xx_hal_tim.d b/build/stm32l0xx_hal_tim.d new file mode 100644 index 0000000..c9b61b8 --- /dev/null +++ b/build/stm32l0xx_hal_tim.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_tim.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_tim.lst b/build/stm32l0xx_hal_tim.lst new file mode 100644 index 0000000..9665685 --- /dev/null +++ b/build/stm32l0xx_hal_tim.lst @@ -0,0 +1,16567 @@ +ARM GAS /tmp/ccH6KUTS.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_tim.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.TIM_Base_SetConfig,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 TIM_Base_SetConfig: + 23 .LFB130: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @file stm32l0xx_hal_tim.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * functionalities of the Timer (TIM) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Base Initialization + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Base Start + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Base Start Interruption + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Base Start DMA + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Output Compare/PWM Initialization + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Output Compare/PWM Channel Configuration + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Output Compare/PWM Start + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Output Compare/PWM Start Interruption + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Output Compare/PWM Start DMA + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Input Capture Initialization + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Input Capture Channel Configuration + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Input Capture Start + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Input Capture Start Interruption + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Input Capture Start DMA + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer One Pulse Initialization + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer One Pulse Channel Configuration + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer One Pulse Start + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Encoder Interface Initialization + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Encoder Interface Start + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Encoder Interface Start Interruption + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Encoder Interface Start DMA + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer OCRef clear configuration + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer External Clock configuration + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Complementary signal bread and dead time configuration + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + Timer Master and Slave synchronization configuration + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + ARM GAS /tmp/ccH6KUTS.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### TIMER Generic features ##### + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] The Timer features include: + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) 16-bit up, down, up/down auto-reload counter. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** frequency either by any factor between 1 and 65536. + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Up to 4 independent channels for: + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Input Capture + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Output Compare + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) PWM generation (Edge and Center-aligned Mode) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) One-pulse mode output + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Synchronization circuit to control the timer with external signals and to interconnect + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** several timers together. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** purposes + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### How to use this driver ##### + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ================================================================================ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Initialize the TIM low level resources by implementing the following functions + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** depending from feature used : + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Time Base : HAL_TIM_Base_MspInit() + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Input Capture : HAL_TIM_IC_MspInit() + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Output Compare : HAL_TIM_OC_MspInit() + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) PWM generation : HAL_TIM_PWM_MspInit() + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Initialize the TIM low level resources : + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (##) TIM pins configuration + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+++) Enable the clock for the TIM GPIOs using the following function: + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) The external Clock can be configured, if needed (the default clock is the internal clock f + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** using the following function: + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before any start functio + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Configure the TIM in the desired functioning mode using one of the + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** initialization function of this driver: + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** Output Compare signal. + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** PWM signal. + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** external signal. + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pul + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) Activate the TIM peripheral using one of the start functions: + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), + ARM GAS /tmp/ccH6KUTS.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT() + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (#) The DMA Burst is managed with the two following functions: + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_DMABurst_WriteStart + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_DMABurst_ReadStart + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ****************************************************************************** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @attention + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * Redistribution and use in source and binary forms, with or without modification, + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * are permitted provided that the following conditions are met: + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * 1. Redistributions of source code must retain the above copyright notice, + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * this list of conditions and the following disclaimer. + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * this list of conditions and the following disclaimer in the documentation + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * and/or other materials provided with the distribution. + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * may be used to endorse or promote products derived from this software + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * without specific prior written permission. + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ****************************************************************************** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Includes ------------------------------------------------------------------*/ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** #include "stm32l0xx_hal.h" + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup STM32L0xx_HAL_Driver + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** #ifdef HAL_TIM_MODULE_ENABLED + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM HAL module driver + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Private + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private typedef -----------------------------------------------------------*/ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private define ------------------------------------------------------------*/ + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private macro -------------------------------------------------------------*/ + ARM GAS /tmp/ccH6KUTS.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private variables ---------------------------------------------------------*/ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private function prototypes -----------------------------------------------*/ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGP + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig) + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /*******************************************************************************/ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Exported functions ---------------------------------------------------------*/ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /*******************************************************************************/ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group1 + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Base functions + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer Base functions ##### + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM base. + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM base. + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Base. + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Base. + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Base and enable interrupt. + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Base and disable interrupt. + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Base and enable DMA transfer. + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Base and disable DMA transfer. + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Time base Unit according to the specified + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and create the associated handle. + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + ARM GAS /tmp/ccH6KUTS.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Base_MspInit(htim); + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Time Base configuration */ + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM Base peripheral + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Base_MspDeInit(htim); + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + ARM GAS /tmp/ccH6KUTS.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Base MSP. + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_Base_MspInit could be implemented in the user file + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM Base MSP. + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_Base_MspDeInit could be implemented in the user file + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Base generation. + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the TIM state*/ + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + ARM GAS /tmp/ccH6KUTS.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Base generation. + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the TIM state*/ + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Base generation in interrupt mode. + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Update interrupt */ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Base generation in interrupt mode. + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Update interrupt */ + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + ARM GAS /tmp/ccH6KUTS.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Base generation in DMA mode. + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData: The source Buffer address. + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Length: The length of data to be transferred from memory to peripheral. + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((pData == 0U ) && (Length > 0U)) + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Update DMA request */ + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Base generation in DMA mode. + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + ARM GAS /tmp/ccH6KUTS.s page 9 + + + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Update DMA request */ + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group2 + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Output Compare functions + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer Output Compare functions ##### + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM Output Compare. + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM Output Compare. + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Output Compare. + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Output Compare. + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Output Compare and enable interrupt. + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Output Compare and disable interrupt. + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Output Compare and enable DMA transfer. + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Output Compare and disable DMA transfer. + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Output Compare according to the specified + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and create the associated handle. + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Output Compare handle + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 10 + + + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/ + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_MspInit(htim); + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the base time for the Output Compare */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Output Compare handle + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_MspDeInit(htim); + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 11 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Output Compare MSP. + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_OC_MspInit could be implemented in the user file + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM Output Compare MSP. + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_OC_MspDeInit could be implemented in the user file + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation. + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be enabled. + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Output compare channel */ + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + ARM GAS /tmp/ccH6KUTS.s page 12 + + + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation. + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be disabled. + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Output compare channel */ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in interrupt mode. + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be enabled. + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 13 + + + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Output compare channel */ + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in interrupt mode. + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be disabled. + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + ARM GAS /tmp/ccH6KUTS.s page 14 + + + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Output compare channel */ + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in DMA mode. + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be enabled. + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData: The source Buffer address. + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Length: The length of data to be transferred from memory to TIM peripheral + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(((uint32_t)pData == 0U ) && (Length > 0U)) + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 15 + + + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1 + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2 + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3 + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 16 + + + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4 + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Output compare channel */ + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in DMA mode. + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be disabled. + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 17 + + + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Output compare channel */ + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group3 + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time PWM functions + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer PWM functions ##### + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM OPWM. + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM PWM. + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer PWM. + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer PWM. + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer PWM and enable interrupt. + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer PWM and disable interrupt. + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer PWM and enable DMA transfer. + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer PWM and disable DMA transfer. + ARM GAS /tmp/ccH6KUTS.s page 18 + + + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM PWM Time Base according to the specified + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and create the associated handle. + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_MspInit(htim); + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the base time for the PWM */ + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + ARM GAS /tmp/ccH6KUTS.s page 19 + + +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_MspDeInit(htim); +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM PWM MSP. +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_PWM_MspInit could be implemented in the user file +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM PWM MSP. +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_PWM_MspDeInit could be implemented in the user file +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the PWM signal generation. +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + ARM GAS /tmp/ccH6KUTS.s page 20 + + +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the PWM signal generation. +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare channel */ +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the PWM signal generation in interrupt mode. +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be enabled. +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ + ARM GAS /tmp/ccH6KUTS.s page 21 + + +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the PWM signal generation in interrupt mode. +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + ARM GAS /tmp/ccH6KUTS.s page 22 + + +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare channel */ +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM PWM signal generation in DMA mode. +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + ARM GAS /tmp/ccH6KUTS.s page 23 + + +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData: The source Buffer address. This buffer contains the values +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * which will be loaded inside the capture/compare registers. +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Length: The length of data to be transferred from memory to TIM peripheral +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(((uint32_t)pData == 0U ) && (Length > 0U)) +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1 +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2 + ARM GAS /tmp/ccH6KUTS.s page 24 + + +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3 +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Output Capture/Compare 3 request */ +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4 +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM PWM signal generation in DMA mode. +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + ARM GAS /tmp/ccH6KUTS.s page 25 + + +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare channel */ +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 26 + + +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group4 +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Input Capture functions +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer Input Capture functions ##### +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM Input Capture. +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM Input Capture. +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Input Capture. +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Input Capture. +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Input Capture and enable interrupt. +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Input Capture and disable interrupt. +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Input Capture and enable DMA transfer. +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Input Capture and disable DMA transfer. +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Time base according to the specified +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and create the associated handle. +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Input Capture handle +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_MspInit(htim); +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ + ARM GAS /tmp/ccH6KUTS.s page 27 + + +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the base time for the input capture */ +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Input Capture handle +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_MspDeInit(htim); +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM INput Capture MSP. +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_IC_MspInit could be implemented in the user file +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM Input Capture MSP. +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None + ARM GAS /tmp/ccH6KUTS.s page 28 + + +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_IC_MspDeInit could be implemented in the user file +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement. +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Input Capture channel */ +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement. +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channel */ +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + ARM GAS /tmp/ccH6KUTS.s page 29 + + +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement in interrupt mode. +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Input Capture channel */ +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 30 + + +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement in interrupt mode. +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel : TIM Channels to be disabled +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 31 + + +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channel */ +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement on in DMA mode. +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel : TIM Channels to be enabled +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData: The destination Buffer address. +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Length: The length of data to be transferred from TIM peripheral to memory. +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((pData == 0U ) && (Length > 0U)) +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData + ARM GAS /tmp/ccH6KUTS.s page 32 + + +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 33 + + +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Input Capture channel */ +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement on in DMA mode. +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel : TIM Channels to be disabled +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 DMA request */ +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + ARM GAS /tmp/ccH6KUTS.s page 34 + + +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channel */ +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group5 +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time One Pulse functions +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer One Pulse functions ##### +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM One Pulse. +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM One Pulse. +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer One Pulse. +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer One Pulse. +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer One Pulse and enable interrupt. +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer One Pulse and disable interrupt. +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer One Pulse and enable DMA transfer. +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer One Pulse and disable DMA transfer. +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Time Base according to the specified +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and create the associated handle. +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM OnePulse handle +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OnePulseMode: Select the One pulse mode. +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) + ARM GAS /tmp/ccH6KUTS.s page 35 + + +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OPM_MODE(OnePulseMode)); +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OnePulse_MspInit(htim); +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Time base in the One Pulse Mode */ +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the OPM Bit */ +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CR1 &= ~TIM_CR1_OPM; +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the OPM Mode */ +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CR1 |= OnePulseMode; +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM One Pulse +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM One Pulse handle +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +1959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OnePulse_MspDeInit(htim); +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 36 + + +1973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM One Pulse MSP. +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +1985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_OnePulse_MspInit could be implemented in the user file +1994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +1998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM One Pulse MSP. +1999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +2001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation. +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OutputChannel : TIM Channels to be enabled. +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter is not used since both channels TIM_CHANNEL_1 and +2017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * TIM_CHANNEL_2 are automatically selected. +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ + ARM GAS /tmp/ccH6KUTS.s page 37 + + +2030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation. +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OutputChannel : TIM Channels to be disable. +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation in interrupt mode. +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OutputChannel: TIM Channels to be enabled. +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + ARM GAS /tmp/ccH6KUTS.s page 38 + + +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation in interrupt mode. +2100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OutputChannel: TIM Channels to be enabled. +2102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +2114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group6 +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Encoder functions +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +2137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Timer Encoder functions ##### +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Initialize and configure the TIM Encoder. + ARM GAS /tmp/ccH6KUTS.s page 39 + + +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) De-initialize the TIM Encoder. +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Encoder. +2146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Encoder. +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Encoder and enable interrupt. +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Encoder and disable interrupt. +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Start the Timer Encoder and enable DMA transfer. +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Stop the Timer Encoder and disable DMA transfer. +2151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +2153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface and create the associated handle. +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Encoder Interface handle +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sConfig: TIM Encoder Interface configuration structure +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim == NULL) +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); +2176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim->Init.Period)); +2185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); +2186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(htim->State == HAL_TIM_STATE_RESET) +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +2190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +2191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Encoder_MspInit(htim); +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TIM state */ +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_BUSY; +2198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the SMS bits */ +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; + ARM GAS /tmp/ccH6KUTS.s page 40 + + +2201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Time base in the Encoder Mode */ +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +2204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +2207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +2209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; +2210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCER register value */ +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = htim->Instance->CCER; +2213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the encoder Mode */ +2215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= sConfig->EncoderMode; +2216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Capture Compare 1 and the Capture Compare 2 as input */ +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); +2220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ +2222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); +2223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); +2225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the TI1 and the TI2 Polarities */ +2228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); +2231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +2234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +2236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; +2237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCER */ +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCER = tmpccer; +2240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Initialize the TIM state*/ +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes the TIM Encoder interface +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Encoder handle +2250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + ARM GAS /tmp/ccH6KUTS.s page 41 + + +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +2263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_Encoder_MspDeInit(htim); +2264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change TIM state */ +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +2267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Release Lock */ +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +2270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface MSP. +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +2279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +2284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_Encoder_MspInit could be implemented in the user file +2287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief DeInitializes TIM Encoder Interface MSP. +2293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +2297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +2300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_Encoder_MspDeInit could be implemented in the user file +2303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface. +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +2310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +2314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status + ARM GAS /tmp/ccH6KUTS.s page 42 + + +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +2317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the encoder interface channels */ +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +2323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +2325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +2330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default : +2335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +2342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface. +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +2352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +2356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +2365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +2366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +2368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 43 + + +2372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +2373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default : +2378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in interrupt mode. +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +2395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +2399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the encoder interface channels */ +2407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the capture compare Interrupts 1 and/or 2 */ +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +2409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +2411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +2414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +2417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +2420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default : +2423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +2428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + ARM GAS /tmp/ccH6KUTS.s page 44 + + +2429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +2433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in interrupt mode. +2441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be disabled. +2443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +2447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +2455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +2456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(Channel == TIM_CHANNEL_1) +2457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 */ +2461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +2462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if(Channel == TIM_CHANNEL_2) +2464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare Interrupts 2 */ +2468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +2469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 and 2 */ +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +2478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +2481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ +2484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 45 + + +2486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in DMA mode. +2492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +2494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected +2498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData1: The destination Buffer address for IC1. +2499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param pData2: The destination Buffer address for IC2. +2500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Length: The length of data to be transferred from TIM peripheral to memory. +2501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD +2504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) +2509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; +2511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) +2513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) +2515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +2517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +2525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +2527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +2529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +2530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +2532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +2533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +2535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pDat +2536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +2538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +2539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +2541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 46 + + +2543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +2544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +2549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +2551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +2552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +2554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; +2555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +2556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData +2557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +2559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +2560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +2562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +2565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_ALL: +2570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +2572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +2573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +2575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +2576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +2578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData +2579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +2581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +2582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +2585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +2587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData +2588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Peripheral */ +2590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare channel */ +2593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +2597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +2598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +2599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + ARM GAS /tmp/ccH6KUTS.s page 47 + + +2600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +2604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in DMA mode. +2612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +2614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +2618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +2621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +2626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +2627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(Channel == TIM_CHANNEL_1) +2628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 */ +2632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +2633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if(Channel == TIM_CHANNEL_2) +2635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare DMA Request 2 */ +2639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +2640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 and 2 */ +2647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +2648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +2649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Peripheral */ +2652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the htim state */ +2655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 48 + + +2657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +2658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +2663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group7 +2666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief IRQ handler management +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +2668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +2669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### IRQ handler management ##### +2671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +2673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides Timer IRQ handler function. +2674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +2676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +2677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief This function handles TIM interrupts requests. +2680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM handle +2681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +2682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +2684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Capture compare 1 event */ +2686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) +2687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) +2689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); +2692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +2693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ +2695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) +2696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +2698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Output compare event */ +2700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +2703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +2704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Capture compare 2 event */ +2710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) +2711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) +2713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 49 + + +2714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); +2715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +2716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ +2717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) +2718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +2720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Output compare event */ +2722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +2725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +2726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Capture compare 3 event */ +2731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) +2732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) +2734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +2737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ +2738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) +2739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +2741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Output compare event */ +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +2746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +2747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Capture compare 4 event */ +2752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) +2753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) +2755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); +2757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +2758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ +2759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) +2760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +2762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Output compare event */ +2764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +2767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +2768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 50 + + +2771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TIM Update event */ +2773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) +2774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) +2776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +2778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); +2779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TIM Trigger detection event */ +2782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) +2783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) +2785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +2787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); +2788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +2794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group8 +2797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Peripheral Control functions +2798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +2799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +2800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Peripheral Control functions ##### +2802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +2803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +2804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides functions allowing to: +2805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. +2806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Configure External Clock source. +2807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Configure Master and the Slave synchronization. +2808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Configure the DMA Burst Mode. +2809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +2811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +2812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Output Compare Channels according to the specified +2815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. +2816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sConfig: TIM Output Compare configuration structure +2818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be configure. +2819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, ui +2827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 51 + + +2828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +2830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); +2831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); +2832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Process lock */ +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +2835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +2839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +2841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +2843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the TIM Channel 1 in Output Compare */ +2844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); +2845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +2849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the TIM Channel 2 in Output Compare */ +2852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); +2853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +2857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +2859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the TIM Channel 3 in Output Compare */ +2860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); +2861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +2865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +2867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the TIM Channel 4 in Output Compare */ +2868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); +2869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +2873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +2874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +2878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Channels according to the specified +2884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_IC_InitTypeDef. + ARM GAS /tmp/ccH6KUTS.s page 52 + + +2885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sConfig: TIM Input Capture configuration structure +2887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +2888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, ui +2896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +2899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); +2900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); +2901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); +2902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); +2903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +2905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +2909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TI1 Configuration */ +2911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, +2912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, +2913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, +2914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICFilter); +2915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +2917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; +2918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the IC1PSC value */ +2920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->ICPrescaler; +2921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +2923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TI2 Configuration */ +2925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +2926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, +2928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, +2929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, +2930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICFilter); +2931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; +2934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the IC2PSC value */ +2936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); +2937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_3) +2939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TI3 Configuration */ +2941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + ARM GAS /tmp/ccH6KUTS.s page 53 + + +2942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI3_SetConfig(htim->Instance, +2944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, +2945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, +2946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICFilter); +2947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC3PSC Bits */ +2949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; +2950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the IC3PSC value */ +2952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->ICPrescaler; +2953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +2955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* TI4 Configuration */ +2957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +2958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI4_SetConfig(htim->Instance, +2960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, +2961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, +2962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICFilter); +2963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC4PSC Bits */ +2965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; +2966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the IC4PSC value */ +2968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); +2969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +2974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +2976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +2977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +2979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM PWM channels according to the specified +2980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. +2981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +2982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sConfig: TIM PWM configuration structure +2983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channel to be configured. +2984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +2985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +2990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +2991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, u +2992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +2993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +2994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +2995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +2996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +2997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); +2998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + ARM GAS /tmp/ccH6KUTS.s page 54 + + +2999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); +3000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +3004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +3006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Channel 1 in PWM mode */ +3009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); +3010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Preload enable bit for channel1 */ +3012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; +3013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Output Fast mode */ +3015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; +3016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; +3017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +3021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Channel 2 in PWM mode */ +3024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); +3025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Preload enable bit for channel2 */ +3027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; +3028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Output Fast mode */ +3030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; +3031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; +3032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +3036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +3038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Channel 3 in PWM mode */ +3039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); +3040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Preload enable bit for channel3 */ +3042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; +3043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Output Fast mode */ +3045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; +3046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; +3047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +3051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +3053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Channel 4 in PWM mode */ +3054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); +3055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 55 + + +3056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Preload enable bit for channel4 */ +3057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; +3058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the Output Fast mode */ +3060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; +3061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; +3062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Channels according to the specified +3078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * parameters in the TIM_OnePulse_InitTypeDef. +3079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sConfig: TIM One Pulse configuration structure +3081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OutputChannel: TIM Channels to be enabled. +3082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param InputChannel: TIM Channels to be enabled. +3086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef +3092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC_InitTypeDef temp1; +3094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); +3097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); +3098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(OutputChannel != InputChannel) +3100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Extract the Ouput compare configuration from sConfig structure */ +3106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** temp1.OCMode = sConfig->OCMode; +3107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; +3108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; +3109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (OutputChannel) +3111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: + ARM GAS /tmp/ccH6KUTS.s page 56 + + +3113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, &temp1); +3117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +3120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, &temp1); +3124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (InputChannel) +3130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +3132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, +3136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +3137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +3139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; +3140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Trigger source */ +3142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +3143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; +3144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Slave Mode */ +3146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; +3147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; +3148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +3151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, +3155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +3156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +3158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; +3159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Trigger source */ +3161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +3162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; +3163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Slave Mode */ +3165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; +3166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; +3167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 57 + + +3170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +3183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral +3188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. +3190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameters can be on of the following values: +3191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +3192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +3193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +3194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +3195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_SR +3196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +3197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +3198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +3199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +3200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +3201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +3202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +3203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +3204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +3205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +3206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +3207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_DCR +3208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstRequestSrc: TIM DMA Request sources. +3209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameters can be on of the following values: +3210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +3211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +3212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +3213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +3214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +3215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +3216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstBuffer: The Buffer address. +3217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstLength: DMA Burst length. This parameter can be one value +3218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS . +3219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, u +3222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t* BurstBuffer, uint32_t BurstLength) +3223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +3226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + ARM GAS /tmp/ccH6KUTS.s page 58 + + +3227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +3228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +3229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) +3231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; +3233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) +3235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((BurstBuffer == 0U ) && (BurstLength > 0U)) +3237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +3239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch(BurstRequestSrc) +3246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_UPDATE: +3248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; +3251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; +3254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Insta +3257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC1: +3260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; +3263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +3266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance +3269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: +3272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; +3275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +3278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance +3281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: + ARM GAS /tmp/ccH6KUTS.s page 59 + + +3284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; +3287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +3290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance +3293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: +3296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; +3299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +3302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance +3305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: +3308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; +3311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; +3314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Inst +3317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* configure the DMA Burst Mode */ +3323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->DCR = BurstBaseAddress | BurstLength; +3324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM DMA Request */ +3326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); +3327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +3331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stops the TIM DMA Burst mode +3336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstRequestSrc: TIM DMA Request sources to disable +3338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) + ARM GAS /tmp/ccH6KUTS.s page 60 + + +3341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +3344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA channel) */ +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch(BurstRequestSrc) +3347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_UPDATE: +3349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); +3351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC1: +3354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); +3356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: +3359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); +3361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: +3364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); +3366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: +3369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); +3371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: +3374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); +3376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +3382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); +3383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +3385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory +3390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. +3392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameters can be on of the following values: +3393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +3394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +3395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +3396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +3397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_SR + ARM GAS /tmp/ccH6KUTS.s page 61 + + +3398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +3399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +3400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +3401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +3402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +3403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +3404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +3405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +3406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +3407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +3408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +3409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMABASE_DCR +3410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstRequestSrc: TIM DMA Request sources. +3411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameters can be on of the following values: +3412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +3413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +3414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +3415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +3416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +3417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +3418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstBuffer: The Buffer address. +3419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstLength: DMA Burst length. This parameter can be one value +3420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS . +3421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, ui +3424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t *BurstBuffer, uint32_t BurstLength) +3425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +3428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); +3429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +3430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +3431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((htim->State == HAL_TIM_STATE_BUSY)) +3433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_BUSY; +3435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if((htim->State == HAL_TIM_STATE_READY)) +3437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if((BurstBuffer == 0U ) && (BurstLength > 0U)) +3439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_ERROR; +3441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch(BurstRequestSrc) +3448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_UPDATE: +3450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; +3453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ + ARM GAS /tmp/ccH6KUTS.s page 62 + + +3455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; +3456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +3459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC1: +3462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +3465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +3468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)Burst +3471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: +3474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +3477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +3480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)Burst +3483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: +3486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; +3489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +3492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)Burst +3495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: +3498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ +3500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; +3501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +3504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)Burst +3507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: +3510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA Period elapsed callback */ + ARM GAS /tmp/ccH6KUTS.s page 63 + + +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; +3513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the DMA error callback */ +3515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; +3516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ +3518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +3519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* configure the DMA Burst Mode */ +3526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->DCR = BurstBaseAddress | BurstLength; +3527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM DMA Request */ +3529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); +3530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +3534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Stop the DMA burst reading +3539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param BurstRequestSrc: TIM DMA Request sources to disable. +3541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +3544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +3547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA channel) */ +3549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch(BurstRequestSrc) +3550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_UPDATE: +3552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); +3554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC1: +3557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); +3559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: +3562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); +3564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: +3567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + ARM GAS /tmp/ccH6KUTS.s page 64 + + +3569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: +3572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); +3574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: +3577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); +3579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +3586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); +3587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +3589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Generate a software event +3594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param EventSource: specifies the event source. +3596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EventSource_Update: Timer update Event source +3598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source +3599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source +3600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source +3601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source +3602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source +3603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @note TIM6 can only generate an update event. +3604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +3608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +3611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_EVENT_SOURCE(EventSource)); +3612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Process Locked */ +3614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the TIM state */ +3617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the event sources */ +3620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->EGR = EventSource; +3621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Change the TIM state */ +3623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); + ARM GAS /tmp/ccH6KUTS.s page 65 + + +3626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return function status */ +3628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configures the OCRef clear feature +3633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that +3635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * contains the OCREF clear feature and parameters for the TIM peripheral. +3636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: specifies the TIM Channel. +3637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +3641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +3642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * s +3645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +3649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); +3650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); +3651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); +3652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); +3653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Process Locked */ +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) +3660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +3662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, +3663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClearInputConfig->ClearInputPolarity, +3664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClearInputConfig->ClearInputFilter); +3665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the OCREF clear selection bit */ +3667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SMCR_OCCS; +3668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +3671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +3673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(sClearInputConfig->ClearInputState != RESET) +3675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Ocref clear feature for Channel 1 */ +3677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; +3678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Ocref clear feature for Channel 1 */ +3682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + ARM GAS /tmp/ccH6KUTS.s page 66 + + +3683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +3687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(sClearInputConfig->ClearInputState != RESET) +3690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Ocref clear feature for Channel 2 */ +3692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; +3693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Ocref clear feature for Channel 2 */ +3697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; +3698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +3702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +3704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(sClearInputConfig->ClearInputState != RESET) +3705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Ocref clear feature for Channel 3 */ +3707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; +3708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Ocref clear feature for Channel 3 */ +3712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; +3713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +3717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +3719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(sClearInputConfig->ClearInputState != RESET) +3720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Ocref clear feature for Channel 4 */ +3722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; +3723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +3725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Ocref clear feature for Channel 4 */ +3727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; +3728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; + ARM GAS /tmp/ccH6KUTS.s page 67 + + +3740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configures the clock source to be used +3744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that +3746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * contains the clock source information for the TIM peripheral. +3747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sCloc +3750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; +3752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Process Locked */ +3754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the clock source */ +3759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); +3760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ +3762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +3763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); +3764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); +3765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +3766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (sClockSourceConfig->ClockSource) +3768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_INTERNAL: +3770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +3772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable slave mode to clock the prescaler directly with the internal clock */ +3773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; +3774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE1: +3778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); +3780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); +3781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +3782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +3783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the ETR Clock source */ +3784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +3785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, +3786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +3787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +3788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +3789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +3790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the SMS and TS Bits */ +3791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); +3792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the External clock mode1 and the ETRF trigger */ +3793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); +3794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ +3795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +3796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 68 + + +3797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE2: +3800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); +3802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); +3803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +3804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +3805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the ETR Clock source */ +3806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +3807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, +3808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +3809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +3810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the External clock mode2 */ +3811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SMCR_ECE; +3812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1: +3816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +3819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +3820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +3821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +3822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +3823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); +3824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI2: +3827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +3830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +3831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, +3832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +3833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +3834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); +3835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1ED: +3838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +3840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +3841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +3842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +3843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +3844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +3845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); +3846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR0: +3849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); +3852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + ARM GAS /tmp/ccH6KUTS.s page 69 + + +3854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR1: +3855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); +3858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR2: +3861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); +3864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR3: +3867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +3869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); +3870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +3874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +3875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Selects the signal connected to the TI1 input: direct from CH1_input +3885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * or a XOR combination between CH1_input, CH2_input & CH3_input +3886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TI1_Selection: Indicate whether or not channel 1 is connected to the +3888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * output of a XOR gate. +3889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input +3891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 +3892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * pins are connected to the TI1 input (XOR combination) +3893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +3896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; +3898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); +3901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); +3902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +3904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 = htim->Instance->CR2; +3905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TI1 selection */ +3907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_TI1S; +3908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the the TI1 selection */ +3910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 |= TI1_Selection; + ARM GAS /tmp/ccH6KUTS.s page 70 + + +3911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMxCR2 */ +3913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CR2 = tmpcr2; +3914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configures the TIM in Slave mode +3920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that +3922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +3923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * timer input or external trigger input) and the ) and the Slave +3924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * mode (Disable, Reset, Gated, Trigger, External clock mode 1). +3925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDe +3928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +3930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +3931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +3932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +3933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configuration in slave mode */ +3939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); +3940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable Trigger Interrupt */ +3942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); +3943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable Trigger DMA request */ +3945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); +3946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the new state */ +3948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configures the TIM in Slave mode in interrupt mode +3957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle. +3958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that +3959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +3960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * timer input or external trigger input) and the ) and the Slave +3961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * mode (Disable, Reset, Gated, Trigger, External clock mode 1). +3962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL status +3963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +3964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, +3965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_SlaveConfigTypeDef * sSlaveConfig) +3966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +3967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccH6KUTS.s page 71 + + +3968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +3969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +3970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +3971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +3973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); +3977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable Trigger Interrupt */ +3979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); +3980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable Trigger DMA request */ +3982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); +3983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +3987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return HAL_OK; +3989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +3990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +3991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +3992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Read the captured value from Capture Compare unit +3993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +3994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: TIM Channels to be enabled. +3995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +3996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +3999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval Captured value +4001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +4003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpreg = 0U; +4005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); +4007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (Channel) +4009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_1: +4011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return the capture 1 value */ +4016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpreg = htim->Instance->CCR1; +4017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +4019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: +4021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 72 + + +4025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return the capture 2 value */ +4026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpreg = htim->Instance->CCR2; +4027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +4029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_3: +4032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return the capture 3 value */ +4037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpreg = htim->Instance->CCR3; +4038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +4040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_4: +4043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Return the capture 4 value */ +4048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpreg = htim->Instance->CCR4; +4049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +4051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +4054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +4055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_UNLOCK(htim); +4058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return tmpreg; +4059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +4063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group9 +4066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM Callbacks functions +4067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +4068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +4069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +4070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### TIM Callbacks functions ##### +4071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +4072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +4073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This section provides TIM callback functions: +4074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Timer Period elapsed callback +4075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Timer Output Compare callback +4076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Timer Input capture callback +4077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Timer Trigger callback +4078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** (+) Timer Error callback +4079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +4081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ + ARM GAS /tmp/ccH6KUTS.s page 73 + + +4082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Period elapsed callback in non blocking mode +4086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +4090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +4095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file +4096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Output Compare callback in non blocking mode +4101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +4105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +4110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file +4111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Input Capture callback in non blocking mode +4115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM IC handle +4116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +4119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +4124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the __HAL_TIM_IC_CaptureCallback could be implemented in the user file +4125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief PWM Pulse finished callback in non blocking mode +4130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +4134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, + ARM GAS /tmp/ccH6KUTS.s page 74 + + +4139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file +4140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Hall Trigger detection callback in non blocking mode +4145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +4149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +4154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_TriggerCallback could be implemented in the user file +4155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Timer error callback in non blocking mode +4160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +4164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +4166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** UNUSED(htim); +4167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* NOTE : This function Should not be modified, when the callback is needed, +4169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** the HAL_TIM_ErrorCallback could be implemented in the user file +4170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +4175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Exported_Functions_Group10 +4178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Peripheral State functions +4179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * +4180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @verbatim +4181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +4182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ##### Peripheral State functions ##### +4183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** ============================================================================== +4184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** [..] +4185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** This subsection permits to get in run-time the status of the peripheral +4186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** and the data flow. +4187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** @endverbatim +4189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +4190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM Base state +4194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state + ARM GAS /tmp/ccH6KUTS.s page 75 + + +4196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +4198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM OC state +4204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM Ouput Compare handle +4205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state +4206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +4208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM PWM state +4214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state +4216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +4218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM Input Capture state +4224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state +4226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +4228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM One Pulse Mode state +4234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim: TIM OPM handle +4235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state +4236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +4238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Return the TIM Encoder Mode state +4244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval HAL state +4246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +4248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; +4250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 76 + + +4253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM DMA error callback +4256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +4257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * the configuration information for the specified DMA module. +4258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** void TIM_DMAError(DMA_HandleTypeDef *hdma) +4261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +4263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +4265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_ErrorCallback(htim); +4267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM DMA Delay Pulse complete callback. +4271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains +4272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * the configuration information for the specified DMA module. +4273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +4276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +4278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +4280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +4282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +4284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +4286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +4288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +4290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +4292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +4294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +4296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +4298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +4300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM DMA Capture complete callback. +4303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains +4304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * the configuration information for the specified DMA module. +4305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +4308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ARM GAS /tmp/ccH6KUTS.s page 77 + + +4310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +4312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +4314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +4316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +4318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +4320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +4322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +4324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +4326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +4328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +4331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +4333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +4338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @} +4342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /*************************************************************/ +4344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Private functions */ +4345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /*************************************************************/ +4346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** @addtogroup TIM_Private TIM Private +4348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @{ +4349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM DMA Period Elapse complete callback. +4352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param hdma : pointer to DMA handle. +4353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +4356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +4358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +4360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); +4362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief TIM DMA Trigger callback. + ARM GAS /tmp/ccH6KUTS.s page 78 + + +4367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param hdma : pointer to DMA handle. +4368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +4371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +4373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->State= HAL_TIM_STATE_READY; +4375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); +4377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Base configuration +4381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx : TIM peripheral +4382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Structure : TIM Base configuration structure +4383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +4386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 25 .loc 1 4386 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: +4387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr1 = 0U; +4388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr1 = TIMx->CR1; + 31 .loc 1 4388 0 + 32 0000 0368 ldr r3, [r0] + 33 .LVL1: +4389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set TIM Time Base Unit parameters ---------------------------------------*/ +4391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) + 34 .loc 1 4391 0 + 35 0002 8022 movs r2, #128 + 36 0004 D205 lsls r2, r2, #23 + 37 0006 9042 cmp r0, r2 + 38 0008 08D0 beq .L2 + 39 .loc 1 4391 0 is_stmt 0 discriminator 2 + 40 000a 134A ldr r2, .L6 + 41 000c 9042 cmp r0, r2 + 42 000e 05D0 beq .L2 + 43 .loc 1 4391 0 discriminator 4 + 44 0010 124A ldr r2, .L6+4 + 45 0012 9042 cmp r0, r2 + 46 0014 02D0 beq .L2 + 47 .loc 1 4391 0 discriminator 6 + 48 0016 124A ldr r2, .L6+8 + 49 0018 9042 cmp r0, r2 + 50 001a 03D1 bne .L3 + 51 .L2: +4392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Counter Mode */ +4394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 52 .loc 1 4394 0 is_stmt 1 + 53 001c 7022 movs r2, #112 + ARM GAS /tmp/ccH6KUTS.s page 79 + + + 54 001e 9343 bics r3, r2 + 55 .LVL2: +4395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr1 |= Structure->CounterMode; + 56 .loc 1 4395 0 + 57 0020 4A68 ldr r2, [r1, #4] + 58 0022 1343 orrs r3, r2 + 59 .LVL3: + 60 .L3: +4396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) + 61 .loc 1 4398 0 + 62 0024 8022 movs r2, #128 + 63 0026 D205 lsls r2, r2, #23 + 64 0028 9042 cmp r0, r2 + 65 002a 08D0 beq .L4 + 66 .loc 1 4398 0 is_stmt 0 discriminator 2 + 67 002c 0A4A ldr r2, .L6 + 68 002e 9042 cmp r0, r2 + 69 0030 05D0 beq .L4 + 70 .loc 1 4398 0 discriminator 4 + 71 0032 0A4A ldr r2, .L6+4 + 72 0034 9042 cmp r0, r2 + 73 0036 02D0 beq .L4 + 74 .loc 1 4398 0 discriminator 6 + 75 0038 094A ldr r2, .L6+8 + 76 003a 9042 cmp r0, r2 + 77 003c 03D1 bne .L5 + 78 .L4: +4399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the clock division */ +4401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr1 &= ~TIM_CR1_CKD; + 79 .loc 1 4401 0 is_stmt 1 + 80 003e 094A ldr r2, .L6+12 + 81 0040 1340 ands r3, r2 + 82 .LVL4: +4402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr1 |= (uint32_t)Structure->ClockDivision; + 83 .loc 1 4402 0 + 84 0042 CA68 ldr r2, [r1, #12] + 85 0044 1343 orrs r3, r2 + 86 .LVL5: + 87 .L5: +4403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CR1 = tmpcr1; + 88 .loc 1 4405 0 + 89 0046 0360 str r3, [r0] +4406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Autoreload value */ +4408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->ARR = (uint32_t)Structure->Period ; + 90 .loc 1 4408 0 + 91 0048 8B68 ldr r3, [r1, #8] + 92 .LVL6: + 93 004a C362 str r3, [r0, #44] + 94 .LVL7: +4409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Prescaler value */ + ARM GAS /tmp/ccH6KUTS.s page 80 + + +4411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->PSC = (uint32_t)Structure->Prescaler; + 95 .loc 1 4411 0 + 96 004c 0B68 ldr r3, [r1] + 97 004e 8362 str r3, [r0, #40] +4412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Generate an update event to reload the Prescaler value immediatly */ +4414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->EGR = TIM_EGR_UG; + 98 .loc 1 4414 0 + 99 0050 0123 movs r3, #1 + 100 0052 4361 str r3, [r0, #20] +4415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 101 .loc 1 4415 0 + 102 @ sp needed + 103 0054 7047 bx lr + 104 .L7: + 105 0056 C046 .align 2 + 106 .L6: + 107 0058 00040040 .word 1073742848 + 108 005c 00080140 .word 1073809408 + 109 0060 00140140 .word 1073812480 + 110 0064 FFFCFFFF .word -769 + 111 .cfi_endproc + 112 .LFE130: + 114 .section .text.TIM_TI1_SetConfig,"ax",%progbits + 115 .align 1 + 116 .syntax unified + 117 .code 16 + 118 .thumb_func + 119 .fpu softvfp + 121 TIM_TI1_SetConfig: + 122 .LFB135: +4416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Ouput Compare 1 configuration +4419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OC_Config: The ouput configuration structure +4421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +4424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmrx = 0U; +4426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; +4428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +4430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; +4431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCER register value */ +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +4435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 = TIMx->CR2; +4436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +4438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; +4439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +4441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC1M; + ARM GAS /tmp/ccH6KUTS.s page 81 + + +4442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC1S; +4443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ +4444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; +4445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Polarity level */ +4447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1P; +4448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ +4449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= OC_Config->OCPolarity; +4450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CR2 */ +4452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CR2 = tmpcr2; +4453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +4455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; +4456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Capture Compare Register value */ +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCR1 = OC_Config->Pulse; +4459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCER */ +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Ouput Compare 2 configuration +4466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OC_Config: The ouput configuration structure +4468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +4471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmrx = 0U; +4473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; +4475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +4477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; +4478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCER register value */ +4480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +4482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 = TIMx->CR2; +4483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +4485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; +4486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +4488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC2M; +4489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC2S; +4490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); +4493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Polarity level */ +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2P; +4496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ +4497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 4U); +4498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 82 + + +4499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CR2 */ +4500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CR2 = tmpcr2; +4501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; +4504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Capture Compare Register value */ +4506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCR2 = OC_Config->Pulse; +4507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCER */ +4509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Ouput Compare 3 configuration +4514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OC_Config: The ouput configuration structure +4516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +4519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmrx = 0U; +4521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; +4523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC2E Bit */ +4525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; +4526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCER register value */ +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +4530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 = TIMx->CR2; +4531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +4533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; +4534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +4536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC3M; +4537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC3S; +4538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ +4539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; +4540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Polarity level */ +4542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3P; +4543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ +4544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 8U); +4545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CR2 */ +4547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CR2 = tmpcr2; +4548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR2 */ +4550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; +4551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Capture Compare Register value */ +4553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCR3 = OC_Config->Pulse; +4554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCER */ + ARM GAS /tmp/ccH6KUTS.s page 83 + + +4556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Time Ouput Compare 4 configuration +4561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param OC_Config: The ouput configuration structure +4563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +4566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmrx = 0U; +4568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; +4570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +4572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; +4573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCER register value */ +4575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +4577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpcr2 = TIMx->CR2; +4578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +4580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; +4581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +4583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC4M; +4584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC4S; +4585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ +4587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); +4588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Output Polarity level */ +4590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC4P; +4591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ +4592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 12U); +4593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CR2 */ +4595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CR2 = tmpcr2; +4596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR2 */ +4598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; +4599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Capture Compare Register value */ +4601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCR4 = OC_Config->Pulse; +4602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCER */ +4604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the TI1 as Input. +4609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +4610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising + ARM GAS /tmp/ccH6KUTS.s page 84 + + +4613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICSelection: specifies the input to be used. +4616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. +4618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. +4619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. +4620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +4622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +4625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t TIM_ICFilter) +4626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 123 .loc 1 4626 0 + 124 .cfi_startproc + 125 @ args = 0, pretend = 0, frame = 0 + 126 @ frame_needed = 0, uses_anonymous_args = 0 + 127 .LVL8: + 128 0000 70B5 push {r4, r5, r6, lr} + 129 .LCFI0: + 130 .cfi_def_cfa_offset 16 + 131 .cfi_offset 4, -16 + 132 .cfi_offset 5, -12 + 133 .cfi_offset 6, -8 + 134 .cfi_offset 14, -4 + 135 .LVL9: +4627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +4628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +4631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 136 .loc 1 4631 0 + 137 0002 046A ldr r4, [r0, #32] + 138 0004 0125 movs r5, #1 + 139 0006 AC43 bics r4, r5 + 140 0008 0462 str r4, [r0, #32] +4632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 141 .loc 1 4632 0 + 142 000a 8469 ldr r4, [r0, #24] + 143 .LVL10: +4633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 144 .loc 1 4633 0 + 145 000c 056A ldr r5, [r0, #32] + 146 .LVL11: +4634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Input */ +4636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + 147 .loc 1 4636 0 + 148 000e 8026 movs r6, #128 + 149 0010 F605 lsls r6, r6, #23 + 150 0012 B042 cmp r0, r6 + 151 0014 0ED0 beq .L9 + 152 .loc 1 4636 0 is_stmt 0 discriminator 2 + 153 0016 0F4E ldr r6, .L11 + 154 0018 B042 cmp r0, r6 + 155 001a 0BD0 beq .L9 + ARM GAS /tmp/ccH6KUTS.s page 85 + + + 156 .loc 1 4636 0 discriminator 4 + 157 001c 0E4E ldr r6, .L11+4 + 158 001e B042 cmp r0, r6 + 159 0020 08D0 beq .L9 + 160 .loc 1 4636 0 discriminator 6 + 161 0022 0E4E ldr r6, .L11+8 + 162 0024 B042 cmp r0, r6 + 163 0026 05D0 beq .L9 +4637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC1S; +4639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; +4640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** else +4642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC1S; + 164 .loc 1 4643 0 is_stmt 1 + 165 0028 0322 movs r2, #3 + 166 .LVL12: + 167 002a 9443 bics r4, r2 + 168 .LVL13: + 169 002c 2200 movs r2, r4 + 170 .LVL14: +4644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= TIM_CCMR1_CC1S_0; + 171 .loc 1 4644 0 + 172 002e 0124 movs r4, #1 + 173 0030 2243 orrs r2, r4 + 174 .LVL15: + 175 0032 02E0 b .L10 + 176 .LVL16: + 177 .L9: +4638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; + 178 .loc 1 4638 0 + 179 0034 0326 movs r6, #3 + 180 0036 B443 bics r4, r6 + 181 .LVL17: +4639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 182 .loc 1 4639 0 + 183 0038 2243 orrs r2, r4 + 184 .LVL18: + 185 .L10: +4645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + 186 .loc 1 4648 0 + 187 003a F024 movs r4, #240 + 188 003c A243 bics r2, r4 + 189 .LVL19: +4649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + 190 .loc 1 4649 0 + 191 003e 1C01 lsls r4, r3, #4 + 192 0040 FF23 movs r3, #255 + 193 .LVL20: + 194 0042 2340 ands r3, r4 + 195 0044 1A43 orrs r2, r3 + 196 .LVL21: +4650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 86 + + +4651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +4652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 197 .loc 1 4652 0 + 198 0046 0A24 movs r4, #10 + 199 0048 A543 bics r5, r4 + 200 .LVL22: +4653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + 201 .loc 1 4653 0 + 202 004a 0C40 ands r4, r1 + 203 004c 2C43 orrs r4, r5 + 204 .LVL23: +4654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +4656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; + 205 .loc 1 4656 0 + 206 004e 8261 str r2, [r0, #24] +4657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 207 .loc 1 4657 0 + 208 0050 0462 str r4, [r0, #32] +4658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 209 .loc 1 4658 0 + 210 @ sp needed + 211 .LVL24: + 212 0052 70BD pop {r4, r5, r6, pc} + 213 .L12: + 214 .align 2 + 215 .L11: + 216 0054 00040040 .word 1073742848 + 217 0058 00080140 .word 1073809408 + 218 005c 00140140 .word 1073812480 + 219 .cfi_endproc + 220 .LFE135: + 222 .section .text.TIM_SlaveTimer_SetConfig,"ax",%progbits + 223 .align 1 + 224 .syntax unified + 225 .code 16 + 226 .thumb_func + 227 .fpu softvfp + 229 TIM_SlaveTimer_SetConfig: + 230 .LFB144: +4659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI1. +4662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +4663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising +4666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +4670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil +4673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +4675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; + ARM GAS /tmp/ccH6KUTS.s page 87 + + +4676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +4678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; +4680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; +4681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); +4685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +4687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); +4688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; +4689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +4691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; +4692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the TI2 as Input. +4697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising +4701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICSelection: specifies the input to be used. +4704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. +4706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. +4707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. +4708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +4710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +4713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t TIM_ICFilter) +4714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +4716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +4719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; +4720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; +4721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Input */ +4724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC2S; +4725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICSelection << 8U); +4726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; +4729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); +4730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +4732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + ARM GAS /tmp/ccH6KUTS.s page 88 + + +4733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); +4734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +4736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; +4737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI2. +4742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +4743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising +4746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +4750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil +4753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +4755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +4758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; +4759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; +4760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; +4764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 12U); +4765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +4767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); +4768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity << 4U); +4769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +4771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; +4772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the TI3 as Input. +4777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising +4781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICSelection: specifies the input to be used. +4784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. +4786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. +4787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. +4788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. + ARM GAS /tmp/ccH6KUTS.s page 89 + + +4790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +4793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t TIM_ICFilter) +4794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr2 = 0U; +4796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ +4799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; +4800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; +4801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; +4802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Input */ +4804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC3S; +4805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= TIM_ICSelection; +4806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC3F; +4809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); +4810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC3E Bit */ +4812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); +4813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); +4814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +4816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; +4817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; +4818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configure the TI4 as Input. +4822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICPolarity : The Input Polarity. +4824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Rising +4826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_Falling +4827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICPolarity_BothEdge +4828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICSelection: specifies the input to be used. +4829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. +4831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. +4832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. +4833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ICFilter: Specifies the Input Capture Filter. +4834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +4835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +4838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t TIM_ICFilter) +4839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr2 = 0U; +4841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +4844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; +4845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; +4846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + ARM GAS /tmp/ccH6KUTS.s page 90 + + +4847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Input */ +4849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC4S; +4850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= (TIM_ICSelection << 8U); +4851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +4853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC4F; +4854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); +4855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Polarity and set the CC4E Bit */ +4857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); +4858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); +4859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +4861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; +4862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer ; +4863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Selects the Input Trigger source +4867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param InputTriggerSource: The Input Trigger source. +4869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_ITR0: Internal Trigger 0 +4871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_ITR1: Internal Trigger 1 +4872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_ITR2: Internal Trigger 2 +4873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_ITR3: Internal Trigger 3 +4874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_TI1F_ED: TI1 Edge Detector +4875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 +4876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +4877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_TS_ETRF: External Trigger input +4878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +4881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; +4883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; +4886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; +4888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; +4890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; +4892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Configures the TIMx External Trigger (ETR). +4895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +4897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF. +4899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +4900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +4901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +4902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIM_ExtTRGPolarity: The external Trigger Polarity. +4903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: + ARM GAS /tmp/ccH6KUTS.s page 91 + + +4904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +4905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +4906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param ExtTRGFilter: External Trigger Filter. +4907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F +4908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +4911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +4912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; +4914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; +4916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the ETR Bits */ +4918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); +4919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Prescaler, the Filter value and the Polarity */ +4921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); +4922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ +4924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; +4925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Enables or disables the TIM Capture Compare Channel x. +4929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +4930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param Channel: specifies the TIM Channel +4931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be one of the following values: +4932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_Channel_1: TIM Channel 1 +4933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_Channel_2: TIM Channel 2 +4934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_Channel_3: TIM Channel 3 +4935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @arg TIM_Channel_4: TIM Channel 4 +4936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param ChannelState: specifies the TIM Channel CCxE bit new state. +4937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. +4938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +4941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmp = 0U; +4943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel)); +4946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmp = TIM_CCER_CC1E << Channel; +4948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the CCxE Bit */ +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~tmp; +4951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set or reset the CCxE Bit */ +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER |= (uint32_t)(ChannelState << Channel); +4954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +4955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** +4956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @brief Set the slave timer configuration. +4957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param htim : TIM handle +4958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that +4959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +4960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * timer input or external trigger input) and the ) and the Slave + ARM GAS /tmp/ccH6KUTS.s page 92 + + +4961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * mode (Disable, Reset, Gated, Trigger, External clock mode 1). +4962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** * @retval None +4963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** */ +4964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, +4965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_SlaveConfigTypeDef * sSlaveConfig) +4966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 231 .loc 1 4966 0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 0 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 .LVL25: + 236 0000 30B5 push {r4, r5, lr} + 237 .LCFI1: + 238 .cfi_def_cfa_offset 12 + 239 .cfi_offset 4, -12 + 240 .cfi_offset 5, -8 + 241 .cfi_offset 14, -4 + 242 .LVL26: +4967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; +4968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccmr1 = 0U; +4969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpccer = 0U; +4970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +4972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; + 243 .loc 1 4972 0 + 244 0002 0268 ldr r2, [r0] + 245 0004 9368 ldr r3, [r2, #8] + 246 .LVL27: +4973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the Trigger Selection Bits */ +4975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; + 247 .loc 1 4975 0 + 248 0006 7024 movs r4, #112 + 249 0008 A343 bics r3, r4 + 250 .LVL28: +4976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source */ +4977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->InputTrigger; + 251 .loc 1 4977 0 + 252 000a 4C68 ldr r4, [r1, #4] + 253 000c 2343 orrs r3, r4 + 254 .LVL29: +4978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the slave mode Bits */ +4980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_SMS; + 255 .loc 1 4980 0 + 256 000e 0724 movs r4, #7 + 257 0010 A343 bics r3, r4 + 258 .LVL30: +4981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the slave mode */ +4982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->SlaveMode; + 259 .loc 1 4982 0 + 260 0012 0C68 ldr r4, [r1] + 261 0014 2343 orrs r3, r4 + 262 .LVL31: +4983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ +4985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + ARM GAS /tmp/ccH6KUTS.s page 93 + + + 263 .loc 1 4985 0 + 264 0016 9360 str r3, [r2, #8] +4986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +4987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the trigger prescaler, filter, and polarity */ +4988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** switch (sSlaveConfig->InputTrigger) + 265 .loc 1 4988 0 + 266 0018 4B68 ldr r3, [r1, #4] + 267 .LVL32: + 268 001a 502B cmp r3, #80 + 269 001c 25D0 beq .L15 + 270 001e 10D9 bls .L20 + 271 0020 602B cmp r3, #96 + 272 0022 35D0 beq .L18 + 273 0024 702B cmp r3, #112 + 274 0026 0BD1 bne .L13 +4989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_ETRF: +4991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +4992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +4993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); +4994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); +4995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +4996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +4997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure the ETR Trigger source */ +4998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, + 275 .loc 1 4998 0 + 276 0028 0468 ldr r4, [r0] + 277 002a CA68 ldr r2, [r1, #12] + 278 .LVL33: + 279 002c 8868 ldr r0, [r1, #8] + 280 .LVL34: + 281 002e 0969 ldr r1, [r1, #16] + 282 .LVL35: + 283 .LBB162: + 284 .LBB163: +4915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 285 .loc 1 4915 0 + 286 0030 A368 ldr r3, [r4, #8] + 287 .LVL36: +4918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 288 .loc 1 4918 0 + 289 0032 214D ldr r5, .L21 + 290 0034 2B40 ands r3, r5 + 291 .LVL37: +4921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 292 .loc 1 4921 0 + 293 0036 0902 lsls r1, r1, #8 + 294 .LVL38: + 295 0038 0143 orrs r1, r0 + 296 003a 0A43 orrs r2, r1 + 297 .LVL39: + 298 003c 1343 orrs r3, r2 + 299 .LVL40: +4924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 300 .loc 1 4924 0 + 301 003e A360 str r3, [r4, #8] + 302 .LVL41: + ARM GAS /tmp/ccH6KUTS.s page 94 + + + 303 .L13: + 304 .LBE163: + 305 .LBE162: +4999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, +5000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +5001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +5002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_TI1F_ED: +5006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +5008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +5009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +5010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +5012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = htim->Instance->CCER; +5013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; +5014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; +5015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the filter */ +5017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; +5018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); +5019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +5021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; +5022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCER = tmpccer; +5023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_TI1FP1: +5028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +5030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +5031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +5032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +5033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure TI1 Filter and Polarity */ +5035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +5036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +5037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +5038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_TI2FP2: +5042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ +5044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +5046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +5047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Configure TI2 Filter and Polarity */ +5049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, +5050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +5051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +5052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 95 + + +5053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_ITR0: +5056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameter */ +5058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_ITR1: +5063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameter */ +5065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_ITR2: +5070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameter */ +5072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_TS_ITR3: +5077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { +5078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameter */ +5079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** +5083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: +5084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; +5085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } +5086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 306 .loc 1 5086 0 + 307 @ sp needed + 308 0040 30BD pop {r4, r5, pc} + 309 .LVL42: + 310 .L20: +4988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 311 .loc 1 4988 0 + 312 0042 402B cmp r3, #64 + 313 0044 FCD1 bne .L13 +5012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; + 314 .loc 1 5012 0 + 315 0046 0368 ldr r3, [r0] + 316 0048 1D6A ldr r5, [r3, #32] + 317 .LVL43: +5013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 318 .loc 1 5013 0 + 319 004a 1A6A ldr r2, [r3, #32] + 320 .LVL44: + 321 004c 0124 movs r4, #1 + 322 004e A243 bics r2, r4 + 323 0050 1A62 str r2, [r3, #32] +5014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 324 .loc 1 5014 0 + ARM GAS /tmp/ccH6KUTS.s page 96 + + + 325 0052 0468 ldr r4, [r0] + 326 0054 A369 ldr r3, [r4, #24] + 327 .LVL45: +5017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + 328 .loc 1 5017 0 + 329 0056 F022 movs r2, #240 + 330 0058 9343 bics r3, r2 + 331 .LVL46: + 332 005a 1A00 movs r2, r3 + 333 .LVL47: +5018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 334 .loc 1 5018 0 + 335 005c 0B69 ldr r3, [r1, #16] + 336 005e 1B01 lsls r3, r3, #4 + 337 0060 1343 orrs r3, r2 + 338 .LVL48: +5021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCER = tmpccer; + 339 .loc 1 5021 0 + 340 0062 A361 str r3, [r4, #24] +5022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 341 .loc 1 5022 0 + 342 0064 0368 ldr r3, [r0] + 343 .LVL49: + 344 0066 1D62 str r5, [r3, #32] + 345 .LVL50: +5025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 346 .loc 1 5025 0 + 347 0068 EAE7 b .L13 + 348 .LVL51: + 349 .L15: +5035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 350 .loc 1 5035 0 + 351 006a 0368 ldr r3, [r0] + 352 006c 8868 ldr r0, [r1, #8] + 353 .LVL52: + 354 006e 0C69 ldr r4, [r1, #16] + 355 .LVL53: + 356 .LBB164: + 357 .LBB165: +4678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 358 .loc 1 4678 0 + 359 0070 196A ldr r1, [r3, #32] + 360 .LVL54: +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 361 .loc 1 4679 0 + 362 0072 1A6A ldr r2, [r3, #32] + 363 .LVL55: + 364 0074 0125 movs r5, #1 + 365 0076 AA43 bics r2, r5 + 366 0078 1A62 str r2, [r3, #32] +4680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 367 .loc 1 4680 0 + 368 007a 9A69 ldr r2, [r3, #24] + 369 .LVL56: +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); + 370 .loc 1 4683 0 + 371 007c EF35 adds r5, r5, #239 + ARM GAS /tmp/ccH6KUTS.s page 97 + + + 372 007e AA43 bics r2, r5 + 373 .LVL57: +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 374 .loc 1 4684 0 + 375 0080 2401 lsls r4, r4, #4 + 376 .LVL58: + 377 0082 2243 orrs r2, r4 + 378 .LVL59: +4687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; + 379 .loc 1 4687 0 + 380 0084 0A24 movs r4, #10 + 381 0086 A143 bics r1, r4 + 382 .LVL60: +4688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 383 .loc 1 4688 0 + 384 0088 0143 orrs r1, r0 + 385 .LVL61: +4691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 386 .loc 1 4691 0 + 387 008a 9A61 str r2, [r3, #24] +4692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 388 .loc 1 4692 0 + 389 008c 1962 str r1, [r3, #32] + 390 008e D7E7 b .L13 + 391 .LVL62: + 392 .L18: + 393 .LBE165: + 394 .LBE164: +5049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 395 .loc 1 5049 0 + 396 0090 0368 ldr r3, [r0] + 397 0092 8868 ldr r0, [r1, #8] + 398 .LVL63: + 399 0094 0C69 ldr r4, [r1, #16] + 400 .LVL64: + 401 .LBB166: + 402 .LBB167: +4758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 403 .loc 1 4758 0 + 404 0096 1A6A ldr r2, [r3, #32] + 405 .LVL65: + 406 0098 1021 movs r1, #16 + 407 .LVL66: + 408 009a 8A43 bics r2, r1 + 409 009c 1A62 str r2, [r3, #32] +4759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 410 .loc 1 4759 0 + 411 009e 9969 ldr r1, [r3, #24] + 412 .LVL67: +4760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 413 .loc 1 4760 0 + 414 00a0 1A6A ldr r2, [r3, #32] + 415 .LVL68: +4763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 12U); + 416 .loc 1 4763 0 + 417 00a2 064D ldr r5, .L21+4 + 418 00a4 2940 ands r1, r5 + ARM GAS /tmp/ccH6KUTS.s page 98 + + + 419 .LVL69: +4764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 420 .loc 1 4764 0 + 421 00a6 2403 lsls r4, r4, #12 + 422 .LVL70: + 423 00a8 2143 orrs r1, r4 + 424 .LVL71: +4767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity << 4U); + 425 .loc 1 4767 0 + 426 00aa A024 movs r4, #160 + 427 00ac A243 bics r2, r4 + 428 .LVL72: +4768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 429 .loc 1 4768 0 + 430 00ae 0001 lsls r0, r0, #4 + 431 .LVL73: + 432 00b0 0243 orrs r2, r0 + 433 .LVL74: +4771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 434 .loc 1 4771 0 + 435 00b2 9961 str r1, [r3, #24] +4772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 436 .loc 1 4772 0 + 437 00b4 1A62 str r2, [r3, #32] + 438 .LBE167: + 439 .LBE166: + 440 .loc 1 5086 0 + 441 00b6 C3E7 b .L13 + 442 .L22: + 443 .align 2 + 444 .L21: + 445 00b8 FF00FFFF .word -65281 + 446 00bc FF0FFFFF .word -61441 + 447 .cfi_endproc + 448 .LFE144: + 450 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits + 451 .align 1 + 452 .weak HAL_TIM_Base_MspInit + 453 .syntax unified + 454 .code 16 + 455 .thumb_func + 456 .fpu softvfp + 458 HAL_TIM_Base_MspInit: + 459 .LFB41: + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 460 .loc 1 276 0 + 461 .cfi_startproc + 462 @ args = 0, pretend = 0, frame = 0 + 463 @ frame_needed = 0, uses_anonymous_args = 0 + 464 @ link register save eliminated. + 465 .LVL75: + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 466 .loc 1 283 0 + 467 @ sp needed + 468 0000 7047 bx lr + 469 .cfi_endproc + 470 .LFE41: + ARM GAS /tmp/ccH6KUTS.s page 99 + + + 472 .section .text.HAL_TIM_Base_Init,"ax",%progbits + 473 .align 1 + 474 .global HAL_TIM_Base_Init + 475 .syntax unified + 476 .code 16 + 477 .thumb_func + 478 .fpu softvfp + 480 HAL_TIM_Base_Init: + 481 .LFB39: + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 482 .loc 1 208 0 + 483 .cfi_startproc + 484 @ args = 0, pretend = 0, frame = 0 + 485 @ frame_needed = 0, uses_anonymous_args = 0 + 486 .LVL76: + 487 0000 70B5 push {r4, r5, r6, lr} + 488 .LCFI2: + 489 .cfi_def_cfa_offset 16 + 490 .cfi_offset 4, -16 + 491 .cfi_offset 5, -12 + 492 .cfi_offset 6, -8 + 493 .cfi_offset 14, -4 + 494 0002 041E subs r4, r0, #0 + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 495 .loc 1 210 0 + 496 0004 14D0 beq .L27 + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 497 .loc 1 222 0 + 498 0006 3523 movs r3, #53 + 499 0008 C35C ldrb r3, [r0, r3] + 500 000a 002B cmp r3, #0 + 501 000c 0AD0 beq .L28 + 502 .LVL77: + 503 .L26: + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 504 .loc 1 232 0 + 505 000e 3525 movs r5, #53 + 506 0010 0223 movs r3, #2 + 507 0012 6355 strb r3, [r4, r5] + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 508 .loc 1 235 0 + 509 0014 211D adds r1, r4, #4 + 510 0016 2068 ldr r0, [r4] + 511 0018 FFF7FEFF bl TIM_Base_SetConfig + 512 .LVL78: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 513 .loc 1 238 0 + 514 001c 0123 movs r3, #1 + 515 001e 6355 strb r3, [r4, r5] + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 516 .loc 1 240 0 + 517 0020 0020 movs r0, #0 + 518 .L25: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 519 .loc 1 241 0 + 520 @ sp needed + 521 .LVL79: + ARM GAS /tmp/ccH6KUTS.s page 100 + + + 522 0022 70BD pop {r4, r5, r6, pc} + 523 .LVL80: + 524 .L28: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 525 .loc 1 225 0 + 526 0024 3433 adds r3, r3, #52 + 527 0026 0022 movs r2, #0 + 528 0028 C254 strb r2, [r0, r3] + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 529 .loc 1 228 0 + 530 002a FFF7FEFF bl HAL_TIM_Base_MspInit + 531 .LVL81: + 532 002e EEE7 b .L26 + 533 .LVL82: + 534 .L27: + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 535 .loc 1 212 0 + 536 0030 0120 movs r0, #1 + 537 .LVL83: + 538 0032 F6E7 b .L25 + 539 .cfi_endproc + 540 .LFE39: + 542 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits + 543 .align 1 + 544 .weak HAL_TIM_Base_MspDeInit + 545 .syntax unified + 546 .code 16 + 547 .thumb_func + 548 .fpu softvfp + 550 HAL_TIM_Base_MspDeInit: + 551 .LFB42: + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 552 .loc 1 291 0 + 553 .cfi_startproc + 554 @ args = 0, pretend = 0, frame = 0 + 555 @ frame_needed = 0, uses_anonymous_args = 0 + 556 @ link register save eliminated. + 557 .LVL84: + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 558 .loc 1 298 0 + 559 @ sp needed + 560 0000 7047 bx lr + 561 .cfi_endproc + 562 .LFE42: + 564 .section .text.HAL_TIM_Base_DeInit,"ax",%progbits + 565 .align 1 + 566 .global HAL_TIM_Base_DeInit + 567 .syntax unified + 568 .code 16 + 569 .thumb_func + 570 .fpu softvfp + 572 HAL_TIM_Base_DeInit: + 573 .LFB40: + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 574 .loc 1 249 0 + 575 .cfi_startproc + 576 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccH6KUTS.s page 101 + + + 577 @ frame_needed = 0, uses_anonymous_args = 0 + 578 .LVL85: + 579 0000 10B5 push {r4, lr} + 580 .LCFI3: + 581 .cfi_def_cfa_offset 8 + 582 .cfi_offset 4, -8 + 583 .cfi_offset 14, -4 + 584 0002 0400 movs r4, r0 + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 585 .loc 1 253 0 + 586 0004 3523 movs r3, #53 + 587 0006 0222 movs r2, #2 + 588 0008 C254 strb r2, [r0, r3] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 589 .loc 1 256 0 + 590 000a 0368 ldr r3, [r0] + 591 000c 196A ldr r1, [r3, #32] + 592 000e 084A ldr r2, .L32 + 593 0010 1142 tst r1, r2 + 594 0012 03D1 bne .L31 + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 595 .loc 1 256 0 is_stmt 0 discriminator 1 + 596 0014 1A68 ldr r2, [r3] + 597 0016 0121 movs r1, #1 + 598 0018 8A43 bics r2, r1 + 599 001a 1A60 str r2, [r3] + 600 .L31: + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 601 .loc 1 259 0 is_stmt 1 + 602 001c 2000 movs r0, r4 + 603 .LVL86: + 604 001e FFF7FEFF bl HAL_TIM_Base_MspDeInit + 605 .LVL87: + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 606 .loc 1 262 0 + 607 0022 0023 movs r3, #0 + 608 0024 3522 movs r2, #53 + 609 0026 A354 strb r3, [r4, r2] + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 610 .loc 1 265 0 + 611 0028 013A subs r2, r2, #1 + 612 002a A354 strb r3, [r4, r2] + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 613 .loc 1 268 0 + 614 002c 0020 movs r0, #0 + 615 @ sp needed + 616 .LVL88: + 617 002e 10BD pop {r4, pc} + 618 .L33: + 619 .align 2 + 620 .L32: + 621 0030 11110000 .word 4369 + 622 .cfi_endproc + 623 .LFE40: + 625 .section .text.HAL_TIM_Base_Start,"ax",%progbits + 626 .align 1 + 627 .global HAL_TIM_Base_Start + ARM GAS /tmp/ccH6KUTS.s page 102 + + + 628 .syntax unified + 629 .code 16 + 630 .thumb_func + 631 .fpu softvfp + 633 HAL_TIM_Base_Start: + 634 .LFB43: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 635 .loc 1 306 0 + 636 .cfi_startproc + 637 @ args = 0, pretend = 0, frame = 0 + 638 @ frame_needed = 0, uses_anonymous_args = 0 + 639 .LVL89: + 640 0000 10B5 push {r4, lr} + 641 .LCFI4: + 642 .cfi_def_cfa_offset 8 + 643 .cfi_offset 4, -8 + 644 .cfi_offset 14, -4 + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 645 .loc 1 311 0 + 646 0002 3522 movs r2, #53 + 647 0004 0223 movs r3, #2 + 648 0006 8354 strb r3, [r0, r2] + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 649 .loc 1 314 0 + 650 0008 0468 ldr r4, [r0] + 651 000a 2368 ldr r3, [r4] + 652 000c 0121 movs r1, #1 + 653 000e 0B43 orrs r3, r1 + 654 0010 2360 str r3, [r4] + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 655 .loc 1 317 0 + 656 0012 8154 strb r1, [r0, r2] + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 657 .loc 1 321 0 + 658 0014 0020 movs r0, #0 + 659 .LVL90: + 660 @ sp needed + 661 0016 10BD pop {r4, pc} + 662 .cfi_endproc + 663 .LFE43: + 665 .section .text.HAL_TIM_Base_Stop,"ax",%progbits + 666 .align 1 + 667 .global HAL_TIM_Base_Stop + 668 .syntax unified + 669 .code 16 + 670 .thumb_func + 671 .fpu softvfp + 673 HAL_TIM_Base_Stop: + 674 .LFB44: + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 675 .loc 1 329 0 + 676 .cfi_startproc + 677 @ args = 0, pretend = 0, frame = 0 + 678 @ frame_needed = 0, uses_anonymous_args = 0 + 679 @ link register save eliminated. + 680 .LVL91: + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 103 + + + 681 .loc 1 334 0 + 682 0000 3523 movs r3, #53 + 683 0002 0222 movs r2, #2 + 684 0004 C254 strb r2, [r0, r3] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 685 .loc 1 337 0 + 686 0006 0368 ldr r3, [r0] + 687 0008 196A ldr r1, [r3, #32] + 688 000a 064A ldr r2, .L37 + 689 000c 1142 tst r1, r2 + 690 000e 03D1 bne .L36 + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 691 .loc 1 337 0 is_stmt 0 discriminator 1 + 692 0010 1A68 ldr r2, [r3] + 693 0012 0121 movs r1, #1 + 694 0014 8A43 bics r2, r1 + 695 0016 1A60 str r2, [r3] + 696 .L36: + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 697 .loc 1 340 0 is_stmt 1 + 698 0018 3523 movs r3, #53 + 699 001a 0122 movs r2, #1 + 700 001c C254 strb r2, [r0, r3] + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 701 .loc 1 344 0 + 702 001e 0020 movs r0, #0 + 703 .LVL92: + 704 @ sp needed + 705 0020 7047 bx lr + 706 .L38: + 707 0022 C046 .align 2 + 708 .L37: + 709 0024 11110000 .word 4369 + 710 .cfi_endproc + 711 .LFE44: + 713 .section .text.HAL_TIM_Base_Start_IT,"ax",%progbits + 714 .align 1 + 715 .global HAL_TIM_Base_Start_IT + 716 .syntax unified + 717 .code 16 + 718 .thumb_func + 719 .fpu softvfp + 721 HAL_TIM_Base_Start_IT: + 722 .LFB45: + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 723 .loc 1 352 0 + 724 .cfi_startproc + 725 @ args = 0, pretend = 0, frame = 0 + 726 @ frame_needed = 0, uses_anonymous_args = 0 + 727 @ link register save eliminated. + 728 .LVL93: + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 729 .loc 1 357 0 + 730 0000 0368 ldr r3, [r0] + 731 0002 DA68 ldr r2, [r3, #12] + 732 0004 0121 movs r1, #1 + 733 0006 0A43 orrs r2, r1 + ARM GAS /tmp/ccH6KUTS.s page 104 + + + 734 0008 DA60 str r2, [r3, #12] + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 735 .loc 1 360 0 + 736 000a 0268 ldr r2, [r0] + 737 000c 1368 ldr r3, [r2] + 738 000e 0B43 orrs r3, r1 + 739 0010 1360 str r3, [r2] + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 740 .loc 1 364 0 + 741 0012 0020 movs r0, #0 + 742 .LVL94: + 743 @ sp needed + 744 0014 7047 bx lr + 745 .cfi_endproc + 746 .LFE45: + 748 .section .text.HAL_TIM_Base_Stop_IT,"ax",%progbits + 749 .align 1 + 750 .global HAL_TIM_Base_Stop_IT + 751 .syntax unified + 752 .code 16 + 753 .thumb_func + 754 .fpu softvfp + 756 HAL_TIM_Base_Stop_IT: + 757 .LFB46: + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 758 .loc 1 372 0 + 759 .cfi_startproc + 760 @ args = 0, pretend = 0, frame = 0 + 761 @ frame_needed = 0, uses_anonymous_args = 0 + 762 @ link register save eliminated. + 763 .LVL95: + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 764 .loc 1 376 0 + 765 0000 0268 ldr r2, [r0] + 766 0002 D368 ldr r3, [r2, #12] + 767 0004 0121 movs r1, #1 + 768 0006 8B43 bics r3, r1 + 769 0008 D360 str r3, [r2, #12] + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 770 .loc 1 379 0 + 771 000a 0368 ldr r3, [r0] + 772 000c 196A ldr r1, [r3, #32] + 773 000e 044A ldr r2, .L42 + 774 0010 1142 tst r1, r2 + 775 0012 03D1 bne .L41 + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 776 .loc 1 379 0 is_stmt 0 discriminator 1 + 777 0014 1A68 ldr r2, [r3] + 778 0016 0121 movs r1, #1 + 779 0018 8A43 bics r2, r1 + 780 001a 1A60 str r2, [r3] + 781 .L41: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 782 .loc 1 383 0 is_stmt 1 + 783 001c 0020 movs r0, #0 + 784 .LVL96: + 785 @ sp needed + ARM GAS /tmp/ccH6KUTS.s page 105 + + + 786 001e 7047 bx lr + 787 .L43: + 788 .align 2 + 789 .L42: + 790 0020 11110000 .word 4369 + 791 .cfi_endproc + 792 .LFE46: + 794 .section .text.HAL_TIM_Base_Start_DMA,"ax",%progbits + 795 .align 1 + 796 .global HAL_TIM_Base_Start_DMA + 797 .syntax unified + 798 .code 16 + 799 .thumb_func + 800 .fpu softvfp + 802 HAL_TIM_Base_Start_DMA: + 803 .LFB47: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 804 .loc 1 393 0 + 805 .cfi_startproc + 806 @ args = 0, pretend = 0, frame = 0 + 807 @ frame_needed = 0, uses_anonymous_args = 0 + 808 .LVL97: + 809 0000 10B5 push {r4, lr} + 810 .LCFI5: + 811 .cfi_def_cfa_offset 8 + 812 .cfi_offset 4, -8 + 813 .cfi_offset 14, -4 + 814 0002 0400 movs r4, r0 + 815 0004 1300 movs r3, r2 + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 816 .loc 1 397 0 + 817 0006 3520 movs r0, #53 + 818 .LVL98: + 819 0008 205C ldrb r0, [r4, r0] + 820 000a 0228 cmp r0, #2 + 821 000c 24D0 beq .L48 + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 822 .loc 1 401 0 + 823 000e 3522 movs r2, #53 + 824 .LVL99: + 825 0010 A25C ldrb r2, [r4, r2] + 826 0012 012A cmp r2, #1 + 827 0014 04D1 bne .L46 + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 828 .loc 1 403 0 + 829 0016 0029 cmp r1, #0 + 830 0018 1AD0 beq .L50 + 831 .L47: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 832 .loc 1 409 0 + 833 001a 3522 movs r2, #53 + 834 001c 0220 movs r0, #2 + 835 001e A054 strb r0, [r4, r2] + 836 .L46: + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 837 .loc 1 413 0 + 838 0020 A269 ldr r2, [r4, #24] + ARM GAS /tmp/ccH6KUTS.s page 106 + + + 839 0022 0E48 ldr r0, .L51 + 840 0024 D062 str r0, [r2, #44] + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 841 .loc 1 416 0 + 842 0026 A269 ldr r2, [r4, #24] + 843 0028 0D48 ldr r0, .L51+4 + 844 002a 5063 str r0, [r2, #52] + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 845 .loc 1 419 0 + 846 002c 2268 ldr r2, [r4] + 847 002e 2C32 adds r2, r2, #44 + 848 0030 A069 ldr r0, [r4, #24] + 849 0032 FFF7FEFF bl HAL_DMA_Start_IT + 850 .LVL100: + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 851 .loc 1 422 0 + 852 0036 2268 ldr r2, [r4] + 853 0038 D168 ldr r1, [r2, #12] + 854 003a 8023 movs r3, #128 + 855 003c 5B00 lsls r3, r3, #1 + 856 003e 0B43 orrs r3, r1 + 857 0040 D360 str r3, [r2, #12] + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 858 .loc 1 425 0 + 859 0042 2268 ldr r2, [r4] + 860 0044 1368 ldr r3, [r2] + 861 0046 0121 movs r1, #1 + 862 0048 0B43 orrs r3, r1 + 863 004a 1360 str r3, [r2] + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 864 .loc 1 428 0 + 865 004c 0020 movs r0, #0 + 866 .L45: + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 867 .loc 1 429 0 + 868 @ sp needed + 869 .LVL101: + 870 004e 10BD pop {r4, pc} + 871 .LVL102: + 872 .L50: + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 873 .loc 1 403 0 discriminator 1 + 874 0050 002B cmp r3, #0 + 875 0052 E2D0 beq .L47 + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 876 .loc 1 405 0 + 877 0054 0120 movs r0, #1 + 878 0056 FAE7 b .L45 + 879 .LVL103: + 880 .L48: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 881 .loc 1 399 0 + 882 0058 0220 movs r0, #2 + 883 005a F8E7 b .L45 + 884 .L52: + 885 .align 2 + 886 .L51: + ARM GAS /tmp/ccH6KUTS.s page 107 + + + 887 005c 00000000 .word TIM_DMAPeriodElapsedCplt + 888 0060 00000000 .word TIM_DMAError + 889 .cfi_endproc + 890 .LFE47: + 892 .section .text.HAL_TIM_Base_Stop_DMA,"ax",%progbits + 893 .align 1 + 894 .global HAL_TIM_Base_Stop_DMA + 895 .syntax unified + 896 .code 16 + 897 .thumb_func + 898 .fpu softvfp + 900 HAL_TIM_Base_Stop_DMA: + 901 .LFB48: + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 902 .loc 1 437 0 + 903 .cfi_startproc + 904 @ args = 0, pretend = 0, frame = 0 + 905 @ frame_needed = 0, uses_anonymous_args = 0 + 906 @ link register save eliminated. + 907 .LVL104: + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 908 .loc 1 442 0 + 909 0000 0268 ldr r2, [r0] + 910 0002 D368 ldr r3, [r2, #12] + 911 0004 0849 ldr r1, .L55 + 912 0006 0B40 ands r3, r1 + 913 0008 D360 str r3, [r2, #12] + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 914 .loc 1 445 0 + 915 000a 0368 ldr r3, [r0] + 916 000c 196A ldr r1, [r3, #32] + 917 000e 074A ldr r2, .L55+4 + 918 0010 1142 tst r1, r2 + 919 0012 03D1 bne .L54 + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 920 .loc 1 445 0 is_stmt 0 discriminator 1 + 921 0014 1A68 ldr r2, [r3] + 922 0016 0121 movs r1, #1 + 923 0018 8A43 bics r2, r1 + 924 001a 1A60 str r2, [r3] + 925 .L54: + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 926 .loc 1 448 0 is_stmt 1 + 927 001c 3523 movs r3, #53 + 928 001e 0122 movs r2, #1 + 929 0020 C254 strb r2, [r0, r3] + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 930 .loc 1 452 0 + 931 0022 0020 movs r0, #0 + 932 .LVL105: + 933 @ sp needed + 934 0024 7047 bx lr + 935 .L56: + 936 0026 C046 .align 2 + 937 .L55: + 938 0028 FFFEFFFF .word -257 + 939 002c 11110000 .word 4369 + ARM GAS /tmp/ccH6KUTS.s page 108 + + + 940 .cfi_endproc + 941 .LFE48: + 943 .section .text.HAL_TIM_OC_MspInit,"ax",%progbits + 944 .align 1 + 945 .weak HAL_TIM_OC_MspInit + 946 .syntax unified + 947 .code 16 + 948 .thumb_func + 949 .fpu softvfp + 951 HAL_TIM_OC_MspInit: + 952 .LFB51: + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 953 .loc 1 554 0 + 954 .cfi_startproc + 955 @ args = 0, pretend = 0, frame = 0 + 956 @ frame_needed = 0, uses_anonymous_args = 0 + 957 @ link register save eliminated. + 958 .LVL106: + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 959 .loc 1 561 0 + 960 @ sp needed + 961 0000 7047 bx lr + 962 .cfi_endproc + 963 .LFE51: + 965 .section .text.HAL_TIM_OC_Init,"ax",%progbits + 966 .align 1 + 967 .global HAL_TIM_OC_Init + 968 .syntax unified + 969 .code 16 + 970 .thumb_func + 971 .fpu softvfp + 973 HAL_TIM_OC_Init: + 974 .LFB49: + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 975 .loc 1 487 0 + 976 .cfi_startproc + 977 @ args = 0, pretend = 0, frame = 0 + 978 @ frame_needed = 0, uses_anonymous_args = 0 + 979 .LVL107: + 980 0000 70B5 push {r4, r5, r6, lr} + 981 .LCFI6: + 982 .cfi_def_cfa_offset 16 + 983 .cfi_offset 4, -16 + 984 .cfi_offset 5, -12 + 985 .cfi_offset 6, -8 + 986 .cfi_offset 14, -4 + 987 0002 041E subs r4, r0, #0 + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 988 .loc 1 489 0 + 989 0004 14D0 beq .L61 + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 990 .loc 1 501 0 + 991 0006 3523 movs r3, #53 + 992 0008 C35C ldrb r3, [r0, r3] + 993 000a 002B cmp r3, #0 + 994 000c 0AD0 beq .L62 + 995 .LVL108: + ARM GAS /tmp/ccH6KUTS.s page 109 + + + 996 .L60: + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 997 .loc 1 510 0 + 998 000e 3525 movs r5, #53 + 999 0010 0223 movs r3, #2 + 1000 0012 6355 strb r3, [r4, r5] + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1001 .loc 1 513 0 + 1002 0014 211D adds r1, r4, #4 + 1003 0016 2068 ldr r0, [r4] + 1004 0018 FFF7FEFF bl TIM_Base_SetConfig + 1005 .LVL109: + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1006 .loc 1 516 0 + 1007 001c 0123 movs r3, #1 + 1008 001e 6355 strb r3, [r4, r5] + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1009 .loc 1 518 0 + 1010 0020 0020 movs r0, #0 + 1011 .L59: + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1012 .loc 1 519 0 + 1013 @ sp needed + 1014 .LVL110: + 1015 0022 70BD pop {r4, r5, r6, pc} + 1016 .LVL111: + 1017 .L62: + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1018 .loc 1 504 0 + 1019 0024 3433 adds r3, r3, #52 + 1020 0026 0022 movs r2, #0 + 1021 0028 C254 strb r2, [r0, r3] + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1022 .loc 1 507 0 + 1023 002a FFF7FEFF bl HAL_TIM_OC_MspInit + 1024 .LVL112: + 1025 002e EEE7 b .L60 + 1026 .LVL113: + 1027 .L61: + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1028 .loc 1 491 0 + 1029 0030 0120 movs r0, #1 + 1030 .LVL114: + 1031 0032 F6E7 b .L59 + 1032 .cfi_endproc + 1033 .LFE49: + 1035 .section .text.HAL_TIM_OC_MspDeInit,"ax",%progbits + 1036 .align 1 + 1037 .weak HAL_TIM_OC_MspDeInit + 1038 .syntax unified + 1039 .code 16 + 1040 .thumb_func + 1041 .fpu softvfp + 1043 HAL_TIM_OC_MspDeInit: + 1044 .LFB52: + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1045 .loc 1 569 0 + ARM GAS /tmp/ccH6KUTS.s page 110 + + + 1046 .cfi_startproc + 1047 @ args = 0, pretend = 0, frame = 0 + 1048 @ frame_needed = 0, uses_anonymous_args = 0 + 1049 @ link register save eliminated. + 1050 .LVL115: + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1051 .loc 1 576 0 + 1052 @ sp needed + 1053 0000 7047 bx lr + 1054 .cfi_endproc + 1055 .LFE52: + 1057 .section .text.HAL_TIM_OC_DeInit,"ax",%progbits + 1058 .align 1 + 1059 .global HAL_TIM_OC_DeInit + 1060 .syntax unified + 1061 .code 16 + 1062 .thumb_func + 1063 .fpu softvfp + 1065 HAL_TIM_OC_DeInit: + 1066 .LFB50: + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1067 .loc 1 527 0 + 1068 .cfi_startproc + 1069 @ args = 0, pretend = 0, frame = 0 + 1070 @ frame_needed = 0, uses_anonymous_args = 0 + 1071 .LVL116: + 1072 0000 10B5 push {r4, lr} + 1073 .LCFI7: + 1074 .cfi_def_cfa_offset 8 + 1075 .cfi_offset 4, -8 + 1076 .cfi_offset 14, -4 + 1077 0002 0400 movs r4, r0 + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1078 .loc 1 531 0 + 1079 0004 3523 movs r3, #53 + 1080 0006 0222 movs r2, #2 + 1081 0008 C254 strb r2, [r0, r3] + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1082 .loc 1 534 0 + 1083 000a 0368 ldr r3, [r0] + 1084 000c 196A ldr r1, [r3, #32] + 1085 000e 084A ldr r2, .L66 + 1086 0010 1142 tst r1, r2 + 1087 0012 03D1 bne .L65 + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1088 .loc 1 534 0 is_stmt 0 discriminator 1 + 1089 0014 1A68 ldr r2, [r3] + 1090 0016 0121 movs r1, #1 + 1091 0018 8A43 bics r2, r1 + 1092 001a 1A60 str r2, [r3] + 1093 .L65: + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1094 .loc 1 537 0 is_stmt 1 + 1095 001c 2000 movs r0, r4 + 1096 .LVL117: + 1097 001e FFF7FEFF bl HAL_TIM_OC_MspDeInit + 1098 .LVL118: + ARM GAS /tmp/ccH6KUTS.s page 111 + + + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1099 .loc 1 540 0 + 1100 0022 0023 movs r3, #0 + 1101 0024 3522 movs r2, #53 + 1102 0026 A354 strb r3, [r4, r2] + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1103 .loc 1 543 0 + 1104 0028 013A subs r2, r2, #1 + 1105 002a A354 strb r3, [r4, r2] + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1106 .loc 1 546 0 + 1107 002c 0020 movs r0, #0 + 1108 @ sp needed + 1109 .LVL119: + 1110 002e 10BD pop {r4, pc} + 1111 .L67: + 1112 .align 2 + 1113 .L66: + 1114 0030 11110000 .word 4369 + 1115 .cfi_endproc + 1116 .LFE50: + 1118 .section .text.HAL_TIM_OC_Start,"ax",%progbits + 1119 .align 1 + 1120 .global HAL_TIM_OC_Start + 1121 .syntax unified + 1122 .code 16 + 1123 .thumb_func + 1124 .fpu softvfp + 1126 HAL_TIM_OC_Start: + 1127 .LFB53: + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1128 .loc 1 590 0 + 1129 .cfi_startproc + 1130 @ args = 0, pretend = 0, frame = 0 + 1131 @ frame_needed = 0, uses_anonymous_args = 0 + 1132 .LVL120: + 1133 0000 10B5 push {r4, lr} + 1134 .LCFI8: + 1135 .cfi_def_cfa_offset 8 + 1136 .cfi_offset 4, -8 + 1137 .cfi_offset 14, -4 + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1138 .loc 1 595 0 + 1139 0002 0368 ldr r3, [r0] + 1140 .LVL121: + 1141 .LBB168: + 1142 .LBB169: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1143 .loc 1 4947 0 + 1144 0004 0124 movs r4, #1 + 1145 0006 2200 movs r2, r4 + 1146 0008 8A40 lsls r2, r2, r1 + 1147 .LVL122: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1148 .loc 1 4950 0 + 1149 000a 196A ldr r1, [r3, #32] + 1150 .LVL123: + ARM GAS /tmp/ccH6KUTS.s page 112 + + + 1151 000c 9143 bics r1, r2 + 1152 000e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1153 .loc 1 4953 0 + 1154 0010 196A ldr r1, [r3, #32] + 1155 0012 0A43 orrs r2, r1 + 1156 .LVL124: + 1157 0014 1A62 str r2, [r3, #32] + 1158 .LVL125: + 1159 .LBE169: + 1160 .LBE168: + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1161 .loc 1 598 0 + 1162 0016 0268 ldr r2, [r0] + 1163 0018 1368 ldr r3, [r2] + 1164 001a 2343 orrs r3, r4 + 1165 001c 1360 str r3, [r2] + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1166 .loc 1 602 0 + 1167 001e 0020 movs r0, #0 + 1168 .LVL126: + 1169 @ sp needed + 1170 0020 10BD pop {r4, pc} + 1171 .cfi_endproc + 1172 .LFE53: + 1174 .section .text.HAL_TIM_OC_Stop,"ax",%progbits + 1175 .align 1 + 1176 .global HAL_TIM_OC_Stop + 1177 .syntax unified + 1178 .code 16 + 1179 .thumb_func + 1180 .fpu softvfp + 1182 HAL_TIM_OC_Stop: + 1183 .LFB54: + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1184 .loc 1 616 0 + 1185 .cfi_startproc + 1186 @ args = 0, pretend = 0, frame = 0 + 1187 @ frame_needed = 0, uses_anonymous_args = 0 + 1188 @ link register save eliminated. + 1189 .LVL127: + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1190 .loc 1 621 0 + 1191 0000 0368 ldr r3, [r0] + 1192 .LVL128: + 1193 .LBB170: + 1194 .LBB171: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1195 .loc 1 4947 0 + 1196 0002 0122 movs r2, #1 + 1197 0004 8A40 lsls r2, r2, r1 + 1198 0006 1100 movs r1, r2 + 1199 .LVL129: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1200 .loc 1 4950 0 + 1201 0008 1A6A ldr r2, [r3, #32] + 1202 000a 8A43 bics r2, r1 + ARM GAS /tmp/ccH6KUTS.s page 113 + + + 1203 000c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1204 .loc 1 4953 0 + 1205 000e 1A6A ldr r2, [r3, #32] + 1206 0010 1A62 str r2, [r3, #32] + 1207 .LVL130: + 1208 .LBE171: + 1209 .LBE170: + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1210 .loc 1 624 0 + 1211 0012 0368 ldr r3, [r0] + 1212 0014 196A ldr r1, [r3, #32] + 1213 0016 044A ldr r2, .L71 + 1214 0018 1142 tst r1, r2 + 1215 001a 03D1 bne .L70 + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1216 .loc 1 624 0 is_stmt 0 discriminator 1 + 1217 001c 1A68 ldr r2, [r3] + 1218 001e 0121 movs r1, #1 + 1219 0020 8A43 bics r2, r1 + 1220 0022 1A60 str r2, [r3] + 1221 .L70: + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1222 .loc 1 628 0 is_stmt 1 + 1223 0024 0020 movs r0, #0 + 1224 .LVL131: + 1225 @ sp needed + 1226 0026 7047 bx lr + 1227 .L72: + 1228 .align 2 + 1229 .L71: + 1230 0028 11110000 .word 4369 + 1231 .cfi_endproc + 1232 .LFE54: + 1234 .section .text.HAL_TIM_OC_Start_IT,"ax",%progbits + 1235 .align 1 + 1236 .global HAL_TIM_OC_Start_IT + 1237 .syntax unified + 1238 .code 16 + 1239 .thumb_func + 1240 .fpu softvfp + 1242 HAL_TIM_OC_Start_IT: + 1243 .LFB55: + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1244 .loc 1 642 0 + 1245 .cfi_startproc + 1246 @ args = 0, pretend = 0, frame = 0 + 1247 @ frame_needed = 0, uses_anonymous_args = 0 + 1248 .LVL132: + 1249 0000 10B5 push {r4, lr} + 1250 .LCFI9: + 1251 .cfi_def_cfa_offset 8 + 1252 .cfi_offset 4, -8 + 1253 .cfi_offset 14, -4 + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1254 .loc 1 646 0 + 1255 0002 0429 cmp r1, #4 + ARM GAS /tmp/ccH6KUTS.s page 114 + + + 1256 0004 21D0 beq .L75 + 1257 0006 09D9 bls .L80 + 1258 0008 0829 cmp r1, #8 + 1259 000a 24D0 beq .L78 + 1260 000c 0C29 cmp r1, #12 + 1261 000e 0CD1 bne .L74 + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1262 .loc 1 672 0 + 1263 0010 0268 ldr r2, [r0] + 1264 0012 D368 ldr r3, [r2, #12] + 1265 0014 1024 movs r4, #16 + 1266 0016 2343 orrs r3, r4 + 1267 0018 D360 str r3, [r2, #12] + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1268 .loc 1 674 0 + 1269 001a 06E0 b .L74 + 1270 .L80: + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1271 .loc 1 646 0 + 1272 001c 0029 cmp r1, #0 + 1273 001e 04D1 bne .L74 + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1274 .loc 1 651 0 + 1275 0020 0268 ldr r2, [r0] + 1276 0022 D368 ldr r3, [r2, #12] + 1277 0024 0224 movs r4, #2 + 1278 0026 2343 orrs r3, r4 + 1279 0028 D360 str r3, [r2, #12] + 1280 .L74: + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1281 .loc 1 681 0 + 1282 002a 0368 ldr r3, [r0] + 1283 .LVL133: + 1284 .LBB172: + 1285 .LBB173: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1286 .loc 1 4947 0 + 1287 002c 0124 movs r4, #1 + 1288 002e 2200 movs r2, r4 + 1289 0030 8A40 lsls r2, r2, r1 + 1290 .LVL134: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1291 .loc 1 4950 0 + 1292 0032 196A ldr r1, [r3, #32] + 1293 .LVL135: + 1294 0034 9143 bics r1, r2 + 1295 0036 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1296 .loc 1 4953 0 + 1297 0038 196A ldr r1, [r3, #32] + 1298 003a 0A43 orrs r2, r1 + 1299 .LVL136: + 1300 003c 1A62 str r2, [r3, #32] + 1301 .LVL137: + 1302 .LBE173: + 1303 .LBE172: + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 115 + + + 1304 .loc 1 684 0 + 1305 003e 0268 ldr r2, [r0] + 1306 0040 1368 ldr r3, [r2] + 1307 0042 2343 orrs r3, r4 + 1308 0044 1360 str r3, [r2] + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1309 .loc 1 688 0 + 1310 0046 0020 movs r0, #0 + 1311 .LVL138: + 1312 @ sp needed + 1313 0048 10BD pop {r4, pc} + 1314 .LVL139: + 1315 .L75: + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1316 .loc 1 658 0 + 1317 004a 0268 ldr r2, [r0] + 1318 004c D368 ldr r3, [r2, #12] + 1319 004e 0424 movs r4, #4 + 1320 0050 2343 orrs r3, r4 + 1321 0052 D360 str r3, [r2, #12] + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1322 .loc 1 660 0 + 1323 0054 E9E7 b .L74 + 1324 .L78: + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1325 .loc 1 665 0 + 1326 0056 0268 ldr r2, [r0] + 1327 0058 D368 ldr r3, [r2, #12] + 1328 005a 0824 movs r4, #8 + 1329 005c 2343 orrs r3, r4 + 1330 005e D360 str r3, [r2, #12] + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1331 .loc 1 667 0 + 1332 0060 E3E7 b .L74 + 1333 .cfi_endproc + 1334 .LFE55: + 1336 .section .text.HAL_TIM_OC_Stop_IT,"ax",%progbits + 1337 .align 1 + 1338 .global HAL_TIM_OC_Stop_IT + 1339 .syntax unified + 1340 .code 16 + 1341 .thumb_func + 1342 .fpu softvfp + 1344 HAL_TIM_OC_Stop_IT: + 1345 .LFB56: + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1346 .loc 1 702 0 + 1347 .cfi_startproc + 1348 @ args = 0, pretend = 0, frame = 0 + 1349 @ frame_needed = 0, uses_anonymous_args = 0 + 1350 .LVL140: + 1351 0000 10B5 push {r4, lr} + 1352 .LCFI10: + 1353 .cfi_def_cfa_offset 8 + 1354 .cfi_offset 4, -8 + 1355 .cfi_offset 14, -4 + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 116 + + + 1356 .loc 1 706 0 + 1357 0002 0429 cmp r1, #4 + 1358 0004 25D0 beq .L83 + 1359 0006 09D9 bls .L89 + 1360 0008 0829 cmp r1, #8 + 1361 000a 28D0 beq .L86 + 1362 000c 0C29 cmp r1, #12 + 1363 000e 0CD1 bne .L82 + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1364 .loc 1 732 0 + 1365 0010 0268 ldr r2, [r0] + 1366 0012 D368 ldr r3, [r2, #12] + 1367 0014 1024 movs r4, #16 + 1368 0016 A343 bics r3, r4 + 1369 0018 D360 str r3, [r2, #12] + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1370 .loc 1 734 0 + 1371 001a 06E0 b .L82 + 1372 .L89: + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1373 .loc 1 706 0 + 1374 001c 0029 cmp r1, #0 + 1375 001e 04D1 bne .L82 + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1376 .loc 1 711 0 + 1377 0020 0268 ldr r2, [r0] + 1378 0022 D368 ldr r3, [r2, #12] + 1379 0024 0224 movs r4, #2 + 1380 0026 A343 bics r3, r4 + 1381 0028 D360 str r3, [r2, #12] + 1382 .L82: + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1383 .loc 1 741 0 + 1384 002a 0368 ldr r3, [r0] + 1385 .LVL141: + 1386 .LBB174: + 1387 .LBB175: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1388 .loc 1 4947 0 + 1389 002c 0122 movs r2, #1 + 1390 002e 8A40 lsls r2, r2, r1 + 1391 0030 1100 movs r1, r2 + 1392 .LVL142: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1393 .loc 1 4950 0 + 1394 0032 1A6A ldr r2, [r3, #32] + 1395 0034 8A43 bics r2, r1 + 1396 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1397 .loc 1 4953 0 + 1398 0038 1A6A ldr r2, [r3, #32] + 1399 003a 1A62 str r2, [r3, #32] + 1400 .LVL143: + 1401 .LBE175: + 1402 .LBE174: + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1403 .loc 1 744 0 + ARM GAS /tmp/ccH6KUTS.s page 117 + + + 1404 003c 0368 ldr r3, [r0] + 1405 003e 196A ldr r1, [r3, #32] + 1406 0040 0A4A ldr r2, .L90 + 1407 0042 1142 tst r1, r2 + 1408 0044 03D1 bne .L88 + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1409 .loc 1 744 0 is_stmt 0 discriminator 1 + 1410 0046 1A68 ldr r2, [r3] + 1411 0048 0121 movs r1, #1 + 1412 004a 8A43 bics r2, r1 + 1413 004c 1A60 str r2, [r3] + 1414 .L88: + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1415 .loc 1 748 0 is_stmt 1 + 1416 004e 0020 movs r0, #0 + 1417 .LVL144: + 1418 @ sp needed + 1419 0050 10BD pop {r4, pc} + 1420 .LVL145: + 1421 .L83: + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1422 .loc 1 718 0 + 1423 0052 0268 ldr r2, [r0] + 1424 0054 D368 ldr r3, [r2, #12] + 1425 0056 0424 movs r4, #4 + 1426 0058 A343 bics r3, r4 + 1427 005a D360 str r3, [r2, #12] + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1428 .loc 1 720 0 + 1429 005c E5E7 b .L82 + 1430 .L86: + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1431 .loc 1 725 0 + 1432 005e 0268 ldr r2, [r0] + 1433 0060 D368 ldr r3, [r2, #12] + 1434 0062 0824 movs r4, #8 + 1435 0064 A343 bics r3, r4 + 1436 0066 D360 str r3, [r2, #12] + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1437 .loc 1 727 0 + 1438 0068 DFE7 b .L82 + 1439 .L91: + 1440 006a C046 .align 2 + 1441 .L90: + 1442 006c 11110000 .word 4369 + 1443 .cfi_endproc + 1444 .LFE56: + 1446 .section .text.HAL_TIM_OC_Start_DMA,"ax",%progbits + 1447 .align 1 + 1448 .global HAL_TIM_OC_Start_DMA + 1449 .syntax unified + 1450 .code 16 + 1451 .thumb_func + 1452 .fpu softvfp + 1454 HAL_TIM_OC_Start_DMA: + 1455 .LFB57: + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccH6KUTS.s page 118 + + + 1456 .loc 1 764 0 + 1457 .cfi_startproc + 1458 @ args = 0, pretend = 0, frame = 0 + 1459 @ frame_needed = 0, uses_anonymous_args = 0 + 1460 .LVL146: + 1461 0000 70B5 push {r4, r5, r6, lr} + 1462 .LCFI11: + 1463 .cfi_def_cfa_offset 16 + 1464 .cfi_offset 4, -16 + 1465 .cfi_offset 5, -12 + 1466 .cfi_offset 6, -8 + 1467 .cfi_offset 14, -4 + 1468 0002 0400 movs r4, r0 + 1469 0004 0D00 movs r5, r1 + 1470 0006 1100 movs r1, r2 + 1471 .LVL147: + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1472 .loc 1 768 0 + 1473 0008 3522 movs r2, #53 + 1474 .LVL148: + 1475 000a 825C ldrb r2, [r0, r2] + 1476 000c 022A cmp r2, #2 + 1477 000e 00D1 bne .LCB1333 + 1478 0010 6DE0 b .L102 @long jump + 1479 .LCB1333: + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1480 .loc 1 772 0 + 1481 0012 3522 movs r2, #53 + 1482 0014 825C ldrb r2, [r0, r2] + 1483 0016 012A cmp r2, #1 + 1484 0018 18D0 beq .L104 + 1485 .LVL149: + 1486 .L94: + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1487 .loc 1 783 0 + 1488 001a 042D cmp r5, #4 + 1489 001c 43D0 beq .L97 + 1490 001e 1FD9 bls .L105 + 1491 0020 082D cmp r5, #8 + 1492 0022 52D0 beq .L100 + 1493 0024 0C2D cmp r5, #12 + 1494 0026 2ED1 bne .L96 + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1495 .loc 1 836 0 + 1496 0028 A26A ldr r2, [r4, #40] + 1497 002a 3248 ldr r0, .L107 + 1498 002c D062 str r0, [r2, #44] + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1499 .loc 1 839 0 + 1500 002e A26A ldr r2, [r4, #40] + 1501 0030 3148 ldr r0, .L107+4 + 1502 0032 5063 str r0, [r2, #52] + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1503 .loc 1 842 0 + 1504 0034 2268 ldr r2, [r4] + 1505 0036 4032 adds r2, r2, #64 + 1506 0038 A06A ldr r0, [r4, #40] + ARM GAS /tmp/ccH6KUTS.s page 119 + + + 1507 003a FFF7FEFF bl HAL_DMA_Start_IT + 1508 .LVL150: + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1509 .loc 1 845 0 + 1510 003e 2268 ldr r2, [r4] + 1511 0040 D168 ldr r1, [r2, #12] + 1512 0042 8023 movs r3, #128 + 1513 0044 5B01 lsls r3, r3, #5 + 1514 0046 0B43 orrs r3, r1 + 1515 0048 D360 str r3, [r2, #12] + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1516 .loc 1 847 0 + 1517 004a 1CE0 b .L96 + 1518 .LVL151: + 1519 .L104: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1520 .loc 1 774 0 + 1521 004c 0029 cmp r1, #0 + 1522 004e 03D0 beq .L106 + 1523 .L95: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1524 .loc 1 780 0 + 1525 0050 3522 movs r2, #53 + 1526 0052 0220 movs r0, #2 + 1527 .LVL152: + 1528 0054 A054 strb r0, [r4, r2] + 1529 0056 E0E7 b .L94 + 1530 .LVL153: + 1531 .L106: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1532 .loc 1 774 0 discriminator 1 + 1533 0058 002B cmp r3, #0 + 1534 005a F9D0 beq .L95 + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1535 .loc 1 776 0 + 1536 005c 0120 movs r0, #1 + 1537 .LVL154: + 1538 005e 21E0 b .L93 + 1539 .L105: + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1540 .loc 1 783 0 + 1541 0060 002D cmp r5, #0 + 1542 0062 10D1 bne .L96 + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1543 .loc 1 788 0 + 1544 0064 E269 ldr r2, [r4, #28] + 1545 0066 2348 ldr r0, .L107 + 1546 0068 D062 str r0, [r2, #44] + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1547 .loc 1 791 0 + 1548 006a E269 ldr r2, [r4, #28] + 1549 006c 2248 ldr r0, .L107+4 + 1550 006e 5063 str r0, [r2, #52] + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1551 .loc 1 794 0 + 1552 0070 2268 ldr r2, [r4] + 1553 0072 3432 adds r2, r2, #52 + ARM GAS /tmp/ccH6KUTS.s page 120 + + + 1554 0074 E069 ldr r0, [r4, #28] + 1555 0076 FFF7FEFF bl HAL_DMA_Start_IT + 1556 .LVL155: + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1557 .loc 1 797 0 + 1558 007a 2268 ldr r2, [r4] + 1559 007c D168 ldr r1, [r2, #12] + 1560 007e 8023 movs r3, #128 + 1561 0080 9B00 lsls r3, r3, #2 + 1562 0082 0B43 orrs r3, r1 + 1563 0084 D360 str r3, [r2, #12] + 1564 .L96: + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1565 .loc 1 854 0 + 1566 0086 2368 ldr r3, [r4] + 1567 .LVL156: + 1568 .LBB176: + 1569 .LBB177: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1570 .loc 1 4947 0 + 1571 0088 0120 movs r0, #1 + 1572 008a 0200 movs r2, r0 + 1573 008c AA40 lsls r2, r2, r5 + 1574 .LVL157: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1575 .loc 1 4950 0 + 1576 008e 196A ldr r1, [r3, #32] + 1577 0090 9143 bics r1, r2 + 1578 0092 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1579 .loc 1 4953 0 + 1580 0094 196A ldr r1, [r3, #32] + 1581 0096 0A43 orrs r2, r1 + 1582 .LVL158: + 1583 0098 1A62 str r2, [r3, #32] + 1584 .LVL159: + 1585 .LBE177: + 1586 .LBE176: + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1587 .loc 1 857 0 + 1588 009a 2268 ldr r2, [r4] + 1589 009c 1368 ldr r3, [r2] + 1590 009e 0343 orrs r3, r0 + 1591 00a0 1360 str r3, [r2] + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1592 .loc 1 860 0 + 1593 00a2 0020 movs r0, #0 + 1594 .L93: + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1595 .loc 1 861 0 + 1596 @ sp needed + 1597 .LVL160: + 1598 .LVL161: + 1599 00a4 70BD pop {r4, r5, r6, pc} + 1600 .LVL162: + 1601 .L97: + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 121 + + + 1602 .loc 1 804 0 + 1603 00a6 226A ldr r2, [r4, #32] + 1604 00a8 1248 ldr r0, .L107 + 1605 00aa D062 str r0, [r2, #44] + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1606 .loc 1 807 0 + 1607 00ac 226A ldr r2, [r4, #32] + 1608 00ae 1248 ldr r0, .L107+4 + 1609 00b0 5063 str r0, [r2, #52] + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1610 .loc 1 810 0 + 1611 00b2 2268 ldr r2, [r4] + 1612 00b4 3832 adds r2, r2, #56 + 1613 00b6 206A ldr r0, [r4, #32] + 1614 00b8 FFF7FEFF bl HAL_DMA_Start_IT + 1615 .LVL163: + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1616 .loc 1 813 0 + 1617 00bc 2268 ldr r2, [r4] + 1618 00be D168 ldr r1, [r2, #12] + 1619 00c0 8023 movs r3, #128 + 1620 00c2 DB00 lsls r3, r3, #3 + 1621 00c4 0B43 orrs r3, r1 + 1622 00c6 D360 str r3, [r2, #12] + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1623 .loc 1 815 0 + 1624 00c8 DDE7 b .L96 + 1625 .LVL164: + 1626 .L100: + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1627 .loc 1 820 0 + 1628 00ca 626A ldr r2, [r4, #36] + 1629 00cc 0948 ldr r0, .L107 + 1630 00ce D062 str r0, [r2, #44] + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1631 .loc 1 823 0 + 1632 00d0 626A ldr r2, [r4, #36] + 1633 00d2 0948 ldr r0, .L107+4 + 1634 00d4 5063 str r0, [r2, #52] + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1635 .loc 1 826 0 + 1636 00d6 2268 ldr r2, [r4] + 1637 00d8 3C32 adds r2, r2, #60 + 1638 00da 606A ldr r0, [r4, #36] + 1639 00dc FFF7FEFF bl HAL_DMA_Start_IT + 1640 .LVL165: + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1641 .loc 1 829 0 + 1642 00e0 2268 ldr r2, [r4] + 1643 00e2 D168 ldr r1, [r2, #12] + 1644 00e4 8023 movs r3, #128 + 1645 00e6 1B01 lsls r3, r3, #4 + 1646 00e8 0B43 orrs r3, r1 + 1647 00ea D360 str r3, [r2, #12] + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1648 .loc 1 831 0 + 1649 00ec CBE7 b .L96 + ARM GAS /tmp/ccH6KUTS.s page 122 + + + 1650 .LVL166: + 1651 .L102: + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1652 .loc 1 770 0 + 1653 00ee 0220 movs r0, #2 + 1654 .LVL167: + 1655 00f0 D8E7 b .L93 + 1656 .L108: + 1657 00f2 C046 .align 2 + 1658 .L107: + 1659 00f4 00000000 .word TIM_DMADelayPulseCplt + 1660 00f8 00000000 .word TIM_DMAError + 1661 .cfi_endproc + 1662 .LFE57: + 1664 .section .text.HAL_TIM_OC_Stop_DMA,"ax",%progbits + 1665 .align 1 + 1666 .global HAL_TIM_OC_Stop_DMA + 1667 .syntax unified + 1668 .code 16 + 1669 .thumb_func + 1670 .fpu softvfp + 1672 HAL_TIM_OC_Stop_DMA: + 1673 .LFB58: + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1674 .loc 1 875 0 + 1675 .cfi_startproc + 1676 @ args = 0, pretend = 0, frame = 0 + 1677 @ frame_needed = 0, uses_anonymous_args = 0 + 1678 .LVL168: + 1679 0000 10B5 push {r4, lr} + 1680 .LCFI12: + 1681 .cfi_def_cfa_offset 8 + 1682 .cfi_offset 4, -8 + 1683 .cfi_offset 14, -4 + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1684 .loc 1 879 0 + 1685 0002 0429 cmp r1, #4 + 1686 0004 28D0 beq .L111 + 1687 0006 09D9 bls .L117 + 1688 0008 0829 cmp r1, #8 + 1689 000a 2BD0 beq .L114 + 1690 000c 0C29 cmp r1, #12 + 1691 000e 0CD1 bne .L110 + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1692 .loc 1 905 0 + 1693 0010 0268 ldr r2, [r0] + 1694 0012 D368 ldr r3, [r2, #12] + 1695 0014 164C ldr r4, .L118 + 1696 0016 2340 ands r3, r4 + 1697 0018 D360 str r3, [r2, #12] + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1698 .loc 1 907 0 + 1699 001a 06E0 b .L110 + 1700 .L117: + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1701 .loc 1 879 0 + 1702 001c 0029 cmp r1, #0 + ARM GAS /tmp/ccH6KUTS.s page 123 + + + 1703 001e 04D1 bne .L110 + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1704 .loc 1 884 0 + 1705 0020 0268 ldr r2, [r0] + 1706 0022 D368 ldr r3, [r2, #12] + 1707 0024 134C ldr r4, .L118+4 + 1708 0026 2340 ands r3, r4 + 1709 0028 D360 str r3, [r2, #12] + 1710 .L110: + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1711 .loc 1 914 0 + 1712 002a 0368 ldr r3, [r0] + 1713 .LVL169: + 1714 .LBB178: + 1715 .LBB179: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1716 .loc 1 4947 0 + 1717 002c 0122 movs r2, #1 + 1718 002e 8A40 lsls r2, r2, r1 + 1719 0030 1100 movs r1, r2 + 1720 .LVL170: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1721 .loc 1 4950 0 + 1722 0032 1A6A ldr r2, [r3, #32] + 1723 0034 8A43 bics r2, r1 + 1724 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1725 .loc 1 4953 0 + 1726 0038 1A6A ldr r2, [r3, #32] + 1727 003a 1A62 str r2, [r3, #32] + 1728 .LVL171: + 1729 .LBE179: + 1730 .LBE178: + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1731 .loc 1 917 0 + 1732 003c 0368 ldr r3, [r0] + 1733 003e 196A ldr r1, [r3, #32] + 1734 0040 0D4A ldr r2, .L118+8 + 1735 0042 1142 tst r1, r2 + 1736 0044 03D1 bne .L116 + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1737 .loc 1 917 0 is_stmt 0 discriminator 1 + 1738 0046 1A68 ldr r2, [r3] + 1739 0048 0121 movs r1, #1 + 1740 004a 8A43 bics r2, r1 + 1741 004c 1A60 str r2, [r3] + 1742 .L116: + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1743 .loc 1 920 0 is_stmt 1 + 1744 004e 3523 movs r3, #53 + 1745 0050 0122 movs r2, #1 + 1746 0052 C254 strb r2, [r0, r3] + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1747 .loc 1 924 0 + 1748 0054 0020 movs r0, #0 + 1749 .LVL172: + 1750 @ sp needed + ARM GAS /tmp/ccH6KUTS.s page 124 + + + 1751 0056 10BD pop {r4, pc} + 1752 .LVL173: + 1753 .L111: + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1754 .loc 1 891 0 + 1755 0058 0268 ldr r2, [r0] + 1756 005a D368 ldr r3, [r2, #12] + 1757 005c 074C ldr r4, .L118+12 + 1758 005e 2340 ands r3, r4 + 1759 0060 D360 str r3, [r2, #12] + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1760 .loc 1 893 0 + 1761 0062 E2E7 b .L110 + 1762 .L114: + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1763 .loc 1 898 0 + 1764 0064 0268 ldr r2, [r0] + 1765 0066 D368 ldr r3, [r2, #12] + 1766 0068 054C ldr r4, .L118+16 + 1767 006a 2340 ands r3, r4 + 1768 006c D360 str r3, [r2, #12] + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1769 .loc 1 900 0 + 1770 006e DCE7 b .L110 + 1771 .L119: + 1772 .align 2 + 1773 .L118: + 1774 0070 FFEFFFFF .word -4097 + 1775 0074 FFFDFFFF .word -513 + 1776 0078 11110000 .word 4369 + 1777 007c FFFBFFFF .word -1025 + 1778 0080 FFF7FFFF .word -2049 + 1779 .cfi_endproc + 1780 .LFE58: + 1782 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits + 1783 .align 1 + 1784 .weak HAL_TIM_PWM_MspInit + 1785 .syntax unified + 1786 .code 16 + 1787 .thumb_func + 1788 .fpu softvfp + 1790 HAL_TIM_PWM_MspInit: + 1791 .LFB61: +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1792 .loc 1 1028 0 + 1793 .cfi_startproc + 1794 @ args = 0, pretend = 0, frame = 0 + 1795 @ frame_needed = 0, uses_anonymous_args = 0 + 1796 @ link register save eliminated. + 1797 .LVL174: +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1798 .loc 1 1035 0 + 1799 @ sp needed + 1800 0000 7047 bx lr + 1801 .cfi_endproc + 1802 .LFE61: + 1804 .section .text.HAL_TIM_PWM_Init,"ax",%progbits + ARM GAS /tmp/ccH6KUTS.s page 125 + + + 1805 .align 1 + 1806 .global HAL_TIM_PWM_Init + 1807 .syntax unified + 1808 .code 16 + 1809 .thumb_func + 1810 .fpu softvfp + 1812 HAL_TIM_PWM_Init: + 1813 .LFB59: + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 1814 .loc 1 960 0 + 1815 .cfi_startproc + 1816 @ args = 0, pretend = 0, frame = 0 + 1817 @ frame_needed = 0, uses_anonymous_args = 0 + 1818 .LVL175: + 1819 0000 70B5 push {r4, r5, r6, lr} + 1820 .LCFI13: + 1821 .cfi_def_cfa_offset 16 + 1822 .cfi_offset 4, -16 + 1823 .cfi_offset 5, -12 + 1824 .cfi_offset 6, -8 + 1825 .cfi_offset 14, -4 + 1826 0002 041E subs r4, r0, #0 + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1827 .loc 1 962 0 + 1828 0004 14D0 beq .L124 + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 1829 .loc 1 974 0 + 1830 0006 3523 movs r3, #53 + 1831 0008 C35C ldrb r3, [r0, r3] + 1832 000a 002B cmp r3, #0 + 1833 000c 0AD0 beq .L125 + 1834 .LVL176: + 1835 .L123: + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1836 .loc 1 984 0 + 1837 000e 3525 movs r5, #53 + 1838 0010 0223 movs r3, #2 + 1839 0012 6355 strb r3, [r4, r5] + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1840 .loc 1 987 0 + 1841 0014 211D adds r1, r4, #4 + 1842 0016 2068 ldr r0, [r4] + 1843 0018 FFF7FEFF bl TIM_Base_SetConfig + 1844 .LVL177: + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1845 .loc 1 990 0 + 1846 001c 0123 movs r3, #1 + 1847 001e 6355 strb r3, [r4, r5] + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1848 .loc 1 992 0 + 1849 0020 0020 movs r0, #0 + 1850 .L122: + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1851 .loc 1 993 0 + 1852 @ sp needed + 1853 .LVL178: + 1854 0022 70BD pop {r4, r5, r6, pc} + ARM GAS /tmp/ccH6KUTS.s page 126 + + + 1855 .LVL179: + 1856 .L125: + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1857 .loc 1 977 0 + 1858 0024 3433 adds r3, r3, #52 + 1859 0026 0022 movs r2, #0 + 1860 0028 C254 strb r2, [r0, r3] + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1861 .loc 1 980 0 + 1862 002a FFF7FEFF bl HAL_TIM_PWM_MspInit + 1863 .LVL180: + 1864 002e EEE7 b .L123 + 1865 .LVL181: + 1866 .L124: + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1867 .loc 1 964 0 + 1868 0030 0120 movs r0, #1 + 1869 .LVL182: + 1870 0032 F6E7 b .L122 + 1871 .cfi_endproc + 1872 .LFE59: + 1874 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits + 1875 .align 1 + 1876 .weak HAL_TIM_PWM_MspDeInit + 1877 .syntax unified + 1878 .code 16 + 1879 .thumb_func + 1880 .fpu softvfp + 1882 HAL_TIM_PWM_MspDeInit: + 1883 .LFB62: +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1884 .loc 1 1043 0 + 1885 .cfi_startproc + 1886 @ args = 0, pretend = 0, frame = 0 + 1887 @ frame_needed = 0, uses_anonymous_args = 0 + 1888 @ link register save eliminated. + 1889 .LVL183: +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1890 .loc 1 1050 0 + 1891 @ sp needed + 1892 0000 7047 bx lr + 1893 .cfi_endproc + 1894 .LFE62: + 1896 .section .text.HAL_TIM_PWM_DeInit,"ax",%progbits + 1897 .align 1 + 1898 .global HAL_TIM_PWM_DeInit + 1899 .syntax unified + 1900 .code 16 + 1901 .thumb_func + 1902 .fpu softvfp + 1904 HAL_TIM_PWM_DeInit: + 1905 .LFB60: +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1906 .loc 1 1001 0 + 1907 .cfi_startproc + 1908 @ args = 0, pretend = 0, frame = 0 + 1909 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccH6KUTS.s page 127 + + + 1910 .LVL184: + 1911 0000 10B5 push {r4, lr} + 1912 .LCFI14: + 1913 .cfi_def_cfa_offset 8 + 1914 .cfi_offset 4, -8 + 1915 .cfi_offset 14, -4 + 1916 0002 0400 movs r4, r0 +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1917 .loc 1 1005 0 + 1918 0004 3523 movs r3, #53 + 1919 0006 0222 movs r2, #2 + 1920 0008 C254 strb r2, [r0, r3] +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1921 .loc 1 1008 0 + 1922 000a 0368 ldr r3, [r0] + 1923 000c 196A ldr r1, [r3, #32] + 1924 000e 084A ldr r2, .L129 + 1925 0010 1142 tst r1, r2 + 1926 0012 03D1 bne .L128 +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1927 .loc 1 1008 0 is_stmt 0 discriminator 1 + 1928 0014 1A68 ldr r2, [r3] + 1929 0016 0121 movs r1, #1 + 1930 0018 8A43 bics r2, r1 + 1931 001a 1A60 str r2, [r3] + 1932 .L128: +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1933 .loc 1 1011 0 is_stmt 1 + 1934 001c 2000 movs r0, r4 + 1935 .LVL185: + 1936 001e FFF7FEFF bl HAL_TIM_PWM_MspDeInit + 1937 .LVL186: +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1938 .loc 1 1014 0 + 1939 0022 0023 movs r3, #0 + 1940 0024 3522 movs r2, #53 + 1941 0026 A354 strb r3, [r4, r2] +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1942 .loc 1 1017 0 + 1943 0028 013A subs r2, r2, #1 + 1944 002a A354 strb r3, [r4, r2] +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1945 .loc 1 1020 0 + 1946 002c 0020 movs r0, #0 + 1947 @ sp needed + 1948 .LVL187: + 1949 002e 10BD pop {r4, pc} + 1950 .L130: + 1951 .align 2 + 1952 .L129: + 1953 0030 11110000 .word 4369 + 1954 .cfi_endproc + 1955 .LFE60: + 1957 .section .text.HAL_TIM_PWM_Start,"ax",%progbits + 1958 .align 1 + 1959 .global HAL_TIM_PWM_Start + 1960 .syntax unified + ARM GAS /tmp/ccH6KUTS.s page 128 + + + 1961 .code 16 + 1962 .thumb_func + 1963 .fpu softvfp + 1965 HAL_TIM_PWM_Start: + 1966 .LFB63: +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 1967 .loc 1 1064 0 + 1968 .cfi_startproc + 1969 @ args = 0, pretend = 0, frame = 0 + 1970 @ frame_needed = 0, uses_anonymous_args = 0 + 1971 .LVL188: + 1972 0000 10B5 push {r4, lr} + 1973 .LCFI15: + 1974 .cfi_def_cfa_offset 8 + 1975 .cfi_offset 4, -8 + 1976 .cfi_offset 14, -4 +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1977 .loc 1 1069 0 + 1978 0002 0368 ldr r3, [r0] + 1979 .LVL189: + 1980 .LBB180: + 1981 .LBB181: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1982 .loc 1 4947 0 + 1983 0004 0124 movs r4, #1 + 1984 0006 2200 movs r2, r4 + 1985 0008 8A40 lsls r2, r2, r1 + 1986 .LVL190: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 1987 .loc 1 4950 0 + 1988 000a 196A ldr r1, [r3, #32] + 1989 .LVL191: + 1990 000c 9143 bics r1, r2 + 1991 000e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 1992 .loc 1 4953 0 + 1993 0010 196A ldr r1, [r3, #32] + 1994 0012 0A43 orrs r2, r1 + 1995 .LVL192: + 1996 0014 1A62 str r2, [r3, #32] + 1997 .LVL193: + 1998 .LBE181: + 1999 .LBE180: +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2000 .loc 1 1072 0 + 2001 0016 0268 ldr r2, [r0] + 2002 0018 1368 ldr r3, [r2] + 2003 001a 2343 orrs r3, r4 + 2004 001c 1360 str r3, [r2] +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2005 .loc 1 1076 0 + 2006 001e 0020 movs r0, #0 + 2007 .LVL194: + 2008 @ sp needed + 2009 0020 10BD pop {r4, pc} + 2010 .cfi_endproc + 2011 .LFE63: + ARM GAS /tmp/ccH6KUTS.s page 129 + + + 2013 .section .text.HAL_TIM_PWM_Stop,"ax",%progbits + 2014 .align 1 + 2015 .global HAL_TIM_PWM_Stop + 2016 .syntax unified + 2017 .code 16 + 2018 .thumb_func + 2019 .fpu softvfp + 2021 HAL_TIM_PWM_Stop: + 2022 .LFB64: +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2023 .loc 1 1090 0 + 2024 .cfi_startproc + 2025 @ args = 0, pretend = 0, frame = 0 + 2026 @ frame_needed = 0, uses_anonymous_args = 0 + 2027 @ link register save eliminated. + 2028 .LVL195: +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2029 .loc 1 1095 0 + 2030 0000 0368 ldr r3, [r0] + 2031 .LVL196: + 2032 .LBB182: + 2033 .LBB183: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2034 .loc 1 4947 0 + 2035 0002 0122 movs r2, #1 + 2036 0004 8A40 lsls r2, r2, r1 + 2037 0006 1100 movs r1, r2 + 2038 .LVL197: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2039 .loc 1 4950 0 + 2040 0008 1A6A ldr r2, [r3, #32] + 2041 000a 8A43 bics r2, r1 + 2042 000c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2043 .loc 1 4953 0 + 2044 000e 1A6A ldr r2, [r3, #32] + 2045 0010 1A62 str r2, [r3, #32] + 2046 .LVL198: + 2047 .LBE183: + 2048 .LBE182: +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2049 .loc 1 1098 0 + 2050 0012 0368 ldr r3, [r0] + 2051 0014 196A ldr r1, [r3, #32] + 2052 0016 064A ldr r2, .L134 + 2053 0018 1142 tst r1, r2 + 2054 001a 03D1 bne .L133 +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2055 .loc 1 1098 0 is_stmt 0 discriminator 1 + 2056 001c 1A68 ldr r2, [r3] + 2057 001e 0121 movs r1, #1 + 2058 0020 8A43 bics r2, r1 + 2059 0022 1A60 str r2, [r3] + 2060 .L133: +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2061 .loc 1 1101 0 is_stmt 1 + 2062 0024 3523 movs r3, #53 + ARM GAS /tmp/ccH6KUTS.s page 130 + + + 2063 0026 0122 movs r2, #1 + 2064 0028 C254 strb r2, [r0, r3] +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2065 .loc 1 1105 0 + 2066 002a 0020 movs r0, #0 + 2067 .LVL199: + 2068 @ sp needed + 2069 002c 7047 bx lr + 2070 .L135: + 2071 002e C046 .align 2 + 2072 .L134: + 2073 0030 11110000 .word 4369 + 2074 .cfi_endproc + 2075 .LFE64: + 2077 .section .text.HAL_TIM_PWM_Start_IT,"ax",%progbits + 2078 .align 1 + 2079 .global HAL_TIM_PWM_Start_IT + 2080 .syntax unified + 2081 .code 16 + 2082 .thumb_func + 2083 .fpu softvfp + 2085 HAL_TIM_PWM_Start_IT: + 2086 .LFB65: +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2087 .loc 1 1119 0 + 2088 .cfi_startproc + 2089 @ args = 0, pretend = 0, frame = 0 + 2090 @ frame_needed = 0, uses_anonymous_args = 0 + 2091 .LVL200: + 2092 0000 10B5 push {r4, lr} + 2093 .LCFI16: + 2094 .cfi_def_cfa_offset 8 + 2095 .cfi_offset 4, -8 + 2096 .cfi_offset 14, -4 +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2097 .loc 1 1123 0 + 2098 0002 0429 cmp r1, #4 + 2099 0004 21D0 beq .L138 + 2100 0006 09D9 bls .L143 + 2101 0008 0829 cmp r1, #8 + 2102 000a 24D0 beq .L141 + 2103 000c 0C29 cmp r1, #12 + 2104 000e 0CD1 bne .L137 +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2105 .loc 1 1149 0 + 2106 0010 0268 ldr r2, [r0] + 2107 0012 D368 ldr r3, [r2, #12] + 2108 0014 1024 movs r4, #16 + 2109 0016 2343 orrs r3, r4 + 2110 0018 D360 str r3, [r2, #12] +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2111 .loc 1 1151 0 + 2112 001a 06E0 b .L137 + 2113 .L143: +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2114 .loc 1 1123 0 + 2115 001c 0029 cmp r1, #0 + ARM GAS /tmp/ccH6KUTS.s page 131 + + + 2116 001e 04D1 bne .L137 +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2117 .loc 1 1128 0 + 2118 0020 0268 ldr r2, [r0] + 2119 0022 D368 ldr r3, [r2, #12] + 2120 0024 0224 movs r4, #2 + 2121 0026 2343 orrs r3, r4 + 2122 0028 D360 str r3, [r2, #12] + 2123 .L137: +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2124 .loc 1 1158 0 + 2125 002a 0368 ldr r3, [r0] + 2126 .LVL201: + 2127 .LBB184: + 2128 .LBB185: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2129 .loc 1 4947 0 + 2130 002c 0124 movs r4, #1 + 2131 002e 2200 movs r2, r4 + 2132 0030 8A40 lsls r2, r2, r1 + 2133 .LVL202: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2134 .loc 1 4950 0 + 2135 0032 196A ldr r1, [r3, #32] + 2136 .LVL203: + 2137 0034 9143 bics r1, r2 + 2138 0036 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2139 .loc 1 4953 0 + 2140 0038 196A ldr r1, [r3, #32] + 2141 003a 0A43 orrs r2, r1 + 2142 .LVL204: + 2143 003c 1A62 str r2, [r3, #32] + 2144 .LVL205: + 2145 .LBE185: + 2146 .LBE184: +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2147 .loc 1 1161 0 + 2148 003e 0268 ldr r2, [r0] + 2149 0040 1368 ldr r3, [r2] + 2150 0042 2343 orrs r3, r4 + 2151 0044 1360 str r3, [r2] +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2152 .loc 1 1165 0 + 2153 0046 0020 movs r0, #0 + 2154 .LVL206: + 2155 @ sp needed + 2156 0048 10BD pop {r4, pc} + 2157 .LVL207: + 2158 .L138: +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2159 .loc 1 1135 0 + 2160 004a 0268 ldr r2, [r0] + 2161 004c D368 ldr r3, [r2, #12] + 2162 004e 0424 movs r4, #4 + 2163 0050 2343 orrs r3, r4 + 2164 0052 D360 str r3, [r2, #12] + ARM GAS /tmp/ccH6KUTS.s page 132 + + +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2165 .loc 1 1137 0 + 2166 0054 E9E7 b .L137 + 2167 .L141: +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2168 .loc 1 1142 0 + 2169 0056 0268 ldr r2, [r0] + 2170 0058 D368 ldr r3, [r2, #12] + 2171 005a 0824 movs r4, #8 + 2172 005c 2343 orrs r3, r4 + 2173 005e D360 str r3, [r2, #12] +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2174 .loc 1 1144 0 + 2175 0060 E3E7 b .L137 + 2176 .cfi_endproc + 2177 .LFE65: + 2179 .section .text.HAL_TIM_PWM_Stop_IT,"ax",%progbits + 2180 .align 1 + 2181 .global HAL_TIM_PWM_Stop_IT + 2182 .syntax unified + 2183 .code 16 + 2184 .thumb_func + 2185 .fpu softvfp + 2187 HAL_TIM_PWM_Stop_IT: + 2188 .LFB66: +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2189 .loc 1 1179 0 + 2190 .cfi_startproc + 2191 @ args = 0, pretend = 0, frame = 0 + 2192 @ frame_needed = 0, uses_anonymous_args = 0 + 2193 .LVL208: + 2194 0000 10B5 push {r4, lr} + 2195 .LCFI17: + 2196 .cfi_def_cfa_offset 8 + 2197 .cfi_offset 4, -8 + 2198 .cfi_offset 14, -4 +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2199 .loc 1 1183 0 + 2200 0002 0429 cmp r1, #4 + 2201 0004 25D0 beq .L146 + 2202 0006 09D9 bls .L152 + 2203 0008 0829 cmp r1, #8 + 2204 000a 28D0 beq .L149 + 2205 000c 0C29 cmp r1, #12 + 2206 000e 0CD1 bne .L145 +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2207 .loc 1 1209 0 + 2208 0010 0268 ldr r2, [r0] + 2209 0012 D368 ldr r3, [r2, #12] + 2210 0014 1024 movs r4, #16 + 2211 0016 A343 bics r3, r4 + 2212 0018 D360 str r3, [r2, #12] +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2213 .loc 1 1211 0 + 2214 001a 06E0 b .L145 + 2215 .L152: +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 133 + + + 2216 .loc 1 1183 0 + 2217 001c 0029 cmp r1, #0 + 2218 001e 04D1 bne .L145 +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2219 .loc 1 1188 0 + 2220 0020 0268 ldr r2, [r0] + 2221 0022 D368 ldr r3, [r2, #12] + 2222 0024 0224 movs r4, #2 + 2223 0026 A343 bics r3, r4 + 2224 0028 D360 str r3, [r2, #12] + 2225 .L145: +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2226 .loc 1 1218 0 + 2227 002a 0368 ldr r3, [r0] + 2228 .LVL209: + 2229 .LBB186: + 2230 .LBB187: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2231 .loc 1 4947 0 + 2232 002c 0122 movs r2, #1 + 2233 002e 8A40 lsls r2, r2, r1 + 2234 0030 1100 movs r1, r2 + 2235 .LVL210: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2236 .loc 1 4950 0 + 2237 0032 1A6A ldr r2, [r3, #32] + 2238 0034 8A43 bics r2, r1 + 2239 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2240 .loc 1 4953 0 + 2241 0038 1A6A ldr r2, [r3, #32] + 2242 003a 1A62 str r2, [r3, #32] + 2243 .LVL211: + 2244 .LBE187: + 2245 .LBE186: +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2246 .loc 1 1221 0 + 2247 003c 0368 ldr r3, [r0] + 2248 003e 196A ldr r1, [r3, #32] + 2249 0040 0A4A ldr r2, .L153 + 2250 0042 1142 tst r1, r2 + 2251 0044 03D1 bne .L151 +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2252 .loc 1 1221 0 is_stmt 0 discriminator 1 + 2253 0046 1A68 ldr r2, [r3] + 2254 0048 0121 movs r1, #1 + 2255 004a 8A43 bics r2, r1 + 2256 004c 1A60 str r2, [r3] + 2257 .L151: +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2258 .loc 1 1225 0 is_stmt 1 + 2259 004e 0020 movs r0, #0 + 2260 .LVL212: + 2261 @ sp needed + 2262 0050 10BD pop {r4, pc} + 2263 .LVL213: + 2264 .L146: + ARM GAS /tmp/ccH6KUTS.s page 134 + + +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2265 .loc 1 1195 0 + 2266 0052 0268 ldr r2, [r0] + 2267 0054 D368 ldr r3, [r2, #12] + 2268 0056 0424 movs r4, #4 + 2269 0058 A343 bics r3, r4 + 2270 005a D360 str r3, [r2, #12] +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2271 .loc 1 1197 0 + 2272 005c E5E7 b .L145 + 2273 .L149: +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2274 .loc 1 1202 0 + 2275 005e 0268 ldr r2, [r0] + 2276 0060 D368 ldr r3, [r2, #12] + 2277 0062 0824 movs r4, #8 + 2278 0064 A343 bics r3, r4 + 2279 0066 D360 str r3, [r2, #12] +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2280 .loc 1 1204 0 + 2281 0068 DFE7 b .L145 + 2282 .L154: + 2283 006a C046 .align 2 + 2284 .L153: + 2285 006c 11110000 .word 4369 + 2286 .cfi_endproc + 2287 .LFE66: + 2289 .section .text.HAL_TIM_PWM_Start_DMA,"ax",%progbits + 2290 .align 1 + 2291 .global HAL_TIM_PWM_Start_DMA + 2292 .syntax unified + 2293 .code 16 + 2294 .thumb_func + 2295 .fpu softvfp + 2297 HAL_TIM_PWM_Start_DMA: + 2298 .LFB67: +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2299 .loc 1 1242 0 + 2300 .cfi_startproc + 2301 @ args = 0, pretend = 0, frame = 0 + 2302 @ frame_needed = 0, uses_anonymous_args = 0 + 2303 .LVL214: + 2304 0000 70B5 push {r4, r5, r6, lr} + 2305 .LCFI18: + 2306 .cfi_def_cfa_offset 16 + 2307 .cfi_offset 4, -16 + 2308 .cfi_offset 5, -12 + 2309 .cfi_offset 6, -8 + 2310 .cfi_offset 14, -4 + 2311 0002 0400 movs r4, r0 + 2312 0004 0D00 movs r5, r1 + 2313 0006 1100 movs r1, r2 + 2314 .LVL215: +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2315 .loc 1 1246 0 + 2316 0008 3522 movs r2, #53 + 2317 .LVL216: + ARM GAS /tmp/ccH6KUTS.s page 135 + + + 2318 000a 825C ldrb r2, [r0, r2] + 2319 000c 022A cmp r2, #2 + 2320 000e 00D1 bne .LCB2143 + 2321 0010 6DE0 b .L165 @long jump + 2322 .LCB2143: +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2323 .loc 1 1250 0 + 2324 0012 3522 movs r2, #53 + 2325 0014 825C ldrb r2, [r0, r2] + 2326 0016 012A cmp r2, #1 + 2327 0018 18D0 beq .L167 + 2328 .LVL217: + 2329 .L157: +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2330 .loc 1 1261 0 + 2331 001a 042D cmp r5, #4 + 2332 001c 43D0 beq .L160 + 2333 001e 1FD9 bls .L168 + 2334 0020 082D cmp r5, #8 + 2335 0022 52D0 beq .L163 + 2336 0024 0C2D cmp r5, #12 + 2337 0026 2ED1 bne .L159 +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2338 .loc 1 1314 0 + 2339 0028 A26A ldr r2, [r4, #40] + 2340 002a 3248 ldr r0, .L170 + 2341 002c D062 str r0, [r2, #44] +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2342 .loc 1 1317 0 + 2343 002e A26A ldr r2, [r4, #40] + 2344 0030 3148 ldr r0, .L170+4 + 2345 0032 5063 str r0, [r2, #52] +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2346 .loc 1 1320 0 + 2347 0034 2268 ldr r2, [r4] + 2348 0036 4032 adds r2, r2, #64 + 2349 0038 A06A ldr r0, [r4, #40] + 2350 003a FFF7FEFF bl HAL_DMA_Start_IT + 2351 .LVL218: +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2352 .loc 1 1323 0 + 2353 003e 2268 ldr r2, [r4] + 2354 0040 D168 ldr r1, [r2, #12] + 2355 0042 8023 movs r3, #128 + 2356 0044 5B01 lsls r3, r3, #5 + 2357 0046 0B43 orrs r3, r1 + 2358 0048 D360 str r3, [r2, #12] +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2359 .loc 1 1325 0 + 2360 004a 1CE0 b .L159 + 2361 .LVL219: + 2362 .L167: +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2363 .loc 1 1252 0 + 2364 004c 0029 cmp r1, #0 + 2365 004e 03D0 beq .L169 + 2366 .L158: + ARM GAS /tmp/ccH6KUTS.s page 136 + + +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2367 .loc 1 1258 0 + 2368 0050 3522 movs r2, #53 + 2369 0052 0220 movs r0, #2 + 2370 .LVL220: + 2371 0054 A054 strb r0, [r4, r2] + 2372 0056 E0E7 b .L157 + 2373 .LVL221: + 2374 .L169: +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2375 .loc 1 1252 0 discriminator 1 + 2376 0058 002B cmp r3, #0 + 2377 005a F9D0 beq .L158 +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2378 .loc 1 1254 0 + 2379 005c 0120 movs r0, #1 + 2380 .LVL222: + 2381 005e 21E0 b .L156 + 2382 .L168: +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2383 .loc 1 1261 0 + 2384 0060 002D cmp r5, #0 + 2385 0062 10D1 bne .L159 +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2386 .loc 1 1266 0 + 2387 0064 E269 ldr r2, [r4, #28] + 2388 0066 2348 ldr r0, .L170 + 2389 0068 D062 str r0, [r2, #44] +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2390 .loc 1 1269 0 + 2391 006a E269 ldr r2, [r4, #28] + 2392 006c 2248 ldr r0, .L170+4 + 2393 006e 5063 str r0, [r2, #52] +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2394 .loc 1 1272 0 + 2395 0070 2268 ldr r2, [r4] + 2396 0072 3432 adds r2, r2, #52 + 2397 0074 E069 ldr r0, [r4, #28] + 2398 0076 FFF7FEFF bl HAL_DMA_Start_IT + 2399 .LVL223: +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2400 .loc 1 1275 0 + 2401 007a 2268 ldr r2, [r4] + 2402 007c D168 ldr r1, [r2, #12] + 2403 007e 8023 movs r3, #128 + 2404 0080 9B00 lsls r3, r3, #2 + 2405 0082 0B43 orrs r3, r1 + 2406 0084 D360 str r3, [r2, #12] + 2407 .L159: +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2408 .loc 1 1332 0 + 2409 0086 2368 ldr r3, [r4] + 2410 .LVL224: + 2411 .LBB188: + 2412 .LBB189: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2413 .loc 1 4947 0 + ARM GAS /tmp/ccH6KUTS.s page 137 + + + 2414 0088 0120 movs r0, #1 + 2415 008a 0200 movs r2, r0 + 2416 008c AA40 lsls r2, r2, r5 + 2417 .LVL225: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2418 .loc 1 4950 0 + 2419 008e 196A ldr r1, [r3, #32] + 2420 0090 9143 bics r1, r2 + 2421 0092 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2422 .loc 1 4953 0 + 2423 0094 196A ldr r1, [r3, #32] + 2424 0096 0A43 orrs r2, r1 + 2425 .LVL226: + 2426 0098 1A62 str r2, [r3, #32] + 2427 .LVL227: + 2428 .LBE189: + 2429 .LBE188: +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2430 .loc 1 1335 0 + 2431 009a 2268 ldr r2, [r4] + 2432 009c 1368 ldr r3, [r2] + 2433 009e 0343 orrs r3, r0 + 2434 00a0 1360 str r3, [r2] +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2435 .loc 1 1338 0 + 2436 00a2 0020 movs r0, #0 + 2437 .L156: +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2438 .loc 1 1339 0 + 2439 @ sp needed + 2440 .LVL228: + 2441 .LVL229: + 2442 00a4 70BD pop {r4, r5, r6, pc} + 2443 .LVL230: + 2444 .L160: +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2445 .loc 1 1282 0 + 2446 00a6 226A ldr r2, [r4, #32] + 2447 00a8 1248 ldr r0, .L170 + 2448 00aa D062 str r0, [r2, #44] +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2449 .loc 1 1285 0 + 2450 00ac 226A ldr r2, [r4, #32] + 2451 00ae 1248 ldr r0, .L170+4 + 2452 00b0 5063 str r0, [r2, #52] +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2453 .loc 1 1288 0 + 2454 00b2 2268 ldr r2, [r4] + 2455 00b4 3832 adds r2, r2, #56 + 2456 00b6 206A ldr r0, [r4, #32] + 2457 00b8 FFF7FEFF bl HAL_DMA_Start_IT + 2458 .LVL231: +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2459 .loc 1 1291 0 + 2460 00bc 2268 ldr r2, [r4] + 2461 00be D168 ldr r1, [r2, #12] + ARM GAS /tmp/ccH6KUTS.s page 138 + + + 2462 00c0 8023 movs r3, #128 + 2463 00c2 DB00 lsls r3, r3, #3 + 2464 00c4 0B43 orrs r3, r1 + 2465 00c6 D360 str r3, [r2, #12] +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2466 .loc 1 1293 0 + 2467 00c8 DDE7 b .L159 + 2468 .LVL232: + 2469 .L163: +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2470 .loc 1 1298 0 + 2471 00ca 626A ldr r2, [r4, #36] + 2472 00cc 0948 ldr r0, .L170 + 2473 00ce D062 str r0, [r2, #44] +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2474 .loc 1 1301 0 + 2475 00d0 626A ldr r2, [r4, #36] + 2476 00d2 0948 ldr r0, .L170+4 + 2477 00d4 5063 str r0, [r2, #52] +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2478 .loc 1 1304 0 + 2479 00d6 2268 ldr r2, [r4] + 2480 00d8 3C32 adds r2, r2, #60 + 2481 00da 606A ldr r0, [r4, #36] + 2482 00dc FFF7FEFF bl HAL_DMA_Start_IT + 2483 .LVL233: +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2484 .loc 1 1307 0 + 2485 00e0 2268 ldr r2, [r4] + 2486 00e2 D168 ldr r1, [r2, #12] + 2487 00e4 8023 movs r3, #128 + 2488 00e6 1B01 lsls r3, r3, #4 + 2489 00e8 0B43 orrs r3, r1 + 2490 00ea D360 str r3, [r2, #12] +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2491 .loc 1 1309 0 + 2492 00ec CBE7 b .L159 + 2493 .LVL234: + 2494 .L165: +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2495 .loc 1 1248 0 + 2496 00ee 0220 movs r0, #2 + 2497 .LVL235: + 2498 00f0 D8E7 b .L156 + 2499 .L171: + 2500 00f2 C046 .align 2 + 2501 .L170: + 2502 00f4 00000000 .word TIM_DMADelayPulseCplt + 2503 00f8 00000000 .word TIM_DMAError + 2504 .cfi_endproc + 2505 .LFE67: + 2507 .section .text.HAL_TIM_PWM_Stop_DMA,"ax",%progbits + 2508 .align 1 + 2509 .global HAL_TIM_PWM_Stop_DMA + 2510 .syntax unified + 2511 .code 16 + 2512 .thumb_func + ARM GAS /tmp/ccH6KUTS.s page 139 + + + 2513 .fpu softvfp + 2515 HAL_TIM_PWM_Stop_DMA: + 2516 .LFB68: +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2517 .loc 1 1353 0 + 2518 .cfi_startproc + 2519 @ args = 0, pretend = 0, frame = 0 + 2520 @ frame_needed = 0, uses_anonymous_args = 0 + 2521 .LVL236: + 2522 0000 10B5 push {r4, lr} + 2523 .LCFI19: + 2524 .cfi_def_cfa_offset 8 + 2525 .cfi_offset 4, -8 + 2526 .cfi_offset 14, -4 +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2527 .loc 1 1357 0 + 2528 0002 0429 cmp r1, #4 + 2529 0004 28D0 beq .L174 + 2530 0006 09D9 bls .L180 + 2531 0008 0829 cmp r1, #8 + 2532 000a 2BD0 beq .L177 + 2533 000c 0C29 cmp r1, #12 + 2534 000e 0CD1 bne .L173 +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2535 .loc 1 1383 0 + 2536 0010 0268 ldr r2, [r0] + 2537 0012 D368 ldr r3, [r2, #12] + 2538 0014 164C ldr r4, .L181 + 2539 0016 2340 ands r3, r4 + 2540 0018 D360 str r3, [r2, #12] +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2541 .loc 1 1385 0 + 2542 001a 06E0 b .L173 + 2543 .L180: +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2544 .loc 1 1357 0 + 2545 001c 0029 cmp r1, #0 + 2546 001e 04D1 bne .L173 +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2547 .loc 1 1362 0 + 2548 0020 0268 ldr r2, [r0] + 2549 0022 D368 ldr r3, [r2, #12] + 2550 0024 134C ldr r4, .L181+4 + 2551 0026 2340 ands r3, r4 + 2552 0028 D360 str r3, [r2, #12] + 2553 .L173: +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2554 .loc 1 1392 0 + 2555 002a 0368 ldr r3, [r0] + 2556 .LVL237: + 2557 .LBB190: + 2558 .LBB191: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2559 .loc 1 4947 0 + 2560 002c 0122 movs r2, #1 + 2561 002e 8A40 lsls r2, r2, r1 + 2562 0030 1100 movs r1, r2 + ARM GAS /tmp/ccH6KUTS.s page 140 + + + 2563 .LVL238: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2564 .loc 1 4950 0 + 2565 0032 1A6A ldr r2, [r3, #32] + 2566 0034 8A43 bics r2, r1 + 2567 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2568 .loc 1 4953 0 + 2569 0038 1A6A ldr r2, [r3, #32] + 2570 003a 1A62 str r2, [r3, #32] + 2571 .LVL239: + 2572 .LBE191: + 2573 .LBE190: +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2574 .loc 1 1395 0 + 2575 003c 0368 ldr r3, [r0] + 2576 003e 196A ldr r1, [r3, #32] + 2577 0040 0D4A ldr r2, .L181+8 + 2578 0042 1142 tst r1, r2 + 2579 0044 03D1 bne .L179 +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2580 .loc 1 1395 0 is_stmt 0 discriminator 1 + 2581 0046 1A68 ldr r2, [r3] + 2582 0048 0121 movs r1, #1 + 2583 004a 8A43 bics r2, r1 + 2584 004c 1A60 str r2, [r3] + 2585 .L179: +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2586 .loc 1 1398 0 is_stmt 1 + 2587 004e 3523 movs r3, #53 + 2588 0050 0122 movs r2, #1 + 2589 0052 C254 strb r2, [r0, r3] +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2590 .loc 1 1402 0 + 2591 0054 0020 movs r0, #0 + 2592 .LVL240: + 2593 @ sp needed + 2594 0056 10BD pop {r4, pc} + 2595 .LVL241: + 2596 .L174: +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2597 .loc 1 1369 0 + 2598 0058 0268 ldr r2, [r0] + 2599 005a D368 ldr r3, [r2, #12] + 2600 005c 074C ldr r4, .L181+12 + 2601 005e 2340 ands r3, r4 + 2602 0060 D360 str r3, [r2, #12] +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2603 .loc 1 1371 0 + 2604 0062 E2E7 b .L173 + 2605 .L177: +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2606 .loc 1 1376 0 + 2607 0064 0268 ldr r2, [r0] + 2608 0066 D368 ldr r3, [r2, #12] + 2609 0068 054C ldr r4, .L181+16 + 2610 006a 2340 ands r3, r4 + ARM GAS /tmp/ccH6KUTS.s page 141 + + + 2611 006c D360 str r3, [r2, #12] +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2612 .loc 1 1378 0 + 2613 006e DCE7 b .L173 + 2614 .L182: + 2615 .align 2 + 2616 .L181: + 2617 0070 FFEFFFFF .word -4097 + 2618 0074 FFFDFFFF .word -513 + 2619 0078 11110000 .word 4369 + 2620 007c FFFBFFFF .word -1025 + 2621 0080 FFF7FFFF .word -2049 + 2622 .cfi_endproc + 2623 .LFE68: + 2625 .section .text.HAL_TIM_IC_MspInit,"ax",%progbits + 2626 .align 1 + 2627 .weak HAL_TIM_IC_MspInit + 2628 .syntax unified + 2629 .code 16 + 2630 .thumb_func + 2631 .fpu softvfp + 2633 HAL_TIM_IC_MspInit: + 2634 .LFB71: +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2635 .loc 1 1504 0 + 2636 .cfi_startproc + 2637 @ args = 0, pretend = 0, frame = 0 + 2638 @ frame_needed = 0, uses_anonymous_args = 0 + 2639 @ link register save eliminated. + 2640 .LVL242: +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2641 .loc 1 1511 0 + 2642 @ sp needed + 2643 0000 7047 bx lr + 2644 .cfi_endproc + 2645 .LFE71: + 2647 .section .text.HAL_TIM_IC_Init,"ax",%progbits + 2648 .align 1 + 2649 .global HAL_TIM_IC_Init + 2650 .syntax unified + 2651 .code 16 + 2652 .thumb_func + 2653 .fpu softvfp + 2655 HAL_TIM_IC_Init: + 2656 .LFB69: +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 2657 .loc 1 1436 0 + 2658 .cfi_startproc + 2659 @ args = 0, pretend = 0, frame = 0 + 2660 @ frame_needed = 0, uses_anonymous_args = 0 + 2661 .LVL243: + 2662 0000 70B5 push {r4, r5, r6, lr} + 2663 .LCFI20: + 2664 .cfi_def_cfa_offset 16 + 2665 .cfi_offset 4, -16 + 2666 .cfi_offset 5, -12 + 2667 .cfi_offset 6, -8 + ARM GAS /tmp/ccH6KUTS.s page 142 + + + 2668 .cfi_offset 14, -4 + 2669 0002 041E subs r4, r0, #0 +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2670 .loc 1 1438 0 + 2671 0004 14D0 beq .L187 +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2672 .loc 1 1450 0 + 2673 0006 3523 movs r3, #53 + 2674 0008 C35C ldrb r3, [r0, r3] + 2675 000a 002B cmp r3, #0 + 2676 000c 0AD0 beq .L188 + 2677 .LVL244: + 2678 .L186: +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2679 .loc 1 1460 0 + 2680 000e 3525 movs r5, #53 + 2681 0010 0223 movs r3, #2 + 2682 0012 6355 strb r3, [r4, r5] +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2683 .loc 1 1463 0 + 2684 0014 211D adds r1, r4, #4 + 2685 0016 2068 ldr r0, [r4] + 2686 0018 FFF7FEFF bl TIM_Base_SetConfig + 2687 .LVL245: +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2688 .loc 1 1466 0 + 2689 001c 0123 movs r3, #1 + 2690 001e 6355 strb r3, [r4, r5] +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2691 .loc 1 1468 0 + 2692 0020 0020 movs r0, #0 + 2693 .L185: +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2694 .loc 1 1469 0 + 2695 @ sp needed + 2696 .LVL246: + 2697 0022 70BD pop {r4, r5, r6, pc} + 2698 .LVL247: + 2699 .L188: +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2700 .loc 1 1453 0 + 2701 0024 3433 adds r3, r3, #52 + 2702 0026 0022 movs r2, #0 + 2703 0028 C254 strb r2, [r0, r3] +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2704 .loc 1 1456 0 + 2705 002a FFF7FEFF bl HAL_TIM_IC_MspInit + 2706 .LVL248: + 2707 002e EEE7 b .L186 + 2708 .LVL249: + 2709 .L187: +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2710 .loc 1 1440 0 + 2711 0030 0120 movs r0, #1 + 2712 .LVL250: + 2713 0032 F6E7 b .L185 + 2714 .cfi_endproc + ARM GAS /tmp/ccH6KUTS.s page 143 + + + 2715 .LFE69: + 2717 .section .text.HAL_TIM_IC_MspDeInit,"ax",%progbits + 2718 .align 1 + 2719 .weak HAL_TIM_IC_MspDeInit + 2720 .syntax unified + 2721 .code 16 + 2722 .thumb_func + 2723 .fpu softvfp + 2725 HAL_TIM_IC_MspDeInit: + 2726 .LFB72: +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2727 .loc 1 1519 0 + 2728 .cfi_startproc + 2729 @ args = 0, pretend = 0, frame = 0 + 2730 @ frame_needed = 0, uses_anonymous_args = 0 + 2731 @ link register save eliminated. + 2732 .LVL251: +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 2733 .loc 1 1526 0 + 2734 @ sp needed + 2735 0000 7047 bx lr + 2736 .cfi_endproc + 2737 .LFE72: + 2739 .section .text.HAL_TIM_IC_DeInit,"ax",%progbits + 2740 .align 1 + 2741 .global HAL_TIM_IC_DeInit + 2742 .syntax unified + 2743 .code 16 + 2744 .thumb_func + 2745 .fpu softvfp + 2747 HAL_TIM_IC_DeInit: + 2748 .LFB70: +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2749 .loc 1 1477 0 + 2750 .cfi_startproc + 2751 @ args = 0, pretend = 0, frame = 0 + 2752 @ frame_needed = 0, uses_anonymous_args = 0 + 2753 .LVL252: + 2754 0000 10B5 push {r4, lr} + 2755 .LCFI21: + 2756 .cfi_def_cfa_offset 8 + 2757 .cfi_offset 4, -8 + 2758 .cfi_offset 14, -4 + 2759 0002 0400 movs r4, r0 +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2760 .loc 1 1481 0 + 2761 0004 3523 movs r3, #53 + 2762 0006 0222 movs r2, #2 + 2763 0008 C254 strb r2, [r0, r3] +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2764 .loc 1 1484 0 + 2765 000a 0368 ldr r3, [r0] + 2766 000c 196A ldr r1, [r3, #32] + 2767 000e 084A ldr r2, .L192 + 2768 0010 1142 tst r1, r2 + 2769 0012 03D1 bne .L191 +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 144 + + + 2770 .loc 1 1484 0 is_stmt 0 discriminator 1 + 2771 0014 1A68 ldr r2, [r3] + 2772 0016 0121 movs r1, #1 + 2773 0018 8A43 bics r2, r1 + 2774 001a 1A60 str r2, [r3] + 2775 .L191: +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2776 .loc 1 1487 0 is_stmt 1 + 2777 001c 2000 movs r0, r4 + 2778 .LVL253: + 2779 001e FFF7FEFF bl HAL_TIM_IC_MspDeInit + 2780 .LVL254: +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2781 .loc 1 1490 0 + 2782 0022 0023 movs r3, #0 + 2783 0024 3522 movs r2, #53 + 2784 0026 A354 strb r3, [r4, r2] +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2785 .loc 1 1493 0 + 2786 0028 013A subs r2, r2, #1 + 2787 002a A354 strb r3, [r4, r2] +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2788 .loc 1 1496 0 + 2789 002c 0020 movs r0, #0 + 2790 @ sp needed + 2791 .LVL255: + 2792 002e 10BD pop {r4, pc} + 2793 .L193: + 2794 .align 2 + 2795 .L192: + 2796 0030 11110000 .word 4369 + 2797 .cfi_endproc + 2798 .LFE70: + 2800 .section .text.HAL_TIM_IC_Start,"ax",%progbits + 2801 .align 1 + 2802 .global HAL_TIM_IC_Start + 2803 .syntax unified + 2804 .code 16 + 2805 .thumb_func + 2806 .fpu softvfp + 2808 HAL_TIM_IC_Start: + 2809 .LFB73: +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2810 .loc 1 1539 0 + 2811 .cfi_startproc + 2812 @ args = 0, pretend = 0, frame = 0 + 2813 @ frame_needed = 0, uses_anonymous_args = 0 + 2814 .LVL256: + 2815 0000 10B5 push {r4, lr} + 2816 .LCFI22: + 2817 .cfi_def_cfa_offset 8 + 2818 .cfi_offset 4, -8 + 2819 .cfi_offset 14, -4 +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2820 .loc 1 1544 0 + 2821 0002 0368 ldr r3, [r0] + 2822 .LVL257: + ARM GAS /tmp/ccH6KUTS.s page 145 + + + 2823 .LBB192: + 2824 .LBB193: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2825 .loc 1 4947 0 + 2826 0004 0124 movs r4, #1 + 2827 0006 2200 movs r2, r4 + 2828 0008 8A40 lsls r2, r2, r1 + 2829 .LVL258: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2830 .loc 1 4950 0 + 2831 000a 196A ldr r1, [r3, #32] + 2832 .LVL259: + 2833 000c 9143 bics r1, r2 + 2834 000e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2835 .loc 1 4953 0 + 2836 0010 196A ldr r1, [r3, #32] + 2837 0012 0A43 orrs r2, r1 + 2838 .LVL260: + 2839 0014 1A62 str r2, [r3, #32] + 2840 .LVL261: + 2841 .LBE193: + 2842 .LBE192: +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2843 .loc 1 1547 0 + 2844 0016 0268 ldr r2, [r0] + 2845 0018 1368 ldr r3, [r2] + 2846 001a 2343 orrs r3, r4 + 2847 001c 1360 str r3, [r2] +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2848 .loc 1 1551 0 + 2849 001e 0020 movs r0, #0 + 2850 .LVL262: + 2851 @ sp needed + 2852 0020 10BD pop {r4, pc} + 2853 .cfi_endproc + 2854 .LFE73: + 2856 .section .text.HAL_TIM_IC_Stop,"ax",%progbits + 2857 .align 1 + 2858 .global HAL_TIM_IC_Stop + 2859 .syntax unified + 2860 .code 16 + 2861 .thumb_func + 2862 .fpu softvfp + 2864 HAL_TIM_IC_Stop: + 2865 .LFB74: +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2866 .loc 1 1565 0 + 2867 .cfi_startproc + 2868 @ args = 0, pretend = 0, frame = 0 + 2869 @ frame_needed = 0, uses_anonymous_args = 0 + 2870 @ link register save eliminated. + 2871 .LVL263: +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2872 .loc 1 1570 0 + 2873 0000 0368 ldr r3, [r0] + 2874 .LVL264: + ARM GAS /tmp/ccH6KUTS.s page 146 + + + 2875 .LBB194: + 2876 .LBB195: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2877 .loc 1 4947 0 + 2878 0002 0122 movs r2, #1 + 2879 0004 8A40 lsls r2, r2, r1 + 2880 0006 1100 movs r1, r2 + 2881 .LVL265: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2882 .loc 1 4950 0 + 2883 0008 1A6A ldr r2, [r3, #32] + 2884 000a 8A43 bics r2, r1 + 2885 000c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2886 .loc 1 4953 0 + 2887 000e 1A6A ldr r2, [r3, #32] + 2888 0010 1A62 str r2, [r3, #32] + 2889 .LVL266: + 2890 .LBE195: + 2891 .LBE194: +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2892 .loc 1 1573 0 + 2893 0012 0368 ldr r3, [r0] + 2894 0014 196A ldr r1, [r3, #32] + 2895 0016 044A ldr r2, .L197 + 2896 0018 1142 tst r1, r2 + 2897 001a 03D1 bne .L196 +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2898 .loc 1 1573 0 is_stmt 0 discriminator 1 + 2899 001c 1A68 ldr r2, [r3] + 2900 001e 0121 movs r1, #1 + 2901 0020 8A43 bics r2, r1 + 2902 0022 1A60 str r2, [r3] + 2903 .L196: +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2904 .loc 1 1577 0 is_stmt 1 + 2905 0024 0020 movs r0, #0 + 2906 .LVL267: + 2907 @ sp needed + 2908 0026 7047 bx lr + 2909 .L198: + 2910 .align 2 + 2911 .L197: + 2912 0028 11110000 .word 4369 + 2913 .cfi_endproc + 2914 .LFE74: + 2916 .section .text.HAL_TIM_IC_Start_IT,"ax",%progbits + 2917 .align 1 + 2918 .global HAL_TIM_IC_Start_IT + 2919 .syntax unified + 2920 .code 16 + 2921 .thumb_func + 2922 .fpu softvfp + 2924 HAL_TIM_IC_Start_IT: + 2925 .LFB75: +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 2926 .loc 1 1591 0 + ARM GAS /tmp/ccH6KUTS.s page 147 + + + 2927 .cfi_startproc + 2928 @ args = 0, pretend = 0, frame = 0 + 2929 @ frame_needed = 0, uses_anonymous_args = 0 + 2930 .LVL268: + 2931 0000 10B5 push {r4, lr} + 2932 .LCFI23: + 2933 .cfi_def_cfa_offset 8 + 2934 .cfi_offset 4, -8 + 2935 .cfi_offset 14, -4 +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2936 .loc 1 1595 0 + 2937 0002 0429 cmp r1, #4 + 2938 0004 21D0 beq .L201 + 2939 0006 09D9 bls .L206 + 2940 0008 0829 cmp r1, #8 + 2941 000a 24D0 beq .L204 + 2942 000c 0C29 cmp r1, #12 + 2943 000e 0CD1 bne .L200 +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2944 .loc 1 1621 0 + 2945 0010 0268 ldr r2, [r0] + 2946 0012 D368 ldr r3, [r2, #12] + 2947 0014 1024 movs r4, #16 + 2948 0016 2343 orrs r3, r4 + 2949 0018 D360 str r3, [r2, #12] +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2950 .loc 1 1623 0 + 2951 001a 06E0 b .L200 + 2952 .L206: +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 2953 .loc 1 1595 0 + 2954 001c 0029 cmp r1, #0 + 2955 001e 04D1 bne .L200 +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2956 .loc 1 1600 0 + 2957 0020 0268 ldr r2, [r0] + 2958 0022 D368 ldr r3, [r2, #12] + 2959 0024 0224 movs r4, #2 + 2960 0026 2343 orrs r3, r4 + 2961 0028 D360 str r3, [r2, #12] + 2962 .L200: +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2963 .loc 1 1629 0 + 2964 002a 0368 ldr r3, [r0] + 2965 .LVL269: + 2966 .LBB196: + 2967 .LBB197: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2968 .loc 1 4947 0 + 2969 002c 0124 movs r4, #1 + 2970 002e 2200 movs r2, r4 + 2971 0030 8A40 lsls r2, r2, r1 + 2972 .LVL270: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2973 .loc 1 4950 0 + 2974 0032 196A ldr r1, [r3, #32] + 2975 .LVL271: + ARM GAS /tmp/ccH6KUTS.s page 148 + + + 2976 0034 9143 bics r1, r2 + 2977 0036 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2978 .loc 1 4953 0 + 2979 0038 196A ldr r1, [r3, #32] + 2980 003a 0A43 orrs r2, r1 + 2981 .LVL272: + 2982 003c 1A62 str r2, [r3, #32] + 2983 .LVL273: + 2984 .LBE197: + 2985 .LBE196: +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2986 .loc 1 1632 0 + 2987 003e 0268 ldr r2, [r0] + 2988 0040 1368 ldr r3, [r2] + 2989 0042 2343 orrs r3, r4 + 2990 0044 1360 str r3, [r2] +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 2991 .loc 1 1636 0 + 2992 0046 0020 movs r0, #0 + 2993 .LVL274: + 2994 @ sp needed + 2995 0048 10BD pop {r4, pc} + 2996 .LVL275: + 2997 .L201: +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 2998 .loc 1 1607 0 + 2999 004a 0268 ldr r2, [r0] + 3000 004c D368 ldr r3, [r2, #12] + 3001 004e 0424 movs r4, #4 + 3002 0050 2343 orrs r3, r4 + 3003 0052 D360 str r3, [r2, #12] +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3004 .loc 1 1609 0 + 3005 0054 E9E7 b .L200 + 3006 .L204: +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3007 .loc 1 1614 0 + 3008 0056 0268 ldr r2, [r0] + 3009 0058 D368 ldr r3, [r2, #12] + 3010 005a 0824 movs r4, #8 + 3011 005c 2343 orrs r3, r4 + 3012 005e D360 str r3, [r2, #12] +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3013 .loc 1 1616 0 + 3014 0060 E3E7 b .L200 + 3015 .cfi_endproc + 3016 .LFE75: + 3018 .section .text.HAL_TIM_IC_Stop_IT,"ax",%progbits + 3019 .align 1 + 3020 .global HAL_TIM_IC_Stop_IT + 3021 .syntax unified + 3022 .code 16 + 3023 .thumb_func + 3024 .fpu softvfp + 3026 HAL_TIM_IC_Stop_IT: + 3027 .LFB76: + ARM GAS /tmp/ccH6KUTS.s page 149 + + +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 3028 .loc 1 1650 0 + 3029 .cfi_startproc + 3030 @ args = 0, pretend = 0, frame = 0 + 3031 @ frame_needed = 0, uses_anonymous_args = 0 + 3032 .LVL276: + 3033 0000 10B5 push {r4, lr} + 3034 .LCFI24: + 3035 .cfi_def_cfa_offset 8 + 3036 .cfi_offset 4, -8 + 3037 .cfi_offset 14, -4 +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3038 .loc 1 1654 0 + 3039 0002 0429 cmp r1, #4 + 3040 0004 25D0 beq .L209 + 3041 0006 09D9 bls .L215 + 3042 0008 0829 cmp r1, #8 + 3043 000a 28D0 beq .L212 + 3044 000c 0C29 cmp r1, #12 + 3045 000e 0CD1 bne .L208 +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3046 .loc 1 1680 0 + 3047 0010 0268 ldr r2, [r0] + 3048 0012 D368 ldr r3, [r2, #12] + 3049 0014 1024 movs r4, #16 + 3050 0016 A343 bics r3, r4 + 3051 0018 D360 str r3, [r2, #12] +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3052 .loc 1 1682 0 + 3053 001a 06E0 b .L208 + 3054 .L215: +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3055 .loc 1 1654 0 + 3056 001c 0029 cmp r1, #0 + 3057 001e 04D1 bne .L208 +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3058 .loc 1 1659 0 + 3059 0020 0268 ldr r2, [r0] + 3060 0022 D368 ldr r3, [r2, #12] + 3061 0024 0224 movs r4, #2 + 3062 0026 A343 bics r3, r4 + 3063 0028 D360 str r3, [r2, #12] + 3064 .L208: +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3065 .loc 1 1689 0 + 3066 002a 0368 ldr r3, [r0] + 3067 .LVL277: + 3068 .LBB198: + 3069 .LBB199: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3070 .loc 1 4947 0 + 3071 002c 0122 movs r2, #1 + 3072 002e 8A40 lsls r2, r2, r1 + 3073 0030 1100 movs r1, r2 + 3074 .LVL278: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3075 .loc 1 4950 0 + ARM GAS /tmp/ccH6KUTS.s page 150 + + + 3076 0032 1A6A ldr r2, [r3, #32] + 3077 0034 8A43 bics r2, r1 + 3078 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3079 .loc 1 4953 0 + 3080 0038 1A6A ldr r2, [r3, #32] + 3081 003a 1A62 str r2, [r3, #32] + 3082 .LVL279: + 3083 .LBE199: + 3084 .LBE198: +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3085 .loc 1 1692 0 + 3086 003c 0368 ldr r3, [r0] + 3087 003e 196A ldr r1, [r3, #32] + 3088 0040 0A4A ldr r2, .L216 + 3089 0042 1142 tst r1, r2 + 3090 0044 03D1 bne .L214 +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3091 .loc 1 1692 0 is_stmt 0 discriminator 1 + 3092 0046 1A68 ldr r2, [r3] + 3093 0048 0121 movs r1, #1 + 3094 004a 8A43 bics r2, r1 + 3095 004c 1A60 str r2, [r3] + 3096 .L214: +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3097 .loc 1 1696 0 is_stmt 1 + 3098 004e 0020 movs r0, #0 + 3099 .LVL280: + 3100 @ sp needed + 3101 0050 10BD pop {r4, pc} + 3102 .LVL281: + 3103 .L209: +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3104 .loc 1 1666 0 + 3105 0052 0268 ldr r2, [r0] + 3106 0054 D368 ldr r3, [r2, #12] + 3107 0056 0424 movs r4, #4 + 3108 0058 A343 bics r3, r4 + 3109 005a D360 str r3, [r2, #12] +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3110 .loc 1 1668 0 + 3111 005c E5E7 b .L208 + 3112 .L212: +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3113 .loc 1 1673 0 + 3114 005e 0268 ldr r2, [r0] + 3115 0060 D368 ldr r3, [r2, #12] + 3116 0062 0824 movs r4, #8 + 3117 0064 A343 bics r3, r4 + 3118 0066 D360 str r3, [r2, #12] +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3119 .loc 1 1675 0 + 3120 0068 DFE7 b .L208 + 3121 .L217: + 3122 006a C046 .align 2 + 3123 .L216: + 3124 006c 11110000 .word 4369 + ARM GAS /tmp/ccH6KUTS.s page 151 + + + 3125 .cfi_endproc + 3126 .LFE76: + 3128 .section .text.HAL_TIM_IC_Start_DMA,"ax",%progbits + 3129 .align 1 + 3130 .global HAL_TIM_IC_Start_DMA + 3131 .syntax unified + 3132 .code 16 + 3133 .thumb_func + 3134 .fpu softvfp + 3136 HAL_TIM_IC_Start_DMA: + 3137 .LFB77: +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 3138 .loc 1 1712 0 + 3139 .cfi_startproc + 3140 @ args = 0, pretend = 0, frame = 0 + 3141 @ frame_needed = 0, uses_anonymous_args = 0 + 3142 .LVL282: + 3143 0000 70B5 push {r4, r5, r6, lr} + 3144 .LCFI25: + 3145 .cfi_def_cfa_offset 16 + 3146 .cfi_offset 4, -16 + 3147 .cfi_offset 5, -12 + 3148 .cfi_offset 6, -8 + 3149 .cfi_offset 14, -4 + 3150 0002 0400 movs r4, r0 + 3151 0004 0D00 movs r5, r1 +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3152 .loc 1 1717 0 + 3153 0006 3521 movs r1, #53 + 3154 .LVL283: + 3155 0008 415C ldrb r1, [r0, r1] + 3156 000a 0229 cmp r1, #2 + 3157 000c 00D1 bne .LCB2948 + 3158 000e 6DE0 b .L228 @long jump + 3159 .LCB2948: +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3160 .loc 1 1721 0 + 3161 0010 3521 movs r1, #53 + 3162 0012 415C ldrb r1, [r0, r1] + 3163 0014 0129 cmp r1, #1 + 3164 0016 18D0 beq .L230 + 3165 .LVL284: + 3166 .L220: +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3167 .loc 1 1733 0 + 3168 0018 042D cmp r5, #4 + 3169 001a 43D0 beq .L223 + 3170 001c 1FD9 bls .L231 + 3171 001e 082D cmp r5, #8 + 3172 0020 52D0 beq .L226 + 3173 0022 0C2D cmp r5, #12 + 3174 0024 2ED1 bne .L222 +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3175 .loc 1 1786 0 + 3176 0026 A16A ldr r1, [r4, #40] + 3177 0028 3148 ldr r0, .L233 + 3178 002a C862 str r0, [r1, #44] + ARM GAS /tmp/ccH6KUTS.s page 152 + + +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3179 .loc 1 1789 0 + 3180 002c A16A ldr r1, [r4, #40] + 3181 002e 3148 ldr r0, .L233+4 + 3182 0030 4863 str r0, [r1, #52] +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3183 .loc 1 1792 0 + 3184 0032 2168 ldr r1, [r4] + 3185 0034 4031 adds r1, r1, #64 + 3186 0036 A06A ldr r0, [r4, #40] + 3187 0038 FFF7FEFF bl HAL_DMA_Start_IT + 3188 .LVL285: +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3189 .loc 1 1795 0 + 3190 003c 2268 ldr r2, [r4] + 3191 003e D168 ldr r1, [r2, #12] + 3192 0040 8023 movs r3, #128 + 3193 0042 5B01 lsls r3, r3, #5 + 3194 0044 0B43 orrs r3, r1 + 3195 0046 D360 str r3, [r2, #12] +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3196 .loc 1 1797 0 + 3197 0048 1CE0 b .L222 + 3198 .LVL286: + 3199 .L230: +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3200 .loc 1 1723 0 + 3201 004a 002A cmp r2, #0 + 3202 004c 03D0 beq .L232 + 3203 .L221: +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3204 .loc 1 1729 0 + 3205 004e 3521 movs r1, #53 + 3206 0050 0220 movs r0, #2 + 3207 .LVL287: + 3208 0052 6054 strb r0, [r4, r1] + 3209 0054 E0E7 b .L220 + 3210 .LVL288: + 3211 .L232: +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3212 .loc 1 1723 0 discriminator 1 + 3213 0056 002B cmp r3, #0 + 3214 0058 F9D0 beq .L221 +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3215 .loc 1 1725 0 + 3216 005a 0120 movs r0, #1 + 3217 .LVL289: + 3218 005c 21E0 b .L219 + 3219 .L231: +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3220 .loc 1 1733 0 + 3221 005e 002D cmp r5, #0 + 3222 0060 10D1 bne .L222 +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3223 .loc 1 1738 0 + 3224 0062 E169 ldr r1, [r4, #28] + 3225 0064 2248 ldr r0, .L233 + ARM GAS /tmp/ccH6KUTS.s page 153 + + + 3226 0066 C862 str r0, [r1, #44] +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3227 .loc 1 1741 0 + 3228 0068 E169 ldr r1, [r4, #28] + 3229 006a 2248 ldr r0, .L233+4 + 3230 006c 4863 str r0, [r1, #52] +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3231 .loc 1 1744 0 + 3232 006e 2168 ldr r1, [r4] + 3233 0070 3431 adds r1, r1, #52 + 3234 0072 E069 ldr r0, [r4, #28] + 3235 0074 FFF7FEFF bl HAL_DMA_Start_IT + 3236 .LVL290: +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3237 .loc 1 1747 0 + 3238 0078 2268 ldr r2, [r4] + 3239 007a D168 ldr r1, [r2, #12] + 3240 007c 8023 movs r3, #128 + 3241 007e 9B00 lsls r3, r3, #2 + 3242 0080 0B43 orrs r3, r1 + 3243 0082 D360 str r3, [r2, #12] + 3244 .L222: +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3245 .loc 1 1804 0 + 3246 0084 2368 ldr r3, [r4] + 3247 .LVL291: + 3248 .LBB200: + 3249 .LBB201: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3250 .loc 1 4947 0 + 3251 0086 0120 movs r0, #1 + 3252 0088 0200 movs r2, r0 + 3253 008a AA40 lsls r2, r2, r5 + 3254 .LVL292: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3255 .loc 1 4950 0 + 3256 008c 196A ldr r1, [r3, #32] + 3257 008e 9143 bics r1, r2 + 3258 0090 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3259 .loc 1 4953 0 + 3260 0092 196A ldr r1, [r3, #32] + 3261 0094 0A43 orrs r2, r1 + 3262 .LVL293: + 3263 0096 1A62 str r2, [r3, #32] + 3264 .LVL294: + 3265 .LBE201: + 3266 .LBE200: +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3267 .loc 1 1807 0 + 3268 0098 2268 ldr r2, [r4] + 3269 009a 1368 ldr r3, [r2] + 3270 009c 0343 orrs r3, r0 + 3271 009e 1360 str r3, [r2] +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3272 .loc 1 1810 0 + 3273 00a0 0020 movs r0, #0 + ARM GAS /tmp/ccH6KUTS.s page 154 + + + 3274 .L219: +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3275 .loc 1 1811 0 + 3276 @ sp needed + 3277 .LVL295: + 3278 .LVL296: + 3279 00a2 70BD pop {r4, r5, r6, pc} + 3280 .LVL297: + 3281 .L223: +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3282 .loc 1 1754 0 + 3283 00a4 216A ldr r1, [r4, #32] + 3284 00a6 1248 ldr r0, .L233 + 3285 00a8 C862 str r0, [r1, #44] +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3286 .loc 1 1757 0 + 3287 00aa 216A ldr r1, [r4, #32] + 3288 00ac 1148 ldr r0, .L233+4 + 3289 00ae 4863 str r0, [r1, #52] +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3290 .loc 1 1760 0 + 3291 00b0 2168 ldr r1, [r4] + 3292 00b2 3831 adds r1, r1, #56 + 3293 00b4 206A ldr r0, [r4, #32] + 3294 00b6 FFF7FEFF bl HAL_DMA_Start_IT + 3295 .LVL298: +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3296 .loc 1 1763 0 + 3297 00ba 2268 ldr r2, [r4] + 3298 00bc D168 ldr r1, [r2, #12] + 3299 00be 8023 movs r3, #128 + 3300 00c0 DB00 lsls r3, r3, #3 + 3301 00c2 0B43 orrs r3, r1 + 3302 00c4 D360 str r3, [r2, #12] +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3303 .loc 1 1765 0 + 3304 00c6 DDE7 b .L222 + 3305 .LVL299: + 3306 .L226: +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3307 .loc 1 1770 0 + 3308 00c8 616A ldr r1, [r4, #36] + 3309 00ca 0948 ldr r0, .L233 + 3310 00cc C862 str r0, [r1, #44] +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3311 .loc 1 1773 0 + 3312 00ce 616A ldr r1, [r4, #36] + 3313 00d0 0848 ldr r0, .L233+4 + 3314 00d2 4863 str r0, [r1, #52] +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3315 .loc 1 1776 0 + 3316 00d4 2168 ldr r1, [r4] + 3317 00d6 3C31 adds r1, r1, #60 + 3318 00d8 606A ldr r0, [r4, #36] + 3319 00da FFF7FEFF bl HAL_DMA_Start_IT + 3320 .LVL300: +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 155 + + + 3321 .loc 1 1779 0 + 3322 00de 2268 ldr r2, [r4] + 3323 00e0 D168 ldr r1, [r2, #12] + 3324 00e2 8023 movs r3, #128 + 3325 00e4 1B01 lsls r3, r3, #4 + 3326 00e6 0B43 orrs r3, r1 + 3327 00e8 D360 str r3, [r2, #12] +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3328 .loc 1 1781 0 + 3329 00ea CBE7 b .L222 + 3330 .LVL301: + 3331 .L228: +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3332 .loc 1 1719 0 + 3333 00ec 0220 movs r0, #2 + 3334 .LVL302: + 3335 00ee D8E7 b .L219 + 3336 .L234: + 3337 .align 2 + 3338 .L233: + 3339 00f0 00000000 .word TIM_DMACaptureCplt + 3340 00f4 00000000 .word TIM_DMAError + 3341 .cfi_endproc + 3342 .LFE77: + 3344 .section .text.HAL_TIM_IC_Stop_DMA,"ax",%progbits + 3345 .align 1 + 3346 .global HAL_TIM_IC_Stop_DMA + 3347 .syntax unified + 3348 .code 16 + 3349 .thumb_func + 3350 .fpu softvfp + 3352 HAL_TIM_IC_Stop_DMA: + 3353 .LFB78: +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 3354 .loc 1 1825 0 + 3355 .cfi_startproc + 3356 @ args = 0, pretend = 0, frame = 0 + 3357 @ frame_needed = 0, uses_anonymous_args = 0 + 3358 .LVL303: + 3359 0000 10B5 push {r4, lr} + 3360 .LCFI26: + 3361 .cfi_def_cfa_offset 8 + 3362 .cfi_offset 4, -8 + 3363 .cfi_offset 14, -4 +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3364 .loc 1 1830 0 + 3365 0002 0429 cmp r1, #4 + 3366 0004 28D0 beq .L237 + 3367 0006 09D9 bls .L243 + 3368 0008 0829 cmp r1, #8 + 3369 000a 2BD0 beq .L240 + 3370 000c 0C29 cmp r1, #12 + 3371 000e 0CD1 bne .L236 +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3372 .loc 1 1856 0 + 3373 0010 0268 ldr r2, [r0] + 3374 0012 D368 ldr r3, [r2, #12] + ARM GAS /tmp/ccH6KUTS.s page 156 + + + 3375 0014 164C ldr r4, .L244 + 3376 0016 2340 ands r3, r4 + 3377 0018 D360 str r3, [r2, #12] +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3378 .loc 1 1858 0 + 3379 001a 06E0 b .L236 + 3380 .L243: +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3381 .loc 1 1830 0 + 3382 001c 0029 cmp r1, #0 + 3383 001e 04D1 bne .L236 +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3384 .loc 1 1835 0 + 3385 0020 0268 ldr r2, [r0] + 3386 0022 D368 ldr r3, [r2, #12] + 3387 0024 134C ldr r4, .L244+4 + 3388 0026 2340 ands r3, r4 + 3389 0028 D360 str r3, [r2, #12] + 3390 .L236: +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3391 .loc 1 1865 0 + 3392 002a 0368 ldr r3, [r0] + 3393 .LVL304: + 3394 .LBB202: + 3395 .LBB203: +4947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3396 .loc 1 4947 0 + 3397 002c 0122 movs r2, #1 + 3398 002e 8A40 lsls r2, r2, r1 + 3399 0030 1100 movs r1, r2 + 3400 .LVL305: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3401 .loc 1 4950 0 + 3402 0032 1A6A ldr r2, [r3, #32] + 3403 0034 8A43 bics r2, r1 + 3404 0036 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3405 .loc 1 4953 0 + 3406 0038 1A6A ldr r2, [r3, #32] + 3407 003a 1A62 str r2, [r3, #32] + 3408 .LVL306: + 3409 .LBE203: + 3410 .LBE202: +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3411 .loc 1 1868 0 + 3412 003c 0368 ldr r3, [r0] + 3413 003e 196A ldr r1, [r3, #32] + 3414 0040 0D4A ldr r2, .L244+8 + 3415 0042 1142 tst r1, r2 + 3416 0044 03D1 bne .L242 +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3417 .loc 1 1868 0 is_stmt 0 discriminator 1 + 3418 0046 1A68 ldr r2, [r3] + 3419 0048 0121 movs r1, #1 + 3420 004a 8A43 bics r2, r1 + 3421 004c 1A60 str r2, [r3] + 3422 .L242: + ARM GAS /tmp/ccH6KUTS.s page 157 + + +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3423 .loc 1 1871 0 is_stmt 1 + 3424 004e 3523 movs r3, #53 + 3425 0050 0122 movs r2, #1 + 3426 0052 C254 strb r2, [r0, r3] +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3427 .loc 1 1875 0 + 3428 0054 0020 movs r0, #0 + 3429 .LVL307: + 3430 @ sp needed + 3431 0056 10BD pop {r4, pc} + 3432 .LVL308: + 3433 .L237: +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3434 .loc 1 1842 0 + 3435 0058 0268 ldr r2, [r0] + 3436 005a D368 ldr r3, [r2, #12] + 3437 005c 074C ldr r4, .L244+12 + 3438 005e 2340 ands r3, r4 + 3439 0060 D360 str r3, [r2, #12] +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3440 .loc 1 1844 0 + 3441 0062 E2E7 b .L236 + 3442 .L240: +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3443 .loc 1 1849 0 + 3444 0064 0268 ldr r2, [r0] + 3445 0066 D368 ldr r3, [r2, #12] + 3446 0068 054C ldr r4, .L244+16 + 3447 006a 2340 ands r3, r4 + 3448 006c D360 str r3, [r2, #12] +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3449 .loc 1 1851 0 + 3450 006e DCE7 b .L236 + 3451 .L245: + 3452 .align 2 + 3453 .L244: + 3454 0070 FFEFFFFF .word -4097 + 3455 0074 FFFDFFFF .word -513 + 3456 0078 11110000 .word 4369 + 3457 007c FFFBFFFF .word -1025 + 3458 0080 FFF7FFFF .word -2049 + 3459 .cfi_endproc + 3460 .LFE78: + 3462 .section .text.HAL_TIM_OnePulse_MspInit,"ax",%progbits + 3463 .align 1 + 3464 .weak HAL_TIM_OnePulse_MspInit + 3465 .syntax unified + 3466 .code 16 + 3467 .thumb_func + 3468 .fpu softvfp + 3470 HAL_TIM_OnePulse_MspInit: + 3471 .LFB81: +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 3472 .loc 1 1988 0 + 3473 .cfi_startproc + 3474 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccH6KUTS.s page 158 + + + 3475 @ frame_needed = 0, uses_anonymous_args = 0 + 3476 @ link register save eliminated. + 3477 .LVL309: +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3478 .loc 1 1995 0 + 3479 @ sp needed + 3480 0000 7047 bx lr + 3481 .cfi_endproc + 3482 .LFE81: + 3484 .section .text.HAL_TIM_OnePulse_Init,"ax",%progbits + 3485 .align 1 + 3486 .global HAL_TIM_OnePulse_Init + 3487 .syntax unified + 3488 .code 16 + 3489 .thumb_func + 3490 .fpu softvfp + 3492 HAL_TIM_OnePulse_Init: + 3493 .LFB79: +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the TIM handle allocation */ + 3494 .loc 1 1913 0 + 3495 .cfi_startproc + 3496 @ args = 0, pretend = 0, frame = 0 + 3497 @ frame_needed = 0, uses_anonymous_args = 0 + 3498 .LVL310: + 3499 0000 70B5 push {r4, r5, r6, lr} + 3500 .LCFI27: + 3501 .cfi_def_cfa_offset 16 + 3502 .cfi_offset 4, -16 + 3503 .cfi_offset 5, -12 + 3504 .cfi_offset 6, -8 + 3505 .cfi_offset 14, -4 + 3506 0002 0400 movs r4, r0 + 3507 0004 0D00 movs r5, r1 +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3508 .loc 1 1915 0 + 3509 0006 0028 cmp r0, #0 + 3510 0008 1DD0 beq .L250 +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 3511 .loc 1 1928 0 + 3512 000a 3523 movs r3, #53 + 3513 000c C35C ldrb r3, [r0, r3] + 3514 000e 002B cmp r3, #0 + 3515 0010 13D0 beq .L251 + 3516 .LVL311: + 3517 .L249: +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3518 .loc 1 1938 0 + 3519 0012 3526 movs r6, #53 + 3520 0014 0223 movs r3, #2 + 3521 0016 A355 strb r3, [r4, r6] +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3522 .loc 1 1941 0 + 3523 0018 211D adds r1, r4, #4 + 3524 001a 2068 ldr r0, [r4] + 3525 001c FFF7FEFF bl TIM_Base_SetConfig + 3526 .LVL312: +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 159 + + + 3527 .loc 1 1944 0 + 3528 0020 2268 ldr r2, [r4] + 3529 0022 1368 ldr r3, [r2] + 3530 0024 0821 movs r1, #8 + 3531 0026 8B43 bics r3, r1 + 3532 0028 1360 str r3, [r2] +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3533 .loc 1 1947 0 + 3534 002a 2368 ldr r3, [r4] + 3535 002c 1968 ldr r1, [r3] + 3536 002e 2943 orrs r1, r5 + 3537 0030 1960 str r1, [r3] +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3538 .loc 1 1950 0 + 3539 0032 0123 movs r3, #1 + 3540 0034 A355 strb r3, [r4, r6] +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3541 .loc 1 1952 0 + 3542 0036 0020 movs r0, #0 + 3543 .L248: +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3544 .loc 1 1953 0 + 3545 @ sp needed + 3546 .LVL313: + 3547 .LVL314: + 3548 0038 70BD pop {r4, r5, r6, pc} + 3549 .LVL315: + 3550 .L251: +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3551 .loc 1 1931 0 + 3552 003a 3433 adds r3, r3, #52 + 3553 003c 0022 movs r2, #0 + 3554 003e C254 strb r2, [r0, r3] +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3555 .loc 1 1934 0 + 3556 0040 FFF7FEFF bl HAL_TIM_OnePulse_MspInit + 3557 .LVL316: + 3558 0044 E5E7 b .L249 + 3559 .LVL317: + 3560 .L250: +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3561 .loc 1 1917 0 + 3562 0046 0120 movs r0, #1 + 3563 .LVL318: + 3564 0048 F6E7 b .L248 + 3565 .cfi_endproc + 3566 .LFE79: + 3568 .section .text.HAL_TIM_OnePulse_MspDeInit,"ax",%progbits + 3569 .align 1 + 3570 .weak HAL_TIM_OnePulse_MspDeInit + 3571 .syntax unified + 3572 .code 16 + 3573 .thumb_func + 3574 .fpu softvfp + 3576 HAL_TIM_OnePulse_MspDeInit: + 3577 .LFB82: +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccH6KUTS.s page 160 + + + 3578 .loc 1 2003 0 + 3579 .cfi_startproc + 3580 @ args = 0, pretend = 0, frame = 0 + 3581 @ frame_needed = 0, uses_anonymous_args = 0 + 3582 @ link register save eliminated. + 3583 .LVL319: +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3584 .loc 1 2010 0 + 3585 @ sp needed + 3586 0000 7047 bx lr + 3587 .cfi_endproc + 3588 .LFE82: + 3590 .section .text.HAL_TIM_OnePulse_DeInit,"ax",%progbits + 3591 .align 1 + 3592 .global HAL_TIM_OnePulse_DeInit + 3593 .syntax unified + 3594 .code 16 + 3595 .thumb_func + 3596 .fpu softvfp + 3598 HAL_TIM_OnePulse_DeInit: + 3599 .LFB80: +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 3600 .loc 1 1961 0 + 3601 .cfi_startproc + 3602 @ args = 0, pretend = 0, frame = 0 + 3603 @ frame_needed = 0, uses_anonymous_args = 0 + 3604 .LVL320: + 3605 0000 10B5 push {r4, lr} + 3606 .LCFI28: + 3607 .cfi_def_cfa_offset 8 + 3608 .cfi_offset 4, -8 + 3609 .cfi_offset 14, -4 + 3610 0002 0400 movs r4, r0 +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3611 .loc 1 1965 0 + 3612 0004 3523 movs r3, #53 + 3613 0006 0222 movs r2, #2 + 3614 0008 C254 strb r2, [r0, r3] +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3615 .loc 1 1968 0 + 3616 000a 0368 ldr r3, [r0] + 3617 000c 196A ldr r1, [r3, #32] + 3618 000e 084A ldr r2, .L255 + 3619 0010 1142 tst r1, r2 + 3620 0012 03D1 bne .L254 +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3621 .loc 1 1968 0 is_stmt 0 discriminator 1 + 3622 0014 1A68 ldr r2, [r3] + 3623 0016 0121 movs r1, #1 + 3624 0018 8A43 bics r2, r1 + 3625 001a 1A60 str r2, [r3] + 3626 .L254: +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3627 .loc 1 1971 0 is_stmt 1 + 3628 001c 2000 movs r0, r4 + 3629 .LVL321: + 3630 001e FFF7FEFF bl HAL_TIM_OnePulse_MspDeInit + ARM GAS /tmp/ccH6KUTS.s page 161 + + + 3631 .LVL322: +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3632 .loc 1 1974 0 + 3633 0022 0023 movs r3, #0 + 3634 0024 3522 movs r2, #53 + 3635 0026 A354 strb r3, [r4, r2] +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3636 .loc 1 1977 0 + 3637 0028 013A subs r2, r2, #1 + 3638 002a A354 strb r3, [r4, r2] +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3639 .loc 1 1980 0 + 3640 002c 0020 movs r0, #0 + 3641 @ sp needed + 3642 .LVL323: + 3643 002e 10BD pop {r4, pc} + 3644 .L256: + 3645 .align 2 + 3646 .L255: + 3647 0030 11110000 .word 4369 + 3648 .cfi_endproc + 3649 .LFE80: + 3651 .section .text.HAL_TIM_OnePulse_Start,"ax",%progbits + 3652 .align 1 + 3653 .global HAL_TIM_OnePulse_Start + 3654 .syntax unified + 3655 .code 16 + 3656 .thumb_func + 3657 .fpu softvfp + 3659 HAL_TIM_OnePulse_Start: + 3660 .LFB83: +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels + 3661 .loc 1 2021 0 + 3662 .cfi_startproc + 3663 @ args = 0, pretend = 0, frame = 0 + 3664 @ frame_needed = 0, uses_anonymous_args = 0 + 3665 .LVL324: + 3666 0000 10B5 push {r4, lr} + 3667 .LCFI29: + 3668 .cfi_def_cfa_offset 8 + 3669 .cfi_offset 4, -8 + 3670 .cfi_offset 14, -4 +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 3671 .loc 1 2031 0 + 3672 0002 0368 ldr r3, [r0] + 3673 .LVL325: + 3674 .LBB204: + 3675 .LBB205: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3676 .loc 1 4950 0 + 3677 0004 196A ldr r1, [r3, #32] + 3678 .LVL326: + 3679 0006 0124 movs r4, #1 + 3680 0008 A143 bics r1, r4 + 3681 000a 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3682 .loc 1 4953 0 + ARM GAS /tmp/ccH6KUTS.s page 162 + + + 3683 000c 1A6A ldr r2, [r3, #32] + 3684 000e 2243 orrs r2, r4 + 3685 0010 1A62 str r2, [r3, #32] + 3686 .LVL327: + 3687 .LBE205: + 3688 .LBE204: +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3689 .loc 1 2032 0 + 3690 0012 0368 ldr r3, [r0] + 3691 .LVL328: + 3692 .LBB206: + 3693 .LBB207: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3694 .loc 1 4950 0 + 3695 0014 196A ldr r1, [r3, #32] + 3696 0016 1020 movs r0, #16 + 3697 .LVL329: + 3698 0018 8143 bics r1, r0 + 3699 001a 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3700 .loc 1 4953 0 + 3701 001c 1A6A ldr r2, [r3, #32] + 3702 001e 0243 orrs r2, r0 + 3703 0020 1A62 str r2, [r3, #32] + 3704 .LVL330: + 3705 .LBE207: + 3706 .LBE206: +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3707 .loc 1 2036 0 + 3708 0022 0020 movs r0, #0 + 3709 @ sp needed + 3710 0024 10BD pop {r4, pc} + 3711 .cfi_endproc + 3712 .LFE83: + 3714 .section .text.HAL_TIM_OnePulse_Stop,"ax",%progbits + 3715 .align 1 + 3716 .global HAL_TIM_OnePulse_Stop + 3717 .syntax unified + 3718 .code 16 + 3719 .thumb_func + 3720 .fpu softvfp + 3722 HAL_TIM_OnePulse_Stop: + 3723 .LFB84: +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels + 3724 .loc 1 2048 0 + 3725 .cfi_startproc + 3726 @ args = 0, pretend = 0, frame = 0 + 3727 @ frame_needed = 0, uses_anonymous_args = 0 + 3728 @ link register save eliminated. + 3729 .LVL331: +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 3730 .loc 1 2055 0 + 3731 0000 0368 ldr r3, [r0] + 3732 .LVL332: + 3733 .LBB208: + 3734 .LBB209: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 163 + + + 3735 .loc 1 4950 0 + 3736 0002 1A6A ldr r2, [r3, #32] + 3737 0004 0121 movs r1, #1 + 3738 .LVL333: + 3739 0006 8A43 bics r2, r1 + 3740 0008 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3741 .loc 1 4953 0 + 3742 000a 1A6A ldr r2, [r3, #32] + 3743 000c 1A62 str r2, [r3, #32] + 3744 .LVL334: + 3745 .LBE209: + 3746 .LBE208: +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3747 .loc 1 2056 0 + 3748 000e 0368 ldr r3, [r0] + 3749 .LVL335: + 3750 .LBB210: + 3751 .LBB211: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3752 .loc 1 4950 0 + 3753 0010 1A6A ldr r2, [r3, #32] + 3754 0012 0F31 adds r1, r1, #15 + 3755 0014 8A43 bics r2, r1 + 3756 0016 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3757 .loc 1 4953 0 + 3758 0018 1A6A ldr r2, [r3, #32] + 3759 001a 1A62 str r2, [r3, #32] + 3760 .LVL336: + 3761 .LBE211: + 3762 .LBE210: +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3763 .loc 1 2059 0 + 3764 001c 0368 ldr r3, [r0] + 3765 001e 196A ldr r1, [r3, #32] + 3766 0020 044A ldr r2, .L260 + 3767 0022 1142 tst r1, r2 + 3768 0024 03D1 bne .L259 +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3769 .loc 1 2059 0 is_stmt 0 discriminator 1 + 3770 0026 1A68 ldr r2, [r3] + 3771 0028 0121 movs r1, #1 + 3772 002a 8A43 bics r2, r1 + 3773 002c 1A60 str r2, [r3] + 3774 .L259: +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3775 .loc 1 2063 0 is_stmt 1 + 3776 002e 0020 movs r0, #0 + 3777 .LVL337: + 3778 @ sp needed + 3779 0030 7047 bx lr + 3780 .L261: + 3781 0032 C046 .align 2 + 3782 .L260: + 3783 0034 11110000 .word 4369 + 3784 .cfi_endproc + ARM GAS /tmp/ccH6KUTS.s page 164 + + + 3785 .LFE84: + 3787 .section .text.HAL_TIM_OnePulse_Start_IT,"ax",%progbits + 3788 .align 1 + 3789 .global HAL_TIM_OnePulse_Start_IT + 3790 .syntax unified + 3791 .code 16 + 3792 .thumb_func + 3793 .fpu softvfp + 3795 HAL_TIM_OnePulse_Start_IT: + 3796 .LFB85: +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels + 3797 .loc 1 2075 0 + 3798 .cfi_startproc + 3799 @ args = 0, pretend = 0, frame = 0 + 3800 @ frame_needed = 0, uses_anonymous_args = 0 + 3801 .LVL338: + 3802 0000 10B5 push {r4, lr} + 3803 .LCFI30: + 3804 .cfi_def_cfa_offset 8 + 3805 .cfi_offset 4, -8 + 3806 .cfi_offset 14, -4 +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3807 .loc 1 2086 0 + 3808 0002 0268 ldr r2, [r0] + 3809 0004 D368 ldr r3, [r2, #12] + 3810 0006 0221 movs r1, #2 + 3811 .LVL339: + 3812 0008 0B43 orrs r3, r1 + 3813 000a D360 str r3, [r2, #12] +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3814 .loc 1 2089 0 + 3815 000c 0268 ldr r2, [r0] + 3816 000e D368 ldr r3, [r2, #12] + 3817 0010 0231 adds r1, r1, #2 + 3818 0012 0B43 orrs r3, r1 + 3819 0014 D360 str r3, [r2, #12] +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 3820 .loc 1 2091 0 + 3821 0016 0368 ldr r3, [r0] + 3822 .LVL340: + 3823 .LBB212: + 3824 .LBB213: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3825 .loc 1 4950 0 + 3826 0018 196A ldr r1, [r3, #32] + 3827 001a 0124 movs r4, #1 + 3828 001c A143 bics r1, r4 + 3829 001e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3830 .loc 1 4953 0 + 3831 0020 1A6A ldr r2, [r3, #32] + 3832 0022 2243 orrs r2, r4 + 3833 0024 1A62 str r2, [r3, #32] + 3834 .LVL341: + 3835 .LBE213: + 3836 .LBE212: +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 165 + + + 3837 .loc 1 2092 0 + 3838 0026 0368 ldr r3, [r0] + 3839 .LVL342: + 3840 .LBB214: + 3841 .LBB215: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3842 .loc 1 4950 0 + 3843 0028 196A ldr r1, [r3, #32] + 3844 002a 1020 movs r0, #16 + 3845 .LVL343: + 3846 002c 8143 bics r1, r0 + 3847 002e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3848 .loc 1 4953 0 + 3849 0030 1A6A ldr r2, [r3, #32] + 3850 0032 0243 orrs r2, r0 + 3851 0034 1A62 str r2, [r3, #32] + 3852 .LVL344: + 3853 .LBE215: + 3854 .LBE214: +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3855 .loc 1 2096 0 + 3856 0036 0020 movs r0, #0 + 3857 @ sp needed + 3858 0038 10BD pop {r4, pc} + 3859 .cfi_endproc + 3860 .LFE85: + 3862 .section .text.HAL_TIM_OnePulse_Stop_IT,"ax",%progbits + 3863 .align 1 + 3864 .global HAL_TIM_OnePulse_Stop_IT + 3865 .syntax unified + 3866 .code 16 + 3867 .thumb_func + 3868 .fpu softvfp + 3870 HAL_TIM_OnePulse_Stop_IT: + 3871 .LFB86: +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ + 3872 .loc 1 2108 0 + 3873 .cfi_startproc + 3874 @ args = 0, pretend = 0, frame = 0 + 3875 @ frame_needed = 0, uses_anonymous_args = 0 + 3876 @ link register save eliminated. + 3877 .LVL345: +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3878 .loc 1 2110 0 + 3879 0000 0268 ldr r2, [r0] + 3880 0002 D368 ldr r3, [r2, #12] + 3881 0004 0221 movs r1, #2 + 3882 .LVL346: + 3883 0006 8B43 bics r3, r1 + 3884 0008 D360 str r3, [r2, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3885 .loc 1 2113 0 + 3886 000a 0268 ldr r2, [r0] + 3887 000c D368 ldr r3, [r2, #12] + 3888 000e 0231 adds r1, r1, #2 + 3889 0010 8B43 bics r3, r1 + ARM GAS /tmp/ccH6KUTS.s page 166 + + + 3890 0012 D360 str r3, [r2, #12] +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 3891 .loc 1 2120 0 + 3892 0014 0368 ldr r3, [r0] + 3893 .LVL347: + 3894 .LBB216: + 3895 .LBB217: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3896 .loc 1 4950 0 + 3897 0016 1A6A ldr r2, [r3, #32] + 3898 0018 0339 subs r1, r1, #3 + 3899 001a 8A43 bics r2, r1 + 3900 001c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3901 .loc 1 4953 0 + 3902 001e 1A6A ldr r2, [r3, #32] + 3903 0020 1A62 str r2, [r3, #32] + 3904 .LVL348: + 3905 .LBE217: + 3906 .LBE216: +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3907 .loc 1 2121 0 + 3908 0022 0368 ldr r3, [r0] + 3909 .LVL349: + 3910 .LBB218: + 3911 .LBB219: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3912 .loc 1 4950 0 + 3913 0024 1A6A ldr r2, [r3, #32] + 3914 0026 0F31 adds r1, r1, #15 + 3915 0028 8A43 bics r2, r1 + 3916 002a 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 3917 .loc 1 4953 0 + 3918 002c 1A6A ldr r2, [r3, #32] + 3919 002e 1A62 str r2, [r3, #32] + 3920 .LVL350: + 3921 .LBE219: + 3922 .LBE218: +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3923 .loc 1 2124 0 + 3924 0030 0368 ldr r3, [r0] + 3925 0032 196A ldr r1, [r3, #32] + 3926 0034 044A ldr r2, .L265 + 3927 0036 1142 tst r1, r2 + 3928 0038 03D1 bne .L264 +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3929 .loc 1 2124 0 is_stmt 0 discriminator 1 + 3930 003a 1A68 ldr r2, [r3] + 3931 003c 0121 movs r1, #1 + 3932 003e 8A43 bics r2, r1 + 3933 0040 1A60 str r2, [r3] + 3934 .L264: +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3935 .loc 1 2128 0 is_stmt 1 + 3936 0042 0020 movs r0, #0 + 3937 .LVL351: + ARM GAS /tmp/ccH6KUTS.s page 167 + + + 3938 @ sp needed + 3939 0044 7047 bx lr + 3940 .L266: + 3941 0046 C046 .align 2 + 3942 .L265: + 3943 0048 11110000 .word 4369 + 3944 .cfi_endproc + 3945 .LFE86: + 3947 .section .text.HAL_TIM_Encoder_MspInit,"ax",%progbits + 3948 .align 1 + 3949 .weak HAL_TIM_Encoder_MspInit + 3950 .syntax unified + 3951 .code 16 + 3952 .thumb_func + 3953 .fpu softvfp + 3955 HAL_TIM_Encoder_MspInit: + 3956 .LFB89: +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 3957 .loc 1 2281 0 + 3958 .cfi_startproc + 3959 @ args = 0, pretend = 0, frame = 0 + 3960 @ frame_needed = 0, uses_anonymous_args = 0 + 3961 @ link register save eliminated. + 3962 .LVL352: +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 3963 .loc 1 2288 0 + 3964 @ sp needed + 3965 0000 7047 bx lr + 3966 .cfi_endproc + 3967 .LFE89: + 3969 .section .text.HAL_TIM_Encoder_Init,"ax",%progbits + 3970 .align 1 + 3971 .global HAL_TIM_Encoder_Init + 3972 .syntax unified + 3973 .code 16 + 3974 .thumb_func + 3975 .fpu softvfp + 3977 HAL_TIM_Encoder_Init: + 3978 .LFB87: +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; + 3979 .loc 1 2162 0 + 3980 .cfi_startproc + 3981 @ args = 0, pretend = 0, frame = 0 + 3982 @ frame_needed = 0, uses_anonymous_args = 0 + 3983 .LVL353: + 3984 0000 F0B5 push {r4, r5, r6, r7, lr} + 3985 .LCFI31: + 3986 .cfi_def_cfa_offset 20 + 3987 .cfi_offset 4, -20 + 3988 .cfi_offset 5, -16 + 3989 .cfi_offset 6, -12 + 3990 .cfi_offset 7, -8 + 3991 .cfi_offset 14, -4 + 3992 0002 C646 mov lr, r8 + 3993 0004 00B5 push {lr} + 3994 .LCFI32: + 3995 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccH6KUTS.s page 168 + + + 3996 .cfi_offset 8, -24 + 3997 0006 0400 movs r4, r0 + 3998 0008 0D00 movs r5, r1 + 3999 .LVL354: +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4000 .loc 1 2168 0 + 4001 000a 0028 cmp r0, #0 + 4002 000c 43D0 beq .L271 +2187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4003 .loc 1 2187 0 + 4004 000e 3523 movs r3, #53 + 4005 0010 C35C ldrb r3, [r0, r3] + 4006 0012 002B cmp r3, #0 + 4007 0014 39D0 beq .L272 + 4008 .LVL355: + 4009 .L270: +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4010 .loc 1 2197 0 + 4011 0016 3526 movs r6, #53 + 4012 0018 0223 movs r3, #2 + 4013 001a A355 strb r3, [r4, r6] +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4014 .loc 1 2200 0 + 4015 001c 2100 movs r1, r4 + 4016 001e 04C9 ldmia r1!, {r2} + 4017 0020 9368 ldr r3, [r2, #8] + 4018 0022 0720 movs r0, #7 + 4019 0024 8343 bics r3, r0 + 4020 0026 9360 str r3, [r2, #8] +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4021 .loc 1 2203 0 + 4022 0028 2068 ldr r0, [r4] + 4023 002a FFF7FEFF bl TIM_Base_SetConfig + 4024 .LVL356: +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4025 .loc 1 2206 0 + 4026 002e 2168 ldr r1, [r4] + 4027 0030 8868 ldr r0, [r1, #8] + 4028 .LVL357: +2209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4029 .loc 1 2209 0 + 4030 0032 8A69 ldr r2, [r1, #24] + 4031 .LVL358: +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4032 .loc 1 2212 0 + 4033 0034 0F6A ldr r7, [r1, #32] + 4034 .LVL359: +2215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4035 .loc 1 2215 0 + 4036 0036 2B68 ldr r3, [r5] + 4037 0038 1843 orrs r0, r3 + 4038 .LVL360: + 4039 003a 8046 mov r8, r0 + 4040 .LVL361: +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 4041 .loc 1 2218 0 + 4042 003c 174B ldr r3, .L273 + ARM GAS /tmp/ccH6KUTS.s page 169 + + + 4043 003e 1340 ands r3, r2 + 4044 .LVL362: +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4045 .loc 1 2219 0 + 4046 0040 AA69 ldr r2, [r5, #24] + 4047 0042 1202 lsls r2, r2, #8 + 4048 0044 A868 ldr r0, [r5, #8] + 4049 .LVL363: + 4050 0046 0243 orrs r2, r0 + 4051 0048 1A43 orrs r2, r3 + 4052 .LVL364: +2223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 4053 .loc 1 2223 0 + 4054 004a 154B ldr r3, .L273+4 + 4055 004c 1A40 ands r2, r3 + 4056 .LVL365: +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 4057 .loc 1 2224 0 + 4058 004e EB69 ldr r3, [r5, #28] + 4059 0050 1B02 lsls r3, r3, #8 + 4060 0052 E868 ldr r0, [r5, #12] + 4061 0054 0343 orrs r3, r0 + 4062 0056 1A43 orrs r2, r3 + 4063 .LVL366: +2225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4064 .loc 1 2225 0 + 4065 0058 2B69 ldr r3, [r5, #16] + 4066 005a 1B01 lsls r3, r3, #4 + 4067 005c 286A ldr r0, [r5, #32] + 4068 005e 0003 lsls r0, r0, #12 + 4069 0060 0343 orrs r3, r0 + 4070 0062 1343 orrs r3, r2 + 4071 .LVL367: +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 4072 .loc 1 2229 0 + 4073 0064 AA22 movs r2, #170 + 4074 0066 9743 bics r7, r2 + 4075 .LVL368: +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4076 .loc 1 2230 0 + 4077 0068 6A68 ldr r2, [r5, #4] + 4078 006a 6D69 ldr r5, [r5, #20] + 4079 .LVL369: + 4080 006c 2D01 lsls r5, r5, #4 + 4081 006e 2A43 orrs r2, r5 + 4082 0070 3A43 orrs r2, r7 + 4083 .LVL370: +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4084 .loc 1 2233 0 + 4085 0072 4046 mov r0, r8 + 4086 0074 8860 str r0, [r1, #8] +2236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4087 .loc 1 2236 0 + 4088 0076 2168 ldr r1, [r4] + 4089 0078 8B61 str r3, [r1, #24] +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4090 .loc 1 2239 0 + ARM GAS /tmp/ccH6KUTS.s page 170 + + + 4091 007a 2368 ldr r3, [r4] + 4092 .LVL371: + 4093 007c 1A62 str r2, [r3, #32] + 4094 .LVL372: +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4095 .loc 1 2242 0 + 4096 007e 0123 movs r3, #1 + 4097 0080 A355 strb r3, [r4, r6] +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4098 .loc 1 2244 0 + 4099 0082 0020 movs r0, #0 + 4100 .LVL373: + 4101 .L269: +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4102 .loc 1 2245 0 + 4103 @ sp needed + 4104 .LVL374: + 4105 0084 04BC pop {r2} + 4106 0086 9046 mov r8, r2 + 4107 0088 F0BD pop {r4, r5, r6, r7, pc} + 4108 .LVL375: + 4109 .L272: +2190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4110 .loc 1 2190 0 + 4111 008a 3433 adds r3, r3, #52 + 4112 008c 0022 movs r2, #0 + 4113 008e C254 strb r2, [r0, r3] +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4114 .loc 1 2193 0 + 4115 0090 FFF7FEFF bl HAL_TIM_Encoder_MspInit + 4116 .LVL376: + 4117 0094 BFE7 b .L270 + 4118 .LVL377: + 4119 .L271: +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4120 .loc 1 2170 0 + 4121 0096 0120 movs r0, #1 + 4122 .LVL378: + 4123 0098 F4E7 b .L269 + 4124 .L274: + 4125 009a C046 .align 2 + 4126 .L273: + 4127 009c FCFCFFFF .word -772 + 4128 00a0 0303FFFF .word -64765 + 4129 .cfi_endproc + 4130 .LFE87: + 4132 .section .text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits + 4133 .align 1 + 4134 .weak HAL_TIM_Encoder_MspDeInit + 4135 .syntax unified + 4136 .code 16 + 4137 .thumb_func + 4138 .fpu softvfp + 4140 HAL_TIM_Encoder_MspDeInit: + 4141 .LFB90: +2297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4142 .loc 1 2297 0 + ARM GAS /tmp/ccH6KUTS.s page 171 + + + 4143 .cfi_startproc + 4144 @ args = 0, pretend = 0, frame = 0 + 4145 @ frame_needed = 0, uses_anonymous_args = 0 + 4146 @ link register save eliminated. + 4147 .LVL379: +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4148 .loc 1 2304 0 + 4149 @ sp needed + 4150 0000 7047 bx lr + 4151 .cfi_endproc + 4152 .LFE90: + 4154 .section .text.HAL_TIM_Encoder_DeInit,"ax",%progbits + 4155 .align 1 + 4156 .global HAL_TIM_Encoder_DeInit + 4157 .syntax unified + 4158 .code 16 + 4159 .thumb_func + 4160 .fpu softvfp + 4162 HAL_TIM_Encoder_DeInit: + 4163 .LFB88: +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 4164 .loc 1 2253 0 + 4165 .cfi_startproc + 4166 @ args = 0, pretend = 0, frame = 0 + 4167 @ frame_needed = 0, uses_anonymous_args = 0 + 4168 .LVL380: + 4169 0000 10B5 push {r4, lr} + 4170 .LCFI33: + 4171 .cfi_def_cfa_offset 8 + 4172 .cfi_offset 4, -8 + 4173 .cfi_offset 14, -4 + 4174 0002 0400 movs r4, r0 +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4175 .loc 1 2257 0 + 4176 0004 3523 movs r3, #53 + 4177 0006 0222 movs r2, #2 + 4178 0008 C254 strb r2, [r0, r3] +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4179 .loc 1 2260 0 + 4180 000a 0368 ldr r3, [r0] + 4181 000c 196A ldr r1, [r3, #32] + 4182 000e 084A ldr r2, .L278 + 4183 0010 1142 tst r1, r2 + 4184 0012 03D1 bne .L277 +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4185 .loc 1 2260 0 is_stmt 0 discriminator 1 + 4186 0014 1A68 ldr r2, [r3] + 4187 0016 0121 movs r1, #1 + 4188 0018 8A43 bics r2, r1 + 4189 001a 1A60 str r2, [r3] + 4190 .L277: +2263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4191 .loc 1 2263 0 is_stmt 1 + 4192 001c 2000 movs r0, r4 + 4193 .LVL381: + 4194 001e FFF7FEFF bl HAL_TIM_Encoder_MspDeInit + 4195 .LVL382: + ARM GAS /tmp/ccH6KUTS.s page 172 + + +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4196 .loc 1 2266 0 + 4197 0022 0023 movs r3, #0 + 4198 0024 3522 movs r2, #53 + 4199 0026 A354 strb r3, [r4, r2] +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4200 .loc 1 2269 0 + 4201 0028 013A subs r2, r2, #1 + 4202 002a A354 strb r3, [r4, r2] +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4203 .loc 1 2272 0 + 4204 002c 0020 movs r0, #0 + 4205 @ sp needed + 4206 .LVL383: + 4207 002e 10BD pop {r4, pc} + 4208 .L279: + 4209 .align 2 + 4210 .L278: + 4211 0030 11110000 .word 4369 + 4212 .cfi_endproc + 4213 .LFE88: + 4215 .section .text.HAL_TIM_Encoder_Start,"ax",%progbits + 4216 .align 1 + 4217 .global HAL_TIM_Encoder_Start + 4218 .syntax unified + 4219 .code 16 + 4220 .thumb_func + 4221 .fpu softvfp + 4223 HAL_TIM_Encoder_Start: + 4224 .LFB91: +2317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 4225 .loc 1 2317 0 + 4226 .cfi_startproc + 4227 @ args = 0, pretend = 0, frame = 0 + 4228 @ frame_needed = 0, uses_anonymous_args = 0 + 4229 .LVL384: + 4230 0000 10B5 push {r4, lr} + 4231 .LCFI34: + 4232 .cfi_def_cfa_offset 8 + 4233 .cfi_offset 4, -8 + 4234 .cfi_offset 14, -4 +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4235 .loc 1 2322 0 + 4236 0002 0029 cmp r1, #0 + 4237 0004 12D0 beq .L282 + 4238 0006 0429 cmp r1, #4 + 4239 0008 1FD0 beq .L283 +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 4240 .loc 1 2336 0 + 4241 000a 0368 ldr r3, [r0] + 4242 .LVL385: + 4243 .LBB220: + 4244 .LBB221: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4245 .loc 1 4950 0 + 4246 000c 196A ldr r1, [r3, #32] + 4247 .LVL386: + ARM GAS /tmp/ccH6KUTS.s page 173 + + + 4248 000e 0124 movs r4, #1 + 4249 0010 A143 bics r1, r4 + 4250 0012 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4251 .loc 1 4953 0 + 4252 0014 1A6A ldr r2, [r3, #32] + 4253 0016 2243 orrs r2, r4 + 4254 0018 1A62 str r2, [r3, #32] + 4255 .LVL387: + 4256 .LBE221: + 4257 .LBE220: +2337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4258 .loc 1 2337 0 + 4259 001a 0368 ldr r3, [r0] + 4260 .LVL388: + 4261 .LBB222: + 4262 .LBB223: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4263 .loc 1 4950 0 + 4264 001c 196A ldr r1, [r3, #32] + 4265 001e 0F34 adds r4, r4, #15 + 4266 0020 A143 bics r1, r4 + 4267 0022 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4268 .loc 1 4953 0 + 4269 0024 1A6A ldr r2, [r3, #32] + 4270 0026 2243 orrs r2, r4 + 4271 0028 1A62 str r2, [r3, #32] + 4272 002a 07E0 b .L284 + 4273 .LVL389: + 4274 .L282: + 4275 .LBE223: + 4276 .LBE222: +2326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4277 .loc 1 2326 0 + 4278 002c 0368 ldr r3, [r0] + 4279 .LVL390: + 4280 .LBB224: + 4281 .LBB225: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4282 .loc 1 4950 0 + 4283 002e 196A ldr r1, [r3, #32] + 4284 .LVL391: + 4285 0030 0124 movs r4, #1 + 4286 0032 A143 bics r1, r4 + 4287 0034 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4288 .loc 1 4953 0 + 4289 0036 1A6A ldr r2, [r3, #32] + 4290 0038 2243 orrs r2, r4 + 4291 003a 1A62 str r2, [r3, #32] + 4292 .LVL392: + 4293 .L284: + 4294 .LBE225: + 4295 .LBE224: +2342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4296 .loc 1 2342 0 + ARM GAS /tmp/ccH6KUTS.s page 174 + + + 4297 003c 0268 ldr r2, [r0] + 4298 003e 1368 ldr r3, [r2] + 4299 0040 0121 movs r1, #1 + 4300 0042 0B43 orrs r3, r1 + 4301 0044 1360 str r3, [r2] +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4302 .loc 1 2346 0 + 4303 0046 0020 movs r0, #0 + 4304 .LVL393: + 4305 @ sp needed + 4306 0048 10BD pop {r4, pc} + 4307 .LVL394: + 4308 .L283: +2331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4309 .loc 1 2331 0 + 4310 004a 0368 ldr r3, [r0] + 4311 .LVL395: + 4312 .LBB226: + 4313 .LBB227: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4314 .loc 1 4950 0 + 4315 004c 196A ldr r1, [r3, #32] + 4316 .LVL396: + 4317 004e 1024 movs r4, #16 + 4318 0050 A143 bics r1, r4 + 4319 0052 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4320 .loc 1 4953 0 + 4321 0054 1A6A ldr r2, [r3, #32] + 4322 0056 2243 orrs r2, r4 + 4323 0058 1A62 str r2, [r3, #32] + 4324 005a EFE7 b .L284 + 4325 .LBE227: + 4326 .LBE226: + 4327 .cfi_endproc + 4328 .LFE91: + 4330 .section .text.HAL_TIM_Encoder_Stop,"ax",%progbits + 4331 .align 1 + 4332 .global HAL_TIM_Encoder_Stop + 4333 .syntax unified + 4334 .code 16 + 4335 .thumb_func + 4336 .fpu softvfp + 4338 HAL_TIM_Encoder_Stop: + 4339 .LFB92: +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 4340 .loc 1 2359 0 + 4341 .cfi_startproc + 4342 @ args = 0, pretend = 0, frame = 0 + 4343 @ frame_needed = 0, uses_anonymous_args = 0 + 4344 @ link register save eliminated. + 4345 .LVL397: +2365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4346 .loc 1 2365 0 + 4347 0000 0029 cmp r1, #0 + 4348 0002 10D0 beq .L288 + 4349 0004 0429 cmp r1, #4 + ARM GAS /tmp/ccH6KUTS.s page 175 + + + 4350 0006 20D0 beq .L289 +2379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 4351 .loc 1 2379 0 + 4352 0008 0368 ldr r3, [r0] + 4353 .LVL398: + 4354 .LBB228: + 4355 .LBB229: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4356 .loc 1 4950 0 + 4357 000a 1A6A ldr r2, [r3, #32] + 4358 000c 0121 movs r1, #1 + 4359 .LVL399: + 4360 000e 8A43 bics r2, r1 + 4361 0010 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4362 .loc 1 4953 0 + 4363 0012 1A6A ldr r2, [r3, #32] + 4364 0014 1A62 str r2, [r3, #32] + 4365 .LVL400: + 4366 .LBE229: + 4367 .LBE228: +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4368 .loc 1 2380 0 + 4369 0016 0368 ldr r3, [r0] + 4370 .LVL401: + 4371 .LBB230: + 4372 .LBB231: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4373 .loc 1 4950 0 + 4374 0018 1A6A ldr r2, [r3, #32] + 4375 001a 0F31 adds r1, r1, #15 + 4376 001c 8A43 bics r2, r1 + 4377 001e 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4378 .loc 1 4953 0 + 4379 0020 1A6A ldr r2, [r3, #32] + 4380 0022 1A62 str r2, [r3, #32] + 4381 0024 06E0 b .L290 + 4382 .LVL402: + 4383 .L288: + 4384 .LBE231: + 4385 .LBE230: +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4386 .loc 1 2369 0 + 4387 0026 0368 ldr r3, [r0] + 4388 .LVL403: + 4389 .LBB232: + 4390 .LBB233: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4391 .loc 1 4950 0 + 4392 0028 1A6A ldr r2, [r3, #32] + 4393 002a 0121 movs r1, #1 + 4394 .LVL404: + 4395 002c 8A43 bics r2, r1 + 4396 002e 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4397 .loc 1 4953 0 + ARM GAS /tmp/ccH6KUTS.s page 176 + + + 4398 0030 1A6A ldr r2, [r3, #32] + 4399 0032 1A62 str r2, [r3, #32] + 4400 .LVL405: + 4401 .L290: + 4402 .LBE233: + 4403 .LBE232: +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4404 .loc 1 2385 0 + 4405 0034 0368 ldr r3, [r0] + 4406 0036 196A ldr r1, [r3, #32] + 4407 0038 084A ldr r2, .L293 + 4408 003a 1142 tst r1, r2 + 4409 003c 03D1 bne .L291 +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4410 .loc 1 2385 0 is_stmt 0 discriminator 1 + 4411 003e 1A68 ldr r2, [r3] + 4412 0040 0121 movs r1, #1 + 4413 0042 8A43 bics r2, r1 + 4414 0044 1A60 str r2, [r3] + 4415 .L291: +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4416 .loc 1 2389 0 is_stmt 1 + 4417 0046 0020 movs r0, #0 + 4418 .LVL406: + 4419 @ sp needed + 4420 0048 7047 bx lr + 4421 .LVL407: + 4422 .L289: +2374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4423 .loc 1 2374 0 + 4424 004a 0368 ldr r3, [r0] + 4425 .LVL408: + 4426 .LBB234: + 4427 .LBB235: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4428 .loc 1 4950 0 + 4429 004c 1A6A ldr r2, [r3, #32] + 4430 004e 1021 movs r1, #16 + 4431 .LVL409: + 4432 0050 8A43 bics r2, r1 + 4433 0052 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4434 .loc 1 4953 0 + 4435 0054 1A6A ldr r2, [r3, #32] + 4436 0056 1A62 str r2, [r3, #32] + 4437 0058 ECE7 b .L290 + 4438 .L294: + 4439 005a C046 .align 2 + 4440 .L293: + 4441 005c 11110000 .word 4369 + 4442 .LBE235: + 4443 .LBE234: + 4444 .cfi_endproc + 4445 .LFE92: + 4447 .section .text.HAL_TIM_Encoder_Start_IT,"ax",%progbits + 4448 .align 1 + 4449 .global HAL_TIM_Encoder_Start_IT + ARM GAS /tmp/ccH6KUTS.s page 177 + + + 4450 .syntax unified + 4451 .code 16 + 4452 .thumb_func + 4453 .fpu softvfp + 4455 HAL_TIM_Encoder_Start_IT: + 4456 .LFB93: +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 4457 .loc 1 2402 0 + 4458 .cfi_startproc + 4459 @ args = 0, pretend = 0, frame = 0 + 4460 @ frame_needed = 0, uses_anonymous_args = 0 + 4461 .LVL410: + 4462 0000 10B5 push {r4, lr} + 4463 .LCFI35: + 4464 .cfi_def_cfa_offset 8 + 4465 .cfi_offset 4, -8 + 4466 .cfi_offset 14, -4 +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4467 .loc 1 2408 0 + 4468 0002 0029 cmp r1, #0 + 4469 0004 1CD0 beq .L297 + 4470 0006 0429 cmp r1, #4 + 4471 0008 2ED0 beq .L298 +2424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 4472 .loc 1 2424 0 + 4473 000a 0368 ldr r3, [r0] + 4474 .LVL411: + 4475 .LBB236: + 4476 .LBB237: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4477 .loc 1 4950 0 + 4478 000c 196A ldr r1, [r3, #32] + 4479 .LVL412: + 4480 000e 0124 movs r4, #1 + 4481 0010 A143 bics r1, r4 + 4482 0012 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4483 .loc 1 4953 0 + 4484 0014 1A6A ldr r2, [r3, #32] + 4485 0016 2243 orrs r2, r4 + 4486 0018 1A62 str r2, [r3, #32] + 4487 .LVL413: + 4488 .LBE237: + 4489 .LBE236: +2425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 4490 .loc 1 2425 0 + 4491 001a 0368 ldr r3, [r0] + 4492 .LVL414: + 4493 .LBB238: + 4494 .LBB239: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4495 .loc 1 4950 0 + 4496 001c 196A ldr r1, [r3, #32] + 4497 001e 0F34 adds r4, r4, #15 + 4498 0020 A143 bics r1, r4 + 4499 0022 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 178 + + + 4500 .loc 1 4953 0 + 4501 0024 1A6A ldr r2, [r3, #32] + 4502 0026 2243 orrs r2, r4 + 4503 0028 1A62 str r2, [r3, #32] + 4504 .LVL415: + 4505 .LBE239: + 4506 .LBE238: +2426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 4507 .loc 1 2426 0 + 4508 002a 0268 ldr r2, [r0] + 4509 002c D368 ldr r3, [r2, #12] + 4510 002e 0221 movs r1, #2 + 4511 0030 0B43 orrs r3, r1 + 4512 0032 D360 str r3, [r2, #12] +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4513 .loc 1 2427 0 + 4514 0034 0268 ldr r2, [r0] + 4515 0036 D368 ldr r3, [r2, #12] + 4516 0038 0231 adds r1, r1, #2 + 4517 003a 0B43 orrs r3, r1 + 4518 003c D360 str r3, [r2, #12] +2428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4519 .loc 1 2428 0 + 4520 003e 0CE0 b .L299 + 4521 .LVL416: + 4522 .L297: +2412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 4523 .loc 1 2412 0 + 4524 0040 0368 ldr r3, [r0] + 4525 .LVL417: + 4526 .LBB240: + 4527 .LBB241: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4528 .loc 1 4950 0 + 4529 0042 196A ldr r1, [r3, #32] + 4530 .LVL418: + 4531 0044 0124 movs r4, #1 + 4532 0046 A143 bics r1, r4 + 4533 0048 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4534 .loc 1 4953 0 + 4535 004a 1A6A ldr r2, [r3, #32] + 4536 004c 2243 orrs r2, r4 + 4537 004e 1A62 str r2, [r3, #32] + 4538 .LVL419: + 4539 .LBE241: + 4540 .LBE240: +2413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4541 .loc 1 2413 0 + 4542 0050 0268 ldr r2, [r0] + 4543 0052 D368 ldr r3, [r2, #12] + 4544 0054 0221 movs r1, #2 + 4545 0056 0B43 orrs r3, r1 + 4546 0058 D360 str r3, [r2, #12] + 4547 .L299: +2433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4548 .loc 1 2433 0 + ARM GAS /tmp/ccH6KUTS.s page 179 + + + 4549 005a 0268 ldr r2, [r0] + 4550 005c 1368 ldr r3, [r2] + 4551 005e 0121 movs r1, #1 + 4552 0060 0B43 orrs r3, r1 + 4553 0062 1360 str r3, [r2] +2437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4554 .loc 1 2437 0 + 4555 0064 0020 movs r0, #0 + 4556 .LVL420: + 4557 @ sp needed + 4558 0066 10BD pop {r4, pc} + 4559 .LVL421: + 4560 .L298: +2418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 4561 .loc 1 2418 0 + 4562 0068 0368 ldr r3, [r0] + 4563 .LVL422: + 4564 .LBB242: + 4565 .LBB243: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4566 .loc 1 4950 0 + 4567 006a 196A ldr r1, [r3, #32] + 4568 .LVL423: + 4569 006c 1024 movs r4, #16 + 4570 006e A143 bics r1, r4 + 4571 0070 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4572 .loc 1 4953 0 + 4573 0072 1A6A ldr r2, [r3, #32] + 4574 0074 2243 orrs r2, r4 + 4575 0076 1A62 str r2, [r3, #32] + 4576 .LVL424: + 4577 .LBE243: + 4578 .LBE242: +2419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** break; + 4579 .loc 1 2419 0 + 4580 0078 0268 ldr r2, [r0] + 4581 007a D368 ldr r3, [r2, #12] + 4582 007c 0421 movs r1, #4 + 4583 007e 0B43 orrs r3, r1 + 4584 0080 D360 str r3, [r2, #12] +2420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4585 .loc 1 2420 0 + 4586 0082 EAE7 b .L299 + 4587 .cfi_endproc + 4588 .LFE93: + 4590 .section .text.HAL_TIM_Encoder_Stop_IT,"ax",%progbits + 4591 .align 1 + 4592 .global HAL_TIM_Encoder_Stop_IT + 4593 .syntax unified + 4594 .code 16 + 4595 .thumb_func + 4596 .fpu softvfp + 4598 HAL_TIM_Encoder_Stop_IT: + 4599 .LFB94: +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 4600 .loc 1 2450 0 + ARM GAS /tmp/ccH6KUTS.s page 180 + + + 4601 .cfi_startproc + 4602 @ args = 0, pretend = 0, frame = 0 + 4603 @ frame_needed = 0, uses_anonymous_args = 0 + 4604 @ link register save eliminated. + 4605 .LVL425: +2456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4606 .loc 1 2456 0 + 4607 0000 0029 cmp r1, #0 + 4608 0002 19D1 bne .L302 +2458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4609 .loc 1 2458 0 + 4610 0004 0368 ldr r3, [r0] + 4611 .LVL426: + 4612 .LBB244: + 4613 .LBB245: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4614 .loc 1 4950 0 + 4615 0006 1A6A ldr r2, [r3, #32] + 4616 0008 0131 adds r1, r1, #1 + 4617 .LVL427: + 4618 000a 8A43 bics r2, r1 + 4619 000c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4620 .loc 1 4953 0 + 4621 000e 1A6A ldr r2, [r3, #32] + 4622 0010 1A62 str r2, [r3, #32] + 4623 .LVL428: + 4624 .LBE245: + 4625 .LBE244: +2461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4626 .loc 1 2461 0 + 4627 0012 0268 ldr r2, [r0] + 4628 0014 D368 ldr r3, [r2, #12] + 4629 0016 0131 adds r1, r1, #1 + 4630 .LVL429: + 4631 0018 8B43 bics r3, r1 + 4632 001a D360 str r3, [r2, #12] + 4633 .LVL430: + 4634 .L303: +2481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4635 .loc 1 2481 0 + 4636 001c 0368 ldr r3, [r0] + 4637 001e 196A ldr r1, [r3, #32] + 4638 0020 194A ldr r2, .L307 + 4639 0022 1142 tst r1, r2 + 4640 0024 03D1 bne .L305 +2481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4641 .loc 1 2481 0 is_stmt 0 discriminator 1 + 4642 0026 1A68 ldr r2, [r3] + 4643 0028 0121 movs r1, #1 + 4644 002a 8A43 bics r2, r1 + 4645 002c 1A60 str r2, [r3] + 4646 .L305: +2484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4647 .loc 1 2484 0 is_stmt 1 + 4648 002e 3523 movs r3, #53 + 4649 0030 0122 movs r2, #1 + ARM GAS /tmp/ccH6KUTS.s page 181 + + + 4650 0032 C254 strb r2, [r0, r3] +2488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4651 .loc 1 2488 0 + 4652 0034 0020 movs r0, #0 + 4653 .LVL431: + 4654 @ sp needed + 4655 0036 7047 bx lr + 4656 .LVL432: + 4657 .L302: +2463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4658 .loc 1 2463 0 + 4659 0038 0429 cmp r1, #4 + 4660 003a 18D0 beq .L306 +2472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 4661 .loc 1 2472 0 + 4662 003c 0368 ldr r3, [r0] + 4663 .LVL433: + 4664 .LBB246: + 4665 .LBB247: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4666 .loc 1 4950 0 + 4667 003e 1A6A ldr r2, [r3, #32] + 4668 0040 0121 movs r1, #1 + 4669 .LVL434: + 4670 0042 8A43 bics r2, r1 + 4671 0044 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4672 .loc 1 4953 0 + 4673 0046 1A6A ldr r2, [r3, #32] + 4674 0048 1A62 str r2, [r3, #32] + 4675 .LVL435: + 4676 .LBE247: + 4677 .LBE246: +2473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4678 .loc 1 2473 0 + 4679 004a 0368 ldr r3, [r0] + 4680 .LVL436: + 4681 .LBB248: + 4682 .LBB249: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4683 .loc 1 4950 0 + 4684 004c 1A6A ldr r2, [r3, #32] + 4685 004e 0F31 adds r1, r1, #15 + 4686 0050 8A43 bics r2, r1 + 4687 0052 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4688 .loc 1 4953 0 + 4689 0054 1A6A ldr r2, [r3, #32] + 4690 0056 1A62 str r2, [r3, #32] + 4691 .LVL437: + 4692 .LBE249: + 4693 .LBE248: +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 4694 .loc 1 2476 0 + 4695 0058 0268 ldr r2, [r0] + 4696 005a D368 ldr r3, [r2, #12] + 4697 005c 0E39 subs r1, r1, #14 + ARM GAS /tmp/ccH6KUTS.s page 182 + + + 4698 005e 8B43 bics r3, r1 + 4699 0060 D360 str r3, [r2, #12] +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4700 .loc 1 2477 0 + 4701 0062 0268 ldr r2, [r0] + 4702 0064 D368 ldr r3, [r2, #12] + 4703 0066 0231 adds r1, r1, #2 + 4704 0068 8B43 bics r3, r1 + 4705 006a D360 str r3, [r2, #12] + 4706 006c D6E7 b .L303 + 4707 .LVL438: + 4708 .L306: +2465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4709 .loc 1 2465 0 + 4710 006e 0368 ldr r3, [r0] + 4711 .LVL439: + 4712 .LBB250: + 4713 .LBB251: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4714 .loc 1 4950 0 + 4715 0070 1A6A ldr r2, [r3, #32] + 4716 0072 0C31 adds r1, r1, #12 + 4717 .LVL440: + 4718 0074 8A43 bics r2, r1 + 4719 0076 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4720 .loc 1 4953 0 + 4721 0078 1A6A ldr r2, [r3, #32] + 4722 007a 1A62 str r2, [r3, #32] + 4723 .LVL441: + 4724 .LBE251: + 4725 .LBE250: +2468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4726 .loc 1 2468 0 + 4727 007c 0268 ldr r2, [r0] + 4728 007e D368 ldr r3, [r2, #12] + 4729 0080 0C39 subs r1, r1, #12 + 4730 .LVL442: + 4731 0082 8B43 bics r3, r1 + 4732 0084 D360 str r3, [r2, #12] + 4733 0086 C9E7 b .L303 + 4734 .L308: + 4735 .align 2 + 4736 .L307: + 4737 0088 11110000 .word 4369 + 4738 .cfi_endproc + 4739 .LFE94: + 4741 .section .text.HAL_TIM_Encoder_Start_DMA,"ax",%progbits + 4742 .align 1 + 4743 .global HAL_TIM_Encoder_Start_DMA + 4744 .syntax unified + 4745 .code 16 + 4746 .thumb_func + 4747 .fpu softvfp + 4749 HAL_TIM_Encoder_Start_DMA: + 4750 .LFB95: +2504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccH6KUTS.s page 183 + + + 4751 .loc 1 2504 0 + 4752 .cfi_startproc + 4753 @ args = 4, pretend = 0, frame = 0 + 4754 @ frame_needed = 0, uses_anonymous_args = 0 + 4755 .LVL443: + 4756 0000 F0B5 push {r4, r5, r6, r7, lr} + 4757 .LCFI36: + 4758 .cfi_def_cfa_offset 20 + 4759 .cfi_offset 4, -20 + 4760 .cfi_offset 5, -16 + 4761 .cfi_offset 6, -12 + 4762 .cfi_offset 7, -8 + 4763 .cfi_offset 14, -4 + 4764 0002 C646 mov lr, r8 + 4765 0004 00B5 push {lr} + 4766 .LCFI37: + 4767 .cfi_def_cfa_offset 24 + 4768 .cfi_offset 8, -24 + 4769 0006 0400 movs r4, r0 + 4770 0008 1D00 movs r5, r3 + 4771 000a 06AB add r3, sp, #24 + 4772 .LVL444: + 4773 000c 1E88 ldrh r6, [r3] +2508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4774 .loc 1 2508 0 + 4775 000e 3523 movs r3, #53 + 4776 .LVL445: + 4777 0010 C35C ldrb r3, [r0, r3] + 4778 0012 022B cmp r3, #2 + 4779 0014 00D1 bne .LCB4542 + 4780 0016 94E0 b .L317 @long jump + 4781 .LCB4542: +2512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4782 .loc 1 2512 0 + 4783 0018 3523 movs r3, #53 + 4784 001a C35C ldrb r3, [r0, r3] + 4785 001c 012B cmp r3, #1 + 4786 001e 07D0 beq .L321 + 4787 .LVL446: + 4788 .L311: +2524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4789 .loc 1 2524 0 + 4790 0020 0429 cmp r1, #4 + 4791 0022 31D0 beq .L314 + 4792 0024 1829 cmp r1, #24 + 4793 0026 51D0 beq .L315 + 4794 0028 0029 cmp r1, #0 + 4795 002a 0DD0 beq .L322 +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4796 .loc 1 2607 0 + 4797 002c 0020 movs r0, #0 + 4798 002e 89E0 b .L310 + 4799 .LVL447: + 4800 .L321: +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4801 .loc 1 2514 0 + 4802 0030 002A cmp r2, #0 + ARM GAS /tmp/ccH6KUTS.s page 184 + + + 4803 0032 05D0 beq .L312 +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4804 .loc 1 2514 0 is_stmt 0 discriminator 2 + 4805 0034 002D cmp r5, #0 + 4806 0036 03D0 beq .L312 + 4807 .L313: +2520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4808 .loc 1 2520 0 is_stmt 1 + 4809 0038 3523 movs r3, #53 + 4810 003a 0220 movs r0, #2 + 4811 .LVL448: + 4812 003c E054 strb r0, [r4, r3] + 4813 003e EFE7 b .L311 + 4814 .LVL449: + 4815 .L312: +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 4816 .loc 1 2514 0 discriminator 3 + 4817 0040 002E cmp r6, #0 + 4818 0042 F9D0 beq .L313 +2516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4819 .loc 1 2516 0 + 4820 0044 0120 movs r0, #1 + 4821 .LVL450: + 4822 0046 7DE0 b .L310 + 4823 .L322: +2529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4824 .loc 1 2529 0 + 4825 0048 E369 ldr r3, [r4, #28] + 4826 004a 4049 ldr r1, .L323 + 4827 .LVL451: + 4828 004c D962 str r1, [r3, #44] +2532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4829 .loc 1 2532 0 + 4830 004e E369 ldr r3, [r4, #28] + 4831 0050 3F49 ldr r1, .L323+4 + 4832 0052 5963 str r1, [r3, #52] +2535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4833 .loc 1 2535 0 + 4834 0054 2168 ldr r1, [r4] + 4835 0056 3431 adds r1, r1, #52 + 4836 0058 3300 movs r3, r6 + 4837 005a E069 ldr r0, [r4, #28] + 4838 005c FFF7FEFF bl HAL_DMA_Start_IT + 4839 .LVL452: +2538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4840 .loc 1 2538 0 + 4841 0060 2268 ldr r2, [r4] + 4842 0062 D168 ldr r1, [r2, #12] + 4843 0064 8023 movs r3, #128 + 4844 0066 9B00 lsls r3, r3, #2 + 4845 0068 0B43 orrs r3, r1 + 4846 006a D360 str r3, [r2, #12] +2541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4847 .loc 1 2541 0 + 4848 006c 2268 ldr r2, [r4] + 4849 006e 1368 ldr r3, [r2] + 4850 0070 0121 movs r1, #1 + ARM GAS /tmp/ccH6KUTS.s page 185 + + + 4851 0072 0B43 orrs r3, r1 + 4852 0074 1360 str r3, [r2] +2544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4853 .loc 1 2544 0 + 4854 0076 2368 ldr r3, [r4] + 4855 .LVL453: + 4856 .LBB252: + 4857 .LBB253: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4858 .loc 1 4950 0 + 4859 0078 1A6A ldr r2, [r3, #32] + 4860 007a 8A43 bics r2, r1 + 4861 007c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4862 .loc 1 4953 0 + 4863 007e 1A6A ldr r2, [r3, #32] + 4864 0080 0A43 orrs r2, r1 + 4865 0082 1A62 str r2, [r3, #32] + 4866 .LBE253: + 4867 .LBE252: +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4868 .loc 1 2607 0 + 4869 0084 0020 movs r0, #0 + 4870 0086 5DE0 b .L310 + 4871 .LVL454: + 4872 .L314: +2551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4873 .loc 1 2551 0 + 4874 0088 236A ldr r3, [r4, #32] + 4875 008a 304A ldr r2, .L323 + 4876 .LVL455: + 4877 008c DA62 str r2, [r3, #44] +2554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the DMA Stream */ + 4878 .loc 1 2554 0 + 4879 008e 236A ldr r3, [r4, #32] + 4880 0090 2F4A ldr r2, .L323+4 + 4881 0092 5A63 str r2, [r3, #52] +2556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4882 .loc 1 2556 0 + 4883 0094 2168 ldr r1, [r4] + 4884 .LVL456: + 4885 0096 3831 adds r1, r1, #56 + 4886 0098 3300 movs r3, r6 + 4887 009a 2A00 movs r2, r5 + 4888 009c 206A ldr r0, [r4, #32] + 4889 009e FFF7FEFF bl HAL_DMA_Start_IT + 4890 .LVL457: +2559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4891 .loc 1 2559 0 + 4892 00a2 2268 ldr r2, [r4] + 4893 00a4 D168 ldr r1, [r2, #12] + 4894 00a6 8023 movs r3, #128 + 4895 00a8 DB00 lsls r3, r3, #3 + 4896 00aa 0B43 orrs r3, r1 + 4897 00ac D360 str r3, [r2, #12] +2562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4898 .loc 1 2562 0 + ARM GAS /tmp/ccH6KUTS.s page 186 + + + 4899 00ae 2268 ldr r2, [r4] + 4900 00b0 1368 ldr r3, [r2] + 4901 00b2 0121 movs r1, #1 + 4902 00b4 0B43 orrs r3, r1 + 4903 00b6 1360 str r3, [r2] +2565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4904 .loc 1 2565 0 + 4905 00b8 2368 ldr r3, [r4] + 4906 .LVL458: + 4907 .LBB254: + 4908 .LBB255: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4909 .loc 1 4950 0 + 4910 00ba 196A ldr r1, [r3, #32] + 4911 00bc 1020 movs r0, #16 + 4912 00be 8143 bics r1, r0 + 4913 00c0 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4914 .loc 1 4953 0 + 4915 00c2 1A6A ldr r2, [r3, #32] + 4916 00c4 0243 orrs r2, r0 + 4917 00c6 1A62 str r2, [r3, #32] + 4918 .LBE255: + 4919 .LBE254: +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4920 .loc 1 2607 0 + 4921 00c8 0020 movs r0, #0 + 4922 00ca 3BE0 b .L310 + 4923 .LVL459: + 4924 .L315: +2572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4925 .loc 1 2572 0 + 4926 00cc E369 ldr r3, [r4, #28] + 4927 00ce 1F49 ldr r1, .L323 + 4928 .LVL460: + 4929 00d0 8846 mov r8, r1 + 4930 00d2 D962 str r1, [r3, #44] +2575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4931 .loc 1 2575 0 + 4932 00d4 E369 ldr r3, [r4, #28] + 4933 00d6 1E4F ldr r7, .L323+4 + 4934 00d8 5F63 str r7, [r3, #52] +2578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4935 .loc 1 2578 0 + 4936 00da 2168 ldr r1, [r4] + 4937 00dc 3431 adds r1, r1, #52 + 4938 00de 3300 movs r3, r6 + 4939 00e0 E069 ldr r0, [r4, #28] + 4940 00e2 FFF7FEFF bl HAL_DMA_Start_IT + 4941 .LVL461: +2581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4942 .loc 1 2581 0 + 4943 00e6 236A ldr r3, [r4, #32] + 4944 00e8 4246 mov r2, r8 + 4945 00ea DA62 str r2, [r3, #44] +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4946 .loc 1 2584 0 + ARM GAS /tmp/ccH6KUTS.s page 187 + + + 4947 00ec 236A ldr r3, [r4, #32] + 4948 00ee 5F63 str r7, [r3, #52] +2587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4949 .loc 1 2587 0 + 4950 00f0 2168 ldr r1, [r4] + 4951 00f2 3831 adds r1, r1, #56 + 4952 00f4 3300 movs r3, r6 + 4953 00f6 2A00 movs r2, r5 + 4954 00f8 206A ldr r0, [r4, #32] + 4955 00fa FFF7FEFF bl HAL_DMA_Start_IT + 4956 .LVL462: +2590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4957 .loc 1 2590 0 + 4958 00fe 2268 ldr r2, [r4] + 4959 0100 1368 ldr r3, [r2] + 4960 0102 0121 movs r1, #1 + 4961 0104 0B43 orrs r3, r1 + 4962 0106 1360 str r3, [r2] +2593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 4963 .loc 1 2593 0 + 4964 0108 2368 ldr r3, [r4] + 4965 .LVL463: + 4966 .LBB256: + 4967 .LBB257: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4968 .loc 1 4950 0 + 4969 010a 1A6A ldr r2, [r3, #32] + 4970 010c 8A43 bics r2, r1 + 4971 010e 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4972 .loc 1 4953 0 + 4973 0110 1A6A ldr r2, [r3, #32] + 4974 0112 0A43 orrs r2, r1 + 4975 0114 1A62 str r2, [r3, #32] + 4976 .LVL464: + 4977 .LBE257: + 4978 .LBE256: +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4979 .loc 1 2594 0 + 4980 0116 2368 ldr r3, [r4] + 4981 .LVL465: + 4982 .LBB258: + 4983 .LBB259: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 4984 .loc 1 4950 0 + 4985 0118 196A ldr r1, [r3, #32] + 4986 011a 1020 movs r0, #16 + 4987 011c 8143 bics r1, r0 + 4988 011e 1962 str r1, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 4989 .loc 1 4953 0 + 4990 0120 1A6A ldr r2, [r3, #32] + 4991 0122 0243 orrs r2, r0 + 4992 0124 1A62 str r2, [r3, #32] + 4993 .LVL466: + 4994 .LBE259: + 4995 .LBE258: + ARM GAS /tmp/ccH6KUTS.s page 188 + + +2597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ + 4996 .loc 1 2597 0 + 4997 0126 2268 ldr r2, [r4] + 4998 0128 D168 ldr r1, [r2, #12] + 4999 012a 8023 movs r3, #128 + 5000 012c 9B00 lsls r3, r3, #2 + 5001 012e 0B43 orrs r3, r1 + 5002 0130 D360 str r3, [r2, #12] +2599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5003 .loc 1 2599 0 + 5004 0132 2268 ldr r2, [r4] + 5005 0134 D168 ldr r1, [r2, #12] + 5006 0136 8023 movs r3, #128 + 5007 0138 DB00 lsls r3, r3, #3 + 5008 013a 0B43 orrs r3, r1 + 5009 013c D360 str r3, [r2, #12] +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5010 .loc 1 2607 0 + 5011 013e 0020 movs r0, #0 +2601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5012 .loc 1 2601 0 + 5013 0140 00E0 b .L310 + 5014 .LVL467: + 5015 .L317: +2510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5016 .loc 1 2510 0 + 5017 0142 0220 movs r0, #2 + 5018 .LVL468: + 5019 .L310: +2608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5020 .loc 1 2608 0 + 5021 @ sp needed + 5022 .LVL469: + 5023 .LVL470: + 5024 0144 04BC pop {r2} + 5025 0146 9046 mov r8, r2 + 5026 0148 F0BD pop {r4, r5, r6, r7, pc} + 5027 .L324: + 5028 014a C046 .align 2 + 5029 .L323: + 5030 014c 00000000 .word TIM_DMACaptureCplt + 5031 0150 00000000 .word TIM_DMAError + 5032 .cfi_endproc + 5033 .LFE95: + 5035 .section .text.HAL_TIM_Encoder_Stop_DMA,"ax",%progbits + 5036 .align 1 + 5037 .global HAL_TIM_Encoder_Stop_DMA + 5038 .syntax unified + 5039 .code 16 + 5040 .thumb_func + 5041 .fpu softvfp + 5043 HAL_TIM_Encoder_Stop_DMA: + 5044 .LFB96: +2621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 5045 .loc 1 2621 0 + 5046 .cfi_startproc + 5047 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccH6KUTS.s page 189 + + + 5048 @ frame_needed = 0, uses_anonymous_args = 0 + 5049 @ link register save eliminated. + 5050 .LVL471: +2627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5051 .loc 1 2627 0 + 5052 0000 0029 cmp r1, #0 + 5053 0002 19D1 bne .L326 +2629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5054 .loc 1 2629 0 + 5055 0004 0368 ldr r3, [r0] + 5056 .LVL472: + 5057 .LBB260: + 5058 .LBB261: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5059 .loc 1 4950 0 + 5060 0006 1A6A ldr r2, [r3, #32] + 5061 0008 0131 adds r1, r1, #1 + 5062 .LVL473: + 5063 000a 8A43 bics r2, r1 + 5064 000c 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5065 .loc 1 4953 0 + 5066 000e 1A6A ldr r2, [r3, #32] + 5067 0010 1A62 str r2, [r3, #32] + 5068 .LVL474: + 5069 .LBE261: + 5070 .LBE260: +2632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5071 .loc 1 2632 0 + 5072 0012 0268 ldr r2, [r0] + 5073 0014 D368 ldr r3, [r2, #12] + 5074 0016 1C49 ldr r1, .L331 + 5075 .LVL475: + 5076 0018 0B40 ands r3, r1 + 5077 001a D360 str r3, [r2, #12] + 5078 .L327: +2652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5079 .loc 1 2652 0 + 5080 001c 0368 ldr r3, [r0] + 5081 001e 196A ldr r1, [r3, #32] + 5082 0020 1A4A ldr r2, .L331+4 + 5083 0022 1142 tst r1, r2 + 5084 0024 03D1 bne .L329 +2652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5085 .loc 1 2652 0 is_stmt 0 discriminator 1 + 5086 0026 1A68 ldr r2, [r3] + 5087 0028 0121 movs r1, #1 + 5088 002a 8A43 bics r2, r1 + 5089 002c 1A60 str r2, [r3] + 5090 .L329: +2655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5091 .loc 1 2655 0 is_stmt 1 + 5092 002e 3523 movs r3, #53 + 5093 0030 0122 movs r2, #1 + 5094 0032 C254 strb r2, [r0, r3] +2659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5095 .loc 1 2659 0 + ARM GAS /tmp/ccH6KUTS.s page 190 + + + 5096 0034 0020 movs r0, #0 + 5097 .LVL476: + 5098 @ sp needed + 5099 0036 7047 bx lr + 5100 .LVL477: + 5101 .L326: +2634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5102 .loc 1 2634 0 + 5103 0038 0429 cmp r1, #4 + 5104 003a 18D0 beq .L330 +2643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 5105 .loc 1 2643 0 + 5106 003c 0368 ldr r3, [r0] + 5107 .LVL478: + 5108 .LBB262: + 5109 .LBB263: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5110 .loc 1 4950 0 + 5111 003e 1A6A ldr r2, [r3, #32] + 5112 0040 0121 movs r1, #1 + 5113 .LVL479: + 5114 0042 8A43 bics r2, r1 + 5115 0044 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5116 .loc 1 4953 0 + 5117 0046 1A6A ldr r2, [r3, #32] + 5118 0048 1A62 str r2, [r3, #32] + 5119 .LVL480: + 5120 .LBE263: + 5121 .LBE262: +2644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5122 .loc 1 2644 0 + 5123 004a 0368 ldr r3, [r0] + 5124 .LVL481: + 5125 .LBB264: + 5126 .LBB265: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5127 .loc 1 4950 0 + 5128 004c 1A6A ldr r2, [r3, #32] + 5129 004e 0F31 adds r1, r1, #15 + 5130 0050 8A43 bics r2, r1 + 5131 0052 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5132 .loc 1 4953 0 + 5133 0054 1A6A ldr r2, [r3, #32] + 5134 0056 1A62 str r2, [r3, #32] + 5135 .LVL482: + 5136 .LBE265: + 5137 .LBE264: +2647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 5138 .loc 1 2647 0 + 5139 0058 0268 ldr r2, [r0] + 5140 005a D368 ldr r3, [r2, #12] + 5141 005c 0A49 ldr r1, .L331 + 5142 005e 0B40 ands r3, r1 + 5143 0060 D360 str r3, [r2, #12] +2648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 191 + + + 5144 .loc 1 2648 0 + 5145 0062 0268 ldr r2, [r0] + 5146 0064 D368 ldr r3, [r2, #12] + 5147 0066 0A49 ldr r1, .L331+8 + 5148 0068 0B40 ands r3, r1 + 5149 006a D360 str r3, [r2, #12] + 5150 006c D6E7 b .L327 + 5151 .LVL483: + 5152 .L330: +2636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5153 .loc 1 2636 0 + 5154 006e 0368 ldr r3, [r0] + 5155 .LVL484: + 5156 .LBB266: + 5157 .LBB267: +4950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5158 .loc 1 4950 0 + 5159 0070 1A6A ldr r2, [r3, #32] + 5160 0072 0C31 adds r1, r1, #12 + 5161 .LVL485: + 5162 0074 8A43 bics r2, r1 + 5163 0076 1A62 str r2, [r3, #32] +4953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5164 .loc 1 4953 0 + 5165 0078 1A6A ldr r2, [r3, #32] + 5166 007a 1A62 str r2, [r3, #32] + 5167 .LVL486: + 5168 .LBE267: + 5169 .LBE266: +2639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5170 .loc 1 2639 0 + 5171 007c 0268 ldr r2, [r0] + 5172 007e D368 ldr r3, [r2, #12] + 5173 0080 0349 ldr r1, .L331+8 + 5174 .LVL487: + 5175 0082 0B40 ands r3, r1 + 5176 0084 D360 str r3, [r2, #12] + 5177 0086 C9E7 b .L327 + 5178 .L332: + 5179 .align 2 + 5180 .L331: + 5181 0088 FFFDFFFF .word -513 + 5182 008c 11110000 .word 4369 + 5183 0090 FFFBFFFF .word -1025 + 5184 .cfi_endproc + 5185 .LFE96: + 5187 .section .text.HAL_TIM_OC_ConfigChannel,"ax",%progbits + 5188 .align 1 + 5189 .global HAL_TIM_OC_ConfigChannel + 5190 .syntax unified + 5191 .code 16 + 5192 .thumb_func + 5193 .fpu softvfp + 5195 HAL_TIM_OC_ConfigChannel: + 5196 .LFB98: +2827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 5197 .loc 1 2827 0 + ARM GAS /tmp/ccH6KUTS.s page 192 + + + 5198 .cfi_startproc + 5199 @ args = 0, pretend = 0, frame = 0 + 5200 @ frame_needed = 0, uses_anonymous_args = 0 + 5201 .LVL488: + 5202 0000 70B5 push {r4, r5, r6, lr} + 5203 .LCFI38: + 5204 .cfi_def_cfa_offset 16 + 5205 .cfi_offset 4, -16 + 5206 .cfi_offset 5, -12 + 5207 .cfi_offset 6, -8 + 5208 .cfi_offset 14, -4 +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5209 .loc 1 2834 0 + 5210 0002 3423 movs r3, #52 + 5211 0004 C35C ldrb r3, [r0, r3] + 5212 0006 012B cmp r3, #1 + 5213 0008 00D1 bne .LCB4995 + 5214 000a 72E0 b .L341 @long jump + 5215 .LCB4995: +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5216 .loc 1 2834 0 is_stmt 0 discriminator 2 + 5217 000c 3423 movs r3, #52 + 5218 000e 0124 movs r4, #1 + 5219 0010 C454 strb r4, [r0, r3] +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5220 .loc 1 2836 0 is_stmt 1 discriminator 2 + 5221 0012 0133 adds r3, r3, #1 + 5222 0014 0134 adds r4, r4, #1 + 5223 0016 C454 strb r4, [r0, r3] +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5224 .loc 1 2838 0 discriminator 2 + 5225 0018 042A cmp r2, #4 + 5226 001a 3BD0 beq .L336 + 5227 001c 1BD9 bls .L342 + 5228 001e 082A cmp r2, #8 + 5229 0020 50D0 beq .L339 + 5230 0022 0C2A cmp r2, #12 + 5231 0024 2ED1 bne .L335 +2868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5232 .loc 1 2868 0 + 5233 0026 0368 ldr r3, [r0] + 5234 .LVL489: + 5235 .LBB268: + 5236 .LBB269: +4572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5237 .loc 1 4572 0 + 5238 0028 1A6A ldr r2, [r3, #32] + 5239 .LVL490: + 5240 002a 334C ldr r4, .L343 + 5241 002c 2240 ands r2, r4 + 5242 002e 1A62 str r2, [r3, #32] +4575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5243 .loc 1 4575 0 + 5244 0030 1A6A ldr r2, [r3, #32] + 5245 .LVL491: +4577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5246 .loc 1 4577 0 + ARM GAS /tmp/ccH6KUTS.s page 193 + + + 5247 0032 5E68 ldr r6, [r3, #4] + 5248 .LVL492: +4580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5249 .loc 1 4580 0 + 5250 0034 DC69 ldr r4, [r3, #28] + 5251 .LVL493: +4584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5252 .loc 1 4584 0 + 5253 0036 314D ldr r5, .L343+4 + 5254 0038 2C40 ands r4, r5 + 5255 .LVL494: +4587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5256 .loc 1 4587 0 + 5257 003a 0D68 ldr r5, [r1] + 5258 003c 2D02 lsls r5, r5, #8 + 5259 003e 2C43 orrs r4, r5 + 5260 .LVL495: +4590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5261 .loc 1 4590 0 + 5262 0040 2F4D ldr r5, .L343+8 + 5263 0042 2A40 ands r2, r5 + 5264 .LVL496: +4592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5265 .loc 1 4592 0 + 5266 0044 8D68 ldr r5, [r1, #8] + 5267 0046 2D03 lsls r5, r5, #12 + 5268 0048 2A43 orrs r2, r5 + 5269 .LVL497: +4595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5270 .loc 1 4595 0 + 5271 004a 5E60 str r6, [r3, #4] +4598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5272 .loc 1 4598 0 + 5273 004c DC61 str r4, [r3, #28] +4601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5274 .loc 1 4601 0 + 5275 004e 4968 ldr r1, [r1, #4] + 5276 .LVL498: + 5277 0050 1964 str r1, [r3, #64] +4604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5278 .loc 1 4604 0 + 5279 0052 1A62 str r2, [r3, #32] + 5280 0054 16E0 b .L335 + 5281 .LVL499: + 5282 .L342: + 5283 .LBE269: + 5284 .LBE268: +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5285 .loc 1 2838 0 discriminator 2 + 5286 0056 002A cmp r2, #0 + 5287 0058 14D1 bne .L335 +2844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5288 .loc 1 2844 0 + 5289 005a 0368 ldr r3, [r0] + 5290 .LVL500: + 5291 .LBB270: + 5292 .LBB271: + ARM GAS /tmp/ccH6KUTS.s page 194 + + +4430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5293 .loc 1 4430 0 + 5294 005c 1A6A ldr r2, [r3, #32] + 5295 .LVL501: + 5296 005e 0124 movs r4, #1 + 5297 0060 A243 bics r2, r4 + 5298 0062 1A62 str r2, [r3, #32] +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5299 .loc 1 4433 0 + 5300 0064 1A6A ldr r2, [r3, #32] + 5301 .LVL502: +4435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5302 .loc 1 4435 0 + 5303 0066 5D68 ldr r5, [r3, #4] + 5304 .LVL503: +4438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5305 .loc 1 4438 0 + 5306 0068 9C69 ldr r4, [r3, #24] + 5307 .LVL504: +4442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ + 5308 .loc 1 4442 0 + 5309 006a 7326 movs r6, #115 + 5310 006c B443 bics r4, r6 + 5311 .LVL505: +4444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5312 .loc 1 4444 0 + 5313 006e 0E68 ldr r6, [r1] + 5314 0070 3443 orrs r4, r6 + 5315 .LVL506: +4447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5316 .loc 1 4447 0 + 5317 0072 0226 movs r6, #2 + 5318 0074 B243 bics r2, r6 + 5319 .LVL507: +4449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5320 .loc 1 4449 0 + 5321 0076 8E68 ldr r6, [r1, #8] + 5322 0078 3243 orrs r2, r6 + 5323 .LVL508: +4452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5324 .loc 1 4452 0 + 5325 007a 5D60 str r5, [r3, #4] +4455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5326 .loc 1 4455 0 + 5327 007c 9C61 str r4, [r3, #24] +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5328 .loc 1 4458 0 + 5329 007e 4968 ldr r1, [r1, #4] + 5330 .LVL509: + 5331 0080 5963 str r1, [r3, #52] +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5332 .loc 1 4461 0 + 5333 0082 1A62 str r2, [r3, #32] + 5334 .LVL510: + 5335 .L335: + 5336 .LBE271: + 5337 .LBE270: + ARM GAS /tmp/ccH6KUTS.s page 195 + + +2875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5338 .loc 1 2875 0 + 5339 0084 3523 movs r3, #53 + 5340 0086 0122 movs r2, #1 + 5341 0088 C254 strb r2, [r0, r3] +2877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5342 .loc 1 2877 0 + 5343 008a 013B subs r3, r3, #1 + 5344 008c 0022 movs r2, #0 + 5345 008e C254 strb r2, [r0, r3] +2879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5346 .loc 1 2879 0 + 5347 0090 0020 movs r0, #0 + 5348 .LVL511: + 5349 .L334: +2880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5350 .loc 1 2880 0 + 5351 @ sp needed + 5352 0092 70BD pop {r4, r5, r6, pc} + 5353 .LVL512: + 5354 .L336: +2852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5355 .loc 1 2852 0 + 5356 0094 0368 ldr r3, [r0] + 5357 .LVL513: + 5358 .LBB272: + 5359 .LBB273: +4477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5360 .loc 1 4477 0 + 5361 0096 1A6A ldr r2, [r3, #32] + 5362 .LVL514: + 5363 0098 1024 movs r4, #16 + 5364 009a A243 bics r2, r4 + 5365 009c 1A62 str r2, [r3, #32] +4480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5366 .loc 1 4480 0 + 5367 009e 1A6A ldr r2, [r3, #32] + 5368 .LVL515: +4482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5369 .loc 1 4482 0 + 5370 00a0 5E68 ldr r6, [r3, #4] + 5371 .LVL516: +4485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5372 .loc 1 4485 0 + 5373 00a2 9C69 ldr r4, [r3, #24] + 5374 .LVL517: +4489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5375 .loc 1 4489 0 + 5376 00a4 154D ldr r5, .L343+4 + 5377 00a6 2C40 ands r4, r5 + 5378 .LVL518: +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5379 .loc 1 4492 0 + 5380 00a8 0D68 ldr r5, [r1] + 5381 00aa 2D02 lsls r5, r5, #8 + 5382 00ac 2C43 orrs r4, r5 + 5383 .LVL519: + ARM GAS /tmp/ccH6KUTS.s page 196 + + +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5384 .loc 1 4495 0 + 5385 00ae 2025 movs r5, #32 + 5386 00b0 AA43 bics r2, r5 + 5387 .LVL520: +4497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5388 .loc 1 4497 0 + 5389 00b2 8D68 ldr r5, [r1, #8] + 5390 00b4 2D01 lsls r5, r5, #4 + 5391 00b6 2A43 orrs r2, r5 + 5392 .LVL521: +4500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5393 .loc 1 4500 0 + 5394 00b8 5E60 str r6, [r3, #4] +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5395 .loc 1 4503 0 + 5396 00ba 9C61 str r4, [r3, #24] +4506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5397 .loc 1 4506 0 + 5398 00bc 4968 ldr r1, [r1, #4] + 5399 .LVL522: + 5400 00be 9963 str r1, [r3, #56] +4509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5401 .loc 1 4509 0 + 5402 00c0 1A62 str r2, [r3, #32] + 5403 00c2 DFE7 b .L335 + 5404 .LVL523: + 5405 .L339: + 5406 .LBE273: + 5407 .LBE272: +2860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5408 .loc 1 2860 0 + 5409 00c4 0368 ldr r3, [r0] + 5410 .LVL524: + 5411 .LBB274: + 5412 .LBB275: +4525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5413 .loc 1 4525 0 + 5414 00c6 1A6A ldr r2, [r3, #32] + 5415 .LVL525: + 5416 00c8 0E4C ldr r4, .L343+12 + 5417 00ca 2240 ands r2, r4 + 5418 00cc 1A62 str r2, [r3, #32] +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5419 .loc 1 4528 0 + 5420 00ce 1A6A ldr r2, [r3, #32] + 5421 .LVL526: +4530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5422 .loc 1 4530 0 + 5423 00d0 5E68 ldr r6, [r3, #4] + 5424 .LVL527: +4533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5425 .loc 1 4533 0 + 5426 00d2 DC69 ldr r4, [r3, #28] + 5427 .LVL528: +4537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ + 5428 .loc 1 4537 0 + ARM GAS /tmp/ccH6KUTS.s page 197 + + + 5429 00d4 7325 movs r5, #115 + 5430 00d6 AC43 bics r4, r5 + 5431 .LVL529: +4539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5432 .loc 1 4539 0 + 5433 00d8 0D68 ldr r5, [r1] + 5434 00da 2C43 orrs r4, r5 + 5435 .LVL530: +4542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5436 .loc 1 4542 0 + 5437 00dc 0A4D ldr r5, .L343+16 + 5438 00de 2A40 ands r2, r5 + 5439 .LVL531: +4544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5440 .loc 1 4544 0 + 5441 00e0 8D68 ldr r5, [r1, #8] + 5442 00e2 2D02 lsls r5, r5, #8 + 5443 00e4 2A43 orrs r2, r5 + 5444 .LVL532: +4547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5445 .loc 1 4547 0 + 5446 00e6 5E60 str r6, [r3, #4] +4550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5447 .loc 1 4550 0 + 5448 00e8 DC61 str r4, [r3, #28] +4553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5449 .loc 1 4553 0 + 5450 00ea 4968 ldr r1, [r1, #4] + 5451 .LVL533: + 5452 00ec D963 str r1, [r3, #60] +4556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5453 .loc 1 4556 0 + 5454 00ee 1A62 str r2, [r3, #32] + 5455 00f0 C8E7 b .L335 + 5456 .LVL534: + 5457 .L341: + 5458 .LBE275: + 5459 .LBE274: +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5460 .loc 1 2834 0 + 5461 00f2 0220 movs r0, #2 + 5462 .LVL535: + 5463 00f4 CDE7 b .L334 + 5464 .L344: + 5465 00f6 C046 .align 2 + 5466 .L343: + 5467 00f8 FFEFFFFF .word -4097 + 5468 00fc FF8CFFFF .word -29441 + 5469 0100 FFDFFFFF .word -8193 + 5470 0104 FFFEFFFF .word -257 + 5471 0108 FFFDFFFF .word -513 + 5472 .cfi_endproc + 5473 .LFE98: + 5475 .section .text.HAL_TIM_IC_ConfigChannel,"ax",%progbits + 5476 .align 1 + 5477 .global HAL_TIM_IC_ConfigChannel + 5478 .syntax unified + ARM GAS /tmp/ccH6KUTS.s page 198 + + + 5479 .code 16 + 5480 .thumb_func + 5481 .fpu softvfp + 5483 HAL_TIM_IC_ConfigChannel: + 5484 .LFB99: +2896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 5485 .loc 1 2896 0 + 5486 .cfi_startproc + 5487 @ args = 0, pretend = 0, frame = 0 + 5488 @ frame_needed = 0, uses_anonymous_args = 0 + 5489 .LVL536: + 5490 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 5491 .LCFI39: + 5492 .cfi_def_cfa_offset 24 + 5493 .cfi_offset 3, -24 + 5494 .cfi_offset 4, -20 + 5495 .cfi_offset 5, -16 + 5496 .cfi_offset 6, -12 + 5497 .cfi_offset 7, -8 + 5498 .cfi_offset 14, -4 + 5499 0002 CE46 mov lr, r9 + 5500 0004 4746 mov r7, r8 + 5501 0006 80B5 push {r7, lr} + 5502 .LCFI40: + 5503 .cfi_def_cfa_offset 32 + 5504 .cfi_offset 8, -32 + 5505 .cfi_offset 9, -28 + 5506 0008 0400 movs r4, r0 + 5507 000a 0D00 movs r5, r1 +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5508 .loc 1 2904 0 + 5509 000c 3423 movs r3, #52 + 5510 000e C35C ldrb r3, [r0, r3] + 5511 0010 012B cmp r3, #1 + 5512 0012 00D1 bne .LCB5325 + 5513 0014 A8E0 b .L351 @long jump + 5514 .LCB5325: +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5515 .loc 1 2904 0 is_stmt 0 discriminator 2 + 5516 0016 3423 movs r3, #52 + 5517 0018 0121 movs r1, #1 + 5518 .LVL537: + 5519 001a C154 strb r1, [r0, r3] +2906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5520 .loc 1 2906 0 is_stmt 1 discriminator 2 + 5521 001c 0133 adds r3, r3, #1 + 5522 001e 0131 adds r1, r1, #1 + 5523 0020 C154 strb r1, [r0, r3] +2908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5524 .loc 1 2908 0 discriminator 2 + 5525 0022 002A cmp r2, #0 + 5526 0024 31D0 beq .L352 +2922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5527 .loc 1 2922 0 + 5528 0026 042A cmp r2, #4 + 5529 0028 4AD0 beq .L353 +2938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + ARM GAS /tmp/ccH6KUTS.s page 199 + + + 5530 .loc 1 2938 0 + 5531 002a 082A cmp r2, #8 + 5532 002c 00D1 bne .LCB5338 + 5533 002e 72E0 b .L354 @long jump + 5534 .LCB5338: +2959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, + 5535 .loc 1 2959 0 + 5536 0030 0268 ldr r2, [r0] + 5537 .LVL538: + 5538 0032 2868 ldr r0, [r5] + 5539 .LVL539: + 5540 0034 6F68 ldr r7, [r5, #4] + 5541 0036 EE68 ldr r6, [r5, #12] + 5542 .LVL540: + 5543 .LBB276: + 5544 .LBB277: +4844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 5545 .loc 1 4844 0 + 5546 0038 136A ldr r3, [r2, #32] + 5547 003a 4C49 ldr r1, .L355 + 5548 003c 0B40 ands r3, r1 + 5549 003e 1362 str r3, [r2, #32] +4845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 5550 .loc 1 4845 0 + 5551 0040 D369 ldr r3, [r2, #28] + 5552 .LVL541: + 5553 0042 9846 mov r8, r3 + 5554 .LVL542: +4846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5555 .loc 1 4846 0 + 5556 0044 136A ldr r3, [r2, #32] + 5557 .LVL543: + 5558 0046 9946 mov r9, r3 + 5559 .LVL544: +4849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= (TIM_ICSelection << 8U); + 5560 .loc 1 4849 0 + 5561 0048 494B ldr r3, .L355+4 + 5562 .LVL545: + 5563 004a 4146 mov r1, r8 + 5564 004c 1940 ands r1, r3 + 5565 004e 0B00 movs r3, r1 + 5566 .LVL546: +4850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5567 .loc 1 4850 0 + 5568 0050 3F02 lsls r7, r7, #8 + 5569 .LVL547: + 5570 0052 3B43 orrs r3, r7 + 5571 .LVL548: +4853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + 5572 .loc 1 4853 0 + 5573 0054 474F ldr r7, .L355+8 + 5574 0056 3B40 ands r3, r7 + 5575 .LVL549: +4854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5576 .loc 1 4854 0 + 5577 0058 3607 lsls r6, r6, #28 + 5578 .LVL550: + ARM GAS /tmp/ccH6KUTS.s page 200 + + + 5579 005a 360C lsrs r6, r6, #16 + 5580 005c 3343 orrs r3, r6 + 5581 .LVL551: +4857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + 5582 .loc 1 4857 0 + 5583 005e 464E ldr r6, .L355+12 + 5584 0060 4946 mov r1, r9 + 5585 0062 3140 ands r1, r6 + 5586 .LVL552: +4858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5587 .loc 1 4858 0 + 5588 0064 0003 lsls r0, r0, #12 + 5589 .LVL553: + 5590 0066 A026 movs r6, #160 + 5591 0068 3602 lsls r6, r6, #8 + 5592 006a 3040 ands r0, r6 + 5593 006c 0143 orrs r1, r0 + 5594 .LVL554: +4861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer ; + 5595 .loc 1 4861 0 + 5596 006e D361 str r3, [r2, #28] +4862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5597 .loc 1 4862 0 + 5598 0070 1162 str r1, [r2, #32] + 5599 .LVL555: + 5600 .LBE277: + 5601 .LBE276: +2965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5602 .loc 1 2965 0 + 5603 0072 2268 ldr r2, [r4] + 5604 0074 D369 ldr r3, [r2, #28] + 5605 0076 4149 ldr r1, .L355+16 + 5606 0078 0B40 ands r3, r1 + 5607 007a D361 str r3, [r2, #28] +2968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5608 .loc 1 2968 0 + 5609 007c 2168 ldr r1, [r4] + 5610 007e CB69 ldr r3, [r1, #28] + 5611 0080 AA68 ldr r2, [r5, #8] + 5612 0082 1202 lsls r2, r2, #8 + 5613 0084 1343 orrs r3, r2 + 5614 0086 CB61 str r3, [r1, #28] + 5615 0088 0FE0 b .L348 + 5616 .LVL556: + 5617 .L352: +2911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, + 5618 .loc 1 2911 0 + 5619 008a EB68 ldr r3, [r5, #12] + 5620 008c 6A68 ldr r2, [r5, #4] + 5621 .LVL557: + 5622 008e 2968 ldr r1, [r5] + 5623 0090 0068 ldr r0, [r0] + 5624 .LVL558: + 5625 0092 FFF7FEFF bl TIM_TI1_SetConfig + 5626 .LVL559: +2917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5627 .loc 1 2917 0 + ARM GAS /tmp/ccH6KUTS.s page 201 + + + 5628 0096 2268 ldr r2, [r4] + 5629 0098 9369 ldr r3, [r2, #24] + 5630 009a 0C21 movs r1, #12 + 5631 009c 8B43 bics r3, r1 + 5632 009e 9361 str r3, [r2, #24] +2920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5633 .loc 1 2920 0 + 5634 00a0 2268 ldr r2, [r4] + 5635 00a2 9369 ldr r3, [r2, #24] + 5636 00a4 A968 ldr r1, [r5, #8] + 5637 00a6 0B43 orrs r3, r1 + 5638 00a8 9361 str r3, [r2, #24] + 5639 .L348: +2971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5640 .loc 1 2971 0 + 5641 00aa 3523 movs r3, #53 + 5642 00ac 0122 movs r2, #1 + 5643 00ae E254 strb r2, [r4, r3] +2973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5644 .loc 1 2973 0 + 5645 00b0 013B subs r3, r3, #1 + 5646 00b2 0022 movs r2, #0 + 5647 00b4 E254 strb r2, [r4, r3] +2975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5648 .loc 1 2975 0 + 5649 00b6 0020 movs r0, #0 + 5650 .L346: +2976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5651 .loc 1 2976 0 + 5652 @ sp needed + 5653 .LVL560: + 5654 .LVL561: + 5655 00b8 0CBC pop {r2, r3} + 5656 00ba 9046 mov r8, r2 + 5657 00bc 9946 mov r9, r3 + 5658 00be F8BD pop {r3, r4, r5, r6, r7, pc} + 5659 .LVL562: + 5660 .L353: +2927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, + 5661 .loc 1 2927 0 + 5662 00c0 0268 ldr r2, [r0] + 5663 .LVL563: + 5664 00c2 2E68 ldr r6, [r5] + 5665 00c4 6F68 ldr r7, [r5, #4] + 5666 00c6 E868 ldr r0, [r5, #12] + 5667 .LVL564: + 5668 .LBB278: + 5669 .LBB279: +4719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 5670 .loc 1 4719 0 + 5671 00c8 136A ldr r3, [r2, #32] + 5672 00ca 1021 movs r1, #16 + 5673 00cc 8B43 bics r3, r1 + 5674 00ce 1362 str r3, [r2, #32] +4720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 5675 .loc 1 4720 0 + 5676 00d0 9369 ldr r3, [r2, #24] + ARM GAS /tmp/ccH6KUTS.s page 202 + + + 5677 .LVL565: + 5678 00d2 9846 mov r8, r3 + 5679 .LVL566: +4721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5680 .loc 1 4721 0 + 5681 00d4 136A ldr r3, [r2, #32] + 5682 .LVL567: + 5683 00d6 9946 mov r9, r3 + 5684 .LVL568: +4724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICSelection << 8U); + 5685 .loc 1 4724 0 + 5686 00d8 254B ldr r3, .L355+4 + 5687 .LVL569: + 5688 00da 4146 mov r1, r8 + 5689 00dc 1940 ands r1, r3 + 5690 00de 0B00 movs r3, r1 + 5691 .LVL570: +4725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5692 .loc 1 4725 0 + 5693 00e0 3F02 lsls r7, r7, #8 + 5694 .LVL571: + 5695 00e2 3B43 orrs r3, r7 + 5696 .LVL572: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + 5697 .loc 1 4728 0 + 5698 00e4 234F ldr r7, .L355+8 + 5699 00e6 3B40 ands r3, r7 + 5700 .LVL573: +4729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5701 .loc 1 4729 0 + 5702 00e8 0007 lsls r0, r0, #28 + 5703 .LVL574: + 5704 00ea 000C lsrs r0, r0, #16 + 5705 00ec 0343 orrs r3, r0 + 5706 .LVL575: +4732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + 5707 .loc 1 4732 0 + 5708 00ee A020 movs r0, #160 + 5709 00f0 4946 mov r1, r9 + 5710 00f2 8143 bics r1, r0 + 5711 .LVL576: +4733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5712 .loc 1 4733 0 + 5713 00f4 3601 lsls r6, r6, #4 + 5714 .LVL577: + 5715 00f6 3040 ands r0, r6 + 5716 00f8 0143 orrs r1, r0 + 5717 .LVL578: +4736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 5718 .loc 1 4736 0 + 5719 00fa 9361 str r3, [r2, #24] +4737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5720 .loc 1 4737 0 + 5721 00fc 1162 str r1, [r2, #32] + 5722 .LVL579: + 5723 .LBE279: + 5724 .LBE278: + ARM GAS /tmp/ccH6KUTS.s page 203 + + +2933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5725 .loc 1 2933 0 + 5726 00fe 2268 ldr r2, [r4] + 5727 0100 9369 ldr r3, [r2, #24] + 5728 0102 1E49 ldr r1, .L355+16 + 5729 0104 0B40 ands r3, r1 + 5730 0106 9361 str r3, [r2, #24] +2936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5731 .loc 1 2936 0 + 5732 0108 2168 ldr r1, [r4] + 5733 010a 8B69 ldr r3, [r1, #24] + 5734 010c AA68 ldr r2, [r5, #8] + 5735 010e 1202 lsls r2, r2, #8 + 5736 0110 1343 orrs r3, r2 + 5737 0112 8B61 str r3, [r1, #24] + 5738 0114 C9E7 b .L348 + 5739 .LVL580: + 5740 .L354: +2943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICPolarity, + 5741 .loc 1 2943 0 + 5742 0116 0268 ldr r2, [r0] + 5743 .LVL581: + 5744 0118 2868 ldr r0, [r5] + 5745 .LVL582: + 5746 011a 6B68 ldr r3, [r5, #4] + 5747 011c 9846 mov r8, r3 + 5748 011e EE68 ldr r6, [r5, #12] + 5749 .LVL583: + 5750 .LBB280: + 5751 .LBB281: +4799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 5752 .loc 1 4799 0 + 5753 0120 116A ldr r1, [r2, #32] + 5754 0122 174F ldr r7, .L355+20 + 5755 0124 3940 ands r1, r7 + 5756 0126 1162 str r1, [r2, #32] +4800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 5757 .loc 1 4800 0 + 5758 0128 D769 ldr r7, [r2, #28] + 5759 .LVL584: +4801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5760 .loc 1 4801 0 + 5761 012a 116A ldr r1, [r2, #32] + 5762 .LVL585: +4804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= TIM_ICSelection; + 5763 .loc 1 4804 0 + 5764 012c 0323 movs r3, #3 + 5765 .LVL586: + 5766 012e 9F43 bics r7, r3 + 5767 .LVL587: +4805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5768 .loc 1 4805 0 + 5769 0130 4346 mov r3, r8 + 5770 0132 3B43 orrs r3, r7 + 5771 .LVL588: +4808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + 5772 .loc 1 4808 0 + ARM GAS /tmp/ccH6KUTS.s page 204 + + + 5773 0134 F027 movs r7, #240 + 5774 0136 BB43 bics r3, r7 + 5775 .LVL589: +4809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5776 .loc 1 4809 0 + 5777 0138 3701 lsls r7, r6, #4 + 5778 013a FF26 movs r6, #255 + 5779 .LVL590: + 5780 013c 3E40 ands r6, r7 + 5781 013e 3343 orrs r3, r6 + 5782 .LVL591: +4812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + 5783 .loc 1 4812 0 + 5784 0140 104E ldr r6, .L355+24 + 5785 0142 3140 ands r1, r6 + 5786 .LVL592: +4813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5787 .loc 1 4813 0 + 5788 0144 0002 lsls r0, r0, #8 + 5789 .LVL593: + 5790 0146 A026 movs r6, #160 + 5791 0148 3601 lsls r6, r6, #4 + 5792 014a 3040 ands r0, r6 + 5793 014c 0143 orrs r1, r0 + 5794 .LVL594: +4816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 5795 .loc 1 4816 0 + 5796 014e D361 str r3, [r2, #28] +4817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5797 .loc 1 4817 0 + 5798 0150 1162 str r1, [r2, #32] + 5799 .LVL595: + 5800 .LBE281: + 5801 .LBE280: +2949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5802 .loc 1 2949 0 + 5803 0152 2268 ldr r2, [r4] + 5804 0154 D369 ldr r3, [r2, #28] + 5805 0156 0C21 movs r1, #12 + 5806 0158 8B43 bics r3, r1 + 5807 015a D361 str r3, [r2, #28] +2952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5808 .loc 1 2952 0 + 5809 015c 2268 ldr r2, [r4] + 5810 015e D369 ldr r3, [r2, #28] + 5811 0160 A968 ldr r1, [r5, #8] + 5812 0162 0B43 orrs r3, r1 + 5813 0164 D361 str r3, [r2, #28] + 5814 0166 A0E7 b .L348 + 5815 .LVL596: + 5816 .L351: +2904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5817 .loc 1 2904 0 + 5818 0168 0220 movs r0, #2 + 5819 .LVL597: + 5820 016a A5E7 b .L346 + 5821 .L356: + ARM GAS /tmp/ccH6KUTS.s page 205 + + + 5822 .align 2 + 5823 .L355: + 5824 016c FFEFFFFF .word -4097 + 5825 0170 FFFCFFFF .word -769 + 5826 0174 FF0FFFFF .word -61441 + 5827 0178 FF5FFFFF .word -40961 + 5828 017c FFF3FFFF .word -3073 + 5829 0180 FFFEFFFF .word -257 + 5830 0184 FFF5FFFF .word -2561 + 5831 .cfi_endproc + 5832 .LFE99: + 5834 .section .text.HAL_TIM_PWM_ConfigChannel,"ax",%progbits + 5835 .align 1 + 5836 .global HAL_TIM_PWM_ConfigChannel + 5837 .syntax unified + 5838 .code 16 + 5839 .thumb_func + 5840 .fpu softvfp + 5842 HAL_TIM_PWM_ConfigChannel: + 5843 .LFB100: +2992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** __HAL_LOCK(htim); + 5844 .loc 1 2992 0 + 5845 .cfi_startproc + 5846 @ args = 0, pretend = 0, frame = 0 + 5847 @ frame_needed = 0, uses_anonymous_args = 0 + 5848 .LVL598: + 5849 0000 70B5 push {r4, r5, r6, lr} + 5850 .LCFI41: + 5851 .cfi_def_cfa_offset 16 + 5852 .cfi_offset 4, -16 + 5853 .cfi_offset 5, -12 + 5854 .cfi_offset 6, -8 + 5855 .cfi_offset 14, -4 +2993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5856 .loc 1 2993 0 + 5857 0002 3423 movs r3, #52 + 5858 0004 C35C ldrb r3, [r0, r3] + 5859 0006 012B cmp r3, #1 + 5860 0008 00D1 bne .LCB5681 + 5861 000a B3E0 b .L365 @long jump + 5862 .LCB5681: +2993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5863 .loc 1 2993 0 is_stmt 0 discriminator 2 + 5864 000c 3423 movs r3, #52 + 5865 000e 0124 movs r4, #1 + 5866 0010 C454 strb r4, [r0, r3] +3001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5867 .loc 1 3001 0 is_stmt 1 discriminator 2 + 5868 0012 0133 adds r3, r3, #1 + 5869 0014 0134 adds r4, r4, #1 + 5870 0016 C454 strb r4, [r0, r3] +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5871 .loc 1 3003 0 discriminator 2 + 5872 0018 042A cmp r2, #4 + 5873 001a 5CD0 beq .L360 + 5874 001c 2DD9 bls .L366 + 5875 001e 082A cmp r2, #8 + ARM GAS /tmp/ccH6KUTS.s page 206 + + + 5876 0020 00D1 bne .LCB5693 + 5877 0022 81E0 b .L363 @long jump + 5878 .LCB5693: + 5879 0024 0C2A cmp r2, #12 + 5880 0026 4ED1 bne .L359 +3054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5881 .loc 1 3054 0 + 5882 0028 0368 ldr r3, [r0] + 5883 .LVL599: + 5884 .LBB282: + 5885 .LBB283: +4572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5886 .loc 1 4572 0 + 5887 002a 1A6A ldr r2, [r3, #32] + 5888 .LVL600: + 5889 002c 524C ldr r4, .L367 + 5890 002e 2240 ands r2, r4 + 5891 0030 1A62 str r2, [r3, #32] +4575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5892 .loc 1 4575 0 + 5893 0032 1A6A ldr r2, [r3, #32] + 5894 .LVL601: +4577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5895 .loc 1 4577 0 + 5896 0034 5E68 ldr r6, [r3, #4] + 5897 .LVL602: +4580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5898 .loc 1 4580 0 + 5899 0036 DC69 ldr r4, [r3, #28] + 5900 .LVL603: +4584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5901 .loc 1 4584 0 + 5902 0038 504D ldr r5, .L367+4 + 5903 003a 2C40 ands r4, r5 + 5904 .LVL604: +4587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5905 .loc 1 4587 0 + 5906 003c 0D68 ldr r5, [r1] + 5907 003e 2D02 lsls r5, r5, #8 + 5908 0040 2C43 orrs r4, r5 + 5909 .LVL605: +4590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5910 .loc 1 4590 0 + 5911 0042 4F4D ldr r5, .L367+8 + 5912 0044 2A40 ands r2, r5 + 5913 .LVL606: +4592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5914 .loc 1 4592 0 + 5915 0046 8D68 ldr r5, [r1, #8] + 5916 0048 2D03 lsls r5, r5, #12 + 5917 004a 2A43 orrs r2, r5 + 5918 .LVL607: +4595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5919 .loc 1 4595 0 + 5920 004c 5E60 str r6, [r3, #4] +4598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5921 .loc 1 4598 0 + ARM GAS /tmp/ccH6KUTS.s page 207 + + + 5922 004e DC61 str r4, [r3, #28] +4601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5923 .loc 1 4601 0 + 5924 0050 4C68 ldr r4, [r1, #4] + 5925 .LVL608: + 5926 0052 1C64 str r4, [r3, #64] + 5927 .LVL609: +4604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5928 .loc 1 4604 0 + 5929 0054 1A62 str r2, [r3, #32] + 5930 .LVL610: + 5931 .LBE283: + 5932 .LBE282: +3057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5933 .loc 1 3057 0 + 5934 0056 0268 ldr r2, [r0] + 5935 0058 D469 ldr r4, [r2, #28] + 5936 005a 8023 movs r3, #128 + 5937 005c 1B01 lsls r3, r3, #4 + 5938 005e 2343 orrs r3, r4 + 5939 0060 D361 str r3, [r2, #28] +3060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 5940 .loc 1 3060 0 + 5941 0062 0268 ldr r2, [r0] + 5942 0064 D369 ldr r3, [r2, #28] + 5943 0066 474C ldr r4, .L367+12 + 5944 0068 2340 ands r3, r4 + 5945 006a D361 str r3, [r2, #28] +3061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 5946 .loc 1 3061 0 + 5947 006c 0468 ldr r4, [r0] + 5948 006e E369 ldr r3, [r4, #28] + 5949 0070 CA68 ldr r2, [r1, #12] + 5950 0072 1202 lsls r2, r2, #8 + 5951 0074 1343 orrs r3, r2 + 5952 0076 E361 str r3, [r4, #28] +3063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5953 .loc 1 3063 0 + 5954 0078 25E0 b .L359 + 5955 .LVL611: + 5956 .L366: +3003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 5957 .loc 1 3003 0 discriminator 2 + 5958 007a 002A cmp r2, #0 + 5959 007c 23D1 bne .L359 +3009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5960 .loc 1 3009 0 + 5961 007e 0368 ldr r3, [r0] + 5962 .LVL612: + 5963 .LBB284: + 5964 .LBB285: +4430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5965 .loc 1 4430 0 + 5966 0080 1A6A ldr r2, [r3, #32] + 5967 .LVL613: + 5968 0082 0124 movs r4, #1 + 5969 0084 A243 bics r2, r4 + ARM GAS /tmp/ccH6KUTS.s page 208 + + + 5970 0086 1A62 str r2, [r3, #32] +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 5971 .loc 1 4433 0 + 5972 0088 1A6A ldr r2, [r3, #32] + 5973 .LVL614: +4435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5974 .loc 1 4435 0 + 5975 008a 5D68 ldr r5, [r3, #4] + 5976 .LVL615: +4438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5977 .loc 1 4438 0 + 5978 008c 9C69 ldr r4, [r3, #24] + 5979 .LVL616: +4442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ + 5980 .loc 1 4442 0 + 5981 008e 7326 movs r6, #115 + 5982 0090 B443 bics r4, r6 + 5983 .LVL617: +4444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5984 .loc 1 4444 0 + 5985 0092 0E68 ldr r6, [r1] + 5986 0094 3443 orrs r4, r6 + 5987 .LVL618: +4447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 5988 .loc 1 4447 0 + 5989 0096 0226 movs r6, #2 + 5990 0098 B243 bics r2, r6 + 5991 .LVL619: +4449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5992 .loc 1 4449 0 + 5993 009a 8E68 ldr r6, [r1, #8] + 5994 009c 3243 orrs r2, r6 + 5995 .LVL620: +4452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5996 .loc 1 4452 0 + 5997 009e 5D60 str r5, [r3, #4] +4455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 5998 .loc 1 4455 0 + 5999 00a0 9C61 str r4, [r3, #24] +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6000 .loc 1 4458 0 + 6001 00a2 4C68 ldr r4, [r1, #4] + 6002 .LVL621: + 6003 00a4 5C63 str r4, [r3, #52] + 6004 .LVL622: +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6005 .loc 1 4461 0 + 6006 00a6 1A62 str r2, [r3, #32] + 6007 .LVL623: + 6008 .LBE285: + 6009 .LBE284: +3012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6010 .loc 1 3012 0 + 6011 00a8 0268 ldr r2, [r0] + 6012 00aa 9369 ldr r3, [r2, #24] + 6013 00ac 0824 movs r4, #8 + 6014 00ae 2343 orrs r3, r4 + ARM GAS /tmp/ccH6KUTS.s page 209 + + + 6015 00b0 9361 str r3, [r2, #24] +3015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 6016 .loc 1 3015 0 + 6017 00b2 0268 ldr r2, [r0] + 6018 00b4 9369 ldr r3, [r2, #24] + 6019 00b6 043C subs r4, r4, #4 + 6020 00b8 A343 bics r3, r4 + 6021 00ba 9361 str r3, [r2, #24] +3016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6022 .loc 1 3016 0 + 6023 00bc 0268 ldr r2, [r0] + 6024 00be 9369 ldr r3, [r2, #24] + 6025 00c0 C968 ldr r1, [r1, #12] + 6026 .LVL624: + 6027 00c2 0B43 orrs r3, r1 + 6028 00c4 9361 str r3, [r2, #24] + 6029 .L359: +3069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6030 .loc 1 3069 0 + 6031 00c6 3523 movs r3, #53 + 6032 00c8 0122 movs r2, #1 + 6033 00ca C254 strb r2, [r0, r3] +3071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6034 .loc 1 3071 0 + 6035 00cc 013B subs r3, r3, #1 + 6036 00ce 0022 movs r2, #0 + 6037 00d0 C254 strb r2, [r0, r3] +3073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6038 .loc 1 3073 0 + 6039 00d2 0020 movs r0, #0 + 6040 .LVL625: + 6041 .L358: +3074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6042 .loc 1 3074 0 + 6043 @ sp needed + 6044 00d4 70BD pop {r4, r5, r6, pc} + 6045 .LVL626: + 6046 .L360: +3024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6047 .loc 1 3024 0 + 6048 00d6 0368 ldr r3, [r0] + 6049 .LVL627: + 6050 .LBB286: + 6051 .LBB287: +4477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6052 .loc 1 4477 0 + 6053 00d8 1A6A ldr r2, [r3, #32] + 6054 .LVL628: + 6055 00da 1024 movs r4, #16 + 6056 00dc A243 bics r2, r4 + 6057 00de 1A62 str r2, [r3, #32] +4480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 6058 .loc 1 4480 0 + 6059 00e0 1A6A ldr r2, [r3, #32] + 6060 .LVL629: +4482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6061 .loc 1 4482 0 + ARM GAS /tmp/ccH6KUTS.s page 210 + + + 6062 00e2 5E68 ldr r6, [r3, #4] + 6063 .LVL630: +4485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6064 .loc 1 4485 0 + 6065 00e4 9C69 ldr r4, [r3, #24] + 6066 .LVL631: +4489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6067 .loc 1 4489 0 + 6068 00e6 254D ldr r5, .L367+4 + 6069 00e8 2C40 ands r4, r5 + 6070 .LVL632: +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6071 .loc 1 4492 0 + 6072 00ea 0D68 ldr r5, [r1] + 6073 00ec 2D02 lsls r5, r5, #8 + 6074 00ee 2C43 orrs r4, r5 + 6075 .LVL633: +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6076 .loc 1 4495 0 + 6077 00f0 2025 movs r5, #32 + 6078 00f2 AA43 bics r2, r5 + 6079 .LVL634: +4497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6080 .loc 1 4497 0 + 6081 00f4 8D68 ldr r5, [r1, #8] + 6082 00f6 2D01 lsls r5, r5, #4 + 6083 00f8 2A43 orrs r2, r5 + 6084 .LVL635: +4500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6085 .loc 1 4500 0 + 6086 00fa 5E60 str r6, [r3, #4] +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6087 .loc 1 4503 0 + 6088 00fc 9C61 str r4, [r3, #24] +4506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6089 .loc 1 4506 0 + 6090 00fe 4C68 ldr r4, [r1, #4] + 6091 .LVL636: + 6092 0100 9C63 str r4, [r3, #56] + 6093 .LVL637: +4509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6094 .loc 1 4509 0 + 6095 0102 1A62 str r2, [r3, #32] + 6096 .LVL638: + 6097 .LBE287: + 6098 .LBE286: +3027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6099 .loc 1 3027 0 + 6100 0104 0268 ldr r2, [r0] + 6101 0106 9469 ldr r4, [r2, #24] + 6102 0108 8023 movs r3, #128 + 6103 010a 1B01 lsls r3, r3, #4 + 6104 010c 2343 orrs r3, r4 + 6105 010e 9361 str r3, [r2, #24] +3030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 6106 .loc 1 3030 0 + 6107 0110 0268 ldr r2, [r0] + ARM GAS /tmp/ccH6KUTS.s page 211 + + + 6108 0112 9369 ldr r3, [r2, #24] + 6109 0114 1B4C ldr r4, .L367+12 + 6110 0116 2340 ands r3, r4 + 6111 0118 9361 str r3, [r2, #24] +3031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6112 .loc 1 3031 0 + 6113 011a 0468 ldr r4, [r0] + 6114 011c A369 ldr r3, [r4, #24] + 6115 011e CA68 ldr r2, [r1, #12] + 6116 0120 1202 lsls r2, r2, #8 + 6117 0122 1343 orrs r3, r2 + 6118 0124 A361 str r3, [r4, #24] +3033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6119 .loc 1 3033 0 + 6120 0126 CEE7 b .L359 + 6121 .LVL639: + 6122 .L363: +3039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6123 .loc 1 3039 0 + 6124 0128 0368 ldr r3, [r0] + 6125 .LVL640: + 6126 .LBB288: + 6127 .LBB289: +4525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6128 .loc 1 4525 0 + 6129 012a 1A6A ldr r2, [r3, #32] + 6130 .LVL641: + 6131 012c 164C ldr r4, .L367+16 + 6132 012e 2240 ands r2, r4 + 6133 0130 1A62 str r2, [r3, #32] +4528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 6134 .loc 1 4528 0 + 6135 0132 1A6A ldr r2, [r3, #32] + 6136 .LVL642: +4530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6137 .loc 1 4530 0 + 6138 0134 5E68 ldr r6, [r3, #4] + 6139 .LVL643: +4533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6140 .loc 1 4533 0 + 6141 0136 DC69 ldr r4, [r3, #28] + 6142 .LVL644: +4537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ + 6143 .loc 1 4537 0 + 6144 0138 7325 movs r5, #115 + 6145 013a AC43 bics r4, r5 + 6146 .LVL645: +4539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6147 .loc 1 4539 0 + 6148 013c 0D68 ldr r5, [r1] + 6149 013e 2C43 orrs r4, r5 + 6150 .LVL646: +4542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6151 .loc 1 4542 0 + 6152 0140 124D ldr r5, .L367+20 + 6153 0142 2A40 ands r2, r5 + 6154 .LVL647: + ARM GAS /tmp/ccH6KUTS.s page 212 + + +4544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6155 .loc 1 4544 0 + 6156 0144 8D68 ldr r5, [r1, #8] + 6157 0146 2D02 lsls r5, r5, #8 + 6158 0148 2A43 orrs r2, r5 + 6159 .LVL648: +4547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6160 .loc 1 4547 0 + 6161 014a 5E60 str r6, [r3, #4] +4550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6162 .loc 1 4550 0 + 6163 014c DC61 str r4, [r3, #28] +4553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6164 .loc 1 4553 0 + 6165 014e 4C68 ldr r4, [r1, #4] + 6166 .LVL649: + 6167 0150 DC63 str r4, [r3, #60] + 6168 .LVL650: +4556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6169 .loc 1 4556 0 + 6170 0152 1A62 str r2, [r3, #32] + 6171 .LVL651: + 6172 .LBE289: + 6173 .LBE288: +3042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6174 .loc 1 3042 0 + 6175 0154 0268 ldr r2, [r0] + 6176 0156 D369 ldr r3, [r2, #28] + 6177 0158 0824 movs r4, #8 + 6178 015a 2343 orrs r3, r4 + 6179 015c D361 str r3, [r2, #28] +3045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 6180 .loc 1 3045 0 + 6181 015e 0268 ldr r2, [r0] + 6182 0160 D369 ldr r3, [r2, #28] + 6183 0162 043C subs r4, r4, #4 + 6184 0164 A343 bics r3, r4 + 6185 0166 D361 str r3, [r2, #28] +3046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6186 .loc 1 3046 0 + 6187 0168 0268 ldr r2, [r0] + 6188 016a D369 ldr r3, [r2, #28] + 6189 016c C968 ldr r1, [r1, #12] + 6190 .LVL652: + 6191 016e 0B43 orrs r3, r1 + 6192 0170 D361 str r3, [r2, #28] +3048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6193 .loc 1 3048 0 + 6194 0172 A8E7 b .L359 + 6195 .LVL653: + 6196 .L365: +2993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6197 .loc 1 2993 0 + 6198 0174 0220 movs r0, #2 + 6199 .LVL654: + 6200 0176 ADE7 b .L358 + 6201 .L368: + ARM GAS /tmp/ccH6KUTS.s page 213 + + + 6202 .align 2 + 6203 .L367: + 6204 0178 FFEFFFFF .word -4097 + 6205 017c FF8CFFFF .word -29441 + 6206 0180 FFDFFFFF .word -8193 + 6207 0184 FFFBFFFF .word -1025 + 6208 0188 FFFEFFFF .word -257 + 6209 018c FFFDFFFF .word -513 + 6210 .cfi_endproc + 6211 .LFE100: + 6213 .section .text.HAL_TIM_OnePulse_ConfigChannel,"ax",%progbits + 6214 .align 1 + 6215 .global HAL_TIM_OnePulse_ConfigChannel + 6216 .syntax unified + 6217 .code 16 + 6218 .thumb_func + 6219 .fpu softvfp + 6221 HAL_TIM_OnePulse_ConfigChannel: + 6222 .LFB101: +3092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_OC_InitTypeDef temp1; + 6223 .loc 1 3092 0 + 6224 .cfi_startproc + 6225 @ args = 0, pretend = 0, frame = 0 + 6226 @ frame_needed = 0, uses_anonymous_args = 0 + 6227 .LVL655: + 6228 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 6229 .LCFI42: + 6230 .cfi_def_cfa_offset 24 + 6231 .cfi_offset 3, -24 + 6232 .cfi_offset 4, -20 + 6233 .cfi_offset 5, -16 + 6234 .cfi_offset 6, -12 + 6235 .cfi_offset 7, -8 + 6236 .cfi_offset 14, -4 + 6237 0002 DE46 mov lr, fp + 6238 0004 5746 mov r7, r10 + 6239 0006 4E46 mov r6, r9 + 6240 0008 4546 mov r5, r8 + 6241 000a E0B5 push {r5, r6, r7, lr} + 6242 .LCFI43: + 6243 .cfi_def_cfa_offset 40 + 6244 .cfi_offset 8, -40 + 6245 .cfi_offset 9, -36 + 6246 .cfi_offset 10, -32 + 6247 .cfi_offset 11, -28 + 6248 000c 0400 movs r4, r0 +3099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6249 .loc 1 3099 0 + 6250 000e 9A42 cmp r2, r3 + 6251 0010 00D1 bne .LCB6083 + 6252 0012 B1E0 b .L377 @long jump + 6253 .LCB6083: +3101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6254 .loc 1 3101 0 + 6255 0014 3420 movs r0, #52 + 6256 .LVL656: + 6257 0016 205C ldrb r0, [r4, r0] + ARM GAS /tmp/ccH6KUTS.s page 214 + + + 6258 0018 0128 cmp r0, #1 + 6259 001a 00D1 bne .LCB6088 + 6260 001c AEE0 b .L378 @long jump + 6261 .LCB6088: +3101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6262 .loc 1 3101 0 is_stmt 0 discriminator 2 + 6263 001e 3420 movs r0, #52 + 6264 0020 0125 movs r5, #1 + 6265 0022 2554 strb r5, [r4, r0] +3103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6266 .loc 1 3103 0 is_stmt 1 discriminator 2 + 6267 0024 0130 adds r0, r0, #1 + 6268 0026 0135 adds r5, r5, #1 + 6269 0028 2554 strb r5, [r4, r0] +3106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; + 6270 .loc 1 3106 0 discriminator 2 + 6271 002a 0D68 ldr r5, [r1] +3107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; + 6272 .loc 1 3107 0 discriminator 2 + 6273 002c 4F68 ldr r7, [r1, #4] +3108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6274 .loc 1 3108 0 discriminator 2 + 6275 002e 8868 ldr r0, [r1, #8] + 6276 0030 8246 mov r10, r0 +3110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6277 .loc 1 3110 0 discriminator 2 + 6278 0032 002A cmp r2, #0 + 6279 0034 12D0 beq .L372 + 6280 0036 042A cmp r2, #4 + 6281 0038 2CD0 beq .L373 + 6282 .LVL657: + 6283 .L371: +3129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6284 .loc 1 3129 0 + 6285 003a 002B cmp r3, #0 + 6286 003c 48D0 beq .L375 + 6287 003e 042B cmp r3, #4 + 6288 0040 66D0 beq .L376 + 6289 .LVL658: + 6290 .L374: +3174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6291 .loc 1 3174 0 + 6292 0042 3523 movs r3, #53 + 6293 0044 0122 movs r2, #1 + 6294 0046 E254 strb r2, [r4, r3] +3176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6295 .loc 1 3176 0 + 6296 0048 013B subs r3, r3, #1 + 6297 004a 0022 movs r2, #0 + 6298 004c E254 strb r2, [r4, r3] +3178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6299 .loc 1 3178 0 + 6300 004e 0020 movs r0, #0 + 6301 .L370: +3184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6302 .loc 1 3184 0 + 6303 @ sp needed + ARM GAS /tmp/ccH6KUTS.s page 215 + + + 6304 .LVL659: + 6305 0050 3CBC pop {r2, r3, r4, r5} + 6306 0052 9046 mov r8, r2 + 6307 0054 9946 mov r9, r3 + 6308 0056 A246 mov r10, r4 + 6309 0058 AB46 mov fp, r5 + 6310 005a F8BD pop {r3, r4, r5, r6, r7, pc} + 6311 .LVL660: + 6312 .L372: +3116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6313 .loc 1 3116 0 + 6314 005c 2268 ldr r2, [r4] + 6315 .LVL661: + 6316 .LBB290: + 6317 .LBB291: +4430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6318 .loc 1 4430 0 + 6319 005e 166A ldr r6, [r2, #32] + 6320 0060 0120 movs r0, #1 + 6321 0062 8643 bics r6, r0 + 6322 0064 1662 str r6, [r2, #32] +4433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 6323 .loc 1 4433 0 + 6324 0066 106A ldr r0, [r2, #32] + 6325 .LVL662: + 6326 0068 8346 mov fp, r0 + 6327 .LVL663: +4435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6328 .loc 1 4435 0 + 6329 006a 5068 ldr r0, [r2, #4] + 6330 .LVL664: + 6331 006c 8046 mov r8, r0 + 6332 .LVL665: +4438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6333 .loc 1 4438 0 + 6334 006e 9069 ldr r0, [r2, #24] + 6335 .LVL666: + 6336 0070 8446 mov ip, r0 + 6337 .LVL667: +4442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the Output Compare Mode */ + 6338 .loc 1 4442 0 + 6339 0072 7320 movs r0, #115 + 6340 .LVL668: + 6341 0074 8146 mov r9, r0 + 6342 0076 6046 mov r0, ip + 6343 0078 4E46 mov r6, r9 + 6344 007a B043 bics r0, r6 + 6345 .LVL669: +4444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6346 .loc 1 4444 0 + 6347 007c 0543 orrs r5, r0 + 6348 .LVL670: +4447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6349 .loc 1 4447 0 + 6350 007e 0220 movs r0, #2 + 6351 0080 5E46 mov r6, fp + 6352 0082 8643 bics r6, r0 + ARM GAS /tmp/ccH6KUTS.s page 216 + + + 6353 .LVL671: +4449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6354 .loc 1 4449 0 + 6355 0084 5046 mov r0, r10 + 6356 0086 3043 orrs r0, r6 + 6357 .LVL672: +4452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6358 .loc 1 4452 0 + 6359 0088 4646 mov r6, r8 + 6360 008a 5660 str r6, [r2, #4] +4455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6361 .loc 1 4455 0 + 6362 008c 9561 str r5, [r2, #24] +4458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6363 .loc 1 4458 0 + 6364 008e 5763 str r7, [r2, #52] +4461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6365 .loc 1 4461 0 + 6366 0090 1062 str r0, [r2, #32] + 6367 0092 D2E7 b .L371 + 6368 .LVL673: + 6369 .L373: + 6370 .LBE291: + 6371 .LBE290: +3123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6372 .loc 1 3123 0 + 6373 0094 2268 ldr r2, [r4] + 6374 .LVL674: + 6375 .LBB292: + 6376 .LBB293: +4477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6377 .loc 1 4477 0 + 6378 0096 166A ldr r6, [r2, #32] + 6379 0098 1020 movs r0, #16 + 6380 009a 8643 bics r6, r0 + 6381 009c 1662 str r6, [r2, #32] +4480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Get the TIMx CR2 register value */ + 6382 .loc 1 4480 0 + 6383 009e 106A ldr r0, [r2, #32] + 6384 .LVL675: + 6385 00a0 8346 mov fp, r0 + 6386 .LVL676: +4482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6387 .loc 1 4482 0 + 6388 00a2 5068 ldr r0, [r2, #4] + 6389 .LVL677: + 6390 00a4 8446 mov ip, r0 + 6391 .LVL678: +4485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6392 .loc 1 4485 0 + 6393 00a6 9069 ldr r0, [r2, #24] + 6394 .LVL679: + 6395 00a8 8046 mov r8, r0 + 6396 .LVL680: +4489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6397 .loc 1 4489 0 + 6398 00aa 3548 ldr r0, .L379 + ARM GAS /tmp/ccH6KUTS.s page 217 + + + 6399 .LVL681: + 6400 00ac 8146 mov r9, r0 + 6401 00ae 4046 mov r0, r8 + 6402 00b0 4E46 mov r6, r9 + 6403 00b2 3040 ands r0, r6 + 6404 .LVL682: +4492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6405 .loc 1 4492 0 + 6406 00b4 2D02 lsls r5, r5, #8 + 6407 00b6 0543 orrs r5, r0 + 6408 .LVL683: +4495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6409 .loc 1 4495 0 + 6410 00b8 2020 movs r0, #32 + 6411 00ba 5E46 mov r6, fp + 6412 00bc 8643 bics r6, r0 + 6413 .LVL684: +4497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6414 .loc 1 4497 0 + 6415 00be 5046 mov r0, r10 + 6416 00c0 0001 lsls r0, r0, #4 + 6417 00c2 3043 orrs r0, r6 + 6418 .LVL685: +4500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6419 .loc 1 4500 0 + 6420 00c4 6646 mov r6, ip + 6421 00c6 5660 str r6, [r2, #4] +4503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6422 .loc 1 4503 0 + 6423 00c8 9561 str r5, [r2, #24] +4506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6424 .loc 1 4506 0 + 6425 00ca 9763 str r7, [r2, #56] +4509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6426 .loc 1 4509 0 + 6427 00cc 1062 str r0, [r2, #32] + 6428 00ce B4E7 b .L371 + 6429 .LVL686: + 6430 .L375: + 6431 .LBE293: + 6432 .LBE292: +3135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); + 6433 .loc 1 3135 0 + 6434 00d0 4B69 ldr r3, [r1, #20] + 6435 .LVL687: + 6436 00d2 0A69 ldr r2, [r1, #16] + 6437 00d4 C968 ldr r1, [r1, #12] + 6438 .LVL688: + 6439 00d6 2068 ldr r0, [r4] + 6440 00d8 FFF7FEFF bl TIM_TI1_SetConfig + 6441 .LVL689: +3139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6442 .loc 1 3139 0 + 6443 00dc 2268 ldr r2, [r4] + 6444 00de 9369 ldr r3, [r2, #24] + 6445 00e0 0C21 movs r1, #12 + 6446 00e2 8B43 bics r3, r1 + ARM GAS /tmp/ccH6KUTS.s page 218 + + + 6447 00e4 9361 str r3, [r2, #24] +3142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 6448 .loc 1 3142 0 + 6449 00e6 2268 ldr r2, [r4] + 6450 00e8 9368 ldr r3, [r2, #8] + 6451 00ea 6431 adds r1, r1, #100 + 6452 00ec 8B43 bics r3, r1 + 6453 00ee 9360 str r3, [r2, #8] +3143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6454 .loc 1 3143 0 + 6455 00f0 2268 ldr r2, [r4] + 6456 00f2 9368 ldr r3, [r2, #8] + 6457 00f4 2039 subs r1, r1, #32 + 6458 00f6 0B43 orrs r3, r1 + 6459 00f8 9360 str r3, [r2, #8] +3146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 6460 .loc 1 3146 0 + 6461 00fa 2268 ldr r2, [r4] + 6462 00fc 9368 ldr r3, [r2, #8] + 6463 00fe 4939 subs r1, r1, #73 + 6464 0100 8B43 bics r3, r1 + 6465 0102 9360 str r3, [r2, #8] +3147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6466 .loc 1 3147 0 + 6467 0104 2268 ldr r2, [r4] + 6468 0106 9368 ldr r3, [r2, #8] + 6469 0108 0139 subs r1, r1, #1 + 6470 010a 0B43 orrs r3, r1 + 6471 010c 9360 str r3, [r2, #8] +3149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_CHANNEL_2: + 6472 .loc 1 3149 0 + 6473 010e 98E7 b .L374 + 6474 .LVL690: + 6475 .L376: +3154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); + 6476 .loc 1 3154 0 + 6477 0110 2268 ldr r2, [r4] + 6478 0112 CD68 ldr r5, [r1, #12] + 6479 0114 0E69 ldr r6, [r1, #16] + 6480 0116 4869 ldr r0, [r1, #20] + 6481 .LVL691: + 6482 .LBB294: + 6483 .LBB295: +4719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 6484 .loc 1 4719 0 + 6485 0118 136A ldr r3, [r2, #32] + 6486 .LVL692: + 6487 011a 1021 movs r1, #16 + 6488 .LVL693: + 6489 011c 8B43 bics r3, r1 + 6490 011e 1362 str r3, [r2, #32] +4720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 6491 .loc 1 4720 0 + 6492 0120 9369 ldr r3, [r2, #24] + 6493 .LVL694: +4721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6494 .loc 1 4721 0 + ARM GAS /tmp/ccH6KUTS.s page 219 + + + 6495 0122 116A ldr r1, [r2, #32] + 6496 .LVL695: +4724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICSelection << 8U); + 6497 .loc 1 4724 0 + 6498 0124 174F ldr r7, .L379+4 + 6499 0126 3B40 ands r3, r7 + 6500 .LVL696: +4725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6501 .loc 1 4725 0 + 6502 0128 3602 lsls r6, r6, #8 + 6503 .LVL697: + 6504 012a 3343 orrs r3, r6 + 6505 .LVL698: +4728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + 6506 .loc 1 4728 0 + 6507 012c 164E ldr r6, .L379+8 + 6508 012e 3340 ands r3, r6 + 6509 .LVL699: +4729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6510 .loc 1 4729 0 + 6511 0130 0007 lsls r0, r0, #28 + 6512 .LVL700: + 6513 0132 000C lsrs r0, r0, #16 + 6514 0134 0343 orrs r3, r0 + 6515 .LVL701: +4732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + 6516 .loc 1 4732 0 + 6517 0136 A020 movs r0, #160 + 6518 0138 8143 bics r1, r0 + 6519 .LVL702: +4733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6520 .loc 1 4733 0 + 6521 013a 2D01 lsls r5, r5, #4 + 6522 .LVL703: + 6523 013c 2840 ands r0, r5 + 6524 013e 0143 orrs r1, r0 + 6525 .LVL704: +4736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 6526 .loc 1 4736 0 + 6527 0140 9361 str r3, [r2, #24] +4737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6528 .loc 1 4737 0 + 6529 0142 1162 str r1, [r2, #32] + 6530 .LVL705: + 6531 .LBE295: + 6532 .LBE294: +3158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6533 .loc 1 3158 0 + 6534 0144 2268 ldr r2, [r4] + 6535 0146 9369 ldr r3, [r2, #24] + 6536 0148 1049 ldr r1, .L379+12 + 6537 014a 0B40 ands r3, r1 + 6538 014c 9361 str r3, [r2, #24] +3161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 6539 .loc 1 3161 0 + 6540 014e 2268 ldr r2, [r4] + 6541 0150 9368 ldr r3, [r2, #8] + ARM GAS /tmp/ccH6KUTS.s page 220 + + + 6542 0152 7021 movs r1, #112 + 6543 0154 8B43 bics r3, r1 + 6544 0156 9360 str r3, [r2, #8] +3162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6545 .loc 1 3162 0 + 6546 0158 2268 ldr r2, [r4] + 6547 015a 9368 ldr r3, [r2, #8] + 6548 015c 1039 subs r1, r1, #16 + 6549 015e 0B43 orrs r3, r1 + 6550 0160 9360 str r3, [r2, #8] +3165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 6551 .loc 1 3165 0 + 6552 0162 2268 ldr r2, [r4] + 6553 0164 9368 ldr r3, [r2, #8] + 6554 0166 5939 subs r1, r1, #89 + 6555 0168 8B43 bics r3, r1 + 6556 016a 9360 str r3, [r2, #8] +3166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6557 .loc 1 3166 0 + 6558 016c 2268 ldr r2, [r4] + 6559 016e 9368 ldr r3, [r2, #8] + 6560 0170 0139 subs r1, r1, #1 + 6561 0172 0B43 orrs r3, r1 + 6562 0174 9360 str r3, [r2, #8] +3168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6563 .loc 1 3168 0 + 6564 0176 64E7 b .L374 + 6565 .LVL706: + 6566 .L377: +3182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6567 .loc 1 3182 0 + 6568 0178 0120 movs r0, #1 + 6569 .LVL707: + 6570 017a 69E7 b .L370 + 6571 .L378: +3101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6572 .loc 1 3101 0 + 6573 017c 0220 movs r0, #2 + 6574 017e 67E7 b .L370 + 6575 .L380: + 6576 .align 2 + 6577 .L379: + 6578 0180 FF8CFFFF .word -29441 + 6579 0184 FFFCFFFF .word -769 + 6580 0188 FF0FFFFF .word -61441 + 6581 018c FFF3FFFF .word -3073 + 6582 .cfi_endproc + 6583 .LFE101: + 6585 .section .text.HAL_TIM_DMABurst_WriteStart,"ax",%progbits + 6586 .align 1 + 6587 .global HAL_TIM_DMABurst_WriteStart + 6588 .syntax unified + 6589 .code 16 + 6590 .thumb_func + 6591 .fpu softvfp + 6593 HAL_TIM_DMABurst_WriteStart: + 6594 .LFB102: + ARM GAS /tmp/ccH6KUTS.s page 221 + + +3223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 6595 .loc 1 3223 0 + 6596 .cfi_startproc + 6597 @ args = 4, pretend = 0, frame = 0 + 6598 @ frame_needed = 0, uses_anonymous_args = 0 + 6599 .LVL708: + 6600 0000 70B5 push {r4, r5, r6, lr} + 6601 .LCFI44: + 6602 .cfi_def_cfa_offset 16 + 6603 .cfi_offset 4, -16 + 6604 .cfi_offset 5, -12 + 6605 .cfi_offset 6, -8 + 6606 .cfi_offset 14, -4 + 6607 0002 0400 movs r4, r0 + 6608 0004 0E00 movs r6, r1 + 6609 0006 1500 movs r5, r2 + 6610 0008 1900 movs r1, r3 + 6611 .LVL709: +3230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6612 .loc 1 3230 0 + 6613 000a 3523 movs r3, #53 + 6614 .LVL710: + 6615 000c C35C ldrb r3, [r0, r3] + 6616 000e 022B cmp r3, #2 + 6617 0010 00D1 bne .LCB6448 + 6618 0012 8EE0 b .L393 @long jump + 6619 .LCB6448: +3234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6620 .loc 1 3234 0 + 6621 0014 3523 movs r3, #53 + 6622 0016 C35C ldrb r3, [r0, r3] + 6623 0018 012B cmp r3, #1 + 6624 001a 20D0 beq .L395 + 6625 .LVL711: + 6626 .L383: +3245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6627 .loc 1 3245 0 + 6628 001c 8023 movs r3, #128 + 6629 001e DB00 lsls r3, r3, #3 + 6630 0020 9D42 cmp r5, r3 + 6631 0022 59D0 beq .L386 + 6632 0024 26D9 bls .L396 + 6633 0026 8023 movs r3, #128 + 6634 0028 5B01 lsls r3, r3, #5 + 6635 002a 9D42 cmp r5, r3 + 6636 002c 63D0 beq .L390 + 6637 002e 8023 movs r3, #128 + 6638 0030 DB01 lsls r3, r3, #7 + 6639 0032 9D42 cmp r5, r3 + 6640 0034 00D1 bne .LCB6469 + 6641 0036 6DE0 b .L391 @long jump + 6642 .LCB6469: + 6643 0038 8023 movs r3, #128 + 6644 003a 1B01 lsls r3, r3, #4 + 6645 003c 9D42 cmp r5, r3 + 6646 003e 3ED1 bne .L385 +3286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 222 + + + 6647 .loc 1 3286 0 + 6648 0040 636A ldr r3, [r4, #36] + 6649 0042 3D4A ldr r2, .L398 + 6650 0044 DA62 str r2, [r3, #44] +3289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6651 .loc 1 3289 0 + 6652 0046 636A ldr r3, [r4, #36] + 6653 0048 3C4A ldr r2, .L398+4 + 6654 004a 5A63 str r2, [r3, #52] +3292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6655 .loc 1 3292 0 + 6656 004c 2268 ldr r2, [r4] + 6657 004e 4C32 adds r2, r2, #76 + 6658 0050 049B ldr r3, [sp, #16] + 6659 0052 1B0A lsrs r3, r3, #8 + 6660 0054 0133 adds r3, r3, #1 + 6661 0056 606A ldr r0, [r4, #36] + 6662 .LVL712: + 6663 0058 FFF7FEFF bl HAL_DMA_Start_IT + 6664 .LVL713: +3294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: + 6665 .loc 1 3294 0 + 6666 005c 2FE0 b .L385 + 6667 .LVL714: + 6668 .L395: +3236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6669 .loc 1 3236 0 + 6670 005e 0029 cmp r1, #0 + 6671 0060 03D0 beq .L397 + 6672 .L384: +3242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6673 .loc 1 3242 0 + 6674 0062 3523 movs r3, #53 + 6675 0064 0222 movs r2, #2 + 6676 .LVL715: + 6677 0066 E254 strb r2, [r4, r3] + 6678 0068 D8E7 b .L383 + 6679 .LVL716: + 6680 .L397: +3236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6681 .loc 1 3236 0 discriminator 1 + 6682 006a 049B ldr r3, [sp, #16] + 6683 006c 002B cmp r3, #0 + 6684 006e F8D0 beq .L384 +3238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6685 .loc 1 3238 0 + 6686 0070 0120 movs r0, #1 + 6687 .LVL717: + 6688 0072 30E0 b .L382 + 6689 .LVL718: + 6690 .L396: +3245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6691 .loc 1 3245 0 + 6692 0074 8023 movs r3, #128 + 6693 0076 5B00 lsls r3, r3, #1 + 6694 0078 9D42 cmp r5, r3 + 6695 007a 12D0 beq .L388 + ARM GAS /tmp/ccH6KUTS.s page 223 + + + 6696 007c 0133 adds r3, r3, #1 + 6697 007e FF33 adds r3, r3, #255 + 6698 0080 9D42 cmp r5, r3 + 6699 0082 1CD1 bne .L385 +3262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6700 .loc 1 3262 0 + 6701 0084 E369 ldr r3, [r4, #28] + 6702 0086 2C4A ldr r2, .L398 + 6703 0088 DA62 str r2, [r3, #44] +3265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6704 .loc 1 3265 0 + 6705 008a E369 ldr r3, [r4, #28] + 6706 008c 2B4A ldr r2, .L398+4 + 6707 008e 5A63 str r2, [r3, #52] +3268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6708 .loc 1 3268 0 + 6709 0090 2268 ldr r2, [r4] + 6710 0092 4C32 adds r2, r2, #76 + 6711 0094 049B ldr r3, [sp, #16] + 6712 0096 1B0A lsrs r3, r3, #8 + 6713 0098 0133 adds r3, r3, #1 + 6714 009a E069 ldr r0, [r4, #28] + 6715 .LVL719: + 6716 009c FFF7FEFF bl HAL_DMA_Start_IT + 6717 .LVL720: +3270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: + 6718 .loc 1 3270 0 + 6719 00a0 0DE0 b .L385 + 6720 .LVL721: + 6721 .L388: +3250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6722 .loc 1 3250 0 + 6723 00a2 A369 ldr r3, [r4, #24] + 6724 00a4 264A ldr r2, .L398+8 + 6725 00a6 DA62 str r2, [r3, #44] +3253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6726 .loc 1 3253 0 + 6727 00a8 A369 ldr r3, [r4, #24] + 6728 00aa 244A ldr r2, .L398+4 + 6729 00ac 5A63 str r2, [r3, #52] +3256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6730 .loc 1 3256 0 + 6731 00ae 2268 ldr r2, [r4] + 6732 00b0 4C32 adds r2, r2, #76 + 6733 00b2 049B ldr r3, [sp, #16] + 6734 00b4 1B0A lsrs r3, r3, #8 + 6735 00b6 0133 adds r3, r3, #1 + 6736 00b8 A069 ldr r0, [r4, #24] + 6737 .LVL722: + 6738 00ba FFF7FEFF bl HAL_DMA_Start_IT + 6739 .LVL723: + 6740 .L385: +3323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6741 .loc 1 3323 0 + 6742 00be 2368 ldr r3, [r4] + 6743 00c0 049A ldr r2, [sp, #16] + 6744 00c2 1643 orrs r6, r2 + ARM GAS /tmp/ccH6KUTS.s page 224 + + + 6745 .LVL724: + 6746 00c4 9E64 str r6, [r3, #72] +3326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6747 .loc 1 3326 0 + 6748 00c6 2268 ldr r2, [r4] + 6749 00c8 D368 ldr r3, [r2, #12] + 6750 00ca 1D43 orrs r5, r3 + 6751 .LVL725: + 6752 00cc D560 str r5, [r2, #12] +3328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6753 .loc 1 3328 0 + 6754 00ce 3523 movs r3, #53 + 6755 00d0 0122 movs r2, #1 + 6756 00d2 E254 strb r2, [r4, r3] +3331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6757 .loc 1 3331 0 + 6758 00d4 0020 movs r0, #0 + 6759 .L382: +3332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6760 .loc 1 3332 0 + 6761 @ sp needed + 6762 .LVL726: + 6763 00d6 70BD pop {r4, r5, r6, pc} + 6764 .LVL727: + 6765 .L386: +3274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6766 .loc 1 3274 0 + 6767 00d8 236A ldr r3, [r4, #32] + 6768 00da 174A ldr r2, .L398 + 6769 00dc DA62 str r2, [r3, #44] +3277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6770 .loc 1 3277 0 + 6771 00de 236A ldr r3, [r4, #32] + 6772 00e0 164A ldr r2, .L398+4 + 6773 00e2 5A63 str r2, [r3, #52] +3280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6774 .loc 1 3280 0 + 6775 00e4 2268 ldr r2, [r4] + 6776 00e6 4C32 adds r2, r2, #76 + 6777 00e8 049B ldr r3, [sp, #16] + 6778 00ea 1B0A lsrs r3, r3, #8 + 6779 00ec 0133 adds r3, r3, #1 + 6780 00ee 206A ldr r0, [r4, #32] + 6781 .LVL728: + 6782 00f0 FFF7FEFF bl HAL_DMA_Start_IT + 6783 .LVL729: +3282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: + 6784 .loc 1 3282 0 + 6785 00f4 E3E7 b .L385 + 6786 .LVL730: + 6787 .L390: +3298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6788 .loc 1 3298 0 + 6789 00f6 A36A ldr r3, [r4, #40] + 6790 00f8 0F4A ldr r2, .L398 + 6791 00fa DA62 str r2, [r3, #44] +3301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 225 + + + 6792 .loc 1 3301 0 + 6793 00fc A36A ldr r3, [r4, #40] + 6794 00fe 0F4A ldr r2, .L398+4 + 6795 0100 5A63 str r2, [r3, #52] +3304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6796 .loc 1 3304 0 + 6797 0102 2268 ldr r2, [r4] + 6798 0104 4C32 adds r2, r2, #76 + 6799 0106 049B ldr r3, [sp, #16] + 6800 0108 1B0A lsrs r3, r3, #8 + 6801 010a 0133 adds r3, r3, #1 + 6802 010c A06A ldr r0, [r4, #40] + 6803 .LVL731: + 6804 010e FFF7FEFF bl HAL_DMA_Start_IT + 6805 .LVL732: +3306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: + 6806 .loc 1 3306 0 + 6807 0112 D4E7 b .L385 + 6808 .LVL733: + 6809 .L391: +3310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6810 .loc 1 3310 0 + 6811 0114 E36A ldr r3, [r4, #44] + 6812 0116 0B4A ldr r2, .L398+12 + 6813 0118 DA62 str r2, [r3, #44] +3313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6814 .loc 1 3313 0 + 6815 011a E36A ldr r3, [r4, #44] + 6816 011c 074A ldr r2, .L398+4 + 6817 011e 5A63 str r2, [r3, #52] +3316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6818 .loc 1 3316 0 + 6819 0120 2268 ldr r2, [r4] + 6820 0122 4C32 adds r2, r2, #76 + 6821 0124 049B ldr r3, [sp, #16] + 6822 0126 1B0A lsrs r3, r3, #8 + 6823 0128 0133 adds r3, r3, #1 + 6824 012a E06A ldr r0, [r4, #44] + 6825 .LVL734: + 6826 012c FFF7FEFF bl HAL_DMA_Start_IT + 6827 .LVL735: +3318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 6828 .loc 1 3318 0 + 6829 0130 C5E7 b .L385 + 6830 .LVL736: + 6831 .L393: +3232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6832 .loc 1 3232 0 + 6833 0132 0220 movs r0, #2 + 6834 .LVL737: + 6835 0134 CFE7 b .L382 + 6836 .L399: + 6837 0136 C046 .align 2 + 6838 .L398: + 6839 0138 00000000 .word TIM_DMADelayPulseCplt + 6840 013c 00000000 .word TIM_DMAError + 6841 0140 00000000 .word TIM_DMAPeriodElapsedCplt + ARM GAS /tmp/ccH6KUTS.s page 226 + + + 6842 0144 00000000 .word TIM_DMATriggerCplt + 6843 .cfi_endproc + 6844 .LFE102: + 6846 .section .text.HAL_TIM_DMABurst_WriteStop,"ax",%progbits + 6847 .align 1 + 6848 .global HAL_TIM_DMABurst_WriteStop + 6849 .syntax unified + 6850 .code 16 + 6851 .thumb_func + 6852 .fpu softvfp + 6854 HAL_TIM_DMABurst_WriteStop: + 6855 .LFB103: +3341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 6856 .loc 1 3341 0 + 6857 .cfi_startproc + 6858 @ args = 0, pretend = 0, frame = 0 + 6859 @ frame_needed = 0, uses_anonymous_args = 0 + 6860 .LVL738: + 6861 0000 70B5 push {r4, r5, r6, lr} + 6862 .LCFI45: + 6863 .cfi_def_cfa_offset 16 + 6864 .cfi_offset 4, -16 + 6865 .cfi_offset 5, -12 + 6866 .cfi_offset 6, -8 + 6867 .cfi_offset 14, -4 + 6868 0002 0500 movs r5, r0 + 6869 0004 0C00 movs r4, r1 +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6870 .loc 1 3346 0 + 6871 0006 8023 movs r3, #128 + 6872 0008 DB00 lsls r3, r3, #3 + 6873 000a 9942 cmp r1, r3 + 6874 000c 25D0 beq .L402 + 6875 000e 0FD9 bls .L409 + 6876 0010 8023 movs r3, #128 + 6877 0012 5B01 lsls r3, r3, #5 + 6878 0014 9942 cmp r1, r3 + 6879 0016 24D0 beq .L406 + 6880 0018 8023 movs r3, #128 + 6881 001a DB01 lsls r3, r3, #7 + 6882 001c 9942 cmp r1, r3 + 6883 001e 24D0 beq .L407 + 6884 0020 8023 movs r3, #128 + 6885 0022 1B01 lsls r3, r3, #4 + 6886 0024 9942 cmp r1, r3 + 6887 0026 12D1 bne .L401 +3365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6888 .loc 1 3365 0 + 6889 0028 406A ldr r0, [r0, #36] + 6890 .LVL739: + 6891 002a FFF7FEFF bl HAL_DMA_Abort + 6892 .LVL740: +3367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: + 6893 .loc 1 3367 0 + 6894 002e 0EE0 b .L401 + 6895 .LVL741: + 6896 .L409: + ARM GAS /tmp/ccH6KUTS.s page 227 + + +3346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6897 .loc 1 3346 0 + 6898 0030 8023 movs r3, #128 + 6899 0032 5B00 lsls r3, r3, #1 + 6900 0034 9942 cmp r1, r3 + 6901 0036 07D0 beq .L404 + 6902 0038 0133 adds r3, r3, #1 + 6903 003a FF33 adds r3, r3, #255 + 6904 003c 9942 cmp r1, r3 + 6905 003e 06D1 bne .L401 +3355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6906 .loc 1 3355 0 + 6907 0040 C069 ldr r0, [r0, #28] + 6908 .LVL742: + 6909 0042 FFF7FEFF bl HAL_DMA_Abort + 6910 .LVL743: +3357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: + 6911 .loc 1 3357 0 + 6912 0046 02E0 b .L401 + 6913 .LVL744: + 6914 .L404: +3350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6915 .loc 1 3350 0 + 6916 0048 8069 ldr r0, [r0, #24] + 6917 .LVL745: + 6918 004a FFF7FEFF bl HAL_DMA_Abort + 6919 .LVL746: + 6920 .L401: +3382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6921 .loc 1 3382 0 + 6922 004e 2A68 ldr r2, [r5] + 6923 0050 D368 ldr r3, [r2, #12] + 6924 0052 A343 bics r3, r4 + 6925 0054 D360 str r3, [r2, #12] +3386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 6926 .loc 1 3386 0 + 6927 0056 0020 movs r0, #0 + 6928 @ sp needed + 6929 .LVL747: + 6930 .LVL748: + 6931 0058 70BD pop {r4, r5, r6, pc} + 6932 .LVL749: + 6933 .L402: +3360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6934 .loc 1 3360 0 + 6935 005a 006A ldr r0, [r0, #32] + 6936 .LVL750: + 6937 005c FFF7FEFF bl HAL_DMA_Abort + 6938 .LVL751: +3362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: + 6939 .loc 1 3362 0 + 6940 0060 F5E7 b .L401 + 6941 .LVL752: + 6942 .L406: +3370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6943 .loc 1 3370 0 + 6944 0062 806A ldr r0, [r0, #40] + ARM GAS /tmp/ccH6KUTS.s page 228 + + + 6945 .LVL753: + 6946 0064 FFF7FEFF bl HAL_DMA_Abort + 6947 .LVL754: +3372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: + 6948 .loc 1 3372 0 + 6949 0068 F1E7 b .L401 + 6950 .LVL755: + 6951 .L407: +3375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 6952 .loc 1 3375 0 + 6953 006a C06A ldr r0, [r0, #44] + 6954 .LVL756: + 6955 006c FFF7FEFF bl HAL_DMA_Abort + 6956 .LVL757: +3377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 6957 .loc 1 3377 0 + 6958 0070 EDE7 b .L401 + 6959 .cfi_endproc + 6960 .LFE103: + 6962 .section .text.HAL_TIM_DMABurst_ReadStart,"ax",%progbits + 6963 .align 1 + 6964 .global HAL_TIM_DMABurst_ReadStart + 6965 .syntax unified + 6966 .code 16 + 6967 .thumb_func + 6968 .fpu softvfp + 6970 HAL_TIM_DMABurst_ReadStart: + 6971 .LFB104: +3425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 6972 .loc 1 3425 0 + 6973 .cfi_startproc + 6974 @ args = 4, pretend = 0, frame = 0 + 6975 @ frame_needed = 0, uses_anonymous_args = 0 + 6976 .LVL758: + 6977 0000 70B5 push {r4, r5, r6, lr} + 6978 .LCFI46: + 6979 .cfi_def_cfa_offset 16 + 6980 .cfi_offset 4, -16 + 6981 .cfi_offset 5, -12 + 6982 .cfi_offset 6, -8 + 6983 .cfi_offset 14, -4 + 6984 0002 0400 movs r4, r0 + 6985 0004 0E00 movs r6, r1 + 6986 0006 1500 movs r5, r2 + 6987 0008 1A00 movs r2, r3 + 6988 .LVL759: +3432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6989 .loc 1 3432 0 + 6990 000a 3523 movs r3, #53 + 6991 .LVL760: + 6992 000c C35C ldrb r3, [r0, r3] + 6993 000e 022B cmp r3, #2 + 6994 0010 00D1 bne .LCB6856 + 6995 0012 8EE0 b .L422 @long jump + 6996 .LCB6856: +3436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 6997 .loc 1 3436 0 + ARM GAS /tmp/ccH6KUTS.s page 229 + + + 6998 0014 3523 movs r3, #53 + 6999 0016 C35C ldrb r3, [r0, r3] + 7000 0018 012B cmp r3, #1 + 7001 001a 20D0 beq .L424 + 7002 .LVL761: + 7003 .L412: +3447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7004 .loc 1 3447 0 + 7005 001c 8023 movs r3, #128 + 7006 001e DB00 lsls r3, r3, #3 + 7007 0020 9D42 cmp r5, r3 + 7008 0022 59D0 beq .L415 + 7009 0024 26D9 bls .L425 + 7010 0026 8023 movs r3, #128 + 7011 0028 5B01 lsls r3, r3, #5 + 7012 002a 9D42 cmp r5, r3 + 7013 002c 63D0 beq .L419 + 7014 002e 8023 movs r3, #128 + 7015 0030 DB01 lsls r3, r3, #7 + 7016 0032 9D42 cmp r5, r3 + 7017 0034 00D1 bne .LCB6877 + 7018 0036 6DE0 b .L420 @long jump + 7019 .LCB6877: + 7020 0038 8023 movs r3, #128 + 7021 003a 1B01 lsls r3, r3, #4 + 7022 003c 9D42 cmp r5, r3 + 7023 003e 3ED1 bne .L414 +3488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7024 .loc 1 3488 0 + 7025 0040 636A ldr r3, [r4, #36] + 7026 0042 3D49 ldr r1, .L427 + 7027 0044 D962 str r1, [r3, #44] +3491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7028 .loc 1 3491 0 + 7029 0046 636A ldr r3, [r4, #36] + 7030 0048 3C49 ldr r1, .L427+4 + 7031 004a 5963 str r1, [r3, #52] +3494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7032 .loc 1 3494 0 + 7033 004c 2168 ldr r1, [r4] + 7034 004e 4C31 adds r1, r1, #76 + 7035 0050 049B ldr r3, [sp, #16] + 7036 0052 1B0A lsrs r3, r3, #8 + 7037 0054 0133 adds r3, r3, #1 + 7038 0056 606A ldr r0, [r4, #36] + 7039 .LVL762: + 7040 0058 FFF7FEFF bl HAL_DMA_Start_IT + 7041 .LVL763: +3496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: + 7042 .loc 1 3496 0 + 7043 005c 2FE0 b .L414 + 7044 .LVL764: + 7045 .L424: +3438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7046 .loc 1 3438 0 + 7047 005e 002A cmp r2, #0 + 7048 0060 03D0 beq .L426 + ARM GAS /tmp/ccH6KUTS.s page 230 + + + 7049 .L413: +3444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7050 .loc 1 3444 0 + 7051 0062 3523 movs r3, #53 + 7052 0064 0221 movs r1, #2 + 7053 .LVL765: + 7054 0066 E154 strb r1, [r4, r3] + 7055 0068 D8E7 b .L412 + 7056 .LVL766: + 7057 .L426: +3438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7058 .loc 1 3438 0 discriminator 1 + 7059 006a 049B ldr r3, [sp, #16] + 7060 006c 002B cmp r3, #0 + 7061 006e F8D0 beq .L413 +3440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7062 .loc 1 3440 0 + 7063 0070 0120 movs r0, #1 + 7064 .LVL767: + 7065 0072 30E0 b .L411 + 7066 .LVL768: + 7067 .L425: +3447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7068 .loc 1 3447 0 + 7069 0074 8023 movs r3, #128 + 7070 0076 5B00 lsls r3, r3, #1 + 7071 0078 9D42 cmp r5, r3 + 7072 007a 12D0 beq .L417 + 7073 007c 0133 adds r3, r3, #1 + 7074 007e FF33 adds r3, r3, #255 + 7075 0080 9D42 cmp r5, r3 + 7076 0082 1CD1 bne .L414 +3464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7077 .loc 1 3464 0 + 7078 0084 E369 ldr r3, [r4, #28] + 7079 0086 2C49 ldr r1, .L427 + 7080 0088 D962 str r1, [r3, #44] +3467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7081 .loc 1 3467 0 + 7082 008a E369 ldr r3, [r4, #28] + 7083 008c 2B49 ldr r1, .L427+4 + 7084 008e 5963 str r1, [r3, #52] +3470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7085 .loc 1 3470 0 + 7086 0090 2168 ldr r1, [r4] + 7087 0092 4C31 adds r1, r1, #76 + 7088 0094 049B ldr r3, [sp, #16] + 7089 0096 1B0A lsrs r3, r3, #8 + 7090 0098 0133 adds r3, r3, #1 + 7091 009a E069 ldr r0, [r4, #28] + 7092 .LVL769: + 7093 009c FFF7FEFF bl HAL_DMA_Start_IT + 7094 .LVL770: +3472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: + 7095 .loc 1 3472 0 + 7096 00a0 0DE0 b .L414 + 7097 .LVL771: + ARM GAS /tmp/ccH6KUTS.s page 231 + + + 7098 .L417: +3452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7099 .loc 1 3452 0 + 7100 00a2 A369 ldr r3, [r4, #24] + 7101 00a4 2649 ldr r1, .L427+8 + 7102 00a6 D962 str r1, [r3, #44] +3455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7103 .loc 1 3455 0 + 7104 00a8 A369 ldr r3, [r4, #24] + 7105 00aa 2449 ldr r1, .L427+4 + 7106 00ac 5963 str r1, [r3, #52] +3458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7107 .loc 1 3458 0 + 7108 00ae 2168 ldr r1, [r4] + 7109 00b0 4C31 adds r1, r1, #76 + 7110 00b2 049B ldr r3, [sp, #16] + 7111 00b4 1B0A lsrs r3, r3, #8 + 7112 00b6 0133 adds r3, r3, #1 + 7113 00b8 A069 ldr r0, [r4, #24] + 7114 .LVL772: + 7115 00ba FFF7FEFF bl HAL_DMA_Start_IT + 7116 .LVL773: + 7117 .L414: +3526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7118 .loc 1 3526 0 + 7119 00be 2368 ldr r3, [r4] + 7120 00c0 049A ldr r2, [sp, #16] + 7121 00c2 1643 orrs r6, r2 + 7122 .LVL774: + 7123 00c4 9E64 str r6, [r3, #72] +3529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7124 .loc 1 3529 0 + 7125 00c6 2268 ldr r2, [r4] + 7126 00c8 D368 ldr r3, [r2, #12] + 7127 00ca 1D43 orrs r5, r3 + 7128 .LVL775: + 7129 00cc D560 str r5, [r2, #12] +3531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7130 .loc 1 3531 0 + 7131 00ce 3523 movs r3, #53 + 7132 00d0 0122 movs r2, #1 + 7133 00d2 E254 strb r2, [r4, r3] +3534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7134 .loc 1 3534 0 + 7135 00d4 0020 movs r0, #0 + 7136 .L411: +3535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7137 .loc 1 3535 0 + 7138 @ sp needed + 7139 .LVL776: + 7140 00d6 70BD pop {r4, r5, r6, pc} + 7141 .LVL777: + 7142 .L415: +3476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7143 .loc 1 3476 0 + 7144 00d8 236A ldr r3, [r4, #32] + 7145 00da 1749 ldr r1, .L427 + ARM GAS /tmp/ccH6KUTS.s page 232 + + + 7146 00dc D962 str r1, [r3, #44] +3479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7147 .loc 1 3479 0 + 7148 00de 236A ldr r3, [r4, #32] + 7149 00e0 1649 ldr r1, .L427+4 + 7150 00e2 5963 str r1, [r3, #52] +3482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7151 .loc 1 3482 0 + 7152 00e4 2168 ldr r1, [r4] + 7153 00e6 4C31 adds r1, r1, #76 + 7154 00e8 049B ldr r3, [sp, #16] + 7155 00ea 1B0A lsrs r3, r3, #8 + 7156 00ec 0133 adds r3, r3, #1 + 7157 00ee 206A ldr r0, [r4, #32] + 7158 .LVL778: + 7159 00f0 FFF7FEFF bl HAL_DMA_Start_IT + 7160 .LVL779: +3484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: + 7161 .loc 1 3484 0 + 7162 00f4 E3E7 b .L414 + 7163 .LVL780: + 7164 .L419: +3500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7165 .loc 1 3500 0 + 7166 00f6 A36A ldr r3, [r4, #40] + 7167 00f8 0F49 ldr r1, .L427 + 7168 00fa D962 str r1, [r3, #44] +3503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7169 .loc 1 3503 0 + 7170 00fc A36A ldr r3, [r4, #40] + 7171 00fe 0F49 ldr r1, .L427+4 + 7172 0100 5963 str r1, [r3, #52] +3506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7173 .loc 1 3506 0 + 7174 0102 2168 ldr r1, [r4] + 7175 0104 4C31 adds r1, r1, #76 + 7176 0106 049B ldr r3, [sp, #16] + 7177 0108 1B0A lsrs r3, r3, #8 + 7178 010a 0133 adds r3, r3, #1 + 7179 010c A06A ldr r0, [r4, #40] + 7180 .LVL781: + 7181 010e FFF7FEFF bl HAL_DMA_Start_IT + 7182 .LVL782: +3508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: + 7183 .loc 1 3508 0 + 7184 0112 D4E7 b .L414 + 7185 .LVL783: + 7186 .L420: +3512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7187 .loc 1 3512 0 + 7188 0114 E36A ldr r3, [r4, #44] + 7189 0116 0B49 ldr r1, .L427+12 + 7190 0118 D962 str r1, [r3, #44] +3515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7191 .loc 1 3515 0 + 7192 011a E36A ldr r3, [r4, #44] + 7193 011c 0749 ldr r1, .L427+4 + ARM GAS /tmp/ccH6KUTS.s page 233 + + + 7194 011e 5963 str r1, [r3, #52] +3518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7195 .loc 1 3518 0 + 7196 0120 2168 ldr r1, [r4] + 7197 0122 4C31 adds r1, r1, #76 + 7198 0124 049B ldr r3, [sp, #16] + 7199 0126 1B0A lsrs r3, r3, #8 + 7200 0128 0133 adds r3, r3, #1 + 7201 012a E06A ldr r0, [r4, #44] + 7202 .LVL784: + 7203 012c FFF7FEFF bl HAL_DMA_Start_IT + 7204 .LVL785: +3520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 7205 .loc 1 3520 0 + 7206 0130 C5E7 b .L414 + 7207 .LVL786: + 7208 .L422: +3434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7209 .loc 1 3434 0 + 7210 0132 0220 movs r0, #2 + 7211 .LVL787: + 7212 0134 CFE7 b .L411 + 7213 .L428: + 7214 0136 C046 .align 2 + 7215 .L427: + 7216 0138 00000000 .word TIM_DMACaptureCplt + 7217 013c 00000000 .word TIM_DMAError + 7218 0140 00000000 .word TIM_DMAPeriodElapsedCplt + 7219 0144 00000000 .word TIM_DMATriggerCplt + 7220 .cfi_endproc + 7221 .LFE104: + 7223 .section .text.HAL_TIM_DMABurst_ReadStop,"ax",%progbits + 7224 .align 1 + 7225 .global HAL_TIM_DMABurst_ReadStop + 7226 .syntax unified + 7227 .code 16 + 7228 .thumb_func + 7229 .fpu softvfp + 7231 HAL_TIM_DMABurst_ReadStop: + 7232 .LFB105: +3544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 7233 .loc 1 3544 0 + 7234 .cfi_startproc + 7235 @ args = 0, pretend = 0, frame = 0 + 7236 @ frame_needed = 0, uses_anonymous_args = 0 + 7237 .LVL788: + 7238 0000 70B5 push {r4, r5, r6, lr} + 7239 .LCFI47: + 7240 .cfi_def_cfa_offset 16 + 7241 .cfi_offset 4, -16 + 7242 .cfi_offset 5, -12 + 7243 .cfi_offset 6, -8 + 7244 .cfi_offset 14, -4 + 7245 0002 0500 movs r5, r0 + 7246 0004 0C00 movs r4, r1 +3549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7247 .loc 1 3549 0 + ARM GAS /tmp/ccH6KUTS.s page 234 + + + 7248 0006 8023 movs r3, #128 + 7249 0008 DB00 lsls r3, r3, #3 + 7250 000a 9942 cmp r1, r3 + 7251 000c 25D0 beq .L431 + 7252 000e 0FD9 bls .L438 + 7253 0010 8023 movs r3, #128 + 7254 0012 5B01 lsls r3, r3, #5 + 7255 0014 9942 cmp r1, r3 + 7256 0016 24D0 beq .L435 + 7257 0018 8023 movs r3, #128 + 7258 001a DB01 lsls r3, r3, #7 + 7259 001c 9942 cmp r1, r3 + 7260 001e 24D0 beq .L436 + 7261 0020 8023 movs r3, #128 + 7262 0022 1B01 lsls r3, r3, #4 + 7263 0024 9942 cmp r1, r3 + 7264 0026 12D1 bne .L430 +3568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7265 .loc 1 3568 0 + 7266 0028 406A ldr r0, [r0, #36] + 7267 .LVL789: + 7268 002a FFF7FEFF bl HAL_DMA_Abort + 7269 .LVL790: +3570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC4: + 7270 .loc 1 3570 0 + 7271 002e 0EE0 b .L430 + 7272 .LVL791: + 7273 .L438: +3549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7274 .loc 1 3549 0 + 7275 0030 8023 movs r3, #128 + 7276 0032 5B00 lsls r3, r3, #1 + 7277 0034 9942 cmp r1, r3 + 7278 0036 07D0 beq .L433 + 7279 0038 0133 adds r3, r3, #1 + 7280 003a FF33 adds r3, r3, #255 + 7281 003c 9942 cmp r1, r3 + 7282 003e 06D1 bne .L430 +3558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7283 .loc 1 3558 0 + 7284 0040 C069 ldr r0, [r0, #28] + 7285 .LVL792: + 7286 0042 FFF7FEFF bl HAL_DMA_Abort + 7287 .LVL793: +3560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC2: + 7288 .loc 1 3560 0 + 7289 0046 02E0 b .L430 + 7290 .LVL794: + 7291 .L433: +3553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7292 .loc 1 3553 0 + 7293 0048 8069 ldr r0, [r0, #24] + 7294 .LVL795: + 7295 004a FFF7FEFF bl HAL_DMA_Abort + 7296 .LVL796: + 7297 .L430: +3586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + ARM GAS /tmp/ccH6KUTS.s page 235 + + + 7298 .loc 1 3586 0 + 7299 004e 2A68 ldr r2, [r5] + 7300 0050 D368 ldr r3, [r2, #12] + 7301 0052 A343 bics r3, r4 + 7302 0054 D360 str r3, [r2, #12] +3590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7303 .loc 1 3590 0 + 7304 0056 0020 movs r0, #0 + 7305 @ sp needed + 7306 .LVL797: + 7307 .LVL798: + 7308 0058 70BD pop {r4, r5, r6, pc} + 7309 .LVL799: + 7310 .L431: +3563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7311 .loc 1 3563 0 + 7312 005a 006A ldr r0, [r0, #32] + 7313 .LVL800: + 7314 005c FFF7FEFF bl HAL_DMA_Abort + 7315 .LVL801: +3565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_CC3: + 7316 .loc 1 3565 0 + 7317 0060 F5E7 b .L430 + 7318 .LVL802: + 7319 .L435: +3573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7320 .loc 1 3573 0 + 7321 0062 806A ldr r0, [r0, #40] + 7322 .LVL803: + 7323 0064 FFF7FEFF bl HAL_DMA_Abort + 7324 .LVL804: +3575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** case TIM_DMA_TRIGGER: + 7325 .loc 1 3575 0 + 7326 0068 F1E7 b .L430 + 7327 .LVL805: + 7328 .L436: +3578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7329 .loc 1 3578 0 + 7330 006a C06A ldr r0, [r0, #44] + 7331 .LVL806: + 7332 006c FFF7FEFF bl HAL_DMA_Abort + 7333 .LVL807: +3580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** default: + 7334 .loc 1 3580 0 + 7335 0070 EDE7 b .L430 + 7336 .cfi_endproc + 7337 .LFE105: + 7339 .section .text.HAL_TIM_GenerateEvent,"ax",%progbits + 7340 .align 1 + 7341 .global HAL_TIM_GenerateEvent + 7342 .syntax unified + 7343 .code 16 + 7344 .thumb_func + 7345 .fpu softvfp + 7347 HAL_TIM_GenerateEvent: + 7348 .LFB106: +3608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccH6KUTS.s page 236 + + + 7349 .loc 1 3608 0 + 7350 .cfi_startproc + 7351 @ args = 0, pretend = 0, frame = 0 + 7352 @ frame_needed = 0, uses_anonymous_args = 0 + 7353 @ link register save eliminated. + 7354 .LVL808: +3614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7355 .loc 1 3614 0 + 7356 0000 3423 movs r3, #52 + 7357 0002 C35C ldrb r3, [r0, r3] + 7358 0004 012B cmp r3, #1 + 7359 0006 0BD0 beq .L441 +3617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7360 .loc 1 3617 0 discriminator 2 + 7361 0008 3523 movs r3, #53 + 7362 000a 0222 movs r2, #2 + 7363 000c C254 strb r2, [r0, r3] +3620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7364 .loc 1 3620 0 discriminator 2 + 7365 000e 0268 ldr r2, [r0] + 7366 0010 5161 str r1, [r2, #20] +3623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7367 .loc 1 3623 0 discriminator 2 + 7368 0012 0122 movs r2, #1 + 7369 0014 C254 strb r2, [r0, r3] +3625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7370 .loc 1 3625 0 discriminator 2 + 7371 0016 013B subs r3, r3, #1 + 7372 0018 0022 movs r2, #0 + 7373 001a C254 strb r2, [r0, r3] +3628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7374 .loc 1 3628 0 discriminator 2 + 7375 001c 0020 movs r0, #0 + 7376 .LVL809: + 7377 .L440: +3629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7378 .loc 1 3629 0 + 7379 @ sp needed + 7380 001e 7047 bx lr + 7381 .LVL810: + 7382 .L441: +3614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7383 .loc 1 3614 0 + 7384 0020 0220 movs r0, #2 + 7385 .LVL811: + 7386 0022 FCE7 b .L440 + 7387 .cfi_endproc + 7388 .LFE106: + 7390 .section .text.HAL_TIM_ConfigOCrefClear,"ax",%progbits + 7391 .align 1 + 7392 .global HAL_TIM_ConfigOCrefClear + 7393 .syntax unified + 7394 .code 16 + 7395 .thumb_func + 7396 .fpu softvfp + 7398 HAL_TIM_ConfigOCrefClear: + 7399 .LFB107: + ARM GAS /tmp/ccH6KUTS.s page 237 + + +3645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 7400 .loc 1 3645 0 + 7401 .cfi_startproc + 7402 @ args = 0, pretend = 0, frame = 0 + 7403 @ frame_needed = 0, uses_anonymous_args = 0 + 7404 .LVL812: + 7405 0000 70B5 push {r4, r5, r6, lr} + 7406 .LCFI48: + 7407 .cfi_def_cfa_offset 16 + 7408 .cfi_offset 4, -16 + 7409 .cfi_offset 5, -12 + 7410 .cfi_offset 6, -8 + 7411 .cfi_offset 14, -4 +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7412 .loc 1 3655 0 + 7413 0002 3423 movs r3, #52 + 7414 0004 C35C ldrb r3, [r0, r3] + 7415 0006 012B cmp r3, #1 + 7416 0008 68D0 beq .L455 +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7417 .loc 1 3655 0 is_stmt 0 discriminator 2 + 7418 000a 3423 movs r3, #52 + 7419 000c 0124 movs r4, #1 + 7420 000e C454 strb r4, [r0, r3] +3657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7421 .loc 1 3657 0 is_stmt 1 discriminator 2 + 7422 0010 0133 adds r3, r3, #1 + 7423 0012 0134 adds r4, r4, #1 + 7424 0014 C454 strb r4, [r0, r3] +3659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7425 .loc 1 3659 0 discriminator 2 + 7426 0016 4B68 ldr r3, [r1, #4] + 7427 0018 012B cmp r3, #1 + 7428 001a 10D0 beq .L456 + 7429 .L444: +3670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7430 .loc 1 3670 0 + 7431 001c 042A cmp r2, #4 + 7432 001e 38D0 beq .L446 + 7433 0020 1FD9 bls .L457 + 7434 0022 082A cmp r2, #8 + 7435 0024 45D0 beq .L449 + 7436 0026 0C2A cmp r2, #12 + 7437 0028 25D1 bne .L445 +3719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7438 .loc 1 3719 0 + 7439 002a 0B68 ldr r3, [r1] + 7440 002c 002B cmp r3, #0 + 7441 002e 4FD0 beq .L454 +3722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7442 .loc 1 3722 0 + 7443 0030 0268 ldr r2, [r0] + 7444 .LVL813: + 7445 0032 D169 ldr r1, [r2, #28] + 7446 .LVL814: + 7447 0034 8023 movs r3, #128 + 7448 0036 1B02 lsls r3, r3, #8 + ARM GAS /tmp/ccH6KUTS.s page 238 + + + 7449 0038 0B43 orrs r3, r1 + 7450 003a D361 str r3, [r2, #28] + 7451 003c 1BE0 b .L445 + 7452 .LVL815: + 7453 .L456: +3661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 7454 .loc 1 3661 0 + 7455 003e 0568 ldr r5, [r0] + 7456 .LVL816: + 7457 .LBB296: + 7458 .LBB297: +4915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7459 .loc 1 4915 0 + 7460 0040 AB68 ldr r3, [r5, #8] + 7461 .LVL817: +4918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7462 .loc 1 4918 0 + 7463 0042 274C ldr r4, .L458 + 7464 0044 2340 ands r3, r4 + 7465 .LVL818: +4921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7466 .loc 1 4921 0 + 7467 0046 0C69 ldr r4, [r1, #16] + 7468 0048 2402 lsls r4, r4, #8 + 7469 004a 8E68 ldr r6, [r1, #8] + 7470 004c 3443 orrs r4, r6 + 7471 004e CE68 ldr r6, [r1, #12] + 7472 0050 3443 orrs r4, r6 + 7473 0052 2343 orrs r3, r4 + 7474 .LVL819: +4924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7475 .loc 1 4924 0 + 7476 0054 AB60 str r3, [r5, #8] + 7477 .LVL820: + 7478 .LBE297: + 7479 .LBE296: +3667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7480 .loc 1 3667 0 + 7481 0056 0468 ldr r4, [r0] + 7482 0058 A368 ldr r3, [r4, #8] + 7483 005a 0825 movs r5, #8 + 7484 005c 2B43 orrs r3, r5 + 7485 005e A360 str r3, [r4, #8] + 7486 0060 DCE7 b .L444 + 7487 .L457: +3670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7488 .loc 1 3670 0 + 7489 0062 002A cmp r2, #0 + 7490 0064 07D1 bne .L445 +3674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7491 .loc 1 3674 0 + 7492 0066 0B68 ldr r3, [r1] + 7493 0068 002B cmp r3, #0 + 7494 006a 0CD0 beq .L451 +3677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7495 .loc 1 3677 0 + 7496 006c 0268 ldr r2, [r0] + ARM GAS /tmp/ccH6KUTS.s page 239 + + + 7497 .LVL821: + 7498 006e 9369 ldr r3, [r2, #24] + 7499 0070 8021 movs r1, #128 + 7500 .LVL822: + 7501 0072 0B43 orrs r3, r1 + 7502 0074 9361 str r3, [r2, #24] + 7503 .L445: +3735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7504 .loc 1 3735 0 + 7505 0076 3523 movs r3, #53 + 7506 0078 0122 movs r2, #1 + 7507 007a C254 strb r2, [r0, r3] +3737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7508 .loc 1 3737 0 + 7509 007c 013B subs r3, r3, #1 + 7510 007e 0022 movs r2, #0 + 7511 0080 C254 strb r2, [r0, r3] +3739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7512 .loc 1 3739 0 + 7513 0082 0020 movs r0, #0 + 7514 .LVL823: + 7515 .L443: +3740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7516 .loc 1 3740 0 + 7517 @ sp needed + 7518 0084 70BD pop {r4, r5, r6, pc} + 7519 .LVL824: + 7520 .L451: +3682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7521 .loc 1 3682 0 + 7522 0086 0268 ldr r2, [r0] + 7523 .LVL825: + 7524 0088 9369 ldr r3, [r2, #24] + 7525 008a 8021 movs r1, #128 + 7526 .LVL826: + 7527 008c 8B43 bics r3, r1 + 7528 008e 9361 str r3, [r2, #24] + 7529 0090 F1E7 b .L445 + 7530 .LVL827: + 7531 .L446: +3689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7532 .loc 1 3689 0 + 7533 0092 0B68 ldr r3, [r1] + 7534 0094 002B cmp r3, #0 + 7535 0096 06D0 beq .L452 +3692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7536 .loc 1 3692 0 + 7537 0098 0268 ldr r2, [r0] + 7538 .LVL828: + 7539 009a 9169 ldr r1, [r2, #24] + 7540 .LVL829: + 7541 009c 8023 movs r3, #128 + 7542 009e 1B02 lsls r3, r3, #8 + 7543 00a0 0B43 orrs r3, r1 + 7544 00a2 9361 str r3, [r2, #24] + 7545 00a4 E7E7 b .L445 + 7546 .LVL830: + ARM GAS /tmp/ccH6KUTS.s page 240 + + + 7547 .L452: +3697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7548 .loc 1 3697 0 + 7549 00a6 0268 ldr r2, [r0] + 7550 .LVL831: + 7551 00a8 9369 ldr r3, [r2, #24] + 7552 00aa 0E49 ldr r1, .L458+4 + 7553 .LVL832: + 7554 00ac 0B40 ands r3, r1 + 7555 00ae 9361 str r3, [r2, #24] + 7556 00b0 E1E7 b .L445 + 7557 .LVL833: + 7558 .L449: +3704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7559 .loc 1 3704 0 + 7560 00b2 0B68 ldr r3, [r1] + 7561 00b4 002B cmp r3, #0 + 7562 00b6 05D0 beq .L453 +3707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7563 .loc 1 3707 0 + 7564 00b8 0268 ldr r2, [r0] + 7565 .LVL834: + 7566 00ba D369 ldr r3, [r2, #28] + 7567 00bc 8021 movs r1, #128 + 7568 .LVL835: + 7569 00be 0B43 orrs r3, r1 + 7570 00c0 D361 str r3, [r2, #28] + 7571 00c2 D8E7 b .L445 + 7572 .LVL836: + 7573 .L453: +3712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7574 .loc 1 3712 0 + 7575 00c4 0268 ldr r2, [r0] + 7576 .LVL837: + 7577 00c6 D369 ldr r3, [r2, #28] + 7578 00c8 8021 movs r1, #128 + 7579 .LVL838: + 7580 00ca 8B43 bics r3, r1 + 7581 00cc D361 str r3, [r2, #28] + 7582 00ce D2E7 b .L445 + 7583 .LVL839: + 7584 .L454: +3727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7585 .loc 1 3727 0 + 7586 00d0 0268 ldr r2, [r0] + 7587 .LVL840: + 7588 00d2 D369 ldr r3, [r2, #28] + 7589 00d4 0349 ldr r1, .L458+4 + 7590 .LVL841: + 7591 00d6 0B40 ands r3, r1 + 7592 00d8 D361 str r3, [r2, #28] + 7593 00da CCE7 b .L445 + 7594 .LVL842: + 7595 .L455: +3655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7596 .loc 1 3655 0 + 7597 00dc 0220 movs r0, #2 + ARM GAS /tmp/ccH6KUTS.s page 241 + + + 7598 .LVL843: + 7599 00de D1E7 b .L443 + 7600 .L459: + 7601 .align 2 + 7602 .L458: + 7603 00e0 FF00FFFF .word -65281 + 7604 00e4 FF7FFFFF .word -32769 + 7605 .cfi_endproc + 7606 .LFE107: + 7608 .section .text.HAL_TIM_ConfigClockSource,"ax",%progbits + 7609 .align 1 + 7610 .global HAL_TIM_ConfigClockSource + 7611 .syntax unified + 7612 .code 16 + 7613 .thumb_func + 7614 .fpu softvfp + 7616 HAL_TIM_ConfigClockSource: + 7617 .LFB108: +3750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpsmcr = 0U; + 7618 .loc 1 3750 0 + 7619 .cfi_startproc + 7620 @ args = 0, pretend = 0, frame = 0 + 7621 @ frame_needed = 0, uses_anonymous_args = 0 + 7622 .LVL844: + 7623 0000 70B5 push {r4, r5, r6, lr} + 7624 .LCFI49: + 7625 .cfi_def_cfa_offset 16 + 7626 .cfi_offset 4, -16 + 7627 .cfi_offset 5, -12 + 7628 .cfi_offset 6, -8 + 7629 .cfi_offset 14, -4 + 7630 .LVL845: +3754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7631 .loc 1 3754 0 + 7632 0002 3423 movs r3, #52 + 7633 0004 C35C ldrb r3, [r0, r3] + 7634 0006 012B cmp r3, #1 + 7635 0008 00D1 bne .LCB7540 + 7636 000a CCE0 b .L476 @long jump + 7637 .LCB7540: +3754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7638 .loc 1 3754 0 is_stmt 0 discriminator 2 + 7639 000c 3423 movs r3, #52 + 7640 000e 0122 movs r2, #1 + 7641 0010 C254 strb r2, [r0, r3] +3756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7642 .loc 1 3756 0 is_stmt 1 discriminator 2 + 7643 0012 0133 adds r3, r3, #1 + 7644 0014 0132 adds r2, r2, #1 + 7645 0016 C254 strb r2, [r0, r3] +3762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 7646 .loc 1 3762 0 discriminator 2 + 7647 0018 0268 ldr r2, [r0] + 7648 001a 9368 ldr r3, [r2, #8] + 7649 .LVL846: +3764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 7650 .loc 1 3764 0 discriminator 2 + ARM GAS /tmp/ccH6KUTS.s page 242 + + + 7651 001c 634C ldr r4, .L479 + 7652 001e 2340 ands r3, r4 + 7653 .LVL847: +3765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7654 .loc 1 3765 0 discriminator 2 + 7655 0020 9360 str r3, [r2, #8] +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7656 .loc 1 3767 0 discriminator 2 + 7657 0022 0B68 ldr r3, [r1] + 7658 .LVL848: + 7659 0024 402B cmp r3, #64 + 7660 0026 00D1 bne .LCB7559 + 7661 0028 93E0 b .L463 @long jump + 7662 .LCB7559: + 7663 002a 22D9 bls .L477 + 7664 002c 702B cmp r3, #112 + 7665 002e 63D0 beq .L470 + 7666 0030 3AD8 bhi .L471 + 7667 0032 502B cmp r3, #80 + 7668 0034 00D1 bne .LCB7567 + 7669 0036 72E0 b .L472 @long jump + 7670 .LCB7567: + 7671 0038 602B cmp r3, #96 + 7672 003a 55D1 bne .L462 +3831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 7673 .loc 1 3831 0 + 7674 003c 0368 ldr r3, [r0] + 7675 003e 4C68 ldr r4, [r1, #4] + 7676 0040 CD68 ldr r5, [r1, #12] + 7677 .LVL849: + 7678 .LBB298: + 7679 .LBB299: +4758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 7680 .loc 1 4758 0 + 7681 0042 1A6A ldr r2, [r3, #32] + 7682 .LVL850: + 7683 0044 1021 movs r1, #16 + 7684 .LVL851: + 7685 0046 8A43 bics r2, r1 + 7686 0048 1A62 str r2, [r3, #32] +4759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer = TIMx->CCER; + 7687 .loc 1 4759 0 + 7688 004a 9969 ldr r1, [r3, #24] + 7689 .LVL852: +4760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7690 .loc 1 4760 0 + 7691 004c 1A6A ldr r2, [r3, #32] + 7692 .LVL853: +4763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 12U); + 7693 .loc 1 4763 0 + 7694 004e 584E ldr r6, .L479+4 + 7695 0050 3140 ands r1, r6 + 7696 .LVL854: +4764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7697 .loc 1 4764 0 + 7698 0052 2D03 lsls r5, r5, #12 + 7699 .LVL855: + ARM GAS /tmp/ccH6KUTS.s page 243 + + + 7700 0054 2943 orrs r1, r5 + 7701 .LVL856: +4767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity << 4U); + 7702 .loc 1 4767 0 + 7703 0056 A025 movs r5, #160 + 7704 0058 AA43 bics r2, r5 + 7705 .LVL857: +4768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7706 .loc 1 4768 0 + 7707 005a 2401 lsls r4, r4, #4 + 7708 .LVL858: + 7709 005c 2243 orrs r2, r4 + 7710 .LVL859: +4771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 7711 .loc 1 4771 0 + 7712 005e 9961 str r1, [r3, #24] +4772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7713 .loc 1 4772 0 + 7714 0060 1A62 str r2, [r3, #32] + 7715 .LVL860: + 7716 .LBE299: + 7717 .LBE298: +3834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7718 .loc 1 3834 0 + 7719 0062 0268 ldr r2, [r0] + 7720 .LVL861: + 7721 .LBB300: + 7722 .LBB301: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 7723 .loc 1 4885 0 + 7724 0064 9368 ldr r3, [r2, #8] + 7725 .LVL862: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 7726 .loc 1 4887 0 + 7727 0066 7021 movs r1, #112 + 7728 0068 8B43 bics r3, r1 + 7729 .LVL863: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 7730 .loc 1 4889 0 + 7731 006a 0939 subs r1, r1, #9 + 7732 006c 0B43 orrs r3, r1 + 7733 .LVL864: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7734 .loc 1 4891 0 + 7735 006e 9360 str r3, [r2, #8] + 7736 0070 3AE0 b .L462 + 7737 .LVL865: + 7738 .L477: + 7739 .LBE301: + 7740 .LBE300: +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7741 .loc 1 3767 0 discriminator 2 + 7742 0072 102B cmp r3, #16 + 7743 0074 00D1 bne .LCB7650 + 7744 0076 86E0 b .L465 @long jump + 7745 .LCB7650: + 7746 0078 0CD9 bls .L478 + ARM GAS /tmp/ccH6KUTS.s page 244 + + + 7747 007a 202B cmp r3, #32 + 7748 007c 00D1 bne .LCB7654 + 7749 007e 8AE0 b .L468 @long jump + 7750 .LCB7654: + 7751 0080 302B cmp r3, #48 + 7752 0082 31D1 bne .L462 +3869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7753 .loc 1 3869 0 + 7754 0084 0268 ldr r2, [r0] + 7755 .LVL866: + 7756 .LBB302: + 7757 .LBB303: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 7758 .loc 1 4885 0 + 7759 0086 9368 ldr r3, [r2, #8] + 7760 .LVL867: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 7761 .loc 1 4887 0 + 7762 0088 7021 movs r1, #112 + 7763 .LVL868: + 7764 008a 8B43 bics r3, r1 + 7765 .LVL869: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 7766 .loc 1 4889 0 + 7767 008c 3939 subs r1, r1, #57 + 7768 008e 0B43 orrs r3, r1 + 7769 .LVL870: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7770 .loc 1 4891 0 + 7771 0090 9360 str r3, [r2, #8] + 7772 0092 29E0 b .L462 + 7773 .LVL871: + 7774 .L478: + 7775 .LBE303: + 7776 .LBE302: +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7777 .loc 1 3767 0 discriminator 2 + 7778 0094 002B cmp r3, #0 + 7779 0096 27D1 bne .L462 +3851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7780 .loc 1 3851 0 + 7781 0098 0268 ldr r2, [r0] + 7782 .LVL872: + 7783 .LBB304: + 7784 .LBB305: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 7785 .loc 1 4885 0 + 7786 009a 9368 ldr r3, [r2, #8] + 7787 .LVL873: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 7788 .loc 1 4887 0 + 7789 009c 7021 movs r1, #112 + 7790 .LVL874: + 7791 009e 8B43 bics r3, r1 + 7792 .LVL875: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 7793 .loc 1 4889 0 + ARM GAS /tmp/ccH6KUTS.s page 245 + + + 7794 00a0 6939 subs r1, r1, #105 + 7795 00a2 0B43 orrs r3, r1 + 7796 .LVL876: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7797 .loc 1 4891 0 + 7798 00a4 9360 str r3, [r2, #8] + 7799 00a6 1FE0 b .L462 + 7800 .LVL877: + 7801 .L471: + 7802 .LBE305: + 7803 .LBE304: +3767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 7804 .loc 1 3767 0 discriminator 2 + 7805 00a8 8022 movs r2, #128 + 7806 .LVL878: + 7807 00aa 5201 lsls r2, r2, #5 + 7808 00ac 9342 cmp r3, r2 + 7809 00ae 16D0 beq .L474 + 7810 00b0 8022 movs r2, #128 + 7811 00b2 9201 lsls r2, r2, #6 + 7812 00b4 9342 cmp r3, r2 + 7813 00b6 17D1 bne .L462 +3806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 7814 .loc 1 3806 0 + 7815 00b8 0568 ldr r5, [r0] + 7816 00ba 8A68 ldr r2, [r1, #8] + 7817 00bc 4C68 ldr r4, [r1, #4] + 7818 00be C968 ldr r1, [r1, #12] + 7819 .LVL879: + 7820 .LBB306: + 7821 .LBB307: +4915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7822 .loc 1 4915 0 + 7823 00c0 AB68 ldr r3, [r5, #8] + 7824 .LVL880: +4918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7825 .loc 1 4918 0 + 7826 00c2 3C4E ldr r6, .L479+8 + 7827 00c4 3340 ands r3, r6 + 7828 .LVL881: +4921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7829 .loc 1 4921 0 + 7830 00c6 0902 lsls r1, r1, #8 + 7831 .LVL882: + 7832 00c8 2143 orrs r1, r4 + 7833 00ca 0A43 orrs r2, r1 + 7834 .LVL883: + 7835 00cc 1343 orrs r3, r2 + 7836 .LVL884: +4924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7837 .loc 1 4924 0 + 7838 00ce AB60 str r3, [r5, #8] + 7839 .LVL885: + 7840 .LBE307: + 7841 .LBE306: +3811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7842 .loc 1 3811 0 + ARM GAS /tmp/ccH6KUTS.s page 246 + + + 7843 00d0 0268 ldr r2, [r0] + 7844 00d2 9168 ldr r1, [r2, #8] + 7845 00d4 8023 movs r3, #128 + 7846 00d6 DB01 lsls r3, r3, #7 + 7847 00d8 0B43 orrs r3, r1 + 7848 00da 9360 str r3, [r2, #8] +3813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7849 .loc 1 3813 0 + 7850 00dc 04E0 b .L462 + 7851 .LVL886: + 7852 .L474: +3773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7853 .loc 1 3773 0 + 7854 00de 0268 ldr r2, [r0] + 7855 00e0 9368 ldr r3, [r2, #8] + 7856 00e2 0721 movs r1, #7 + 7857 .LVL887: + 7858 00e4 8B43 bics r3, r1 + 7859 00e6 9360 str r3, [r2, #8] + 7860 .L462: +3876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7861 .loc 1 3876 0 + 7862 00e8 3523 movs r3, #53 + 7863 00ea 0122 movs r2, #1 + 7864 00ec C254 strb r2, [r0, r3] +3878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7865 .loc 1 3878 0 + 7866 00ee 013B subs r3, r3, #1 + 7867 00f0 0022 movs r2, #0 + 7868 00f2 C254 strb r2, [r0, r3] +3880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7869 .loc 1 3880 0 + 7870 00f4 0020 movs r0, #0 + 7871 .LVL888: + 7872 .L461: +3881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7873 .loc 1 3881 0 + 7874 @ sp needed + 7875 00f6 70BD pop {r4, r5, r6, pc} + 7876 .LVL889: + 7877 .L470: +3784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 7878 .loc 1 3784 0 + 7879 00f8 0568 ldr r5, [r0] + 7880 00fa 8A68 ldr r2, [r1, #8] + 7881 .LVL890: + 7882 00fc 4C68 ldr r4, [r1, #4] + 7883 00fe C968 ldr r1, [r1, #12] + 7884 .LVL891: + 7885 .LBB308: + 7886 .LBB309: +4915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7887 .loc 1 4915 0 + 7888 0100 AB68 ldr r3, [r5, #8] + 7889 .LVL892: +4918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7890 .loc 1 4918 0 + ARM GAS /tmp/ccH6KUTS.s page 247 + + + 7891 0102 2C4E ldr r6, .L479+8 + 7892 0104 3340 ands r3, r6 + 7893 .LVL893: +4921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7894 .loc 1 4921 0 + 7895 0106 0902 lsls r1, r1, #8 + 7896 .LVL894: + 7897 0108 2143 orrs r1, r4 + 7898 010a 0A43 orrs r2, r1 + 7899 .LVL895: + 7900 010c 1343 orrs r3, r2 + 7901 .LVL896: +4924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7902 .loc 1 4924 0 + 7903 010e AB60 str r3, [r5, #8] + 7904 .LVL897: + 7905 .LBE309: + 7906 .LBE308: +3789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the SMS and TS Bits */ + 7907 .loc 1 3789 0 + 7908 0110 0268 ldr r2, [r0] + 7909 0112 9368 ldr r3, [r2, #8] + 7910 .LVL898: +3791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Select the External clock mode1 and the ETRF trigger */ + 7911 .loc 1 3791 0 + 7912 0114 7721 movs r1, #119 + 7913 0116 8B43 bics r3, r1 + 7914 .LVL899: +3793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 7915 .loc 1 3793 0 + 7916 0118 0B43 orrs r3, r1 + 7917 .LVL900: +3795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7918 .loc 1 3795 0 + 7919 011a 9360 str r3, [r2, #8] +3797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7920 .loc 1 3797 0 + 7921 011c E4E7 b .L462 + 7922 .LVL901: + 7923 .L472: +3820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 7924 .loc 1 3820 0 + 7925 011e 0368 ldr r3, [r0] + 7926 0120 4C68 ldr r4, [r1, #4] + 7927 0122 CD68 ldr r5, [r1, #12] + 7928 .LVL902: + 7929 .LBB310: + 7930 .LBB311: +4678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 7931 .loc 1 4678 0 + 7932 0124 196A ldr r1, [r3, #32] + 7933 .LVL903: +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 7934 .loc 1 4679 0 + 7935 0126 1A6A ldr r2, [r3, #32] + 7936 .LVL904: + 7937 0128 0126 movs r6, #1 + ARM GAS /tmp/ccH6KUTS.s page 248 + + + 7938 012a B243 bics r2, r6 + 7939 012c 1A62 str r2, [r3, #32] +4680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7940 .loc 1 4680 0 + 7941 012e 9A69 ldr r2, [r3, #24] + 7942 .LVL905: +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); + 7943 .loc 1 4683 0 + 7944 0130 EF36 adds r6, r6, #239 + 7945 0132 B243 bics r2, r6 + 7946 .LVL906: +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7947 .loc 1 4684 0 + 7948 0134 2D01 lsls r5, r5, #4 + 7949 .LVL907: + 7950 0136 2A43 orrs r2, r5 + 7951 .LVL908: +4687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; + 7952 .loc 1 4687 0 + 7953 0138 0A25 movs r5, #10 + 7954 013a A943 bics r1, r5 + 7955 .LVL909: +4688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 7956 .loc 1 4688 0 + 7957 013c 2143 orrs r1, r4 + 7958 .LVL910: +4691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 7959 .loc 1 4691 0 + 7960 013e 9A61 str r2, [r3, #24] +4692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7961 .loc 1 4692 0 + 7962 0140 1962 str r1, [r3, #32] + 7963 .LVL911: + 7964 .LBE311: + 7965 .LBE310: +3823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7966 .loc 1 3823 0 + 7967 0142 0268 ldr r2, [r0] + 7968 .LVL912: + 7969 .LBB312: + 7970 .LBB313: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 7971 .loc 1 4885 0 + 7972 0144 9368 ldr r3, [r2, #8] + 7973 .LVL913: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 7974 .loc 1 4887 0 + 7975 0146 7021 movs r1, #112 + 7976 0148 8B43 bics r3, r1 + 7977 .LVL914: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 7978 .loc 1 4889 0 + 7979 014a 1939 subs r1, r1, #25 + 7980 014c 0B43 orrs r3, r1 + 7981 .LVL915: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 7982 .loc 1 4891 0 + ARM GAS /tmp/ccH6KUTS.s page 249 + + + 7983 014e 9360 str r3, [r2, #8] + 7984 0150 CAE7 b .L462 + 7985 .LVL916: + 7986 .L463: + 7987 .LBE313: + 7988 .LBE312: +3842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 7989 .loc 1 3842 0 + 7990 0152 0368 ldr r3, [r0] + 7991 0154 4C68 ldr r4, [r1, #4] + 7992 0156 CD68 ldr r5, [r1, #12] + 7993 .LVL917: + 7994 .LBB314: + 7995 .LBB315: +4678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 7996 .loc 1 4678 0 + 7997 0158 196A ldr r1, [r3, #32] + 7998 .LVL918: +4679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 7999 .loc 1 4679 0 + 8000 015a 1A6A ldr r2, [r3, #32] + 8001 .LVL919: + 8002 015c 0126 movs r6, #1 + 8003 015e B243 bics r2, r6 + 8004 0160 1A62 str r2, [r3, #32] +4680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8005 .loc 1 4680 0 + 8006 0162 9A69 ldr r2, [r3, #24] + 8007 .LVL920: +4683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); + 8008 .loc 1 4683 0 + 8009 0164 EF36 adds r6, r6, #239 + 8010 0166 B243 bics r2, r6 + 8011 .LVL921: +4684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8012 .loc 1 4684 0 + 8013 0168 2D01 lsls r5, r5, #4 + 8014 .LVL922: + 8015 016a 2A43 orrs r2, r5 + 8016 .LVL923: +4687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; + 8017 .loc 1 4687 0 + 8018 016c 0A25 movs r5, #10 + 8019 016e A943 bics r1, r5 + 8020 .LVL924: +4688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8021 .loc 1 4688 0 + 8022 0170 2143 orrs r1, r4 + 8023 .LVL925: +4691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIMx->CCER = tmpccer; + 8024 .loc 1 4691 0 + 8025 0172 9A61 str r2, [r3, #24] +4692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8026 .loc 1 4692 0 + 8027 0174 1962 str r1, [r3, #32] + 8028 .LVL926: + 8029 .LBE315: + ARM GAS /tmp/ccH6KUTS.s page 250 + + + 8030 .LBE314: +3845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8031 .loc 1 3845 0 + 8032 0176 0268 ldr r2, [r0] + 8033 .LVL927: + 8034 .LBB316: + 8035 .LBB317: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 8036 .loc 1 4885 0 + 8037 0178 9368 ldr r3, [r2, #8] + 8038 .LVL928: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 8039 .loc 1 4887 0 + 8040 017a 7021 movs r1, #112 + 8041 017c 8B43 bics r3, r1 + 8042 .LVL929: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 8043 .loc 1 4889 0 + 8044 017e 2939 subs r1, r1, #41 + 8045 0180 0B43 orrs r3, r1 + 8046 .LVL930: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8047 .loc 1 4891 0 + 8048 0182 9360 str r3, [r2, #8] + 8049 0184 B0E7 b .L462 + 8050 .LVL931: + 8051 .L465: + 8052 .LBE317: + 8053 .LBE316: +3857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8054 .loc 1 3857 0 + 8055 0186 0268 ldr r2, [r0] + 8056 .LVL932: + 8057 .LBB318: + 8058 .LBB319: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 8059 .loc 1 4885 0 + 8060 0188 9368 ldr r3, [r2, #8] + 8061 .LVL933: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 8062 .loc 1 4887 0 + 8063 018a 7021 movs r1, #112 + 8064 .LVL934: + 8065 018c 8B43 bics r3, r1 + 8066 .LVL935: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 8067 .loc 1 4889 0 + 8068 018e 5939 subs r1, r1, #89 + 8069 0190 0B43 orrs r3, r1 + 8070 .LVL936: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8071 .loc 1 4891 0 + 8072 0192 9360 str r3, [r2, #8] + 8073 0194 A8E7 b .L462 + 8074 .LVL937: + 8075 .L468: + 8076 .LBE319: + ARM GAS /tmp/ccH6KUTS.s page 251 + + + 8077 .LBE318: +3863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8078 .loc 1 3863 0 + 8079 0196 0268 ldr r2, [r0] + 8080 .LVL938: + 8081 .LBB320: + 8082 .LBB321: +4885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Reset the TS Bits */ + 8083 .loc 1 4885 0 + 8084 0198 9368 ldr r3, [r2, #8] + 8085 .LVL939: +4887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ + 8086 .loc 1 4887 0 + 8087 019a 7021 movs r1, #112 + 8088 .LVL940: + 8089 019c 8B43 bics r3, r1 + 8090 .LVL941: +4889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Write to TIMx SMCR */ + 8091 .loc 1 4889 0 + 8092 019e 4939 subs r1, r1, #73 + 8093 01a0 0B43 orrs r3, r1 + 8094 .LVL942: +4891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8095 .loc 1 4891 0 + 8096 01a2 9360 str r3, [r2, #8] + 8097 01a4 A0E7 b .L462 + 8098 .LVL943: + 8099 .L476: + 8100 .LBE321: + 8101 .LBE320: +3754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8102 .loc 1 3754 0 + 8103 01a6 0220 movs r0, #2 + 8104 .LVL944: + 8105 01a8 A5E7 b .L461 + 8106 .L480: + 8107 01aa C046 .align 2 + 8108 .L479: + 8109 01ac 8800FFFF .word -65400 + 8110 01b0 FF0FFFFF .word -61441 + 8111 01b4 FF00FFFF .word -65281 + 8112 .cfi_endproc + 8113 .LFE108: + 8115 .section .text.HAL_TIM_ConfigTI1Input,"ax",%progbits + 8116 .align 1 + 8117 .global HAL_TIM_ConfigTI1Input + 8118 .syntax unified + 8119 .code 16 + 8120 .thumb_func + 8121 .fpu softvfp + 8123 HAL_TIM_ConfigTI1Input: + 8124 .LFB109: +3896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpcr2 = 0U; + 8125 .loc 1 3896 0 + 8126 .cfi_startproc + 8127 @ args = 0, pretend = 0, frame = 0 + 8128 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccH6KUTS.s page 252 + + + 8129 @ link register save eliminated. + 8130 .LVL945: +3904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8131 .loc 1 3904 0 + 8132 0000 0268 ldr r2, [r0] + 8133 0002 5368 ldr r3, [r2, #4] + 8134 .LVL946: +3907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8135 .loc 1 3907 0 + 8136 0004 8020 movs r0, #128 + 8137 .LVL947: + 8138 0006 8343 bics r3, r0 + 8139 .LVL948: +3910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8140 .loc 1 3910 0 + 8141 0008 1943 orrs r1, r3 + 8142 .LVL949: +3913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8143 .loc 1 3913 0 + 8144 000a 5160 str r1, [r2, #4] +3916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8145 .loc 1 3916 0 + 8146 000c 0020 movs r0, #0 + 8147 @ sp needed + 8148 000e 7047 bx lr + 8149 .cfi_endproc + 8150 .LFE109: + 8152 .section .text.HAL_TIM_SlaveConfigSynchronization,"ax",%progbits + 8153 .align 1 + 8154 .global HAL_TIM_SlaveConfigSynchronization + 8155 .syntax unified + 8156 .code 16 + 8157 .thumb_func + 8158 .fpu softvfp + 8160 HAL_TIM_SlaveConfigSynchronization: + 8161 .LFB110: +3928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 8162 .loc 1 3928 0 + 8163 .cfi_startproc + 8164 @ args = 0, pretend = 0, frame = 0 + 8165 @ frame_needed = 0, uses_anonymous_args = 0 + 8166 .LVL950: + 8167 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8168 .LCFI50: + 8169 .cfi_def_cfa_offset 24 + 8170 .cfi_offset 3, -24 + 8171 .cfi_offset 4, -20 + 8172 .cfi_offset 5, -16 + 8173 .cfi_offset 6, -12 + 8174 .cfi_offset 7, -8 + 8175 .cfi_offset 14, -4 + 8176 0002 0400 movs r4, r0 +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8177 .loc 1 3934 0 + 8178 0004 3423 movs r3, #52 + 8179 0006 C35C ldrb r3, [r0, r3] + 8180 0008 012B cmp r3, #1 + ARM GAS /tmp/ccH6KUTS.s page 253 + + + 8181 000a 16D0 beq .L484 +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8182 .loc 1 3934 0 is_stmt 0 discriminator 2 + 8183 000c 3425 movs r5, #52 + 8184 000e 0127 movs r7, #1 + 8185 0010 4755 strb r7, [r0, r5] +3936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8186 .loc 1 3936 0 is_stmt 1 discriminator 2 + 8187 0012 3526 movs r6, #53 + 8188 0014 0223 movs r3, #2 + 8189 0016 8355 strb r3, [r0, r6] +3939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8190 .loc 1 3939 0 discriminator 2 + 8191 0018 FFF7FEFF bl TIM_SlaveTimer_SetConfig + 8192 .LVL951: +3942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8193 .loc 1 3942 0 discriminator 2 + 8194 001c 2268 ldr r2, [r4] + 8195 001e D368 ldr r3, [r2, #12] + 8196 0020 4021 movs r1, #64 + 8197 0022 8B43 bics r3, r1 + 8198 0024 D360 str r3, [r2, #12] +3945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8199 .loc 1 3945 0 discriminator 2 + 8200 0026 2268 ldr r2, [r4] + 8201 0028 D368 ldr r3, [r2, #12] + 8202 002a 0549 ldr r1, .L485 + 8203 002c 0B40 ands r3, r1 + 8204 002e D360 str r3, [r2, #12] +3948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8205 .loc 1 3948 0 discriminator 2 + 8206 0030 A755 strb r7, [r4, r6] +3950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8207 .loc 1 3950 0 discriminator 2 + 8208 0032 0023 movs r3, #0 + 8209 0034 6355 strb r3, [r4, r5] +3952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8210 .loc 1 3952 0 discriminator 2 + 8211 0036 0020 movs r0, #0 + 8212 .L483: +3953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8213 .loc 1 3953 0 + 8214 @ sp needed + 8215 .LVL952: + 8216 0038 F8BD pop {r3, r4, r5, r6, r7, pc} + 8217 .LVL953: + 8218 .L484: +3934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8219 .loc 1 3934 0 + 8220 003a 0220 movs r0, #2 + 8221 .LVL954: + 8222 003c FCE7 b .L483 + 8223 .L486: + 8224 003e C046 .align 2 + 8225 .L485: + 8226 0040 FFBFFFFF .word -16385 + 8227 .cfi_endproc + ARM GAS /tmp/ccH6KUTS.s page 254 + + + 8228 .LFE110: + 8230 .section .text.HAL_TIM_SlaveConfigSynchronization_IT,"ax",%progbits + 8231 .align 1 + 8232 .global HAL_TIM_SlaveConfigSynchronization_IT + 8233 .syntax unified + 8234 .code 16 + 8235 .thumb_func + 8236 .fpu softvfp + 8238 HAL_TIM_SlaveConfigSynchronization_IT: + 8239 .LFB111: +3966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Check the parameters */ + 8240 .loc 1 3966 0 + 8241 .cfi_startproc + 8242 @ args = 0, pretend = 0, frame = 0 + 8243 @ frame_needed = 0, uses_anonymous_args = 0 + 8244 .LVL955: + 8245 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8246 .LCFI51: + 8247 .cfi_def_cfa_offset 24 + 8248 .cfi_offset 3, -24 + 8249 .cfi_offset 4, -20 + 8250 .cfi_offset 5, -16 + 8251 .cfi_offset 6, -12 + 8252 .cfi_offset 7, -8 + 8253 .cfi_offset 14, -4 + 8254 0002 0400 movs r4, r0 +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8255 .loc 1 3972 0 + 8256 0004 3423 movs r3, #52 + 8257 0006 C35C ldrb r3, [r0, r3] + 8258 0008 012B cmp r3, #1 + 8259 000a 16D0 beq .L489 +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8260 .loc 1 3972 0 is_stmt 0 discriminator 2 + 8261 000c 3425 movs r5, #52 + 8262 000e 0127 movs r7, #1 + 8263 0010 4755 strb r7, [r0, r5] +3974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8264 .loc 1 3974 0 is_stmt 1 discriminator 2 + 8265 0012 3526 movs r6, #53 + 8266 0014 0223 movs r3, #2 + 8267 0016 8355 strb r3, [r0, r6] +3976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8268 .loc 1 3976 0 discriminator 2 + 8269 0018 FFF7FEFF bl TIM_SlaveTimer_SetConfig + 8270 .LVL956: +3979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8271 .loc 1 3979 0 discriminator 2 + 8272 001c 2268 ldr r2, [r4] + 8273 001e D368 ldr r3, [r2, #12] + 8274 0020 4021 movs r1, #64 + 8275 0022 0B43 orrs r3, r1 + 8276 0024 D360 str r3, [r2, #12] +3982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8277 .loc 1 3982 0 discriminator 2 + 8278 0026 2268 ldr r2, [r4] + 8279 0028 D368 ldr r3, [r2, #12] + ARM GAS /tmp/ccH6KUTS.s page 255 + + + 8280 002a 0549 ldr r1, .L490 + 8281 002c 0B40 ands r3, r1 + 8282 002e D360 str r3, [r2, #12] +3984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8283 .loc 1 3984 0 discriminator 2 + 8284 0030 A755 strb r7, [r4, r6] +3986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8285 .loc 1 3986 0 discriminator 2 + 8286 0032 0023 movs r3, #0 + 8287 0034 6355 strb r3, [r4, r5] +3988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8288 .loc 1 3988 0 discriminator 2 + 8289 0036 0020 movs r0, #0 + 8290 .L488: +3989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8291 .loc 1 3989 0 + 8292 @ sp needed + 8293 .LVL957: + 8294 0038 F8BD pop {r3, r4, r5, r6, r7, pc} + 8295 .LVL958: + 8296 .L489: +3972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8297 .loc 1 3972 0 + 8298 003a 0220 movs r0, #2 + 8299 .LVL959: + 8300 003c FCE7 b .L488 + 8301 .L491: + 8302 003e C046 .align 2 + 8303 .L490: + 8304 0040 FFBFFFFF .word -16385 + 8305 .cfi_endproc + 8306 .LFE111: + 8308 .section .text.HAL_TIM_ReadCapturedValue,"ax",%progbits + 8309 .align 1 + 8310 .global HAL_TIM_ReadCapturedValue + 8311 .syntax unified + 8312 .code 16 + 8313 .thumb_func + 8314 .fpu softvfp + 8316 HAL_TIM_ReadCapturedValue: + 8317 .LFB112: +4003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** uint32_t tmpreg = 0U; + 8318 .loc 1 4003 0 + 8319 .cfi_startproc + 8320 @ args = 0, pretend = 0, frame = 0 + 8321 @ frame_needed = 0, uses_anonymous_args = 0 + 8322 @ link register save eliminated. + 8323 .LVL960: +4006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8324 .loc 1 4006 0 + 8325 0000 3423 movs r3, #52 + 8326 0002 C35C ldrb r3, [r0, r3] + 8327 0004 012B cmp r3, #1 + 8328 0006 1DD0 beq .L500 +4006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8329 .loc 1 4006 0 is_stmt 0 discriminator 2 + 8330 0008 3423 movs r3, #52 + ARM GAS /tmp/ccH6KUTS.s page 256 + + + 8331 000a 0122 movs r2, #1 + 8332 000c C254 strb r2, [r0, r3] +4008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8333 .loc 1 4008 0 is_stmt 1 discriminator 2 + 8334 000e 0429 cmp r1, #4 + 8335 0010 10D0 beq .L495 + 8336 0012 06D9 bls .L502 + 8337 0014 0829 cmp r1, #8 + 8338 0016 10D0 beq .L498 + 8339 0018 0C29 cmp r1, #12 + 8340 001a 11D1 bne .L501 +4048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8341 .loc 1 4048 0 + 8342 001c 0368 ldr r3, [r0] + 8343 001e 1B6C ldr r3, [r3, #64] + 8344 .LVL961: +4050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8345 .loc 1 4050 0 + 8346 0020 03E0 b .L494 + 8347 .LVL962: + 8348 .L502: +4008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8349 .loc 1 4008 0 discriminator 2 + 8350 0022 0029 cmp r1, #0 + 8351 0024 0CD1 bne .L501 +4016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8352 .loc 1 4016 0 + 8353 0026 0368 ldr r3, [r0] + 8354 0028 5B6B ldr r3, [r3, #52] + 8355 .LVL963: + 8356 .L494: +4057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return tmpreg; + 8357 .loc 1 4057 0 + 8358 002a 3422 movs r2, #52 + 8359 002c 0021 movs r1, #0 + 8360 .LVL964: + 8361 002e 8154 strb r1, [r0, r2] + 8362 .LVL965: + 8363 .L492: +4059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8364 .loc 1 4059 0 + 8365 0030 1800 movs r0, r3 + 8366 .LVL966: + 8367 @ sp needed + 8368 0032 7047 bx lr + 8369 .LVL967: + 8370 .L495: +4026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8371 .loc 1 4026 0 + 8372 0034 0368 ldr r3, [r0] + 8373 0036 9B6B ldr r3, [r3, #56] + 8374 .LVL968: +4028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8375 .loc 1 4028 0 + 8376 0038 F7E7 b .L494 + 8377 .LVL969: + 8378 .L498: + ARM GAS /tmp/ccH6KUTS.s page 257 + + +4037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8379 .loc 1 4037 0 + 8380 003a 0368 ldr r3, [r0] + 8381 003c DB6B ldr r3, [r3, #60] + 8382 .LVL970: +4039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8383 .loc 1 4039 0 + 8384 003e F4E7 b .L494 + 8385 .LVL971: + 8386 .L501: +4004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8387 .loc 1 4004 0 + 8388 0040 0023 movs r3, #0 + 8389 0042 F2E7 b .L494 + 8390 .L500: +4006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8391 .loc 1 4006 0 + 8392 0044 0223 movs r3, #2 + 8393 0046 F3E7 b .L492 + 8394 .cfi_endproc + 8395 .LFE112: + 8397 .section .text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits + 8398 .align 1 + 8399 .weak HAL_TIM_PeriodElapsedCallback + 8400 .syntax unified + 8401 .code 16 + 8402 .thumb_func + 8403 .fpu softvfp + 8405 HAL_TIM_PeriodElapsedCallback: + 8406 .LFB113: +4090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8407 .loc 1 4090 0 + 8408 .cfi_startproc + 8409 @ args = 0, pretend = 0, frame = 0 + 8410 @ frame_needed = 0, uses_anonymous_args = 0 + 8411 @ link register save eliminated. + 8412 .LVL972: +4098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 8413 .loc 1 4098 0 + 8414 @ sp needed + 8415 0000 7047 bx lr + 8416 .cfi_endproc + 8417 .LFE113: + 8419 .section .text.TIM_DMAPeriodElapsedCplt,"ax",%progbits + 8420 .align 1 + 8421 .syntax unified + 8422 .code 16 + 8423 .thumb_func + 8424 .fpu softvfp + 8426 TIM_DMAPeriodElapsedCplt: + 8427 .LFB128: +4356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 8428 .loc 1 4356 0 + 8429 .cfi_startproc + 8430 @ args = 0, pretend = 0, frame = 0 + 8431 @ frame_needed = 0, uses_anonymous_args = 0 + 8432 .LVL973: + ARM GAS /tmp/ccH6KUTS.s page 258 + + + 8433 0000 10B5 push {r4, lr} + 8434 .LCFI52: + 8435 .cfi_def_cfa_offset 8 + 8436 .cfi_offset 4, -8 + 8437 .cfi_offset 14, -4 +4357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8438 .loc 1 4357 0 + 8439 0002 806A ldr r0, [r0, #40] + 8440 .LVL974: +4359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8441 .loc 1 4359 0 + 8442 0004 3523 movs r3, #53 + 8443 0006 0122 movs r2, #1 + 8444 0008 C254 strb r2, [r0, r3] +4361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8445 .loc 1 4361 0 + 8446 000a FFF7FEFF bl HAL_TIM_PeriodElapsedCallback + 8447 .LVL975: +4362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8448 .loc 1 4362 0 + 8449 @ sp needed + 8450 000e 10BD pop {r4, pc} + 8451 .cfi_endproc + 8452 .LFE128: + 8454 .section .text.HAL_TIM_OC_DelayElapsedCallback,"ax",%progbits + 8455 .align 1 + 8456 .weak HAL_TIM_OC_DelayElapsedCallback + 8457 .syntax unified + 8458 .code 16 + 8459 .thumb_func + 8460 .fpu softvfp + 8462 HAL_TIM_OC_DelayElapsedCallback: + 8463 .LFB114: +4105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8464 .loc 1 4105 0 + 8465 .cfi_startproc + 8466 @ args = 0, pretend = 0, frame = 0 + 8467 @ frame_needed = 0, uses_anonymous_args = 0 + 8468 @ link register save eliminated. + 8469 .LVL976: +4112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 8470 .loc 1 4112 0 + 8471 @ sp needed + 8472 0000 7047 bx lr + 8473 .cfi_endproc + 8474 .LFE114: + 8476 .section .text.HAL_TIM_IC_CaptureCallback,"ax",%progbits + 8477 .align 1 + 8478 .weak HAL_TIM_IC_CaptureCallback + 8479 .syntax unified + 8480 .code 16 + 8481 .thumb_func + 8482 .fpu softvfp + 8484 HAL_TIM_IC_CaptureCallback: + 8485 .LFB115: +4119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8486 .loc 1 4119 0 + ARM GAS /tmp/ccH6KUTS.s page 259 + + + 8487 .cfi_startproc + 8488 @ args = 0, pretend = 0, frame = 0 + 8489 @ frame_needed = 0, uses_anonymous_args = 0 + 8490 @ link register save eliminated. + 8491 .LVL977: +4126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8492 .loc 1 4126 0 + 8493 @ sp needed + 8494 0000 7047 bx lr + 8495 .cfi_endproc + 8496 .LFE115: + 8498 .section .text.TIM_DMACaptureCplt,"ax",%progbits + 8499 .align 1 + 8500 .global TIM_DMACaptureCplt + 8501 .syntax unified + 8502 .code 16 + 8503 .thumb_func + 8504 .fpu softvfp + 8506 TIM_DMACaptureCplt: + 8507 .LFB127: +4308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 8508 .loc 1 4308 0 + 8509 .cfi_startproc + 8510 @ args = 0, pretend = 0, frame = 0 + 8511 @ frame_needed = 0, uses_anonymous_args = 0 + 8512 .LVL978: + 8513 0000 10B5 push {r4, lr} + 8514 .LCFI53: + 8515 .cfi_def_cfa_offset 8 + 8516 .cfi_offset 4, -8 + 8517 .cfi_offset 14, -4 +4309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8518 .loc 1 4309 0 + 8519 0002 846A ldr r4, [r0, #40] + 8520 .LVL979: +4311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8521 .loc 1 4311 0 + 8522 0004 3523 movs r3, #53 + 8523 0006 0122 movs r2, #1 + 8524 0008 E254 strb r2, [r4, r3] +4313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8525 .loc 1 4313 0 + 8526 000a E369 ldr r3, [r4, #28] + 8527 000c 8342 cmp r3, r0 + 8528 000e 0BD0 beq .L512 +4317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8529 .loc 1 4317 0 + 8530 0010 236A ldr r3, [r4, #32] + 8531 0012 8342 cmp r3, r0 + 8532 0014 10D0 beq .L513 +4321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8533 .loc 1 4321 0 + 8534 0016 636A ldr r3, [r4, #36] + 8535 0018 8342 cmp r3, r0 + 8536 001a 10D0 beq .L514 +4325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8537 .loc 1 4325 0 + ARM GAS /tmp/ccH6KUTS.s page 260 + + + 8538 001c A36A ldr r3, [r4, #40] + 8539 001e 8342 cmp r3, r0 + 8540 0020 04D1 bne .L509 +4327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8541 .loc 1 4327 0 + 8542 0022 0823 movs r3, #8 + 8543 0024 2375 strb r3, [r4, #20] + 8544 0026 01E0 b .L509 + 8545 .L512: +4315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8546 .loc 1 4315 0 + 8547 0028 0123 movs r3, #1 + 8548 002a 2375 strb r3, [r4, #20] + 8549 .L509: +4330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8550 .loc 1 4330 0 + 8551 002c 2000 movs r0, r4 + 8552 .LVL980: + 8553 002e FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 8554 .LVL981: +4332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8555 .loc 1 4332 0 + 8556 0032 0023 movs r3, #0 + 8557 0034 2375 strb r3, [r4, #20] +4333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8558 .loc 1 4333 0 + 8559 @ sp needed + 8560 .LVL982: + 8561 0036 10BD pop {r4, pc} + 8562 .LVL983: + 8563 .L513: +4319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8564 .loc 1 4319 0 + 8565 0038 0223 movs r3, #2 + 8566 003a 2375 strb r3, [r4, #20] + 8567 003c F6E7 b .L509 + 8568 .L514: +4323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8569 .loc 1 4323 0 + 8570 003e 0423 movs r3, #4 + 8571 0040 2375 strb r3, [r4, #20] + 8572 0042 F3E7 b .L509 + 8573 .cfi_endproc + 8574 .LFE127: + 8576 .section .text.HAL_TIM_PWM_PulseFinishedCallback,"ax",%progbits + 8577 .align 1 + 8578 .weak HAL_TIM_PWM_PulseFinishedCallback + 8579 .syntax unified + 8580 .code 16 + 8581 .thumb_func + 8582 .fpu softvfp + 8584 HAL_TIM_PWM_PulseFinishedCallback: + 8585 .LFB116: +4134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8586 .loc 1 4134 0 + 8587 .cfi_startproc + 8588 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccH6KUTS.s page 261 + + + 8589 @ frame_needed = 0, uses_anonymous_args = 0 + 8590 @ link register save eliminated. + 8591 .LVL984: +4141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8592 .loc 1 4141 0 + 8593 @ sp needed + 8594 0000 7047 bx lr + 8595 .cfi_endproc + 8596 .LFE116: + 8598 .section .text.TIM_DMADelayPulseCplt,"ax",%progbits + 8599 .align 1 + 8600 .global TIM_DMADelayPulseCplt + 8601 .syntax unified + 8602 .code 16 + 8603 .thumb_func + 8604 .fpu softvfp + 8606 TIM_DMADelayPulseCplt: + 8607 .LFB126: +4276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 8608 .loc 1 4276 0 + 8609 .cfi_startproc + 8610 @ args = 0, pretend = 0, frame = 0 + 8611 @ frame_needed = 0, uses_anonymous_args = 0 + 8612 .LVL985: + 8613 0000 10B5 push {r4, lr} + 8614 .LCFI54: + 8615 .cfi_def_cfa_offset 8 + 8616 .cfi_offset 4, -8 + 8617 .cfi_offset 14, -4 +4277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8618 .loc 1 4277 0 + 8619 0002 846A ldr r4, [r0, #40] + 8620 .LVL986: +4279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8621 .loc 1 4279 0 + 8622 0004 3523 movs r3, #53 + 8623 0006 0122 movs r2, #1 + 8624 0008 E254 strb r2, [r4, r3] +4281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8625 .loc 1 4281 0 + 8626 000a E369 ldr r3, [r4, #28] + 8627 000c 8342 cmp r3, r0 + 8628 000e 0BD0 beq .L521 +4285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8629 .loc 1 4285 0 + 8630 0010 236A ldr r3, [r4, #32] + 8631 0012 8342 cmp r3, r0 + 8632 0014 10D0 beq .L522 +4289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8633 .loc 1 4289 0 + 8634 0016 636A ldr r3, [r4, #36] + 8635 0018 8342 cmp r3, r0 + 8636 001a 10D0 beq .L523 +4293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8637 .loc 1 4293 0 + 8638 001c A36A ldr r3, [r4, #40] + 8639 001e 8342 cmp r3, r0 + ARM GAS /tmp/ccH6KUTS.s page 262 + + + 8640 0020 04D1 bne .L518 +4295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8641 .loc 1 4295 0 + 8642 0022 0823 movs r3, #8 + 8643 0024 2375 strb r3, [r4, #20] + 8644 0026 01E0 b .L518 + 8645 .L521: +4283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8646 .loc 1 4283 0 + 8647 0028 0123 movs r3, #1 + 8648 002a 2375 strb r3, [r4, #20] + 8649 .L518: +4297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8650 .loc 1 4297 0 + 8651 002c 2000 movs r0, r4 + 8652 .LVL987: + 8653 002e FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 8654 .LVL988: +4299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8655 .loc 1 4299 0 + 8656 0032 0023 movs r3, #0 + 8657 0034 2375 strb r3, [r4, #20] +4300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /** + 8658 .loc 1 4300 0 + 8659 @ sp needed + 8660 .LVL989: + 8661 0036 10BD pop {r4, pc} + 8662 .LVL990: + 8663 .L522: +4287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8664 .loc 1 4287 0 + 8665 0038 0223 movs r3, #2 + 8666 003a 2375 strb r3, [r4, #20] + 8667 003c F6E7 b .L518 + 8668 .L523: +4291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8669 .loc 1 4291 0 + 8670 003e 0423 movs r3, #4 + 8671 0040 2375 strb r3, [r4, #20] + 8672 0042 F3E7 b .L518 + 8673 .cfi_endproc + 8674 .LFE126: + 8676 .section .text.HAL_TIM_TriggerCallback,"ax",%progbits + 8677 .align 1 + 8678 .weak HAL_TIM_TriggerCallback + 8679 .syntax unified + 8680 .code 16 + 8681 .thumb_func + 8682 .fpu softvfp + 8684 HAL_TIM_TriggerCallback: + 8685 .LFB117: +4149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8686 .loc 1 4149 0 + 8687 .cfi_startproc + 8688 @ args = 0, pretend = 0, frame = 0 + 8689 @ frame_needed = 0, uses_anonymous_args = 0 + 8690 @ link register save eliminated. + ARM GAS /tmp/ccH6KUTS.s page 263 + + + 8691 .LVL991: +4156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8692 .loc 1 4156 0 + 8693 @ sp needed + 8694 0000 7047 bx lr + 8695 .cfi_endproc + 8696 .LFE117: + 8698 .section .text.HAL_TIM_IRQHandler,"ax",%progbits + 8699 .align 1 + 8700 .global HAL_TIM_IRQHandler + 8701 .syntax unified + 8702 .code 16 + 8703 .thumb_func + 8704 .fpu softvfp + 8706 HAL_TIM_IRQHandler: + 8707 .LFB97: +2684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Capture compare 1 event */ + 8708 .loc 1 2684 0 + 8709 .cfi_startproc + 8710 @ args = 0, pretend = 0, frame = 0 + 8711 @ frame_needed = 0, uses_anonymous_args = 0 + 8712 .LVL992: + 8713 0000 10B5 push {r4, lr} + 8714 .LCFI55: + 8715 .cfi_def_cfa_offset 8 + 8716 .cfi_offset 4, -8 + 8717 .cfi_offset 14, -4 + 8718 0002 0400 movs r4, r0 +2686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8719 .loc 1 2686 0 + 8720 0004 0368 ldr r3, [r0] + 8721 0006 1A69 ldr r2, [r3, #16] + 8722 0008 9207 lsls r2, r2, #30 + 8723 000a 0FD5 bpl .L526 +2688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8724 .loc 1 2688 0 + 8725 000c DA68 ldr r2, [r3, #12] + 8726 000e 9207 lsls r2, r2, #30 + 8727 0010 0CD5 bpl .L526 +2691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8728 .loc 1 2691 0 + 8729 0012 0322 movs r2, #3 + 8730 0014 5242 rsbs r2, r2, #0 + 8731 0016 1A61 str r2, [r3, #16] +2692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8732 .loc 1 2692 0 + 8733 0018 0123 movs r3, #1 + 8734 001a 0375 strb r3, [r0, #20] +2695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8735 .loc 1 2695 0 + 8736 001c 0368 ldr r3, [r0] + 8737 001e 9B69 ldr r3, [r3, #24] + 8738 0020 9B07 lsls r3, r3, #30 + 8739 0022 55D0 beq .L527 +2697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8740 .loc 1 2697 0 + 8741 0024 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + ARM GAS /tmp/ccH6KUTS.s page 264 + + + 8742 .LVL993: + 8743 .L528: +2705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8744 .loc 1 2705 0 + 8745 0028 0023 movs r3, #0 + 8746 002a 2375 strb r3, [r4, #20] + 8747 .L526: +2710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8748 .loc 1 2710 0 + 8749 002c 2368 ldr r3, [r4] + 8750 002e 1A69 ldr r2, [r3, #16] + 8751 0030 5207 lsls r2, r2, #29 + 8752 0032 12D5 bpl .L529 +2712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8753 .loc 1 2712 0 + 8754 0034 DA68 ldr r2, [r3, #12] + 8755 0036 5207 lsls r2, r2, #29 + 8756 0038 0FD5 bpl .L529 +2714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8757 .loc 1 2714 0 + 8758 003a 0522 movs r2, #5 + 8759 003c 5242 rsbs r2, r2, #0 + 8760 003e 1A61 str r2, [r3, #16] +2715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ + 8761 .loc 1 2715 0 + 8762 0040 0223 movs r3, #2 + 8763 0042 2375 strb r3, [r4, #20] +2717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8764 .loc 1 2717 0 + 8765 0044 2368 ldr r3, [r4] + 8766 0046 9A69 ldr r2, [r3, #24] + 8767 0048 C023 movs r3, #192 + 8768 004a 9B00 lsls r3, r3, #2 + 8769 004c 1A42 tst r2, r3 + 8770 004e 45D0 beq .L530 +2719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8771 .loc 1 2719 0 + 8772 0050 2000 movs r0, r4 + 8773 0052 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 8774 .LVL994: + 8775 .L531: +2727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8776 .loc 1 2727 0 + 8777 0056 0023 movs r3, #0 + 8778 0058 2375 strb r3, [r4, #20] + 8779 .L529: +2731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8780 .loc 1 2731 0 + 8781 005a 2368 ldr r3, [r4] + 8782 005c 1A69 ldr r2, [r3, #16] + 8783 005e 1207 lsls r2, r2, #28 + 8784 0060 10D5 bpl .L532 +2733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8785 .loc 1 2733 0 + 8786 0062 DA68 ldr r2, [r3, #12] + 8787 0064 1207 lsls r2, r2, #28 + 8788 0066 0DD5 bpl .L532 + ARM GAS /tmp/ccH6KUTS.s page 265 + + +2735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8789 .loc 1 2735 0 + 8790 0068 0922 movs r2, #9 + 8791 006a 5242 rsbs r2, r2, #0 + 8792 006c 1A61 str r2, [r3, #16] +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ + 8793 .loc 1 2736 0 + 8794 006e 0423 movs r3, #4 + 8795 0070 2375 strb r3, [r4, #20] +2738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8796 .loc 1 2738 0 + 8797 0072 2368 ldr r3, [r4] + 8798 0074 DB69 ldr r3, [r3, #28] + 8799 0076 9B07 lsls r3, r3, #30 + 8800 0078 37D0 beq .L533 +2740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8801 .loc 1 2740 0 + 8802 007a 2000 movs r0, r4 + 8803 007c FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 8804 .LVL995: + 8805 .L534: +2748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8806 .loc 1 2748 0 + 8807 0080 0023 movs r3, #0 + 8808 0082 2375 strb r3, [r4, #20] + 8809 .L532: +2752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8810 .loc 1 2752 0 + 8811 0084 2368 ldr r3, [r4] + 8812 0086 1A69 ldr r2, [r3, #16] + 8813 0088 D206 lsls r2, r2, #27 + 8814 008a 12D5 bpl .L535 +2754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8815 .loc 1 2754 0 + 8816 008c DA68 ldr r2, [r3, #12] + 8817 008e D206 lsls r2, r2, #27 + 8818 0090 0FD5 bpl .L535 +2756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8819 .loc 1 2756 0 + 8820 0092 1122 movs r2, #17 + 8821 0094 5242 rsbs r2, r2, #0 + 8822 0096 1A61 str r2, [r3, #16] +2757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Input capture event */ + 8823 .loc 1 2757 0 + 8824 0098 0823 movs r3, #8 + 8825 009a 2375 strb r3, [r4, #20] +2759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8826 .loc 1 2759 0 + 8827 009c 2368 ldr r3, [r4] + 8828 009e DA69 ldr r2, [r3, #28] + 8829 00a0 C023 movs r3, #192 + 8830 00a2 9B00 lsls r3, r3, #2 + 8831 00a4 1A42 tst r2, r3 + 8832 00a6 27D0 beq .L536 +2761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8833 .loc 1 2761 0 + 8834 00a8 2000 movs r0, r4 + ARM GAS /tmp/ccH6KUTS.s page 266 + + + 8835 00aa FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 8836 .LVL996: + 8837 .L537: +2769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8838 .loc 1 2769 0 + 8839 00ae 0023 movs r3, #0 + 8840 00b0 2375 strb r3, [r4, #20] + 8841 .L535: +2773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8842 .loc 1 2773 0 + 8843 00b2 2368 ldr r3, [r4] + 8844 00b4 1A69 ldr r2, [r3, #16] + 8845 00b6 D207 lsls r2, r2, #31 + 8846 00b8 02D5 bpl .L538 +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8847 .loc 1 2775 0 + 8848 00ba DA68 ldr r2, [r3, #12] + 8849 00bc D207 lsls r2, r2, #31 + 8850 00be 22D4 bmi .L540 + 8851 .L538: +2782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8852 .loc 1 2782 0 + 8853 00c0 2368 ldr r3, [r4] + 8854 00c2 1A69 ldr r2, [r3, #16] + 8855 00c4 5206 lsls r2, r2, #25 + 8856 00c6 02D5 bpl .L525 +2784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** { + 8857 .loc 1 2784 0 + 8858 00c8 DA68 ldr r2, [r3, #12] + 8859 00ca 5206 lsls r2, r2, #25 + 8860 00cc 22D4 bmi .L541 + 8861 .L525: +2790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8862 .loc 1 2790 0 + 8863 @ sp needed + 8864 .LVL997: + 8865 00ce 10BD pop {r4, pc} + 8866 .LVL998: + 8867 .L527: +2702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 8868 .loc 1 2702 0 + 8869 00d0 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 8870 .LVL999: +2703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8871 .loc 1 2703 0 + 8872 00d4 2000 movs r0, r4 + 8873 00d6 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 8874 .LVL1000: + 8875 00da A5E7 b .L528 + 8876 .L530: +2724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 8877 .loc 1 2724 0 + 8878 00dc 2000 movs r0, r4 + 8879 00de FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 8880 .LVL1001: +2725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8881 .loc 1 2725 0 + ARM GAS /tmp/ccH6KUTS.s page 267 + + + 8882 00e2 2000 movs r0, r4 + 8883 00e4 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 8884 .LVL1002: + 8885 00e8 B5E7 b .L531 + 8886 .L533: +2745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 8887 .loc 1 2745 0 + 8888 00ea 2000 movs r0, r4 + 8889 00ec FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 8890 .LVL1003: +2746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8891 .loc 1 2746 0 + 8892 00f0 2000 movs r0, r4 + 8893 00f2 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 8894 .LVL1004: + 8895 00f6 C3E7 b .L534 + 8896 .L536: +2766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 8897 .loc 1 2766 0 + 8898 00f8 2000 movs r0, r4 + 8899 00fa FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 8900 .LVL1005: +2767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8901 .loc 1 2767 0 + 8902 00fe 2000 movs r0, r4 + 8903 0100 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 8904 .LVL1006: + 8905 0104 D3E7 b .L537 + 8906 .L540: +2777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); + 8907 .loc 1 2777 0 + 8908 0106 0222 movs r2, #2 + 8909 0108 5242 rsbs r2, r2, #0 + 8910 010a 1A61 str r2, [r3, #16] +2778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8911 .loc 1 2778 0 + 8912 010c 2000 movs r0, r4 + 8913 010e FFF7FEFF bl HAL_TIM_PeriodElapsedCallback + 8914 .LVL1007: + 8915 0112 D5E7 b .L538 + 8916 .L541: +2786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); + 8917 .loc 1 2786 0 + 8918 0114 4122 movs r2, #65 + 8919 0116 5242 rsbs r2, r2, #0 + 8920 0118 1A61 str r2, [r3, #16] +2787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8921 .loc 1 2787 0 + 8922 011a 2000 movs r0, r4 + 8923 011c FFF7FEFF bl HAL_TIM_TriggerCallback + 8924 .LVL1008: +2790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8925 .loc 1 2790 0 + 8926 0120 D5E7 b .L525 + 8927 .cfi_endproc + 8928 .LFE97: + 8930 .section .text.TIM_DMATriggerCplt,"ax",%progbits + ARM GAS /tmp/ccH6KUTS.s page 268 + + + 8931 .align 1 + 8932 .syntax unified + 8933 .code 16 + 8934 .thumb_func + 8935 .fpu softvfp + 8937 TIM_DMATriggerCplt: + 8938 .LFB129: +4371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 8939 .loc 1 4371 0 + 8940 .cfi_startproc + 8941 @ args = 0, pretend = 0, frame = 0 + 8942 @ frame_needed = 0, uses_anonymous_args = 0 + 8943 .LVL1009: + 8944 0000 10B5 push {r4, lr} + 8945 .LCFI56: + 8946 .cfi_def_cfa_offset 8 + 8947 .cfi_offset 4, -8 + 8948 .cfi_offset 14, -4 +4372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8949 .loc 1 4372 0 + 8950 0002 806A ldr r0, [r0, #40] + 8951 .LVL1010: +4374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8952 .loc 1 4374 0 + 8953 0004 3523 movs r3, #53 + 8954 0006 0122 movs r2, #1 + 8955 0008 C254 strb r2, [r0, r3] +4376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 8956 .loc 1 4376 0 + 8957 000a FFF7FEFF bl HAL_TIM_TriggerCallback + 8958 .LVL1011: +4377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8959 .loc 1 4377 0 + 8960 @ sp needed + 8961 000e 10BD pop {r4, pc} + 8962 .cfi_endproc + 8963 .LFE129: + 8965 .section .text.HAL_TIM_ErrorCallback,"ax",%progbits + 8966 .align 1 + 8967 .weak HAL_TIM_ErrorCallback + 8968 .syntax unified + 8969 .code 16 + 8970 .thumb_func + 8971 .fpu softvfp + 8973 HAL_TIM_ErrorCallback: + 8974 .LFB118: +4164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 8975 .loc 1 4164 0 + 8976 .cfi_startproc + 8977 @ args = 0, pretend = 0, frame = 0 + 8978 @ frame_needed = 0, uses_anonymous_args = 0 + 8979 @ link register save eliminated. + 8980 .LVL1012: +4171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 8981 .loc 1 4171 0 + 8982 @ sp needed + 8983 0000 7047 bx lr + ARM GAS /tmp/ccH6KUTS.s page 269 + + + 8984 .cfi_endproc + 8985 .LFE118: + 8987 .section .text.TIM_DMAError,"ax",%progbits + 8988 .align 1 + 8989 .global TIM_DMAError + 8990 .syntax unified + 8991 .code 16 + 8992 .thumb_func + 8993 .fpu softvfp + 8995 TIM_DMAError: + 8996 .LFB125: +4261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 8997 .loc 1 4261 0 + 8998 .cfi_startproc + 8999 @ args = 0, pretend = 0, frame = 0 + 9000 @ frame_needed = 0, uses_anonymous_args = 0 + 9001 .LVL1013: + 9002 0000 10B5 push {r4, lr} + 9003 .LCFI57: + 9004 .cfi_def_cfa_offset 8 + 9005 .cfi_offset 4, -8 + 9006 .cfi_offset 14, -4 +4262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9007 .loc 1 4262 0 + 9008 0002 806A ldr r0, [r0, #40] + 9009 .LVL1014: +4264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9010 .loc 1 4264 0 + 9011 0004 3523 movs r3, #53 + 9012 0006 0122 movs r2, #1 + 9013 0008 C254 strb r2, [r0, r3] +4266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9014 .loc 1 4266 0 + 9015 000a FFF7FEFF bl HAL_TIM_ErrorCallback + 9016 .LVL1015: +4267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9017 .loc 1 4267 0 + 9018 @ sp needed + 9019 000e 10BD pop {r4, pc} + 9020 .cfi_endproc + 9021 .LFE125: + 9023 .section .text.HAL_TIM_Base_GetState,"ax",%progbits + 9024 .align 1 + 9025 .global HAL_TIM_Base_GetState + 9026 .syntax unified + 9027 .code 16 + 9028 .thumb_func + 9029 .fpu softvfp + 9031 HAL_TIM_Base_GetState: + 9032 .LFB119: +4198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9033 .loc 1 4198 0 + 9034 .cfi_startproc + 9035 @ args = 0, pretend = 0, frame = 0 + 9036 @ frame_needed = 0, uses_anonymous_args = 0 + 9037 @ link register save eliminated. + 9038 .LVL1016: + ARM GAS /tmp/ccH6KUTS.s page 270 + + +4199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9039 .loc 1 4199 0 + 9040 0000 3523 movs r3, #53 + 9041 0002 C05C ldrb r0, [r0, r3] + 9042 .LVL1017: + 9043 0004 C0B2 uxtb r0, r0 +4200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9044 .loc 1 4200 0 + 9045 @ sp needed + 9046 0006 7047 bx lr + 9047 .cfi_endproc + 9048 .LFE119: + 9050 .section .text.HAL_TIM_OC_GetState,"ax",%progbits + 9051 .align 1 + 9052 .global HAL_TIM_OC_GetState + 9053 .syntax unified + 9054 .code 16 + 9055 .thumb_func + 9056 .fpu softvfp + 9058 HAL_TIM_OC_GetState: + 9059 .LFB120: +4208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9060 .loc 1 4208 0 + 9061 .cfi_startproc + 9062 @ args = 0, pretend = 0, frame = 0 + 9063 @ frame_needed = 0, uses_anonymous_args = 0 + 9064 @ link register save eliminated. + 9065 .LVL1018: +4209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9066 .loc 1 4209 0 + 9067 0000 3523 movs r3, #53 + 9068 0002 C05C ldrb r0, [r0, r3] + 9069 .LVL1019: + 9070 0004 C0B2 uxtb r0, r0 +4210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9071 .loc 1 4210 0 + 9072 @ sp needed + 9073 0006 7047 bx lr + 9074 .cfi_endproc + 9075 .LFE120: + 9077 .section .text.HAL_TIM_PWM_GetState,"ax",%progbits + 9078 .align 1 + 9079 .global HAL_TIM_PWM_GetState + 9080 .syntax unified + 9081 .code 16 + 9082 .thumb_func + 9083 .fpu softvfp + 9085 HAL_TIM_PWM_GetState: + 9086 .LFB121: +4218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9087 .loc 1 4218 0 + 9088 .cfi_startproc + 9089 @ args = 0, pretend = 0, frame = 0 + 9090 @ frame_needed = 0, uses_anonymous_args = 0 + 9091 @ link register save eliminated. + 9092 .LVL1020: +4219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + ARM GAS /tmp/ccH6KUTS.s page 271 + + + 9093 .loc 1 4219 0 + 9094 0000 3523 movs r3, #53 + 9095 0002 C05C ldrb r0, [r0, r3] + 9096 .LVL1021: + 9097 0004 C0B2 uxtb r0, r0 +4220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9098 .loc 1 4220 0 + 9099 @ sp needed + 9100 0006 7047 bx lr + 9101 .cfi_endproc + 9102 .LFE121: + 9104 .section .text.HAL_TIM_IC_GetState,"ax",%progbits + 9105 .align 1 + 9106 .global HAL_TIM_IC_GetState + 9107 .syntax unified + 9108 .code 16 + 9109 .thumb_func + 9110 .fpu softvfp + 9112 HAL_TIM_IC_GetState: + 9113 .LFB122: +4228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9114 .loc 1 4228 0 + 9115 .cfi_startproc + 9116 @ args = 0, pretend = 0, frame = 0 + 9117 @ frame_needed = 0, uses_anonymous_args = 0 + 9118 @ link register save eliminated. + 9119 .LVL1022: +4229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9120 .loc 1 4229 0 + 9121 0000 3523 movs r3, #53 + 9122 0002 C05C ldrb r0, [r0, r3] + 9123 .LVL1023: + 9124 0004 C0B2 uxtb r0, r0 +4230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9125 .loc 1 4230 0 + 9126 @ sp needed + 9127 0006 7047 bx lr + 9128 .cfi_endproc + 9129 .LFE122: + 9131 .section .text.HAL_TIM_OnePulse_GetState,"ax",%progbits + 9132 .align 1 + 9133 .global HAL_TIM_OnePulse_GetState + 9134 .syntax unified + 9135 .code 16 + 9136 .thumb_func + 9137 .fpu softvfp + 9139 HAL_TIM_OnePulse_GetState: + 9140 .LFB123: +4238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9141 .loc 1 4238 0 + 9142 .cfi_startproc + 9143 @ args = 0, pretend = 0, frame = 0 + 9144 @ frame_needed = 0, uses_anonymous_args = 0 + 9145 @ link register save eliminated. + 9146 .LVL1024: +4239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9147 .loc 1 4239 0 + ARM GAS /tmp/ccH6KUTS.s page 272 + + + 9148 0000 3523 movs r3, #53 + 9149 0002 C05C ldrb r0, [r0, r3] + 9150 .LVL1025: + 9151 0004 C0B2 uxtb r0, r0 +4240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9152 .loc 1 4240 0 + 9153 @ sp needed + 9154 0006 7047 bx lr + 9155 .cfi_endproc + 9156 .LFE123: + 9158 .section .text.HAL_TIM_Encoder_GetState,"ax",%progbits + 9159 .align 1 + 9160 .global HAL_TIM_Encoder_GetState + 9161 .syntax unified + 9162 .code 16 + 9163 .thumb_func + 9164 .fpu softvfp + 9166 HAL_TIM_Encoder_GetState: + 9167 .LFB124: +4248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** return htim->State; + 9168 .loc 1 4248 0 + 9169 .cfi_startproc + 9170 @ args = 0, pretend = 0, frame = 0 + 9171 @ frame_needed = 0, uses_anonymous_args = 0 + 9172 @ link register save eliminated. + 9173 .LVL1026: +4249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** } + 9174 .loc 1 4249 0 + 9175 0000 3523 movs r3, #53 + 9176 0002 C05C ldrb r0, [r0, r3] + 9177 .LVL1027: + 9178 0004 C0B2 uxtb r0, r0 +4250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c **** + 9179 .loc 1 4250 0 + 9180 @ sp needed + 9181 0006 7047 bx lr + 9182 .cfi_endproc + 9183 .LFE124: + 9185 .text + 9186 .Letext0: + 9187 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 9188 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 9189 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 9190 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 9191 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 9192 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 9193 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 9194 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 9195 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 9196 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 9197 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 9198 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h" + ARM GAS /tmp/ccH6KUTS.s page 273 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_tim.c + /tmp/ccH6KUTS.s:16 .text.TIM_Base_SetConfig:0000000000000000 $t + /tmp/ccH6KUTS.s:22 .text.TIM_Base_SetConfig:0000000000000000 TIM_Base_SetConfig + /tmp/ccH6KUTS.s:107 .text.TIM_Base_SetConfig:0000000000000058 $d + /tmp/ccH6KUTS.s:115 .text.TIM_TI1_SetConfig:0000000000000000 $t + /tmp/ccH6KUTS.s:121 .text.TIM_TI1_SetConfig:0000000000000000 TIM_TI1_SetConfig + /tmp/ccH6KUTS.s:216 .text.TIM_TI1_SetConfig:0000000000000054 $d + /tmp/ccH6KUTS.s:223 .text.TIM_SlaveTimer_SetConfig:0000000000000000 $t + /tmp/ccH6KUTS.s:229 .text.TIM_SlaveTimer_SetConfig:0000000000000000 TIM_SlaveTimer_SetConfig + /tmp/ccH6KUTS.s:445 .text.TIM_SlaveTimer_SetConfig:00000000000000b8 $d + /tmp/ccH6KUTS.s:451 .text.HAL_TIM_Base_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:458 .text.HAL_TIM_Base_MspInit:0000000000000000 HAL_TIM_Base_MspInit + /tmp/ccH6KUTS.s:473 .text.HAL_TIM_Base_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:480 .text.HAL_TIM_Base_Init:0000000000000000 HAL_TIM_Base_Init + /tmp/ccH6KUTS.s:543 .text.HAL_TIM_Base_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:550 .text.HAL_TIM_Base_MspDeInit:0000000000000000 HAL_TIM_Base_MspDeInit + /tmp/ccH6KUTS.s:565 .text.HAL_TIM_Base_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:572 .text.HAL_TIM_Base_DeInit:0000000000000000 HAL_TIM_Base_DeInit + /tmp/ccH6KUTS.s:621 .text.HAL_TIM_Base_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:626 .text.HAL_TIM_Base_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:633 .text.HAL_TIM_Base_Start:0000000000000000 HAL_TIM_Base_Start + /tmp/ccH6KUTS.s:666 .text.HAL_TIM_Base_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:673 .text.HAL_TIM_Base_Stop:0000000000000000 HAL_TIM_Base_Stop + /tmp/ccH6KUTS.s:709 .text.HAL_TIM_Base_Stop:0000000000000024 $d + /tmp/ccH6KUTS.s:714 .text.HAL_TIM_Base_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:721 .text.HAL_TIM_Base_Start_IT:0000000000000000 HAL_TIM_Base_Start_IT + /tmp/ccH6KUTS.s:749 .text.HAL_TIM_Base_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:756 .text.HAL_TIM_Base_Stop_IT:0000000000000000 HAL_TIM_Base_Stop_IT + /tmp/ccH6KUTS.s:790 .text.HAL_TIM_Base_Stop_IT:0000000000000020 $d + /tmp/ccH6KUTS.s:795 .text.HAL_TIM_Base_Start_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:802 .text.HAL_TIM_Base_Start_DMA:0000000000000000 HAL_TIM_Base_Start_DMA + /tmp/ccH6KUTS.s:887 .text.HAL_TIM_Base_Start_DMA:000000000000005c $d + /tmp/ccH6KUTS.s:8426 .text.TIM_DMAPeriodElapsedCplt:0000000000000000 TIM_DMAPeriodElapsedCplt + /tmp/ccH6KUTS.s:8995 .text.TIM_DMAError:0000000000000000 TIM_DMAError + /tmp/ccH6KUTS.s:893 .text.HAL_TIM_Base_Stop_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:900 .text.HAL_TIM_Base_Stop_DMA:0000000000000000 HAL_TIM_Base_Stop_DMA + /tmp/ccH6KUTS.s:938 .text.HAL_TIM_Base_Stop_DMA:0000000000000028 $d + /tmp/ccH6KUTS.s:944 .text.HAL_TIM_OC_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:951 .text.HAL_TIM_OC_MspInit:0000000000000000 HAL_TIM_OC_MspInit + /tmp/ccH6KUTS.s:966 .text.HAL_TIM_OC_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:973 .text.HAL_TIM_OC_Init:0000000000000000 HAL_TIM_OC_Init + /tmp/ccH6KUTS.s:1036 .text.HAL_TIM_OC_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:1043 .text.HAL_TIM_OC_MspDeInit:0000000000000000 HAL_TIM_OC_MspDeInit + /tmp/ccH6KUTS.s:1058 .text.HAL_TIM_OC_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:1065 .text.HAL_TIM_OC_DeInit:0000000000000000 HAL_TIM_OC_DeInit + /tmp/ccH6KUTS.s:1114 .text.HAL_TIM_OC_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:1119 .text.HAL_TIM_OC_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:1126 .text.HAL_TIM_OC_Start:0000000000000000 HAL_TIM_OC_Start + /tmp/ccH6KUTS.s:1175 .text.HAL_TIM_OC_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:1182 .text.HAL_TIM_OC_Stop:0000000000000000 HAL_TIM_OC_Stop + /tmp/ccH6KUTS.s:1230 .text.HAL_TIM_OC_Stop:0000000000000028 $d + /tmp/ccH6KUTS.s:1235 .text.HAL_TIM_OC_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:1242 .text.HAL_TIM_OC_Start_IT:0000000000000000 HAL_TIM_OC_Start_IT + /tmp/ccH6KUTS.s:1337 .text.HAL_TIM_OC_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:1344 .text.HAL_TIM_OC_Stop_IT:0000000000000000 HAL_TIM_OC_Stop_IT + /tmp/ccH6KUTS.s:1442 .text.HAL_TIM_OC_Stop_IT:000000000000006c $d + ARM GAS /tmp/ccH6KUTS.s page 274 + + + /tmp/ccH6KUTS.s:1447 .text.HAL_TIM_OC_Start_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:1454 .text.HAL_TIM_OC_Start_DMA:0000000000000000 HAL_TIM_OC_Start_DMA + /tmp/ccH6KUTS.s:1659 .text.HAL_TIM_OC_Start_DMA:00000000000000f4 $d + /tmp/ccH6KUTS.s:8606 .text.TIM_DMADelayPulseCplt:0000000000000000 TIM_DMADelayPulseCplt + /tmp/ccH6KUTS.s:1665 .text.HAL_TIM_OC_Stop_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:1672 .text.HAL_TIM_OC_Stop_DMA:0000000000000000 HAL_TIM_OC_Stop_DMA + /tmp/ccH6KUTS.s:1774 .text.HAL_TIM_OC_Stop_DMA:0000000000000070 $d + /tmp/ccH6KUTS.s:1783 .text.HAL_TIM_PWM_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:1790 .text.HAL_TIM_PWM_MspInit:0000000000000000 HAL_TIM_PWM_MspInit + /tmp/ccH6KUTS.s:1805 .text.HAL_TIM_PWM_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:1812 .text.HAL_TIM_PWM_Init:0000000000000000 HAL_TIM_PWM_Init + /tmp/ccH6KUTS.s:1875 .text.HAL_TIM_PWM_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:1882 .text.HAL_TIM_PWM_MspDeInit:0000000000000000 HAL_TIM_PWM_MspDeInit + /tmp/ccH6KUTS.s:1897 .text.HAL_TIM_PWM_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:1904 .text.HAL_TIM_PWM_DeInit:0000000000000000 HAL_TIM_PWM_DeInit + /tmp/ccH6KUTS.s:1953 .text.HAL_TIM_PWM_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:1958 .text.HAL_TIM_PWM_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:1965 .text.HAL_TIM_PWM_Start:0000000000000000 HAL_TIM_PWM_Start + /tmp/ccH6KUTS.s:2014 .text.HAL_TIM_PWM_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:2021 .text.HAL_TIM_PWM_Stop:0000000000000000 HAL_TIM_PWM_Stop + /tmp/ccH6KUTS.s:2073 .text.HAL_TIM_PWM_Stop:0000000000000030 $d + /tmp/ccH6KUTS.s:2078 .text.HAL_TIM_PWM_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:2085 .text.HAL_TIM_PWM_Start_IT:0000000000000000 HAL_TIM_PWM_Start_IT + /tmp/ccH6KUTS.s:2180 .text.HAL_TIM_PWM_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:2187 .text.HAL_TIM_PWM_Stop_IT:0000000000000000 HAL_TIM_PWM_Stop_IT + /tmp/ccH6KUTS.s:2285 .text.HAL_TIM_PWM_Stop_IT:000000000000006c $d + /tmp/ccH6KUTS.s:2290 .text.HAL_TIM_PWM_Start_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:2297 .text.HAL_TIM_PWM_Start_DMA:0000000000000000 HAL_TIM_PWM_Start_DMA + /tmp/ccH6KUTS.s:2502 .text.HAL_TIM_PWM_Start_DMA:00000000000000f4 $d + /tmp/ccH6KUTS.s:2508 .text.HAL_TIM_PWM_Stop_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:2515 .text.HAL_TIM_PWM_Stop_DMA:0000000000000000 HAL_TIM_PWM_Stop_DMA + /tmp/ccH6KUTS.s:2617 .text.HAL_TIM_PWM_Stop_DMA:0000000000000070 $d + /tmp/ccH6KUTS.s:2626 .text.HAL_TIM_IC_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:2633 .text.HAL_TIM_IC_MspInit:0000000000000000 HAL_TIM_IC_MspInit + /tmp/ccH6KUTS.s:2648 .text.HAL_TIM_IC_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:2655 .text.HAL_TIM_IC_Init:0000000000000000 HAL_TIM_IC_Init + /tmp/ccH6KUTS.s:2718 .text.HAL_TIM_IC_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:2725 .text.HAL_TIM_IC_MspDeInit:0000000000000000 HAL_TIM_IC_MspDeInit + /tmp/ccH6KUTS.s:2740 .text.HAL_TIM_IC_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:2747 .text.HAL_TIM_IC_DeInit:0000000000000000 HAL_TIM_IC_DeInit + /tmp/ccH6KUTS.s:2796 .text.HAL_TIM_IC_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:2801 .text.HAL_TIM_IC_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:2808 .text.HAL_TIM_IC_Start:0000000000000000 HAL_TIM_IC_Start + /tmp/ccH6KUTS.s:2857 .text.HAL_TIM_IC_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:2864 .text.HAL_TIM_IC_Stop:0000000000000000 HAL_TIM_IC_Stop + /tmp/ccH6KUTS.s:2912 .text.HAL_TIM_IC_Stop:0000000000000028 $d + /tmp/ccH6KUTS.s:2917 .text.HAL_TIM_IC_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:2924 .text.HAL_TIM_IC_Start_IT:0000000000000000 HAL_TIM_IC_Start_IT + /tmp/ccH6KUTS.s:3019 .text.HAL_TIM_IC_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:3026 .text.HAL_TIM_IC_Stop_IT:0000000000000000 HAL_TIM_IC_Stop_IT + /tmp/ccH6KUTS.s:3124 .text.HAL_TIM_IC_Stop_IT:000000000000006c $d + /tmp/ccH6KUTS.s:3129 .text.HAL_TIM_IC_Start_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:3136 .text.HAL_TIM_IC_Start_DMA:0000000000000000 HAL_TIM_IC_Start_DMA + /tmp/ccH6KUTS.s:3339 .text.HAL_TIM_IC_Start_DMA:00000000000000f0 $d + /tmp/ccH6KUTS.s:8506 .text.TIM_DMACaptureCplt:0000000000000000 TIM_DMACaptureCplt + /tmp/ccH6KUTS.s:3345 .text.HAL_TIM_IC_Stop_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:3352 .text.HAL_TIM_IC_Stop_DMA:0000000000000000 HAL_TIM_IC_Stop_DMA + ARM GAS /tmp/ccH6KUTS.s page 275 + + + /tmp/ccH6KUTS.s:3454 .text.HAL_TIM_IC_Stop_DMA:0000000000000070 $d + /tmp/ccH6KUTS.s:3463 .text.HAL_TIM_OnePulse_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:3470 .text.HAL_TIM_OnePulse_MspInit:0000000000000000 HAL_TIM_OnePulse_MspInit + /tmp/ccH6KUTS.s:3485 .text.HAL_TIM_OnePulse_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:3492 .text.HAL_TIM_OnePulse_Init:0000000000000000 HAL_TIM_OnePulse_Init + /tmp/ccH6KUTS.s:3569 .text.HAL_TIM_OnePulse_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:3576 .text.HAL_TIM_OnePulse_MspDeInit:0000000000000000 HAL_TIM_OnePulse_MspDeInit + /tmp/ccH6KUTS.s:3591 .text.HAL_TIM_OnePulse_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:3598 .text.HAL_TIM_OnePulse_DeInit:0000000000000000 HAL_TIM_OnePulse_DeInit + /tmp/ccH6KUTS.s:3647 .text.HAL_TIM_OnePulse_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:3652 .text.HAL_TIM_OnePulse_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:3659 .text.HAL_TIM_OnePulse_Start:0000000000000000 HAL_TIM_OnePulse_Start + /tmp/ccH6KUTS.s:3715 .text.HAL_TIM_OnePulse_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:3722 .text.HAL_TIM_OnePulse_Stop:0000000000000000 HAL_TIM_OnePulse_Stop + /tmp/ccH6KUTS.s:3783 .text.HAL_TIM_OnePulse_Stop:0000000000000034 $d + /tmp/ccH6KUTS.s:3788 .text.HAL_TIM_OnePulse_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:3795 .text.HAL_TIM_OnePulse_Start_IT:0000000000000000 HAL_TIM_OnePulse_Start_IT + /tmp/ccH6KUTS.s:3863 .text.HAL_TIM_OnePulse_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:3870 .text.HAL_TIM_OnePulse_Stop_IT:0000000000000000 HAL_TIM_OnePulse_Stop_IT + /tmp/ccH6KUTS.s:3943 .text.HAL_TIM_OnePulse_Stop_IT:0000000000000048 $d + /tmp/ccH6KUTS.s:3948 .text.HAL_TIM_Encoder_MspInit:0000000000000000 $t + /tmp/ccH6KUTS.s:3955 .text.HAL_TIM_Encoder_MspInit:0000000000000000 HAL_TIM_Encoder_MspInit + /tmp/ccH6KUTS.s:3970 .text.HAL_TIM_Encoder_Init:0000000000000000 $t + /tmp/ccH6KUTS.s:3977 .text.HAL_TIM_Encoder_Init:0000000000000000 HAL_TIM_Encoder_Init + /tmp/ccH6KUTS.s:4127 .text.HAL_TIM_Encoder_Init:000000000000009c $d + /tmp/ccH6KUTS.s:4133 .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:4140 .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 HAL_TIM_Encoder_MspDeInit + /tmp/ccH6KUTS.s:4155 .text.HAL_TIM_Encoder_DeInit:0000000000000000 $t + /tmp/ccH6KUTS.s:4162 .text.HAL_TIM_Encoder_DeInit:0000000000000000 HAL_TIM_Encoder_DeInit + /tmp/ccH6KUTS.s:4211 .text.HAL_TIM_Encoder_DeInit:0000000000000030 $d + /tmp/ccH6KUTS.s:4216 .text.HAL_TIM_Encoder_Start:0000000000000000 $t + /tmp/ccH6KUTS.s:4223 .text.HAL_TIM_Encoder_Start:0000000000000000 HAL_TIM_Encoder_Start + /tmp/ccH6KUTS.s:4331 .text.HAL_TIM_Encoder_Stop:0000000000000000 $t + /tmp/ccH6KUTS.s:4338 .text.HAL_TIM_Encoder_Stop:0000000000000000 HAL_TIM_Encoder_Stop + /tmp/ccH6KUTS.s:4441 .text.HAL_TIM_Encoder_Stop:000000000000005c $d + /tmp/ccH6KUTS.s:4448 .text.HAL_TIM_Encoder_Start_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:4455 .text.HAL_TIM_Encoder_Start_IT:0000000000000000 HAL_TIM_Encoder_Start_IT + /tmp/ccH6KUTS.s:4591 .text.HAL_TIM_Encoder_Stop_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:4598 .text.HAL_TIM_Encoder_Stop_IT:0000000000000000 HAL_TIM_Encoder_Stop_IT + /tmp/ccH6KUTS.s:4737 .text.HAL_TIM_Encoder_Stop_IT:0000000000000088 $d + /tmp/ccH6KUTS.s:4742 .text.HAL_TIM_Encoder_Start_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:4749 .text.HAL_TIM_Encoder_Start_DMA:0000000000000000 HAL_TIM_Encoder_Start_DMA + /tmp/ccH6KUTS.s:5030 .text.HAL_TIM_Encoder_Start_DMA:000000000000014c $d + /tmp/ccH6KUTS.s:5036 .text.HAL_TIM_Encoder_Stop_DMA:0000000000000000 $t + /tmp/ccH6KUTS.s:5043 .text.HAL_TIM_Encoder_Stop_DMA:0000000000000000 HAL_TIM_Encoder_Stop_DMA + /tmp/ccH6KUTS.s:5181 .text.HAL_TIM_Encoder_Stop_DMA:0000000000000088 $d + /tmp/ccH6KUTS.s:5188 .text.HAL_TIM_OC_ConfigChannel:0000000000000000 $t + /tmp/ccH6KUTS.s:5195 .text.HAL_TIM_OC_ConfigChannel:0000000000000000 HAL_TIM_OC_ConfigChannel + /tmp/ccH6KUTS.s:5467 .text.HAL_TIM_OC_ConfigChannel:00000000000000f8 $d + /tmp/ccH6KUTS.s:5476 .text.HAL_TIM_IC_ConfigChannel:0000000000000000 $t + /tmp/ccH6KUTS.s:5483 .text.HAL_TIM_IC_ConfigChannel:0000000000000000 HAL_TIM_IC_ConfigChannel + /tmp/ccH6KUTS.s:5824 .text.HAL_TIM_IC_ConfigChannel:000000000000016c $d + /tmp/ccH6KUTS.s:5835 .text.HAL_TIM_PWM_ConfigChannel:0000000000000000 $t + /tmp/ccH6KUTS.s:5842 .text.HAL_TIM_PWM_ConfigChannel:0000000000000000 HAL_TIM_PWM_ConfigChannel + /tmp/ccH6KUTS.s:6204 .text.HAL_TIM_PWM_ConfigChannel:0000000000000178 $d + /tmp/ccH6KUTS.s:6214 .text.HAL_TIM_OnePulse_ConfigChannel:0000000000000000 $t + /tmp/ccH6KUTS.s:6221 .text.HAL_TIM_OnePulse_ConfigChannel:0000000000000000 HAL_TIM_OnePulse_ConfigChannel + ARM GAS /tmp/ccH6KUTS.s page 276 + + + /tmp/ccH6KUTS.s:6578 .text.HAL_TIM_OnePulse_ConfigChannel:0000000000000180 $d + /tmp/ccH6KUTS.s:6586 .text.HAL_TIM_DMABurst_WriteStart:0000000000000000 $t + /tmp/ccH6KUTS.s:6593 .text.HAL_TIM_DMABurst_WriteStart:0000000000000000 HAL_TIM_DMABurst_WriteStart + /tmp/ccH6KUTS.s:6839 .text.HAL_TIM_DMABurst_WriteStart:0000000000000138 $d + /tmp/ccH6KUTS.s:8937 .text.TIM_DMATriggerCplt:0000000000000000 TIM_DMATriggerCplt + /tmp/ccH6KUTS.s:6847 .text.HAL_TIM_DMABurst_WriteStop:0000000000000000 $t + /tmp/ccH6KUTS.s:6854 .text.HAL_TIM_DMABurst_WriteStop:0000000000000000 HAL_TIM_DMABurst_WriteStop + /tmp/ccH6KUTS.s:6963 .text.HAL_TIM_DMABurst_ReadStart:0000000000000000 $t + /tmp/ccH6KUTS.s:6970 .text.HAL_TIM_DMABurst_ReadStart:0000000000000000 HAL_TIM_DMABurst_ReadStart + /tmp/ccH6KUTS.s:7216 .text.HAL_TIM_DMABurst_ReadStart:0000000000000138 $d + /tmp/ccH6KUTS.s:7224 .text.HAL_TIM_DMABurst_ReadStop:0000000000000000 $t + /tmp/ccH6KUTS.s:7231 .text.HAL_TIM_DMABurst_ReadStop:0000000000000000 HAL_TIM_DMABurst_ReadStop + /tmp/ccH6KUTS.s:7340 .text.HAL_TIM_GenerateEvent:0000000000000000 $t + /tmp/ccH6KUTS.s:7347 .text.HAL_TIM_GenerateEvent:0000000000000000 HAL_TIM_GenerateEvent + /tmp/ccH6KUTS.s:7391 .text.HAL_TIM_ConfigOCrefClear:0000000000000000 $t + /tmp/ccH6KUTS.s:7398 .text.HAL_TIM_ConfigOCrefClear:0000000000000000 HAL_TIM_ConfigOCrefClear + /tmp/ccH6KUTS.s:7603 .text.HAL_TIM_ConfigOCrefClear:00000000000000e0 $d + /tmp/ccH6KUTS.s:7609 .text.HAL_TIM_ConfigClockSource:0000000000000000 $t + /tmp/ccH6KUTS.s:7616 .text.HAL_TIM_ConfigClockSource:0000000000000000 HAL_TIM_ConfigClockSource + /tmp/ccH6KUTS.s:8109 .text.HAL_TIM_ConfigClockSource:00000000000001ac $d + /tmp/ccH6KUTS.s:8116 .text.HAL_TIM_ConfigTI1Input:0000000000000000 $t + /tmp/ccH6KUTS.s:8123 .text.HAL_TIM_ConfigTI1Input:0000000000000000 HAL_TIM_ConfigTI1Input + /tmp/ccH6KUTS.s:8153 .text.HAL_TIM_SlaveConfigSynchronization:0000000000000000 $t + /tmp/ccH6KUTS.s:8160 .text.HAL_TIM_SlaveConfigSynchronization:0000000000000000 HAL_TIM_SlaveConfigSynchronization + /tmp/ccH6KUTS.s:8226 .text.HAL_TIM_SlaveConfigSynchronization:0000000000000040 $d + /tmp/ccH6KUTS.s:8231 .text.HAL_TIM_SlaveConfigSynchronization_IT:0000000000000000 $t + /tmp/ccH6KUTS.s:8238 .text.HAL_TIM_SlaveConfigSynchronization_IT:0000000000000000 HAL_TIM_SlaveConfigSynchronization_IT + /tmp/ccH6KUTS.s:8304 .text.HAL_TIM_SlaveConfigSynchronization_IT:0000000000000040 $d + /tmp/ccH6KUTS.s:8309 .text.HAL_TIM_ReadCapturedValue:0000000000000000 $t + /tmp/ccH6KUTS.s:8316 .text.HAL_TIM_ReadCapturedValue:0000000000000000 HAL_TIM_ReadCapturedValue + /tmp/ccH6KUTS.s:8398 .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8405 .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 HAL_TIM_PeriodElapsedCallback + /tmp/ccH6KUTS.s:8420 .text.TIM_DMAPeriodElapsedCplt:0000000000000000 $t + /tmp/ccH6KUTS.s:8455 .text.HAL_TIM_OC_DelayElapsedCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8462 .text.HAL_TIM_OC_DelayElapsedCallback:0000000000000000 HAL_TIM_OC_DelayElapsedCallback + /tmp/ccH6KUTS.s:8477 .text.HAL_TIM_IC_CaptureCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8484 .text.HAL_TIM_IC_CaptureCallback:0000000000000000 HAL_TIM_IC_CaptureCallback + /tmp/ccH6KUTS.s:8499 .text.TIM_DMACaptureCplt:0000000000000000 $t + /tmp/ccH6KUTS.s:8577 .text.HAL_TIM_PWM_PulseFinishedCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8584 .text.HAL_TIM_PWM_PulseFinishedCallback:0000000000000000 HAL_TIM_PWM_PulseFinishedCallback + /tmp/ccH6KUTS.s:8599 .text.TIM_DMADelayPulseCplt:0000000000000000 $t + /tmp/ccH6KUTS.s:8677 .text.HAL_TIM_TriggerCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8684 .text.HAL_TIM_TriggerCallback:0000000000000000 HAL_TIM_TriggerCallback + /tmp/ccH6KUTS.s:8699 .text.HAL_TIM_IRQHandler:0000000000000000 $t + /tmp/ccH6KUTS.s:8706 .text.HAL_TIM_IRQHandler:0000000000000000 HAL_TIM_IRQHandler + /tmp/ccH6KUTS.s:8931 .text.TIM_DMATriggerCplt:0000000000000000 $t + /tmp/ccH6KUTS.s:8966 .text.HAL_TIM_ErrorCallback:0000000000000000 $t + /tmp/ccH6KUTS.s:8973 .text.HAL_TIM_ErrorCallback:0000000000000000 HAL_TIM_ErrorCallback + /tmp/ccH6KUTS.s:8988 .text.TIM_DMAError:0000000000000000 $t + /tmp/ccH6KUTS.s:9024 .text.HAL_TIM_Base_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9031 .text.HAL_TIM_Base_GetState:0000000000000000 HAL_TIM_Base_GetState + /tmp/ccH6KUTS.s:9051 .text.HAL_TIM_OC_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9058 .text.HAL_TIM_OC_GetState:0000000000000000 HAL_TIM_OC_GetState + /tmp/ccH6KUTS.s:9078 .text.HAL_TIM_PWM_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9085 .text.HAL_TIM_PWM_GetState:0000000000000000 HAL_TIM_PWM_GetState + /tmp/ccH6KUTS.s:9105 .text.HAL_TIM_IC_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9112 .text.HAL_TIM_IC_GetState:0000000000000000 HAL_TIM_IC_GetState + ARM GAS /tmp/ccH6KUTS.s page 277 + + + /tmp/ccH6KUTS.s:9132 .text.HAL_TIM_OnePulse_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9139 .text.HAL_TIM_OnePulse_GetState:0000000000000000 HAL_TIM_OnePulse_GetState + /tmp/ccH6KUTS.s:9159 .text.HAL_TIM_Encoder_GetState:0000000000000000 $t + /tmp/ccH6KUTS.s:9166 .text.HAL_TIM_Encoder_GetState:0000000000000000 HAL_TIM_Encoder_GetState + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort diff --git a/build/stm32l0xx_hal_tim_ex.d b/build/stm32l0xx_hal_tim_ex.d new file mode 100644 index 0000000..9d9caba --- /dev/null +++ b/build/stm32l0xx_hal_tim_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_tim_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_tim_ex.lst b/build/stm32l0xx_hal_tim_ex.lst new file mode 100644 index 0000000..2fca158 --- /dev/null +++ b/build/stm32l0xx_hal_tim_ex.lst @@ -0,0 +1,648 @@ +ARM GAS /tmp/ccbYH3Zs.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_tim_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_TIMEx_MasterConfigSynchronization,"ax",%progbits + 16 .align 1 + 17 .global HAL_TIMEx_MasterConfigSynchronization + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_TIMEx_MasterConfigSynchronization: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @file stm32l0xx_hal_tim_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief TIM HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * functionalities of the Timer (TIM) peripheral: + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Initialization + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Start + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + Time Master and Slave synchronization configuration + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** @verbatim + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ================================================================================ + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ##### TIM specific features integration ##### + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ================================================================================ + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** [..] The Timer features include: + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) 16-bit up, down, up/down auto-reload counter. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** frequency either by any factor between 1 and 65536. + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Up to 4 independent channels for: + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** Input Capture + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** Output Compare + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** PWM generation (Edge and Center-aligned Mode) + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** One-pulse mode output + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Synchronization circuit to control the timer with external signals and to interconnect + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** several timers together. + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** purposes + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ##### How to use this driver ##### + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ================================================================================ + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** [..] + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Enable the TIM interface clock using + ARM GAS /tmp/ccbYH3Zs.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_RCC_TIMx_CLK_ENABLE(); + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) TIM pins configuration + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (++) Enable the clock for the TIM GPIOs using the following function: + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) The external Clock can be configured, if needed (the default clock is the internal clock f + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** using the following function: + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before any start functio + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Configure the TIM in the desired operating mode using one of the + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** configuration function of this driver: + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (++) HAL_TIMEx_MasterConfigSynchronization() to configure the peripheral in master mode. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (#) Remap the Timer I/O using HAL_TIMEx_RemapConfig() API. + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** @endverbatim + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ****************************************************************************** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @attention + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * are permitted provided that the following conditions are met: + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * this list of conditions and the following disclaimer. + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * this list of conditions and the following disclaimer in the documentation + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * and/or other materials provided with the distribution. + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * may be used to endorse or promote products derived from this software + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * without specific prior written permission. + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ****************************************************************************** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Includes ------------------------------------------------------------------*/ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #include "stm32l0xx_hal.h" + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @{ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** @addtogroup TIMEx + ARM GAS /tmp/ccbYH3Zs.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief TIMEx HAL module driver + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @{ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #ifdef HAL_TIM_MODULE_ENABLED + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** @addtogroup TIMEx_Exported_Functions + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @{ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** @addtogroup TIMEx_Exported_Functions_Group1 + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Peripheral Control functions + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** @verbatim + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** =============================================================================== + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** ##### Peripheral Control functions ##### + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** =============================================================================== + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** [..] This section provides functions allowing to: + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** (+) Configure Master and the Slave synchronization. + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** @endverbatim + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @{ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Configures the TIM in master mode. + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param htim: TIM handle. + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * contains the selected trigger output (TRGO) and the Master/Slave + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * mode. + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @retval HAL status + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTy + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** { + 26 .loc 1 126 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F0B5 push {r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 20 + 34 .cfi_offset 4, -20 + 35 .cfi_offset 5, -16 + 36 .cfi_offset 6, -12 + 37 .cfi_offset 7, -8 + 38 .cfi_offset 14, -4 + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Check the parameters */ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 39 .loc 1 132 0 + 40 0002 3423 movs r3, #52 + ARM GAS /tmp/ccbYH3Zs.s page 4 + + + 41 0004 C35C ldrb r3, [r0, r3] + 42 0006 012B cmp r3, #1 + 43 0008 1ED0 beq .L3 + 44 .loc 1 132 0 is_stmt 0 discriminator 2 + 45 000a 3422 movs r2, #52 + 46 000c 0125 movs r5, #1 + 47 000e 8554 strb r5, [r0, r2] + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Change the handler state */ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 48 .loc 1 135 0 is_stmt 1 discriminator 2 + 49 0010 3524 movs r4, #53 + 50 0012 0223 movs r3, #2 + 51 0014 0355 strb r3, [r0, r4] + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Reset the MMS Bits */ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_MMS; + 52 .loc 1 138 0 discriminator 2 + 53 0016 0668 ldr r6, [r0] + 54 0018 7368 ldr r3, [r6, #4] + 55 001a 7027 movs r7, #112 + 56 001c BB43 bics r3, r7 + 57 001e 7360 str r3, [r6, #4] + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Select the TRGO source */ + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; + 58 .loc 1 140 0 discriminator 2 + 59 0020 0668 ldr r6, [r0] + 60 0022 7368 ldr r3, [r6, #4] + 61 0024 0F68 ldr r7, [r1] + 62 0026 3B43 orrs r3, r7 + 63 0028 7360 str r3, [r6, #4] + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Reset the MSM Bit */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_MSM; + 64 .loc 1 143 0 discriminator 2 + 65 002a 0668 ldr r6, [r0] + 66 002c B368 ldr r3, [r6, #8] + 67 002e 8027 movs r7, #128 + 68 0030 BB43 bics r3, r7 + 69 0032 B360 str r3, [r6, #8] + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Set or Reset the MSM Bit */ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; + 70 .loc 1 145 0 discriminator 2 + 71 0034 0668 ldr r6, [r0] + 72 0036 B368 ldr r3, [r6, #8] + 73 0038 4968 ldr r1, [r1, #4] + 74 .LVL1: + 75 003a 0B43 orrs r3, r1 + 76 003c B360 str r3, [r6, #8] + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 77 .loc 1 147 0 discriminator 2 + 78 003e 0555 strb r5, [r0, r4] + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 79 .loc 1 149 0 discriminator 2 + 80 0040 0023 movs r3, #0 + ARM GAS /tmp/ccbYH3Zs.s page 5 + + + 81 0042 8354 strb r3, [r0, r2] + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** return HAL_OK; + 82 .loc 1 151 0 discriminator 2 + 83 0044 0020 movs r0, #0 + 84 .LVL2: + 85 .L2: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** } + 86 .loc 1 152 0 + 87 @ sp needed + 88 0046 F0BD pop {r4, r5, r6, r7, pc} + 89 .LVL3: + 90 .L3: + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 91 .loc 1 132 0 + 92 0048 0220 movs r0, #2 + 93 .LVL4: + 94 004a FCE7 b .L2 + 95 .cfi_endproc + 96 .LFE39: + 98 .section .text.HAL_TIMEx_RemapConfig,"ax",%progbits + 99 .align 1 + 100 .global HAL_TIMEx_RemapConfig + 101 .syntax unified + 102 .code 16 + 103 .thumb_func + 104 .fpu softvfp + 106 HAL_TIMEx_RemapConfig: + 107 .LFB40: + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Configures the remapping of the TIM2, TIM3, TIM21 and TIM22 inputs. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * The channel inputs (T1..T4) and the Trigger input (ETR) of the + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * timers can be remaped thanks to this function. When an input is + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * mapped, on a GPIO, refer yourself to the GPIO alternate functions + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * for more details. + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @note It is not possible to connect TIM2 and TIM21 on + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB5_AF4 at the same time. + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * connected to GPIOB5_AF4 and Channel2 of TIM22 will be connected to + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * some other GPIOs. (refer to alternate functions for more details) + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * connected an GPIO (other than GPIOB5_AF4) and Channel2 of TIM22 + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * will be connected to GPIOB5_AF4. + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param htim: pointer to a TIM_HandleTypeDef structure that contains + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * the configuration information for TIM module. + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param Remap: specifies the TIM input remapping source. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * This parameter is a combination of the following values + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * depending on TIM instance: + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM2, the parameter can have the following values: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + ARM GAS /tmp/ccbYH3Zs.s page 6 + + + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(15)_AF2 or GPIOE(9)_AF2 + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HSI16 + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO1(default): + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(12)_AF0 + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM3, the parameter can have the following values: + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_ETR_GPIO: TIM3 ETR connected to GPIO (default): + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(2)_AF2 or GPIOD(2)_AF2 or + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(2)AF2 + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_ETR_HSI: TIM3 ETR connected to HSI + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI1_USB_SOF: TIM3 TI1 connected to USB_SOF (default) + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI1_GPIO: TIM3 TI1 connected to GPIO : + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(3)_AF2 or GPIOA(6)_AF2 or + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(6)_AF2 or GPIOB(4)_AF2 + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to GPIOB(5)_AF4 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * (refer to note) + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI2_GPIO_DEF: TIM3 TI3 connected to GPIO (default): + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIO_A(7)_AF2 or GPIO_B(5)_AF4 or + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(7)_AF2 or GPIOE(7)_AF2 + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI4_GPIO_DEF: TIM3 TI4 connected to GPIO: + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIO_B(1)_AF2 or GPIO_E(6)_AF2 + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to GPIOC(9)_AF2 + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM21, the parameter can have the following values: + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * APB2_PC(9)_AF0 or APB2_PA(1)_AF5 + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(2)_AF0 or GPIOB(13)_AF6 or + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(5)_AF0 or GPIOD(0)_AF0 + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF0 or GPIOB(14)_AF6 or + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(6)_AF0 or GPIOD(7)_AF1 + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM22, the parameter can have the following values: + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + ARM GAS /tmp/ccbYH3Zs.s page 7 + + + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(8)_AF0 or GPIOA(4)_AF5 + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(4)_AF4 or GPIOE(0)_AF3 + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(4)_AF4 or GPIOE(3)_AF0 + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @retval HAL status + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #elif defined (STM32L031xx) || defined (STM32L041xx) + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * The channel inputs (T1..T4) and the Trigger input (ETR) of the + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * timers can be remaped thanks to this function. When an input is + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * mapped, on a GPIO, refer yourself to the GPIO alternate functions + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * for more details. + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param htim: pointer to a TIM_HandleTypeDef structure that contains + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * the configuration information for TIM module. + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param Remap: specifies the TIM input remapping source. + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * This parameter is a combination of the following values + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * depending on TIM instance: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM2, the parameter can have the following values: + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(15)_AF2 + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(1)_AF5 + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM21, the parameter can have the following values: + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * APB2_PA(1)_AF5 + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF0 or GPIOB(14)_AF6 + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + ARM GAS /tmp/ccbYH3Zs.s page 8 + + + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM22, the parameter can have the following values: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(4)_AF5 + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(0)_AF6 or GPIOA(5)_AF6 or + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(4)_AF4 + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(6)_AF5 or GPIOB(4)_AF4 + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @retval HAL status + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #elif defined (STM32L011xx) || defined (STM32L021xx) + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Configures the remapping of the TIM2 and TIM21 inputs. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * The channel inputs (T1..T4) and the Trigger input (ETR) of the + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * timers can be remaped thanks to this function. When an input is + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * mapped, on a GPIO, refer yourself to the GPIO alternate functions + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * for more details. + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param htim: pointer to a TIM_HandleTypeDef structure that contains + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * the configuration information for TIM module. + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param Remap: specifies the TIM input remapping source. + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * This parameter is a combination of the following values + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * depending on TIM instance: + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM2, the parameter can have the following values: + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(15)_AF2 + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(1)_AF5 + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM21, the parameter can have the following values: + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * APB2_PA(1)_AF5 + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + ARM GAS /tmp/ccbYH3Zs.s page 9 + + + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF0 or GPIOB(14)_AF6 + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @retval HAL status + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #else + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /** + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * The channel inputs (T1..T4) and the Trigger input (ETR) of the + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * timers can be remaped thanks to this function. When an input is + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * mapped, on a GPIO, refer yourself to the GPIO alternate functions + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * for more details. + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param htim: pointer to a TIM_HandleTypeDef structure that contains + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * the configuration information for TIM module. + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @param Remap: specifies the TIM input remapping source. + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * This parameter is a combination of the following values + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * depending on TIM instance: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM2, the parameter can have the following values: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(15)_AF2 or GPIOE(9)_AF2 + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_GPIO: TIM2 TI4 connected to GPIO1(default): + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(12)_AF0 + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM2_TI4_GPIO2: TIM2 TI4 connected to GPIO2 : + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(12)_AF0 + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM21, the parameter can have the following values: + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * APB2_PC(9)_AF0 or APB2_PA(1)_AF5 + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(2)_AF0 or GPIOB(13)_AF6 or + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(5)_AF0 or GPIOD(0)_AF0 + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOA(3)_AF0 or GPIOB(14)_AF6 or + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOE(6)_AF0 or GPIOD(7)_AF1 + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + ARM GAS /tmp/ccbYH3Zs.s page 10 + + + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * For TIM22, the parameter can have the following values: + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(8)_AF0 or GPIOA(4)_AF5 + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(4)_AF4 or GPIOE(0)_AF3 + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * GPIOB(4)_AF4 or GPIOE(3)_AF0 + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** * @retval HAL status + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** #endif /* STM32L07xxx or STM32L08xxx */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** { + 108 .loc 1 431 0 + 109 .cfi_startproc + 110 @ args = 0, pretend = 0, frame = 0 + 111 @ frame_needed = 0, uses_anonymous_args = 0 + 112 @ link register save eliminated. + 113 .LVL5: + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 114 .loc 1 433 0 + 115 0000 3423 movs r3, #52 + 116 0002 C35C ldrb r3, [r0, r3] + 117 0004 012B cmp r3, #1 + 118 0006 09D0 beq .L6 + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Check parameters */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** assert_param(IS_TIM_REMAP(htim->Instance,Remap)); + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** /* Set the Timer remapping configuration */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->Instance->OR = Remap; + 119 .loc 1 439 0 discriminator 2 + 120 0008 0368 ldr r3, [r0] + 121 000a 1965 str r1, [r3, #80] + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 122 .loc 1 441 0 discriminator 2 + 123 000c 3523 movs r3, #53 + 124 000e 0122 movs r2, #1 + 125 0010 C254 strb r2, [r0, r3] + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 126 .loc 1 443 0 discriminator 2 + 127 0012 013B subs r3, r3, #1 + 128 0014 0022 movs r2, #0 + 129 0016 C254 strb r2, [r0, r3] + ARM GAS /tmp/ccbYH3Zs.s page 11 + + + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** return HAL_OK; + 130 .loc 1 445 0 discriminator 2 + 131 0018 0020 movs r0, #0 + 132 .LVL6: + 133 .L5: + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** } + 134 .loc 1 446 0 + 135 @ sp needed + 136 001a 7047 bx lr + 137 .LVL7: + 138 .L6: + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c **** + 139 .loc 1 433 0 + 140 001c 0220 movs r0, #2 + 141 .LVL8: + 142 001e FCE7 b .L5 + 143 .cfi_endproc + 144 .LFE40: + 146 .text + 147 .Letext0: + 148 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 149 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 150 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 151 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 152 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 153 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 154 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 155 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 156 .file 10 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 157 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 158 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h" + 159 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h" + ARM GAS /tmp/ccbYH3Zs.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_tim_ex.c + /tmp/ccbYH3Zs.s:16 .text.HAL_TIMEx_MasterConfigSynchronization:0000000000000000 $t + /tmp/ccbYH3Zs.s:23 .text.HAL_TIMEx_MasterConfigSynchronization:0000000000000000 HAL_TIMEx_MasterConfigSynchronization + /tmp/ccbYH3Zs.s:99 .text.HAL_TIMEx_RemapConfig:0000000000000000 $t + /tmp/ccbYH3Zs.s:106 .text.HAL_TIMEx_RemapConfig:0000000000000000 HAL_TIMEx_RemapConfig + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_tsc.d b/build/stm32l0xx_hal_tsc.d new file mode 100644 index 0000000..2ced6c8 --- /dev/null +++ b/build/stm32l0xx_hal_tsc.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_tsc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_tsc.lst b/build/stm32l0xx_hal_tsc.lst new file mode 100644 index 0000000..9068489 --- /dev/null +++ b/build/stm32l0xx_hal_tsc.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/ccOGPNPz.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_tsc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccOGPNPz.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_tsc.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_uart.d b/build/stm32l0xx_hal_uart.d new file mode 100644 index 0000000..b4de1cd --- /dev/null +++ b/build/stm32l0xx_hal_uart.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_uart.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_uart.lst b/build/stm32l0xx_hal_uart.lst new file mode 100644 index 0000000..3f27c5d --- /dev/null +++ b/build/stm32l0xx_hal_uart.lst @@ -0,0 +1,9536 @@ +ARM GAS /tmp/cc7An1gz.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_uart.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_UART_MspInit,"ax",%progbits + 16 .align 1 + 17 .weak HAL_UART_MspInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_UART_MspInit: + 24 .LFB44: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @file stm32l0xx_hal_uart.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This file provides firmware functions to manage the following + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + IO operation functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + Peripheral Control functions + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @verbatim + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ##### How to use this driver ##### + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The UART HAL driver can be used as follows: + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Enable the USARTx interface clock. + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) UART pins configuration: + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Enable the clock for the UART GPIOs. + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Configure these UART pins as alternate function pull-up. + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and HAL_UART_Receive_IT() APIs): + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Configure the USARTx interrupt priority. + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Enable the NVIC USART IRQ handle. + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) UART interrupts handling: + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** -@@- The specific UART interrupts (Transmission complete interrupt, + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** RXNE interrupt and Error Interrupts) are managed using the macros + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive + ARM GAS /tmp/cc7An1gz.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and HAL_UART_Receive_DMA() APIs): + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Declare a DMA handle structure for the Tx/Rx channel. + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Enable the DMAx interface clock. + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Configure the DMA Tx/Rx channel. + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the huart handle AdvancedInit structure. + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For the UART asynchronous mode, initialize the UART registers by calling + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_Init() API. + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For the UART Half duplex mode, initialize the UART registers by calling + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_HalfDuplex_Init() API. + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** by calling the HAL_LIN_Init() API. + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For the UART Multiprocessor mode, initialize the UART registers + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** by calling the HAL_MultiProcessor_Init() API. + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** by calling the HAL_RS485Ex_Init() API. + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Ini + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** calling the customized HAL_UART_MspInit() API. + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @endverbatim + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ****************************************************************************** + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @attention + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * Redistribution and use in source and binary forms, with or without modification, + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * are permitted provided that the following conditions are met: + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * 1. Redistributions of source code must retain the above copyright notice, + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * this list of conditions and the following disclaimer. + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * this list of conditions and the following disclaimer in the documentation + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * and/or other materials provided with the distribution. + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * may be used to endorse or promote products derived from this software + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * without specific prior written permission. + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + ARM GAS /tmp/cc7An1gz.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ****************************************************************************** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Includes ------------------------------------------------------------------*/ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** #include "stm32l0xx_hal.h" + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @addtogroup STM32L0xx_HAL_Driver + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART UART + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief HAL UART module driver + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** #ifdef HAL_UART_MODULE_ENABLED + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Private typedef -----------------------------------------------------------*/ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Private define ------------------------------------------------------------*/ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Private_Constants UART Private Constants + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or U + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** #define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized valu + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** #define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized valu + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Private macros ------------------------------------------------------------*/ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Private variables ---------------------------------------------------------*/ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Private function prototypes -----------------------------------------------*/ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @addtogroup UART_Private_Functions + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart); + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart); + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma); + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); + ARM GAS /tmp/cc7An1gz.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Exported functions --------------------------------------------------------*/ + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Exported_Functions UART Exported Functions + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialization and Configuration functions + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @verbatim + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ##### Initialization and Configuration functions ##### + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in asynchronous mode. + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) For the asynchronous mode the parameters below can be configured: + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Baud Rate + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Word Length + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Stop Bit + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the data register is transmitted but is changed by the parity bit. + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Hardware flow control + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Receiver/transmitter modes + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) Over Sampling Method + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) One-Bit Sampling Method + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) TX and/or RX pin level inversion + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) data logical level inversion + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) RX and TX pins swap + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) RX overrun detection disabling + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) DMA disabling on RX error + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) MSB first on communication line + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (++) auto Baud rate detection + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and UART multiprocessor mode configuration procedures (details for the procedures + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** are available in reference manual). + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @endverbatim + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** 8-bit or 9-bit), the possible UART formats are listed in the + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** following table. + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Table 1. UART frame format. + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +-----------------------------------------------------------------------+ + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | M1 bit | M0 bit | PCE bit | UART frame | + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + ARM GAS /tmp/cc7An1gz.s page 5 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +-----------------------------------------------------------------------+ + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialize the UART mode according to the specified + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * parameters in the UART_InitTypeDef and initialize the associated handle. + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart == NULL) + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_INSTANCE(huart->Instance)); + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_RESET) + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_MspInit(huart); + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the Peripheral */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART Communication parameters */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + ARM GAS /tmp/cc7An1gz.s page 6 + + + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In asynchronous mode, the following bits must be kept cleared: + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the Peripheral */ + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialize the half-duplex mode according to the specified + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart == NULL) + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check UART instance */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_RESET) + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_MspInit(huart); + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the Peripheral */ + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART Communication parameters */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 7 + + + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In half-duplex mode, the following bits must be kept cleared: + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the Peripheral */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialize the LIN mode according to the specified + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle . + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param BreakDetectLength: specifies the LIN break detection length. + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This parameter can be one of the following values: + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart == NULL) + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the LIN UART instance */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the Break detection length parameter */ + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* LIN mode limited to 16-bit oversampling only */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* LIN mode limited to 8-bit data length */ + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->Init.WordLength != UART_WORDLENGTH_8B) + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_RESET) + ARM GAS /tmp/cc7An1gz.s page 8 + + + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_MspInit(huart); + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the Peripheral */ + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART Communication parameters */ + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In LIN mode, the following bits must be kept cleared: + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the USART LIN Break detection length. */ + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the Peripheral */ + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialize the multiprocessor mode according to the specified + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * parameters in the UART_InitTypeDef and initialize the associated handle. + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Address: UART node address (4-, 6-, 7- or 8-bit long). + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param WakeUpMethod: specifies the UART wakeup method. + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This parameter can be one of the following values: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note If the user resorts to idle line detection wake up, the Address parameter + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * is useless and ignored by the initialization function. + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note If the user resorts to address mark wake up, the address length detection + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * is configured by default to 4 bits only. For the UART to be able to + ARM GAS /tmp/cc7An1gz.s page 9 + + + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * manage 6-, 7- or 8-bit long addresses detection, the API + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * HAL_MultiProcessorEx_AddressLength_Set() must be called after + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * HAL_MultiProcessor_Init(). + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t Wake + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart == NULL) + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the wake up method parameter */ + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_RESET) + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_MspInit(huart); + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the Peripheral */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART Communication parameters */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In multiprocessor mode, the following bits must be kept cleared: + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* If address mark wake up method is chosen, set the USART address node */ + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS) + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the wake up method by setting the WAKE bit in the CR1 register */ + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the Peripheral */ + ARM GAS /tmp/cc7An1gz.s page 10 + + + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DeInitialize the UART peripheral. + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart == NULL) + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_INSTANCE(huart->Instance)); + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the Peripheral */ + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->CR1 = 0x0U; + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DeInit the low level hardware */ + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_MspDeInit(huart); + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlock */ + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Initialize the UART MSP. + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 26 .loc 1 541 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + ARM GAS /tmp/cc7An1gz.s page 11 + + + 31 .LVL0: + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_MspInit can be implemented in the user file + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 32 .loc 1 548 0 + 33 @ sp needed + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE44: + 38 .section .text.HAL_UART_MspDeInit,"ax",%progbits + 39 .align 1 + 40 .weak HAL_UART_MspDeInit + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 HAL_UART_MspDeInit: + 47 .LFB45: + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DeInitialize the UART MSP. + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 48 .loc 1 556 0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 53 .LVL1: + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_MspDeInit can be implemented in the user file + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 54 .loc 1 563 0 + 55 @ sp needed + 56 0000 7047 bx lr + 57 .cfi_endproc + 58 .LFE45: + 60 .section .text.HAL_UART_DeInit,"ax",%progbits + 61 .align 1 + 62 .global HAL_UART_DeInit + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 HAL_UART_DeInit: + 69 .LFB43: + ARM GAS /tmp/cc7An1gz.s page 12 + + + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 70 .loc 1 503 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .LVL2: + 75 0000 70B5 push {r4, r5, r6, lr} + 76 .LCFI0: + 77 .cfi_def_cfa_offset 16 + 78 .cfi_offset 4, -16 + 79 .cfi_offset 5, -12 + 80 .cfi_offset 6, -8 + 81 .cfi_offset 14, -4 + 82 0002 041E subs r4, r0, #0 + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 83 .loc 1 505 0 + 84 0004 18D0 beq .L5 + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 85 .loc 1 513 0 + 86 0006 6926 movs r6, #105 + 87 0008 2423 movs r3, #36 + 88 000a 8355 strb r3, [r0, r6] + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 89 .loc 1 516 0 + 90 000c 0268 ldr r2, [r0] + 91 000e 1368 ldr r3, [r2] + 92 0010 0121 movs r1, #1 + 93 0012 8B43 bics r3, r1 + 94 0014 1360 str r3, [r2] + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 95 .loc 1 518 0 + 96 0016 0368 ldr r3, [r0] + 97 0018 0025 movs r5, #0 + 98 001a 1D60 str r5, [r3] + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 99 .loc 1 519 0 + 100 001c 0368 ldr r3, [r0] + 101 001e 5D60 str r5, [r3, #4] + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 102 .loc 1 520 0 + 103 0020 0368 ldr r3, [r0] + 104 0022 9D60 str r5, [r3, #8] + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 105 .loc 1 523 0 + 106 0024 FFF7FEFF bl HAL_UART_MspDeInit + 107 .LVL3: + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 108 .loc 1 525 0 + 109 0028 E566 str r5, [r4, #108] + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 110 .loc 1 526 0 + 111 002a A555 strb r5, [r4, r6] + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 112 .loc 1 527 0 + 113 002c 6A23 movs r3, #106 + 114 002e E554 strb r5, [r4, r3] + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 13 + + + 115 .loc 1 530 0 + 116 0030 023B subs r3, r3, #2 + 117 0032 E554 strb r5, [r4, r3] + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 118 .loc 1 532 0 + 119 0034 0020 movs r0, #0 + 120 .L4: + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 121 .loc 1 533 0 + 122 @ sp needed + 123 .LVL4: + 124 0036 70BD pop {r4, r5, r6, pc} + 125 .LVL5: + 126 .L5: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 127 .loc 1 507 0 + 128 0038 0120 movs r0, #1 + 129 .LVL6: + 130 003a FCE7 b .L4 + 131 .cfi_endproc + 132 .LFE43: + 134 .section .text.HAL_UART_Transmit_IT,"ax",%progbits + 135 .align 1 + 136 .global HAL_UART_Transmit_IT + 137 .syntax unified + 138 .code 16 + 139 .thumb_func + 140 .fpu softvfp + 142 HAL_UART_Transmit_IT: + 143 .LFB48: + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group2 IO operation functions + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART Transmit/Receive functions + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @verbatim + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ##### IO operation functions ##### + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** This subsection provides a set of functions allowing to manage the UART asynchronous + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and Half duplex data transfers. + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) There are two mode of transfer: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Blocking mode: The communication is performed in polling mode. + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The HAL status of all data processing is returned by the same function + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** after finishing transfer. + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Non-Blocking mode: The communication is performed using Interrupts + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** or DMA, These API's return the HAL status. + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The end of the data processing will be indicated through the + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** using DMA mode. + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will be executed respectively at the end of the transmit or Receive process + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** The HAL_UART_ErrorCallback()user callback will be executed when a communication error is + ARM GAS /tmp/cc7An1gz.s page 14 + + + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Blocking mode API's are : + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Transmit() + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Receive() + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Non-Blocking mode API's with Interrupt are : + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Transmit_IT() + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Receive_IT() + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_IRQHandler() + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Non-Blocking mode API's with DMA are : + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Transmit_DMA() + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Receive_DMA() + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_DMAPause() + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_DMAResume() + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_DMAStop() + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_TxHalfCpltCallback() + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_TxCpltCallback() + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_RxHalfCpltCallback() + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_RxCpltCallback() + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_ErrorCallback() + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) Non-Blocking mode transfers could be aborted using Abort API's : + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Abort() + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortTransmit() + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortReceive() + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_Abort_IT() + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortTransmit_IT() + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortReceive_IT() + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Call + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortCpltCallback() + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortTransmitCpltCallback() + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_UART_AbortReceiveCpltCallback() + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Errors are handled as follows : + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but er + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Inte + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Received character is then retrieved and stored in Rx buffer, Error code is set to allow + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** If user wants to abort it, Abort services should be called by user. + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Error is considered as Blocking : Transfer could not be completed properly and is aborte + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() use + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** -@- In the Half duplex communication, it is forbidden to run the transmit + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @endverbatim + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Send an amount of data in blocking mode. + ARM GAS /tmp/cc7An1gz.s page 15 + + + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: Pointer to data buffer. + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: Amount of data to be sent. + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Timeout: Timeout duration. + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer containing data to be sent, should be aligned on a half wor + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint3 + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tickstart = 0; + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_READY) + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data to be filled into TDR will be + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled through a u16 cast. */ + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init tickstart for timeout managment*/ + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tickstart = HAL_GetTick(); + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferSize = Size; + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = Size; + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** while(huart->TxXferCount > 0U) + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount--; + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmp = (uint16_t*) pData; + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** pData += 2U; + ARM GAS /tmp/cc7An1gz.s page 16 + + + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Receive an amount of data in blocking mode. + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: pointer to data buffer. + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: amount of data to be received. + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Timeout: Timeout duration. + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer for storing data to be received, should be aligned on a hal + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as received data will be handled using u16 pointer cast). Depending on compilation cha + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32 + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t uhMask; + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tickstart = 0; + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->RxState == HAL_UART_STATE_READY) + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data to be received from RDR will be + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled through a u16 cast. */ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) + ARM GAS /tmp/cc7An1gz.s page 17 + + + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init tickstart for timeout managment*/ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tickstart = HAL_GetTick(); + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferSize = Size; + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = Size; + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* as long as data have to be received */ + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** while(huart->RxXferCount > 0U) + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount--; + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmp = (uint16_t*) pData ; + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** *tmp = (uint16_t)(huart->Instance->RDR & uhMask); + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** pData +=2U; + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Send an amount of data in interrupt mode. + ARM GAS /tmp/cc7An1gz.s page 18 + + + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: pointer to data buffer. + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: amount of data to be sent. + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer containing data to be sent, should be aligned on a half wor + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 144 .loc 1 829 0 + 145 .cfi_startproc + 146 @ args = 0, pretend = 0, frame = 0 + 147 @ frame_needed = 0, uses_anonymous_args = 0 + 148 .LVL7: + 149 0000 10B5 push {r4, lr} + 150 .LCFI1: + 151 .cfi_def_cfa_offset 8 + 152 .cfi_offset 4, -8 + 153 .cfi_offset 14, -4 + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_READY) + 154 .loc 1 831 0 + 155 0002 6923 movs r3, #105 + 156 0004 C35C ldrb r3, [r0, r3] + 157 0006 202B cmp r3, #32 + 158 0008 26D1 bne .L9 + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 159 .loc 1 833 0 + 160 000a 0029 cmp r1, #0 + 161 000c 26D0 beq .L10 + 162 .loc 1 833 0 is_stmt 0 discriminator 1 + 163 000e 002A cmp r2, #0 + 164 0010 26D0 beq .L11 + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data to be filled into TDR will be + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled through a u16 cast. */ + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 165 .loc 1 841 0 is_stmt 1 + 166 0012 8023 movs r3, #128 + 167 0014 5B01 lsls r3, r3, #5 + 168 0016 8468 ldr r4, [r0, #8] + 169 0018 9C42 cmp r4, r3 + 170 001a 16D0 beq .L14 + 171 .L8: + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + ARM GAS /tmp/cc7An1gz.s page 19 + + + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 172 .loc 1 850 0 + 173 001c 6823 movs r3, #104 + 174 001e C35C ldrb r3, [r0, r3] + 175 0020 012B cmp r3, #1 + 176 0022 1FD0 beq .L13 + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pTxBuffPtr = pData; + 177 .loc 1 852 0 discriminator 2 + 178 0024 C164 str r1, [r0, #76] + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferSize = Size; + 179 .loc 1 853 0 discriminator 2 + 180 0026 5023 movs r3, #80 + 181 0028 C252 strh r2, [r0, r3] + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = Size; + 182 .loc 1 854 0 discriminator 2 + 183 002a 0233 adds r3, r3, #2 + 184 002c C252 strh r2, [r0, r3] + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 185 .loc 1 856 0 discriminator 2 + 186 002e 0023 movs r3, #0 + 187 0030 C366 str r3, [r0, #108] + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 188 .loc 1 857 0 discriminator 2 + 189 0032 6922 movs r2, #105 + 190 .LVL8: + 191 0034 2121 movs r1, #33 + 192 .LVL9: + 193 0036 8154 strb r1, [r0, r2] + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 194 .loc 1 860 0 discriminator 2 + 195 0038 013A subs r2, r2, #1 + 196 003a 8354 strb r3, [r0, r2] + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Transmit Data Register Empty Interrupt */ + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + 197 .loc 1 863 0 discriminator 2 + 198 003c 0268 ldr r2, [r0] + 199 003e 1368 ldr r3, [r2] + 200 0040 5F31 adds r1, r1, #95 + 201 0042 0B43 orrs r3, r1 + 202 0044 1360 str r3, [r2] + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 203 .loc 1 865 0 discriminator 2 + 204 0046 0020 movs r0, #0 + 205 .LVL10: + 206 0048 07E0 b .L7 + 207 .LVL11: + 208 .L14: + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 209 .loc 1 841 0 discriminator 1 + ARM GAS /tmp/cc7An1gz.s page 20 + + + 210 004a 0369 ldr r3, [r0, #16] + 211 004c 002B cmp r3, #0 + 212 004e E5D1 bne .L8 + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 213 .loc 1 843 0 + 214 0050 CB07 lsls r3, r1, #31 + 215 0052 E3D5 bpl .L8 + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 216 .loc 1 845 0 + 217 0054 0120 movs r0, #1 + 218 .LVL12: + 219 0056 00E0 b .L7 + 220 .LVL13: + 221 .L9: + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 222 .loc 1 869 0 + 223 0058 0220 movs r0, #2 + 224 .LVL14: + 225 .L7: + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 226 .loc 1 871 0 + 227 @ sp needed + 228 005a 10BD pop {r4, pc} + 229 .LVL15: + 230 .L10: + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 231 .loc 1 835 0 + 232 005c 0120 movs r0, #1 + 233 .LVL16: + 234 005e FCE7 b .L7 + 235 .LVL17: + 236 .L11: + 237 0060 0120 movs r0, #1 + 238 .LVL18: + 239 0062 FAE7 b .L7 + 240 .LVL19: + 241 .L13: + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 242 .loc 1 850 0 + 243 0064 0220 movs r0, #2 + 244 .LVL20: + 245 0066 F8E7 b .L7 + 246 .cfi_endproc + 247 .LFE48: + 249 .section .text.HAL_UART_Receive_IT,"ax",%progbits + 250 .align 1 + 251 .global HAL_UART_Receive_IT + 252 .syntax unified + 253 .code 16 + 254 .thumb_func + 255 .fpu softvfp + 257 HAL_UART_Receive_IT: + 258 .LFB49: + ARM GAS /tmp/cc7An1gz.s page 21 + + + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Receive an amount of data in interrupt mode. + 875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: pointer to data buffer. + 877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: amount of data to be received. + 878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- + 879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer containing data to be sent, should be aligned on a half wor + 880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + 881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure + 882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + 883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) + 885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 259 .loc 1 885 0 + 260 .cfi_startproc + 261 @ args = 0, pretend = 0, frame = 0 + 262 @ frame_needed = 0, uses_anonymous_args = 0 + 263 .LVL21: + 264 0000 30B5 push {r4, r5, lr} + 265 .LCFI2: + 266 .cfi_def_cfa_offset 12 + 267 .cfi_offset 4, -12 + 268 .cfi_offset 5, -8 + 269 .cfi_offset 14, -4 + 886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->RxState == HAL_UART_STATE_READY) + 270 .loc 1 887 0 + 271 0002 6A23 movs r3, #106 + 272 0004 C35C ldrb r3, [r0, r3] + 273 0006 202B cmp r3, #32 + 274 0008 5AD1 bne .L24 + 888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 275 .loc 1 889 0 + 276 000a 0029 cmp r1, #0 + 277 000c 5AD0 beq .L25 + 278 .loc 1 889 0 is_stmt 0 discriminator 1 + 279 000e 002A cmp r2, #0 + 280 0010 5AD0 beq .L26 + 890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + 895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data to be received from RDR will be + 896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled through a u16 cast. */ + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 281 .loc 1 897 0 is_stmt 1 + 282 0012 8368 ldr r3, [r0, #8] + 283 0014 8024 movs r4, #128 + 284 0016 6401 lsls r4, r4, #5 + 285 0018 A342 cmp r3, r4 + 286 001a 18D0 beq .L29 + 287 .L17: + 898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) + ARM GAS /tmp/cc7An1gz.s page 22 + + + 900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 288 .loc 1 906 0 + 289 001c 6824 movs r4, #104 + 290 001e 045D ldrb r4, [r0, r4] + 291 0020 012C cmp r4, #1 + 292 0022 53D0 beq .L28 + 293 .loc 1 906 0 is_stmt 0 discriminator 2 + 294 0024 6824 movs r4, #104 + 295 0026 0125 movs r5, #1 + 296 0028 0555 strb r5, [r0, r4] + 907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pRxBuffPtr = pData; + 297 .loc 1 908 0 is_stmt 1 discriminator 2 + 298 002a 4165 str r1, [r0, #84] + 909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferSize = Size; + 299 .loc 1 909 0 discriminator 2 + 300 002c 5821 movs r1, #88 + 301 .LVL22: + 302 002e 4252 strh r2, [r0, r1] + 303 .LVL23: + 910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = Size; + 304 .loc 1 910 0 discriminator 2 + 305 0030 0231 adds r1, r1, #2 + 306 0032 4252 strh r2, [r0, r1] + 911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); + 307 .loc 1 913 0 discriminator 2 + 308 0034 8022 movs r2, #128 + 309 .LVL24: + 310 0036 5201 lsls r2, r2, #5 + 311 0038 9342 cmp r3, r2 + 312 003a 0FD0 beq .L30 + 313 003c 002B cmp r3, #0 + 314 003e 1CD1 bne .L21 + 315 .loc 1 913 0 is_stmt 0 discriminator 5 + 316 0040 0369 ldr r3, [r0, #16] + 317 0042 002B cmp r3, #0 + 318 0044 15D1 bne .L22 + 319 .loc 1 913 0 discriminator 7 + 320 0046 5C33 adds r3, r3, #92 + 321 0048 FF22 movs r2, #255 + 322 004a C252 strh r2, [r0, r3] + 323 .LVL25: + 324 004c 19E0 b .L20 + 325 .LVL26: + 326 .L29: + 897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 327 .loc 1 897 0 is_stmt 1 discriminator 1 + 328 004e 0469 ldr r4, [r0, #16] + 329 0050 002C cmp r4, #0 + ARM GAS /tmp/cc7An1gz.s page 23 + + + 330 0052 E3D1 bne .L17 + 899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 331 .loc 1 899 0 + 332 0054 CC07 lsls r4, r1, #31 + 333 0056 E1D5 bpl .L17 + 901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 334 .loc 1 901 0 + 335 0058 0120 movs r0, #1 + 336 .LVL27: + 337 005a 32E0 b .L16 + 338 .LVL28: + 339 .L30: + 340 .loc 1 913 0 discriminator 1 + 341 005c 0369 ldr r3, [r0, #16] + 342 005e 002B cmp r3, #0 + 343 0060 03D1 bne .L19 + 344 .loc 1 913 0 is_stmt 0 discriminator 3 + 345 0062 5C33 adds r3, r3, #92 + 346 0064 1A4A ldr r2, .L32 + 347 0066 C252 strh r2, [r0, r3] + 348 .LVL29: + 349 0068 0BE0 b .L20 + 350 .LVL30: + 351 .L19: + 352 .loc 1 913 0 discriminator 4 + 353 006a 5C23 movs r3, #92 + 354 006c FF22 movs r2, #255 + 355 006e C252 strh r2, [r0, r3] + 356 .LVL31: + 357 0070 07E0 b .L20 + 358 .LVL32: + 359 .L22: + 360 .loc 1 913 0 discriminator 8 + 361 0072 5C23 movs r3, #92 + 362 0074 7F22 movs r2, #127 + 363 0076 C252 strh r2, [r0, r3] + 364 .LVL33: + 365 0078 03E0 b .L20 + 366 .LVL34: + 367 .L21: + 368 .loc 1 913 0 discriminator 6 + 369 007a 8022 movs r2, #128 + 370 007c 5205 lsls r2, r2, #21 + 371 007e 9342 cmp r3, r2 + 372 0080 13D0 beq .L31 + 373 .LVL35: + 374 .L20: + 914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 375 .loc 1 915 0 is_stmt 1 + 376 0082 0023 movs r3, #0 + 377 0084 C366 str r3, [r0, #108] + 916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 378 .loc 1 916 0 + 379 0086 6A22 movs r2, #106 + 380 0088 2221 movs r1, #34 + 381 008a 8154 strb r1, [r0, r2] + ARM GAS /tmp/cc7An1gz.s page 24 + + + 917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 382 .loc 1 919 0 + 383 008c 023A subs r2, r2, #2 + 384 008e 8354 strb r3, [r0, r2] + 920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + 922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 385 .loc 1 922 0 + 386 0090 0268 ldr r2, [r0] + 387 0092 9368 ldr r3, [r2, #8] + 388 0094 2139 subs r1, r1, #33 + 389 0096 0B43 orrs r3, r1 + 390 0098 9360 str r3, [r2, #8] + 923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Parity Error and Data Register not empty Interrupts */ + 925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + 391 .loc 1 925 0 + 392 009a 0268 ldr r2, [r0] + 393 009c 1168 ldr r1, [r2] + 394 009e 9023 movs r3, #144 + 395 00a0 5B00 lsls r3, r3, #1 + 396 00a2 0B43 orrs r3, r1 + 397 00a4 1360 str r3, [r2] + 926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 398 .loc 1 927 0 + 399 00a6 0020 movs r0, #0 + 400 .LVL36: + 401 00a8 0BE0 b .L16 + 402 .LVL37: + 403 .L31: + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 404 .loc 1 913 0 discriminator 9 + 405 00aa 0369 ldr r3, [r0, #16] + 406 00ac 002B cmp r3, #0 + 407 00ae 03D1 bne .L23 + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 408 .loc 1 913 0 is_stmt 0 discriminator 10 + 409 00b0 5C33 adds r3, r3, #92 + 410 00b2 7F22 movs r2, #127 + 411 00b4 C252 strh r2, [r0, r3] + 412 .LVL38: + 413 00b6 E4E7 b .L20 + 414 .LVL39: + 415 .L23: + 913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 416 .loc 1 913 0 discriminator 11 + 417 00b8 5C23 movs r3, #92 + 418 00ba 3F22 movs r2, #63 + 419 00bc C252 strh r2, [r0, r3] + 420 .LVL40: + 421 00be E0E7 b .L20 + 422 .LVL41: + 423 .L24: + 928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + ARM GAS /tmp/cc7An1gz.s page 25 + + + 929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + 930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 424 .loc 1 931 0 is_stmt 1 + 425 00c0 0220 movs r0, #2 + 426 .LVL42: + 427 .L16: + 932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 428 .loc 1 933 0 + 429 @ sp needed + 430 00c2 30BD pop {r4, r5, pc} + 431 .LVL43: + 432 .L25: + 891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 433 .loc 1 891 0 + 434 00c4 0120 movs r0, #1 + 435 .LVL44: + 436 00c6 FCE7 b .L16 + 437 .LVL45: + 438 .L26: + 439 00c8 0120 movs r0, #1 + 440 .LVL46: + 441 00ca FAE7 b .L16 + 442 .LVL47: + 443 .L28: + 906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 444 .loc 1 906 0 + 445 00cc 0220 movs r0, #2 + 446 .LVL48: + 447 00ce F8E7 b .L16 + 448 .L33: + 449 .align 2 + 450 .L32: + 451 00d0 FF010000 .word 511 + 452 .cfi_endproc + 453 .LFE49: + 455 .section .text.HAL_UART_Transmit_DMA,"ax",%progbits + 456 .align 1 + 457 .global HAL_UART_Transmit_DMA + 458 .syntax unified + 459 .code 16 + 460 .thumb_func + 461 .fpu softvfp + 463 HAL_UART_Transmit_DMA: + 464 .LFB50: + 934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Send an amount of data in DMA mode. + 937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + 938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: pointer to data buffer. + 939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: amount of data to be sent. + 940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- + 941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer containing data to be sent, should be aligned on a half wor + 942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + 943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure + 944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + ARM GAS /tmp/cc7An1gz.s page 26 + + + 945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + 946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) + 947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 465 .loc 1 947 0 + 466 .cfi_startproc + 467 @ args = 0, pretend = 0, frame = 0 + 468 @ frame_needed = 0, uses_anonymous_args = 0 + 469 .LVL49: + 470 0000 70B5 push {r4, r5, r6, lr} + 471 .LCFI3: + 472 .cfi_def_cfa_offset 16 + 473 .cfi_offset 4, -16 + 474 .cfi_offset 5, -12 + 475 .cfi_offset 6, -8 + 476 .cfi_offset 14, -4 + 477 0002 0400 movs r4, r0 + 948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_READY) + 478 .loc 1 949 0 + 479 0004 6920 movs r0, #105 + 480 .LVL50: + 481 0006 205C ldrb r0, [r4, r0] + 482 0008 2028 cmp r0, #32 + 483 000a 3ED1 bne .L37 + 950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 484 .loc 1 951 0 + 485 000c 0029 cmp r1, #0 + 486 000e 3ED0 beq .L38 + 487 .loc 1 951 0 is_stmt 0 discriminator 1 + 488 0010 002A cmp r2, #0 + 489 0012 3ED0 beq .L39 + 952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + 957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data copy into TDR will be + 958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled by DMA from a u16 frontier. */ + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 490 .loc 1 959 0 is_stmt 1 + 491 0014 8023 movs r3, #128 + 492 0016 5B01 lsls r3, r3, #5 + 493 0018 A068 ldr r0, [r4, #8] + 494 001a 9842 cmp r0, r3 + 495 001c 2ED0 beq .L42 + 496 .L36: + 960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) + 962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; + 964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 497 .loc 1 968 0 + ARM GAS /tmp/cc7An1gz.s page 27 + + + 498 001e 6823 movs r3, #104 + 499 0020 E35C ldrb r3, [r4, r3] + 500 0022 012B cmp r3, #1 + 501 0024 37D0 beq .L41 + 502 .loc 1 968 0 is_stmt 0 discriminator 2 + 503 0026 6826 movs r6, #104 + 504 0028 0123 movs r3, #1 + 505 002a A355 strb r3, [r4, r6] + 969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pTxBuffPtr = pData; + 506 .loc 1 970 0 is_stmt 1 discriminator 2 + 507 002c E164 str r1, [r4, #76] + 971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferSize = Size; + 508 .loc 1 971 0 discriminator 2 + 509 002e 4F33 adds r3, r3, #79 + 510 0030 E252 strh r2, [r4, r3] + 972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = Size; + 511 .loc 1 972 0 discriminator 2 + 512 0032 0233 adds r3, r3, #2 + 513 0034 E252 strh r2, [r4, r3] + 973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 514 .loc 1 974 0 discriminator 2 + 515 0036 0025 movs r5, #0 + 516 0038 E566 str r5, [r4, #108] + 975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 517 .loc 1 975 0 discriminator 2 + 518 003a 1733 adds r3, r3, #23 + 519 003c 2121 movs r1, #33 + 520 .LVL51: + 521 003e E154 strb r1, [r4, r3] + 976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ + 978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + 522 .loc 1 978 0 discriminator 2 + 523 0040 236E ldr r3, [r4, #96] + 524 0042 1649 ldr r1, .L43 + 525 0044 D962 str r1, [r3, #44] + 979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ + 981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + 526 .loc 1 981 0 discriminator 2 + 527 0046 236E ldr r3, [r4, #96] + 528 0048 1549 ldr r1, .L43+4 + 529 004a 1963 str r1, [r3, #48] + 982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the DMA error callback */ + 984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferErrorCallback = UART_DMAError; + 530 .loc 1 984 0 discriminator 2 + 531 004c 236E ldr r3, [r4, #96] + 532 004e 1549 ldr r1, .L43+8 + 533 0050 5963 str r1, [r3, #52] + 985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the DMA abort callback */ + 987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; + 534 .loc 1 987 0 discriminator 2 + 535 0052 236E ldr r3, [r4, #96] + ARM GAS /tmp/cc7An1gz.s page 28 + + + 536 0054 9D63 str r5, [r3, #56] + 988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART transmit DMA channel */ + 990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, S + 537 .loc 1 990 0 discriminator 2 + 538 0056 2168 ldr r1, [r4] + 539 0058 2831 adds r1, r1, #40 + 540 005a 1300 movs r3, r2 + 541 005c 0A00 movs r2, r1 + 542 .LVL52: + 543 005e E16C ldr r1, [r4, #76] + 544 0060 206E ldr r0, [r4, #96] + 545 0062 FFF7FEFF bl HAL_DMA_Start_IT + 546 .LVL53: + 991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the TC flag in the ICR register */ + 993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + 547 .loc 1 993 0 discriminator 2 + 548 0066 2368 ldr r3, [r4] + 549 0068 4022 movs r2, #64 + 550 006a 1A62 str r2, [r3, #32] + 994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 551 .loc 1 996 0 discriminator 2 + 552 006c A555 strb r5, [r4, r6] + 997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the DMA transfer for transmit request by setting the DMAT bit + 999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the UART CR3 register */ +1000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 553 .loc 1 1000 0 discriminator 2 + 554 006e 2268 ldr r2, [r4] + 555 0070 9368 ldr r3, [r2, #8] + 556 0072 8021 movs r1, #128 + 557 0074 0B43 orrs r3, r1 + 558 0076 9360 str r3, [r2, #8] +1001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 559 .loc 1 1002 0 discriminator 2 + 560 0078 0020 movs r0, #0 + 561 007a 07E0 b .L35 + 562 .LVL54: + 563 .L42: + 959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 564 .loc 1 959 0 discriminator 1 + 565 007c 2369 ldr r3, [r4, #16] + 566 007e 002B cmp r3, #0 + 567 0080 CDD1 bne .L36 + 961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 568 .loc 1 961 0 + 569 0082 CB07 lsls r3, r1, #31 + 570 0084 CBD5 bpl .L36 + 963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 571 .loc 1 963 0 + 572 0086 0120 movs r0, #1 + 573 0088 00E0 b .L35 + 574 .L37: + ARM GAS /tmp/cc7An1gz.s page 29 + + +1003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 575 .loc 1 1006 0 + 576 008a 0220 movs r0, #2 + 577 .LVL55: + 578 .L35: +1007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 579 .loc 1 1008 0 + 580 @ sp needed + 581 .LVL56: + 582 008c 70BD pop {r4, r5, r6, pc} + 583 .LVL57: + 584 .L38: + 953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 585 .loc 1 953 0 + 586 008e 0120 movs r0, #1 + 587 0090 FCE7 b .L35 + 588 .L39: + 589 0092 0120 movs r0, #1 + 590 0094 FAE7 b .L35 + 591 .L41: + 968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 592 .loc 1 968 0 + 593 0096 0220 movs r0, #2 + 594 0098 F8E7 b .L35 + 595 .L44: + 596 009a C046 .align 2 + 597 .L43: + 598 009c 00000000 .word UART_DMATransmitCplt + 599 00a0 00000000 .word UART_DMATxHalfCplt + 600 00a4 00000000 .word UART_DMAError + 601 .cfi_endproc + 602 .LFE50: + 604 .section .text.HAL_UART_Receive_DMA,"ax",%progbits + 605 .align 1 + 606 .global HAL_UART_Receive_DMA + 607 .syntax unified + 608 .code 16 + 609 .thumb_func + 610 .fpu softvfp + 612 HAL_UART_Receive_DMA: + 613 .LFB51: +1009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Receive an amount of data in DMA mode. +1012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param pData: pointer to data buffer. +1014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Size: amount of data to be received. +1015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. +1016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * address of user data buffer containing data to be sent, should be aligned on a half wor +1018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, +1019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * use of specific alignment compilation directives or pragmas might be required to ensure +1020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status + ARM GAS /tmp/cc7An1gz.s page 30 + + +1021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 614 .loc 1 1023 0 + 615 .cfi_startproc + 616 @ args = 0, pretend = 0, frame = 0 + 617 @ frame_needed = 0, uses_anonymous_args = 0 + 618 .LVL58: + 619 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 620 .LCFI4: + 621 .cfi_def_cfa_offset 24 + 622 .cfi_offset 3, -24 + 623 .cfi_offset 4, -20 + 624 .cfi_offset 5, -16 + 625 .cfi_offset 6, -12 + 626 .cfi_offset 7, -8 + 627 .cfi_offset 14, -4 + 628 0002 0400 movs r4, r0 +1024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->RxState == HAL_UART_STATE_READY) + 629 .loc 1 1025 0 + 630 0004 6A20 movs r0, #106 + 631 .LVL59: + 632 0006 205C ldrb r0, [r4, r0] + 633 0008 2028 cmp r0, #32 + 634 000a 42D1 bne .L48 +1026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((pData == NULL ) || (Size == 0U)) + 635 .loc 1 1027 0 + 636 000c 0029 cmp r1, #0 + 637 000e 42D0 beq .L49 + 638 .loc 1 1027 0 is_stmt 0 discriminator 1 + 639 0010 002A cmp r2, #0 + 640 0012 42D0 beq .L50 +1028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; +1030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter +1033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** should be aligned on a u16 frontier, as data copy from RDR will be +1034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** handled by DMA from a u16 frontier. */ +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 641 .loc 1 1035 0 is_stmt 1 + 642 0014 8023 movs r3, #128 + 643 0016 5B01 lsls r3, r3, #5 + 644 0018 A068 ldr r0, [r4, #8] + 645 001a 9842 cmp r0, r3 + 646 001c 32D0 beq .L53 + 647 .L47: +1036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((((uint32_t)pData)&1) != 0) +1038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_ERROR; +1040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + ARM GAS /tmp/cc7An1gz.s page 31 + + +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 648 .loc 1 1044 0 + 649 001e 6823 movs r3, #104 + 650 0020 E35C ldrb r3, [r4, r3] + 651 0022 012B cmp r3, #1 + 652 0024 3BD0 beq .L52 + 653 .loc 1 1044 0 is_stmt 0 discriminator 2 + 654 0026 6827 movs r7, #104 + 655 0028 0126 movs r6, #1 + 656 002a E655 strb r6, [r4, r7] +1045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pRxBuffPtr = pData; + 657 .loc 1 1046 0 is_stmt 1 discriminator 2 + 658 002c 6165 str r1, [r4, #84] +1047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferSize = Size; + 659 .loc 1 1047 0 discriminator 2 + 660 002e 5823 movs r3, #88 + 661 0030 E252 strh r2, [r4, r3] +1048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 662 .loc 1 1049 0 discriminator 2 + 663 0032 0025 movs r5, #0 + 664 0034 E566 str r5, [r4, #108] +1050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 665 .loc 1 1050 0 discriminator 2 + 666 0036 1233 adds r3, r3, #18 + 667 0038 2221 movs r1, #34 + 668 .LVL60: + 669 003a E154 strb r1, [r4, r3] +1051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ +1053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + 670 .loc 1 1053 0 discriminator 2 + 671 003c 636E ldr r3, [r4, #100] + 672 003e 1949 ldr r1, .L54 + 673 0040 D962 str r1, [r3, #44] +1054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ +1056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + 674 .loc 1 1056 0 discriminator 2 + 675 0042 636E ldr r3, [r4, #100] + 676 0044 1849 ldr r1, .L54+4 + 677 0046 1963 str r1, [r3, #48] +1057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the DMA error callback */ +1059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferErrorCallback = UART_DMAError; + 678 .loc 1 1059 0 discriminator 2 + 679 0048 636E ldr r3, [r4, #100] + 680 004a 1849 ldr r1, .L54+8 + 681 004c 5963 str r1, [r3, #52] +1060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the DMA abort callback */ +1062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; + 682 .loc 1 1062 0 discriminator 2 + 683 004e 636E ldr r3, [r4, #100] + 684 0050 9D63 str r5, [r3, #56] +1063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 32 + + +1064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the DMA channel */ +1065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, S + 685 .loc 1 1065 0 discriminator 2 + 686 0052 2168 ldr r1, [r4] + 687 0054 2431 adds r1, r1, #36 + 688 0056 1300 movs r3, r2 + 689 0058 626D ldr r2, [r4, #84] + 690 .LVL61: + 691 005a 606E ldr r0, [r4, #100] + 692 005c FFF7FEFF bl HAL_DMA_Start_IT + 693 .LVL62: +1066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +1068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 694 .loc 1 1068 0 discriminator 2 + 695 0060 E555 strb r5, [r4, r7] +1069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Parity Error Interrupt */ +1071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 696 .loc 1 1071 0 discriminator 2 + 697 0062 2268 ldr r2, [r4] + 698 0064 1168 ldr r1, [r2] + 699 0066 8023 movs r3, #128 + 700 0068 5B00 lsls r3, r3, #1 + 701 006a 0B43 orrs r3, r1 + 702 006c 1360 str r3, [r2] +1072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +1074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 703 .loc 1 1074 0 discriminator 2 + 704 006e 2268 ldr r2, [r4] + 705 0070 9368 ldr r3, [r2, #8] + 706 0072 3343 orrs r3, r6 + 707 0074 9360 str r3, [r2, #8] +1075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the DMA transfer for the receiver request by setting the DMAR bit +1077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the UART CR3 register */ +1078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 708 .loc 1 1078 0 discriminator 2 + 709 0076 2268 ldr r2, [r4] + 710 0078 9368 ldr r3, [r2, #8] + 711 007a 4021 movs r1, #64 + 712 007c 0B43 orrs r3, r1 + 713 007e 9360 str r3, [r2, #8] +1079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 714 .loc 1 1080 0 discriminator 2 + 715 0080 0020 movs r0, #0 + 716 0082 07E0 b .L46 + 717 .LVL63: + 718 .L53: +1035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 719 .loc 1 1035 0 discriminator 1 + 720 0084 2369 ldr r3, [r4, #16] + 721 0086 002B cmp r3, #0 + 722 0088 C9D1 bne .L47 +1037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 33 + + + 723 .loc 1 1037 0 + 724 008a CB07 lsls r3, r1, #31 + 725 008c C7D5 bpl .L47 +1039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 726 .loc 1 1039 0 + 727 008e 0120 movs r0, #1 + 728 0090 00E0 b .L46 + 729 .L48: +1081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 730 .loc 1 1084 0 + 731 0092 0220 movs r0, #2 + 732 .LVL64: + 733 .L46: +1085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 734 .loc 1 1086 0 + 735 @ sp needed + 736 .LVL65: + 737 0094 F8BD pop {r3, r4, r5, r6, r7, pc} + 738 .LVL66: + 739 .L49: +1029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 740 .loc 1 1029 0 + 741 0096 0120 movs r0, #1 + 742 0098 FCE7 b .L46 + 743 .L50: + 744 009a 0120 movs r0, #1 + 745 009c FAE7 b .L46 + 746 .L52: +1044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 747 .loc 1 1044 0 + 748 009e 0220 movs r0, #2 + 749 00a0 F8E7 b .L46 + 750 .L55: + 751 00a2 C046 .align 2 + 752 .L54: + 753 00a4 00000000 .word UART_DMAReceiveCplt + 754 00a8 00000000 .word UART_DMARxHalfCplt + 755 00ac 00000000 .word UART_DMAError + 756 .cfi_endproc + 757 .LFE51: + 759 .section .text.HAL_UART_DMAPause,"ax",%progbits + 760 .align 1 + 761 .global HAL_UART_DMAPause + 762 .syntax unified + 763 .code 16 + 764 .thumb_func + 765 .fpu softvfp + 767 HAL_UART_DMAPause: + 768 .LFB52: +1087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Pause the DMA Transfer. +1090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. + ARM GAS /tmp/cc7An1gz.s page 34 + + +1091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +1094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 769 .loc 1 1094 0 + 770 .cfi_startproc + 771 @ args = 0, pretend = 0, frame = 0 + 772 @ frame_needed = 0, uses_anonymous_args = 0 + 773 @ link register save eliminated. + 774 .LVL67: +1095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 775 .loc 1 1096 0 + 776 0000 6823 movs r3, #104 + 777 0002 C35C ldrb r3, [r0, r3] + 778 0004 012B cmp r3, #1 + 779 0006 2CD0 beq .L60 + 780 .loc 1 1096 0 is_stmt 0 discriminator 2 + 781 0008 6823 movs r3, #104 + 782 000a 0122 movs r2, #1 + 783 000c C254 strb r2, [r0, r3] +1097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + 784 .loc 1 1098 0 is_stmt 1 discriminator 2 + 785 000e 0133 adds r3, r3, #1 + 786 0010 C35C ldrb r3, [r0, r3] + 787 0012 212B cmp r3, #33 + 788 0014 08D0 beq .L61 + 789 .L58: +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) +1100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Tx request */ +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + 790 .loc 1 1104 0 + 791 0016 6A23 movs r3, #106 + 792 0018 C35C ldrb r3, [r0, r3] + 793 001a 222B cmp r3, #34 + 794 001c 0DD0 beq .L62 + 795 .L59: +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) +1106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request */ +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +1116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 796 .loc 1 1116 0 + 797 001e 6823 movs r3, #104 + 798 0020 0022 movs r2, #0 + 799 0022 C254 strb r2, [r0, r3] + ARM GAS /tmp/cc7An1gz.s page 35 + + +1117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 800 .loc 1 1118 0 + 801 0024 0020 movs r0, #0 + 802 .LVL68: + 803 .L57: +1119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 804 .loc 1 1119 0 + 805 @ sp needed + 806 0026 7047 bx lr + 807 .LVL69: + 808 .L61: +1099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 809 .loc 1 1099 0 discriminator 1 + 810 0028 0368 ldr r3, [r0] + 811 002a 9A68 ldr r2, [r3, #8] +1098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + 812 .loc 1 1098 0 discriminator 1 + 813 002c 1206 lsls r2, r2, #24 + 814 002e F2D5 bpl .L58 +1102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 815 .loc 1 1102 0 + 816 0030 9A68 ldr r2, [r3, #8] + 817 0032 8021 movs r1, #128 + 818 0034 8A43 bics r2, r1 + 819 0036 9A60 str r2, [r3, #8] + 820 0038 EDE7 b .L58 + 821 .L62: +1105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 822 .loc 1 1105 0 discriminator 1 + 823 003a 0368 ldr r3, [r0] + 824 003c 9A68 ldr r2, [r3, #8] +1104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + 825 .loc 1 1104 0 discriminator 1 + 826 003e 5206 lsls r2, r2, #25 + 827 0040 EDD5 bpl .L59 +1108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 828 .loc 1 1108 0 + 829 0042 1A68 ldr r2, [r3] + 830 0044 0849 ldr r1, .L63 + 831 0046 0A40 ands r2, r1 + 832 0048 1A60 str r2, [r3] +1109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 833 .loc 1 1109 0 + 834 004a 0268 ldr r2, [r0] + 835 004c 9368 ldr r3, [r2, #8] + 836 004e 0331 adds r1, r1, #3 + 837 0050 FF31 adds r1, r1, #255 + 838 0052 8B43 bics r3, r1 + 839 0054 9360 str r3, [r2, #8] +1112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 840 .loc 1 1112 0 + 841 0056 0268 ldr r2, [r0] + 842 0058 9368 ldr r3, [r2, #8] + 843 005a 3F31 adds r1, r1, #63 + 844 005c 8B43 bics r3, r1 + 845 005e 9360 str r3, [r2, #8] + ARM GAS /tmp/cc7An1gz.s page 36 + + + 846 0060 DDE7 b .L59 + 847 .L60: +1096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 848 .loc 1 1096 0 + 849 0062 0220 movs r0, #2 + 850 .LVL70: + 851 0064 DFE7 b .L57 + 852 .L64: + 853 0066 C046 .align 2 + 854 .L63: + 855 0068 FFFEFFFF .word -257 + 856 .cfi_endproc + 857 .LFE52: + 859 .section .text.HAL_UART_DMAResume,"ax",%progbits + 860 .align 1 + 861 .global HAL_UART_DMAResume + 862 .syntax unified + 863 .code 16 + 864 .thumb_func + 865 .fpu softvfp + 867 HAL_UART_DMAResume: + 868 .LFB53: +1120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Resume the DMA Transfer. +1123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +1127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 869 .loc 1 1127 0 + 870 .cfi_startproc + 871 @ args = 0, pretend = 0, frame = 0 + 872 @ frame_needed = 0, uses_anonymous_args = 0 + 873 @ link register save eliminated. + 874 .LVL71: +1128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); + 875 .loc 1 1129 0 + 876 0000 6823 movs r3, #104 + 877 0002 C35C ldrb r3, [r0, r3] + 878 0004 012B cmp r3, #1 + 879 0006 29D0 beq .L69 + 880 .loc 1 1129 0 is_stmt 0 discriminator 2 + 881 0008 6823 movs r3, #104 + 882 000a 0122 movs r2, #1 + 883 000c C254 strb r2, [r0, r3] +1130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->gState == HAL_UART_STATE_BUSY_TX) + 884 .loc 1 1131 0 is_stmt 1 discriminator 2 + 885 000e 0133 adds r3, r3, #1 + 886 0010 C35C ldrb r3, [r0, r3] + 887 0012 212B cmp r3, #33 + 888 0014 08D0 beq .L70 + 889 .L67: +1132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART DMA Tx request */ + ARM GAS /tmp/cc7An1gz.s page 37 + + +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->RxState == HAL_UART_STATE_BUSY_RX) + 890 .loc 1 1136 0 + 891 0016 6A23 movs r3, #106 + 892 0018 C35C ldrb r3, [r0, r3] + 893 001a 222B cmp r3, #34 + 894 001c 0AD0 beq .L71 + 895 .L68: +1137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Overrun flag before resuming the Rx transfer */ +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +1140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +1144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART DMA Rx request */ +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +1150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); + 896 .loc 1 1150 0 + 897 001e 6823 movs r3, #104 + 898 0020 0022 movs r2, #0 + 899 0022 C254 strb r2, [r0, r3] +1151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 900 .loc 1 1152 0 + 901 0024 0020 movs r0, #0 + 902 .LVL72: + 903 .L66: +1153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 904 .loc 1 1153 0 + 905 @ sp needed + 906 0026 7047 bx lr + 907 .LVL73: + 908 .L70: +1134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 909 .loc 1 1134 0 + 910 0028 0268 ldr r2, [r0] + 911 002a 9368 ldr r3, [r2, #8] + 912 002c 8021 movs r1, #128 + 913 002e 0B43 orrs r3, r1 + 914 0030 9360 str r3, [r2, #8] + 915 0032 F0E7 b .L67 + 916 .L71: +1139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 917 .loc 1 1139 0 + 918 0034 0368 ldr r3, [r0] + 919 0036 0822 movs r2, #8 + 920 0038 1A62 str r2, [r3, #32] +1142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 921 .loc 1 1142 0 + 922 003a 0268 ldr r2, [r0] + 923 003c 1168 ldr r1, [r2] + ARM GAS /tmp/cc7An1gz.s page 38 + + + 924 003e 8023 movs r3, #128 + 925 0040 5B00 lsls r3, r3, #1 + 926 0042 0B43 orrs r3, r1 + 927 0044 1360 str r3, [r2] +1143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 928 .loc 1 1143 0 + 929 0046 0268 ldr r2, [r0] + 930 0048 9368 ldr r3, [r2, #8] + 931 004a 0121 movs r1, #1 + 932 004c 0B43 orrs r3, r1 + 933 004e 9360 str r3, [r2, #8] +1146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 934 .loc 1 1146 0 + 935 0050 0268 ldr r2, [r0] + 936 0052 9368 ldr r3, [r2, #8] + 937 0054 3F31 adds r1, r1, #63 + 938 0056 0B43 orrs r3, r1 + 939 0058 9360 str r3, [r2, #8] + 940 005a E0E7 b .L68 + 941 .L69: +1129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 942 .loc 1 1129 0 + 943 005c 0220 movs r0, #2 + 944 .LVL74: + 945 005e E2E7 b .L66 + 946 .cfi_endproc + 947 .LFE53: + 949 .section .text.HAL_UART_DMAStop,"ax",%progbits + 950 .align 1 + 951 .global HAL_UART_DMAStop + 952 .syntax unified + 953 .code 16 + 954 .thumb_func + 955 .fpu softvfp + 957 HAL_UART_DMAStop: + 958 .LFB54: +1154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Stop the DMA Transfer. +1157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +1161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 959 .loc 1 1161 0 + 960 .cfi_startproc + 961 @ args = 0, pretend = 0, frame = 0 + 962 @ frame_needed = 0, uses_anonymous_args = 0 + 963 .LVL75: + 964 0000 10B5 push {r4, lr} + 965 .LCFI5: + 966 .cfi_def_cfa_offset 8 + 967 .cfi_offset 4, -8 + 968 .cfi_offset 14, -4 + 969 0002 0400 movs r4, r0 +1162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application +1163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + ARM GAS /tmp/cc7An1gz.s page 39 + + +1164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: +1165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete +1166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of +1167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the stream and the corresponding call back is executed. */ +1168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + 970 .loc 1 1170 0 + 971 0004 6923 movs r3, #105 + 972 0006 C35C ldrb r3, [r0, r3] + 973 0008 212B cmp r3, #33 + 974 000a 05D0 beq .L77 + 975 .LVL76: + 976 .L73: +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) +1172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Tx channel */ +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmatx); +1179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndTxTransfer(huart); +1182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + 977 .loc 1 1185 0 + 978 000c 6A23 movs r3, #106 + 979 000e E35C ldrb r3, [r4, r3] + 980 0010 222B cmp r3, #34 + 981 0012 17D0 beq .L78 + 982 .L75: +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) +1187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmarx); +1194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndRxTransfer(huart); +1197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 983 .loc 1 1200 0 + 984 0014 0020 movs r0, #0 + 985 @ sp needed + 986 .LVL77: + 987 0016 10BD pop {r4, pc} + 988 .LVL78: + 989 .L77: + ARM GAS /tmp/cc7An1gz.s page 40 + + +1171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + 990 .loc 1 1171 0 discriminator 1 + 991 0018 0368 ldr r3, [r0] + 992 001a 9A68 ldr r2, [r3, #8] +1170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + 993 .loc 1 1170 0 discriminator 1 + 994 001c 1206 lsls r2, r2, #24 + 995 001e F5D5 bpl .L73 +1173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 996 .loc 1 1173 0 + 997 0020 9A68 ldr r2, [r3, #8] + 998 0022 8021 movs r1, #128 + 999 0024 8A43 bics r2, r1 + 1000 0026 9A60 str r2, [r3, #8] +1176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1001 .loc 1 1176 0 + 1002 0028 006E ldr r0, [r0, #96] + 1003 .LVL79: + 1004 002a 0028 cmp r0, #0 + 1005 002c 01D0 beq .L74 +1178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1006 .loc 1 1178 0 + 1007 002e FFF7FEFF bl HAL_DMA_Abort + 1008 .LVL80: + 1009 .L74: + 1010 .LBB14: + 1011 .LBB15: +1201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing transfers (blocking mode). +1204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_ +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; + ARM GAS /tmp/cc7An1gz.s page 41 + + +1231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmatx); +1233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmarx); +1249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +1255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Handle ErrorCode to No Error */ +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (blocking mode). +1271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +1285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + ARM GAS /tmp/cc7An1gz.s page 42 + + +1288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmatx); +1299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Tx transfer counter */ +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +1304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (blocking mode). +1313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +1315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +1317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_DMA_Abort(huart->hdmarx); +1342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 43 + + +1345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Rx transfer counter */ +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +1347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing transfers (Interrupt mode). +1359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +1368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t abortcplt = 1; +1374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_ +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks sh +1380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** before any call to DMA Abort functions */ +1381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DMA Tx Handle is valid */ +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. +1385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Otherwise, set it to NULL */ +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; +1389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DMA Rx Handle is valid */ +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. +1399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Otherwise, set it to NULL */ +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 44 + + +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; +1403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable DMA Tx at UART level */ +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART Tx DMA Abort callback has already been initialised : +1420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort DMA TX */ +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +1424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** abortcplt = 0; +1430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART Rx DMA Abort callback has already been initialised : +1443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort DMA RX */ +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +1447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** abortcplt = 1; +1450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** abortcplt = 0; +1454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if no DMA abort complete callback execution is required => call user Abort Complete callback * + ARM GAS /tmp/cc7An1gz.s page 45 + + +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (abortcplt == 1) +1460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +1464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset errorCode */ +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +1470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +1477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (Interrupt mode). +1484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +1493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +1500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +1508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback : +1510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; +1512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort DMA TX */ +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +1515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 46 + + +1516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback(huart->hdmatx); +1518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Tx transfer counter */ +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +1524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +1530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Tx transfer counter */ +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +1536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +1542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (Interrupt mode). +1549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +1551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * This procedure performs following operations : +1552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +1553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - Set handle State to READY +1556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +1558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + ARM GAS /tmp/cc7An1gz.s page 47 + + +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback : +1576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; +1578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort DMA RX */ +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +1581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +1584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Rx transfer counter */ +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +1590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_F +1593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +1599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset Rx transfer counter */ +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +1605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +1608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +1614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Handle UART interrupt request. +1621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); +1628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t cr3its; +1629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t errorflags; + ARM GAS /tmp/cc7An1gz.s page 48 + + +1630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* If no error occurs */ +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (errorflags == RESET) +1634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART in mode Receiver ---------------------------------------------------*/ +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +1637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_Receive_IT(huart); +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +1640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* If some errors occur */ +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** cr3its = READ_REG(huart->Instance->CR3); +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if( (errorflags != RESET) +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** && ( ((cr3its & USART_CR3_EIE) != RESET) +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +1648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART parity error interrupt occurred -------------------------------------*/ +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) +1651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); +1653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_PE; +1655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART frame error interrupt occurred --------------------------------------*/ +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) +1659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); +1661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_FE; +1663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART noise error interrupt occurred --------------------------------------*/ +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) +1667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); +1669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_NE; +1671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART Over-Run interrupt occurred -----------------------------------------*/ +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_ORE) != RESET) && +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +1676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); +1678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_ORE; +1680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call UART Error Call back function if need be --------------------------*/ +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->ErrorCode != HAL_UART_ERROR_NONE) +1684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART in mode Receiver ---------------------------------------------------*/ +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + ARM GAS /tmp/cc7An1gz.s page 49 + + +1687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_Receive_IT(huart); +1689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* If Overrun error occurs, or if any error occurs in DMA mode reception, +1692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** consider error as blocking */ +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) +1695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Blocking error : transfer is aborted +1697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Set the UART state ready to be able to start again the process, +1698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ +1699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndRxTransfer(huart); +1700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +1708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART DMA Abort callback : +1710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; +1712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Abort DMA RX */ +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +1715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +1718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user error callback */ +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +1724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user error callback */ +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +1730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +1733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Non Blocking error : transfer could go on. +1735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** Error is notified to user through user error callback */ +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +1741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } /* End if some error occurs */ +1743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 50 + + +1744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) +1746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); +1748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART state ready to be able to start again the process */ +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UARTEx_WakeupCallback(huart); +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +1753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART in mode Transmitter ------------------------------------------------*/ +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +1757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_Transmit_IT(huart); +1759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +1760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* UART in mode Transmitter (transmission end) -----------------------------*/ +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) +1764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndTransmit_IT(huart); +1766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +1767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Tx Transfer completed callback. +1773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_TxCpltCallback can be implemented in the user file. +1783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Tx Half Transfer completed callback. +1788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +1797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_TxHalfCpltCallback can be implemented in the user file. +1798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 51 + + +1801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Rx Transfer completed callback. +1803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_RxCpltCallback can be implemented in the user file. +1813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Rx Half Transfer completed callback. +1818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +1827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_RxHalfCpltCallback can be implemented in the user file. +1828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART error callback. +1833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_ErrorCallback can be implemented in the user file. +1843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART Abort Complete callback. +1848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_AbortCpltCallback can be implemented in the user file. + ARM GAS /tmp/cc7An1gz.s page 52 + + +1858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART Abort Complete callback. +1863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. +1873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1875:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1876:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1877:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART Abort Receive Complete callback. +1878:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +1879:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1880:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1881:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1883:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +1884:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UNUSED(huart); +1885:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1886:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +1887:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. +1888:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1890:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1891:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1892:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} +1893:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1894:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1895:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions +1896:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART control functions +1897:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * +1898:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @verbatim +1899:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== +1900:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ##### Peripheral Control functions ##### +1901:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** =============================================================================== +1902:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] +1903:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** This subsection provides a set of functions allowing to control the UART. +1904:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode +1905:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode +1906:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode +1907:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) UART_SetConfig() API configures the UART peripheral +1908:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features +1909:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization +1910:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter +1911:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver +1912:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) HAL_LIN_SendBreak() API transmits the break characters +1913:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @endverbatim +1914:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ + ARM GAS /tmp/cc7An1gz.s page 53 + + +1915:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1916:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1917:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1918:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Enable UART in mute mode (does not mean UART enters mute mode; +1919:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). +1920:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1921:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1922:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1923:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1925:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); +1927:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +1929:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1930:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable USART mute mode by setting the MME bit in the CR1 register */ +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_MME); +1932:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1934:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1937:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1938:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1939:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Disable UART mute mode (does not mean the UART actually exits mute mode +1940:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * as it may not have been in mute mode at this very moment). +1941:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1942:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1943:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1944:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1946:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); +1948:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +1950:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1951:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable USART mute mode by clearing the MME bit in the CR1 register */ +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); +1953:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1955:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1958:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1959:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1960:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Enter UART mute mode (means UART actually enters mute mode). +1961:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. +1962:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1963:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +1964:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1965:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1969:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1970:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1971:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Enable the UART transmitter and disable the UART receiver. + ARM GAS /tmp/cc7An1gz.s page 54 + + +1972:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1973:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +1974:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1975:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +1977:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +1980:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1981:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear TE and RE bits */ +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); +1983:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TE); +1985:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1987:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1988:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); +1990:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +1993:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +1994:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +1995:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Enable the UART receiver and disable the UART transmitter. +1996:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +1997:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status. +1998:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +1999:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2001:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2004:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2005:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear TE and RE bits */ +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); +2007:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_RE); +2009:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2011:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); +2013:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2016:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2017:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2018:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2019:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Transmit break characters. +2020:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +2021:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2022:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2023:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2025:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ +2026:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); +2027:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2028:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + ARM GAS /tmp/cc7An1gz.s page 55 + + +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_LOCK(huart); +2030:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2032:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2033:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Send break characters */ +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->RQR |= UART_SENDBREAK_REQUEST; +2035:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2037:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2038:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); +2040:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2043:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2044:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2045:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2046:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} +2047:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2048:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2049:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions +2050:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief UART Peripheral State functions +2051:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * +2052:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @verbatim +2053:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ============================================================================== +2054:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ##### Peripheral State and Error functions ##### +2055:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ============================================================================== +2056:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** [..] +2057:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** This subsection provides functions allowing to : +2058:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Return the UART handle state. +2059:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (+) Return the UART handle error code +2060:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2061:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** @endverbatim +2062:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ +2063:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2064:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2065:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2066:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Return the UART handle state. +2067:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2068:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * the configuration information for the specified UART. +2069:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL state +2070:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2071:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2073:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t temp1= 0x00U, temp2 = 0x00U; +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** temp1 = huart->gState; +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** temp2 = huart->RxState; +2076:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return (HAL_UART_StateTypeDef)(temp1 | temp2); +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2079:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2080:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2081:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Return the UART handle error code. +2082:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2083:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * the configuration information for the specified UART. +2084:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval UART Error Code +2085:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ + ARM GAS /tmp/cc7An1gz.s page 56 + + +2086:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return huart->ErrorCode; +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2090:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2091:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} +2092:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2093:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2094:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2095:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @} +2096:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2097:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2098:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** @defgroup UART_Private_Functions UART Private Functions +2099:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @{ +2100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Configure the UART peripheral. +2104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +2105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tmpreg = 0x00000000U; +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; +2111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t brrtemp = 0x0000U; +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t usartdiv = 0x0000U; +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; +2114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ +2116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); +2117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_INSTANCE_LOWPOWER(huart)) +2119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); +2121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); +2125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); +2126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_PARITY(huart->Init.Parity)); +2129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_MODE(huart->Init.Mode)); +2130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); +2131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +2132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /*-------------------------- USART CR1 Configuration -----------------------*/ +2135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure +2136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * the UART Word Length, Parity, Mode and oversampling: +2137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * set the M bits according to huart->Init.WordLength value +2138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * set PCE and PS bits according to huart->Init.Parity value +2139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * set TE and RE bits according to huart->Init.Mode value +2140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * set OVER8 bit according to huart->Init.OverSampling value */ +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); + ARM GAS /tmp/cc7An1gz.s page 57 + + +2143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /*-------------------------- USART CR2 Configuration -----------------------*/ +2145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Configure the UART Stop Bits: Set STOP[13:12] bits according +2146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * to huart->Init.StopBits value */ +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); +2148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /*-------------------------- USART CR3 Configuration -----------------------*/ +2150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Configure +2151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - UART HardWare Flow Control: set CTSE and RTSE bits according +2152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * to huart->Init.HwFlowCtl value +2153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * - one-bit sampling method versus three samples' majority rule according +2154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * to huart->Init.OneBitSampling (not applicable to LPUART) */ +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.HwFlowCtl; +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (!(UART_INSTANCE_LOWPOWER(huart))) +2157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg |= huart->Init.OneBitSampling; +2159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); +2161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /*-------------------------- USART BRR Configuration -----------------------*/ +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_GETCLOCKSOURCE(huart, clocksource); +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); +2165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check LPUART instance */ +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_INSTANCE_LOWPOWER(huart)) +2168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Retrieve frequency clock */ +2170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = 0; +2171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** switch (clocksource) +2173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK1: +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = HAL_RCC_GetPCLK1Freq(); +2176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t) (HSI_VALUE >> 2U); +2181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t) HSI_VALUE; +2185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_SYSCLK: +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = HAL_RCC_GetSysClockFreq(); +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +2191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t) LSE_VALUE; +2192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_UNDEFINED: +2194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** default: +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ret = HAL_ERROR; +2196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if proper clock source reported */ + ARM GAS /tmp/cc7An1gz.s page 58 + + +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (tmpreg != 0) +2201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ( (tmpreg < (3 * huart->Init.BaudRate) ) || +2204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (tmpreg > (4096 * huart->Init.BaudRate) )) +2205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ret = HAL_ERROR; +2207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmpreg = (uint32_t)(UART_DIV_LPUART(tmpreg, huart->Init.BaudRate)); +2211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX)) +2213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = tmpreg; +2215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ret = HAL_ERROR; +2219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } /* if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate +2221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } /* if (tmpreg != 0) */ +2222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check UART Over Sampling to set Baud Rate Register */ +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) +2225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** switch (clocksource) +2227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK1: +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(frequency, huart->Init.BaudRate)); +2230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: +2232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> 2U), huart->Init.BaudRate)); +2238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); +2242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_SYSCLK: +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +2246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_UNDEFINED: +2251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** default: +2252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ret = HAL_ERROR; +2253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** brrtemp = usartdiv & 0xFFF0U; + ARM GAS /tmp/cc7An1gz.s page 59 + + +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** brrtemp |= (uint16_t)((uint16_t)(usartdiv & (uint16_t)0x000FU) >> (uint16_t)1U); +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = brrtemp; +2259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** switch (clocksource) +2263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK1: +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.Bau +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: +2268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.Bau +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> 2U), huart->Init.BaudRa +2274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +2278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_SYSCLK: +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init. +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +2284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_UNDEFINED: +2287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** default: +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** ret = HAL_ERROR; +2289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; +2290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return ret; +2294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Configure the UART peripheral advanced features. +2299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart: UART handle. +2300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +2303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ +2305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); +2306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure TX pin active level inversion */ +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) +2309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); +2312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 60 + + +2314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure RX pin active level inversion */ +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) +2316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); +2319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure data inversion */ +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) +2323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); +2325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); +2326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure RX/TX pins swap */ +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) +2330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); +2332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); +2333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure RX overrun detection disabling */ +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) +2337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); +2339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); +2340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure DMA disabling on reception error */ +2343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) +2344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); +2347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure auto Baud rate detection scheme */ +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) +2351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); +2353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); +2354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); +2355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ +2356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) +2357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); +2360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* if required, configure MSB first on communication line */ +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) +2365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); +2367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); +2368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 61 + + +2371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Check the UART Idle State. +2373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tickstart = 0; +2379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Initialize the UART ErrorCode */ +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +2382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Init tickstart for timeout managment*/ +2384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tickstart = HAL_GetTick(); +2385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check if the Transmitter is enabled */ +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) +2388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Wait until TEACK flag is set */ +2390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE +2391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Timeout occurred */ +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; +2394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check if the Receiver is enabled */ +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) +2398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Wait until REACK flag is set */ +2400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE +2401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Timeout occurred */ +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; +2404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Initialize the UART State */ +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +2412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); +2413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Handle UART Communication Timeout. +2419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Flag Specifies the UART flag to check +2421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Status Flag status (SET or RESET) +2422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Tickstart Tick start value +2423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param Timeout Timeout duration +2424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 62 + + +2428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Wait until flag is set */ +2429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) +2430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check for the Timeout */ +2432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(Timeout != HAL_MAX_DELAY) +2433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) +2435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for t +2437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +2438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +2439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ +2444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UNLOCK(huart); +2445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; +2446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit compl +2455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +2459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ +2461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + 1012 .loc 1 2461 0 + 1013 0032 2268 ldr r2, [r4] + 1014 0034 1368 ldr r3, [r2] + 1015 0036 C021 movs r1, #192 + 1016 0038 8B43 bics r3, r1 + 1017 003a 1360 str r3, [r2] +2462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ +2464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 1018 .loc 1 2464 0 + 1019 003c 6923 movs r3, #105 + 1020 003e 2022 movs r2, #32 + 1021 0040 E254 strb r2, [r4, r3] + 1022 0042 E3E7 b .L73 + 1023 .LVL81: + 1024 .L78: + 1025 .LBE15: + 1026 .LBE14: +1186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1027 .loc 1 1186 0 discriminator 1 + 1028 0044 2368 ldr r3, [r4] + 1029 0046 9A68 ldr r2, [r3, #8] +1185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + ARM GAS /tmp/cc7An1gz.s page 63 + + + 1030 .loc 1 1185 0 discriminator 1 + 1031 0048 5206 lsls r2, r2, #25 + 1032 004a E3D5 bpl .L75 +1188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1033 .loc 1 1188 0 + 1034 004c 9A68 ldr r2, [r3, #8] + 1035 004e 4021 movs r1, #64 + 1036 0050 8A43 bics r2, r1 + 1037 0052 9A60 str r2, [r3, #8] +1191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1038 .loc 1 1191 0 + 1039 0054 606E ldr r0, [r4, #100] + 1040 0056 0028 cmp r0, #0 + 1041 0058 01D0 beq .L76 +1193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1042 .loc 1 1193 0 + 1043 005a FFF7FEFF bl HAL_DMA_Abort + 1044 .LVL82: + 1045 .L76: + 1046 .LBB16: + 1047 .LBB17: +2465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception comp +2470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +2474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 1048 .loc 1 2476 0 + 1049 005e 2268 ldr r2, [r4] + 1050 0060 1368 ldr r3, [r2] + 1051 0062 0649 ldr r1, .L79 + 1052 0064 0B40 ands r3, r1 + 1053 0066 1360 str r3, [r2] +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1054 .loc 1 2477 0 + 1055 0068 2268 ldr r2, [r4] + 1056 006a 9368 ldr r3, [r2, #8] + 1057 006c 2331 adds r1, r1, #35 + 1058 006e FF31 adds r1, r1, #255 + 1059 0070 8B43 bics r3, r1 + 1060 0072 9360 str r3, [r2, #8] +2478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 1061 .loc 1 2480 0 + 1062 0074 6A23 movs r3, #106 + 1063 0076 2022 movs r2, #32 + 1064 0078 E254 strb r2, [r4, r3] + 1065 007a CBE7 b .L75 + 1066 .L80: + 1067 .align 2 + ARM GAS /tmp/cc7An1gz.s page 64 + + + 1068 .L79: + 1069 007c DFFEFFFF .word -289 + 1070 .LBE17: + 1071 .LBE16: + 1072 .cfi_endproc + 1073 .LFE54: + 1075 .section .text.HAL_UART_Abort,"ax",%progbits + 1076 .align 1 + 1077 .global HAL_UART_Abort + 1078 .syntax unified + 1079 .code 16 + 1080 .thumb_func + 1081 .fpu softvfp + 1083 HAL_UART_Abort: + 1084 .LFB55: +1215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 1085 .loc 1 1215 0 + 1086 .cfi_startproc + 1087 @ args = 0, pretend = 0, frame = 0 + 1088 @ frame_needed = 0, uses_anonymous_args = 0 + 1089 .LVL83: + 1090 0000 10B5 push {r4, lr} + 1091 .LCFI6: + 1092 .cfi_def_cfa_offset 8 + 1093 .cfi_offset 4, -8 + 1094 .cfi_offset 14, -4 + 1095 0002 0400 movs r4, r0 +1217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1096 .loc 1 1217 0 + 1097 0004 0268 ldr r2, [r0] + 1098 0006 1368 ldr r3, [r2] + 1099 0008 1C49 ldr r1, .L84 + 1100 000a 0B40 ands r3, r1 + 1101 000c 1360 str r3, [r2] +1218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1102 .loc 1 1218 0 + 1103 000e 0268 ldr r2, [r0] + 1104 0010 9368 ldr r3, [r2, #8] + 1105 0012 E331 adds r1, r1, #227 + 1106 0014 FF31 adds r1, r1, #255 + 1107 0016 8B43 bics r3, r1 + 1108 0018 9360 str r3, [r2, #8] +1221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1109 .loc 1 1221 0 + 1110 001a 0368 ldr r3, [r0] + 1111 001c 9A68 ldr r2, [r3, #8] + 1112 001e 1206 lsls r2, r2, #24 + 1113 0020 0BD5 bpl .L82 +1223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1114 .loc 1 1223 0 + 1115 0022 9A68 ldr r2, [r3, #8] + 1116 0024 7F31 adds r1, r1, #127 + 1117 0026 8A43 bics r2, r1 + 1118 0028 9A60 str r2, [r3, #8] +1226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1119 .loc 1 1226 0 + 1120 002a 036E ldr r3, [r0, #96] + ARM GAS /tmp/cc7An1gz.s page 65 + + + 1121 002c 002B cmp r3, #0 + 1122 002e 04D0 beq .L82 +1230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1123 .loc 1 1230 0 + 1124 0030 0022 movs r2, #0 + 1125 0032 9A63 str r2, [r3, #56] +1232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1126 .loc 1 1232 0 + 1127 0034 006E ldr r0, [r0, #96] + 1128 .LVL84: + 1129 0036 FFF7FEFF bl HAL_DMA_Abort + 1130 .LVL85: + 1131 .L82: +1237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1132 .loc 1 1237 0 + 1133 003a 2368 ldr r3, [r4] + 1134 003c 9A68 ldr r2, [r3, #8] + 1135 003e 5206 lsls r2, r2, #25 + 1136 0040 0BD5 bpl .L83 +1239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1137 .loc 1 1239 0 + 1138 0042 9A68 ldr r2, [r3, #8] + 1139 0044 4021 movs r1, #64 + 1140 0046 8A43 bics r2, r1 + 1141 0048 9A60 str r2, [r3, #8] +1242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1142 .loc 1 1242 0 + 1143 004a 636E ldr r3, [r4, #100] + 1144 004c 002B cmp r3, #0 + 1145 004e 04D0 beq .L83 +1246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1146 .loc 1 1246 0 + 1147 0050 0022 movs r2, #0 + 1148 0052 9A63 str r2, [r3, #56] +1248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1149 .loc 1 1248 0 + 1150 0054 606E ldr r0, [r4, #100] + 1151 0056 FFF7FEFF bl HAL_DMA_Abort + 1152 .LVL86: + 1153 .L83: +1253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; + 1154 .loc 1 1253 0 + 1155 005a 0023 movs r3, #0 + 1156 005c 5222 movs r2, #82 + 1157 005e A352 strh r3, [r4, r2] +1254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1158 .loc 1 1254 0 + 1159 0060 0832 adds r2, r2, #8 + 1160 0062 A352 strh r3, [r4, r2] +1257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1161 .loc 1 1257 0 + 1162 0064 2268 ldr r2, [r4] + 1163 0066 0F21 movs r1, #15 + 1164 0068 1162 str r1, [r2, #32] +1260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 1165 .loc 1 1260 0 + 1166 006a 2022 movs r2, #32 + ARM GAS /tmp/cc7An1gz.s page 66 + + + 1167 006c 5A31 adds r1, r1, #90 + 1168 006e 6254 strb r2, [r4, r1] +1261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1169 .loc 1 1261 0 + 1170 0070 0131 adds r1, r1, #1 + 1171 0072 6254 strb r2, [r4, r1] +1264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1172 .loc 1 1264 0 + 1173 0074 E366 str r3, [r4, #108] +1267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1174 .loc 1 1267 0 + 1175 0076 0020 movs r0, #0 + 1176 @ sp needed + 1177 .LVL87: + 1178 0078 10BD pop {r4, pc} + 1179 .L85: + 1180 007a C046 .align 2 + 1181 .L84: + 1182 007c 1FFEFFFF .word -481 + 1183 .cfi_endproc + 1184 .LFE55: + 1186 .section .text.HAL_UART_AbortTransmit,"ax",%progbits + 1187 .align 1 + 1188 .global HAL_UART_AbortTransmit + 1189 .syntax unified + 1190 .code 16 + 1191 .thumb_func + 1192 .fpu softvfp + 1194 HAL_UART_AbortTransmit: + 1195 .LFB56: +1282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ + 1196 .loc 1 1282 0 + 1197 .cfi_startproc + 1198 @ args = 0, pretend = 0, frame = 0 + 1199 @ frame_needed = 0, uses_anonymous_args = 0 + 1200 .LVL88: + 1201 0000 10B5 push {r4, lr} + 1202 .LCFI7: + 1203 .cfi_def_cfa_offset 8 + 1204 .cfi_offset 4, -8 + 1205 .cfi_offset 14, -4 + 1206 0002 0400 movs r4, r0 +1284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1207 .loc 1 1284 0 + 1208 0004 0268 ldr r2, [r0] + 1209 0006 1368 ldr r3, [r2] + 1210 0008 C021 movs r1, #192 + 1211 000a 8B43 bics r3, r1 + 1212 000c 1360 str r3, [r2] +1287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1213 .loc 1 1287 0 + 1214 000e 0368 ldr r3, [r0] + 1215 0010 9A68 ldr r2, [r3, #8] + 1216 0012 1206 lsls r2, r2, #24 + 1217 0014 0BD5 bpl .L87 +1289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1218 .loc 1 1289 0 + ARM GAS /tmp/cc7An1gz.s page 67 + + + 1219 0016 9A68 ldr r2, [r3, #8] + 1220 0018 4039 subs r1, r1, #64 + 1221 001a 8A43 bics r2, r1 + 1222 001c 9A60 str r2, [r3, #8] +1292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1223 .loc 1 1292 0 + 1224 001e 036E ldr r3, [r0, #96] + 1225 0020 002B cmp r3, #0 + 1226 0022 04D0 beq .L87 +1296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1227 .loc 1 1296 0 + 1228 0024 0022 movs r2, #0 + 1229 0026 9A63 str r2, [r3, #56] +1298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1230 .loc 1 1298 0 + 1231 0028 006E ldr r0, [r0, #96] + 1232 .LVL89: + 1233 002a FFF7FEFF bl HAL_DMA_Abort + 1234 .LVL90: + 1235 .L87: +1303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1236 .loc 1 1303 0 + 1237 002e 5223 movs r3, #82 + 1238 0030 0022 movs r2, #0 + 1239 0032 E252 strh r2, [r4, r3] +1306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1240 .loc 1 1306 0 + 1241 0034 1733 adds r3, r3, #23 + 1242 0036 2032 adds r2, r2, #32 + 1243 0038 E254 strb r2, [r4, r3] +1309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1244 .loc 1 1309 0 + 1245 003a 0020 movs r0, #0 + 1246 @ sp needed + 1247 .LVL91: + 1248 003c 10BD pop {r4, pc} + 1249 .cfi_endproc + 1250 .LFE56: + 1252 .section .text.HAL_UART_AbortReceive,"ax",%progbits + 1253 .align 1 + 1254 .global HAL_UART_AbortReceive + 1255 .syntax unified + 1256 .code 16 + 1257 .thumb_func + 1258 .fpu softvfp + 1260 HAL_UART_AbortReceive: + 1261 .LFB57: +1324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 1262 .loc 1 1324 0 + 1263 .cfi_startproc + 1264 @ args = 0, pretend = 0, frame = 0 + 1265 @ frame_needed = 0, uses_anonymous_args = 0 + 1266 .LVL92: + 1267 0000 10B5 push {r4, lr} + 1268 .LCFI8: + 1269 .cfi_def_cfa_offset 8 + 1270 .cfi_offset 4, -8 + ARM GAS /tmp/cc7An1gz.s page 68 + + + 1271 .cfi_offset 14, -4 + 1272 0002 0400 movs r4, r0 +1326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1273 .loc 1 1326 0 + 1274 0004 0268 ldr r2, [r0] + 1275 0006 1368 ldr r3, [r2] + 1276 0008 1149 ldr r1, .L90 + 1277 000a 0B40 ands r3, r1 + 1278 000c 1360 str r3, [r2] +1327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1279 .loc 1 1327 0 + 1280 000e 0268 ldr r2, [r0] + 1281 0010 9368 ldr r3, [r2, #8] + 1282 0012 2331 adds r1, r1, #35 + 1283 0014 FF31 adds r1, r1, #255 + 1284 0016 8B43 bics r3, r1 + 1285 0018 9360 str r3, [r2, #8] +1330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1286 .loc 1 1330 0 + 1287 001a 0368 ldr r3, [r0] + 1288 001c 9A68 ldr r2, [r3, #8] + 1289 001e 5206 lsls r2, r2, #25 + 1290 0020 0BD5 bpl .L89 +1332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1291 .loc 1 1332 0 + 1292 0022 9A68 ldr r2, [r3, #8] + 1293 0024 3F31 adds r1, r1, #63 + 1294 0026 8A43 bics r2, r1 + 1295 0028 9A60 str r2, [r3, #8] +1335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1296 .loc 1 1335 0 + 1297 002a 436E ldr r3, [r0, #100] + 1298 002c 002B cmp r3, #0 + 1299 002e 04D0 beq .L89 +1339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1300 .loc 1 1339 0 + 1301 0030 0022 movs r2, #0 + 1302 0032 9A63 str r2, [r3, #56] +1341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1303 .loc 1 1341 0 + 1304 0034 406E ldr r0, [r0, #100] + 1305 .LVL93: + 1306 0036 FFF7FEFF bl HAL_DMA_Abort + 1307 .LVL94: + 1308 .L89: +1346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1309 .loc 1 1346 0 + 1310 003a 5A23 movs r3, #90 + 1311 003c 0022 movs r2, #0 + 1312 003e E252 strh r2, [r4, r3] +1349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1313 .loc 1 1349 0 + 1314 0040 2368 ldr r3, [r4] + 1315 0042 0F32 adds r2, r2, #15 + 1316 0044 1A62 str r2, [r3, #32] +1352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1317 .loc 1 1352 0 + ARM GAS /tmp/cc7An1gz.s page 69 + + + 1318 0046 6A23 movs r3, #106 + 1319 0048 1132 adds r2, r2, #17 + 1320 004a E254 strb r2, [r4, r3] +1355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1321 .loc 1 1355 0 + 1322 004c 0020 movs r0, #0 + 1323 @ sp needed + 1324 .LVL95: + 1325 004e 10BD pop {r4, pc} + 1326 .L91: + 1327 .align 2 + 1328 .L90: + 1329 0050 DFFEFFFF .word -289 + 1330 .cfi_endproc + 1331 .LFE57: + 1333 .section .text.HAL_UART_TxCpltCallback,"ax",%progbits + 1334 .align 1 + 1335 .weak HAL_UART_TxCpltCallback + 1336 .syntax unified + 1337 .code 16 + 1338 .thumb_func + 1339 .fpu softvfp + 1341 HAL_UART_TxCpltCallback: + 1342 .LFB62: +1777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 1343 .loc 1 1777 0 + 1344 .cfi_startproc + 1345 @ args = 0, pretend = 0, frame = 0 + 1346 @ frame_needed = 0, uses_anonymous_args = 0 + 1347 @ link register save eliminated. + 1348 .LVL96: +1784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1349 .loc 1 1784 0 + 1350 @ sp needed + 1351 0000 7047 bx lr + 1352 .cfi_endproc + 1353 .LFE62: + 1355 .section .text.UART_DMATransmitCplt,"ax",%progbits + 1356 .align 1 + 1357 .syntax unified + 1358 .code 16 + 1359 .thumb_func + 1360 .fpu softvfp + 1362 UART_DMATransmitCplt: + 1363 .LFB84: +2481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART transmit process complete callback. +2486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +2490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1364 .loc 1 2490 0 + 1365 .cfi_startproc + ARM GAS /tmp/cc7An1gz.s page 70 + + + 1366 @ args = 0, pretend = 0, frame = 0 + 1367 @ frame_needed = 0, uses_anonymous_args = 0 + 1368 .LVL97: + 1369 0000 10B5 push {r4, lr} + 1370 .LCFI9: + 1371 .cfi_def_cfa_offset 8 + 1372 .cfi_offset 4, -8 + 1373 .cfi_offset 14, -4 +2491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 1374 .loc 1 2491 0 + 1375 0002 836A ldr r3, [r0, #40] + 1376 .LVL98: +2492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DMA Normal mode */ +2494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + 1377 .loc 1 2494 0 + 1378 0004 0268 ldr r2, [r0] + 1379 0006 1268 ldr r2, [r2] + 1380 0008 9206 lsls r2, r2, #26 + 1381 000a 0DD4 bmi .L94 +2495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0U; + 1382 .loc 1 2496 0 + 1383 000c 5222 movs r2, #82 + 1384 000e 0021 movs r1, #0 + 1385 0010 9952 strh r1, [r3, r2] +2497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the DMA transfer for transmit request by resetting the DMAT bit +2499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the UART CR3 register */ +2500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 1386 .loc 1 2500 0 + 1387 0012 1968 ldr r1, [r3] + 1388 0014 8A68 ldr r2, [r1, #8] + 1389 0016 8020 movs r0, #128 + 1390 .LVL99: + 1391 0018 8243 bics r2, r0 + 1392 001a 8A60 str r2, [r1, #8] +2501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +2503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 1393 .loc 1 2503 0 + 1394 001c 1A68 ldr r2, [r3] + 1395 001e 1368 ldr r3, [r2] + 1396 .LVL100: + 1397 0020 4021 movs r1, #64 + 1398 0022 0B43 orrs r3, r1 + 1399 0024 1360 str r3, [r2] + 1400 .L93: +2504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DMA Circular mode */ +2506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); +2509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1401 .loc 1 2511 0 + ARM GAS /tmp/cc7An1gz.s page 71 + + + 1402 @ sp needed + 1403 0026 10BD pop {r4, pc} + 1404 .LVL101: + 1405 .L94: +2508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1406 .loc 1 2508 0 + 1407 0028 1800 movs r0, r3 + 1408 .LVL102: + 1409 002a FFF7FEFF bl HAL_UART_TxCpltCallback + 1410 .LVL103: + 1411 .loc 1 2511 0 + 1412 002e FAE7 b .L93 + 1413 .cfi_endproc + 1414 .LFE84: + 1416 .section .text.HAL_UART_TxHalfCpltCallback,"ax",%progbits + 1417 .align 1 + 1418 .weak HAL_UART_TxHalfCpltCallback + 1419 .syntax unified + 1420 .code 16 + 1421 .thumb_func + 1422 .fpu softvfp + 1424 HAL_UART_TxHalfCpltCallback: + 1425 .LFB63: +1792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 1426 .loc 1 1792 0 + 1427 .cfi_startproc + 1428 @ args = 0, pretend = 0, frame = 0 + 1429 @ frame_needed = 0, uses_anonymous_args = 0 + 1430 @ link register save eliminated. + 1431 .LVL104: +1799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1432 .loc 1 1799 0 + 1433 @ sp needed + 1434 0000 7047 bx lr + 1435 .cfi_endproc + 1436 .LFE63: + 1438 .section .text.UART_DMATxHalfCplt,"ax",%progbits + 1439 .align 1 + 1440 .syntax unified + 1441 .code 16 + 1442 .thumb_func + 1443 .fpu softvfp + 1445 UART_DMATxHalfCplt: + 1446 .LFB85: +2512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART transmit process half complete callback. +2515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +2519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1447 .loc 1 2519 0 + 1448 .cfi_startproc + 1449 @ args = 0, pretend = 0, frame = 0 + 1450 @ frame_needed = 0, uses_anonymous_args = 0 + 1451 .LVL105: + ARM GAS /tmp/cc7An1gz.s page 72 + + + 1452 0000 10B5 push {r4, lr} + 1453 .LCFI10: + 1454 .cfi_def_cfa_offset 8 + 1455 .cfi_offset 4, -8 + 1456 .cfi_offset 14, -4 +2520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 1457 .loc 1 2520 0 + 1458 0002 806A ldr r0, [r0, #40] + 1459 .LVL106: +2521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback(huart); + 1460 .loc 1 2522 0 + 1461 0004 FFF7FEFF bl HAL_UART_TxHalfCpltCallback + 1462 .LVL107: +2523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1463 .loc 1 2523 0 + 1464 @ sp needed + 1465 0008 10BD pop {r4, pc} + 1466 .cfi_endproc + 1467 .LFE85: + 1469 .section .text.HAL_UART_RxCpltCallback,"ax",%progbits + 1470 .align 1 + 1471 .weak HAL_UART_RxCpltCallback + 1472 .syntax unified + 1473 .code 16 + 1474 .thumb_func + 1475 .fpu softvfp + 1477 HAL_UART_RxCpltCallback: + 1478 .LFB64: +1807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 1479 .loc 1 1807 0 + 1480 .cfi_startproc + 1481 @ args = 0, pretend = 0, frame = 0 + 1482 @ frame_needed = 0, uses_anonymous_args = 0 + 1483 @ link register save eliminated. + 1484 .LVL108: +1814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1485 .loc 1 1814 0 + 1486 @ sp needed + 1487 0000 7047 bx lr + 1488 .cfi_endproc + 1489 .LFE64: + 1491 .section .text.UART_DMAReceiveCplt,"ax",%progbits + 1492 .align 1 + 1493 .syntax unified + 1494 .code 16 + 1495 .thumb_func + 1496 .fpu softvfp + 1498 UART_DMAReceiveCplt: + 1499 .LFB86: +2524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART receive process complete callback. +2527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) + ARM GAS /tmp/cc7An1gz.s page 73 + + +2531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1500 .loc 1 2531 0 + 1501 .cfi_startproc + 1502 @ args = 0, pretend = 0, frame = 0 + 1503 @ frame_needed = 0, uses_anonymous_args = 0 + 1504 .LVL109: + 1505 0000 10B5 push {r4, lr} + 1506 .LCFI11: + 1507 .cfi_def_cfa_offset 8 + 1508 .cfi_offset 4, -8 + 1509 .cfi_offset 14, -4 +2532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 1510 .loc 1 2532 0 + 1511 0002 836A ldr r3, [r0, #40] + 1512 .LVL110: +2533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* DMA Normal mode */ +2535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + 1513 .loc 1 2535 0 + 1514 0004 0268 ldr r2, [r0] + 1515 0006 1268 ldr r2, [r2] + 1516 0008 9206 lsls r2, r2, #26 + 1517 000a 15D4 bmi .L100 +2536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0U; + 1518 .loc 1 2537 0 + 1519 000c 5A22 movs r2, #90 + 1520 000e 0021 movs r1, #0 + 1521 0010 9952 strh r1, [r3, r2] +2538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +2540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 1522 .loc 1 2540 0 + 1523 0012 1968 ldr r1, [r3] + 1524 0014 0A68 ldr r2, [r1] + 1525 0016 0A48 ldr r0, .L101 + 1526 .LVL111: + 1527 0018 0240 ands r2, r0 + 1528 001a 0A60 str r2, [r1] +2541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1529 .loc 1 2541 0 + 1530 001c 1968 ldr r1, [r3] + 1531 001e 8A68 ldr r2, [r1, #8] + 1532 0020 0330 adds r0, r0, #3 + 1533 0022 FF30 adds r0, r0, #255 + 1534 0024 8243 bics r2, r0 + 1535 0026 8A60 str r2, [r1, #8] +2542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the DMA transfer for the receiver request by resetting the DMAR bit +2544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** in the UART CR3 register */ +2545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 1536 .loc 1 2545 0 + 1537 0028 1968 ldr r1, [r3] + 1538 002a 8A68 ldr r2, [r1, #8] + 1539 002c 3F30 adds r0, r0, #63 + 1540 002e 8243 bics r2, r0 + 1541 0030 8A60 str r2, [r1, #8] + ARM GAS /tmp/cc7An1gz.s page 74 + + +2546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +2548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 1542 .loc 1 2548 0 + 1543 0032 6A22 movs r2, #106 + 1544 0034 2021 movs r1, #32 + 1545 0036 9954 strb r1, [r3, r2] + 1546 .L100: +2549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); + 1547 .loc 1 2551 0 + 1548 0038 1800 movs r0, r3 + 1549 003a FFF7FEFF bl HAL_UART_RxCpltCallback + 1550 .LVL112: +2552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1551 .loc 1 2552 0 + 1552 @ sp needed + 1553 003e 10BD pop {r4, pc} + 1554 .L102: + 1555 .align 2 + 1556 .L101: + 1557 0040 FFFEFFFF .word -257 + 1558 .cfi_endproc + 1559 .LFE86: + 1561 .section .text.UART_Receive_IT,"ax",%progbits + 1562 .align 1 + 1563 .syntax unified + 1564 .code 16 + 1565 .thumb_func + 1566 .fpu softvfp + 1568 UART_Receive_IT: + 1569 .LFB96: +2553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART receive process half complete callback. +2556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +2560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); +2562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_RxHalfCpltCallback(huart); +2564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART communication error callback. +2568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma) +2572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); +2574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +2576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ( (huart->gState == HAL_UART_STATE_BUSY_TX) + ARM GAS /tmp/cc7An1gz.s page 75 + + +2577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) +2578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +2580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndTxTransfer(huart); +2581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) +2585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) +2586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +2588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndRxTransfer(huart); +2589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_DMA; +2592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART communication abort callback, when initiated by HAL services on Error +2597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (To be called at end of DMA Abort procedure following error occurrence). +2598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +2602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); +2604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +2605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +2606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user +2612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (To be called at end of DMA Tx Abort procedure following user abort request). +2613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +2614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * Abort still ongoing for Rx DMA Handle. +2615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +2619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); +2621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +2623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +2625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx != NULL) +2626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmarx->XferAbortCallback != NULL) +2628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +2630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba + ARM GAS /tmp/cc7An1gz.s page 76 + + +2634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +2635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +2636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset errorCode */ +2638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +2639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +2642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +2644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user Abort complete callback */ +2648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +2649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user +2654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (To be called at end of DMA Rx Abort procedure following user abort request). +2655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +2656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * Abort still ongoing for Tx DMA Handle. +2657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +2661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); +2663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +2665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx != NULL) +2668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->hdmatx->XferAbortCallback != NULL) +2670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; +2672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba +2676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +2677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +2678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Reset errorCode */ +2680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +2681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +2684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +2686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user Abort complete callback */ +2690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); + ARM GAS /tmp/cc7An1gz.s page 77 + + +2691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user by a call to +2696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) +2697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (This callback is executed at end of DMA Tx Abort procedure following user abort reques +2698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * and leads to user Tx Abort Complete callback execution). +2699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +2703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); +2705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; +2707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->gState to Ready */ +2709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user Abort complete callback */ +2712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +2713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user by a call to +2717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) +2718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * (This callback is executed at end of DMA Rx Abort procedure following user abort reques +2719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * and leads to user Rx Abort Complete callback execution). +2720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param hdma DMA handle. +2721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval None +2722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +2724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; +2728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +2731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +2733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Call user Abort complete callback */ +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +2737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Send an amount of data in interrupt mode. +2741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note Function is called under interruption only, once +2742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +2743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +2747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 78 + + +2748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; +2749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +2751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) +2752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->TxXferCount == 0U) +2754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART Transmit Data Register Empty Interrupt */ +2756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +2757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +2759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +2760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE +2766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmp = (uint16_t*) huart->pTxBuffPtr; +2768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); +2769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pTxBuffPtr += 2U; +2770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); +2774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount--; +2776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; +2783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Wrap up transmission in non-blocking mode. +2788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart pointer to a UART_HandleTypeDef structure that contains +2789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * the configuration information for the specified UART module. +2790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +2793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART Transmit Complete Interrupt */ +2795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); +2796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Tx process is ended, restore huart->gState to Ready */ +2798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); +2801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 79 + + +2805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** +2806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @brief Receive an amount of data in interrupt mode. +2807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @note Function is called under interruption only, once +2808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Receive_IT() +2809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @param huart UART handle. +2810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** * @retval HAL status +2811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** */ +2812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +2813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1570 .loc 1 2813 0 + 1571 .cfi_startproc + 1572 @ args = 0, pretend = 0, frame = 0 + 1573 @ frame_needed = 0, uses_anonymous_args = 0 + 1574 .LVL113: + 1575 0000 70B5 push {r4, r5, r6, lr} + 1576 .LCFI12: + 1577 .cfi_def_cfa_offset 16 + 1578 .cfi_offset 4, -16 + 1579 .cfi_offset 5, -12 + 1580 .cfi_offset 6, -8 + 1581 .cfi_offset 14, -4 +2814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; +2815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 1582 .loc 1 2815 0 + 1583 0002 5C23 movs r3, #92 + 1584 0004 C35A ldrh r3, [r0, r3] + 1585 .LVL114: +2816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t uhdata; +2817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +2819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(huart->RxState == HAL_UART_STATE_BUSY_RX) + 1586 .loc 1 2819 0 + 1587 0006 6A22 movs r2, #106 + 1588 0008 825C ldrb r2, [r0, r2] + 1589 000a 222A cmp r2, #34 + 1590 000c 32D1 bne .L104 +2820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 1591 .loc 1 2821 0 + 1592 000e 0268 ldr r2, [r0] + 1593 0010 526A ldr r2, [r2, #36] + 1594 0012 94B2 uxth r4, r2 + 1595 .LVL115: +2822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 1596 .loc 1 2822 0 + 1597 0014 8021 movs r1, #128 + 1598 0016 4901 lsls r1, r1, #5 + 1599 0018 8568 ldr r5, [r0, #8] + 1600 001a 8D42 cmp r5, r1 + 1601 001c 0ED0 beq .L109 + 1602 .L105: +2823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** tmp = (uint16_t*) huart->pRxBuffPtr ; +2825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); +2826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pRxBuffPtr +=2; +2827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else + ARM GAS /tmp/cc7An1gz.s page 80 + + +2829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + 1603 .loc 1 2830 0 + 1604 001e DBB2 uxtb r3, r3 + 1605 .LVL116: + 1606 0020 416D ldr r1, [r0, #84] + 1607 0022 4C1C adds r4, r1, #1 + 1608 .LVL117: + 1609 0024 4465 str r4, [r0, #84] + 1610 .LVL118: + 1611 0026 1340 ands r3, r2 + 1612 0028 0B70 strb r3, [r1] + 1613 .LVL119: + 1614 .L106: +2831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(--huart->RxXferCount == 0U) + 1615 .loc 1 2833 0 + 1616 002a 5A22 movs r2, #90 + 1617 002c 835A ldrh r3, [r0, r2] + 1618 002e 013B subs r3, r3, #1 + 1619 0030 9BB2 uxth r3, r3 + 1620 0032 8352 strh r3, [r0, r2] + 1621 0034 002B cmp r3, #0 + 1622 0036 0BD0 beq .L110 +2834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +2837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +2839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +2840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +2842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +2845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; +2847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_OK; + 1623 .loc 1 2849 0 + 1624 0038 0020 movs r0, #0 + 1625 .LVL120: + 1626 003a 21E0 b .L107 + 1627 .LVL121: + 1628 .L109: +2822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1629 .loc 1 2822 0 discriminator 1 + 1630 003c 0169 ldr r1, [r0, #16] + 1631 003e 0029 cmp r1, #0 + 1632 0040 EDD1 bne .L105 + 1633 .LVL122: +2825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pRxBuffPtr +=2; + 1634 .loc 1 2825 0 + 1635 0042 2340 ands r3, r4 + 1636 .LVL123: + ARM GAS /tmp/cc7An1gz.s page 81 + + + 1637 0044 426D ldr r2, [r0, #84] + 1638 0046 1380 strh r3, [r2] + 1639 .LVL124: +2826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1640 .loc 1 2826 0 + 1641 0048 436D ldr r3, [r0, #84] + 1642 004a 0233 adds r3, r3, #2 + 1643 004c 4365 str r3, [r0, #84] + 1644 004e ECE7 b .L106 + 1645 .LVL125: + 1646 .L110: +2836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1647 .loc 1 2836 0 + 1648 0050 0268 ldr r2, [r0] + 1649 0052 1368 ldr r3, [r2] + 1650 0054 0B49 ldr r1, .L111 + 1651 0056 0B40 ands r3, r1 + 1652 0058 1360 str r3, [r2] +2839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1653 .loc 1 2839 0 + 1654 005a 0268 ldr r2, [r0] + 1655 005c 9368 ldr r3, [r2, #8] + 1656 005e 2331 adds r1, r1, #35 + 1657 0060 FF31 adds r1, r1, #255 + 1658 0062 8B43 bics r3, r1 + 1659 0064 9360 str r3, [r2, #8] +2842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1660 .loc 1 2842 0 + 1661 0066 6A23 movs r3, #106 + 1662 0068 2022 movs r2, #32 + 1663 006a C254 strb r2, [r0, r3] +2844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1664 .loc 1 2844 0 + 1665 006c FFF7FEFF bl HAL_UART_RxCpltCallback + 1666 .LVL126: +2846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1667 .loc 1 2846 0 + 1668 0070 0020 movs r0, #0 + 1669 0072 05E0 b .L107 + 1670 .LVL127: + 1671 .L104: +2850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** else +2852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { +2853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +2854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 1672 .loc 1 2854 0 + 1673 0074 0268 ldr r2, [r0] + 1674 0076 9369 ldr r3, [r2, #24] + 1675 .LVL128: + 1676 0078 0821 movs r1, #8 + 1677 007a 0B43 orrs r3, r1 + 1678 007c 9361 str r3, [r2, #24] + 1679 .LVL129: +2855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** +2856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_BUSY; + 1680 .loc 1 2856 0 + ARM GAS /tmp/cc7An1gz.s page 82 + + + 1681 007e 0220 movs r0, #2 + 1682 .LVL130: + 1683 .L107: +2857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } +2858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1684 .loc 1 2858 0 + 1685 @ sp needed + 1686 0080 70BD pop {r4, r5, r6, pc} + 1687 .L112: + 1688 0082 C046 .align 2 + 1689 .L111: + 1690 0084 DFFEFFFF .word -289 + 1691 .cfi_endproc + 1692 .LFE96: + 1694 .section .text.HAL_UART_RxHalfCpltCallback,"ax",%progbits + 1695 .align 1 + 1696 .weak HAL_UART_RxHalfCpltCallback + 1697 .syntax unified + 1698 .code 16 + 1699 .thumb_func + 1700 .fpu softvfp + 1702 HAL_UART_RxHalfCpltCallback: + 1703 .LFB65: +1822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 1704 .loc 1 1822 0 + 1705 .cfi_startproc + 1706 @ args = 0, pretend = 0, frame = 0 + 1707 @ frame_needed = 0, uses_anonymous_args = 0 + 1708 @ link register save eliminated. + 1709 .LVL131: +1829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1710 .loc 1 1829 0 + 1711 @ sp needed + 1712 0000 7047 bx lr + 1713 .cfi_endproc + 1714 .LFE65: + 1716 .section .text.UART_DMARxHalfCplt,"ax",%progbits + 1717 .align 1 + 1718 .syntax unified + 1719 .code 16 + 1720 .thumb_func + 1721 .fpu softvfp + 1723 UART_DMARxHalfCplt: + 1724 .LFB87: +2560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 1725 .loc 1 2560 0 + 1726 .cfi_startproc + 1727 @ args = 0, pretend = 0, frame = 0 + 1728 @ frame_needed = 0, uses_anonymous_args = 0 + 1729 .LVL132: + 1730 0000 10B5 push {r4, lr} + 1731 .LCFI13: + 1732 .cfi_def_cfa_offset 8 + 1733 .cfi_offset 4, -8 + 1734 .cfi_offset 14, -4 +2561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1735 .loc 1 2561 0 + ARM GAS /tmp/cc7An1gz.s page 83 + + + 1736 0002 806A ldr r0, [r0, #40] + 1737 .LVL133: +2563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1738 .loc 1 2563 0 + 1739 0004 FFF7FEFF bl HAL_UART_RxHalfCpltCallback + 1740 .LVL134: +2564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1741 .loc 1 2564 0 + 1742 @ sp needed + 1743 0008 10BD pop {r4, pc} + 1744 .cfi_endproc + 1745 .LFE87: + 1747 .section .text.HAL_UART_ErrorCallback,"ax",%progbits + 1748 .align 1 + 1749 .weak HAL_UART_ErrorCallback + 1750 .syntax unified + 1751 .code 16 + 1752 .thumb_func + 1753 .fpu softvfp + 1755 HAL_UART_ErrorCallback: + 1756 .LFB66: +1837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 1757 .loc 1 1837 0 + 1758 .cfi_startproc + 1759 @ args = 0, pretend = 0, frame = 0 + 1760 @ frame_needed = 0, uses_anonymous_args = 0 + 1761 @ link register save eliminated. + 1762 .LVL135: +1844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1763 .loc 1 1844 0 + 1764 @ sp needed + 1765 0000 7047 bx lr + 1766 .cfi_endproc + 1767 .LFE66: + 1769 .section .text.UART_DMAError,"ax",%progbits + 1770 .align 1 + 1771 .syntax unified + 1772 .code 16 + 1773 .thumb_func + 1774 .fpu softvfp + 1776 UART_DMAError: + 1777 .LFB88: +2572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 1778 .loc 1 2572 0 + 1779 .cfi_startproc + 1780 @ args = 0, pretend = 0, frame = 0 + 1781 @ frame_needed = 0, uses_anonymous_args = 0 + 1782 .LVL136: + 1783 0000 10B5 push {r4, lr} + 1784 .LCFI14: + 1785 .cfi_def_cfa_offset 8 + 1786 .cfi_offset 4, -8 + 1787 .cfi_offset 14, -4 +2573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1788 .loc 1 2573 0 + 1789 0002 806A ldr r0, [r0, #40] + 1790 .LVL137: + ARM GAS /tmp/cc7An1gz.s page 84 + + +2576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + 1791 .loc 1 2576 0 + 1792 0004 6923 movs r3, #105 + 1793 0006 C35C ldrb r3, [r0, r3] + 1794 0008 212B cmp r3, #33 + 1795 000a 0AD0 beq .L119 + 1796 .L117: +2584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + 1797 .loc 1 2584 0 + 1798 000c 6A23 movs r3, #106 + 1799 000e C35C ldrb r3, [r0, r3] + 1800 0010 222B cmp r3, #34 + 1801 0012 15D0 beq .L120 + 1802 .L118: +2591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); + 1803 .loc 1 2591 0 + 1804 0014 C36E ldr r3, [r0, #108] + 1805 0016 1022 movs r2, #16 + 1806 0018 1343 orrs r3, r2 + 1807 001a C366 str r3, [r0, #108] +2592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1808 .loc 1 2592 0 + 1809 001c FFF7FEFF bl HAL_UART_ErrorCallback + 1810 .LVL138: +2593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1811 .loc 1 2593 0 + 1812 @ sp needed + 1813 0020 10BD pop {r4, pc} + 1814 .LVL139: + 1815 .L119: +2577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1816 .loc 1 2577 0 + 1817 0022 0368 ldr r3, [r0] + 1818 0024 9A68 ldr r2, [r3, #8] + 1819 0026 1206 lsls r2, r2, #24 + 1820 0028 F0D5 bpl .L117 +2579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndTxTransfer(huart); + 1821 .loc 1 2579 0 + 1822 002a 5222 movs r2, #82 + 1823 002c 0021 movs r1, #0 + 1824 002e 8152 strh r1, [r0, r2] + 1825 .LVL140: + 1826 .LBB18: + 1827 .LBB19: +2461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1828 .loc 1 2461 0 + 1829 0030 1A68 ldr r2, [r3] + 1830 0032 C031 adds r1, r1, #192 + 1831 0034 8A43 bics r2, r1 + 1832 0036 1A60 str r2, [r3] +2464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1833 .loc 1 2464 0 + 1834 0038 6923 movs r3, #105 + 1835 003a 2022 movs r2, #32 + 1836 003c C254 strb r2, [r0, r3] + 1837 003e E5E7 b .L117 + 1838 .LVL141: + ARM GAS /tmp/cc7An1gz.s page 85 + + + 1839 .L120: + 1840 .LBE19: + 1841 .LBE18: +2585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1842 .loc 1 2585 0 + 1843 0040 0368 ldr r3, [r0] + 1844 0042 9A68 ldr r2, [r3, #8] + 1845 0044 5206 lsls r2, r2, #25 + 1846 0046 E5D5 bpl .L118 +2587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_EndRxTransfer(huart); + 1847 .loc 1 2587 0 + 1848 0048 5A22 movs r2, #90 + 1849 004a 0021 movs r1, #0 + 1850 004c 8152 strh r1, [r0, r2] + 1851 .LVL142: + 1852 .LBB20: + 1853 .LBB21: +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1854 .loc 1 2476 0 + 1855 004e 1A68 ldr r2, [r3] + 1856 0050 0649 ldr r1, .L121 + 1857 0052 0A40 ands r2, r1 + 1858 0054 1A60 str r2, [r3] +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1859 .loc 1 2477 0 + 1860 0056 0268 ldr r2, [r0] + 1861 0058 9368 ldr r3, [r2, #8] + 1862 005a 2331 adds r1, r1, #35 + 1863 005c FF31 adds r1, r1, #255 + 1864 005e 8B43 bics r3, r1 + 1865 0060 9360 str r3, [r2, #8] +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1866 .loc 1 2480 0 + 1867 0062 6A23 movs r3, #106 + 1868 0064 2022 movs r2, #32 + 1869 0066 C254 strb r2, [r0, r3] + 1870 0068 D4E7 b .L118 + 1871 .L122: + 1872 006a C046 .align 2 + 1873 .L121: + 1874 006c DFFEFFFF .word -289 + 1875 .LBE21: + 1876 .LBE20: + 1877 .cfi_endproc + 1878 .LFE88: + 1880 .section .text.HAL_UART_IRQHandler,"ax",%progbits + 1881 .align 1 + 1882 .global HAL_UART_IRQHandler + 1883 .syntax unified + 1884 .code 16 + 1885 .thumb_func + 1886 .fpu softvfp + 1888 HAL_UART_IRQHandler: + 1889 .LFB61: +1625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); + 1890 .loc 1 1625 0 + 1891 .cfi_startproc + ARM GAS /tmp/cc7An1gz.s page 86 + + + 1892 @ args = 0, pretend = 0, frame = 0 + 1893 @ frame_needed = 0, uses_anonymous_args = 0 + 1894 .LVL143: + 1895 0000 70B5 push {r4, r5, r6, lr} + 1896 .LCFI15: + 1897 .cfi_def_cfa_offset 16 + 1898 .cfi_offset 4, -16 + 1899 .cfi_offset 5, -12 + 1900 .cfi_offset 6, -8 + 1901 .cfi_offset 14, -4 + 1902 0002 0400 movs r4, r0 +1626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 1903 .loc 1 1626 0 + 1904 0004 0168 ldr r1, [r0] + 1905 0006 CB69 ldr r3, [r1, #28] + 1906 .LVL144: +1627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t cr3its; + 1907 .loc 1 1627 0 + 1908 0008 0868 ldr r0, [r1] + 1909 .LVL145: +1632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (errorflags == RESET) + 1910 .loc 1 1632 0 + 1911 000a 0F22 movs r2, #15 + 1912 000c 1A40 ands r2, r3 + 1913 .LVL146: +1633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1914 .loc 1 1633 0 + 1915 000e 03D1 bne .L124 +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1916 .loc 1 1636 0 + 1917 0010 9D06 lsls r5, r3, #26 + 1918 0012 01D5 bpl .L124 +1636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1919 .loc 1 1636 0 is_stmt 0 discriminator 1 + 1920 0014 8506 lsls r5, r0, #26 + 1921 0016 66D4 bmi .L144 + 1922 .L124: +1644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if( (errorflags != RESET) + 1923 .loc 1 1644 0 is_stmt 1 + 1924 0018 8D68 ldr r5, [r1, #8] + 1925 .LVL147: +1645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** && ( ((cr3its & USART_CR3_EIE) != RESET) + 1926 .loc 1 1645 0 + 1927 001a 002A cmp r2, #0 + 1928 001c 79D0 beq .L126 +1646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + 1929 .loc 1 1646 0 + 1930 001e 0122 movs r2, #1 + 1931 .LVL148: + 1932 0020 2A40 ands r2, r5 + 1933 0022 03D1 bne .L127 +1647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1934 .loc 1 1647 0 + 1935 0024 9026 movs r6, #144 + 1936 0026 7600 lsls r6, r6, #1 + 1937 0028 3042 tst r0, r6 + 1938 002a 72D0 beq .L126 + ARM GAS /tmp/cc7An1gz.s page 87 + + + 1939 .L127: +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1940 .loc 1 1650 0 + 1941 002c DD07 lsls r5, r3, #31 + 1942 002e 06D5 bpl .L128 + 1943 .LVL149: +1650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1944 .loc 1 1650 0 is_stmt 0 discriminator 1 + 1945 0030 C505 lsls r5, r0, #23 + 1946 0032 04D5 bpl .L128 +1652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1947 .loc 1 1652 0 is_stmt 1 + 1948 0034 0125 movs r5, #1 + 1949 0036 0D62 str r5, [r1, #32] +1654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1950 .loc 1 1654 0 + 1951 0038 E16E ldr r1, [r4, #108] + 1952 003a 2943 orrs r1, r5 + 1953 003c E166 str r1, [r4, #108] + 1954 .L128: +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1955 .loc 1 1658 0 + 1956 003e 9907 lsls r1, r3, #30 + 1957 0040 08D5 bpl .L129 +1658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1958 .loc 1 1658 0 is_stmt 0 discriminator 1 + 1959 0042 002A cmp r2, #0 + 1960 0044 06D0 beq .L129 +1660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1961 .loc 1 1660 0 is_stmt 1 + 1962 0046 2168 ldr r1, [r4] + 1963 0048 0225 movs r5, #2 + 1964 004a 0D62 str r5, [r1, #32] +1662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1965 .loc 1 1662 0 + 1966 004c E16E ldr r1, [r4, #108] + 1967 004e 0235 adds r5, r5, #2 + 1968 0050 2943 orrs r1, r5 + 1969 0052 E166 str r1, [r4, #108] + 1970 .L129: +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1971 .loc 1 1666 0 + 1972 0054 5907 lsls r1, r3, #29 + 1973 0056 08D5 bpl .L130 +1666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1974 .loc 1 1666 0 is_stmt 0 discriminator 1 + 1975 0058 002A cmp r2, #0 + 1976 005a 06D0 beq .L130 +1668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1977 .loc 1 1668 0 is_stmt 1 + 1978 005c 2168 ldr r1, [r4] + 1979 005e 0425 movs r5, #4 + 1980 0060 0D62 str r5, [r1, #32] +1670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 1981 .loc 1 1670 0 + 1982 0062 E16E ldr r1, [r4, #108] + 1983 0064 023D subs r5, r5, #2 + ARM GAS /tmp/cc7An1gz.s page 88 + + + 1984 0066 2943 orrs r1, r5 + 1985 0068 E166 str r1, [r4, #108] + 1986 .L130: +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + 1987 .loc 1 1674 0 + 1988 006a 1907 lsls r1, r3, #28 + 1989 006c 09D5 bpl .L131 +1674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + 1990 .loc 1 1674 0 is_stmt 0 discriminator 1 + 1991 006e 8106 lsls r1, r0, #26 + 1992 0070 01D4 bmi .L132 +1675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 1993 .loc 1 1675 0 is_stmt 1 + 1994 0072 002A cmp r2, #0 + 1995 0074 05D0 beq .L131 + 1996 .L132: +1677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 1997 .loc 1 1677 0 + 1998 0076 2268 ldr r2, [r4] + 1999 0078 0821 movs r1, #8 + 2000 007a 1162 str r1, [r2, #32] +1679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2001 .loc 1 1679 0 + 2002 007c E26E ldr r2, [r4, #108] + 2003 007e 0A43 orrs r2, r1 + 2004 0080 E266 str r2, [r4, #108] + 2005 .L131: +1683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2006 .loc 1 1683 0 + 2007 0082 E26E ldr r2, [r4, #108] + 2008 0084 002A cmp r2, #0 + 2009 0086 50D0 beq .L123 +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2010 .loc 1 1686 0 + 2011 0088 9B06 lsls r3, r3, #26 + 2012 008a 01D5 bpl .L133 + 2013 .LVL150: +1686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2014 .loc 1 1686 0 is_stmt 0 discriminator 1 + 2015 008c 8306 lsls r3, r0, #26 + 2016 008e 2ED4 bmi .L145 + 2017 .LVL151: + 2018 .L133: +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + 2019 .loc 1 1693 0 is_stmt 1 + 2020 0090 E36E ldr r3, [r4, #108] + 2021 0092 1B07 lsls r3, r3, #28 + 2022 0094 03D4 bmi .L134 +1694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2023 .loc 1 1694 0 discriminator 1 + 2024 0096 2368 ldr r3, [r4] + 2025 0098 9B68 ldr r3, [r3, #8] +1693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + 2026 .loc 1 1693 0 discriminator 1 + 2027 009a 5B06 lsls r3, r3, #25 + 2028 009c 33D5 bpl .L135 + 2029 .L134: + ARM GAS /tmp/cc7An1gz.s page 89 + + + 2030 .LVL152: + 2031 .LBB28: + 2032 .LBB29: +2476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2033 .loc 1 2476 0 + 2034 009e 2268 ldr r2, [r4] + 2035 00a0 1368 ldr r3, [r2] + 2036 00a2 4749 ldr r1, .L151 + 2037 00a4 0B40 ands r3, r1 + 2038 00a6 1360 str r3, [r2] +2477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2039 .loc 1 2477 0 + 2040 00a8 2268 ldr r2, [r4] + 2041 00aa 9368 ldr r3, [r2, #8] + 2042 00ac 2331 adds r1, r1, #35 + 2043 00ae FF31 adds r1, r1, #255 + 2044 00b0 8B43 bics r3, r1 + 2045 00b2 9360 str r3, [r2, #8] +2480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2046 .loc 1 2480 0 + 2047 00b4 6A23 movs r3, #106 + 2048 00b6 2022 movs r2, #32 + 2049 00b8 E254 strb r2, [r4, r3] + 2050 .LVL153: + 2051 .LBE29: + 2052 .LBE28: +1702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2053 .loc 1 1702 0 + 2054 00ba 2368 ldr r3, [r4] + 2055 00bc 9A68 ldr r2, [r3, #8] + 2056 00be 5206 lsls r2, r2, #25 + 2057 00c0 1DD5 bpl .L136 +1704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2058 .loc 1 1704 0 + 2059 00c2 9A68 ldr r2, [r3, #8] + 2060 00c4 3F31 adds r1, r1, #63 + 2061 00c6 8A43 bics r2, r1 + 2062 00c8 9A60 str r2, [r3, #8] +1707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2063 .loc 1 1707 0 + 2064 00ca 636E ldr r3, [r4, #100] + 2065 00cc 002B cmp r3, #0 + 2066 00ce 12D0 beq .L137 +1711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2067 .loc 1 1711 0 + 2068 00d0 3C4A ldr r2, .L151+4 + 2069 00d2 9A63 str r2, [r3, #56] +1714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2070 .loc 1 1714 0 + 2071 00d4 606E ldr r0, [r4, #100] + 2072 00d6 FFF7FEFF bl HAL_DMA_Abort_IT + 2073 .LVL154: + 2074 00da 0028 cmp r0, #0 + 2075 00dc 25D0 beq .L123 +1717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2076 .loc 1 1717 0 + 2077 00de 606E ldr r0, [r4, #100] + ARM GAS /tmp/cc7An1gz.s page 90 + + + 2078 00e0 836B ldr r3, [r0, #56] + 2079 00e2 9847 blx r3 + 2080 .LVL155: + 2081 00e4 21E0 b .L123 + 2082 .LVL156: + 2083 .L144: +1638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; + 2084 .loc 1 1638 0 + 2085 00e6 2000 movs r0, r4 + 2086 .LVL157: + 2087 00e8 FFF7FEFF bl UART_Receive_IT + 2088 .LVL158: +1639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2089 .loc 1 1639 0 + 2090 00ec 1DE0 b .L123 + 2091 .LVL159: + 2092 .L145: +1688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2093 .loc 1 1688 0 + 2094 00ee 2000 movs r0, r4 + 2095 .LVL160: + 2096 00f0 FFF7FEFF bl UART_Receive_IT + 2097 .LVL161: + 2098 00f4 CCE7 b .L133 + 2099 .L137: +1723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2100 .loc 1 1723 0 + 2101 00f6 2000 movs r0, r4 + 2102 00f8 FFF7FEFF bl HAL_UART_ErrorCallback + 2103 .LVL162: + 2104 00fc 15E0 b .L123 + 2105 .L136: +1729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2106 .loc 1 1729 0 + 2107 00fe 2000 movs r0, r4 + 2108 0100 FFF7FEFF bl HAL_UART_ErrorCallback + 2109 .LVL163: + 2110 0104 11E0 b .L123 + 2111 .L135: +1736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 2112 .loc 1 1736 0 + 2113 0106 2000 movs r0, r4 + 2114 0108 FFF7FEFF bl HAL_UART_ErrorCallback + 2115 .LVL164: +1737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2116 .loc 1 1737 0 + 2117 010c 0023 movs r3, #0 + 2118 010e E366 str r3, [r4, #108] + 2119 0110 0BE0 b .L123 + 2120 .LVL165: + 2121 .L126: +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2122 .loc 1 1745 0 + 2123 0112 DA02 lsls r2, r3, #11 + 2124 0114 01D5 bpl .L138 +1745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2125 .loc 1 1745 0 is_stmt 0 discriminator 1 + ARM GAS /tmp/cc7An1gz.s page 91 + + + 2126 0116 6A02 lsls r2, r5, #9 + 2127 0118 08D4 bmi .L146 + 2128 .L138: +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2129 .loc 1 1756 0 is_stmt 1 + 2130 011a 1A06 lsls r2, r3, #24 + 2131 011c 01D5 bpl .L139 +1756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2132 .loc 1 1756 0 is_stmt 0 discriminator 1 + 2133 011e 0206 lsls r2, r0, #24 + 2134 0120 10D4 bmi .L147 + 2135 .L139: +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2136 .loc 1 1763 0 is_stmt 1 + 2137 0122 5B06 lsls r3, r3, #25 + 2138 0124 01D5 bpl .L123 + 2139 .LVL166: +1763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2140 .loc 1 1763 0 is_stmt 0 discriminator 1 + 2141 0126 4306 lsls r3, r0, #25 + 2142 0128 3ED4 bmi .L148 + 2143 .LVL167: + 2144 .L123: +1769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2145 .loc 1 1769 0 is_stmt 1 + 2146 @ sp needed + 2147 .LVL168: + 2148 012a 70BD pop {r4, r5, r6, pc} + 2149 .LVL169: + 2150 .L146: +1747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Set the UART state ready to be able to start again the process */ + 2151 .loc 1 1747 0 + 2152 012c 8023 movs r3, #128 + 2153 .LVL170: + 2154 012e 5B03 lsls r3, r3, #13 + 2155 0130 0B62 str r3, [r1, #32] +1749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2156 .loc 1 1749 0 + 2157 0132 2023 movs r3, #32 + 2158 0134 6922 movs r2, #105 + 2159 0136 A354 strb r3, [r4, r2] +1750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_UARTEx_WakeupCallback(huart); + 2160 .loc 1 1750 0 + 2161 0138 0132 adds r2, r2, #1 + 2162 013a A354 strb r3, [r4, r2] +1751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return; + 2163 .loc 1 1751 0 + 2164 013c 2000 movs r0, r4 + 2165 .LVL171: + 2166 013e FFF7FEFF bl HAL_UARTEx_WakeupCallback + 2167 .LVL172: +1752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2168 .loc 1 1752 0 + 2169 0142 F2E7 b .L123 + 2170 .LVL173: + 2171 .L147: + 2172 .LBB30: + ARM GAS /tmp/cc7An1gz.s page 92 + + + 2173 .LBB31: +2751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2174 .loc 1 2751 0 + 2175 0144 6923 movs r3, #105 + 2176 .LVL174: + 2177 0146 E35C ldrb r3, [r4, r3] + 2178 0148 212B cmp r3, #33 + 2179 014a EED1 bne .L123 +2753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2180 .loc 1 2753 0 + 2181 014c 3133 adds r3, r3, #49 + 2182 014e E35A ldrh r3, [r4, r3] + 2183 0150 9BB2 uxth r3, r3 + 2184 0152 002B cmp r3, #0 + 2185 0154 10D0 beq .L149 +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2186 .loc 1 2765 0 + 2187 0156 8023 movs r3, #128 + 2188 0158 5B01 lsls r3, r3, #5 + 2189 015a A268 ldr r2, [r4, #8] + 2190 015c 9A42 cmp r2, r3 + 2191 015e 16D0 beq .L150 + 2192 .L142: +2773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2193 .loc 1 2773 0 + 2194 0160 E36C ldr r3, [r4, #76] + 2195 0162 5A1C adds r2, r3, #1 + 2196 0164 E264 str r2, [r4, #76] + 2197 0166 1A78 ldrb r2, [r3] + 2198 0168 2368 ldr r3, [r4] + 2199 016a 9A62 str r2, [r3, #40] + 2200 .L143: +2775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2201 .loc 1 2775 0 + 2202 016c 5222 movs r2, #82 + 2203 016e A35A ldrh r3, [r4, r2] + 2204 0170 013B subs r3, r3, #1 + 2205 0172 9BB2 uxth r3, r3 + 2206 0174 A352 strh r3, [r4, r2] + 2207 0176 D8E7 b .L123 + 2208 .L149: +2756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2209 .loc 1 2756 0 + 2210 0178 2268 ldr r2, [r4] + 2211 017a 1368 ldr r3, [r2] + 2212 017c 8021 movs r1, #128 + 2213 017e 8B43 bics r3, r1 + 2214 0180 1360 str r3, [r2] +2759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2215 .loc 1 2759 0 + 2216 0182 2268 ldr r2, [r4] + 2217 0184 1368 ldr r3, [r2] + 2218 0186 4039 subs r1, r1, #64 + 2219 0188 0B43 orrs r3, r1 + 2220 018a 1360 str r3, [r2] + 2221 018c CDE7 b .L123 + 2222 .L150: + ARM GAS /tmp/cc7An1gz.s page 93 + + +2765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2223 .loc 1 2765 0 + 2224 018e 2369 ldr r3, [r4, #16] + 2225 0190 002B cmp r3, #0 + 2226 0192 E5D1 bne .L142 + 2227 .LVL175: +2768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 2228 .loc 1 2768 0 + 2229 0194 E36C ldr r3, [r4, #76] + 2230 0196 1B88 ldrh r3, [r3] + 2231 0198 2268 ldr r2, [r4] + 2232 019a DB05 lsls r3, r3, #23 + 2233 019c DB0D lsrs r3, r3, #23 + 2234 019e 9362 str r3, [r2, #40] + 2235 .LVL176: +2769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2236 .loc 1 2769 0 + 2237 01a0 E36C ldr r3, [r4, #76] + 2238 01a2 0233 adds r3, r3, #2 + 2239 01a4 E364 str r3, [r4, #76] + 2240 01a6 E1E7 b .L143 + 2241 .LVL177: + 2242 .L148: + 2243 .LBE31: + 2244 .LBE30: + 2245 .LBB32: + 2246 .LBB33: +2795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2247 .loc 1 2795 0 + 2248 01a8 0B68 ldr r3, [r1] + 2249 01aa 4022 movs r2, #64 + 2250 01ac 9343 bics r3, r2 + 2251 01ae 0B60 str r3, [r1] +2798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2252 .loc 1 2798 0 + 2253 01b0 6923 movs r3, #105 + 2254 01b2 203A subs r2, r2, #32 + 2255 01b4 E254 strb r2, [r4, r3] +2800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2256 .loc 1 2800 0 + 2257 01b6 2000 movs r0, r4 + 2258 .LVL178: + 2259 01b8 FFF7FEFF bl HAL_UART_TxCpltCallback + 2260 .LVL179: + 2261 01bc B5E7 b .L123 + 2262 .L152: + 2263 01be C046 .align 2 + 2264 .L151: + 2265 01c0 DFFEFFFF .word -289 + 2266 01c4 00000000 .word UART_DMAAbortOnError + 2267 .LBE33: + 2268 .LBE32: + 2269 .cfi_endproc + 2270 .LFE61: + 2272 .section .text.UART_DMAAbortOnError,"ax",%progbits + 2273 .align 1 + 2274 .syntax unified + ARM GAS /tmp/cc7An1gz.s page 94 + + + 2275 .code 16 + 2276 .thumb_func + 2277 .fpu softvfp + 2279 UART_DMAAbortOnError: + 2280 .LFB89: +2602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 2281 .loc 1 2602 0 + 2282 .cfi_startproc + 2283 @ args = 0, pretend = 0, frame = 0 + 2284 @ frame_needed = 0, uses_anonymous_args = 0 + 2285 .LVL180: + 2286 0000 10B5 push {r4, lr} + 2287 .LCFI16: + 2288 .cfi_def_cfa_offset 8 + 2289 .cfi_offset 4, -8 + 2290 .cfi_offset 14, -4 +2603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; + 2291 .loc 1 2603 0 + 2292 0002 806A ldr r0, [r0, #40] + 2293 .LVL181: +2604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = 0; + 2294 .loc 1 2604 0 + 2295 0004 0023 movs r3, #0 + 2296 0006 5A22 movs r2, #90 + 2297 0008 8352 strh r3, [r0, r2] +2605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2298 .loc 1 2605 0 + 2299 000a 083A subs r2, r2, #8 + 2300 000c 8352 strh r3, [r0, r2] +2607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2301 .loc 1 2607 0 + 2302 000e FFF7FEFF bl HAL_UART_ErrorCallback + 2303 .LVL182: +2608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2304 .loc 1 2608 0 + 2305 @ sp needed + 2306 0012 10BD pop {r4, pc} + 2307 .cfi_endproc + 2308 .LFE89: + 2310 .section .text.HAL_UART_AbortCpltCallback,"ax",%progbits + 2311 .align 1 + 2312 .weak HAL_UART_AbortCpltCallback + 2313 .syntax unified + 2314 .code 16 + 2315 .thumb_func + 2316 .fpu softvfp + 2318 HAL_UART_AbortCpltCallback: + 2319 .LFB67: +1852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2320 .loc 1 1852 0 + 2321 .cfi_startproc + 2322 @ args = 0, pretend = 0, frame = 0 + 2323 @ frame_needed = 0, uses_anonymous_args = 0 + 2324 @ link register save eliminated. + 2325 .LVL183: +1859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2326 .loc 1 1859 0 + ARM GAS /tmp/cc7An1gz.s page 95 + + + 2327 @ sp needed + 2328 0000 7047 bx lr + 2329 .cfi_endproc + 2330 .LFE67: + 2332 .section .text.HAL_UART_Abort_IT,"ax",%progbits + 2333 .align 1 + 2334 .global HAL_UART_Abort_IT + 2335 .syntax unified + 2336 .code 16 + 2337 .thumb_func + 2338 .fpu softvfp + 2340 HAL_UART_Abort_IT: + 2341 .LFB58: +1372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t abortcplt = 1; + 2342 .loc 1 1372 0 + 2343 .cfi_startproc + 2344 @ args = 0, pretend = 0, frame = 0 + 2345 @ frame_needed = 0, uses_anonymous_args = 0 + 2346 .LVL184: + 2347 0000 10B5 push {r4, lr} + 2348 .LCFI17: + 2349 .cfi_def_cfa_offset 8 + 2350 .cfi_offset 4, -8 + 2351 .cfi_offset 14, -4 + 2352 0002 0400 movs r4, r0 + 2353 .LVL185: +1376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2354 .loc 1 1376 0 + 2355 0004 0268 ldr r2, [r0] + 2356 0006 1368 ldr r3, [r2] + 2357 0008 3049 ldr r1, .L167 + 2358 000a 0B40 ands r3, r1 + 2359 000c 1360 str r3, [r2] +1377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2360 .loc 1 1377 0 + 2361 000e 0268 ldr r2, [r0] + 2362 0010 9368 ldr r3, [r2, #8] + 2363 0012 E331 adds r1, r1, #227 + 2364 0014 FF31 adds r1, r1, #255 + 2365 0016 8B43 bics r3, r1 + 2366 0018 9360 str r3, [r2, #8] +1382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2367 .loc 1 1382 0 + 2368 001a 036E ldr r3, [r0, #96] + 2369 001c 002B cmp r3, #0 + 2370 001e 05D0 beq .L156 +1386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2371 .loc 1 1386 0 + 2372 0020 0268 ldr r2, [r0] + 2373 0022 9268 ldr r2, [r2, #8] + 2374 0024 1206 lsls r2, r2, #24 + 2375 0026 1ED5 bpl .L157 +1388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2376 .loc 1 1388 0 + 2377 0028 294A ldr r2, .L167+4 + 2378 002a 9A63 str r2, [r3, #56] + 2379 .L156: + ARM GAS /tmp/cc7An1gz.s page 96 + + +1396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2380 .loc 1 1396 0 + 2381 002c 636E ldr r3, [r4, #100] + 2382 002e 002B cmp r3, #0 + 2383 0030 05D0 beq .L158 +1400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2384 .loc 1 1400 0 + 2385 0032 2268 ldr r2, [r4] + 2386 0034 9268 ldr r2, [r2, #8] + 2387 0036 5206 lsls r2, r2, #25 + 2388 0038 18D5 bpl .L159 +1402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2389 .loc 1 1402 0 + 2390 003a 264A ldr r2, .L167+8 + 2391 003c 9A63 str r2, [r3, #56] + 2392 .L158: +1411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2393 .loc 1 1411 0 + 2394 003e 2368 ldr r3, [r4] + 2395 0040 9A68 ldr r2, [r3, #8] + 2396 0042 1206 lsls r2, r2, #24 + 2397 0044 15D5 bpl .L164 +1414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2398 .loc 1 1414 0 + 2399 0046 9A68 ldr r2, [r3, #8] + 2400 0048 8021 movs r1, #128 + 2401 004a 8A43 bics r2, r1 + 2402 004c 9A60 str r2, [r3, #8] +1417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2403 .loc 1 1417 0 + 2404 004e 206E ldr r0, [r4, #96] + 2405 .LVL186: + 2406 0050 0028 cmp r0, #0 + 2407 0052 33D0 beq .L165 +1423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2408 .loc 1 1423 0 + 2409 0054 FFF7FEFF bl HAL_DMA_Abort_IT + 2410 .LVL187: + 2411 0058 0028 cmp r0, #0 + 2412 005a 31D0 beq .L166 +1425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2413 .loc 1 1425 0 + 2414 005c 236E ldr r3, [r4, #96] + 2415 005e 0022 movs r2, #0 + 2416 0060 9A63 str r2, [r3, #56] +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2417 .loc 1 1373 0 + 2418 0062 0121 movs r1, #1 + 2419 0064 06E0 b .L160 + 2420 .LVL188: + 2421 .L157: +1392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2422 .loc 1 1392 0 + 2423 0066 0022 movs r2, #0 + 2424 0068 9A63 str r2, [r3, #56] + 2425 006a DFE7 b .L156 + 2426 .L159: + ARM GAS /tmp/cc7An1gz.s page 97 + + +1406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2427 .loc 1 1406 0 + 2428 006c 0022 movs r2, #0 + 2429 006e 9A63 str r2, [r3, #56] + 2430 0070 E5E7 b .L158 + 2431 .L164: +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2432 .loc 1 1373 0 + 2433 0072 0121 movs r1, #1 + 2434 .LVL189: + 2435 .L160: +1435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2436 .loc 1 1435 0 + 2437 0074 2368 ldr r3, [r4] + 2438 0076 9A68 ldr r2, [r3, #8] + 2439 0078 5206 lsls r2, r2, #25 + 2440 007a 23D5 bpl .L161 +1437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2441 .loc 1 1437 0 + 2442 007c 9A68 ldr r2, [r3, #8] + 2443 007e 4020 movs r0, #64 + 2444 0080 8243 bics r2, r0 + 2445 0082 9A60 str r2, [r3, #8] +1440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2446 .loc 1 1440 0 + 2447 0084 606E ldr r0, [r4, #100] + 2448 0086 0028 cmp r0, #0 + 2449 0088 1CD0 beq .L161 +1446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2450 .loc 1 1446 0 + 2451 008a FFF7FEFF bl HAL_DMA_Abort_IT + 2452 .LVL190: + 2453 008e 0028 cmp r0, #0 + 2454 0090 1AD0 beq .L162 +1448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** abortcplt = 1; + 2455 .loc 1 1448 0 + 2456 0092 636E ldr r3, [r4, #100] + 2457 0094 0022 movs r2, #0 + 2458 0096 9A63 str r2, [r3, #56] + 2459 .LVL191: + 2460 .L163: +1462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; + 2461 .loc 1 1462 0 + 2462 0098 0023 movs r3, #0 + 2463 009a 5222 movs r2, #82 + 2464 009c A352 strh r3, [r4, r2] +1463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2465 .loc 1 1463 0 + 2466 009e 0832 adds r2, r2, #8 + 2467 00a0 A352 strh r3, [r4, r2] +1466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2468 .loc 1 1466 0 + 2469 00a2 E366 str r3, [r4, #108] +1469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2470 .loc 1 1469 0 + 2471 00a4 2368 ldr r3, [r4] + 2472 00a6 4B3A subs r2, r2, #75 + ARM GAS /tmp/cc7An1gz.s page 98 + + + 2473 00a8 1A62 str r2, [r3, #32] +1472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2474 .loc 1 1472 0 + 2475 00aa 2023 movs r3, #32 + 2476 00ac 5A32 adds r2, r2, #90 + 2477 00ae A354 strb r3, [r4, r2] +1473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2478 .loc 1 1473 0 + 2479 00b0 0132 adds r2, r2, #1 + 2480 00b2 A354 strb r3, [r4, r2] +1476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2481 .loc 1 1476 0 + 2482 00b4 2000 movs r0, r4 + 2483 00b6 FFF7FEFF bl HAL_UART_AbortCpltCallback + 2484 .LVL192: + 2485 00ba 05E0 b .L162 + 2486 .LVL193: + 2487 .L165: +1373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2488 .loc 1 1373 0 + 2489 00bc 0121 movs r1, #1 + 2490 00be D9E7 b .L160 + 2491 .L166: +1429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2492 .loc 1 1429 0 + 2493 00c0 0021 movs r1, #0 + 2494 00c2 D7E7 b .L160 + 2495 .LVL194: + 2496 .L161: +1459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2497 .loc 1 1459 0 + 2498 00c4 0129 cmp r1, #1 + 2499 00c6 E7D0 beq .L163 + 2500 .LVL195: + 2501 .L162: +1480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2502 .loc 1 1480 0 + 2503 00c8 0020 movs r0, #0 + 2504 @ sp needed + 2505 .LVL196: + 2506 00ca 10BD pop {r4, pc} + 2507 .L168: + 2508 .align 2 + 2509 .L167: + 2510 00cc 1FFEFFFF .word -481 + 2511 00d0 00000000 .word UART_DMATxAbortCallback + 2512 00d4 00000000 .word UART_DMARxAbortCallback + 2513 .cfi_endproc + 2514 .LFE58: + 2516 .section .text.UART_DMARxAbortCallback,"ax",%progbits + 2517 .align 1 + 2518 .syntax unified + 2519 .code 16 + 2520 .thumb_func + 2521 .fpu softvfp + 2523 UART_DMARxAbortCallback: + 2524 .LFB91: + ARM GAS /tmp/cc7An1gz.s page 99 + + +2661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); + 2525 .loc 1 2661 0 + 2526 .cfi_startproc + 2527 @ args = 0, pretend = 0, frame = 0 + 2528 @ frame_needed = 0, uses_anonymous_args = 0 + 2529 .LVL197: + 2530 0000 10B5 push {r4, lr} + 2531 .LCFI18: + 2532 .cfi_def_cfa_offset 8 + 2533 .cfi_offset 4, -8 + 2534 .cfi_offset 14, -4 +2662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2535 .loc 1 2662 0 + 2536 0002 806A ldr r0, [r0, #40] + 2537 .LVL198: +2664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2538 .loc 1 2664 0 + 2539 0004 436E ldr r3, [r0, #100] + 2540 0006 0022 movs r2, #0 + 2541 0008 9A63 str r2, [r3, #56] +2667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2542 .loc 1 2667 0 + 2543 000a 036E ldr r3, [r0, #96] + 2544 000c 002B cmp r3, #0 + 2545 000e 03D0 beq .L170 +2669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2546 .loc 1 2669 0 + 2547 0010 9B6B ldr r3, [r3, #56] + 2548 0012 002B cmp r3, #0 + 2549 0014 00D0 beq .L170 + 2550 .LVL199: + 2551 .L169: +2691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2552 .loc 1 2691 0 + 2553 @ sp needed + 2554 0016 10BD pop {r4, pc} + 2555 .LVL200: + 2556 .L170: +2676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; + 2557 .loc 1 2676 0 + 2558 0018 0023 movs r3, #0 + 2559 001a 5222 movs r2, #82 + 2560 001c 8352 strh r3, [r0, r2] +2677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2561 .loc 1 2677 0 + 2562 001e 0832 adds r2, r2, #8 + 2563 0020 8352 strh r3, [r0, r2] +2680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2564 .loc 1 2680 0 + 2565 0022 C366 str r3, [r0, #108] +2683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2566 .loc 1 2683 0 + 2567 0024 0368 ldr r3, [r0] + 2568 0026 4B3A subs r2, r2, #75 + 2569 0028 1A62 str r2, [r3, #32] +2686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2570 .loc 1 2686 0 + ARM GAS /tmp/cc7An1gz.s page 100 + + + 2571 002a 2023 movs r3, #32 + 2572 002c 5A32 adds r2, r2, #90 + 2573 002e 8354 strb r3, [r0, r2] +2687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2574 .loc 1 2687 0 + 2575 0030 0132 adds r2, r2, #1 + 2576 0032 8354 strb r3, [r0, r2] +2690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2577 .loc 1 2690 0 + 2578 0034 FFF7FEFF bl HAL_UART_AbortCpltCallback + 2579 .LVL201: + 2580 0038 EDE7 b .L169 + 2581 .cfi_endproc + 2582 .LFE91: + 2584 .section .text.UART_DMATxAbortCallback,"ax",%progbits + 2585 .align 1 + 2586 .syntax unified + 2587 .code 16 + 2588 .thumb_func + 2589 .fpu softvfp + 2591 UART_DMATxAbortCallback: + 2592 .LFB90: +2619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); + 2593 .loc 1 2619 0 + 2594 .cfi_startproc + 2595 @ args = 0, pretend = 0, frame = 0 + 2596 @ frame_needed = 0, uses_anonymous_args = 0 + 2597 .LVL202: + 2598 0000 10B5 push {r4, lr} + 2599 .LCFI19: + 2600 .cfi_def_cfa_offset 8 + 2601 .cfi_offset 4, -8 + 2602 .cfi_offset 14, -4 +2620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2603 .loc 1 2620 0 + 2604 0002 806A ldr r0, [r0, #40] + 2605 .LVL203: +2622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2606 .loc 1 2622 0 + 2607 0004 036E ldr r3, [r0, #96] + 2608 0006 0022 movs r2, #0 + 2609 0008 9A63 str r2, [r3, #56] +2625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2610 .loc 1 2625 0 + 2611 000a 436E ldr r3, [r0, #100] + 2612 000c 002B cmp r3, #0 + 2613 000e 03D0 beq .L173 +2627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2614 .loc 1 2627 0 + 2615 0010 9B6B ldr r3, [r3, #56] + 2616 0012 002B cmp r3, #0 + 2617 0014 00D0 beq .L173 + 2618 .LVL204: + 2619 .L172: +2649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2620 .loc 1 2649 0 + 2621 @ sp needed + ARM GAS /tmp/cc7An1gz.s page 101 + + + 2622 0016 10BD pop {r4, pc} + 2623 .LVL205: + 2624 .L173: +2634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = 0; + 2625 .loc 1 2634 0 + 2626 0018 0023 movs r3, #0 + 2627 001a 5222 movs r2, #82 + 2628 001c 8352 strh r3, [r0, r2] +2635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2629 .loc 1 2635 0 + 2630 001e 0832 adds r2, r2, #8 + 2631 0020 8352 strh r3, [r0, r2] +2638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2632 .loc 1 2638 0 + 2633 0022 C366 str r3, [r0, #108] +2641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2634 .loc 1 2641 0 + 2635 0024 0368 ldr r3, [r0] + 2636 0026 4B3A subs r2, r2, #75 + 2637 0028 1A62 str r2, [r3, #32] +2644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2638 .loc 1 2644 0 + 2639 002a 2023 movs r3, #32 + 2640 002c 5A32 adds r2, r2, #90 + 2641 002e 8354 strb r3, [r0, r2] +2645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2642 .loc 1 2645 0 + 2643 0030 0132 adds r2, r2, #1 + 2644 0032 8354 strb r3, [r0, r2] +2648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2645 .loc 1 2648 0 + 2646 0034 FFF7FEFF bl HAL_UART_AbortCpltCallback + 2647 .LVL206: + 2648 0038 EDE7 b .L172 + 2649 .cfi_endproc + 2650 .LFE90: + 2652 .section .text.HAL_UART_AbortTransmitCpltCallback,"ax",%progbits + 2653 .align 1 + 2654 .weak HAL_UART_AbortTransmitCpltCallback + 2655 .syntax unified + 2656 .code 16 + 2657 .thumb_func + 2658 .fpu softvfp + 2660 HAL_UART_AbortTransmitCpltCallback: + 2661 .LFB68: +1867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2662 .loc 1 1867 0 + 2663 .cfi_startproc + 2664 @ args = 0, pretend = 0, frame = 0 + 2665 @ frame_needed = 0, uses_anonymous_args = 0 + 2666 @ link register save eliminated. + 2667 .LVL207: +1874:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2668 .loc 1 1874 0 + 2669 @ sp needed + 2670 0000 7047 bx lr + 2671 .cfi_endproc + ARM GAS /tmp/cc7An1gz.s page 102 + + + 2672 .LFE68: + 2674 .section .text.HAL_UART_AbortTransmit_IT,"ax",%progbits + 2675 .align 1 + 2676 .global HAL_UART_AbortTransmit_IT + 2677 .syntax unified + 2678 .code 16 + 2679 .thumb_func + 2680 .fpu softvfp + 2682 HAL_UART_AbortTransmit_IT: + 2683 .LFB59: +1497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ + 2684 .loc 1 1497 0 + 2685 .cfi_startproc + 2686 @ args = 0, pretend = 0, frame = 0 + 2687 @ frame_needed = 0, uses_anonymous_args = 0 + 2688 .LVL208: + 2689 0000 10B5 push {r4, lr} + 2690 .LCFI20: + 2691 .cfi_def_cfa_offset 8 + 2692 .cfi_offset 4, -8 + 2693 .cfi_offset 14, -4 + 2694 0002 0400 movs r4, r0 +1499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2695 .loc 1 1499 0 + 2696 0004 0268 ldr r2, [r0] + 2697 0006 1368 ldr r3, [r2] + 2698 0008 C021 movs r1, #192 + 2699 000a 8B43 bics r3, r1 + 2700 000c 1360 str r3, [r2] +1502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2701 .loc 1 1502 0 + 2702 000e 0368 ldr r3, [r0] + 2703 0010 9A68 ldr r2, [r3, #8] + 2704 0012 1206 lsls r2, r2, #24 + 2705 0014 1BD5 bpl .L177 +1504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2706 .loc 1 1504 0 + 2707 0016 9A68 ldr r2, [r3, #8] + 2708 0018 4039 subs r1, r1, #64 + 2709 001a 8A43 bics r2, r1 + 2710 001c 9A60 str r2, [r3, #8] +1507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2711 .loc 1 1507 0 + 2712 001e 036E ldr r3, [r0, #96] + 2713 0020 002B cmp r3, #0 + 2714 0022 0BD0 beq .L178 +1511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2715 .loc 1 1511 0 + 2716 0024 0E4A ldr r2, .L180 + 2717 0026 9A63 str r2, [r3, #56] +1514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2718 .loc 1 1514 0 + 2719 0028 006E ldr r0, [r0, #96] + 2720 .LVL209: + 2721 002a FFF7FEFF bl HAL_DMA_Abort_IT + 2722 .LVL210: + 2723 002e 0028 cmp r0, #0 + ARM GAS /tmp/cc7An1gz.s page 103 + + + 2724 0030 02D0 beq .L179 +1517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2725 .loc 1 1517 0 + 2726 0032 206E ldr r0, [r4, #96] + 2727 0034 836B ldr r3, [r0, #56] + 2728 0036 9847 blx r3 + 2729 .LVL211: + 2730 .L179: +1545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2731 .loc 1 1545 0 + 2732 0038 0020 movs r0, #0 + 2733 @ sp needed + 2734 .LVL212: + 2735 003a 10BD pop {r4, pc} + 2736 .LVL213: + 2737 .L178: +1523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2738 .loc 1 1523 0 + 2739 003c 5223 movs r3, #82 + 2740 003e 0022 movs r2, #0 + 2741 0040 C252 strh r2, [r0, r3] +1526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2742 .loc 1 1526 0 + 2743 0042 1733 adds r3, r3, #23 + 2744 0044 2032 adds r2, r2, #32 + 2745 0046 C254 strb r2, [r0, r3] +1529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2746 .loc 1 1529 0 + 2747 0048 FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 2748 .LVL214: + 2749 004c F4E7 b .L179 + 2750 .LVL215: + 2751 .L177: +1535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2752 .loc 1 1535 0 + 2753 004e 5223 movs r3, #82 + 2754 0050 0022 movs r2, #0 + 2755 0052 C252 strh r2, [r0, r3] +1538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2756 .loc 1 1538 0 + 2757 0054 1733 adds r3, r3, #23 + 2758 0056 2032 adds r2, r2, #32 + 2759 0058 C254 strb r2, [r0, r3] +1541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2760 .loc 1 1541 0 + 2761 005a FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 2762 .LVL216: + 2763 005e EBE7 b .L179 + 2764 .L181: + 2765 .align 2 + 2766 .L180: + 2767 0060 00000000 .word UART_DMATxOnlyAbortCallback + 2768 .cfi_endproc + 2769 .LFE59: + 2771 .section .text.UART_DMATxOnlyAbortCallback,"ax",%progbits + 2772 .align 1 + 2773 .syntax unified + ARM GAS /tmp/cc7An1gz.s page 104 + + + 2774 .code 16 + 2775 .thumb_func + 2776 .fpu softvfp + 2778 UART_DMATxOnlyAbortCallback: + 2779 .LFB92: +2703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + 2780 .loc 1 2703 0 + 2781 .cfi_startproc + 2782 @ args = 0, pretend = 0, frame = 0 + 2783 @ frame_needed = 0, uses_anonymous_args = 0 + 2784 .LVL217: + 2785 0000 10B5 push {r4, lr} + 2786 .LCFI21: + 2787 .cfi_def_cfa_offset 8 + 2788 .cfi_offset 4, -8 + 2789 .cfi_offset 14, -4 +2704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2790 .loc 1 2704 0 + 2791 0002 806A ldr r0, [r0, #40] + 2792 .LVL218: +2706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2793 .loc 1 2706 0 + 2794 0004 5223 movs r3, #82 + 2795 0006 0022 movs r2, #0 + 2796 0008 C252 strh r2, [r0, r3] +2709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2797 .loc 1 2709 0 + 2798 000a 1733 adds r3, r3, #23 + 2799 000c 2032 adds r2, r2, #32 + 2800 000e C254 strb r2, [r0, r3] +2712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2801 .loc 1 2712 0 + 2802 0010 FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 2803 .LVL219: +2713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2804 .loc 1 2713 0 + 2805 @ sp needed + 2806 0014 10BD pop {r4, pc} + 2807 .cfi_endproc + 2808 .LFE92: + 2810 .section .text.HAL_UART_AbortReceiveCpltCallback,"ax",%progbits + 2811 .align 1 + 2812 .weak HAL_UART_AbortReceiveCpltCallback + 2813 .syntax unified + 2814 .code 16 + 2815 .thumb_func + 2816 .fpu softvfp + 2818 HAL_UART_AbortReceiveCpltCallback: + 2819 .LFB69: +1882:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2820 .loc 1 1882 0 + 2821 .cfi_startproc + 2822 @ args = 0, pretend = 0, frame = 0 + 2823 @ frame_needed = 0, uses_anonymous_args = 0 + 2824 @ link register save eliminated. + 2825 .LVL220: +1889:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 105 + + + 2826 .loc 1 1889 0 + 2827 @ sp needed + 2828 0000 7047 bx lr + 2829 .cfi_endproc + 2830 .LFE69: + 2832 .section .text.HAL_UART_AbortReceive_IT,"ax",%progbits + 2833 .align 1 + 2834 .global HAL_UART_AbortReceive_IT + 2835 .syntax unified + 2836 .code 16 + 2837 .thumb_func + 2838 .fpu softvfp + 2840 HAL_UART_AbortReceive_IT: + 2841 .LFB60: +1562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 2842 .loc 1 1562 0 + 2843 .cfi_startproc + 2844 @ args = 0, pretend = 0, frame = 0 + 2845 @ frame_needed = 0, uses_anonymous_args = 0 + 2846 .LVL221: + 2847 0000 10B5 push {r4, lr} + 2848 .LCFI22: + 2849 .cfi_def_cfa_offset 8 + 2850 .cfi_offset 4, -8 + 2851 .cfi_offset 14, -4 + 2852 0002 0400 movs r4, r0 +1564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2853 .loc 1 1564 0 + 2854 0004 0268 ldr r2, [r0] + 2855 0006 1368 ldr r3, [r2] + 2856 0008 1B49 ldr r1, .L188 + 2857 000a 0B40 ands r3, r1 + 2858 000c 1360 str r3, [r2] +1565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2859 .loc 1 1565 0 + 2860 000e 0268 ldr r2, [r0] + 2861 0010 9368 ldr r3, [r2, #8] + 2862 0012 2331 adds r1, r1, #35 + 2863 0014 FF31 adds r1, r1, #255 + 2864 0016 8B43 bics r3, r1 + 2865 0018 9360 str r3, [r2, #8] +1568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2866 .loc 1 1568 0 + 2867 001a 0368 ldr r3, [r0] + 2868 001c 9A68 ldr r2, [r3, #8] + 2869 001e 5206 lsls r2, r2, #25 + 2870 0020 1ED5 bpl .L185 +1570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2871 .loc 1 1570 0 + 2872 0022 9A68 ldr r2, [r3, #8] + 2873 0024 3F31 adds r1, r1, #63 + 2874 0026 8A43 bics r2, r1 + 2875 0028 9A60 str r2, [r3, #8] +1573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2876 .loc 1 1573 0 + 2877 002a 436E ldr r3, [r0, #100] + 2878 002c 002B cmp r3, #0 + ARM GAS /tmp/cc7An1gz.s page 106 + + + 2879 002e 0BD0 beq .L186 +1577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2880 .loc 1 1577 0 + 2881 0030 124A ldr r2, .L188+4 + 2882 0032 9A63 str r2, [r3, #56] +1580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 2883 .loc 1 1580 0 + 2884 0034 406E ldr r0, [r0, #100] + 2885 .LVL222: + 2886 0036 FFF7FEFF bl HAL_DMA_Abort_IT + 2887 .LVL223: + 2888 003a 0028 cmp r0, #0 + 2889 003c 02D0 beq .L187 +1583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2890 .loc 1 1583 0 + 2891 003e 606E ldr r0, [r4, #100] + 2892 0040 836B ldr r3, [r0, #56] + 2893 0042 9847 blx r3 + 2894 .LVL224: + 2895 .L187: +1617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2896 .loc 1 1617 0 + 2897 0044 0020 movs r0, #0 + 2898 @ sp needed + 2899 .LVL225: + 2900 0046 10BD pop {r4, pc} + 2901 .LVL226: + 2902 .L186: +1589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2903 .loc 1 1589 0 + 2904 0048 5A23 movs r3, #90 + 2905 004a 0022 movs r2, #0 + 2906 004c C252 strh r2, [r0, r3] +1592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2907 .loc 1 1592 0 + 2908 004e 0368 ldr r3, [r0] + 2909 0050 0F32 adds r2, r2, #15 + 2910 0052 1A62 str r2, [r3, #32] +1595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2911 .loc 1 1595 0 + 2912 0054 6A23 movs r3, #106 + 2913 0056 1132 adds r2, r2, #17 + 2914 0058 C254 strb r2, [r0, r3] +1598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2915 .loc 1 1598 0 + 2916 005a FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 2917 .LVL227: + 2918 005e F1E7 b .L187 + 2919 .LVL228: + 2920 .L185: +1604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2921 .loc 1 1604 0 + 2922 0060 5A22 movs r2, #90 + 2923 0062 0021 movs r1, #0 + 2924 0064 8152 strh r1, [r0, r2] +1607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2925 .loc 1 1607 0 + ARM GAS /tmp/cc7An1gz.s page 107 + + + 2926 0066 4B3A subs r2, r2, #75 + 2927 0068 1A62 str r2, [r3, #32] +1610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2928 .loc 1 1610 0 + 2929 006a 6A23 movs r3, #106 + 2930 006c 1132 adds r2, r2, #17 + 2931 006e C254 strb r2, [r0, r3] +1613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2932 .loc 1 1613 0 + 2933 0070 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 2934 .LVL229: + 2935 0074 E6E7 b .L187 + 2936 .L189: + 2937 0076 C046 .align 2 + 2938 .L188: + 2939 0078 DFFEFFFF .word -289 + 2940 007c 00000000 .word UART_DMARxOnlyAbortCallback + 2941 .cfi_endproc + 2942 .LFE60: + 2944 .section .text.UART_DMARxOnlyAbortCallback,"ax",%progbits + 2945 .align 1 + 2946 .syntax unified + 2947 .code 16 + 2948 .thumb_func + 2949 .fpu softvfp + 2951 UART_DMARxOnlyAbortCallback: + 2952 .LFB93: +2724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 2953 .loc 1 2724 0 + 2954 .cfi_startproc + 2955 @ args = 0, pretend = 0, frame = 0 + 2956 @ frame_needed = 0, uses_anonymous_args = 0 + 2957 .LVL230: + 2958 0000 10B5 push {r4, lr} + 2959 .LCFI23: + 2960 .cfi_def_cfa_offset 8 + 2961 .cfi_offset 4, -8 + 2962 .cfi_offset 14, -4 +2725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2963 .loc 1 2725 0 + 2964 0002 806A ldr r0, [r0, #40] + 2965 .LVL231: +2727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2966 .loc 1 2727 0 + 2967 0004 5A23 movs r3, #90 + 2968 0006 0022 movs r2, #0 + 2969 0008 C252 strh r2, [r0, r3] +2730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2970 .loc 1 2730 0 + 2971 000a 0368 ldr r3, [r0] + 2972 000c 0F32 adds r2, r2, #15 + 2973 000e 1A62 str r2, [r3, #32] +2733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2974 .loc 1 2733 0 + 2975 0010 6A23 movs r3, #106 + 2976 0012 1132 adds r2, r2, #17 + 2977 0014 C254 strb r2, [r0, r3] + ARM GAS /tmp/cc7An1gz.s page 108 + + +2736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 2978 .loc 1 2736 0 + 2979 0016 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 2980 .LVL232: +2737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 2981 .loc 1 2737 0 + 2982 @ sp needed + 2983 001a 10BD pop {r4, pc} + 2984 .cfi_endproc + 2985 .LFE93: + 2987 .section .text.HAL_MultiProcessor_EnterMuteMode,"ax",%progbits + 2988 .align 1 + 2989 .global HAL_MultiProcessor_EnterMuteMode + 2990 .syntax unified + 2991 .code 16 + 2992 .thumb_func + 2993 .fpu softvfp + 2995 HAL_MultiProcessor_EnterMuteMode: + 2996 .LFB72: +1966:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); + 2997 .loc 1 1966 0 + 2998 .cfi_startproc + 2999 @ args = 0, pretend = 0, frame = 0 + 3000 @ frame_needed = 0, uses_anonymous_args = 0 + 3001 @ link register save eliminated. + 3002 .LVL233: +1967:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3003 .loc 1 1967 0 + 3004 0000 0268 ldr r2, [r0] + 3005 0002 9369 ldr r3, [r2, #24] + 3006 0004 0421 movs r1, #4 + 3007 0006 0B43 orrs r3, r1 + 3008 0008 9361 str r3, [r2, #24] +1968:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3009 .loc 1 1968 0 + 3010 @ sp needed + 3011 000a 7047 bx lr + 3012 .cfi_endproc + 3013 .LFE72: + 3015 .section .text.HAL_HalfDuplex_EnableTransmitter,"ax",%progbits + 3016 .align 1 + 3017 .global HAL_HalfDuplex_EnableTransmitter + 3018 .syntax unified + 3019 .code 16 + 3020 .thumb_func + 3021 .fpu softvfp + 3023 HAL_HalfDuplex_EnableTransmitter: + 3024 .LFB73: +1976:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 3025 .loc 1 1976 0 + 3026 .cfi_startproc + 3027 @ args = 0, pretend = 0, frame = 0 + 3028 @ frame_needed = 0, uses_anonymous_args = 0 + 3029 .LVL234: + 3030 0000 30B5 push {r4, r5, lr} + 3031 .LCFI24: + 3032 .cfi_def_cfa_offset 12 + ARM GAS /tmp/cc7An1gz.s page 109 + + + 3033 .cfi_offset 4, -12 + 3034 .cfi_offset 5, -8 + 3035 .cfi_offset 14, -4 +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3036 .loc 1 1978 0 + 3037 0002 6823 movs r3, #104 + 3038 0004 C35C ldrb r3, [r0, r3] + 3039 0006 012B cmp r3, #1 + 3040 0008 15D0 beq .L194 +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3041 .loc 1 1978 0 is_stmt 0 discriminator 2 + 3042 000a 6822 movs r2, #104 + 3043 000c 0123 movs r3, #1 + 3044 000e 8354 strb r3, [r0, r2] +1979:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3045 .loc 1 1979 0 is_stmt 1 discriminator 2 + 3046 0010 6921 movs r1, #105 + 3047 0012 2333 adds r3, r3, #35 + 3048 0014 4354 strb r3, [r0, r1] +1982:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + 3049 .loc 1 1982 0 discriminator 2 + 3050 0016 0468 ldr r4, [r0] + 3051 0018 2368 ldr r3, [r4] + 3052 001a 0C25 movs r5, #12 + 3053 001c AB43 bics r3, r5 + 3054 001e 2360 str r3, [r4] +1984:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3055 .loc 1 1984 0 discriminator 2 + 3056 0020 0468 ldr r4, [r0] + 3057 0022 2368 ldr r3, [r4] + 3058 0024 043D subs r5, r5, #4 + 3059 0026 2B43 orrs r3, r5 + 3060 0028 2360 str r3, [r4] +1986:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3061 .loc 1 1986 0 discriminator 2 + 3062 002a 2023 movs r3, #32 + 3063 002c 4354 strb r3, [r0, r1] +1989:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3064 .loc 1 1989 0 discriminator 2 + 3065 002e 0023 movs r3, #0 + 3066 0030 8354 strb r3, [r0, r2] +1991:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3067 .loc 1 1991 0 discriminator 2 + 3068 0032 0020 movs r0, #0 + 3069 .LVL235: + 3070 .L193: +1992:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3071 .loc 1 1992 0 + 3072 @ sp needed + 3073 0034 30BD pop {r4, r5, pc} + 3074 .LVL236: + 3075 .L194: +1978:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3076 .loc 1 1978 0 + 3077 0036 0220 movs r0, #2 + 3078 .LVL237: + 3079 0038 FCE7 b .L193 + ARM GAS /tmp/cc7An1gz.s page 110 + + + 3080 .cfi_endproc + 3081 .LFE73: + 3083 .section .text.HAL_HalfDuplex_EnableReceiver,"ax",%progbits + 3084 .align 1 + 3085 .global HAL_HalfDuplex_EnableReceiver + 3086 .syntax unified + 3087 .code 16 + 3088 .thumb_func + 3089 .fpu softvfp + 3091 HAL_HalfDuplex_EnableReceiver: + 3092 .LFB74: +2000:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 3093 .loc 1 2000 0 + 3094 .cfi_startproc + 3095 @ args = 0, pretend = 0, frame = 0 + 3096 @ frame_needed = 0, uses_anonymous_args = 0 + 3097 .LVL238: + 3098 0000 30B5 push {r4, r5, lr} + 3099 .LCFI25: + 3100 .cfi_def_cfa_offset 12 + 3101 .cfi_offset 4, -12 + 3102 .cfi_offset 5, -8 + 3103 .cfi_offset 14, -4 +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3104 .loc 1 2002 0 + 3105 0002 6823 movs r3, #104 + 3106 0004 C35C ldrb r3, [r0, r3] + 3107 0006 012B cmp r3, #1 + 3108 0008 15D0 beq .L197 +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3109 .loc 1 2002 0 is_stmt 0 discriminator 2 + 3110 000a 6822 movs r2, #104 + 3111 000c 0123 movs r3, #1 + 3112 000e 8354 strb r3, [r0, r2] +2003:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3113 .loc 1 2003 0 is_stmt 1 discriminator 2 + 3114 0010 6921 movs r1, #105 + 3115 0012 2333 adds r3, r3, #35 + 3116 0014 4354 strb r3, [r0, r1] +2006:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + 3117 .loc 1 2006 0 discriminator 2 + 3118 0016 0468 ldr r4, [r0] + 3119 0018 2368 ldr r3, [r4] + 3120 001a 0C25 movs r5, #12 + 3121 001c AB43 bics r3, r5 + 3122 001e 2360 str r3, [r4] +2008:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3123 .loc 1 2008 0 discriminator 2 + 3124 0020 0468 ldr r4, [r0] + 3125 0022 2368 ldr r3, [r4] + 3126 0024 083D subs r5, r5, #8 + 3127 0026 2B43 orrs r3, r5 + 3128 0028 2360 str r3, [r4] +2010:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Unlocked */ + 3129 .loc 1 2010 0 discriminator 2 + 3130 002a 2023 movs r3, #32 + 3131 002c 4354 strb r3, [r0, r1] + ARM GAS /tmp/cc7An1gz.s page 111 + + +2012:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3132 .loc 1 2012 0 discriminator 2 + 3133 002e 0023 movs r3, #0 + 3134 0030 8354 strb r3, [r0, r2] +2014:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3135 .loc 1 2014 0 discriminator 2 + 3136 0032 0020 movs r0, #0 + 3137 .LVL239: + 3138 .L196: +2015:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3139 .loc 1 2015 0 + 3140 @ sp needed + 3141 0034 30BD pop {r4, r5, pc} + 3142 .LVL240: + 3143 .L197: +2002:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 3144 .loc 1 2002 0 + 3145 0036 0220 movs r0, #2 + 3146 .LVL241: + 3147 0038 FCE7 b .L196 + 3148 .cfi_endproc + 3149 .LFE74: + 3151 .section .text.HAL_LIN_SendBreak,"ax",%progbits + 3152 .align 1 + 3153 .global HAL_LIN_SendBreak + 3154 .syntax unified + 3155 .code 16 + 3156 .thumb_func + 3157 .fpu softvfp + 3159 HAL_LIN_SendBreak: + 3160 .LFB75: +2024:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the parameters */ + 3161 .loc 1 2024 0 + 3162 .cfi_startproc + 3163 @ args = 0, pretend = 0, frame = 0 + 3164 @ frame_needed = 0, uses_anonymous_args = 0 + 3165 .LVL242: + 3166 0000 30B5 push {r4, r5, lr} + 3167 .LCFI26: + 3168 .cfi_def_cfa_offset 12 + 3169 .cfi_offset 4, -12 + 3170 .cfi_offset 5, -8 + 3171 .cfi_offset 14, -4 +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3172 .loc 1 2029 0 + 3173 0002 6823 movs r3, #104 + 3174 0004 C35C ldrb r3, [r0, r3] + 3175 0006 012B cmp r3, #1 + 3176 0008 10D0 beq .L200 +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3177 .loc 1 2029 0 is_stmt 0 discriminator 2 + 3178 000a 6822 movs r2, #104 + 3179 000c 0123 movs r3, #1 + 3180 000e 8354 strb r3, [r0, r2] +2031:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3181 .loc 1 2031 0 is_stmt 1 discriminator 2 + 3182 0010 6921 movs r1, #105 + ARM GAS /tmp/cc7An1gz.s page 112 + + + 3183 0012 2333 adds r3, r3, #35 + 3184 0014 4354 strb r3, [r0, r1] +2034:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3185 .loc 1 2034 0 discriminator 2 + 3186 0016 0468 ldr r4, [r0] + 3187 0018 A369 ldr r3, [r4, #24] + 3188 001a 0225 movs r5, #2 + 3189 001c 2B43 orrs r3, r5 + 3190 001e A361 str r3, [r4, #24] +2036:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3191 .loc 1 2036 0 discriminator 2 + 3192 0020 2023 movs r3, #32 + 3193 0022 4354 strb r3, [r0, r1] +2039:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3194 .loc 1 2039 0 discriminator 2 + 3195 0024 0023 movs r3, #0 + 3196 0026 8354 strb r3, [r0, r2] +2041:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3197 .loc 1 2041 0 discriminator 2 + 3198 0028 0020 movs r0, #0 + 3199 .LVL243: + 3200 .L199: +2042:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3201 .loc 1 2042 0 + 3202 @ sp needed + 3203 002a 30BD pop {r4, r5, pc} + 3204 .LVL244: + 3205 .L200: +2029:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3206 .loc 1 2029 0 + 3207 002c 0220 movs r0, #2 + 3208 .LVL245: + 3209 002e FCE7 b .L199 + 3210 .cfi_endproc + 3211 .LFE75: + 3213 .section .text.HAL_UART_GetState,"ax",%progbits + 3214 .align 1 + 3215 .global HAL_UART_GetState + 3216 .syntax unified + 3217 .code 16 + 3218 .thumb_func + 3219 .fpu softvfp + 3221 HAL_UART_GetState: + 3222 .LFB76: +2072:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t temp1= 0x00U, temp2 = 0x00U; + 3223 .loc 1 2072 0 + 3224 .cfi_startproc + 3225 @ args = 0, pretend = 0, frame = 0 + 3226 @ frame_needed = 0, uses_anonymous_args = 0 + 3227 @ link register save eliminated. + 3228 .LVL246: +2074:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** temp2 = huart->RxState; + 3229 .loc 1 2074 0 + 3230 0000 6923 movs r3, #105 + 3231 0002 C35C ldrb r3, [r0, r3] + 3232 .LVL247: +2075:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 113 + + + 3233 .loc 1 2075 0 + 3234 0004 6A22 movs r2, #106 + 3235 0006 805C ldrb r0, [r0, r2] + 3236 .LVL248: +2077:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3237 .loc 1 2077 0 + 3238 0008 1843 orrs r0, r3 + 3239 .LVL249: +2078:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3240 .loc 1 2078 0 + 3241 @ sp needed + 3242 000a 7047 bx lr + 3243 .cfi_endproc + 3244 .LFE76: + 3246 .section .text.HAL_UART_GetError,"ax",%progbits + 3247 .align 1 + 3248 .global HAL_UART_GetError + 3249 .syntax unified + 3250 .code 16 + 3251 .thumb_func + 3252 .fpu softvfp + 3254 HAL_UART_GetError: + 3255 .LFB77: +2087:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return huart->ErrorCode; + 3256 .loc 1 2087 0 + 3257 .cfi_startproc + 3258 @ args = 0, pretend = 0, frame = 0 + 3259 @ frame_needed = 0, uses_anonymous_args = 0 + 3260 @ link register save eliminated. + 3261 .LVL250: +2088:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3262 .loc 1 2088 0 + 3263 0000 C06E ldr r0, [r0, #108] + 3264 .LVL251: +2089:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /** + 3265 .loc 1 2089 0 + 3266 @ sp needed + 3267 0002 7047 bx lr + 3268 .cfi_endproc + 3269 .LFE77: + 3271 .global __aeabi_uldivmod + 3272 .global __aeabi_uidiv + 3273 .section .text.UART_SetConfig,"ax",%progbits + 3274 .align 1 + 3275 .global UART_SetConfig + 3276 .syntax unified + 3277 .code 16 + 3278 .thumb_func + 3279 .fpu softvfp + 3281 UART_SetConfig: + 3282 .LFB78: +2108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tmpreg = 0x00000000U; + 3283 .loc 1 2108 0 + 3284 .cfi_startproc + 3285 @ args = 0, pretend = 0, frame = 0 + 3286 @ frame_needed = 0, uses_anonymous_args = 0 + 3287 .LVL252: + ARM GAS /tmp/cc7An1gz.s page 114 + + + 3288 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3289 .LCFI27: + 3290 .cfi_def_cfa_offset 24 + 3291 .cfi_offset 3, -24 + 3292 .cfi_offset 4, -20 + 3293 .cfi_offset 5, -16 + 3294 .cfi_offset 6, -12 + 3295 .cfi_offset 7, -8 + 3296 .cfi_offset 14, -4 + 3297 0002 0400 movs r4, r0 + 3298 .LVL253: +2118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3299 .loc 1 2118 0 + 3300 0004 0168 ldr r1, [r0] +2141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); + 3301 .loc 1 2141 0 + 3302 0006 8368 ldr r3, [r0, #8] + 3303 0008 0269 ldr r2, [r0, #16] + 3304 000a 1343 orrs r3, r2 + 3305 000c 4269 ldr r2, [r0, #20] + 3306 000e 1343 orrs r3, r2 + 3307 0010 C269 ldr r2, [r0, #28] + 3308 0012 1343 orrs r3, r2 + 3309 .LVL254: +2142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3310 .loc 1 2142 0 + 3311 0014 0A68 ldr r2, [r1] + 3312 0016 BE48 ldr r0, .L271 + 3313 .LVL255: + 3314 0018 0240 ands r2, r0 + 3315 001a 1343 orrs r3, r2 + 3316 .LVL256: + 3317 001c 0B60 str r3, [r1] + 3318 .LVL257: +2147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3319 .loc 1 2147 0 + 3320 001e 2268 ldr r2, [r4] + 3321 0020 5368 ldr r3, [r2, #4] + 3322 0022 BC49 ldr r1, .L271+4 + 3323 0024 0B40 ands r3, r1 + 3324 0026 E168 ldr r1, [r4, #12] + 3325 0028 0B43 orrs r3, r1 + 3326 002a 5360 str r3, [r2, #4] +2155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if (!(UART_INSTANCE_LOWPOWER(huart))) + 3327 .loc 1 2155 0 + 3328 002c A169 ldr r1, [r4, #24] + 3329 .LVL258: +2156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3330 .loc 1 2156 0 + 3331 002e 2268 ldr r2, [r4] + 3332 0030 B94B ldr r3, .L271+8 + 3333 0032 9A42 cmp r2, r3 + 3334 0034 01D0 beq .L204 +2158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3335 .loc 1 2158 0 + 3336 0036 236A ldr r3, [r4, #32] + 3337 0038 1943 orrs r1, r3 + ARM GAS /tmp/cc7An1gz.s page 115 + + + 3338 .LVL259: + 3339 .L204: +2160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3340 .loc 1 2160 0 + 3341 003a 9368 ldr r3, [r2, #8] + 3342 003c B748 ldr r0, .L271+12 + 3343 003e 0340 ands r3, r0 + 3344 0040 0B43 orrs r3, r1 + 3345 0042 9360 str r3, [r2, #8] +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3346 .loc 1 2163 0 + 3347 0044 2368 ldr r3, [r4] + 3348 0046 B64A ldr r2, .L271+16 + 3349 0048 9342 cmp r3, r2 + 3350 004a 20D0 beq .L262 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3351 .loc 1 2163 0 is_stmt 0 discriminator 2 + 3352 004c B54A ldr r2, .L271+20 + 3353 004e 9342 cmp r3, r2 + 3354 0050 31D0 beq .L263 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3355 .loc 1 2163 0 discriminator 14 + 3356 0052 B54A ldr r2, .L271+24 + 3357 0054 9342 cmp r3, r2 + 3358 0056 63D0 beq .L248 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3359 .loc 1 2163 0 discriminator 26 + 3360 0058 B44A ldr r2, .L271+28 + 3361 005a 9342 cmp r3, r2 + 3362 005c 62D0 beq .L249 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3363 .loc 1 2163 0 discriminator 28 + 3364 005e AE4A ldr r2, .L271+8 + 3365 0060 9342 cmp r3, r2 + 3366 0062 3DD0 beq .L264 +2110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t brrtemp = 0x0000U; + 3367 .loc 1 2110 0 is_stmt 1 + 3368 0064 1025 movs r5, #16 + 3369 .LVL260: + 3370 .L209: +2164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3371 .loc 1 2164 0 + 3372 0066 0220 movs r0, #2 + 3373 0068 FFF7FEFF bl HAL_RCCEx_GetPeriphCLKFreq + 3374 .LVL261: +2167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3375 .loc 1 2167 0 + 3376 006c 2668 ldr r6, [r4] + 3377 006e AA4B ldr r3, .L271+8 + 3378 0070 9E42 cmp r6, r3 + 3379 0072 5BD0 beq .L265 +2224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3380 .loc 1 2224 0 + 3381 0074 8023 movs r3, #128 + 3382 0076 1B02 lsls r3, r3, #8 + 3383 0078 E269 ldr r2, [r4, #28] + 3384 007a 9A42 cmp r2, r3 + ARM GAS /tmp/cc7An1gz.s page 116 + + + 3385 007c 00D1 bne .LCB2994 + 3386 007e 90E0 b .L266 @long jump + 3387 .LCB2994: +2262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3388 .loc 1 2262 0 + 3389 0080 082D cmp r5, #8 + 3390 0082 00D9 bls .LCB2996 + 3391 0084 66E1 b .L260 @long jump + 3392 .LCB2996: + 3393 0086 AD00 lsls r5, r5, #2 + 3394 .LVL262: + 3395 0088 A94B ldr r3, .L271+32 + 3396 008a 5B59 ldr r3, [r3, r5] + 3397 008c 9F46 mov pc, r3 + 3398 .section .rodata.UART_SetConfig,"a",%progbits + 3399 .align 2 + 3400 .L240: + 3401 0000 56020000 .word .L239 + 3402 0004 72020000 .word .L241 + 3403 0008 8E020000 .word .L242 + 3404 000c 54030000 .word .L260 + 3405 0010 C6020000 .word .L243 + 3406 0014 54030000 .word .L260 + 3407 0018 54030000 .word .L260 + 3408 001c 54030000 .word .L260 + 3409 0020 E2020000 .word .L244 + 3410 .section .text.UART_SetConfig + 3411 .LVL263: + 3412 .L262: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3413 .loc 1 2163 0 discriminator 1 + 3414 008e A94B ldr r3, .L271+36 + 3415 0090 DA6C ldr r2, [r3, #76] + 3416 0092 0323 movs r3, #3 + 3417 0094 1340 ands r3, r2 + 3418 0096 012B cmp r3, #1 + 3419 0098 09D0 beq .L207 + 3420 009a 002B cmp r3, #0 + 3421 009c 05D0 beq .L208 + 3422 009e 022B cmp r3, #2 + 3423 00a0 3AD0 beq .L246 + 3424 00a2 032B cmp r3, #3 + 3425 00a4 05D0 beq .L210 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3426 .loc 1 2163 0 is_stmt 0 discriminator 3 + 3427 00a6 1025 movs r5, #16 + 3428 00a8 DDE7 b .L209 + 3429 .L208: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3430 .loc 1 2163 0 + 3431 00aa 0125 movs r5, #1 + 3432 00ac DBE7 b .L209 + 3433 .L207: + 3434 .LVL264: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3435 .loc 1 2163 0 discriminator 5 + 3436 00ae 0425 movs r5, #4 + ARM GAS /tmp/cc7An1gz.s page 117 + + + 3437 00b0 D9E7 b .L209 + 3438 .LVL265: + 3439 .L210: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3440 .loc 1 2163 0 discriminator 7 + 3441 00b2 0825 movs r5, #8 + 3442 00b4 D7E7 b .L209 + 3443 .LVL266: + 3444 .L263: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3445 .loc 1 2163 0 discriminator 13 + 3446 00b6 9F4B ldr r3, .L271+36 + 3447 00b8 DA6C ldr r2, [r3, #76] + 3448 00ba 0C23 movs r3, #12 + 3449 00bc 1340 ands r3, r2 + 3450 00be 042B cmp r3, #4 + 3451 00c0 0AD0 beq .L213 + 3452 00c2 05D9 bls .L267 + 3453 00c4 082B cmp r3, #8 + 3454 00c6 29D0 beq .L247 + 3455 00c8 0C2B cmp r3, #12 + 3456 00ca 07D1 bne .L212 + 3457 .LVL267: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3458 .loc 1 2163 0 discriminator 19 + 3459 00cc 0825 movs r5, #8 + 3460 00ce CAE7 b .L209 + 3461 .LVL268: + 3462 .L267: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3463 .loc 1 2163 0 discriminator 13 + 3464 00d0 002B cmp r3, #0 + 3465 00d2 03D1 bne .L212 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3466 .loc 1 2163 0 + 3467 00d4 0025 movs r5, #0 + 3468 00d6 C6E7 b .L209 + 3469 .L213: + 3470 .LVL269: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3471 .loc 1 2163 0 discriminator 17 + 3472 00d8 0425 movs r5, #4 + 3473 00da C4E7 b .L209 + 3474 .LVL270: + 3475 .L212: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3476 .loc 1 2163 0 discriminator 15 + 3477 00dc 1025 movs r5, #16 + 3478 00de C2E7 b .L209 + 3479 .L264: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3480 .loc 1 2163 0 discriminator 29 + 3481 00e0 944B ldr r3, .L271+36 + 3482 00e2 DB6C ldr r3, [r3, #76] + 3483 00e4 C022 movs r2, #192 + 3484 00e6 1201 lsls r2, r2, #4 + 3485 00e8 1340 ands r3, r2 + ARM GAS /tmp/cc7An1gz.s page 118 + + + 3486 00ea 8022 movs r2, #128 + 3487 00ec D200 lsls r2, r2, #3 + 3488 00ee 9342 cmp r3, r2 + 3489 00f0 0ED0 beq .L218 + 3490 00f2 09D9 bls .L268 + 3491 00f4 8022 movs r2, #128 + 3492 00f6 1201 lsls r2, r2, #4 + 3493 00f8 9342 cmp r3, r2 + 3494 00fa 15D0 beq .L251 + 3495 00fc C022 movs r2, #192 + 3496 00fe 1201 lsls r2, r2, #4 + 3497 0100 9342 cmp r3, r2 + 3498 0102 07D1 bne .L217 + 3499 .LVL271: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3500 .loc 1 2163 0 discriminator 34 + 3501 0104 0825 movs r5, #8 + 3502 0106 AEE7 b .L209 + 3503 .LVL272: + 3504 .L268: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3505 .loc 1 2163 0 discriminator 29 + 3506 0108 002B cmp r3, #0 + 3507 010a 03D1 bne .L217 +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3508 .loc 1 2163 0 + 3509 010c 0025 movs r5, #0 + 3510 010e AAE7 b .L209 + 3511 .L218: + 3512 .LVL273: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3513 .loc 1 2163 0 discriminator 32 + 3514 0110 0425 movs r5, #4 + 3515 0112 A8E7 b .L209 + 3516 .LVL274: + 3517 .L217: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3518 .loc 1 2163 0 discriminator 30 + 3519 0114 1025 movs r5, #16 + 3520 0116 A6E7 b .L209 + 3521 .L246: +2163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_USART2); + 3522 .loc 1 2163 0 + 3523 0118 0225 movs r5, #2 + 3524 011a A4E7 b .L209 + 3525 .L247: + 3526 011c 0225 movs r5, #2 + 3527 011e A2E7 b .L209 + 3528 .L248: + 3529 0120 0025 movs r5, #0 + 3530 0122 A0E7 b .L209 + 3531 .L249: + 3532 0124 0025 movs r5, #0 + 3533 0126 9EE7 b .L209 + 3534 .L251: + 3535 0128 0225 movs r5, #2 + 3536 012a 9CE7 b .L209 + ARM GAS /tmp/cc7An1gz.s page 119 + + + 3537 .LVL275: + 3538 .L265: +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3539 .loc 1 2172 0 is_stmt 1 + 3540 012c 022D cmp r5, #2 + 3541 012e 2DD0 beq .L224 + 3542 0130 07D9 bls .L269 + 3543 0132 042D cmp r5, #4 + 3544 0134 30D0 beq .L227 + 3545 0136 082D cmp r5, #8 + 3546 0138 00D0 beq .LCB3172 + 3547 013a DFE0 b .L252 @long jump + 3548 .LCB3172: +2191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3549 .loc 1 2191 0 + 3550 013c 8020 movs r0, #128 + 3551 .LVL276: + 3552 013e 0002 lsls r0, r0, #8 + 3553 0140 07E0 b .L228 + 3554 .LVL277: + 3555 .L269: +2172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3556 .loc 1 2172 0 + 3557 0142 002D cmp r5, #0 + 3558 0144 00D0 beq .LCB3182 + 3559 0146 D9E0 b .L252 @long jump + 3560 .LCB3182: +2175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3561 .loc 1 2175 0 + 3562 0148 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 3563 .LVL278: + 3564 .L229: +2200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3565 .loc 1 2200 0 + 3566 014c 0028 cmp r0, #0 + 3567 014e 00D1 bne .LCB3193 + 3568 0150 D6E0 b .L270 @long jump + 3569 .LCB3193: + 3570 .LVL279: + 3571 .L228: +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (tmpreg > (4096 * huart->Init.BaudRate) )) + 3572 .loc 1 2203 0 + 3573 0152 6268 ldr r2, [r4, #4] + 3574 0154 5300 lsls r3, r2, #1 + 3575 0156 9B18 adds r3, r3, r2 + 3576 0158 8342 cmp r3, r0 + 3577 015a 00D9 bls .LCB3200 + 3578 015c D2E0 b .L256 @long jump + 3579 .LCB3200: +2204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3580 .loc 1 2204 0 discriminator 1 + 3581 015e 1303 lsls r3, r2, #12 +2203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** (tmpreg > (4096 * huart->Init.BaudRate) )) + 3582 .loc 1 2203 0 discriminator 1 + 3583 0160 8342 cmp r3, r0 + 3584 0162 00D2 bcs .LCB3203 + 3585 0164 D0E0 b .L257 @long jump + ARM GAS /tmp/cc7An1gz.s page 120 + + + 3586 .LCB3203: +2210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3587 .loc 1 2210 0 + 3588 0166 070E lsrs r7, r0, #24 + 3589 0168 0602 lsls r6, r0, #8 + 3590 016a 5008 lsrs r0, r2, #1 + 3591 016c 0021 movs r1, #0 + 3592 016e 8019 adds r0, r0, r6 + 3593 0170 7941 adcs r1, r1, r7 + 3594 0172 0023 movs r3, #0 + 3595 0174 FFF7FEFF bl __aeabi_uldivmod + 3596 .LVL280: +2212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3597 .loc 1 2212 0 + 3598 0178 6F4B ldr r3, .L271+40 + 3599 017a C218 adds r2, r0, r3 + 3600 017c 6F4B ldr r3, .L271+44 + 3601 017e 9A42 cmp r2, r3 + 3602 0180 00D9 bls .LCB3220 + 3603 0182 C3E0 b .L258 @long jump + 3604 .LCB3220: +2214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3605 .loc 1 2214 0 + 3606 0184 2368 ldr r3, [r4] + 3607 0186 D860 str r0, [r3, #12] + 3608 0188 0020 movs r0, #0 + 3609 .LVL281: + 3610 018a 22E0 b .L223 + 3611 .LVL282: + 3612 .L224: +2178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3613 .loc 1 2178 0 + 3614 018c 694B ldr r3, .L271+36 + 3615 018e 1B68 ldr r3, [r3] + 3616 0190 DB06 lsls r3, r3, #27 + 3617 0192 04D4 bmi .L254 +2184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3618 .loc 1 2184 0 + 3619 0194 6A48 ldr r0, .L271+48 + 3620 .LVL283: + 3621 0196 DCE7 b .L228 + 3622 .LVL284: + 3623 .L227: +2188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3624 .loc 1 2188 0 + 3625 0198 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 3626 .LVL285: +2189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: + 3627 .loc 1 2189 0 + 3628 019c D6E7 b .L229 + 3629 .LVL286: + 3630 .L254: +2180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3631 .loc 1 2180 0 + 3632 019e 6948 ldr r0, .L271+52 + 3633 .LVL287: + 3634 01a0 D7E7 b .L228 + ARM GAS /tmp/cc7An1gz.s page 121 + + + 3635 .LVL288: + 3636 .L266: +2226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3637 .loc 1 2226 0 + 3638 01a2 082D cmp r5, #8 + 3639 01a4 54D8 bhi .L259 + 3640 01a6 AD00 lsls r5, r5, #2 + 3641 .LVL289: + 3642 01a8 674B ldr r3, .L271+56 + 3643 01aa 5B59 ldr r3, [r3, r5] + 3644 01ac 9F46 mov pc, r3 + 3645 .section .rodata.UART_SetConfig + 3646 .align 2 + 3647 .L233: + 3648 0024 AE010000 .word .L232 + 3649 0028 D4010000 .word .L234 + 3650 002c EC010000 .word .L235 + 3651 0030 50020000 .word .L259 + 3652 0034 20020000 .word .L236 + 3653 0038 50020000 .word .L259 + 3654 003c 50020000 .word .L259 + 3655 0040 50020000 .word .L259 + 3656 0044 38020000 .word .L237 + 3657 .section .text.UART_SetConfig + 3658 .L232: +2229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3659 .loc 1 2229 0 + 3660 01ae 4000 lsls r0, r0, #1 + 3661 .LVL290: + 3662 01b0 6368 ldr r3, [r4, #4] + 3663 01b2 5B08 lsrs r3, r3, #1 + 3664 01b4 C018 adds r0, r0, r3 + 3665 01b6 6168 ldr r1, [r4, #4] + 3666 01b8 FFF7FEFF bl __aeabi_uidiv + 3667 .LVL291: + 3668 01bc 83B2 uxth r3, r0 + 3669 .LVL292: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3670 .loc 1 2113 0 + 3671 01be 0020 movs r0, #0 + 3672 .LVL293: + 3673 .L231: +2256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** brrtemp |= (uint16_t)((uint16_t)(usartdiv & (uint16_t)0x000FU) >> (uint16_t)1U); + 3674 .loc 1 2256 0 + 3675 01c0 0F22 movs r2, #15 + 3676 01c2 1900 movs r1, r3 + 3677 01c4 9143 bics r1, r2 + 3678 .LVL294: +2257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 3679 .loc 1 2257 0 + 3680 01c6 5B10 asrs r3, r3, #1 + 3681 .LVL295: + 3682 01c8 083A subs r2, r2, #8 + 3683 01ca 1340 ands r3, r2 + 3684 01cc 0B43 orrs r3, r1 + 3685 .LVL296: +2258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + ARM GAS /tmp/cc7An1gz.s page 122 + + + 3686 .loc 1 2258 0 + 3687 01ce 2268 ldr r2, [r4] + 3688 01d0 D360 str r3, [r2, #12] + 3689 .LVL297: + 3690 .L223: +2295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3691 .loc 1 2295 0 + 3692 @ sp needed + 3693 .LVL298: + 3694 01d2 F8BD pop {r3, r4, r5, r6, r7, pc} + 3695 .LVL299: + 3696 .L234: +2232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3697 .loc 1 2232 0 + 3698 01d4 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 3699 .LVL300: + 3700 01d8 4000 lsls r0, r0, #1 + 3701 01da 6368 ldr r3, [r4, #4] + 3702 01dc 5B08 lsrs r3, r3, #1 + 3703 01de C018 adds r0, r0, r3 + 3704 01e0 6168 ldr r1, [r4, #4] + 3705 01e2 FFF7FEFF bl __aeabi_uidiv + 3706 .LVL301: + 3707 01e6 83B2 uxth r3, r0 + 3708 .LVL302: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3709 .loc 1 2113 0 + 3710 01e8 0020 movs r0, #0 +2233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 3711 .loc 1 2233 0 + 3712 01ea E9E7 b .L231 + 3713 .LVL303: + 3714 .L235: +2235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3715 .loc 1 2235 0 + 3716 01ec 514B ldr r3, .L271+36 + 3717 01ee 1B68 ldr r3, [r3] + 3718 01f0 DB06 lsls r3, r3, #27 + 3719 01f2 0AD5 bpl .L238 +2237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3720 .loc 1 2237 0 + 3721 01f4 6368 ldr r3, [r4, #4] + 3722 01f6 5808 lsrs r0, r3, #1 + 3723 .LVL304: + 3724 01f8 544B ldr r3, .L271+60 + 3725 01fa 9C46 mov ip, r3 + 3726 01fc 6044 add r0, r0, ip + 3727 01fe 6168 ldr r1, [r4, #4] + 3728 0200 FFF7FEFF bl __aeabi_uidiv + 3729 .LVL305: + 3730 0204 83B2 uxth r3, r0 + 3731 .LVL306: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3732 .loc 1 2113 0 + 3733 0206 0020 movs r0, #0 + 3734 0208 DAE7 b .L231 + 3735 .LVL307: + ARM GAS /tmp/cc7An1gz.s page 123 + + + 3736 .L238: +2241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3737 .loc 1 2241 0 + 3738 020a 6368 ldr r3, [r4, #4] + 3739 020c 5808 lsrs r0, r3, #1 + 3740 .LVL308: + 3741 020e 504B ldr r3, .L271+64 + 3742 0210 9C46 mov ip, r3 + 3743 0212 6044 add r0, r0, ip + 3744 0214 6168 ldr r1, [r4, #4] + 3745 0216 FFF7FEFF bl __aeabi_uidiv + 3746 .LVL309: + 3747 021a 83B2 uxth r3, r0 + 3748 .LVL310: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3749 .loc 1 2113 0 + 3750 021c 0020 movs r0, #0 + 3751 021e CFE7 b .L231 + 3752 .LVL311: + 3753 .L236: +2245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3754 .loc 1 2245 0 + 3755 0220 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 3756 .LVL312: + 3757 0224 4000 lsls r0, r0, #1 + 3758 0226 6368 ldr r3, [r4, #4] + 3759 0228 5B08 lsrs r3, r3, #1 + 3760 022a C018 adds r0, r0, r3 + 3761 022c 6168 ldr r1, [r4, #4] + 3762 022e FFF7FEFF bl __aeabi_uidiv + 3763 .LVL313: + 3764 0232 83B2 uxth r3, r0 + 3765 .LVL314: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3766 .loc 1 2113 0 + 3767 0234 0020 movs r0, #0 +2246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: + 3768 .loc 1 2246 0 + 3769 0236 C3E7 b .L231 + 3770 .LVL315: + 3771 .L237: +2248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3772 .loc 1 2248 0 + 3773 0238 6368 ldr r3, [r4, #4] + 3774 023a 5808 lsrs r0, r3, #1 + 3775 .LVL316: + 3776 023c 8023 movs r3, #128 + 3777 023e 5B02 lsls r3, r3, #9 + 3778 0240 9C46 mov ip, r3 + 3779 0242 6044 add r0, r0, ip + 3780 0244 6168 ldr r1, [r4, #4] + 3781 0246 FFF7FEFF bl __aeabi_uidiv + 3782 .LVL317: + 3783 024a 83B2 uxth r3, r0 + 3784 .LVL318: +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3785 .loc 1 2113 0 + ARM GAS /tmp/cc7An1gz.s page 124 + + + 3786 024c 0020 movs r0, #0 +2249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_UNDEFINED: + 3787 .loc 1 2249 0 + 3788 024e B7E7 b .L231 + 3789 .LVL319: + 3790 .L259: +2252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3791 .loc 1 2252 0 + 3792 0250 0120 movs r0, #1 + 3793 .LVL320: +2112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; + 3794 .loc 1 2112 0 + 3795 0252 0023 movs r3, #0 + 3796 0254 B4E7 b .L231 + 3797 .LVL321: + 3798 .L239: +2265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3799 .loc 1 2265 0 + 3800 0256 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 3801 .LVL322: + 3802 025a 6368 ldr r3, [r4, #4] + 3803 025c 5B08 lsrs r3, r3, #1 + 3804 025e C018 adds r0, r0, r3 + 3805 0260 6168 ldr r1, [r4, #4] + 3806 0262 FFF7FEFF bl __aeabi_uidiv + 3807 .LVL323: + 3808 0266 2368 ldr r3, [r4] + 3809 0268 0004 lsls r0, r0, #16 + 3810 026a 000C lsrs r0, r0, #16 + 3811 026c D860 str r0, [r3, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3812 .loc 1 2113 0 + 3813 026e 0020 movs r0, #0 +2266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: + 3814 .loc 1 2266 0 + 3815 0270 AFE7 b .L223 + 3816 .LVL324: + 3817 .L241: +2268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3818 .loc 1 2268 0 + 3819 0272 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 3820 .LVL325: + 3821 0276 6368 ldr r3, [r4, #4] + 3822 0278 5B08 lsrs r3, r3, #1 + 3823 027a C018 adds r0, r0, r3 + 3824 027c 6168 ldr r1, [r4, #4] + 3825 027e FFF7FEFF bl __aeabi_uidiv + 3826 .LVL326: + 3827 0282 2368 ldr r3, [r4] + 3828 0284 0004 lsls r0, r0, #16 + 3829 0286 000C lsrs r0, r0, #16 + 3830 0288 D860 str r0, [r3, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3831 .loc 1 2113 0 + 3832 028a 0020 movs r0, #0 +2269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 3833 .loc 1 2269 0 + ARM GAS /tmp/cc7An1gz.s page 125 + + + 3834 028c A1E7 b .L223 + 3835 .LVL327: + 3836 .L242: +2271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3837 .loc 1 2271 0 + 3838 028e 294B ldr r3, .L271+36 + 3839 0290 1B68 ldr r3, [r3] + 3840 0292 DB06 lsls r3, r3, #27 + 3841 0294 0BD5 bpl .L245 +2273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3842 .loc 1 2273 0 + 3843 0296 6168 ldr r1, [r4, #4] + 3844 0298 4808 lsrs r0, r1, #1 + 3845 .LVL328: + 3846 029a 2A4B ldr r3, .L271+52 + 3847 029c 9C46 mov ip, r3 + 3848 029e 6044 add r0, r0, ip + 3849 02a0 FFF7FEFF bl __aeabi_uidiv + 3850 .LVL329: + 3851 02a4 0004 lsls r0, r0, #16 + 3852 02a6 000C lsrs r0, r0, #16 + 3853 02a8 F060 str r0, [r6, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3854 .loc 1 2113 0 + 3855 02aa 0020 movs r0, #0 + 3856 02ac 91E7 b .L223 + 3857 .LVL330: + 3858 .L245: +2277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3859 .loc 1 2277 0 + 3860 02ae 6168 ldr r1, [r4, #4] + 3861 02b0 4808 lsrs r0, r1, #1 + 3862 .LVL331: + 3863 02b2 234B ldr r3, .L271+48 + 3864 02b4 9C46 mov ip, r3 + 3865 02b6 6044 add r0, r0, ip + 3866 02b8 FFF7FEFF bl __aeabi_uidiv + 3867 .LVL332: + 3868 02bc 0004 lsls r0, r0, #16 + 3869 02be 000C lsrs r0, r0, #16 + 3870 02c0 F060 str r0, [r6, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3871 .loc 1 2113 0 + 3872 02c2 0020 movs r0, #0 + 3873 02c4 85E7 b .L223 + 3874 .LVL333: + 3875 .L243: +2281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3876 .loc 1 2281 0 + 3877 02c6 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 3878 .LVL334: + 3879 02ca 6368 ldr r3, [r4, #4] + 3880 02cc 5B08 lsrs r3, r3, #1 + 3881 02ce C018 adds r0, r0, r3 + 3882 02d0 6168 ldr r1, [r4, #4] + 3883 02d2 FFF7FEFF bl __aeabi_uidiv + 3884 .LVL335: + ARM GAS /tmp/cc7An1gz.s page 126 + + + 3885 02d6 2368 ldr r3, [r4] + 3886 02d8 0004 lsls r0, r0, #16 + 3887 02da 000C lsrs r0, r0, #16 + 3888 02dc D860 str r0, [r3, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3889 .loc 1 2113 0 + 3890 02de 0020 movs r0, #0 +2282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: + 3891 .loc 1 2282 0 + 3892 02e0 77E7 b .L223 + 3893 .LVL336: + 3894 .L244: +2284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3895 .loc 1 2284 0 + 3896 02e2 6168 ldr r1, [r4, #4] + 3897 02e4 4808 lsrs r0, r1, #1 + 3898 .LVL337: + 3899 02e6 8023 movs r3, #128 + 3900 02e8 1B02 lsls r3, r3, #8 + 3901 02ea 9C46 mov ip, r3 + 3902 02ec 6044 add r0, r0, ip + 3903 02ee FFF7FEFF bl __aeabi_uidiv + 3904 .LVL338: + 3905 02f2 0004 lsls r0, r0, #16 + 3906 02f4 000C lsrs r0, r0, #16 + 3907 02f6 F060 str r0, [r6, #12] +2113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 3908 .loc 1 2113 0 + 3909 02f8 0020 movs r0, #0 +2285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** case UART_CLOCKSOURCE_UNDEFINED: + 3910 .loc 1 2285 0 + 3911 02fa 6AE7 b .L223 + 3912 .LVL339: + 3913 .L252: +2195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3914 .loc 1 2195 0 + 3915 02fc 0120 movs r0, #1 + 3916 .LVL340: + 3917 02fe 68E7 b .L223 + 3918 .LVL341: + 3919 .L270: + 3920 0300 0020 movs r0, #0 + 3921 .LVL342: + 3922 0302 66E7 b .L223 + 3923 .L256: +2206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3924 .loc 1 2206 0 + 3925 0304 0120 movs r0, #1 + 3926 0306 64E7 b .L223 + 3927 .L257: + 3928 0308 0120 movs r0, #1 + 3929 030a 62E7 b .L223 + 3930 .LVL343: + 3931 .L258: +2218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3932 .loc 1 2218 0 + 3933 030c 0120 movs r0, #1 + ARM GAS /tmp/cc7An1gz.s page 127 + + + 3934 .LVL344: + 3935 030e 60E7 b .L223 + 3936 .L272: + 3937 .align 2 + 3938 .L271: + 3939 0310 F369FFEF .word -268473869 + 3940 0314 FFCFFFFF .word -12289 + 3941 0318 00480040 .word 1073760256 + 3942 031c FFF4FFFF .word -2817 + 3943 0320 00380140 .word 1073821696 + 3944 0324 00440040 .word 1073759232 + 3945 0328 004C0040 .word 1073761280 + 3946 032c 00500040 .word 1073762304 + 3947 0330 00000000 .word .L240 + 3948 0334 00100240 .word 1073876992 + 3949 0338 00FDFFFF .word -768 + 3950 033c FFFC0F00 .word 1047807 + 3951 0340 0024F400 .word 16000000 + 3952 0344 00093D00 .word 4000000 + 3953 0348 24000000 .word .L233 + 3954 034c 00127A00 .word 8000000 + 3955 0350 0048E801 .word 32000000 + 3956 .LVL345: + 3957 .L260: +2288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** break; + 3958 .loc 1 2288 0 + 3959 0354 0120 movs r0, #1 + 3960 .LVL346: + 3961 0356 3CE7 b .L223 + 3962 .cfi_endproc + 3963 .LFE78: + 3965 .section .text.UART_AdvFeatureConfig,"ax",%progbits + 3966 .align 1 + 3967 .global UART_AdvFeatureConfig + 3968 .syntax unified + 3969 .code 16 + 3970 .thumb_func + 3971 .fpu softvfp + 3973 UART_AdvFeatureConfig: + 3974 .LFB79: +2303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ + 3975 .loc 1 2303 0 + 3976 .cfi_startproc + 3977 @ args = 0, pretend = 0, frame = 0 + 3978 @ frame_needed = 0, uses_anonymous_args = 0 + 3979 @ link register save eliminated. + 3980 .LVL347: +2308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3981 .loc 1 2308 0 + 3982 0000 436A ldr r3, [r0, #36] + 3983 0002 DB07 lsls r3, r3, #31 + 3984 0004 06D5 bpl .L274 +2311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3985 .loc 1 2311 0 + 3986 0006 0268 ldr r2, [r0] + 3987 0008 5368 ldr r3, [r2, #4] + 3988 000a 2C49 ldr r1, .L283 + ARM GAS /tmp/cc7An1gz.s page 128 + + + 3989 000c 0B40 ands r3, r1 + 3990 000e 816A ldr r1, [r0, #40] + 3991 0010 0B43 orrs r3, r1 + 3992 0012 5360 str r3, [r2, #4] + 3993 .L274: +2315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 3994 .loc 1 2315 0 + 3995 0014 436A ldr r3, [r0, #36] + 3996 0016 9B07 lsls r3, r3, #30 + 3997 0018 06D5 bpl .L275 +2318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 3998 .loc 1 2318 0 + 3999 001a 0268 ldr r2, [r0] + 4000 001c 5368 ldr r3, [r2, #4] + 4001 001e 2849 ldr r1, .L283+4 + 4002 0020 0B40 ands r3, r1 + 4003 0022 C16A ldr r1, [r0, #44] + 4004 0024 0B43 orrs r3, r1 + 4005 0026 5360 str r3, [r2, #4] + 4006 .L275: +2322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4007 .loc 1 2322 0 + 4008 0028 436A ldr r3, [r0, #36] + 4009 002a 5B07 lsls r3, r3, #29 + 4010 002c 06D5 bpl .L276 +2325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4011 .loc 1 2325 0 + 4012 002e 0268 ldr r2, [r0] + 4013 0030 5368 ldr r3, [r2, #4] + 4014 0032 2449 ldr r1, .L283+8 + 4015 0034 0B40 ands r3, r1 + 4016 0036 016B ldr r1, [r0, #48] + 4017 0038 0B43 orrs r3, r1 + 4018 003a 5360 str r3, [r2, #4] + 4019 .L276: +2329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4020 .loc 1 2329 0 + 4021 003c 436A ldr r3, [r0, #36] + 4022 003e 1B07 lsls r3, r3, #28 + 4023 0040 06D5 bpl .L277 +2332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4024 .loc 1 2332 0 + 4025 0042 0268 ldr r2, [r0] + 4026 0044 5368 ldr r3, [r2, #4] + 4027 0046 2049 ldr r1, .L283+12 + 4028 0048 0B40 ands r3, r1 + 4029 004a 416B ldr r1, [r0, #52] + 4030 004c 0B43 orrs r3, r1 + 4031 004e 5360 str r3, [r2, #4] + 4032 .L277: +2336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4033 .loc 1 2336 0 + 4034 0050 436A ldr r3, [r0, #36] + 4035 0052 DB06 lsls r3, r3, #27 + 4036 0054 06D5 bpl .L278 +2339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4037 .loc 1 2339 0 + ARM GAS /tmp/cc7An1gz.s page 129 + + + 4038 0056 0268 ldr r2, [r0] + 4039 0058 9368 ldr r3, [r2, #8] + 4040 005a 1C49 ldr r1, .L283+16 + 4041 005c 0B40 ands r3, r1 + 4042 005e 816B ldr r1, [r0, #56] + 4043 0060 0B43 orrs r3, r1 + 4044 0062 9360 str r3, [r2, #8] + 4045 .L278: +2343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4046 .loc 1 2343 0 + 4047 0064 436A ldr r3, [r0, #36] + 4048 0066 9B06 lsls r3, r3, #26 + 4049 0068 06D5 bpl .L279 +2346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4050 .loc 1 2346 0 + 4051 006a 0268 ldr r2, [r0] + 4052 006c 9368 ldr r3, [r2, #8] + 4053 006e 1849 ldr r1, .L283+20 + 4054 0070 0B40 ands r3, r1 + 4055 0072 C16B ldr r1, [r0, #60] + 4056 0074 0B43 orrs r3, r1 + 4057 0076 9360 str r3, [r2, #8] + 4058 .L279: +2350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4059 .loc 1 2350 0 + 4060 0078 436A ldr r3, [r0, #36] + 4061 007a 5B06 lsls r3, r3, #25 + 4062 007c 0BD5 bpl .L280 +2354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ + 4063 .loc 1 2354 0 + 4064 007e 0268 ldr r2, [r0] + 4065 0080 5368 ldr r3, [r2, #4] + 4066 0082 1449 ldr r1, .L283+24 + 4067 0084 0B40 ands r3, r1 + 4068 0086 016C ldr r1, [r0, #64] + 4069 0088 0B43 orrs r3, r1 + 4070 008a 5360 str r3, [r2, #4] +2356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4071 .loc 1 2356 0 + 4072 008c 8023 movs r3, #128 + 4073 008e 5B03 lsls r3, r3, #13 + 4074 0090 026C ldr r2, [r0, #64] + 4075 0092 9A42 cmp r2, r3 + 4076 0094 0AD0 beq .L282 + 4077 .L280: +2364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4078 .loc 1 2364 0 + 4079 0096 436A ldr r3, [r0, #36] + 4080 0098 1B06 lsls r3, r3, #24 + 4081 009a 06D5 bpl .L273 +2367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4082 .loc 1 2367 0 + 4083 009c 0268 ldr r2, [r0] + 4084 009e 5368 ldr r3, [r2, #4] + 4085 00a0 0D49 ldr r1, .L283+28 + 4086 00a2 0B40 ands r3, r1 + 4087 00a4 816C ldr r1, [r0, #72] + ARM GAS /tmp/cc7An1gz.s page 130 + + + 4088 00a6 0B43 orrs r3, r1 + 4089 00a8 5360 str r3, [r2, #4] + 4090 .L273: +2369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4091 .loc 1 2369 0 + 4092 @ sp needed + 4093 00aa 7047 bx lr + 4094 .L282: +2359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4095 .loc 1 2359 0 + 4096 00ac 0268 ldr r2, [r0] + 4097 00ae 5368 ldr r3, [r2, #4] + 4098 00b0 0A49 ldr r1, .L283+32 + 4099 00b2 0B40 ands r3, r1 + 4100 00b4 416C ldr r1, [r0, #68] + 4101 00b6 0B43 orrs r3, r1 + 4102 00b8 5360 str r3, [r2, #4] + 4103 00ba ECE7 b .L280 + 4104 .L284: + 4105 .align 2 + 4106 .L283: + 4107 00bc FFFFFDFF .word -131073 + 4108 00c0 FFFFFEFF .word -65537 + 4109 00c4 FFFFFBFF .word -262145 + 4110 00c8 FF7FFFFF .word -32769 + 4111 00cc FFEFFFFF .word -4097 + 4112 00d0 FFDFFFFF .word -8193 + 4113 00d4 FFFFEFFF .word -1048577 + 4114 00d8 FFFFF7FF .word -524289 + 4115 00dc FFFF9FFF .word -6291457 + 4116 .cfi_endproc + 4117 .LFE79: + 4119 .section .text.UART_WaitOnFlagUntilTimeout,"ax",%progbits + 4120 .align 1 + 4121 .global UART_WaitOnFlagUntilTimeout + 4122 .syntax unified + 4123 .code 16 + 4124 .thumb_func + 4125 .fpu softvfp + 4127 UART_WaitOnFlagUntilTimeout: + 4128 .LFB81: +2427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Wait until flag is set */ + 4129 .loc 1 2427 0 + 4130 .cfi_startproc + 4131 @ args = 4, pretend = 0, frame = 0 + 4132 @ frame_needed = 0, uses_anonymous_args = 0 + 4133 .LVL348: + 4134 0000 F0B5 push {r4, r5, r6, r7, lr} + 4135 .LCFI28: + 4136 .cfi_def_cfa_offset 20 + 4137 .cfi_offset 4, -20 + 4138 .cfi_offset 5, -16 + 4139 .cfi_offset 6, -12 + 4140 .cfi_offset 7, -8 + 4141 .cfi_offset 14, -4 + 4142 0002 C646 mov lr, r8 + 4143 0004 00B5 push {lr} + ARM GAS /tmp/cc7An1gz.s page 131 + + + 4144 .LCFI29: + 4145 .cfi_def_cfa_offset 24 + 4146 .cfi_offset 8, -24 + 4147 0006 0600 movs r6, r0 + 4148 0008 0C00 movs r4, r1 + 4149 000a 1700 movs r7, r2 + 4150 000c 9846 mov r8, r3 + 4151 000e 069D ldr r5, [sp, #24] + 4152 .LVL349: + 4153 .L287: +2429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4154 .loc 1 2429 0 + 4155 0010 3368 ldr r3, [r6] + 4156 0012 DB69 ldr r3, [r3, #28] + 4157 0014 2340 ands r3, r4 + 4158 0016 1B1B subs r3, r3, r4 + 4159 0018 5A42 rsbs r2, r3, #0 + 4160 001a 5341 adcs r3, r3, r2 + 4161 001c BB42 cmp r3, r7 + 4162 001e 1ED1 bne .L291 +2432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4163 .loc 1 2432 0 + 4164 0020 6B1C adds r3, r5, #1 + 4165 0022 F5D0 beq .L287 +2434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4166 .loc 1 2434 0 + 4167 0024 002D cmp r5, #0 + 4168 0026 05D0 beq .L288 +2434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4169 .loc 1 2434 0 is_stmt 0 discriminator 1 + 4170 0028 FFF7FEFF bl HAL_GetTick + 4171 .LVL350: + 4172 002c 4346 mov r3, r8 + 4173 002e C01A subs r0, r0, r3 + 4174 0030 A842 cmp r0, r5 + 4175 0032 EDD9 bls .L287 + 4176 .L288: +2437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4177 .loc 1 2437 0 is_stmt 1 + 4178 0034 3268 ldr r2, [r6] + 4179 0036 1368 ldr r3, [r2] + 4180 0038 0B49 ldr r1, .L292 + 4181 003a 0B40 ands r3, r1 + 4182 003c 1360 str r3, [r2] +2438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4183 .loc 1 2438 0 + 4184 003e 3268 ldr r2, [r6] + 4185 0040 9368 ldr r3, [r2, #8] + 4186 0042 A331 adds r1, r1, #163 + 4187 0044 FF31 adds r1, r1, #255 + 4188 0046 8B43 bics r3, r1 + 4189 0048 9360 str r3, [r2, #8] +2440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 4190 .loc 1 2440 0 + 4191 004a 2023 movs r3, #32 + 4192 004c 6922 movs r2, #105 + 4193 004e B354 strb r3, [r6, r2] + ARM GAS /tmp/cc7An1gz.s page 132 + + +2441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4194 .loc 1 2441 0 + 4195 0050 0132 adds r2, r2, #1 + 4196 0052 B354 strb r3, [r6, r2] +2444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** return HAL_TIMEOUT; + 4197 .loc 1 2444 0 + 4198 0054 4833 adds r3, r3, #72 + 4199 0056 0022 movs r2, #0 + 4200 0058 F254 strb r2, [r6, r3] +2445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4201 .loc 1 2445 0 + 4202 005a 0320 movs r0, #3 + 4203 005c 00E0 b .L289 + 4204 .L291: +2449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4205 .loc 1 2449 0 + 4206 005e 0020 movs r0, #0 + 4207 .L289: +2450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4208 .loc 1 2450 0 + 4209 @ sp needed + 4210 .LVL351: + 4211 .LVL352: + 4212 .LVL353: + 4213 0060 04BC pop {r2} + 4214 0062 9046 mov r8, r2 + 4215 0064 F0BD pop {r4, r5, r6, r7, pc} + 4216 .L293: + 4217 0066 C046 .align 2 + 4218 .L292: + 4219 0068 5FFEFFFF .word -417 + 4220 .cfi_endproc + 4221 .LFE81: + 4223 .section .text.HAL_UART_Transmit,"ax",%progbits + 4224 .align 1 + 4225 .global HAL_UART_Transmit + 4226 .syntax unified + 4227 .code 16 + 4228 .thumb_func + 4229 .fpu softvfp + 4231 HAL_UART_Transmit: + 4232 .LFB46: + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; + 4233 .loc 1 659 0 + 4234 .cfi_startproc + 4235 @ args = 0, pretend = 0, frame = 8 + 4236 @ frame_needed = 0, uses_anonymous_args = 0 + 4237 .LVL354: + 4238 0000 F0B5 push {r4, r5, r6, r7, lr} + 4239 .LCFI30: + 4240 .cfi_def_cfa_offset 20 + 4241 .cfi_offset 4, -20 + 4242 .cfi_offset 5, -16 + 4243 .cfi_offset 6, -12 + 4244 .cfi_offset 7, -8 + 4245 .cfi_offset 14, -4 + 4246 0002 85B0 sub sp, sp, #20 + ARM GAS /tmp/cc7An1gz.s page 133 + + + 4247 .LCFI31: + 4248 .cfi_def_cfa_offset 40 + 4249 0004 0400 movs r4, r0 + 4250 0006 0E00 movs r6, r1 + 4251 0008 1700 movs r7, r2 + 4252 000a 1D00 movs r5, r3 + 4253 .LVL355: + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4254 .loc 1 664 0 + 4255 000c 6923 movs r3, #105 + 4256 .LVL356: + 4257 000e C35C ldrb r3, [r0, r3] + 4258 0010 202B cmp r3, #32 + 4259 0012 59D1 bne .L301 + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4260 .loc 1 666 0 + 4261 0014 0029 cmp r1, #0 + 4262 0016 5AD0 beq .L302 + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4263 .loc 1 666 0 is_stmt 0 discriminator 1 + 4264 0018 002A cmp r2, #0 + 4265 001a 5AD0 beq .L303 + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4266 .loc 1 674 0 is_stmt 1 + 4267 001c 8023 movs r3, #128 + 4268 001e 5B01 lsls r3, r3, #5 + 4269 0020 8268 ldr r2, [r0, #8] + 4270 .LVL357: + 4271 0022 9A42 cmp r2, r3 + 4272 0024 13D0 beq .L308 + 4273 .L296: + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4274 .loc 1 683 0 + 4275 0026 6823 movs r3, #104 + 4276 0028 E35C ldrb r3, [r4, r3] + 4277 002a 012B cmp r3, #1 + 4278 002c 53D0 beq .L305 + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4279 .loc 1 683 0 is_stmt 0 discriminator 2 + 4280 002e 6823 movs r3, #104 + 4281 0030 0122 movs r2, #1 + 4282 0032 E254 strb r2, [r4, r3] + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 4283 .loc 1 685 0 is_stmt 1 discriminator 2 + 4284 0034 0023 movs r3, #0 + 4285 0036 E366 str r3, [r4, #108] + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4286 .loc 1 686 0 discriminator 2 + 4287 0038 6933 adds r3, r3, #105 + 4288 003a 2032 adds r2, r2, #32 + 4289 003c E254 strb r2, [r4, r3] + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4290 .loc 1 689 0 discriminator 2 + 4291 003e FFF7FEFF bl HAL_GetTick + 4292 .LVL358: + 4293 0042 0390 str r0, [sp, #12] + 4294 .LVL359: + ARM GAS /tmp/cc7An1gz.s page 134 + + + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->TxXferCount = Size; + 4295 .loc 1 691 0 discriminator 2 + 4296 0044 5023 movs r3, #80 + 4297 0046 E752 strh r7, [r4, r3] + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** while(huart->TxXferCount > 0U) + 4298 .loc 1 692 0 discriminator 2 + 4299 0048 0233 adds r3, r3, #2 + 4300 004a E752 strh r7, [r4, r3] + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4301 .loc 1 693 0 discriminator 2 + 4302 004c 0AE0 b .L297 + 4303 .LVL360: + 4304 .L308: + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4305 .loc 1 674 0 discriminator 1 + 4306 004e 0369 ldr r3, [r0, #16] + 4307 0050 002B cmp r3, #0 + 4308 0052 E8D1 bne .L296 + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4309 .loc 1 676 0 + 4310 0054 CB07 lsls r3, r1, #31 + 4311 0056 E6D5 bpl .L296 + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4312 .loc 1 678 0 + 4313 0058 0120 movs r0, #1 + 4314 .LVL361: + 4315 005a 36E0 b .L295 + 4316 .LVL362: + 4317 .L298: + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4318 .loc 1 708 0 + 4319 005c 3278 ldrb r2, [r6] + 4320 005e 2368 ldr r3, [r4] + 4321 0060 9A62 str r2, [r3, #40] + 4322 0062 0136 adds r6, r6, #1 + 4323 .LVL363: + 4324 .L297: + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4325 .loc 1 693 0 + 4326 0064 5223 movs r3, #82 + 4327 0066 E35A ldrh r3, [r4, r3] + 4328 0068 9BB2 uxth r3, r3 + 4329 006a 002B cmp r3, #0 + 4330 006c 1CD0 beq .L309 + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 4331 .loc 1 695 0 + 4332 006e 5222 movs r2, #82 + 4333 0070 A35A ldrh r3, [r4, r2] + 4334 0072 013B subs r3, r3, #1 + 4335 0074 9BB2 uxth r3, r3 + 4336 0076 A352 strh r3, [r4, r2] + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4337 .loc 1 696 0 + 4338 0078 0095 str r5, [sp] + 4339 007a 039B ldr r3, [sp, #12] + 4340 007c 0022 movs r2, #0 + 4341 007e 8021 movs r1, #128 + ARM GAS /tmp/cc7An1gz.s page 135 + + + 4342 0080 2000 movs r0, r4 + 4343 0082 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 4344 .LVL364: + 4345 0086 0028 cmp r0, #0 + 4346 0088 27D1 bne .L306 + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4347 .loc 1 700 0 + 4348 008a 8023 movs r3, #128 + 4349 008c 5B01 lsls r3, r3, #5 + 4350 008e A268 ldr r2, [r4, #8] + 4351 0090 9A42 cmp r2, r3 + 4352 0092 E3D1 bne .L298 + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4353 .loc 1 700 0 is_stmt 0 discriminator 1 + 4354 0094 2369 ldr r3, [r4, #16] + 4355 0096 002B cmp r3, #0 + 4356 0098 E0D1 bne .L298 + 4357 .LVL365: + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** pData += 2U; + 4358 .loc 1 703 0 is_stmt 1 + 4359 009a 3388 ldrh r3, [r6] + 4360 009c 2268 ldr r2, [r4] + 4361 009e DB05 lsls r3, r3, #23 + 4362 00a0 DB0D lsrs r3, r3, #23 + 4363 00a2 9362 str r3, [r2, #40] + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4364 .loc 1 704 0 + 4365 00a4 0236 adds r6, r6, #2 + 4366 .LVL366: + 4367 00a6 DDE7 b .L297 + 4368 .LVL367: + 4369 .L309: + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4370 .loc 1 711 0 + 4371 00a8 0095 str r5, [sp] + 4372 00aa 039B ldr r3, [sp, #12] + 4373 00ac 0022 movs r2, #0 + 4374 00ae 4021 movs r1, #64 + 4375 00b0 2000 movs r0, r4 + 4376 00b2 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 4377 .LVL368: + 4378 00b6 0028 cmp r0, #0 + 4379 00b8 11D1 bne .L307 + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4380 .loc 1 717 0 + 4381 00ba 6923 movs r3, #105 + 4382 00bc 2022 movs r2, #32 + 4383 00be E254 strb r2, [r4, r3] + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4384 .loc 1 720 0 + 4385 00c0 013B subs r3, r3, #1 + 4386 00c2 0022 movs r2, #0 + 4387 00c4 E254 strb r2, [r4, r3] + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4388 .loc 1 722 0 + 4389 00c6 00E0 b .L295 + 4390 .LVL369: + ARM GAS /tmp/cc7An1gz.s page 136 + + + 4391 .L301: + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4392 .loc 1 726 0 + 4393 00c8 0220 movs r0, #2 + 4394 .LVL370: + 4395 .L295: + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4396 .loc 1 728 0 + 4397 00ca 05B0 add sp, sp, #20 + 4398 @ sp needed + 4399 .LVL371: + 4400 .LVL372: + 4401 .LVL373: + 4402 00cc F0BD pop {r4, r5, r6, r7, pc} + 4403 .LVL374: + 4404 .L302: + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4405 .loc 1 668 0 + 4406 00ce 0120 movs r0, #1 + 4407 .LVL375: + 4408 00d0 FBE7 b .L295 + 4409 .LVL376: + 4410 .L303: + 4411 00d2 0120 movs r0, #1 + 4412 .LVL377: + 4413 00d4 F9E7 b .L295 + 4414 .LVL378: + 4415 .L305: + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4416 .loc 1 683 0 + 4417 00d6 0220 movs r0, #2 + 4418 .LVL379: + 4419 00d8 F7E7 b .L295 + 4420 .LVL380: + 4421 .L306: + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4422 .loc 1 698 0 + 4423 00da 0320 movs r0, #3 + 4424 00dc F5E7 b .L295 + 4425 .L307: + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4426 .loc 1 713 0 + 4427 00de 0320 movs r0, #3 + 4428 00e0 F3E7 b .L295 + 4429 .cfi_endproc + 4430 .LFE46: + 4432 .section .text.HAL_UART_Receive,"ax",%progbits + 4433 .align 1 + 4434 .global HAL_UART_Receive + 4435 .syntax unified + 4436 .code 16 + 4437 .thumb_func + 4438 .fpu softvfp + 4440 HAL_UART_Receive: + 4441 .LFB47: + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint16_t* tmp; + 4442 .loc 1 743 0 + ARM GAS /tmp/cc7An1gz.s page 137 + + + 4443 .cfi_startproc + 4444 @ args = 0, pretend = 0, frame = 8 + 4445 @ frame_needed = 0, uses_anonymous_args = 0 + 4446 .LVL381: + 4447 0000 F0B5 push {r4, r5, r6, r7, lr} + 4448 .LCFI32: + 4449 .cfi_def_cfa_offset 20 + 4450 .cfi_offset 4, -20 + 4451 .cfi_offset 5, -16 + 4452 .cfi_offset 6, -12 + 4453 .cfi_offset 7, -8 + 4454 .cfi_offset 14, -4 + 4455 0002 85B0 sub sp, sp, #20 + 4456 .LCFI33: + 4457 .cfi_def_cfa_offset 40 + 4458 0004 0400 movs r4, r0 + 4459 0006 0F00 movs r7, r1 + 4460 0008 1600 movs r6, r2 + 4461 000a 1D00 movs r5, r3 + 4462 .LVL382: + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4463 .loc 1 749 0 + 4464 000c 6A23 movs r3, #106 + 4465 .LVL383: + 4466 000e C35C ldrb r3, [r0, r3] + 4467 0010 202B cmp r3, #32 + 4468 0012 00D0 beq .LCB4183 + 4469 0014 83E0 b .L323 @long jump + 4470 .LCB4183: + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4471 .loc 1 751 0 + 4472 0016 0029 cmp r1, #0 + 4473 0018 00D1 bne .LCB4185 + 4474 001a 83E0 b .L324 @long jump + 4475 .LCB4185: + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4476 .loc 1 751 0 is_stmt 0 discriminator 1 + 4477 001c 002A cmp r2, #0 + 4478 001e 00D1 bne .LCB4187 + 4479 0020 82E0 b .L325 @long jump + 4480 .LCB4187: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4481 .loc 1 759 0 is_stmt 1 + 4482 0022 8023 movs r3, #128 + 4483 0024 5B01 lsls r3, r3, #5 + 4484 0026 8268 ldr r2, [r0, #8] + 4485 .LVL384: + 4486 0028 9A42 cmp r2, r3 + 4487 002a 21D0 beq .L329 + 4488 .L312: + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4489 .loc 1 768 0 + 4490 002c 6823 movs r3, #104 + 4491 002e E35C ldrb r3, [r4, r3] + 4492 0030 012B cmp r3, #1 + 4493 0032 00D1 bne .LCB4199 + 4494 0034 7AE0 b .L327 @long jump + ARM GAS /tmp/cc7An1gz.s page 138 + + + 4495 .LCB4199: + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4496 .loc 1 768 0 is_stmt 0 discriminator 2 + 4497 0036 6823 movs r3, #104 + 4498 0038 0122 movs r2, #1 + 4499 003a E254 strb r2, [r4, r3] + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 4500 .loc 1 770 0 is_stmt 1 discriminator 2 + 4501 003c 0023 movs r3, #0 + 4502 003e E366 str r3, [r4, #108] + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4503 .loc 1 771 0 discriminator 2 + 4504 0040 6A33 adds r3, r3, #106 + 4505 0042 2132 adds r2, r2, #33 + 4506 0044 E254 strb r2, [r4, r3] + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4507 .loc 1 774 0 discriminator 2 + 4508 0046 FFF7FEFF bl HAL_GetTick + 4509 .LVL385: + 4510 004a 0390 str r0, [sp, #12] + 4511 .LVL386: + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxXferCount = Size; + 4512 .loc 1 776 0 discriminator 2 + 4513 004c 5823 movs r3, #88 + 4514 004e E652 strh r6, [r4, r3] + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4515 .loc 1 777 0 discriminator 2 + 4516 0050 0233 adds r3, r3, #2 + 4517 0052 E652 strh r6, [r4, r3] + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4518 .loc 1 780 0 discriminator 2 + 4519 0054 A368 ldr r3, [r4, #8] + 4520 0056 8022 movs r2, #128 + 4521 0058 5201 lsls r2, r2, #5 + 4522 005a 9342 cmp r3, r2 + 4523 005c 0FD0 beq .L330 + 4524 005e 002B cmp r3, #0 + 4525 0060 1CD1 bne .L316 + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4526 .loc 1 780 0 is_stmt 0 discriminator 5 + 4527 0062 2369 ldr r3, [r4, #16] + 4528 0064 002B cmp r3, #0 + 4529 0066 15D1 bne .L317 + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4530 .loc 1 780 0 discriminator 7 + 4531 0068 5C33 adds r3, r3, #92 + 4532 006a FF22 movs r2, #255 + 4533 006c E252 strh r2, [r4, r3] + 4534 006e 19E0 b .L315 + 4535 .LVL387: + 4536 .L329: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4537 .loc 1 759 0 is_stmt 1 discriminator 1 + 4538 0070 0369 ldr r3, [r0, #16] + 4539 0072 002B cmp r3, #0 + 4540 0074 DAD1 bne .L312 + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + ARM GAS /tmp/cc7An1gz.s page 139 + + + 4541 .loc 1 761 0 + 4542 0076 CB07 lsls r3, r1, #31 + 4543 0078 D8D5 bpl .L312 + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4544 .loc 1 763 0 + 4545 007a 0120 movs r0, #1 + 4546 .LVL388: + 4547 007c 50E0 b .L311 + 4548 .LVL389: + 4549 .L330: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4550 .loc 1 780 0 discriminator 1 + 4551 007e 2369 ldr r3, [r4, #16] + 4552 0080 002B cmp r3, #0 + 4553 0082 03D1 bne .L314 + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4554 .loc 1 780 0 is_stmt 0 discriminator 3 + 4555 0084 5C33 adds r3, r3, #92 + 4556 0086 2B4A ldr r2, .L333 + 4557 0088 E252 strh r2, [r4, r3] + 4558 008a 0BE0 b .L315 + 4559 .L314: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4560 .loc 1 780 0 discriminator 4 + 4561 008c 5C23 movs r3, #92 + 4562 008e FF22 movs r2, #255 + 4563 0090 E252 strh r2, [r4, r3] + 4564 0092 07E0 b .L315 + 4565 .L317: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4566 .loc 1 780 0 discriminator 8 + 4567 0094 5C23 movs r3, #92 + 4568 0096 7F22 movs r2, #127 + 4569 0098 E252 strh r2, [r4, r3] + 4570 009a 03E0 b .L315 + 4571 .L316: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4572 .loc 1 780 0 discriminator 6 + 4573 009c 8022 movs r2, #128 + 4574 009e 5205 lsls r2, r2, #21 + 4575 00a0 9342 cmp r3, r2 + 4576 00a2 02D0 beq .L331 + 4577 .L315: + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4578 .loc 1 781 0 is_stmt 1 + 4579 00a4 5C23 movs r3, #92 + 4580 00a6 E65A ldrh r6, [r4, r3] + 4581 .LVL390: + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4582 .loc 1 784 0 + 4583 00a8 10E0 b .L319 + 4584 .LVL391: + 4585 .L331: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4586 .loc 1 780 0 discriminator 9 + 4587 00aa 2369 ldr r3, [r4, #16] + 4588 00ac 002B cmp r3, #0 + ARM GAS /tmp/cc7An1gz.s page 140 + + + 4589 00ae 03D1 bne .L318 + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4590 .loc 1 780 0 is_stmt 0 discriminator 10 + 4591 00b0 5C33 adds r3, r3, #92 + 4592 00b2 7F22 movs r2, #127 + 4593 00b4 E252 strh r2, [r4, r3] + 4594 00b6 F5E7 b .L315 + 4595 .L318: + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uhMask = huart->Mask; + 4596 .loc 1 780 0 discriminator 11 + 4597 00b8 5C23 movs r3, #92 + 4598 00ba 3F22 movs r2, #63 + 4599 00bc E252 strh r2, [r4, r3] + 4600 00be F1E7 b .L315 + 4601 .LVL392: + 4602 .L320: + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4603 .loc 1 799 0 is_stmt 1 + 4604 00c0 2368 ldr r3, [r4] + 4605 00c2 5B6A ldr r3, [r3, #36] + 4606 00c4 F2B2 uxtb r2, r6 + 4607 .LVL393: + 4608 00c6 1340 ands r3, r2 + 4609 00c8 3B70 strb r3, [r7] + 4610 00ca 0137 adds r7, r7, #1 + 4611 .LVL394: + 4612 .L319: + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4613 .loc 1 784 0 + 4614 00cc 5A23 movs r3, #90 + 4615 00ce E35A ldrh r3, [r4, r3] + 4616 00d0 9BB2 uxth r3, r3 + 4617 00d2 002B cmp r3, #0 + 4618 00d4 1BD0 beq .L332 + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + 4619 .loc 1 786 0 + 4620 00d6 5A22 movs r2, #90 + 4621 00d8 A35A ldrh r3, [r4, r2] + 4622 00da 013B subs r3, r3, #1 + 4623 00dc 9BB2 uxth r3, r3 + 4624 00de A352 strh r3, [r4, r2] + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4625 .loc 1 787 0 + 4626 00e0 0095 str r5, [sp] + 4627 00e2 039B ldr r3, [sp, #12] + 4628 00e4 0022 movs r2, #0 + 4629 00e6 2021 movs r1, #32 + 4630 00e8 2000 movs r0, r4 + 4631 00ea FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 4632 .LVL395: + 4633 00ee 0028 cmp r0, #0 + 4634 00f0 1ED1 bne .L328 + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4635 .loc 1 791 0 + 4636 00f2 8023 movs r3, #128 + 4637 00f4 5B01 lsls r3, r3, #5 + 4638 00f6 A268 ldr r2, [r4, #8] + ARM GAS /tmp/cc7An1gz.s page 141 + + + 4639 00f8 9A42 cmp r2, r3 + 4640 00fa E1D1 bne .L320 + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4641 .loc 1 791 0 is_stmt 0 discriminator 1 + 4642 00fc 2369 ldr r3, [r4, #16] + 4643 00fe 002B cmp r3, #0 + 4644 0100 DED1 bne .L320 + 4645 .LVL396: + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** pData +=2U; + 4646 .loc 1 794 0 is_stmt 1 + 4647 0102 2368 ldr r3, [r4] + 4648 0104 5B6A ldr r3, [r3, #36] + 4649 0106 3340 ands r3, r6 + 4650 0108 3B80 strh r3, [r7] + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4651 .loc 1 795 0 + 4652 010a 0237 adds r7, r7, #2 + 4653 .LVL397: + 4654 010c DEE7 b .L319 + 4655 .LVL398: + 4656 .L332: + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4657 .loc 1 804 0 + 4658 010e 6A33 adds r3, r3, #106 + 4659 0110 2022 movs r2, #32 + 4660 0112 E254 strb r2, [r4, r3] + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4661 .loc 1 807 0 + 4662 0114 023B subs r3, r3, #2 + 4663 0116 0022 movs r2, #0 + 4664 0118 E254 strb r2, [r4, r3] + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4665 .loc 1 809 0 + 4666 011a 0020 movs r0, #0 + 4667 011c 00E0 b .L311 + 4668 .LVL399: + 4669 .L323: + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4670 .loc 1 813 0 + 4671 011e 0220 movs r0, #2 + 4672 .LVL400: + 4673 .L311: + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4674 .loc 1 815 0 + 4675 0120 05B0 add sp, sp, #20 + 4676 @ sp needed + 4677 .LVL401: + 4678 .LVL402: + 4679 .LVL403: + 4680 0122 F0BD pop {r4, r5, r6, r7, pc} + 4681 .LVL404: + 4682 .L324: + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4683 .loc 1 753 0 + 4684 0124 0120 movs r0, #1 + 4685 .LVL405: + 4686 0126 FBE7 b .L311 + ARM GAS /tmp/cc7An1gz.s page 142 + + + 4687 .LVL406: + 4688 .L325: + 4689 0128 0120 movs r0, #1 + 4690 .LVL407: + 4691 012a F9E7 b .L311 + 4692 .LVL408: + 4693 .L327: + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4694 .loc 1 768 0 + 4695 012c 0220 movs r0, #2 + 4696 .LVL409: + 4697 012e F7E7 b .L311 + 4698 .LVL410: + 4699 .L328: + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4700 .loc 1 789 0 + 4701 0130 0320 movs r0, #3 + 4702 0132 F5E7 b .L311 + 4703 .L334: + 4704 .align 2 + 4705 .L333: + 4706 0134 FF010000 .word 511 + 4707 .cfi_endproc + 4708 .LFE47: + 4710 .section .text.UART_CheckIdleState,"ax",%progbits + 4711 .align 1 + 4712 .global UART_CheckIdleState + 4713 .syntax unified + 4714 .code 16 + 4715 .thumb_func + 4716 .fpu softvfp + 4718 UART_CheckIdleState: + 4719 .LFB80: +2377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** uint32_t tickstart = 0; + 4720 .loc 1 2377 0 + 4721 .cfi_startproc + 4722 @ args = 0, pretend = 0, frame = 0 + 4723 @ frame_needed = 0, uses_anonymous_args = 0 + 4724 .LVL411: + 4725 0000 30B5 push {r4, r5, lr} + 4726 .LCFI34: + 4727 .cfi_def_cfa_offset 12 + 4728 .cfi_offset 4, -12 + 4729 .cfi_offset 5, -8 + 4730 .cfi_offset 14, -4 + 4731 0002 83B0 sub sp, sp, #12 + 4732 .LCFI35: + 4733 .cfi_def_cfa_offset 24 + 4734 0004 0400 movs r4, r0 + 4735 .LVL412: +2381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4736 .loc 1 2381 0 + 4737 0006 0023 movs r3, #0 + 4738 0008 C366 str r3, [r0, #108] +2384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4739 .loc 1 2384 0 + 4740 000a FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/cc7An1gz.s page 143 + + + 4741 .LVL413: + 4742 000e 0500 movs r5, r0 + 4743 .LVL414: +2387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4744 .loc 1 2387 0 + 4745 0010 2368 ldr r3, [r4] + 4746 0012 1B68 ldr r3, [r3] + 4747 0014 1B07 lsls r3, r3, #28 + 4748 0016 0ED4 bmi .L341 + 4749 .LVL415: + 4750 .L336: +2397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4751 .loc 1 2397 0 + 4752 0018 2368 ldr r3, [r4] + 4753 001a 1B68 ldr r3, [r3] + 4754 001c 5B07 lsls r3, r3, #29 + 4755 001e 17D4 bmi .L342 + 4756 .L338: +2408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 4757 .loc 1 2408 0 + 4758 0020 2023 movs r3, #32 + 4759 0022 6922 movs r2, #105 + 4760 0024 A354 strb r3, [r4, r2] +2409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4761 .loc 1 2409 0 + 4762 0026 0132 adds r2, r2, #1 + 4763 0028 A354 strb r3, [r4, r2] +2412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4764 .loc 1 2412 0 + 4765 002a 4833 adds r3, r3, #72 + 4766 002c 0022 movs r2, #0 + 4767 002e E254 strb r2, [r4, r3] +2414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4768 .loc 1 2414 0 + 4769 0030 0020 movs r0, #0 + 4770 .L337: +2415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4771 .loc 1 2415 0 + 4772 0032 03B0 add sp, sp, #12 + 4773 @ sp needed + 4774 .LVL416: + 4775 .LVL417: + 4776 0034 30BD pop {r4, r5, pc} + 4777 .LVL418: + 4778 .L341: +2390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4779 .loc 1 2390 0 + 4780 0036 8021 movs r1, #128 + 4781 0038 0C4B ldr r3, .L343 + 4782 003a 0093 str r3, [sp] + 4783 003c 0300 movs r3, r0 + 4784 003e 0022 movs r2, #0 + 4785 0040 8903 lsls r1, r1, #14 + 4786 0042 2000 movs r0, r4 + 4787 .LVL419: + 4788 0044 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 4789 .LVL420: + ARM GAS /tmp/cc7An1gz.s page 144 + + + 4790 0048 0028 cmp r0, #0 + 4791 004a E5D0 beq .L336 +2393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4792 .loc 1 2393 0 + 4793 004c 0320 movs r0, #3 + 4794 004e F0E7 b .L337 + 4795 .L342: +2400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4796 .loc 1 2400 0 + 4797 0050 8021 movs r1, #128 + 4798 0052 064B ldr r3, .L343 + 4799 0054 0093 str r3, [sp] + 4800 0056 2B00 movs r3, r5 + 4801 0058 0022 movs r2, #0 + 4802 005a C903 lsls r1, r1, #15 + 4803 005c 2000 movs r0, r4 + 4804 005e FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 4805 .LVL421: + 4806 0062 0028 cmp r0, #0 + 4807 0064 DCD0 beq .L338 +2403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4808 .loc 1 2403 0 + 4809 0066 0320 movs r0, #3 + 4810 0068 E3E7 b .L337 + 4811 .L344: + 4812 006a C046 .align 2 + 4813 .L343: + 4814 006c FFFFFF01 .word 33554431 + 4815 .cfi_endproc + 4816 .LFE80: + 4818 .section .text.HAL_UART_Init,"ax",%progbits + 4819 .align 1 + 4820 .global HAL_UART_Init + 4821 .syntax unified + 4822 .code 16 + 4823 .thumb_func + 4824 .fpu softvfp + 4826 HAL_UART_Init: + 4827 .LFB39: + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 4828 .loc 1 226 0 + 4829 .cfi_startproc + 4830 @ args = 0, pretend = 0, frame = 0 + 4831 @ frame_needed = 0, uses_anonymous_args = 0 + 4832 .LVL422: + 4833 0000 10B5 push {r4, lr} + 4834 .LCFI36: + 4835 .cfi_def_cfa_offset 8 + 4836 .cfi_offset 4, -8 + 4837 .cfi_offset 14, -4 + 4838 0002 041E subs r4, r0, #0 + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4839 .loc 1 228 0 + 4840 0004 30D0 beq .L349 + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4841 .loc 1 244 0 + 4842 0006 6923 movs r3, #105 + ARM GAS /tmp/cc7An1gz.s page 145 + + + 4843 0008 C35C ldrb r3, [r0, r3] + 4844 000a 002B cmp r3, #0 + 4845 000c 22D0 beq .L350 + 4846 .LVL423: + 4847 .L347: + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4848 .loc 1 253 0 + 4849 000e 6923 movs r3, #105 + 4850 0010 2422 movs r2, #36 + 4851 0012 E254 strb r2, [r4, r3] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4852 .loc 1 256 0 + 4853 0014 2268 ldr r2, [r4] + 4854 0016 1368 ldr r3, [r2] + 4855 0018 0121 movs r1, #1 + 4856 001a 8B43 bics r3, r1 + 4857 001c 1360 str r3, [r2] + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4858 .loc 1 259 0 + 4859 001e 636A ldr r3, [r4, #36] + 4860 0020 002B cmp r3, #0 + 4861 0022 1DD1 bne .L351 + 4862 .L348: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4863 .loc 1 264 0 + 4864 0024 2000 movs r0, r4 + 4865 0026 FFF7FEFF bl UART_SetConfig + 4866 .LVL424: + 4867 002a 0128 cmp r0, #1 + 4868 002c 11D0 beq .L346 + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 4869 .loc 1 272 0 + 4870 002e 2268 ldr r2, [r4] + 4871 0030 5368 ldr r3, [r2, #4] + 4872 0032 0E49 ldr r1, .L352 + 4873 0034 0B40 ands r3, r1 + 4874 0036 5360 str r3, [r2, #4] + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4875 .loc 1 273 0 + 4876 0038 2268 ldr r2, [r4] + 4877 003a 9368 ldr r3, [r2, #8] + 4878 003c 2A21 movs r1, #42 + 4879 003e 8B43 bics r3, r1 + 4880 0040 9360 str r3, [r2, #8] + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4881 .loc 1 276 0 + 4882 0042 2268 ldr r2, [r4] + 4883 0044 1368 ldr r3, [r2] + 4884 0046 2939 subs r1, r1, #41 + 4885 0048 0B43 orrs r3, r1 + 4886 004a 1360 str r3, [r2] + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4887 .loc 1 279 0 + 4888 004c 2000 movs r0, r4 + 4889 004e FFF7FEFF bl UART_CheckIdleState + 4890 .LVL425: + 4891 .L346: + ARM GAS /tmp/cc7An1gz.s page 146 + + + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4892 .loc 1 280 0 + 4893 @ sp needed + 4894 .LVL426: + 4895 0052 10BD pop {r4, pc} + 4896 .LVL427: + 4897 .L350: + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4898 .loc 1 247 0 + 4899 0054 6833 adds r3, r3, #104 + 4900 0056 0022 movs r2, #0 + 4901 0058 C254 strb r2, [r0, r3] + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4902 .loc 1 250 0 + 4903 005a FFF7FEFF bl HAL_UART_MspInit + 4904 .LVL428: + 4905 005e D6E7 b .L347 + 4906 .L351: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4907 .loc 1 261 0 + 4908 0060 2000 movs r0, r4 + 4909 0062 FFF7FEFF bl UART_AdvFeatureConfig + 4910 .LVL429: + 4911 0066 DDE7 b .L348 + 4912 .LVL430: + 4913 .L349: + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 4914 .loc 1 230 0 + 4915 0068 0120 movs r0, #1 + 4916 .LVL431: + 4917 006a F2E7 b .L346 + 4918 .L353: + 4919 .align 2 + 4920 .L352: + 4921 006c FFB7FFFF .word -18433 + 4922 .cfi_endproc + 4923 .LFE39: + 4925 .section .text.HAL_HalfDuplex_Init,"ax",%progbits + 4926 .align 1 + 4927 .global HAL_HalfDuplex_Init + 4928 .syntax unified + 4929 .code 16 + 4930 .thumb_func + 4931 .fpu softvfp + 4933 HAL_HalfDuplex_Init: + 4934 .LFB40: + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 4935 .loc 1 289 0 + 4936 .cfi_startproc + 4937 @ args = 0, pretend = 0, frame = 0 + 4938 @ frame_needed = 0, uses_anonymous_args = 0 + 4939 .LVL432: + 4940 0000 10B5 push {r4, lr} + 4941 .LCFI37: + 4942 .cfi_def_cfa_offset 8 + 4943 .cfi_offset 4, -8 + 4944 .cfi_offset 14, -4 + ARM GAS /tmp/cc7An1gz.s page 147 + + + 4945 0002 041E subs r4, r0, #0 + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4946 .loc 1 291 0 + 4947 0004 35D0 beq .L358 + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4948 .loc 1 299 0 + 4949 0006 6923 movs r3, #105 + 4950 0008 C35C ldrb r3, [r0, r3] + 4951 000a 002B cmp r3, #0 + 4952 000c 27D0 beq .L359 + 4953 .LVL433: + 4954 .L356: + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4955 .loc 1 308 0 + 4956 000e 6923 movs r3, #105 + 4957 0010 2422 movs r2, #36 + 4958 0012 E254 strb r2, [r4, r3] + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4959 .loc 1 311 0 + 4960 0014 2268 ldr r2, [r4] + 4961 0016 1368 ldr r3, [r2] + 4962 0018 0121 movs r1, #1 + 4963 001a 8B43 bics r3, r1 + 4964 001c 1360 str r3, [r2] + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4965 .loc 1 314 0 + 4966 001e 636A ldr r3, [r4, #36] + 4967 0020 002B cmp r3, #0 + 4968 0022 22D1 bne .L360 + 4969 .L357: + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 4970 .loc 1 319 0 + 4971 0024 2000 movs r0, r4 + 4972 0026 FFF7FEFF bl UART_SetConfig + 4973 .LVL434: + 4974 002a 0128 cmp r0, #1 + 4975 002c 16D0 beq .L355 + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 4976 .loc 1 327 0 + 4977 002e 2268 ldr r2, [r4] + 4978 0030 5368 ldr r3, [r2, #4] + 4979 0032 1149 ldr r1, .L361 + 4980 0034 0B40 ands r3, r1 + 4981 0036 5360 str r3, [r2, #4] + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4982 .loc 1 328 0 + 4983 0038 2268 ldr r2, [r4] + 4984 003a 9368 ldr r3, [r2, #8] + 4985 003c 2221 movs r1, #34 + 4986 003e 8B43 bics r3, r1 + 4987 0040 9360 str r3, [r2, #8] + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4988 .loc 1 331 0 + 4989 0042 2268 ldr r2, [r4] + 4990 0044 9368 ldr r3, [r2, #8] + 4991 0046 1A39 subs r1, r1, #26 + 4992 0048 0B43 orrs r3, r1 + ARM GAS /tmp/cc7An1gz.s page 148 + + + 4993 004a 9360 str r3, [r2, #8] + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 4994 .loc 1 334 0 + 4995 004c 2268 ldr r2, [r4] + 4996 004e 1368 ldr r3, [r2] + 4997 0050 0739 subs r1, r1, #7 + 4998 0052 0B43 orrs r3, r1 + 4999 0054 1360 str r3, [r2] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5000 .loc 1 337 0 + 5001 0056 2000 movs r0, r4 + 5002 0058 FFF7FEFF bl UART_CheckIdleState + 5003 .LVL435: + 5004 .L355: + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5005 .loc 1 338 0 + 5006 @ sp needed + 5007 .LVL436: + 5008 005c 10BD pop {r4, pc} + 5009 .LVL437: + 5010 .L359: + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5011 .loc 1 302 0 + 5012 005e 6833 adds r3, r3, #104 + 5013 0060 0022 movs r2, #0 + 5014 0062 C254 strb r2, [r0, r3] + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5015 .loc 1 305 0 + 5016 0064 FFF7FEFF bl HAL_UART_MspInit + 5017 .LVL438: + 5018 0068 D1E7 b .L356 + 5019 .L360: + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5020 .loc 1 316 0 + 5021 006a 2000 movs r0, r4 + 5022 006c FFF7FEFF bl UART_AdvFeatureConfig + 5023 .LVL439: + 5024 0070 D8E7 b .L357 + 5025 .LVL440: + 5026 .L358: + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5027 .loc 1 293 0 + 5028 0072 0120 movs r0, #1 + 5029 .LVL441: + 5030 0074 F2E7 b .L355 + 5031 .L362: + 5032 0076 C046 .align 2 + 5033 .L361: + 5034 0078 FFB7FFFF .word -18433 + 5035 .cfi_endproc + 5036 .LFE40: + 5038 .section .text.HAL_LIN_Init,"ax",%progbits + 5039 .align 1 + 5040 .global HAL_LIN_Init + 5041 .syntax unified + 5042 .code 16 + 5043 .thumb_func + ARM GAS /tmp/cc7An1gz.s page 149 + + + 5044 .fpu softvfp + 5046 HAL_LIN_Init: + 5047 .LFB41: + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 5048 .loc 1 352 0 + 5049 .cfi_startproc + 5050 @ args = 0, pretend = 0, frame = 0 + 5051 @ frame_needed = 0, uses_anonymous_args = 0 + 5052 .LVL442: + 5053 0000 70B5 push {r4, r5, r6, lr} + 5054 .LCFI38: + 5055 .cfi_def_cfa_offset 16 + 5056 .cfi_offset 4, -16 + 5057 .cfi_offset 5, -12 + 5058 .cfi_offset 6, -8 + 5059 .cfi_offset 14, -4 + 5060 0002 0400 movs r4, r0 + 5061 0004 0D00 movs r5, r1 + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5062 .loc 1 354 0 + 5063 0006 0028 cmp r0, #0 + 5064 0008 44D0 beq .L367 + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5065 .loc 1 365 0 + 5066 000a 8023 movs r3, #128 + 5067 000c 1B02 lsls r3, r3, #8 + 5068 000e C269 ldr r2, [r0, #28] + 5069 0010 9A42 cmp r2, r3 + 5070 0012 41D0 beq .L368 + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5071 .loc 1 370 0 + 5072 0014 8368 ldr r3, [r0, #8] + 5073 0016 002B cmp r3, #0 + 5074 0018 40D1 bne .L369 + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5075 .loc 1 375 0 + 5076 001a 6933 adds r3, r3, #105 + 5077 001c C35C ldrb r3, [r0, r3] + 5078 001e 002B cmp r3, #0 + 5079 0020 2ED0 beq .L370 + 5080 .LVL443: + 5081 .L365: + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5082 .loc 1 384 0 + 5083 0022 6923 movs r3, #105 + 5084 0024 2422 movs r2, #36 + 5085 0026 E254 strb r2, [r4, r3] + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5086 .loc 1 387 0 + 5087 0028 2268 ldr r2, [r4] + 5088 002a 1368 ldr r3, [r2] + 5089 002c 0121 movs r1, #1 + 5090 002e 8B43 bics r3, r1 + 5091 0030 1360 str r3, [r2] + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5092 .loc 1 390 0 + 5093 0032 636A ldr r3, [r4, #36] + ARM GAS /tmp/cc7An1gz.s page 150 + + + 5094 0034 002B cmp r3, #0 + 5095 0036 29D1 bne .L371 + 5096 .L366: + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5097 .loc 1 395 0 + 5098 0038 2000 movs r0, r4 + 5099 003a FFF7FEFF bl UART_SetConfig + 5100 .LVL444: + 5101 003e 0128 cmp r0, #1 + 5102 0040 29D0 beq .L364 + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 5103 .loc 1 403 0 + 5104 0042 2268 ldr r2, [r4] + 5105 0044 5368 ldr r3, [r2, #4] + 5106 0046 1649 ldr r1, .L372 + 5107 0048 0B40 ands r3, r1 + 5108 004a 5360 str r3, [r2, #4] + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5109 .loc 1 404 0 + 5110 004c 2268 ldr r2, [r4] + 5111 004e 9368 ldr r3, [r2, #8] + 5112 0050 2A21 movs r1, #42 + 5113 0052 8B43 bics r3, r1 + 5114 0054 9360 str r3, [r2, #8] + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5115 .loc 1 407 0 + 5116 0056 2268 ldr r2, [r4] + 5117 0058 5168 ldr r1, [r2, #4] + 5118 005a 8023 movs r3, #128 + 5119 005c DB01 lsls r3, r3, #7 + 5120 005e 0B43 orrs r3, r1 + 5121 0060 5360 str r3, [r2, #4] + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5122 .loc 1 410 0 + 5123 0062 2268 ldr r2, [r4] + 5124 0064 5368 ldr r3, [r2, #4] + 5125 0066 2021 movs r1, #32 + 5126 0068 8B43 bics r3, r1 + 5127 006a 1D43 orrs r5, r3 + 5128 .LVL445: + 5129 006c 5560 str r5, [r2, #4] + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5130 .loc 1 413 0 + 5131 006e 2268 ldr r2, [r4] + 5132 0070 1368 ldr r3, [r2] + 5133 0072 1F39 subs r1, r1, #31 + 5134 0074 0B43 orrs r3, r1 + 5135 0076 1360 str r3, [r2] + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5136 .loc 1 416 0 + 5137 0078 2000 movs r0, r4 + 5138 007a FFF7FEFF bl UART_CheckIdleState + 5139 .LVL446: + 5140 007e 0AE0 b .L364 + 5141 .LVL447: + 5142 .L370: + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + ARM GAS /tmp/cc7An1gz.s page 151 + + + 5143 .loc 1 378 0 + 5144 0080 6833 adds r3, r3, #104 + 5145 0082 0022 movs r2, #0 + 5146 0084 C254 strb r2, [r0, r3] + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5147 .loc 1 381 0 + 5148 0086 FFF7FEFF bl HAL_UART_MspInit + 5149 .LVL448: + 5150 008a CAE7 b .L365 + 5151 .L371: + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5152 .loc 1 392 0 + 5153 008c 2000 movs r0, r4 + 5154 008e FFF7FEFF bl UART_AdvFeatureConfig + 5155 .LVL449: + 5156 0092 D1E7 b .L366 + 5157 .LVL450: + 5158 .L367: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5159 .loc 1 356 0 + 5160 0094 0120 movs r0, #1 + 5161 .LVL451: + 5162 .L364: + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5163 .loc 1 417 0 + 5164 @ sp needed + 5165 .LVL452: + 5166 0096 70BD pop {r4, r5, r6, pc} + 5167 .LVL453: + 5168 .L368: + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5169 .loc 1 367 0 + 5170 0098 0120 movs r0, #1 + 5171 .LVL454: + 5172 009a FCE7 b .L364 + 5173 .LVL455: + 5174 .L369: + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5175 .loc 1 372 0 + 5176 009c 0120 movs r0, #1 + 5177 .LVL456: + 5178 009e FAE7 b .L364 + 5179 .L373: + 5180 .align 2 + 5181 .L372: + 5182 00a0 FFF7FFFF .word -2049 + 5183 .cfi_endproc + 5184 .LFE41: + 5186 .section .text.HAL_MultiProcessor_Init,"ax",%progbits + 5187 .align 1 + 5188 .global HAL_MultiProcessor_Init + 5189 .syntax unified + 5190 .code 16 + 5191 .thumb_func + 5192 .fpu softvfp + 5194 HAL_MultiProcessor_Init: + 5195 .LFB42: + ARM GAS /tmp/cc7An1gz.s page 152 + + + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Check the UART handle allocation */ + 5196 .loc 1 439 0 + 5197 .cfi_startproc + 5198 @ args = 0, pretend = 0, frame = 0 + 5199 @ frame_needed = 0, uses_anonymous_args = 0 + 5200 .LVL457: + 5201 0000 70B5 push {r4, r5, r6, lr} + 5202 .LCFI39: + 5203 .cfi_def_cfa_offset 16 + 5204 .cfi_offset 4, -16 + 5205 .cfi_offset 5, -12 + 5206 .cfi_offset 6, -8 + 5207 .cfi_offset 14, -4 + 5208 0002 0400 movs r4, r0 + 5209 0004 0D00 movs r5, r1 + 5210 0006 1600 movs r6, r2 + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5211 .loc 1 441 0 + 5212 0008 0028 cmp r0, #0 + 5213 000a 42D0 beq .L379 + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5214 .loc 1 449 0 + 5215 000c 6923 movs r3, #105 + 5216 000e C35C ldrb r3, [r0, r3] + 5217 0010 002B cmp r3, #0 + 5218 0012 2CD0 beq .L380 + 5219 .LVL458: + 5220 .L376: + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5221 .loc 1 458 0 + 5222 0014 6923 movs r3, #105 + 5223 0016 2422 movs r2, #36 + 5224 0018 E254 strb r2, [r4, r3] + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5225 .loc 1 461 0 + 5226 001a 2268 ldr r2, [r4] + 5227 001c 1368 ldr r3, [r2] + 5228 001e 0121 movs r1, #1 + 5229 0020 8B43 bics r3, r1 + 5230 0022 1360 str r3, [r2] + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5231 .loc 1 464 0 + 5232 0024 636A ldr r3, [r4, #36] + 5233 0026 002B cmp r3, #0 + 5234 0028 27D1 bne .L381 + 5235 .L377: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5236 .loc 1 469 0 + 5237 002a 2000 movs r0, r4 + 5238 002c FFF7FEFF bl UART_SetConfig + 5239 .LVL459: + 5240 0030 0128 cmp r0, #1 + 5241 0032 1BD0 beq .L375 + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 5242 .loc 1 477 0 + 5243 0034 2268 ldr r2, [r4] + 5244 0036 5368 ldr r3, [r2, #4] + ARM GAS /tmp/cc7An1gz.s page 153 + + + 5245 0038 1749 ldr r1, .L383 + 5246 003a 0B40 ands r3, r1 + 5247 003c 5360 str r3, [r2, #4] + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5248 .loc 1 478 0 + 5249 003e 2268 ldr r2, [r4] + 5250 0040 9368 ldr r3, [r2, #8] + 5251 0042 2A21 movs r1, #42 + 5252 0044 8B43 bics r3, r1 + 5253 0046 9360 str r3, [r2, #8] + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** { + 5254 .loc 1 480 0 + 5255 0048 8023 movs r3, #128 + 5256 004a 1B01 lsls r3, r3, #4 + 5257 004c 9E42 cmp r6, r3 + 5258 004e 18D0 beq .L382 + 5259 .L378: + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5260 .loc 1 487 0 + 5261 0050 2368 ldr r3, [r4] + 5262 0052 1A68 ldr r2, [r3] + 5263 0054 1149 ldr r1, .L383+4 + 5264 0056 0A40 ands r2, r1 + 5265 0058 3243 orrs r2, r6 + 5266 005a 1A60 str r2, [r3] + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5267 .loc 1 490 0 + 5268 005c 2268 ldr r2, [r4] + 5269 005e 1368 ldr r3, [r2] + 5270 0060 0121 movs r1, #1 + 5271 0062 0B43 orrs r3, r1 + 5272 0064 1360 str r3, [r2] + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5273 .loc 1 493 0 + 5274 0066 2000 movs r0, r4 + 5275 0068 FFF7FEFF bl UART_CheckIdleState + 5276 .LVL460: + 5277 .L375: + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5278 .loc 1 494 0 + 5279 @ sp needed + 5280 .LVL461: + 5281 .LVL462: + 5282 006c 70BD pop {r4, r5, r6, pc} + 5283 .LVL463: + 5284 .L380: + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5285 .loc 1 452 0 + 5286 006e 6833 adds r3, r3, #104 + 5287 0070 0022 movs r2, #0 + 5288 .LVL464: + 5289 0072 C254 strb r2, [r0, r3] + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5290 .loc 1 455 0 + 5291 0074 FFF7FEFF bl HAL_UART_MspInit + 5292 .LVL465: + 5293 0078 CCE7 b .L376 + ARM GAS /tmp/cc7An1gz.s page 154 + + + 5294 .L381: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5295 .loc 1 466 0 + 5296 007a 2000 movs r0, r4 + 5297 007c FFF7FEFF bl UART_AdvFeatureConfig + 5298 .LVL466: + 5299 0080 D3E7 b .L377 + 5300 .L382: + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5301 .loc 1 483 0 + 5302 0082 2268 ldr r2, [r4] + 5303 0084 5368 ldr r3, [r2, #4] + 5304 0086 1B02 lsls r3, r3, #8 + 5305 0088 1B0A lsrs r3, r3, #8 + 5306 008a 2D06 lsls r5, r5, #24 + 5307 008c 1D43 orrs r5, r3 + 5308 008e 5560 str r5, [r2, #4] + 5309 0090 DEE7 b .L378 + 5310 .LVL467: + 5311 .L379: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5312 .loc 1 443 0 + 5313 0092 0120 movs r0, #1 + 5314 .LVL468: + 5315 0094 EAE7 b .L375 + 5316 .L384: + 5317 0096 C046 .align 2 + 5318 .L383: + 5319 0098 FFB7FFFF .word -18433 + 5320 009c FFF7FFFF .word -2049 + 5321 .cfi_endproc + 5322 .LFE42: + 5324 .section .text.HAL_MultiProcessor_EnableMuteMode,"ax",%progbits + 5325 .align 1 + 5326 .global HAL_MultiProcessor_EnableMuteMode + 5327 .syntax unified + 5328 .code 16 + 5329 .thumb_func + 5330 .fpu softvfp + 5332 HAL_MultiProcessor_EnableMuteMode: + 5333 .LFB70: +1924:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 5334 .loc 1 1924 0 + 5335 .cfi_startproc + 5336 @ args = 0, pretend = 0, frame = 0 + 5337 @ frame_needed = 0, uses_anonymous_args = 0 + 5338 .LVL469: + 5339 0000 10B5 push {r4, lr} + 5340 .LCFI40: + 5341 .cfi_def_cfa_offset 8 + 5342 .cfi_offset 4, -8 + 5343 .cfi_offset 14, -4 +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5344 .loc 1 1926 0 + 5345 0002 6823 movs r3, #104 + 5346 0004 C35C ldrb r3, [r0, r3] + 5347 0006 012B cmp r3, #1 + ARM GAS /tmp/cc7An1gz.s page 155 + + + 5348 0008 10D0 beq .L387 +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5349 .loc 1 1926 0 is_stmt 0 discriminator 2 + 5350 000a 6823 movs r3, #104 + 5351 000c 0122 movs r2, #1 + 5352 000e C254 strb r2, [r0, r3] +1928:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5353 .loc 1 1928 0 is_stmt 1 discriminator 2 + 5354 0010 6832 adds r2, r2, #104 + 5355 0012 443B subs r3, r3, #68 + 5356 0014 8354 strb r3, [r0, r2] +1931:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5357 .loc 1 1931 0 discriminator 2 + 5358 0016 0168 ldr r1, [r0] + 5359 0018 0C68 ldr r4, [r1] + 5360 001a 8023 movs r3, #128 + 5361 001c 9B01 lsls r3, r3, #6 + 5362 001e 2343 orrs r3, r4 + 5363 0020 0B60 str r3, [r1] +1933:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5364 .loc 1 1933 0 discriminator 2 + 5365 0022 2023 movs r3, #32 + 5366 0024 8354 strb r3, [r0, r2] +1935:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5367 .loc 1 1935 0 discriminator 2 + 5368 0026 FFF7FEFF bl UART_CheckIdleState + 5369 .LVL470: + 5370 .L386: +1936:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5371 .loc 1 1936 0 + 5372 @ sp needed + 5373 002a 10BD pop {r4, pc} + 5374 .LVL471: + 5375 .L387: +1926:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5376 .loc 1 1926 0 + 5377 002c 0220 movs r0, #2 + 5378 .LVL472: + 5379 002e FCE7 b .L386 + 5380 .cfi_endproc + 5381 .LFE70: + 5383 .section .text.HAL_MultiProcessor_DisableMuteMode,"ax",%progbits + 5384 .align 1 + 5385 .global HAL_MultiProcessor_DisableMuteMode + 5386 .syntax unified + 5387 .code 16 + 5388 .thumb_func + 5389 .fpu softvfp + 5391 HAL_MultiProcessor_DisableMuteMode: + 5392 .LFB71: +1945:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** /* Process Locked */ + 5393 .loc 1 1945 0 + 5394 .cfi_startproc + 5395 @ args = 0, pretend = 0, frame = 0 + 5396 @ frame_needed = 0, uses_anonymous_args = 0 + 5397 .LVL473: + 5398 0000 10B5 push {r4, lr} + ARM GAS /tmp/cc7An1gz.s page 156 + + + 5399 .LCFI41: + 5400 .cfi_def_cfa_offset 8 + 5401 .cfi_offset 4, -8 + 5402 .cfi_offset 14, -4 +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5403 .loc 1 1947 0 + 5404 0002 6823 movs r3, #104 + 5405 0004 C35C ldrb r3, [r0, r3] + 5406 0006 012B cmp r3, #1 + 5407 0008 0FD0 beq .L390 +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5408 .loc 1 1947 0 is_stmt 0 discriminator 2 + 5409 000a 6823 movs r3, #104 + 5410 000c 0122 movs r2, #1 + 5411 000e C254 strb r2, [r0, r3] +1949:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5412 .loc 1 1949 0 is_stmt 1 discriminator 2 + 5413 0010 6832 adds r2, r2, #104 + 5414 0012 443B subs r3, r3, #68 + 5415 0014 8354 strb r3, [r0, r2] +1952:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5416 .loc 1 1952 0 discriminator 2 + 5417 0016 0168 ldr r1, [r0] + 5418 0018 0B68 ldr r3, [r1] + 5419 001a 054C ldr r4, .L391 + 5420 001c 2340 ands r3, r4 + 5421 001e 0B60 str r3, [r1] +1954:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5422 .loc 1 1954 0 discriminator 2 + 5423 0020 2023 movs r3, #32 + 5424 0022 8354 strb r3, [r0, r2] +1956:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** } + 5425 .loc 1 1956 0 discriminator 2 + 5426 0024 FFF7FEFF bl UART_CheckIdleState + 5427 .LVL474: + 5428 .L389: +1957:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5429 .loc 1 1957 0 + 5430 @ sp needed + 5431 0028 10BD pop {r4, pc} + 5432 .LVL475: + 5433 .L390: +1947:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c **** + 5434 .loc 1 1947 0 + 5435 002a 0220 movs r0, #2 + 5436 .LVL476: + 5437 002c FCE7 b .L389 + 5438 .L392: + 5439 002e C046 .align 2 + 5440 .L391: + 5441 0030 FFDFFFFF .word -8193 + 5442 .cfi_endproc + 5443 .LFE71: + 5445 .text + 5446 .Letext0: + 5447 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 5448 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + ARM GAS /tmp/cc7An1gz.s page 157 + + + 5449 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 5450 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 5451 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 5452 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 5453 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 5454 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 5455 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + 5456 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 5457 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 5458 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h" + 5459 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 5460 .file 15 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h" + 5461 .file 16 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h" + 5462 .file 17 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h" + ARM GAS /tmp/cc7An1gz.s page 158 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_uart.c + /tmp/cc7An1gz.s:16 .text.HAL_UART_MspInit:0000000000000000 $t + /tmp/cc7An1gz.s:23 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit + /tmp/cc7An1gz.s:39 .text.HAL_UART_MspDeInit:0000000000000000 $t + /tmp/cc7An1gz.s:46 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit + /tmp/cc7An1gz.s:61 .text.HAL_UART_DeInit:0000000000000000 $t + /tmp/cc7An1gz.s:68 .text.HAL_UART_DeInit:0000000000000000 HAL_UART_DeInit + /tmp/cc7An1gz.s:135 .text.HAL_UART_Transmit_IT:0000000000000000 $t + /tmp/cc7An1gz.s:142 .text.HAL_UART_Transmit_IT:0000000000000000 HAL_UART_Transmit_IT + /tmp/cc7An1gz.s:250 .text.HAL_UART_Receive_IT:0000000000000000 $t + /tmp/cc7An1gz.s:257 .text.HAL_UART_Receive_IT:0000000000000000 HAL_UART_Receive_IT + /tmp/cc7An1gz.s:451 .text.HAL_UART_Receive_IT:00000000000000d0 $d + /tmp/cc7An1gz.s:456 .text.HAL_UART_Transmit_DMA:0000000000000000 $t + /tmp/cc7An1gz.s:463 .text.HAL_UART_Transmit_DMA:0000000000000000 HAL_UART_Transmit_DMA + /tmp/cc7An1gz.s:598 .text.HAL_UART_Transmit_DMA:000000000000009c $d + /tmp/cc7An1gz.s:1362 .text.UART_DMATransmitCplt:0000000000000000 UART_DMATransmitCplt + /tmp/cc7An1gz.s:1445 .text.UART_DMATxHalfCplt:0000000000000000 UART_DMATxHalfCplt + /tmp/cc7An1gz.s:1776 .text.UART_DMAError:0000000000000000 UART_DMAError + /tmp/cc7An1gz.s:605 .text.HAL_UART_Receive_DMA:0000000000000000 $t + /tmp/cc7An1gz.s:612 .text.HAL_UART_Receive_DMA:0000000000000000 HAL_UART_Receive_DMA + /tmp/cc7An1gz.s:753 .text.HAL_UART_Receive_DMA:00000000000000a4 $d + /tmp/cc7An1gz.s:1498 .text.UART_DMAReceiveCplt:0000000000000000 UART_DMAReceiveCplt + /tmp/cc7An1gz.s:1723 .text.UART_DMARxHalfCplt:0000000000000000 UART_DMARxHalfCplt + /tmp/cc7An1gz.s:760 .text.HAL_UART_DMAPause:0000000000000000 $t + /tmp/cc7An1gz.s:767 .text.HAL_UART_DMAPause:0000000000000000 HAL_UART_DMAPause + /tmp/cc7An1gz.s:855 .text.HAL_UART_DMAPause:0000000000000068 $d + /tmp/cc7An1gz.s:860 .text.HAL_UART_DMAResume:0000000000000000 $t + /tmp/cc7An1gz.s:867 .text.HAL_UART_DMAResume:0000000000000000 HAL_UART_DMAResume + /tmp/cc7An1gz.s:950 .text.HAL_UART_DMAStop:0000000000000000 $t + /tmp/cc7An1gz.s:957 .text.HAL_UART_DMAStop:0000000000000000 HAL_UART_DMAStop + /tmp/cc7An1gz.s:1069 .text.HAL_UART_DMAStop:000000000000007c $d + /tmp/cc7An1gz.s:1076 .text.HAL_UART_Abort:0000000000000000 $t + /tmp/cc7An1gz.s:1083 .text.HAL_UART_Abort:0000000000000000 HAL_UART_Abort + /tmp/cc7An1gz.s:1182 .text.HAL_UART_Abort:000000000000007c $d + /tmp/cc7An1gz.s:1187 .text.HAL_UART_AbortTransmit:0000000000000000 $t + /tmp/cc7An1gz.s:1194 .text.HAL_UART_AbortTransmit:0000000000000000 HAL_UART_AbortTransmit + /tmp/cc7An1gz.s:1253 .text.HAL_UART_AbortReceive:0000000000000000 $t + /tmp/cc7An1gz.s:1260 .text.HAL_UART_AbortReceive:0000000000000000 HAL_UART_AbortReceive + /tmp/cc7An1gz.s:1329 .text.HAL_UART_AbortReceive:0000000000000050 $d + /tmp/cc7An1gz.s:1334 .text.HAL_UART_TxCpltCallback:0000000000000000 $t + /tmp/cc7An1gz.s:1341 .text.HAL_UART_TxCpltCallback:0000000000000000 HAL_UART_TxCpltCallback + /tmp/cc7An1gz.s:1356 .text.UART_DMATransmitCplt:0000000000000000 $t + /tmp/cc7An1gz.s:1417 .text.HAL_UART_TxHalfCpltCallback:0000000000000000 $t + /tmp/cc7An1gz.s:1424 .text.HAL_UART_TxHalfCpltCallback:0000000000000000 HAL_UART_TxHalfCpltCallback + /tmp/cc7An1gz.s:1439 .text.UART_DMATxHalfCplt:0000000000000000 $t + /tmp/cc7An1gz.s:1470 .text.HAL_UART_RxCpltCallback:0000000000000000 $t + /tmp/cc7An1gz.s:1477 .text.HAL_UART_RxCpltCallback:0000000000000000 HAL_UART_RxCpltCallback + /tmp/cc7An1gz.s:1492 .text.UART_DMAReceiveCplt:0000000000000000 $t + /tmp/cc7An1gz.s:1557 .text.UART_DMAReceiveCplt:0000000000000040 $d + /tmp/cc7An1gz.s:1562 .text.UART_Receive_IT:0000000000000000 $t + /tmp/cc7An1gz.s:1568 .text.UART_Receive_IT:0000000000000000 UART_Receive_IT + /tmp/cc7An1gz.s:1690 .text.UART_Receive_IT:0000000000000084 $d + /tmp/cc7An1gz.s:1695 .text.HAL_UART_RxHalfCpltCallback:0000000000000000 $t + /tmp/cc7An1gz.s:1702 .text.HAL_UART_RxHalfCpltCallback:0000000000000000 HAL_UART_RxHalfCpltCallback + /tmp/cc7An1gz.s:1717 .text.UART_DMARxHalfCplt:0000000000000000 $t + /tmp/cc7An1gz.s:1748 .text.HAL_UART_ErrorCallback:0000000000000000 $t + ARM GAS /tmp/cc7An1gz.s page 159 + + + /tmp/cc7An1gz.s:1755 .text.HAL_UART_ErrorCallback:0000000000000000 HAL_UART_ErrorCallback + /tmp/cc7An1gz.s:1770 .text.UART_DMAError:0000000000000000 $t + /tmp/cc7An1gz.s:1874 .text.UART_DMAError:000000000000006c $d + /tmp/cc7An1gz.s:1881 .text.HAL_UART_IRQHandler:0000000000000000 $t + /tmp/cc7An1gz.s:1888 .text.HAL_UART_IRQHandler:0000000000000000 HAL_UART_IRQHandler + /tmp/cc7An1gz.s:2265 .text.HAL_UART_IRQHandler:00000000000001c0 $d + /tmp/cc7An1gz.s:2279 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.text.HAL_UART_AbortTransmitCpltCallback:0000000000000000 HAL_UART_AbortTransmitCpltCallback + /tmp/cc7An1gz.s:2675 .text.HAL_UART_AbortTransmit_IT:0000000000000000 $t + /tmp/cc7An1gz.s:2682 .text.HAL_UART_AbortTransmit_IT:0000000000000000 HAL_UART_AbortTransmit_IT + /tmp/cc7An1gz.s:2767 .text.HAL_UART_AbortTransmit_IT:0000000000000060 $d + /tmp/cc7An1gz.s:2778 .text.UART_DMATxOnlyAbortCallback:0000000000000000 UART_DMATxOnlyAbortCallback + /tmp/cc7An1gz.s:2772 .text.UART_DMATxOnlyAbortCallback:0000000000000000 $t + /tmp/cc7An1gz.s:2811 .text.HAL_UART_AbortReceiveCpltCallback:0000000000000000 $t + /tmp/cc7An1gz.s:2818 .text.HAL_UART_AbortReceiveCpltCallback:0000000000000000 HAL_UART_AbortReceiveCpltCallback + /tmp/cc7An1gz.s:2833 .text.HAL_UART_AbortReceive_IT:0000000000000000 $t + /tmp/cc7An1gz.s:2840 .text.HAL_UART_AbortReceive_IT:0000000000000000 HAL_UART_AbortReceive_IT + /tmp/cc7An1gz.s:2939 .text.HAL_UART_AbortReceive_IT:0000000000000078 $d + /tmp/cc7An1gz.s:2951 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.text.HAL_MultiProcessor_DisableMuteMode:0000000000000030 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort +HAL_DMA_Abort_IT +HAL_UARTEx_WakeupCallback +__aeabi_uldivmod +__aeabi_uidiv +HAL_RCCEx_GetPeriphCLKFreq +HAL_RCC_GetPCLK1Freq +HAL_RCC_GetSysClockFreq +HAL_RCC_GetPCLK2Freq +HAL_GetTick diff --git a/build/stm32l0xx_hal_uart_ex.d b/build/stm32l0xx_hal_uart_ex.d new file mode 100644 index 0000000..573f4a3 --- /dev/null +++ b/build/stm32l0xx_hal_uart_ex.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_uart_ex.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_uart_ex.lst b/build/stm32l0xx_hal_uart_ex.lst new file mode 100644 index 0000000..1146920 --- /dev/null +++ b/build/stm32l0xx_hal_uart_ex.lst @@ -0,0 +1,1291 @@ +ARM GAS /tmp/ccvIfV49.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_uart_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_RS485Ex_Init,"ax",%progbits + 16 .align 1 + 17 .global HAL_RS485Ex_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HAL_RS485Ex_Init: + 24 .LFB39: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @file stm32l0xx_hal_uart_ex.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Extended UART HAL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * This file provides firmware functions to manage the following extended + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + Initialization and de-initialization functions + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + Peripheral Control functions + 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @verbatim + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ============================================================================== + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ##### UART peripheral extended features ##### + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ============================================================================== + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (#) Declare a UART_HandleTypeDef handle structure. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (#) For the UART RS485 Driver Enable mode, initialize the UART registers + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** by calling the HAL_RS485Ex_Init() API. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @endverbatim + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ****************************************************************************** + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @attention + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * Redistribution and use in source and binary forms, with or without modification, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * are permitted provided that the following conditions are met: + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 1. Redistributions of source code must retain the above copyright notice, + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * this list of conditions and the following disclaimer. + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + ARM GAS /tmp/ccvIfV49.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * this list of conditions and the following disclaimer in the documentation + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * and/or other materials provided with the distribution. + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * may be used to endorse or promote products derived from this software + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * without specific prior written permission. + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ****************************************************************************** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** #include "stm32l0xx_hal.h" + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @addtogroup STM32L0xx_HAL_Driver + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief UART Extended HAL module driver + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @} + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Extended Initialization and Configuration Functions + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @verbatim + ARM GAS /tmp/ccvIfV49.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** =============================================================================== + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ##### Initialization and Configuration functions ##### + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** =============================================================================== + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** [..] + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** in asynchronous mode. + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) For the asynchronous mode the parameters below can be configured: + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Baud Rate + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Word Length + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Stop Bit + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** in the data register is transmitted but is changed by the parity bit. + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Hardware flow control + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Receiver/transmitter modes + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) Over Sampling Method + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) One-Bit Sampling Method + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) TX and/or RX pin level inversion + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) data logical level inversion + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) RX and TX pins swap + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) RX overrun detection disabling + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) DMA disabling on RX error + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) MSB first on communication line + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (++) auto Baud rate detection + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** [..] + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** procedures (details for the procedures are available in reference manual). + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @endverbatim + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** 8-bit or 9-bit), the possible UART formats are listed in the + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** following table. + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** Table 1. UART frame format. + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | M1 bit | M0 bit | PCE bit | UART frame | + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Initialize the RS485 Driver enable feature according to the specified + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + ARM GAS /tmp/ccvIfV49.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param Polarity: select the driver enable polarity. + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param AssertionTime: Driver Enable assertion time: + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 5-bit value defining the time between the activation of the DE (Driver + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * signal and the beginning of the start bit. It is expressed in sample ti + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * units (1/8 or 1/16 bit time, depending on the oversampling rate) + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param DeassertionTime: Driver Enable deassertion time: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 5-bit value defining the time between the end of the last stop bit, in + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * transmitted message, and the de-activation of the DE (Driver Enable) si + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * It is expressed in sample time units (1/8 or 1/16 bit time, depending o + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * oversampling rate). + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 26 .loc 1 165 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 24 + 34 .cfi_offset 3, -24 + 35 .cfi_offset 4, -20 + 36 .cfi_offset 5, -16 + 37 .cfi_offset 6, -12 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 + 40 0002 0400 movs r4, r0 + 41 0004 0F00 movs r7, r1 + 42 0006 1600 movs r6, r2 + 43 0008 1D00 movs r5, r3 + 44 .LVL1: + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** uint32_t temp = 0x0U; + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(huart == NULL) + 45 .loc 1 169 0 + 46 000a 0028 cmp r0, #0 + 47 000c 3BD0 beq .L5 + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_ERROR; + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the Driver Enable polarity */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_DE_POLARITY(Polarity)); + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the Driver Enable assertion time */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the Driver Enable deassertion time */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + ARM GAS /tmp/ccvIfV49.s page 5 + + + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(huart->gState == HAL_UART_STATE_RESET) + 48 .loc 1 183 0 + 49 000e 6923 movs r3, #105 + 50 .LVL2: + 51 0010 C35C ldrb r3, [r0, r3] + 52 0012 002B cmp r3, #0 + 53 0014 2DD0 beq .L6 + 54 .LVL3: + 55 .L3: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Allocate lock resource and initialize it */ + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->Lock = HAL_UNLOCKED; + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_UART_MspInit(huart); + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 56 .loc 1 192 0 + 57 0016 6923 movs r3, #105 + 58 0018 2422 movs r2, #36 + 59 001a E254 strb r2, [r4, r3] + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 60 .loc 1 195 0 + 61 001c 2268 ldr r2, [r4] + 62 001e 1368 ldr r3, [r2] + 63 0020 0121 movs r1, #1 + 64 0022 8B43 bics r3, r1 + 65 0024 1360 str r3, [r2] + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the UART Communication parameters */ + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 66 .loc 1 198 0 + 67 0026 636A ldr r3, [r4, #36] + 68 0028 002B cmp r3, #0 + 69 002a 28D1 bne .L7 + 70 .L4: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** UART_AdvFeatureConfig(huart); + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 71 .loc 1 203 0 + 72 002c 2000 movs r0, r4 + 73 002e FFF7FEFF bl UART_SetConfig + 74 .LVL4: + 75 0032 0128 cmp r0, #1 + 76 0034 1CD0 beq .L2 + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_ERROR; + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + 77 .loc 1 209 0 + ARM GAS /tmp/ccvIfV49.s page 6 + + + 78 0036 2268 ldr r2, [r4] + 79 0038 9168 ldr r1, [r2, #8] + 80 003a 8023 movs r3, #128 + 81 003c DB01 lsls r3, r3, #7 + 82 003e 0B43 orrs r3, r1 + 83 0040 9360 str r3, [r2, #8] + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the Driver Enable polarity */ + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + 84 .loc 1 212 0 + 85 0042 2268 ldr r2, [r4] + 86 0044 9368 ldr r3, [r2, #8] + 87 0046 1149 ldr r1, .L8 + 88 0048 0B40 ands r3, r1 + 89 004a 1F43 orrs r7, r3 + 90 .LVL5: + 91 004c 9760 str r7, [r2, #8] + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the Driver Enable assertion and deassertion times */ + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + 92 .loc 1 215 0 + 93 004e 7605 lsls r6, r6, #21 + 94 .LVL6: + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + 95 .loc 1 216 0 + 96 0050 2D04 lsls r5, r5, #16 + 97 .LVL7: + 98 0052 2E43 orrs r6, r5 + 99 .LVL8: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); + 100 .loc 1 217 0 + 101 0054 2368 ldr r3, [r4] + 102 0056 1D68 ldr r5, [r3] + 103 0058 0D4A ldr r2, .L8+4 + 104 005a 1540 ands r5, r2 + 105 005c 2E43 orrs r6, r5 + 106 .LVL9: + 107 005e 1E60 str r6, [r3] + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 108 .loc 1 220 0 + 109 0060 2268 ldr r2, [r4] + 110 0062 1368 ldr r3, [r2] + 111 0064 0121 movs r1, #1 + 112 0066 0B43 orrs r3, r1 + 113 0068 1360 str r3, [r2] + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 114 .loc 1 223 0 + 115 006a 2000 movs r0, r4 + 116 006c FFF7FEFF bl UART_CheckIdleState + 117 .LVL10: + 118 .L2: + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 119 .loc 1 224 0 + ARM GAS /tmp/ccvIfV49.s page 7 + + + 120 @ sp needed + 121 .LVL11: + 122 0070 F8BD pop {r3, r4, r5, r6, r7, pc} + 123 .LVL12: + 124 .L6: + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 125 .loc 1 186 0 + 126 0072 6833 adds r3, r3, #104 + 127 0074 0022 movs r2, #0 + 128 .LVL13: + 129 0076 C254 strb r2, [r0, r3] + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 130 .loc 1 189 0 + 131 0078 FFF7FEFF bl HAL_UART_MspInit + 132 .LVL14: + 133 007c CBE7 b .L3 + 134 .L7: + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 135 .loc 1 200 0 + 136 007e 2000 movs r0, r4 + 137 0080 FFF7FEFF bl UART_AdvFeatureConfig + 138 .LVL15: + 139 0084 D2E7 b .L4 + 140 .LVL16: + 141 .L5: + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 142 .loc 1 171 0 + 143 0086 0120 movs r0, #1 + 144 .LVL17: + 145 0088 F2E7 b .L2 + 146 .L9: + 147 008a C046 .align 2 + 148 .L8: + 149 008c FF7FFFFF .word -32769 + 150 0090 FFFF00FC .word -67043329 + 151 .cfi_endproc + 152 .LFE39: + 154 .section .text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits + 155 .align 1 + 156 .global HAL_MultiProcessorEx_AddressLength_Set + 157 .syntax unified + 158 .code 16 + 159 .thumb_func + 160 .fpu softvfp + 162 HAL_MultiProcessorEx_AddressLength_Set: + 163 .LFB40: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @} + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Extended Peripheral Control functions + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @verbatim + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** =============================================================================== + ARM GAS /tmp/ccvIfV49.s page 8 + + + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** ##### Peripheral Control functions ##### + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** =============================================================================== + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** [..] This section provides the following functions: + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** detection length to more than 4 bits for multiprocessor address mark wake up. + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** trigger: address match, Start Bit detection or RXNE bit status. + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableClockStopMode() API enables the UART HSI clock during stop mode + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** @endverbatim + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief By default in multiprocessor mode, when the wake up method is set + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * to address mark, the UART handles only 4-bit long addresses detection; + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * this API allows to enable longer addresses detection (6-, 7- or 8-bit + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * long). + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param AddressLength: this parameter can be one of the following values: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 164 .loc 1 273 0 + 165 .cfi_startproc + 166 @ args = 0, pretend = 0, frame = 0 + 167 @ frame_needed = 0, uses_anonymous_args = 0 + 168 .LVL18: + 169 0000 70B5 push {r4, r5, r6, lr} + 170 .LCFI1: + 171 .cfi_def_cfa_offset 16 + 172 .cfi_offset 4, -16 + 173 .cfi_offset 5, -12 + 174 .cfi_offset 6, -8 + 175 .cfi_offset 14, -4 + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(huart == NULL) + 176 .loc 1 275 0 + 177 0002 0028 cmp r0, #0 + 178 0004 14D0 beq .L12 + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_ERROR; + ARM GAS /tmp/ccvIfV49.s page 9 + + + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Check the address length parameter */ + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 179 .loc 1 283 0 + 180 0006 6923 movs r3, #105 + 181 0008 2422 movs r2, #36 + 182 000a C254 strb r2, [r0, r3] + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 183 .loc 1 286 0 + 184 000c 0368 ldr r3, [r0] + 185 000e 1A68 ldr r2, [r3] + 186 0010 0124 movs r4, #1 + 187 0012 A243 bics r2, r4 + 188 0014 1A60 str r2, [r3] + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the address length */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + 189 .loc 1 289 0 + 190 0016 0268 ldr r2, [r0] + 191 0018 5368 ldr r3, [r2, #4] + 192 001a 1025 movs r5, #16 + 193 001c AB43 bics r3, r5 + 194 001e 1943 orrs r1, r3 + 195 .LVL19: + 196 0020 5160 str r1, [r2, #4] + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 197 .loc 1 292 0 + 198 0022 0268 ldr r2, [r0] + 199 0024 1368 ldr r3, [r2] + 200 0026 2343 orrs r3, r4 + 201 0028 1360 str r3, [r2] + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and/or huart->RxState to Ready */ + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 202 .loc 1 295 0 + 203 002a FFF7FEFF bl UART_CheckIdleState + 204 .LVL20: + 205 .L11: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 206 .loc 1 296 0 + 207 @ sp needed + 208 002e 70BD pop {r4, r5, r6, pc} + 209 .LVL21: + 210 .L12: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 211 .loc 1 277 0 + 212 0030 0120 movs r0, #1 + 213 .LVL22: + 214 0032 FCE7 b .L11 + 215 .cfi_endproc + ARM GAS /tmp/ccvIfV49.s page 10 + + + 216 .LFE40: + 218 .section .text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits + 219 .align 1 + 220 .global HAL_UARTEx_StopModeWakeUpSourceConfig + 221 .syntax unified + 222 .code 16 + 223 .thumb_func + 224 .fpu softvfp + 226 HAL_UARTEx_StopModeWakeUpSourceConfig: + 227 .LFB41: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Set Wakeup from Stop mode interrupt flag selection. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_ADDRESS + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_STARTBIT + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 228 .loc 1 310 0 + 229 .cfi_startproc + 230 @ args = 0, pretend = 0, frame = 16 + 231 @ frame_needed = 0, uses_anonymous_args = 0 + 232 .LVL23: + 233 0000 30B5 push {r4, r5, lr} + 234 .LCFI2: + 235 .cfi_def_cfa_offset 12 + 236 .cfi_offset 4, -12 + 237 .cfi_offset 5, -8 + 238 .cfi_offset 14, -4 + 239 0002 87B0 sub sp, sp, #28 + 240 .LCFI3: + 241 .cfi_def_cfa_offset 40 + 242 0004 0400 movs r4, r0 + 243 0006 0291 str r1, [sp, #8] + 244 0008 0392 str r2, [sp, #12] + 245 .LVL24: + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** uint32_t tickstart = 0; + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* check the wake-up from stop mode UART instance */ + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 246 .loc 1 320 0 + 247 000a 6823 movs r3, #104 + 248 000c C35C ldrb r3, [r0, r3] + 249 000e 012B cmp r3, #1 + 250 0010 42D0 beq .L17 + ARM GAS /tmp/ccvIfV49.s page 11 + + + 251 .loc 1 320 0 is_stmt 0 discriminator 2 + 252 0012 0121 movs r1, #1 + 253 0014 6823 movs r3, #104 + 254 0016 C154 strb r1, [r0, r3] + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 255 .loc 1 322 0 is_stmt 1 discriminator 2 + 256 0018 0133 adds r3, r3, #1 + 257 001a 2422 movs r2, #36 + 258 001c C254 strb r2, [r0, r3] + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 259 .loc 1 325 0 discriminator 2 + 260 001e 0268 ldr r2, [r0] + 261 0020 1368 ldr r3, [r2] + 262 0022 8B43 bics r3, r1 + 263 0024 1360 str r3, [r2] + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the wake-up selection scheme */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 264 .loc 1 328 0 discriminator 2 + 265 0026 0168 ldr r1, [r0] + 266 0028 8B68 ldr r3, [r1, #8] + 267 002a 1C4A ldr r2, .L19 + 268 002c 1340 ands r3, r2 + 269 002e 029A ldr r2, [sp, #8] + 270 0030 1343 orrs r3, r2 + 271 0032 8B60 str r3, [r1, #8] + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 272 .loc 1 330 0 discriminator 2 + 273 0034 002A cmp r2, #0 + 274 0036 13D1 bne .L15 + 275 .LVL25: + 276 0038 04AA add r2, sp, #16 + 277 003a 02AB add r3, sp, #8 + 278 003c 1100 movs r1, r2 + 279 003e 21CB ldmia r3!, {r0, r5} + 280 0040 21C1 stmia r1!, {r0, r5} + 281 .LVL26: + 282 .LBB4: + 283 .LBB5: + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Init tickstart for timeout managment*/ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Wait until REACK flag is set */ + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** status = HAL_TIMEOUT; + ARM GAS /tmp/ccvIfV49.s page 12 + + + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** else + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Initialize the UART State */ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Unlocked */ + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return status; + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Enable UART Stop Mode. + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set UESM bit */ + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Unlocked */ + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_OK; + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Disable UART Stop Mode. + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Clear UESM bit */ + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Unlocked */ + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + ARM GAS /tmp/ccvIfV49.s page 13 + + + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_OK; + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Enable UART Clock in Stop Mode + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * The UART keeps the Clock ON during Stop mode + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: uart handle + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set UCESM bit */ + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Unlocked */ + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_OK; + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Disable UART Clock in Stop Mode + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: uart handle + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval HAL status + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Clear UCESM bit */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Unlocked */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** return HAL_OK; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief UART wakeup from Stop mode callback. + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval None + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) + ARM GAS /tmp/ccvIfV49.s page 14 + + + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** UNUSED(huart); + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** the HAL_UARTEx_WakeupCallback can be implemented in the user file. + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @} + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @} + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @{ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /** + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param huart: UART handle. + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @param WakeUpSelection: UART wake up from stop mode parameters. + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** * @retval None + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** */ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** if(WakeUpSelection.AddressLength == UART_ADDRESS_DETECT_4B) + 284 .loc 1 489 0 + 285 0042 9088 ldrh r0, [r2, #4] + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_4B_ADDRESS(WakeUpSelection.Address)); + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** else + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** assert_param(IS_UART_7B_ADDRESS(WakeUpSelection.Address)); + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the USART address length */ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 286 .loc 1 499 0 + 287 0044 2168 ldr r1, [r4] + 288 0046 4B68 ldr r3, [r1, #4] + 289 0048 1025 movs r5, #16 + 290 004a AB43 bics r3, r5 + 291 004c 0343 orrs r3, r0 + 292 004e 4B60 str r3, [r1, #4] + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Set the USART address node */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD + 293 .loc 1 502 0 + 294 0050 2168 ldr r1, [r4] + 295 0052 4B68 ldr r3, [r1, #4] + 296 0054 1B02 lsls r3, r3, #8 + ARM GAS /tmp/ccvIfV49.s page 15 + + + 297 0056 1B0A lsrs r3, r3, #8 + 298 0058 9279 ldrb r2, [r2, #6] + 299 005a 1206 lsls r2, r2, #24 + 300 005c 1343 orrs r3, r2 + 301 005e 4B60 str r3, [r1, #4] + 302 .LVL27: + 303 .L15: + 304 .LBE5: + 305 .LBE4: + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 306 .loc 1 336 0 + 307 0060 2268 ldr r2, [r4] + 308 0062 1368 ldr r3, [r2] + 309 0064 0121 movs r1, #1 + 310 0066 0B43 orrs r3, r1 + 311 0068 1360 str r3, [r2] + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 312 .loc 1 339 0 + 313 006a FFF7FEFF bl HAL_GetTick + 314 .LVL28: + 315 006e 0300 movs r3, r0 + 316 .LVL29: + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** { + 317 .loc 1 342 0 + 318 0070 8021 movs r1, #128 + 319 0072 0B4A ldr r2, .L19+4 + 320 0074 0092 str r2, [sp] + 321 0076 0022 movs r2, #0 + 322 0078 C903 lsls r1, r1, #15 + 323 007a 2000 movs r0, r4 + 324 .LVL30: + 325 007c FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 326 .LVL31: + 327 0080 0028 cmp r0, #0 + 328 0082 03D1 bne .L18 + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 329 .loc 1 349 0 + 330 0084 6923 movs r3, #105 + 331 0086 2022 movs r2, #32 + 332 0088 E254 strb r2, [r4, r3] + 333 008a 00E0 b .L16 + 334 .L18: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 335 .loc 1 344 0 + 336 008c 0320 movs r0, #3 + 337 .L16: + 338 .LVL32: + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 339 .loc 1 353 0 + 340 008e 6823 movs r3, #104 + 341 0090 0022 movs r2, #0 + 342 0092 E254 strb r2, [r4, r3] + 343 .LVL33: + 344 .L14: + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 345 .loc 1 356 0 + 346 0094 07B0 add sp, sp, #28 + ARM GAS /tmp/ccvIfV49.s page 16 + + + 347 @ sp needed + 348 .LVL34: + 349 0096 30BD pop {r4, r5, pc} + 350 .LVL35: + 351 .L17: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 352 .loc 1 320 0 + 353 0098 0220 movs r0, #2 + 354 .LVL36: + 355 009a FBE7 b .L14 + 356 .L20: + 357 .align 2 + 358 .L19: + 359 009c FFFFCFFF .word -3145729 + 360 00a0 FFFFFF01 .word 33554431 + 361 .cfi_endproc + 362 .LFE41: + 364 .section .text.HAL_UARTEx_EnableStopMode,"ax",%progbits + 365 .align 1 + 366 .global HAL_UARTEx_EnableStopMode + 367 .syntax unified + 368 .code 16 + 369 .thumb_func + 370 .fpu softvfp + 372 HAL_UARTEx_EnableStopMode: + 373 .LFB42: + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 374 .loc 1 366 0 + 375 .cfi_startproc + 376 @ args = 0, pretend = 0, frame = 0 + 377 @ frame_needed = 0, uses_anonymous_args = 0 + 378 .LVL37: + 379 0000 30B5 push {r4, r5, lr} + 380 .LCFI4: + 381 .cfi_def_cfa_offset 12 + 382 .cfi_offset 4, -12 + 383 .cfi_offset 5, -8 + 384 .cfi_offset 14, -4 + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 385 .loc 1 368 0 + 386 0002 6823 movs r3, #104 + 387 0004 C35C ldrb r3, [r0, r3] + 388 0006 012B cmp r3, #1 + 389 0008 10D0 beq .L23 + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 390 .loc 1 368 0 is_stmt 0 discriminator 2 + 391 000a 6822 movs r2, #104 + 392 000c 0123 movs r3, #1 + 393 000e 8354 strb r3, [r0, r2] + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 394 .loc 1 370 0 is_stmt 1 discriminator 2 + 395 0010 6921 movs r1, #105 + 396 0012 2333 adds r3, r3, #35 + 397 0014 4354 strb r3, [r0, r1] + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 398 .loc 1 373 0 discriminator 2 + 399 0016 0468 ldr r4, [r0] + ARM GAS /tmp/ccvIfV49.s page 17 + + + 400 0018 2368 ldr r3, [r4] + 401 001a 0225 movs r5, #2 + 402 001c 2B43 orrs r3, r5 + 403 001e 2360 str r3, [r4] + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 404 .loc 1 375 0 discriminator 2 + 405 0020 2023 movs r3, #32 + 406 0022 4354 strb r3, [r0, r1] + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 407 .loc 1 378 0 discriminator 2 + 408 0024 0023 movs r3, #0 + 409 0026 8354 strb r3, [r0, r2] + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 410 .loc 1 380 0 discriminator 2 + 411 0028 0020 movs r0, #0 + 412 .LVL38: + 413 .L22: + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 414 .loc 1 381 0 + 415 @ sp needed + 416 002a 30BD pop {r4, r5, pc} + 417 .LVL39: + 418 .L23: + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 419 .loc 1 368 0 + 420 002c 0220 movs r0, #2 + 421 .LVL40: + 422 002e FCE7 b .L22 + 423 .cfi_endproc + 424 .LFE42: + 426 .section .text.HAL_UARTEx_DisableStopMode,"ax",%progbits + 427 .align 1 + 428 .global HAL_UARTEx_DisableStopMode + 429 .syntax unified + 430 .code 16 + 431 .thumb_func + 432 .fpu softvfp + 434 HAL_UARTEx_DisableStopMode: + 435 .LFB43: + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 436 .loc 1 389 0 + 437 .cfi_startproc + 438 @ args = 0, pretend = 0, frame = 0 + 439 @ frame_needed = 0, uses_anonymous_args = 0 + 440 .LVL41: + 441 0000 30B5 push {r4, r5, lr} + 442 .LCFI5: + 443 .cfi_def_cfa_offset 12 + 444 .cfi_offset 4, -12 + 445 .cfi_offset 5, -8 + 446 .cfi_offset 14, -4 + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 447 .loc 1 391 0 + 448 0002 6823 movs r3, #104 + 449 0004 C35C ldrb r3, [r0, r3] + 450 0006 012B cmp r3, #1 + 451 0008 10D0 beq .L26 + ARM GAS /tmp/ccvIfV49.s page 18 + + + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 452 .loc 1 391 0 is_stmt 0 discriminator 2 + 453 000a 6822 movs r2, #104 + 454 000c 0123 movs r3, #1 + 455 000e 8354 strb r3, [r0, r2] + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 456 .loc 1 393 0 is_stmt 1 discriminator 2 + 457 0010 6921 movs r1, #105 + 458 0012 2333 adds r3, r3, #35 + 459 0014 4354 strb r3, [r0, r1] + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 460 .loc 1 396 0 discriminator 2 + 461 0016 0468 ldr r4, [r0] + 462 0018 2368 ldr r3, [r4] + 463 001a 0225 movs r5, #2 + 464 001c AB43 bics r3, r5 + 465 001e 2360 str r3, [r4] + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 466 .loc 1 398 0 discriminator 2 + 467 0020 2023 movs r3, #32 + 468 0022 4354 strb r3, [r0, r1] + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 469 .loc 1 401 0 discriminator 2 + 470 0024 0023 movs r3, #0 + 471 0026 8354 strb r3, [r0, r2] + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 472 .loc 1 403 0 discriminator 2 + 473 0028 0020 movs r0, #0 + 474 .LVL42: + 475 .L25: + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 476 .loc 1 404 0 + 477 @ sp needed + 478 002a 30BD pop {r4, r5, pc} + 479 .LVL43: + 480 .L26: + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 481 .loc 1 391 0 + 482 002c 0220 movs r0, #2 + 483 .LVL44: + 484 002e FCE7 b .L25 + 485 .cfi_endproc + 486 .LFE43: + 488 .section .text.HAL_UARTEx_EnableClockStopMode,"ax",%progbits + 489 .align 1 + 490 .global HAL_UARTEx_EnableClockStopMode + 491 .syntax unified + 492 .code 16 + 493 .thumb_func + 494 .fpu softvfp + 496 HAL_UARTEx_EnableClockStopMode: + 497 .LFB44: + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 498 .loc 1 413 0 + 499 .cfi_startproc + 500 @ args = 0, pretend = 0, frame = 0 + 501 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccvIfV49.s page 19 + + + 502 .LVL45: + 503 0000 30B5 push {r4, r5, lr} + 504 .LCFI6: + 505 .cfi_def_cfa_offset 12 + 506 .cfi_offset 4, -12 + 507 .cfi_offset 5, -8 + 508 .cfi_offset 14, -4 + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 509 .loc 1 415 0 + 510 0002 6823 movs r3, #104 + 511 0004 C35C ldrb r3, [r0, r3] + 512 0006 012B cmp r3, #1 + 513 0008 11D0 beq .L29 + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 514 .loc 1 415 0 is_stmt 0 discriminator 2 + 515 000a 6822 movs r2, #104 + 516 000c 0123 movs r3, #1 + 517 000e 8354 strb r3, [r0, r2] + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 518 .loc 1 417 0 is_stmt 1 discriminator 2 + 519 0010 6921 movs r1, #105 + 520 0012 2333 adds r3, r3, #35 + 521 0014 4354 strb r3, [r0, r1] + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 522 .loc 1 420 0 discriminator 2 + 523 0016 0468 ldr r4, [r0] + 524 0018 A568 ldr r5, [r4, #8] + 525 001a 8023 movs r3, #128 + 526 001c 1B04 lsls r3, r3, #16 + 527 001e 2B43 orrs r3, r5 + 528 0020 A360 str r3, [r4, #8] + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 529 .loc 1 422 0 discriminator 2 + 530 0022 2023 movs r3, #32 + 531 0024 4354 strb r3, [r0, r1] + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 532 .loc 1 425 0 discriminator 2 + 533 0026 0023 movs r3, #0 + 534 0028 8354 strb r3, [r0, r2] + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 535 .loc 1 427 0 discriminator 2 + 536 002a 0020 movs r0, #0 + 537 .LVL46: + 538 .L28: + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 539 .loc 1 428 0 + 540 @ sp needed + 541 002c 30BD pop {r4, r5, pc} + 542 .LVL47: + 543 .L29: + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 544 .loc 1 415 0 + 545 002e 0220 movs r0, #2 + 546 .LVL48: + 547 0030 FCE7 b .L28 + 548 .cfi_endproc + 549 .LFE44: + ARM GAS /tmp/ccvIfV49.s page 20 + + + 551 .section .text.HAL_UARTEx_DisableClockStopMode,"ax",%progbits + 552 .align 1 + 553 .global HAL_UARTEx_DisableClockStopMode + 554 .syntax unified + 555 .code 16 + 556 .thumb_func + 557 .fpu softvfp + 559 HAL_UARTEx_DisableClockStopMode: + 560 .LFB45: + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Process Locked */ + 561 .loc 1 436 0 + 562 .cfi_startproc + 563 @ args = 0, pretend = 0, frame = 0 + 564 @ frame_needed = 0, uses_anonymous_args = 0 + 565 .LVL49: + 566 0000 30B5 push {r4, r5, lr} + 567 .LCFI7: + 568 .cfi_def_cfa_offset 12 + 569 .cfi_offset 4, -12 + 570 .cfi_offset 5, -8 + 571 .cfi_offset 14, -4 + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 572 .loc 1 438 0 + 573 0002 6823 movs r3, #104 + 574 0004 C35C ldrb r3, [r0, r3] + 575 0006 012B cmp r3, #1 + 576 0008 10D0 beq .L32 + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 577 .loc 1 438 0 is_stmt 0 discriminator 2 + 578 000a 6822 movs r2, #104 + 579 000c 0123 movs r3, #1 + 580 000e 8354 strb r3, [r0, r2] + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 581 .loc 1 440 0 is_stmt 1 discriminator 2 + 582 0010 6921 movs r1, #105 + 583 0012 2333 adds r3, r3, #35 + 584 0014 4354 strb r3, [r0, r1] + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 585 .loc 1 443 0 discriminator 2 + 586 0016 0468 ldr r4, [r0] + 587 0018 A368 ldr r3, [r4, #8] + 588 001a 054D ldr r5, .L33 + 589 001c 2B40 ands r3, r5 + 590 001e A360 str r3, [r4, #8] + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 591 .loc 1 445 0 discriminator 2 + 592 0020 2023 movs r3, #32 + 593 0022 4354 strb r3, [r0, r1] + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 594 .loc 1 448 0 discriminator 2 + 595 0024 0023 movs r3, #0 + 596 0026 8354 strb r3, [r0, r2] + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** } + 597 .loc 1 450 0 discriminator 2 + 598 0028 0020 movs r0, #0 + 599 .LVL50: + 600 .L31: + ARM GAS /tmp/ccvIfV49.s page 21 + + + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 601 .loc 1 451 0 + 602 @ sp needed + 603 002a 30BD pop {r4, r5, pc} + 604 .LVL51: + 605 .L32: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 606 .loc 1 438 0 + 607 002c 0220 movs r0, #2 + 608 .LVL52: + 609 002e FCE7 b .L31 + 610 .L34: + 611 .align 2 + 612 .L33: + 613 0030 FFFF7FFF .word -8388609 + 614 .cfi_endproc + 615 .LFE45: + 617 .section .text.HAL_UARTEx_WakeupCallback,"ax",%progbits + 618 .align 1 + 619 .weak HAL_UARTEx_WakeupCallback + 620 .syntax unified + 621 .code 16 + 622 .thumb_func + 623 .fpu softvfp + 625 HAL_UARTEx_WakeupCallback: + 626 .LFB46: + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 627 .loc 1 459 0 + 628 .cfi_startproc + 629 @ args = 0, pretend = 0, frame = 0 + 630 @ frame_needed = 0, uses_anonymous_args = 0 + 631 @ link register save eliminated. + 632 .LVL53: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c **** + 633 .loc 1 466 0 + 634 @ sp needed + 635 0000 7047 bx lr + 636 .cfi_endproc + 637 .LFE46: + 639 .text + 640 .Letext0: + 641 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 642 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 643 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 644 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 645 .file 6 "/usr/arm-none-eabi/include/sys/lock.h" + 646 .file 7 "/usr/arm-none-eabi/include/sys/_types.h" + 647 .file 8 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 648 .file 9 "/usr/arm-none-eabi/include/sys/reent.h" + 649 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 650 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 651 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 652 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h" + 653 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h" + 654 .file 15 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccvIfV49.s page 22 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_uart_ex.c + /tmp/ccvIfV49.s:16 .text.HAL_RS485Ex_Init:0000000000000000 $t + /tmp/ccvIfV49.s:23 .text.HAL_RS485Ex_Init:0000000000000000 HAL_RS485Ex_Init + /tmp/ccvIfV49.s:149 .text.HAL_RS485Ex_Init:000000000000008c $d + /tmp/ccvIfV49.s:155 .text.HAL_MultiProcessorEx_AddressLength_Set:0000000000000000 $t + /tmp/ccvIfV49.s:162 .text.HAL_MultiProcessorEx_AddressLength_Set:0000000000000000 HAL_MultiProcessorEx_AddressLength_Set + /tmp/ccvIfV49.s:219 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:0000000000000000 $t + /tmp/ccvIfV49.s:226 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:0000000000000000 HAL_UARTEx_StopModeWakeUpSourceConfig + /tmp/ccvIfV49.s:359 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:000000000000009c $d + /tmp/ccvIfV49.s:365 .text.HAL_UARTEx_EnableStopMode:0000000000000000 $t + /tmp/ccvIfV49.s:372 .text.HAL_UARTEx_EnableStopMode:0000000000000000 HAL_UARTEx_EnableStopMode + /tmp/ccvIfV49.s:427 .text.HAL_UARTEx_DisableStopMode:0000000000000000 $t + /tmp/ccvIfV49.s:434 .text.HAL_UARTEx_DisableStopMode:0000000000000000 HAL_UARTEx_DisableStopMode + /tmp/ccvIfV49.s:489 .text.HAL_UARTEx_EnableClockStopMode:0000000000000000 $t + /tmp/ccvIfV49.s:496 .text.HAL_UARTEx_EnableClockStopMode:0000000000000000 HAL_UARTEx_EnableClockStopMode + /tmp/ccvIfV49.s:552 .text.HAL_UARTEx_DisableClockStopMode:0000000000000000 $t + /tmp/ccvIfV49.s:559 .text.HAL_UARTEx_DisableClockStopMode:0000000000000000 HAL_UARTEx_DisableClockStopMode + /tmp/ccvIfV49.s:613 .text.HAL_UARTEx_DisableClockStopMode:0000000000000030 $d + /tmp/ccvIfV49.s:618 .text.HAL_UARTEx_WakeupCallback:0000000000000000 $t + /tmp/ccvIfV49.s:625 .text.HAL_UARTEx_WakeupCallback:0000000000000000 HAL_UARTEx_WakeupCallback + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +UART_SetConfig +UART_CheckIdleState +HAL_UART_MspInit +UART_AdvFeatureConfig +HAL_GetTick +UART_WaitOnFlagUntilTimeout diff --git a/build/stm32l0xx_hal_usart.d b/build/stm32l0xx_hal_usart.d new file mode 100644 index 0000000..e04a092 --- /dev/null +++ b/build/stm32l0xx_hal_usart.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_usart.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_usart.lst b/build/stm32l0xx_hal_usart.lst new file mode 100644 index 0000000..70e7388 --- /dev/null +++ b/build/stm32l0xx_hal_usart.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cc2zokRx.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_usart.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc2zokRx.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_usart.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hal_wwdg.d b/build/stm32l0xx_hal_wwdg.d new file mode 100644 index 0000000..e43bd09 --- /dev/null +++ b/build/stm32l0xx_hal_wwdg.d @@ -0,0 +1,103 @@ +build/stm32l0xx_hal_wwdg.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_hal_wwdg.lst b/build/stm32l0xx_hal_wwdg.lst new file mode 100644 index 0000000..4390364 --- /dev/null +++ b/build/stm32l0xx_hal_wwdg.lst @@ -0,0 +1,32 @@ +ARM GAS /tmp/cc6Q3X1T.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hal_wwdg.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + 16 .file 1 "/usr/arm-none-eabi/include/machine/_default_types.h" + 17 .file 2 "/usr/arm-none-eabi/include/sys/_stdint.h" + 18 .file 3 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 19 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 20 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 21 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 22 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc6Q3X1T.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hal_wwdg.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_hw.d b/build/stm32l0xx_hw.d new file mode 100644 index 0000000..81f24ec --- /dev/null +++ b/build/stm32l0xx_hw.d @@ -0,0 +1,142 @@ +build/stm32l0xx_hw.d: Src/stm32l0xx_hw.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Phy/radio.h Inc/debug.h Inc/vcom.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Phy/radio.h: + +Inc/debug.h: + +Inc/vcom.h: diff --git a/build/stm32l0xx_hw.lst b/build/stm32l0xx_hw.lst new file mode 100644 index 0000000..2b132f1 --- /dev/null +++ b/build/stm32l0xx_hw.lst @@ -0,0 +1,1305 @@ +ARM GAS /tmp/ccKytYSe.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_hw.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HW_Init,"ax",%progbits + 16 .align 1 + 17 .global HW_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 HW_Init: + 24 .LFB96: + 25 .file 1 "./Src/stm32l0xx_hw.c" + 1:./Src/stm32l0xx_hw.c **** /* + 2:./Src/stm32l0xx_hw.c **** / _____) _ | | + 3:./Src/stm32l0xx_hw.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/stm32l0xx_hw.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/stm32l0xx_hw.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/stm32l0xx_hw.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/stm32l0xx_hw.c **** (C)2013 Semtech + 8:./Src/stm32l0xx_hw.c **** + 9:./Src/stm32l0xx_hw.c **** Description: Target board general functions implementation + 10:./Src/stm32l0xx_hw.c **** + 11:./Src/stm32l0xx_hw.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/stm32l0xx_hw.c **** + 13:./Src/stm32l0xx_hw.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Src/stm32l0xx_hw.c **** */ + 15:./Src/stm32l0xx_hw.c **** /******************************************************************************* + 16:./Src/stm32l0xx_hw.c **** * @file stm32l0xx_hw.c + 17:./Src/stm32l0xx_hw.c **** * @author MCD Application Team + 18:./Src/stm32l0xx_hw.c **** * @version V1.1.2 + 19:./Src/stm32l0xx_hw.c **** * @date 08-September-2017 + 20:./Src/stm32l0xx_hw.c **** * @brief system hardware driver + 21:./Src/stm32l0xx_hw.c **** ****************************************************************************** + 22:./Src/stm32l0xx_hw.c **** * @attention + 23:./Src/stm32l0xx_hw.c **** * + 24:./Src/stm32l0xx_hw.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/stm32l0xx_hw.c **** * All rights reserved.

+ 26:./Src/stm32l0xx_hw.c **** * + 27:./Src/stm32l0xx_hw.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/stm32l0xx_hw.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/stm32l0xx_hw.c **** * + 30:./Src/stm32l0xx_hw.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/stm32l0xx_hw.c **** * this list of conditions and the following disclaimer. + 32:./Src/stm32l0xx_hw.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/stm32l0xx_hw.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/ccKytYSe.s page 2 + + + 34:./Src/stm32l0xx_hw.c **** * and/or other materials provided with the distribution. + 35:./Src/stm32l0xx_hw.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/stm32l0xx_hw.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/stm32l0xx_hw.c **** * derived from this software without specific written permission. + 38:./Src/stm32l0xx_hw.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/stm32l0xx_hw.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/stm32l0xx_hw.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/stm32l0xx_hw.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/stm32l0xx_hw.c **** * this license is void and will automatically terminate your rights under + 43:./Src/stm32l0xx_hw.c **** * this license. + 44:./Src/stm32l0xx_hw.c **** * + 45:./Src/stm32l0xx_hw.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/stm32l0xx_hw.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/stm32l0xx_hw.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/stm32l0xx_hw.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/stm32l0xx_hw.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/stm32l0xx_hw.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/stm32l0xx_hw.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/stm32l0xx_hw.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/stm32l0xx_hw.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/stm32l0xx_hw.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/stm32l0xx_hw.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/stm32l0xx_hw.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/stm32l0xx_hw.c **** * + 58:./Src/stm32l0xx_hw.c **** ****************************************************************************** + 59:./Src/stm32l0xx_hw.c **** */ + 60:./Src/stm32l0xx_hw.c **** #include "hw.h" + 61:./Src/stm32l0xx_hw.c **** #include "radio.h" + 62:./Src/stm32l0xx_hw.c **** #include "debug.h" + 63:./Src/stm32l0xx_hw.c **** #include "vcom.h" + 64:./Src/stm32l0xx_hw.c **** + 65:./Src/stm32l0xx_hw.c **** /*! + 66:./Src/stm32l0xx_hw.c **** * \brief Unique Devices IDs register set ( STM32L0xxx ) + 67:./Src/stm32l0xx_hw.c **** */ + 68:./Src/stm32l0xx_hw.c **** #define ID1 ( 0x1FF80050 ) + 69:./Src/stm32l0xx_hw.c **** #define ID2 ( 0x1FF80054 ) + 70:./Src/stm32l0xx_hw.c **** #define ID3 ( 0x1FF80064 ) + 71:./Src/stm32l0xx_hw.c **** + 72:./Src/stm32l0xx_hw.c **** /*! + 73:./Src/stm32l0xx_hw.c **** * \brief ADC Vbat measurement constants + 74:./Src/stm32l0xx_hw.c **** */ + 75:./Src/stm32l0xx_hw.c **** + 76:./Src/stm32l0xx_hw.c **** /* Internal voltage reference, parameter VREFINT_CAL*/ + 77:./Src/stm32l0xx_hw.c **** #define VREFINT_CAL ((uint16_t*) ((uint32_t) 0x1FF80078)) + 78:./Src/stm32l0xx_hw.c **** #define LORAWAN_MAX_BAT 254 + 79:./Src/stm32l0xx_hw.c **** + 80:./Src/stm32l0xx_hw.c **** + 81:./Src/stm32l0xx_hw.c **** /* Internal temperature sensor: constants data used for indicative values in */ + 82:./Src/stm32l0xx_hw.c **** /* this example. Refer to device datasheet for min/typ/max values. */ + 83:./Src/stm32l0xx_hw.c **** + 84:./Src/stm32l0xx_hw.c **** /* Internal temperature sensor, parameter TS_CAL1: TS ADC raw data acquired at + 85:./Src/stm32l0xx_hw.c **** *a temperature of 110 DegC (+-5 DegC), VDDA = 3.3 V (+-10 mV). */ + 86:./Src/stm32l0xx_hw.c **** #define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FF8007A)) + 87:./Src/stm32l0xx_hw.c **** + 88:./Src/stm32l0xx_hw.c **** /* Internal temperature sensor, parameter TS_CAL2: TS ADC raw data acquired at + 89:./Src/stm32l0xx_hw.c **** *a temperature of 30 DegC (+-5 DegC), VDDA = 3.3 V (+-10 mV). */ + 90:./Src/stm32l0xx_hw.c **** #define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FF8007E)) + ARM GAS /tmp/ccKytYSe.s page 3 + + + 91:./Src/stm32l0xx_hw.c **** + 92:./Src/stm32l0xx_hw.c **** /* Vdda value with which temperature sensor has been calibrated in production + 93:./Src/stm32l0xx_hw.c **** (+-10 mV). */ + 94:./Src/stm32l0xx_hw.c **** #define VDDA_TEMP_CAL ((uint32_t) 3000) + 95:./Src/stm32l0xx_hw.c **** + 96:./Src/stm32l0xx_hw.c **** /*! + 97:./Src/stm32l0xx_hw.c **** * Flag to indicate if the MCU is Initialized + 98:./Src/stm32l0xx_hw.c **** */ + 99:./Src/stm32l0xx_hw.c **** static bool McuInitialized = false; + 100:./Src/stm32l0xx_hw.c **** + 101:./Src/stm32l0xx_hw.c **** /** + 102:./Src/stm32l0xx_hw.c **** * @brief This function initializes the hardware + 103:./Src/stm32l0xx_hw.c **** * @param None + 104:./Src/stm32l0xx_hw.c **** * @retval None + 105:./Src/stm32l0xx_hw.c **** */ + 106:./Src/stm32l0xx_hw.c **** void HW_Init( void ) + 107:./Src/stm32l0xx_hw.c **** { + 26 .loc 1 107 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 10B5 push {r4, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 4, -8 + 34 .cfi_offset 14, -4 + 108:./Src/stm32l0xx_hw.c **** if( McuInitialized == false ) + 35 .loc 1 108 0 + 36 0002 084B ldr r3, .L3 + 37 0004 1B78 ldrb r3, [r3] + 38 0006 002B cmp r3, #0 + 39 0008 0BD1 bne .L1 + 109:./Src/stm32l0xx_hw.c **** { + 110:./Src/stm32l0xx_hw.c **** #if defined( USE_BOOTLOADER ) + 111:./Src/stm32l0xx_hw.c **** /* Set the Vector Table base location at 0x3000 */ + 112:./Src/stm32l0xx_hw.c **** NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x3000 ); + 113:./Src/stm32l0xx_hw.c **** #endif + 114:./Src/stm32l0xx_hw.c **** + 115:./Src/stm32l0xx_hw.c **** // HW_AdcInit( ); + 116:./Src/stm32l0xx_hw.c **** + 117:./Src/stm32l0xx_hw.c **** Radio.IoInit( ); + 40 .loc 1 117 0 + 41 000a 074B ldr r3, .L3+4 + 42 000c 1B68 ldr r3, [r3] + 43 000e 9847 blx r3 + 44 .LVL0: + 118:./Src/stm32l0xx_hw.c **** + 119:./Src/stm32l0xx_hw.c **** HW_SPI_Init( ); + 45 .loc 1 119 0 + 46 0010 FFF7FEFF bl HW_SPI_Init + 47 .LVL1: + 120:./Src/stm32l0xx_hw.c **** + 121:./Src/stm32l0xx_hw.c **** HW_RTC_Init( ); + 48 .loc 1 121 0 + 49 0014 FFF7FEFF bl HW_RTC_Init + 50 .LVL2: + 122:./Src/stm32l0xx_hw.c **** + ARM GAS /tmp/ccKytYSe.s page 4 + + + 123:./Src/stm32l0xx_hw.c **** vcom_Init( ); + 51 .loc 1 123 0 + 52 0018 FFF7FEFF bl vcom_Init + 53 .LVL3: + 124:./Src/stm32l0xx_hw.c **** + 125:./Src/stm32l0xx_hw.c **** McuInitialized = true; + 54 .loc 1 125 0 + 55 001c 014B ldr r3, .L3 + 56 001e 0122 movs r2, #1 + 57 0020 1A70 strb r2, [r3] + 58 .L1: + 126:./Src/stm32l0xx_hw.c **** } + 127:./Src/stm32l0xx_hw.c **** } + 59 .loc 1 127 0 + 60 @ sp needed + 61 0022 10BD pop {r4, pc} + 62 .L4: + 63 .align 2 + 64 .L3: + 65 0024 00000000 .word .LANCHOR0 + 66 0028 00000000 .word Radio + 67 .cfi_endproc + 68 .LFE96: + 70 .section .text.HW_DeInit,"ax",%progbits + 71 .align 1 + 72 .global HW_DeInit + 73 .syntax unified + 74 .code 16 + 75 .thumb_func + 76 .fpu softvfp + 78 HW_DeInit: + 79 .LFB97: + 128:./Src/stm32l0xx_hw.c **** + 129:./Src/stm32l0xx_hw.c **** /** + 130:./Src/stm32l0xx_hw.c **** * @brief This function Deinitializes the hardware + 131:./Src/stm32l0xx_hw.c **** * @param None + 132:./Src/stm32l0xx_hw.c **** * @retval None + 133:./Src/stm32l0xx_hw.c **** */ + 134:./Src/stm32l0xx_hw.c **** void HW_DeInit( void ) + 135:./Src/stm32l0xx_hw.c **** { + 80 .loc 1 135 0 + 81 .cfi_startproc + 82 @ args = 0, pretend = 0, frame = 0 + 83 @ frame_needed = 0, uses_anonymous_args = 0 + 84 0000 10B5 push {r4, lr} + 85 .LCFI1: + 86 .cfi_def_cfa_offset 8 + 87 .cfi_offset 4, -8 + 88 .cfi_offset 14, -4 + 136:./Src/stm32l0xx_hw.c **** HW_SPI_DeInit( ); + 89 .loc 1 136 0 + 90 0002 FFF7FEFF bl HW_SPI_DeInit + 91 .LVL4: + 137:./Src/stm32l0xx_hw.c **** + 138:./Src/stm32l0xx_hw.c **** Radio.IoDeInit( ); + 92 .loc 1 138 0 + 93 0006 044B ldr r3, .L6 + ARM GAS /tmp/ccKytYSe.s page 5 + + + 94 0008 5B68 ldr r3, [r3, #4] + 95 000a 9847 blx r3 + 96 .LVL5: + 139:./Src/stm32l0xx_hw.c **** + 140:./Src/stm32l0xx_hw.c **** vcom_DeInit( ); + 97 .loc 1 140 0 + 98 000c FFF7FEFF bl vcom_DeInit + 99 .LVL6: + 141:./Src/stm32l0xx_hw.c **** + 142:./Src/stm32l0xx_hw.c **** McuInitialized = false; + 100 .loc 1 142 0 + 101 0010 024B ldr r3, .L6+4 + 102 0012 0022 movs r2, #0 + 103 0014 1A70 strb r2, [r3] + 143:./Src/stm32l0xx_hw.c **** } + 104 .loc 1 143 0 + 105 @ sp needed + 106 0016 10BD pop {r4, pc} + 107 .L7: + 108 .align 2 + 109 .L6: + 110 0018 00000000 .word Radio + 111 001c 00000000 .word .LANCHOR0 + 112 .cfi_endproc + 113 .LFE97: + 115 .section .text.HW_GpioInit,"ax",%progbits + 116 .align 1 + 117 .global HW_GpioInit + 118 .syntax unified + 119 .code 16 + 120 .thumb_func + 121 .fpu softvfp + 123 HW_GpioInit: + 124 .LFB100: + 144:./Src/stm32l0xx_hw.c **** + 145:./Src/stm32l0xx_hw.c **** /** + 146:./Src/stm32l0xx_hw.c **** * @brief This function Initializes the hardware Ios + 147:./Src/stm32l0xx_hw.c **** * @param None + 148:./Src/stm32l0xx_hw.c **** * @retval None + 149:./Src/stm32l0xx_hw.c **** */ + 150:./Src/stm32l0xx_hw.c **** static void HW_IoInit( void ) + 151:./Src/stm32l0xx_hw.c **** { + 152:./Src/stm32l0xx_hw.c **** HW_SPI_IoInit( ); + 153:./Src/stm32l0xx_hw.c **** + 154:./Src/stm32l0xx_hw.c **** Radio.IoInit( ); + 155:./Src/stm32l0xx_hw.c **** + 156:./Src/stm32l0xx_hw.c **** vcom_IoInit( ); + 157:./Src/stm32l0xx_hw.c **** } + 158:./Src/stm32l0xx_hw.c **** + 159:./Src/stm32l0xx_hw.c **** /** + 160:./Src/stm32l0xx_hw.c **** * @brief This function Deinitializes the hardware Ios + 161:./Src/stm32l0xx_hw.c **** * @param None + 162:./Src/stm32l0xx_hw.c **** * @retval None + 163:./Src/stm32l0xx_hw.c **** */ + 164:./Src/stm32l0xx_hw.c **** static void HW_IoDeInit( void ) + 165:./Src/stm32l0xx_hw.c **** { + 166:./Src/stm32l0xx_hw.c **** HW_SPI_IoDeInit( ); + ARM GAS /tmp/ccKytYSe.s page 6 + + + 167:./Src/stm32l0xx_hw.c **** + 168:./Src/stm32l0xx_hw.c **** Radio.IoDeInit( ); + 169:./Src/stm32l0xx_hw.c **** + 170:./Src/stm32l0xx_hw.c **** vcom_IoDeInit( ); + 171:./Src/stm32l0xx_hw.c **** } + 172:./Src/stm32l0xx_hw.c **** + 173:./Src/stm32l0xx_hw.c **** + 174:./Src/stm32l0xx_hw.c **** void HW_GpioInit(void) + 175:./Src/stm32l0xx_hw.c **** { + 125 .loc 1 175 0 + 126 .cfi_startproc + 127 @ args = 0, pretend = 0, frame = 0 + 128 @ frame_needed = 0, uses_anonymous_args = 0 + 129 @ link register save eliminated. + 176:./Src/stm32l0xx_hw.c **** /* STM32L0 Gpios are all already configured in analog input at nReset*/ + 177:./Src/stm32l0xx_hw.c **** } + 130 .loc 1 177 0 + 131 @ sp needed + 132 0000 7047 bx lr + 133 .cfi_endproc + 134 .LFE100: + 136 .section .text.SystemClock_Config,"ax",%progbits + 137 .align 1 + 138 .global SystemClock_Config + 139 .syntax unified + 140 .code 16 + 141 .thumb_func + 142 .fpu softvfp + 144 SystemClock_Config: + 145 .LFB101: + 178:./Src/stm32l0xx_hw.c **** + 179:./Src/stm32l0xx_hw.c **** /** + 180:./Src/stm32l0xx_hw.c **** * @brief System Clock Configuration + 181:./Src/stm32l0xx_hw.c **** * The system Clock is configured as follow : + 182:./Src/stm32l0xx_hw.c **** * System Clock source = PLL (HSI) + 183:./Src/stm32l0xx_hw.c **** * SYSCLK(Hz) = 32000000 + 184:./Src/stm32l0xx_hw.c **** * HCLK(Hz) = 32000000 + 185:./Src/stm32l0xx_hw.c **** * AHB Prescaler = 1 + 186:./Src/stm32l0xx_hw.c **** * APB1 Prescaler = 1 + 187:./Src/stm32l0xx_hw.c **** * APB2 Prescaler = 1 + 188:./Src/stm32l0xx_hw.c **** * HSI Frequency(Hz) = 16000000 + 189:./Src/stm32l0xx_hw.c **** * PLLMUL = 6 + 190:./Src/stm32l0xx_hw.c **** * PLLDIV = 3 + 191:./Src/stm32l0xx_hw.c **** * Flash Latency(WS) = 1 + 192:./Src/stm32l0xx_hw.c **** * @retval None + 193:./Src/stm32l0xx_hw.c **** */ + 194:./Src/stm32l0xx_hw.c **** + 195:./Src/stm32l0xx_hw.c **** void SystemClock_Config( void ) + 196:./Src/stm32l0xx_hw.c **** { + 146 .loc 1 196 0 + 147 .cfi_startproc + 148 @ args = 0, pretend = 0, frame = 80 + 149 @ frame_needed = 0, uses_anonymous_args = 0 + 150 0000 00B5 push {lr} + 151 .LCFI2: + 152 .cfi_def_cfa_offset 4 + 153 .cfi_offset 14, -4 + ARM GAS /tmp/ccKytYSe.s page 7 + + + 154 0002 95B0 sub sp, sp, #84 + 155 .LCFI3: + 156 .cfi_def_cfa_offset 88 + 197:./Src/stm32l0xx_hw.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 157 .loc 1 197 0 + 158 0004 1422 movs r2, #20 + 159 0006 0021 movs r1, #0 + 160 0008 0FA8 add r0, sp, #60 + 161 000a FFF7FEFF bl memset + 162 .LVL7: + 198:./Src/stm32l0xx_hw.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 163 .loc 1 198 0 + 164 000e 2C22 movs r2, #44 + 165 0010 0021 movs r1, #0 + 166 0012 02A8 add r0, sp, #8 + 167 0014 FFF7FEFF bl memset + 168 .LVL8: + 199:./Src/stm32l0xx_hw.c **** + 200:./Src/stm32l0xx_hw.c **** /* Enable HSE Oscillator and Activate PLL with HSE as source */ + 201:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 169 .loc 1 201 0 + 170 0018 0223 movs r3, #2 + 171 001a 0193 str r3, [sp, #4] + 202:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + 203:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 172 .loc 1 203 0 + 173 001c 0122 movs r2, #1 + 174 001e 0492 str r2, [sp, #16] + 204:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 175 .loc 1 204 0 + 176 0020 0F32 adds r2, r2, #15 + 177 0022 0592 str r2, [sp, #20] + 205:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 178 .loc 1 205 0 + 179 0024 0B93 str r3, [sp, #44] + 206:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + 207:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_6; + 180 .loc 1 207 0 + 181 0026 8023 movs r3, #128 + 182 0028 1B03 lsls r3, r3, #12 + 183 002a 0D93 str r3, [sp, #52] + 208:./Src/stm32l0xx_hw.c **** RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3; + 184 .loc 1 208 0 + 185 002c 8023 movs r3, #128 + 186 002e 1B04 lsls r3, r3, #16 + 187 0030 0E93 str r3, [sp, #56] + 209:./Src/stm32l0xx_hw.c **** + 210:./Src/stm32l0xx_hw.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 188 .loc 1 210 0 + 189 0032 01A8 add r0, sp, #4 + 190 0034 FFF7FEFF bl HAL_RCC_OscConfig + 191 .LVL9: + 192 0038 0028 cmp r0, #0 + 193 003a 21D1 bne .L13 + 194 .L10: + 211:./Src/stm32l0xx_hw.c **** { + 212:./Src/stm32l0xx_hw.c **** Error_Handler(); + ARM GAS /tmp/ccKytYSe.s page 8 + + + 213:./Src/stm32l0xx_hw.c **** } + 214:./Src/stm32l0xx_hw.c **** + 215:./Src/stm32l0xx_hw.c **** /* Set Voltage scale1 as MCU will run at 32MHz */ + 216:./Src/stm32l0xx_hw.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 195 .loc 1 216 0 + 196 003c 154A ldr r2, .L15 + 197 003e 916B ldr r1, [r2, #56] + 198 0040 8023 movs r3, #128 + 199 0042 5B05 lsls r3, r3, #21 + 200 0044 0B43 orrs r3, r1 + 201 0046 9363 str r3, [r2, #56] + 217:./Src/stm32l0xx_hw.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 202 .loc 1 217 0 + 203 0048 1349 ldr r1, .L15+4 + 204 004a 0B68 ldr r3, [r1] + 205 004c 134A ldr r2, .L15+8 + 206 004e 1A40 ands r2, r3 + 207 0050 8023 movs r3, #128 + 208 0052 1B01 lsls r3, r3, #4 + 209 0054 1343 orrs r3, r2 + 210 0056 0B60 str r3, [r1] + 211 .L11: + 218:./Src/stm32l0xx_hw.c **** + 219:./Src/stm32l0xx_hw.c **** /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ + 220:./Src/stm32l0xx_hw.c **** while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; + 212 .loc 1 220 0 discriminator 1 + 213 0058 0F4B ldr r3, .L15+4 + 214 005a 5B68 ldr r3, [r3, #4] + 215 005c DB06 lsls r3, r3, #27 + 216 005e FBD4 bmi .L11 + 221:./Src/stm32l0xx_hw.c **** + 222:./Src/stm32l0xx_hw.c **** /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + 223:./Src/stm32l0xx_hw.c **** clocks dividers */ + 224:./Src/stm32l0xx_hw.c **** RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + 217 .loc 1 224 0 + 218 0060 0F23 movs r3, #15 + 219 0062 0F93 str r3, [sp, #60] + 225:./Src/stm32l0xx_hw.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 220 .loc 1 225 0 + 221 0064 0C3B subs r3, r3, #12 + 222 0066 1093 str r3, [sp, #64] + 226:./Src/stm32l0xx_hw.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 223 .loc 1 226 0 + 224 0068 0023 movs r3, #0 + 225 006a 1193 str r3, [sp, #68] + 227:./Src/stm32l0xx_hw.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 226 .loc 1 227 0 + 227 006c 1293 str r3, [sp, #72] + 228:./Src/stm32l0xx_hw.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 228 .loc 1 228 0 + 229 006e 1393 str r3, [sp, #76] + 229:./Src/stm32l0xx_hw.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + 230 .loc 1 229 0 + 231 0070 0121 movs r1, #1 + 232 0072 0FA8 add r0, sp, #60 + 233 0074 FFF7FEFF bl HAL_RCC_ClockConfig + 234 .LVL10: + ARM GAS /tmp/ccKytYSe.s page 9 + + + 235 0078 0028 cmp r0, #0 + 236 007a 06D1 bne .L14 + 237 .L9: + 230:./Src/stm32l0xx_hw.c **** { + 231:./Src/stm32l0xx_hw.c **** Error_Handler(); + 232:./Src/stm32l0xx_hw.c **** } + 233:./Src/stm32l0xx_hw.c **** } + 238 .loc 1 233 0 + 239 007c 15B0 add sp, sp, #84 + 240 @ sp needed + 241 007e 00BD pop {pc} + 242 .L13: + 212:./Src/stm32l0xx_hw.c **** } + 243 .loc 1 212 0 + 244 0080 D421 movs r1, #212 + 245 0082 0748 ldr r0, .L15+12 + 246 0084 FFF7FEFF bl _Error_Handler + 247 .LVL11: + 248 0088 D8E7 b .L10 + 249 .L14: + 231:./Src/stm32l0xx_hw.c **** } + 250 .loc 1 231 0 + 251 008a E721 movs r1, #231 + 252 008c 0448 ldr r0, .L15+12 + 253 008e FFF7FEFF bl _Error_Handler + 254 .LVL12: + 255 .loc 1 233 0 + 256 0092 F3E7 b .L9 + 257 .L16: + 258 .align 2 + 259 .L15: + 260 0094 00100240 .word 1073876992 + 261 0098 00700040 .word 1073770496 + 262 009c FFE7FFFF .word -6145 + 263 00a0 00000000 .word .LC4 + 264 .cfi_endproc + 265 .LFE101: + 267 .section .text.HW_GetRandomSeed,"ax",%progbits + 268 .align 1 + 269 .global HW_GetRandomSeed + 270 .syntax unified + 271 .code 16 + 272 .thumb_func + 273 .fpu softvfp + 275 HW_GetRandomSeed: + 276 .LFB102: + 234:./Src/stm32l0xx_hw.c **** /** + 235:./Src/stm32l0xx_hw.c **** * @brief This function return a random seed + 236:./Src/stm32l0xx_hw.c **** * @note based on the device unique ID + 237:./Src/stm32l0xx_hw.c **** * @param None + 238:./Src/stm32l0xx_hw.c **** * @retval see + 239:./Src/stm32l0xx_hw.c **** */ + 240:./Src/stm32l0xx_hw.c **** uint32_t HW_GetRandomSeed( void ) + 241:./Src/stm32l0xx_hw.c **** { + 277 .loc 1 241 0 + 278 .cfi_startproc + 279 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccKytYSe.s page 10 + + + 280 @ frame_needed = 0, uses_anonymous_args = 0 + 281 @ link register save eliminated. + 242:./Src/stm32l0xx_hw.c **** return ( ( *( uint32_t* )ID1 ) ^ ( *( uint32_t* )ID2 ) ^ ( *( uint32_t* )ID3 ) ); + 282 .loc 1 242 0 + 283 0000 044B ldr r3, .L18 + 284 0002 1868 ldr r0, [r3] + 285 0004 044B ldr r3, .L18+4 + 286 0006 1B68 ldr r3, [r3] + 287 0008 5840 eors r0, r3 + 288 000a 044B ldr r3, .L18+8 + 289 000c 1B68 ldr r3, [r3] + 290 000e 5840 eors r0, r3 + 243:./Src/stm32l0xx_hw.c **** } + 291 .loc 1 243 0 + 292 @ sp needed + 293 0010 7047 bx lr + 294 .L19: + 295 0012 C046 .align 2 + 296 .L18: + 297 0014 5000F81F .word 536346704 + 298 0018 5400F81F .word 536346708 + 299 001c 6400F81F .word 536346724 + 300 .cfi_endproc + 301 .LFE102: + 303 .section .text.HW_GetUniqueId,"ax",%progbits + 304 .align 1 + 305 .global HW_GetUniqueId + 306 .syntax unified + 307 .code 16 + 308 .thumb_func + 309 .fpu softvfp + 311 HW_GetUniqueId: + 312 .LFB103: + 244:./Src/stm32l0xx_hw.c **** + 245:./Src/stm32l0xx_hw.c **** /** + 246:./Src/stm32l0xx_hw.c **** * @brief This function return a unique ID + 247:./Src/stm32l0xx_hw.c **** * @param unique ID + 248:./Src/stm32l0xx_hw.c **** * @retval none + 249:./Src/stm32l0xx_hw.c **** */ + 250:./Src/stm32l0xx_hw.c **** void HW_GetUniqueId( uint8_t *id ) + 251:./Src/stm32l0xx_hw.c **** { + 313 .loc 1 251 0 + 314 .cfi_startproc + 315 @ args = 0, pretend = 0, frame = 0 + 316 @ frame_needed = 0, uses_anonymous_args = 0 + 317 .LVL13: + 318 0000 10B5 push {r4, lr} + 319 .LCFI4: + 320 .cfi_def_cfa_offset 8 + 321 .cfi_offset 4, -8 + 322 .cfi_offset 14, -4 + 252:./Src/stm32l0xx_hw.c **** id[7] = ( ( *( uint32_t* )ID1 )+ ( *( uint32_t* )ID3 ) ) >> 24; + 323 .loc 1 252 0 + 324 0002 1349 ldr r1, .L21 + 325 0004 134A ldr r2, .L21+4 + 326 0006 0B68 ldr r3, [r1] + 327 0008 1C00 movs r4, r3 + ARM GAS /tmp/ccKytYSe.s page 11 + + + 328 000a 1368 ldr r3, [r2] + 329 000c 9C46 mov ip, r3 + 330 000e 6444 add r4, r4, ip + 331 0010 230E lsrs r3, r4, #24 + 332 0012 C371 strb r3, [r0, #7] + 253:./Src/stm32l0xx_hw.c **** id[6] = ( ( *( uint32_t* )ID1 )+ ( *( uint32_t* )ID3 ) ) >> 16; + 333 .loc 1 253 0 + 334 0014 0B68 ldr r3, [r1] + 335 0016 1C00 movs r4, r3 + 336 0018 1368 ldr r3, [r2] + 337 001a 9C46 mov ip, r3 + 338 001c 6444 add r4, r4, ip + 339 001e 230C lsrs r3, r4, #16 + 340 0020 8371 strb r3, [r0, #6] + 254:./Src/stm32l0xx_hw.c **** id[5] = ( ( *( uint32_t* )ID1 )+ ( *( uint32_t* )ID3 ) ) >> 8; + 341 .loc 1 254 0 + 342 0022 0B68 ldr r3, [r1] + 343 0024 1C00 movs r4, r3 + 344 0026 1368 ldr r3, [r2] + 345 0028 9C46 mov ip, r3 + 346 002a 6444 add r4, r4, ip + 347 002c 230A lsrs r3, r4, #8 + 348 002e 4371 strb r3, [r0, #5] + 255:./Src/stm32l0xx_hw.c **** id[4] = ( ( *( uint32_t* )ID1 )+ ( *( uint32_t* )ID3 ) ); + 349 .loc 1 255 0 + 350 0030 0B68 ldr r3, [r1] + 351 0032 1268 ldr r2, [r2] + 352 0034 9B18 adds r3, r3, r2 + 353 0036 0371 strb r3, [r0, #4] + 256:./Src/stm32l0xx_hw.c **** id[3] = ( ( *( uint32_t* )ID2 ) ) >> 24; + 354 .loc 1 256 0 + 355 0038 074B ldr r3, .L21+8 + 356 003a DA78 ldrb r2, [r3, #3] + 357 003c C270 strb r2, [r0, #3] + 257:./Src/stm32l0xx_hw.c **** id[2] = ( ( *( uint32_t* )ID2 ) ) >> 16; + 358 .loc 1 257 0 + 359 003e 5A88 ldrh r2, [r3, #2] + 360 0040 8270 strb r2, [r0, #2] + 258:./Src/stm32l0xx_hw.c **** id[1] = ( ( *( uint32_t* )ID2 ) ) >> 8; + 361 .loc 1 258 0 + 362 0042 1A68 ldr r2, [r3] + 363 0044 120A lsrs r2, r2, #8 + 364 0046 4270 strb r2, [r0, #1] + 259:./Src/stm32l0xx_hw.c **** id[0] = ( ( *( uint32_t* )ID2 ) ); + 365 .loc 1 259 0 + 366 0048 1B68 ldr r3, [r3] + 367 004a 0370 strb r3, [r0] + 260:./Src/stm32l0xx_hw.c **** } + 368 .loc 1 260 0 + 369 @ sp needed + 370 004c 10BD pop {r4, pc} + 371 .L22: + 372 004e C046 .align 2 + 373 .L21: + 374 0050 5000F81F .word 536346704 + 375 0054 6400F81F .word 536346724 + 376 0058 5400F81F .word 536346708 + ARM GAS /tmp/ccKytYSe.s page 12 + + + 377 .cfi_endproc + 378 .LFE103: + 380 .section .text.HW_EnterStopMode,"ax",%progbits + 381 .align 1 + 382 .global HW_EnterStopMode + 383 .syntax unified + 384 .code 16 + 385 .thumb_func + 386 .fpu softvfp + 388 HW_EnterStopMode: + 389 .LFB104: + 261:./Src/stm32l0xx_hw.c **** + 262:./Src/stm32l0xx_hw.c **** + 263:./Src/stm32l0xx_hw.c **** /** + 264:./Src/stm32l0xx_hw.c **** * @brief Enters Low Power Stop Mode + 265:./Src/stm32l0xx_hw.c **** * @note ARM exists the function when waking up + 266:./Src/stm32l0xx_hw.c **** * @param none + 267:./Src/stm32l0xx_hw.c **** * @retval none + 268:./Src/stm32l0xx_hw.c **** */ + 269:./Src/stm32l0xx_hw.c **** void HW_EnterStopMode( void) + 270:./Src/stm32l0xx_hw.c **** { + 390 .loc 1 270 0 + 391 .cfi_startproc + 392 @ args = 0, pretend = 0, frame = 0 + 393 @ frame_needed = 0, uses_anonymous_args = 0 + 394 0000 10B5 push {r4, lr} + 395 .LCFI5: + 396 .cfi_def_cfa_offset 8 + 397 .cfi_offset 4, -8 + 398 .cfi_offset 14, -4 + 399 .LBB22: + 400 .LBB23: + 401 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + ARM GAS /tmp/ccKytYSe.s page 13 + + + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccKytYSe.s page 14 + + + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + ARM GAS /tmp/ccKytYSe.s page 15 + + + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + ARM GAS /tmp/ccKytYSe.s page 16 + + + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 402 .loc 2 203 0 + 403 .syntax divided + 404 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 405 0002 EFF31084 MRS r4, primask + 406 @ 0 "" 2 + 407 .thumb + 408 .syntax unified + 409 .LBE23: + 410 .LBE22: + 411 .LBB24: + 412 .LBB25: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 413 .loc 2 71 0 + 414 .syntax divided + 415 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 416 0006 72B6 cpsid i + 417 @ 0 "" 2 + 418 .thumb + 419 .syntax unified + 420 .LBE25: + 421 .LBE24: + 422 .LBB26: + 423 .LBB27: + 166:./Src/stm32l0xx_hw.c **** + 424 .loc 1 166 0 + 425 0008 FFF7FEFF bl HW_SPI_IoDeInit + 426 .LVL14: + 168:./Src/stm32l0xx_hw.c **** + 427 .loc 1 168 0 + 428 000c 084B ldr r3, .L24 + 429 000e 5B68 ldr r3, [r3, #4] + 430 0010 9847 blx r3 + 431 .LVL15: + 170:./Src/stm32l0xx_hw.c **** } + 432 .loc 1 170 0 + 433 0012 FFF7FEFF bl vcom_IoDeInit + 434 .LVL16: + 435 .LBE27: + 436 .LBE26: + 271:./Src/stm32l0xx_hw.c **** BACKUP_PRIMASK(); + 272:./Src/stm32l0xx_hw.c **** + 273:./Src/stm32l0xx_hw.c **** DISABLE_IRQ( ); + 274:./Src/stm32l0xx_hw.c **** + 275:./Src/stm32l0xx_hw.c **** HW_IoDeInit( ); + 276:./Src/stm32l0xx_hw.c **** + 277:./Src/stm32l0xx_hw.c **** /*clear wake up flag*/ + 278:./Src/stm32l0xx_hw.c **** SET_BIT(PWR->CR, PWR_CR_CWUF); + 437 .loc 1 278 0 + 438 0016 074A ldr r2, .L24+4 + ARM GAS /tmp/ccKytYSe.s page 17 + + + 439 0018 1368 ldr r3, [r2] + 440 001a 0421 movs r1, #4 + 441 001c 0B43 orrs r3, r1 + 442 001e 1360 str r3, [r2] + 443 .LBB28: + 444 .LBB29: + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 445 .loc 2 215 0 + 446 .syntax divided + 447 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 448 0020 84F31088 MSR primask, r4 + 449 @ 0 "" 2 + 450 .thumb + 451 .syntax unified + 452 .LBE29: + 453 .LBE28: + 279:./Src/stm32l0xx_hw.c **** + 280:./Src/stm32l0xx_hw.c **** RESTORE_PRIMASK( ); + 281:./Src/stm32l0xx_hw.c **** + 282:./Src/stm32l0xx_hw.c **** /* Enter Stop Mode */ + 283:./Src/stm32l0xx_hw.c **** HAL_PWR_EnterSTOPMode ( PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI ); + 454 .loc 1 283 0 + 455 0024 0339 subs r1, r1, #3 + 456 0026 0120 movs r0, #1 + 457 0028 FFF7FEFF bl HAL_PWR_EnterSTOPMode + 458 .LVL17: + 284:./Src/stm32l0xx_hw.c **** } + 459 .loc 1 284 0 + 460 @ sp needed + 461 002c 10BD pop {r4, pc} + 462 .L25: + 463 002e C046 .align 2 + 464 .L24: + 465 0030 00000000 .word Radio + 466 0034 00700040 .word 1073770496 + 467 .cfi_endproc + 468 .LFE104: + 470 .section .text.HW_ExitStopMode,"ax",%progbits + 471 .align 1 + 472 .global HW_ExitStopMode + 473 .syntax unified + 474 .code 16 + 475 .thumb_func + 476 .fpu softvfp + 478 HW_ExitStopMode: + 479 .LFB105: + ARM GAS /tmp/ccKytYSe.s page 18 + + + 285:./Src/stm32l0xx_hw.c **** /** + 286:./Src/stm32l0xx_hw.c **** * @brief Exists Low Power Stop Mode + 287:./Src/stm32l0xx_hw.c **** * @note Enable the pll at 32MHz + 288:./Src/stm32l0xx_hw.c **** * @param none + 289:./Src/stm32l0xx_hw.c **** * @retval none + 290:./Src/stm32l0xx_hw.c **** */ + 291:./Src/stm32l0xx_hw.c **** void HW_ExitStopMode( void) + 292:./Src/stm32l0xx_hw.c **** { + 480 .loc 1 292 0 + 481 .cfi_startproc + 482 @ args = 0, pretend = 0, frame = 0 + 483 @ frame_needed = 0, uses_anonymous_args = 0 + 484 0000 10B5 push {r4, lr} + 485 .LCFI6: + 486 .cfi_def_cfa_offset 8 + 487 .cfi_offset 4, -8 + 488 .cfi_offset 14, -4 + 489 .LBB38: + 490 .LBB39: + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 491 .loc 2 203 0 + 492 .syntax divided + 493 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 494 0002 EFF31084 MRS r4, primask + 495 @ 0 "" 2 + 496 .thumb + 497 .syntax unified + 498 .LBE39: + 499 .LBE38: + 500 .LBB40: + 501 .LBB41: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 502 .loc 2 71 0 + 503 .syntax divided + 504 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 505 0006 72B6 cpsid i + 506 @ 0 "" 2 + 507 .thumb + 508 .syntax unified + 509 .LBE41: + 510 .LBE40: + 293:./Src/stm32l0xx_hw.c **** /* Disable IRQ while the MCU is not running on HSI */ + 294:./Src/stm32l0xx_hw.c **** + 295:./Src/stm32l0xx_hw.c **** BACKUP_PRIMASK(); + 296:./Src/stm32l0xx_hw.c **** + 297:./Src/stm32l0xx_hw.c **** DISABLE_IRQ( ); + 298:./Src/stm32l0xx_hw.c **** + 299:./Src/stm32l0xx_hw.c **** /* After wake-up from STOP reconfigure the system clock */ + 300:./Src/stm32l0xx_hw.c **** /* Enable HSI */ + 301:./Src/stm32l0xx_hw.c **** __HAL_RCC_HSI_ENABLE(); + 511 .loc 1 301 0 + 512 0008 134A ldr r2, .L30 + 513 000a 1368 ldr r3, [r2] + 514 000c 0121 movs r1, #1 + 515 000e 0B43 orrs r3, r1 + 516 0010 1360 str r3, [r2] + 517 .L27: + ARM GAS /tmp/ccKytYSe.s page 19 + + + 302:./Src/stm32l0xx_hw.c **** + 303:./Src/stm32l0xx_hw.c **** /* Wait till HSI is ready */ + 304:./Src/stm32l0xx_hw.c **** while( __HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET ) {} + 518 .loc 1 304 0 discriminator 1 + 519 0012 114B ldr r3, .L30 + 520 0014 1B68 ldr r3, [r3] + 521 0016 5B07 lsls r3, r3, #29 + 522 0018 FBD5 bpl .L27 + 305:./Src/stm32l0xx_hw.c **** + 306:./Src/stm32l0xx_hw.c **** /* Enable PLL */ + 307:./Src/stm32l0xx_hw.c **** __HAL_RCC_PLL_ENABLE(); + 523 .loc 1 307 0 + 524 001a 0F4A ldr r2, .L30 + 525 001c 1168 ldr r1, [r2] + 526 001e 8023 movs r3, #128 + 527 0020 5B04 lsls r3, r3, #17 + 528 0022 0B43 orrs r3, r1 + 529 0024 1360 str r3, [r2] + 530 .L28: + 308:./Src/stm32l0xx_hw.c **** /* Wait till PLL is ready */ + 309:./Src/stm32l0xx_hw.c **** while( __HAL_RCC_GET_FLAG( RCC_FLAG_PLLRDY ) == RESET ) {} + 531 .loc 1 309 0 discriminator 1 + 532 0026 0C4B ldr r3, .L30 + 533 0028 1B68 ldr r3, [r3] + 534 002a 9B01 lsls r3, r3, #6 + 535 002c FBD5 bpl .L28 + 310:./Src/stm32l0xx_hw.c **** + 311:./Src/stm32l0xx_hw.c **** /* Select PLL as system clock source */ + 312:./Src/stm32l0xx_hw.c **** __HAL_RCC_SYSCLK_CONFIG ( RCC_SYSCLKSOURCE_PLLCLK ); + 536 .loc 1 312 0 + 537 002e 0A4A ldr r2, .L30 + 538 0030 D368 ldr r3, [r2, #12] + 539 0032 0321 movs r1, #3 + 540 0034 0B43 orrs r3, r1 + 541 0036 D360 str r3, [r2, #12] + 542 .L29: + 313:./Src/stm32l0xx_hw.c **** + 314:./Src/stm32l0xx_hw.c **** /* Wait till PLL is used as system clock source */ + 315:./Src/stm32l0xx_hw.c **** while( __HAL_RCC_GET_SYSCLK_SOURCE( ) != RCC_SYSCLKSOURCE_STATUS_PLLCLK ) {} + 543 .loc 1 315 0 discriminator 1 + 544 0038 074B ldr r3, .L30 + 545 003a DA68 ldr r2, [r3, #12] + 546 003c 0C23 movs r3, #12 + 547 003e 1340 ands r3, r2 + 548 0040 0C2B cmp r3, #12 + 549 0042 F9D1 bne .L29 + 550 .LBB42: + 551 .LBB43: + 152:./Src/stm32l0xx_hw.c **** + 552 .loc 1 152 0 + 553 0044 FFF7FEFF bl HW_SPI_IoInit + 554 .LVL18: + 154:./Src/stm32l0xx_hw.c **** + 555 .loc 1 154 0 + 556 0048 044B ldr r3, .L30+4 + 557 004a 1B68 ldr r3, [r3] + 558 004c 9847 blx r3 + ARM GAS /tmp/ccKytYSe.s page 20 + + + 559 .LVL19: + 156:./Src/stm32l0xx_hw.c **** } + 560 .loc 1 156 0 + 561 004e FFF7FEFF bl vcom_IoInit + 562 .LVL20: + 563 .LBE43: + 564 .LBE42: + 565 .LBB44: + 566 .LBB45: + 567 .loc 2 215 0 + 568 .syntax divided + 569 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 570 0052 84F31088 MSR primask, r4 + 571 @ 0 "" 2 + 572 .LVL21: + 573 .thumb + 574 .syntax unified + 575 .LBE45: + 576 .LBE44: + 316:./Src/stm32l0xx_hw.c **** + 317:./Src/stm32l0xx_hw.c **** /*initilizes the peripherals*/ + 318:./Src/stm32l0xx_hw.c **** HW_IoInit( ); + 319:./Src/stm32l0xx_hw.c **** + 320:./Src/stm32l0xx_hw.c **** RESTORE_PRIMASK( ); + 321:./Src/stm32l0xx_hw.c **** } + 577 .loc 1 321 0 + 578 @ sp needed + 579 0056 10BD pop {r4, pc} + 580 .L31: + 581 .align 2 + 582 .L30: + 583 0058 00100240 .word 1073876992 + 584 005c 00000000 .word Radio + 585 .cfi_endproc + 586 .LFE105: + 588 .section .text.HW_EnterSleepMode,"ax",%progbits + 589 .align 1 + 590 .global HW_EnterSleepMode + 591 .syntax unified + 592 .code 16 + 593 .thumb_func + 594 .fpu softvfp + 596 HW_EnterSleepMode: + 597 .LFB106: + 322:./Src/stm32l0xx_hw.c **** + 323:./Src/stm32l0xx_hw.c **** /** + 324:./Src/stm32l0xx_hw.c **** * @brief Enters Low Power Sleep Mode + 325:./Src/stm32l0xx_hw.c **** * @note ARM exits the function when waking up + 326:./Src/stm32l0xx_hw.c **** * @param none + 327:./Src/stm32l0xx_hw.c **** * @retval none + 328:./Src/stm32l0xx_hw.c **** */ + 329:./Src/stm32l0xx_hw.c **** void HW_EnterSleepMode( void) + 330:./Src/stm32l0xx_hw.c **** { + 598 .loc 1 330 0 + 599 .cfi_startproc + 600 @ args = 0, pretend = 0, frame = 0 + 601 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccKytYSe.s page 21 + + + 602 0000 10B5 push {r4, lr} + 603 .LCFI7: + 604 .cfi_def_cfa_offset 8 + 605 .cfi_offset 4, -8 + 606 .cfi_offset 14, -4 + 331:./Src/stm32l0xx_hw.c **** HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + 607 .loc 1 331 0 + 608 0002 0121 movs r1, #1 + 609 0004 0020 movs r0, #0 + 610 0006 FFF7FEFF bl HAL_PWR_EnterSLEEPMode + 611 .LVL22: + 332:./Src/stm32l0xx_hw.c **** } + 612 .loc 1 332 0 + 613 @ sp needed + 614 000a 10BD pop {r4, pc} + 615 .cfi_endproc + 616 .LFE106: + 618 .section .bss.McuInitialized,"aw",%nobits + 619 .set .LANCHOR0,. + 0 + 622 McuInitialized: + 623 0000 00 .space 1 + 624 .section .rodata.SystemClock_Config.str1.4,"aMS",%progbits,1 + 625 .align 2 + 626 .LC4: + 627 0000 2E2F5372 .ascii "./Src/stm32l0xx_hw.c\000" + 627 632F7374 + 627 6D33326C + 627 3078785F + 627 68772E63 + 628 .text + 629 .Letext0: + 630 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 631 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 632 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 633 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 634 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + 635 .file 8 "/usr/arm-none-eabi/include/math.h" + 636 .file 9 "/usr/arm-none-eabi/include/sys/_stdint.h" + 637 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 638 .file 11 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 639 .file 12 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 640 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 641 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h" + 642 .file 15 "Middlewares/Third_Party/Lora/Phy/radio.h" + 643 .file 16 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h" + 644 .file 17 "Inc/hw_spi.h" + 645 .file 18 "Inc/vcom.h" + 646 .file 19 "Inc/debug.h" + 647 .file 20 "Inc/hw_rtc.h" + 648 .file 21 "" + ARM GAS /tmp/ccKytYSe.s page 22 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_hw.c + /tmp/ccKytYSe.s:16 .text.HW_Init:0000000000000000 $t + /tmp/ccKytYSe.s:23 .text.HW_Init:0000000000000000 HW_Init + /tmp/ccKytYSe.s:65 .text.HW_Init:0000000000000024 $d + /tmp/ccKytYSe.s:71 .text.HW_DeInit:0000000000000000 $t + /tmp/ccKytYSe.s:78 .text.HW_DeInit:0000000000000000 HW_DeInit + /tmp/ccKytYSe.s:110 .text.HW_DeInit:0000000000000018 $d + /tmp/ccKytYSe.s:116 .text.HW_GpioInit:0000000000000000 $t + /tmp/ccKytYSe.s:123 .text.HW_GpioInit:0000000000000000 HW_GpioInit + /tmp/ccKytYSe.s:137 .text.SystemClock_Config:0000000000000000 $t + /tmp/ccKytYSe.s:144 .text.SystemClock_Config:0000000000000000 SystemClock_Config + /tmp/ccKytYSe.s:260 .text.SystemClock_Config:0000000000000094 $d + /tmp/ccKytYSe.s:268 .text.HW_GetRandomSeed:0000000000000000 $t + /tmp/ccKytYSe.s:275 .text.HW_GetRandomSeed:0000000000000000 HW_GetRandomSeed + /tmp/ccKytYSe.s:297 .text.HW_GetRandomSeed:0000000000000014 $d + /tmp/ccKytYSe.s:304 .text.HW_GetUniqueId:0000000000000000 $t + /tmp/ccKytYSe.s:311 .text.HW_GetUniqueId:0000000000000000 HW_GetUniqueId + /tmp/ccKytYSe.s:374 .text.HW_GetUniqueId:0000000000000050 $d + /tmp/ccKytYSe.s:381 .text.HW_EnterStopMode:0000000000000000 $t + /tmp/ccKytYSe.s:388 .text.HW_EnterStopMode:0000000000000000 HW_EnterStopMode + /tmp/ccKytYSe.s:465 .text.HW_EnterStopMode:0000000000000030 $d + /tmp/ccKytYSe.s:471 .text.HW_ExitStopMode:0000000000000000 $t + /tmp/ccKytYSe.s:478 .text.HW_ExitStopMode:0000000000000000 HW_ExitStopMode + /tmp/ccKytYSe.s:583 .text.HW_ExitStopMode:0000000000000058 $d + /tmp/ccKytYSe.s:589 .text.HW_EnterSleepMode:0000000000000000 $t + /tmp/ccKytYSe.s:596 .text.HW_EnterSleepMode:0000000000000000 HW_EnterSleepMode + /tmp/ccKytYSe.s:622 .bss.McuInitialized:0000000000000000 McuInitialized + /tmp/ccKytYSe.s:623 .bss.McuInitialized:0000000000000000 $d + /tmp/ccKytYSe.s:625 .rodata.SystemClock_Config.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HW_SPI_Init +HW_RTC_Init +vcom_Init +Radio +HW_SPI_DeInit +vcom_DeInit +memset +HAL_RCC_OscConfig +HAL_RCC_ClockConfig +_Error_Handler +HW_SPI_IoDeInit +vcom_IoDeInit +HAL_PWR_EnterSTOPMode +HW_SPI_IoInit +vcom_IoInit +HAL_PWR_EnterSLEEPMode diff --git a/build/stm32l0xx_it.d b/build/stm32l0xx_it.d new file mode 100644 index 0000000..b6e49f7 --- /dev/null +++ b/build/stm32l0xx_it.d @@ -0,0 +1,140 @@ +build/stm32l0xx_it.d: Src/stm32l0xx_it.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h Inc/stm32l0xx_it.h \ + Middlewares/Third_Party/Lora/Utilities/low_power.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Inc/stm32l0xx_it.h: + +Middlewares/Third_Party/Lora/Utilities/low_power.h: diff --git a/build/stm32l0xx_it.lst b/build/stm32l0xx_it.lst new file mode 100644 index 0000000..24590d7 --- /dev/null +++ b/build/stm32l0xx_it.lst @@ -0,0 +1,1162 @@ +ARM GAS /tmp/ccVGIcju.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_it.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.NMI_Handler,"ax",%progbits + 16 .align 1 + 17 .global NMI_Handler + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 NMI_Handler: + 24 .LFB96: + 25 .file 1 "./Src/stm32l0xx_it.c" + 1:./Src/stm32l0xx_it.c **** /* + 2:./Src/stm32l0xx_it.c **** / _____) _ | | + 3:./Src/stm32l0xx_it.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Src/stm32l0xx_it.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Src/stm32l0xx_it.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Src/stm32l0xx_it.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Src/stm32l0xx_it.c **** (C)2013 Semtech + 8:./Src/stm32l0xx_it.c **** + 9:./Src/stm32l0xx_it.c **** Description: Bleeper board GPIO driver implementation + 10:./Src/stm32l0xx_it.c **** + 11:./Src/stm32l0xx_it.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Src/stm32l0xx_it.c **** + 13:./Src/stm32l0xx_it.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Src/stm32l0xx_it.c **** */ + 15:./Src/stm32l0xx_it.c **** /****************************************************************************** + 16:./Src/stm32l0xx_it.c **** * @file stm32l0xx_it.c + 17:./Src/stm32l0xx_it.c **** * @author MCD Application Team + 18:./Src/stm32l0xx_it.c **** * @version V1.1.2 + 19:./Src/stm32l0xx_it.c **** * @date 08-September-2017 + 20:./Src/stm32l0xx_it.c **** * @brief manages interupt + 21:./Src/stm32l0xx_it.c **** ****************************************************************************** + 22:./Src/stm32l0xx_it.c **** * @attention + 23:./Src/stm32l0xx_it.c **** * + 24:./Src/stm32l0xx_it.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Src/stm32l0xx_it.c **** * All rights reserved.

+ 26:./Src/stm32l0xx_it.c **** * + 27:./Src/stm32l0xx_it.c **** * Redistribution and use in source and binary forms, with or without + 28:./Src/stm32l0xx_it.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Src/stm32l0xx_it.c **** * + 30:./Src/stm32l0xx_it.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Src/stm32l0xx_it.c **** * this list of conditions and the following disclaimer. + 32:./Src/stm32l0xx_it.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Src/stm32l0xx_it.c **** * this list of conditions and the following disclaimer in the documentation + ARM GAS /tmp/ccVGIcju.s page 2 + + + 34:./Src/stm32l0xx_it.c **** * and/or other materials provided with the distribution. + 35:./Src/stm32l0xx_it.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Src/stm32l0xx_it.c **** * contributors to this software may be used to endorse or promote products + 37:./Src/stm32l0xx_it.c **** * derived from this software without specific written permission. + 38:./Src/stm32l0xx_it.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Src/stm32l0xx_it.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Src/stm32l0xx_it.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Src/stm32l0xx_it.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Src/stm32l0xx_it.c **** * this license is void and will automatically terminate your rights under + 43:./Src/stm32l0xx_it.c **** * this license. + 44:./Src/stm32l0xx_it.c **** * + 45:./Src/stm32l0xx_it.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Src/stm32l0xx_it.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Src/stm32l0xx_it.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Src/stm32l0xx_it.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Src/stm32l0xx_it.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Src/stm32l0xx_it.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Src/stm32l0xx_it.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Src/stm32l0xx_it.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Src/stm32l0xx_it.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Src/stm32l0xx_it.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Src/stm32l0xx_it.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Src/stm32l0xx_it.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Src/stm32l0xx_it.c **** * + 58:./Src/stm32l0xx_it.c **** ****************************************************************************** + 59:./Src/stm32l0xx_it.c **** */ + 60:./Src/stm32l0xx_it.c **** + 61:./Src/stm32l0xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Src/stm32l0xx_it.c **** #include "hw.h" + 63:./Src/stm32l0xx_it.c **** #include "stm32l0xx_it.h" + 64:./Src/stm32l0xx_it.c **** #include "low_power.h" + 65:./Src/stm32l0xx_it.c **** + 66:./Src/stm32l0xx_it.c **** /** @addtogroup STM32L1xx_HAL_Examples + 67:./Src/stm32l0xx_it.c **** * @{ + 68:./Src/stm32l0xx_it.c **** */ + 69:./Src/stm32l0xx_it.c **** + 70:./Src/stm32l0xx_it.c **** /** @addtogroup SPI_FullDuplex_ComPolling + 71:./Src/stm32l0xx_it.c **** * @{ + 72:./Src/stm32l0xx_it.c **** */ + 73:./Src/stm32l0xx_it.c **** + 74:./Src/stm32l0xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 75:./Src/stm32l0xx_it.c **** /* Private define ------------------------------------------------------------*/ + 76:./Src/stm32l0xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 77:./Src/stm32l0xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 78:./Src/stm32l0xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 79:./Src/stm32l0xx_it.c **** /* Private functions ---------------------------------------------------------*/ + 80:./Src/stm32l0xx_it.c **** + 81:./Src/stm32l0xx_it.c **** /******************************************************************************/ + 82:./Src/stm32l0xx_it.c **** /* Cortex-M3 Processor Exceptions Handlers */ + 83:./Src/stm32l0xx_it.c **** /******************************************************************************/ + 84:./Src/stm32l0xx_it.c **** + 85:./Src/stm32l0xx_it.c **** /** + 86:./Src/stm32l0xx_it.c **** * @brief This function handles NMI exception. + 87:./Src/stm32l0xx_it.c **** * @param None + 88:./Src/stm32l0xx_it.c **** * @retval None + 89:./Src/stm32l0xx_it.c **** */ + 90:./Src/stm32l0xx_it.c **** + ARM GAS /tmp/ccVGIcju.s page 3 + + + 91:./Src/stm32l0xx_it.c **** void NMI_Handler(void) + 92:./Src/stm32l0xx_it.c **** { + 26 .loc 1 92 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 93:./Src/stm32l0xx_it.c **** } + 31 .loc 1 93 0 + 32 @ sp needed + 33 0000 7047 bx lr + 34 .cfi_endproc + 35 .LFE96: + 37 .section .text.HardFault_Handler,"ax",%progbits + 38 .align 1 + 39 .global HardFault_Handler + 40 .syntax unified + 41 .code 16 + 42 .thumb_func + 43 .fpu softvfp + 45 HardFault_Handler: + 46 .LFB97: + 94:./Src/stm32l0xx_it.c **** + 95:./Src/stm32l0xx_it.c **** + 96:./Src/stm32l0xx_it.c **** /** + 97:./Src/stm32l0xx_it.c **** * @brief This function handles Hard Fault exception. + 98:./Src/stm32l0xx_it.c **** * @param None + 99:./Src/stm32l0xx_it.c **** * @retval None + 100:./Src/stm32l0xx_it.c **** */ + 101:./Src/stm32l0xx_it.c **** + 102:./Src/stm32l0xx_it.c **** + 103:./Src/stm32l0xx_it.c **** void HardFault_Handler(void) + 104:./Src/stm32l0xx_it.c **** { + 47 .loc 1 104 0 + 48 .cfi_startproc + 49 @ Volatile: function does not return. + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 0000 10B5 push {r4, lr} + 53 .LCFI0: + 54 .cfi_def_cfa_offset 8 + 55 .cfi_offset 4, -8 + 56 .cfi_offset 14, -4 + 105:./Src/stm32l0xx_it.c **** PRINTF("\r\nHARDFAULT!\r\n"); + 57 .loc 1 105 0 + 58 0002 0248 ldr r0, .L4 + 59 0004 FFF7FEFF bl vcom_Send + 60 .LVL0: + 61 .L3: + 62 .LBB4: + 63 .LBB5: + 64 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + ARM GAS /tmp/ccVGIcju.s page 4 + + + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccVGIcju.s page 5 + + + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + ARM GAS /tmp/ccVGIcju.s page 6 + + + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccVGIcju.s page 7 + + + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + ARM GAS /tmp/ccVGIcju.s page 8 + + + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccVGIcju.s page 9 + + + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */ + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0); + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccVGIcju.s page 10 + + + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop"); + 65 .loc 2 375 0 discriminator 1 + 66 .syntax divided + 67 @ 375 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 68 0008 C046 nop + 69 @ 0 "" 2 + 70 .thumb + 71 .syntax unified + 72 000a FDE7 b .L3 + 73 .L5: + 74 .align 2 + 75 .L4: + 76 000c 00000000 .word .LC0 + 77 .LBE5: + 78 .LBE4: + 79 .cfi_endproc + 80 .LFE97: + 82 .section .text.MemManage_Handler,"ax",%progbits + 83 .align 1 + 84 .global MemManage_Handler + 85 .syntax unified + 86 .code 16 + 87 .thumb_func + 88 .fpu softvfp + 90 MemManage_Handler: + 91 .LFB98: + 106:./Src/stm32l0xx_it.c **** while(1) + 107:./Src/stm32l0xx_it.c **** { + 108:./Src/stm32l0xx_it.c **** __NOP(); + 109:./Src/stm32l0xx_it.c **** } + ARM GAS /tmp/ccVGIcju.s page 11 + + + 110:./Src/stm32l0xx_it.c **** + 111:./Src/stm32l0xx_it.c **** } + 112:./Src/stm32l0xx_it.c **** + 113:./Src/stm32l0xx_it.c **** + 114:./Src/stm32l0xx_it.c **** /** + 115:./Src/stm32l0xx_it.c **** * @brief This function handles Memory Manage exception. + 116:./Src/stm32l0xx_it.c **** * @param None + 117:./Src/stm32l0xx_it.c **** * @retval None + 118:./Src/stm32l0xx_it.c **** */ + 119:./Src/stm32l0xx_it.c **** void MemManage_Handler(void) + 120:./Src/stm32l0xx_it.c **** { + 92 .loc 1 120 0 + 93 .cfi_startproc + 94 @ Volatile: function does not return. + 95 @ args = 0, pretend = 0, frame = 0 + 96 @ frame_needed = 0, uses_anonymous_args = 0 + 97 @ link register save eliminated. + 98 .L7: + 99 0000 FEE7 b .L7 + 100 .cfi_endproc + 101 .LFE98: + 103 .section .text.BusFault_Handler,"ax",%progbits + 104 .align 1 + 105 .global BusFault_Handler + 106 .syntax unified + 107 .code 16 + 108 .thumb_func + 109 .fpu softvfp + 111 BusFault_Handler: + 112 .LFB99: + 121:./Src/stm32l0xx_it.c **** /* Go to infinite loop when Memory Manage exception occurs */ + 122:./Src/stm32l0xx_it.c **** while (1) + 123:./Src/stm32l0xx_it.c **** { + 124:./Src/stm32l0xx_it.c **** } + 125:./Src/stm32l0xx_it.c **** } + 126:./Src/stm32l0xx_it.c **** + 127:./Src/stm32l0xx_it.c **** /** + 128:./Src/stm32l0xx_it.c **** * @brief This function handles Bus Fault exception. + 129:./Src/stm32l0xx_it.c **** * @param None + 130:./Src/stm32l0xx_it.c **** * @retval None + 131:./Src/stm32l0xx_it.c **** */ + 132:./Src/stm32l0xx_it.c **** void BusFault_Handler(void) + 133:./Src/stm32l0xx_it.c **** { + 113 .loc 1 133 0 + 114 .cfi_startproc + 115 @ Volatile: function does not return. + 116 @ args = 0, pretend = 0, frame = 0 + 117 @ frame_needed = 0, uses_anonymous_args = 0 + 118 @ link register save eliminated. + 119 .L9: + 120 0000 FEE7 b .L9 + 121 .cfi_endproc + 122 .LFE99: + 124 .section .text.UsageFault_Handler,"ax",%progbits + 125 .align 1 + 126 .global UsageFault_Handler + 127 .syntax unified + ARM GAS /tmp/ccVGIcju.s page 12 + + + 128 .code 16 + 129 .thumb_func + 130 .fpu softvfp + 132 UsageFault_Handler: + 133 .LFB100: + 134:./Src/stm32l0xx_it.c **** /* Go to infinite loop when Bus Fault exception occurs */ + 135:./Src/stm32l0xx_it.c **** while (1) + 136:./Src/stm32l0xx_it.c **** { + 137:./Src/stm32l0xx_it.c **** } + 138:./Src/stm32l0xx_it.c **** } + 139:./Src/stm32l0xx_it.c **** + 140:./Src/stm32l0xx_it.c **** /** + 141:./Src/stm32l0xx_it.c **** * @brief This function handles Usage Fault exception. + 142:./Src/stm32l0xx_it.c **** * @param None + 143:./Src/stm32l0xx_it.c **** * @retval None + 144:./Src/stm32l0xx_it.c **** */ + 145:./Src/stm32l0xx_it.c **** void UsageFault_Handler(void) + 146:./Src/stm32l0xx_it.c **** { + 134 .loc 1 146 0 + 135 .cfi_startproc + 136 @ Volatile: function does not return. + 137 @ args = 0, pretend = 0, frame = 0 + 138 @ frame_needed = 0, uses_anonymous_args = 0 + 139 @ link register save eliminated. + 140 .L11: + 141 0000 FEE7 b .L11 + 142 .cfi_endproc + 143 .LFE100: + 145 .section .text.SVC_Handler,"ax",%progbits + 146 .align 1 + 147 .global SVC_Handler + 148 .syntax unified + 149 .code 16 + 150 .thumb_func + 151 .fpu softvfp + 153 SVC_Handler: + 154 .LFB101: + 147:./Src/stm32l0xx_it.c **** /* Go to infinite loop when Usage Fault exception occurs */ + 148:./Src/stm32l0xx_it.c **** while (1) + 149:./Src/stm32l0xx_it.c **** { + 150:./Src/stm32l0xx_it.c **** } + 151:./Src/stm32l0xx_it.c **** } + 152:./Src/stm32l0xx_it.c **** + 153:./Src/stm32l0xx_it.c **** /** + 154:./Src/stm32l0xx_it.c **** * @brief This function handles SVCall exception. + 155:./Src/stm32l0xx_it.c **** * @param None + 156:./Src/stm32l0xx_it.c **** * @retval None + 157:./Src/stm32l0xx_it.c **** */ + 158:./Src/stm32l0xx_it.c **** void SVC_Handler(void) + 159:./Src/stm32l0xx_it.c **** { + 155 .loc 1 159 0 + 156 .cfi_startproc + 157 @ args = 0, pretend = 0, frame = 0 + 158 @ frame_needed = 0, uses_anonymous_args = 0 + 159 @ link register save eliminated. + 160:./Src/stm32l0xx_it.c **** } + 160 .loc 1 160 0 + ARM GAS /tmp/ccVGIcju.s page 13 + + + 161 @ sp needed + 162 0000 7047 bx lr + 163 .cfi_endproc + 164 .LFE101: + 166 .section .text.DebugMon_Handler,"ax",%progbits + 167 .align 1 + 168 .global DebugMon_Handler + 169 .syntax unified + 170 .code 16 + 171 .thumb_func + 172 .fpu softvfp + 174 DebugMon_Handler: + 175 .LFB102: + 161:./Src/stm32l0xx_it.c **** + 162:./Src/stm32l0xx_it.c **** /** + 163:./Src/stm32l0xx_it.c **** * @brief This function handles Debug Monitor exception. + 164:./Src/stm32l0xx_it.c **** * @param None + 165:./Src/stm32l0xx_it.c **** * @retval None + 166:./Src/stm32l0xx_it.c **** */ + 167:./Src/stm32l0xx_it.c **** void DebugMon_Handler(void) + 168:./Src/stm32l0xx_it.c **** { + 176 .loc 1 168 0 + 177 .cfi_startproc + 178 @ args = 0, pretend = 0, frame = 0 + 179 @ frame_needed = 0, uses_anonymous_args = 0 + 180 @ link register save eliminated. + 169:./Src/stm32l0xx_it.c **** } + 181 .loc 1 169 0 + 182 @ sp needed + 183 0000 7047 bx lr + 184 .cfi_endproc + 185 .LFE102: + 187 .section .text.PendSV_Handler,"ax",%progbits + 188 .align 1 + 189 .global PendSV_Handler + 190 .syntax unified + 191 .code 16 + 192 .thumb_func + 193 .fpu softvfp + 195 PendSV_Handler: + 196 .LFB103: + 170:./Src/stm32l0xx_it.c **** + 171:./Src/stm32l0xx_it.c **** /** + 172:./Src/stm32l0xx_it.c **** * @brief This function handles PendSVC exception. + 173:./Src/stm32l0xx_it.c **** * @param None + 174:./Src/stm32l0xx_it.c **** * @retval None + 175:./Src/stm32l0xx_it.c **** */ + 176:./Src/stm32l0xx_it.c **** void PendSV_Handler(void) + 177:./Src/stm32l0xx_it.c **** { + 197 .loc 1 177 0 + 198 .cfi_startproc + 199 @ args = 0, pretend = 0, frame = 0 + 200 @ frame_needed = 0, uses_anonymous_args = 0 + 201 @ link register save eliminated. + 178:./Src/stm32l0xx_it.c **** } + 202 .loc 1 178 0 + 203 @ sp needed + ARM GAS /tmp/ccVGIcju.s page 14 + + + 204 0000 7047 bx lr + 205 .cfi_endproc + 206 .LFE103: + 208 .section .text.SysTick_Handler,"ax",%progbits + 209 .align 1 + 210 .global SysTick_Handler + 211 .syntax unified + 212 .code 16 + 213 .thumb_func + 214 .fpu softvfp + 216 SysTick_Handler: + 217 .LFB104: + 179:./Src/stm32l0xx_it.c **** + 180:./Src/stm32l0xx_it.c **** /** + 181:./Src/stm32l0xx_it.c **** * @brief This function handles SysTick Handler. + 182:./Src/stm32l0xx_it.c **** * @param None + 183:./Src/stm32l0xx_it.c **** * @retval None + 184:./Src/stm32l0xx_it.c **** */ + 185:./Src/stm32l0xx_it.c **** void SysTick_Handler(void) + 186:./Src/stm32l0xx_it.c **** { + 218 .loc 1 186 0 + 219 .cfi_startproc + 220 @ args = 0, pretend = 0, frame = 0 + 221 @ frame_needed = 0, uses_anonymous_args = 0 + 222 0000 10B5 push {r4, lr} + 223 .LCFI1: + 224 .cfi_def_cfa_offset 8 + 225 .cfi_offset 4, -8 + 226 .cfi_offset 14, -4 + 187:./Src/stm32l0xx_it.c **** HAL_IncTick(); + 227 .loc 1 187 0 + 228 0002 FFF7FEFF bl HAL_IncTick + 229 .LVL1: + 188:./Src/stm32l0xx_it.c **** } + 230 .loc 1 188 0 + 231 @ sp needed + 232 0006 10BD pop {r4, pc} + 233 .cfi_endproc + 234 .LFE104: + 236 .section .text.USART2_IRQHandler,"ax",%progbits + 237 .align 1 + 238 .global USART2_IRQHandler + 239 .syntax unified + 240 .code 16 + 241 .thumb_func + 242 .fpu softvfp + 244 USART2_IRQHandler: + 245 .LFB105: + 189:./Src/stm32l0xx_it.c **** + 190:./Src/stm32l0xx_it.c **** /******************************************************************************/ + 191:./Src/stm32l0xx_it.c **** /* STM32L1xx Peripherals Interrupt Handlers */ + 192:./Src/stm32l0xx_it.c **** /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ + 193:./Src/stm32l0xx_it.c **** /* available peripheral interrupt handler's name please refer to the startup */ + 194:./Src/stm32l0xx_it.c **** /* file (startup_stm32l1xx.s). */ + 195:./Src/stm32l0xx_it.c **** /******************************************************************************/ + 196:./Src/stm32l0xx_it.c **** + 197:./Src/stm32l0xx_it.c **** /** + ARM GAS /tmp/ccVGIcju.s page 15 + + + 198:./Src/stm32l0xx_it.c **** * @brief This function handles PPP interrupt request. + 199:./Src/stm32l0xx_it.c **** * @param None + 200:./Src/stm32l0xx_it.c **** * @retval None + 201:./Src/stm32l0xx_it.c **** */ + 202:./Src/stm32l0xx_it.c **** /*void PPP_IRQHandler(void) + 203:./Src/stm32l0xx_it.c **** { + 204:./Src/stm32l0xx_it.c **** }*/ + 205:./Src/stm32l0xx_it.c **** + 206:./Src/stm32l0xx_it.c **** void USART2_IRQHandler( void ) + 207:./Src/stm32l0xx_it.c **** { + 246 .loc 1 207 0 + 247 .cfi_startproc + 248 @ args = 0, pretend = 0, frame = 0 + 249 @ frame_needed = 0, uses_anonymous_args = 0 + 250 0000 10B5 push {r4, lr} + 251 .LCFI2: + 252 .cfi_def_cfa_offset 8 + 253 .cfi_offset 4, -8 + 254 .cfi_offset 14, -4 + 208:./Src/stm32l0xx_it.c **** vcom_Print( ); + 255 .loc 1 208 0 + 256 0002 FFF7FEFF bl vcom_Print + 257 .LVL2: + 209:./Src/stm32l0xx_it.c **** } + 258 .loc 1 209 0 + 259 @ sp needed + 260 0006 10BD pop {r4, pc} + 261 .cfi_endproc + 262 .LFE105: + 264 .section .text.RTC_IRQHandler,"ax",%progbits + 265 .align 1 + 266 .global RTC_IRQHandler + 267 .syntax unified + 268 .code 16 + 269 .thumb_func + 270 .fpu softvfp + 272 RTC_IRQHandler: + 273 .LFB106: + 210:./Src/stm32l0xx_it.c **** + 211:./Src/stm32l0xx_it.c **** void RTC_IRQHandler( void ) + 212:./Src/stm32l0xx_it.c **** { + 274 .loc 1 212 0 + 275 .cfi_startproc + 276 @ args = 0, pretend = 0, frame = 0 + 277 @ frame_needed = 0, uses_anonymous_args = 0 + 278 0000 10B5 push {r4, lr} + 279 .LCFI3: + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 4, -8 + 282 .cfi_offset 14, -4 + 213:./Src/stm32l0xx_it.c **** HW_RTC_IrqHandler ( ); + 283 .loc 1 213 0 + 284 0002 FFF7FEFF bl HW_RTC_IrqHandler + 285 .LVL3: + 214:./Src/stm32l0xx_it.c **** } + 286 .loc 1 214 0 + 287 @ sp needed + ARM GAS /tmp/ccVGIcju.s page 16 + + + 288 0006 10BD pop {r4, pc} + 289 .cfi_endproc + 290 .LFE106: + 292 .section .text.EXTI0_1_IRQHandler,"ax",%progbits + 293 .align 1 + 294 .global EXTI0_1_IRQHandler + 295 .syntax unified + 296 .code 16 + 297 .thumb_func + 298 .fpu softvfp + 300 EXTI0_1_IRQHandler: + 301 .LFB107: + 215:./Src/stm32l0xx_it.c **** + 216:./Src/stm32l0xx_it.c **** void EXTI0_1_IRQHandler( void ) + 217:./Src/stm32l0xx_it.c **** { + 302 .loc 1 217 0 + 303 .cfi_startproc + 304 @ args = 0, pretend = 0, frame = 0 + 305 @ frame_needed = 0, uses_anonymous_args = 0 + 306 0000 10B5 push {r4, lr} + 307 .LCFI4: + 308 .cfi_def_cfa_offset 8 + 309 .cfi_offset 4, -8 + 310 .cfi_offset 14, -4 + 218:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_0 ); + 311 .loc 1 218 0 + 312 0002 0120 movs r0, #1 + 313 0004 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 314 .LVL4: + 219:./Src/stm32l0xx_it.c **** + 220:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_1 ); + 315 .loc 1 220 0 + 316 0008 0220 movs r0, #2 + 317 000a FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 318 .LVL5: + 221:./Src/stm32l0xx_it.c **** } + 319 .loc 1 221 0 + 320 @ sp needed + 321 000e 10BD pop {r4, pc} + 322 .cfi_endproc + 323 .LFE107: + 325 .section .text.EXTI2_3_IRQHandler,"ax",%progbits + 326 .align 1 + 327 .global EXTI2_3_IRQHandler + 328 .syntax unified + 329 .code 16 + 330 .thumb_func + 331 .fpu softvfp + 333 EXTI2_3_IRQHandler: + 334 .LFB108: + 222:./Src/stm32l0xx_it.c **** + 223:./Src/stm32l0xx_it.c **** void EXTI2_3_IRQHandler( void ) + 224:./Src/stm32l0xx_it.c **** { + 335 .loc 1 224 0 + 336 .cfi_startproc + 337 @ args = 0, pretend = 0, frame = 0 + 338 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccVGIcju.s page 17 + + + 339 0000 10B5 push {r4, lr} + 340 .LCFI5: + 341 .cfi_def_cfa_offset 8 + 342 .cfi_offset 4, -8 + 343 .cfi_offset 14, -4 + 225:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_2 ); + 344 .loc 1 225 0 + 345 0002 0420 movs r0, #4 + 346 0004 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 347 .LVL6: + 226:./Src/stm32l0xx_it.c **** + 227:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_3 ); + 348 .loc 1 227 0 + 349 0008 0820 movs r0, #8 + 350 000a FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 351 .LVL7: + 228:./Src/stm32l0xx_it.c **** } + 352 .loc 1 228 0 + 353 @ sp needed + 354 000e 10BD pop {r4, pc} + 355 .cfi_endproc + 356 .LFE108: + 358 .section .text.EXTI4_15_IRQHandler,"ax",%progbits + 359 .align 1 + 360 .global EXTI4_15_IRQHandler + 361 .syntax unified + 362 .code 16 + 363 .thumb_func + 364 .fpu softvfp + 366 EXTI4_15_IRQHandler: + 367 .LFB109: + 229:./Src/stm32l0xx_it.c **** + 230:./Src/stm32l0xx_it.c **** + 231:./Src/stm32l0xx_it.c **** void EXTI4_15_IRQHandler( void ) + 232:./Src/stm32l0xx_it.c **** { + 368 .loc 1 232 0 + 369 .cfi_startproc + 370 @ args = 0, pretend = 0, frame = 0 + 371 @ frame_needed = 0, uses_anonymous_args = 0 + 372 0000 10B5 push {r4, lr} + 373 .LCFI6: + 374 .cfi_def_cfa_offset 8 + 375 .cfi_offset 4, -8 + 376 .cfi_offset 14, -4 + 233:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_4 ); + 377 .loc 1 233 0 + 378 0002 1020 movs r0, #16 + 379 0004 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 380 .LVL8: + 234:./Src/stm32l0xx_it.c **** + 235:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_5 ); + 381 .loc 1 235 0 + 382 0008 2020 movs r0, #32 + 383 000a FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 384 .LVL9: + 236:./Src/stm32l0xx_it.c **** + 237:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_6 ); + ARM GAS /tmp/ccVGIcju.s page 18 + + + 385 .loc 1 237 0 + 386 000e 4020 movs r0, #64 + 387 0010 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 388 .LVL10: + 238:./Src/stm32l0xx_it.c **** + 239:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_7 ); + 389 .loc 1 239 0 + 390 0014 8020 movs r0, #128 + 391 0016 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 392 .LVL11: + 240:./Src/stm32l0xx_it.c **** + 241:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_8 ); + 393 .loc 1 241 0 + 394 001a 8020 movs r0, #128 + 395 001c 4000 lsls r0, r0, #1 + 396 001e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 397 .LVL12: + 242:./Src/stm32l0xx_it.c **** + 243:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_9 ); + 398 .loc 1 243 0 + 399 0022 8020 movs r0, #128 + 400 0024 8000 lsls r0, r0, #2 + 401 0026 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 402 .LVL13: + 244:./Src/stm32l0xx_it.c **** + 245:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_10 ); + 403 .loc 1 245 0 + 404 002a 8020 movs r0, #128 + 405 002c C000 lsls r0, r0, #3 + 406 002e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 407 .LVL14: + 246:./Src/stm32l0xx_it.c **** + 247:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_11 ); + 408 .loc 1 247 0 + 409 0032 8020 movs r0, #128 + 410 0034 0001 lsls r0, r0, #4 + 411 0036 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 412 .LVL15: + 248:./Src/stm32l0xx_it.c **** + 249:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_12 ); + 413 .loc 1 249 0 + 414 003a 8020 movs r0, #128 + 415 003c 4001 lsls r0, r0, #5 + 416 003e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 417 .LVL16: + 250:./Src/stm32l0xx_it.c **** + 251:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_13 ); + 418 .loc 1 251 0 + 419 0042 8020 movs r0, #128 + 420 0044 8001 lsls r0, r0, #6 + 421 0046 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 422 .LVL17: + 252:./Src/stm32l0xx_it.c **** + 253:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_14 ); + 423 .loc 1 253 0 + 424 004a 8020 movs r0, #128 + 425 004c C001 lsls r0, r0, #7 + ARM GAS /tmp/ccVGIcju.s page 19 + + + 426 004e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 427 .LVL18: + 254:./Src/stm32l0xx_it.c **** + 255:./Src/stm32l0xx_it.c **** HAL_GPIO_EXTI_IRQHandler( GPIO_PIN_15 ); + 428 .loc 1 255 0 + 429 0052 8020 movs r0, #128 + 430 0054 0002 lsls r0, r0, #8 + 431 0056 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler + 432 .LVL19: + 256:./Src/stm32l0xx_it.c **** } + 433 .loc 1 256 0 + 434 @ sp needed + 435 005a 10BD pop {r4, pc} + 436 .cfi_endproc + 437 .LFE109: + 439 .section .rodata.HardFault_Handler.str1.4,"aMS",%progbits,1 + 440 .align 2 + 441 .LC0: + 442 0000 0D0A4841 .ascii "\015\012HARDFAULT!\015\012\000" + 442 52444641 + 442 554C5421 + 442 0D0A00 + 443 .text + 444 .Letext0: + 445 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 446 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 447 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 448 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 449 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + 450 .file 8 "/usr/arm-none-eabi/include/math.h" + 451 .file 9 "/usr/arm-none-eabi/include/sys/_stdint.h" + 452 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 453 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 454 .file 12 "Inc/hw_rtc.h" + 455 .file 13 "Inc/vcom.h" + 456 .file 14 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + ARM GAS /tmp/ccVGIcju.s page 20 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_it.c + /tmp/ccVGIcju.s:16 .text.NMI_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:23 .text.NMI_Handler:0000000000000000 NMI_Handler + /tmp/ccVGIcju.s:38 .text.HardFault_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:45 .text.HardFault_Handler:0000000000000000 HardFault_Handler + /tmp/ccVGIcju.s:76 .text.HardFault_Handler:000000000000000c $d + /tmp/ccVGIcju.s:83 .text.MemManage_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:90 .text.MemManage_Handler:0000000000000000 MemManage_Handler + /tmp/ccVGIcju.s:104 .text.BusFault_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:111 .text.BusFault_Handler:0000000000000000 BusFault_Handler + /tmp/ccVGIcju.s:125 .text.UsageFault_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:132 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler + /tmp/ccVGIcju.s:146 .text.SVC_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:153 .text.SVC_Handler:0000000000000000 SVC_Handler + /tmp/ccVGIcju.s:167 .text.DebugMon_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:174 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler + /tmp/ccVGIcju.s:188 .text.PendSV_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:195 .text.PendSV_Handler:0000000000000000 PendSV_Handler + /tmp/ccVGIcju.s:209 .text.SysTick_Handler:0000000000000000 $t + /tmp/ccVGIcju.s:216 .text.SysTick_Handler:0000000000000000 SysTick_Handler + /tmp/ccVGIcju.s:237 .text.USART2_IRQHandler:0000000000000000 $t + /tmp/ccVGIcju.s:244 .text.USART2_IRQHandler:0000000000000000 USART2_IRQHandler + /tmp/ccVGIcju.s:265 .text.RTC_IRQHandler:0000000000000000 $t + /tmp/ccVGIcju.s:272 .text.RTC_IRQHandler:0000000000000000 RTC_IRQHandler + /tmp/ccVGIcju.s:293 .text.EXTI0_1_IRQHandler:0000000000000000 $t + /tmp/ccVGIcju.s:300 .text.EXTI0_1_IRQHandler:0000000000000000 EXTI0_1_IRQHandler + /tmp/ccVGIcju.s:326 .text.EXTI2_3_IRQHandler:0000000000000000 $t + /tmp/ccVGIcju.s:333 .text.EXTI2_3_IRQHandler:0000000000000000 EXTI2_3_IRQHandler + /tmp/ccVGIcju.s:359 .text.EXTI4_15_IRQHandler:0000000000000000 $t + /tmp/ccVGIcju.s:366 .text.EXTI4_15_IRQHandler:0000000000000000 EXTI4_15_IRQHandler + /tmp/ccVGIcju.s:440 .rodata.HardFault_Handler.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +vcom_Send +HAL_IncTick +vcom_Print +HW_RTC_IrqHandler +HAL_GPIO_EXTI_IRQHandler diff --git a/build/stm32l0xx_ll_adc.d b/build/stm32l0xx_ll_adc.d new file mode 100644 index 0000000..9590158 --- /dev/null +++ b/build/stm32l0xx_ll_adc.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_adc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_adc.lst b/build/stm32l0xx_ll_adc.lst new file mode 100644 index 0000000..30b4d81 --- /dev/null +++ b/build/stm32l0xx_ll_adc.lst @@ -0,0 +1,5993 @@ +ARM GAS /tmp/ccBKcv9L.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_adc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_ADC_CommonDeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_ADC_CommonDeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_ADC_CommonDeInit: + 24 .LFB170: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @file stm32l0xx_ll_adc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief ADC LL module driver + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ****************************************************************************** + ARM GAS /tmp/ccBKcv9L.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #include "stm32l0xx_ll_adc.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #if defined (ADC1) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup ADC_LL ADC + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup ADC_LL_Private_Constants + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Definitions of ADC hardware constraints delays */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* not timeout values: */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Timeout values for ADC operations are dependent to device clock */ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* configuration (system clock versus ADC clock), */ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* and therefore must be defined in user application. */ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* values definition. */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: ADC timeout values are defined here in CPU cycles to be independent */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* of device clock setting. */ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* In user application, ADC timeout values should be defined with */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* temporal values, in function of device clock settings. */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Highest ratio CPU clock frequency vs ADC clock frequency: */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - ADC clock from synchronous clock with AHB prescaler 512, */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* APB prescaler 16, ADC prescaler 4. */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* with highest ratio CPU clock frequency vs HSI clock frequency: */ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* CPU clock frequency max 32MHz, HSI frequency 16MHz: ratio 2. */ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Unit: CPU cycles. */ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @} + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + ARM GAS /tmp/ccBKcv9L.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Private macros ------------------------------------------------------------*/ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup ADC_LL_Private_Macros + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check of parameters for configuration of ADC hierarchical scope: */ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* common to several ADC instances. */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check of parameters for configuration of ADC hierarchical scope: */ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC instance. */ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_CLOCK(__CLOCK__) \ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check of parameters for configuration of ADC hierarchical scope: */ + ARM GAS /tmp/ccBKcv9L.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC group regular */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2) \ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO) \ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @} + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Private function prototypes -----------------------------------------------*/ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Exported functions --------------------------------------------------------*/ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup ADC_LL_Exported_Functions + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** @addtogroup ADC_LL_EF_Init + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @{ + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief De-initialize registers of all ADC instances belonging to + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * the same ADC common instance to their default reset values. + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note This function is performing a hard reset, using high level + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * clock source RCC ADC reset. + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADCxy_COMMON ADC common instance + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO + ARM GAS /tmp/ccBKcv9L.s page 5 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval An ErrorStatus enumeration value: + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - SUCCESS: ADC common registers are de-initialized + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - ERROR: not applicable + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 26 .loc 1 210 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB30: + 33 .LBB31: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + ARM GAS /tmp/ccBKcv9L.s page 6 + + + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + ARM GAS /tmp/ccBKcv9L.s page 7 + + + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/ccBKcv9L.s page 8 + + + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + ARM GAS /tmp/ccBKcv9L.s page 9 + + + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + ARM GAS /tmp/ccBKcv9L.s page 10 + + + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccBKcv9L.s page 11 + + + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + ARM GAS /tmp/ccBKcv9L.s page 12 + + + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + ARM GAS /tmp/ccBKcv9L.s page 13 + + + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + ARM GAS /tmp/ccBKcv9L.s page 14 + + + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + ARM GAS /tmp/ccBKcv9L.s page 15 + + + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/ccBKcv9L.s page 16 + + + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/ccBKcv9L.s page 17 + + + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1SMENR, Periphs); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + ARM GAS /tmp/ccBKcv9L.s page 18 + + + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1SMENR, Periphs); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + ARM GAS /tmp/ccBKcv9L.s page 19 + + + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. + ARM GAS /tmp/ccBKcv9L.s page 20 + + + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB2 peripherals reset. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 35 .loc 2 891 0 + 36 0000 054B ldr r3, .L2 + 37 0002 596A ldr r1, [r3, #36] + 38 0004 8022 movs r2, #128 + 39 0006 9200 lsls r2, r2, #2 + 40 0008 0A43 orrs r2, r1 + ARM GAS /tmp/ccBKcv9L.s page 21 + + + 41 000a 5A62 str r2, [r3, #36] + 42 .LVL1: + 43 .LBE31: + 44 .LBE30: + 45 .LBB32: + 46 .LBB33: + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB2 peripherals reset. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 47 .loc 2 918 0 + 48 000c 5A6A ldr r2, [r3, #36] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 5A62 str r2, [r3, #36] + 52 .LVL2: + 53 .LBE33: + 54 .LBE32: + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check the parameters */ + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Force reset of ADC clock (core clock) */ + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Release reset of ADC clock (core clock) */ + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** return SUCCESS; + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 55 .loc 1 221 0 + 56 0014 0120 movs r0, #1 + 57 .LVL3: + 58 @ sp needed + 59 0016 7047 bx lr + ARM GAS /tmp/ccBKcv9L.s page 22 + + + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0018 00100240 .word 1073876992 + 64 001c FFFDFFFF .word -513 + 65 .cfi_endproc + 66 .LFE170: + 68 .section .text.LL_ADC_CommonInit,"ax",%progbits + 69 .align 1 + 70 .global LL_ADC_CommonInit + 71 .syntax unified + 72 .code 16 + 73 .thumb_func + 74 .fpu softvfp + 76 LL_ADC_CommonInit: + 77 .LFB171: + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Initialize some features of ADC common parameters + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (all ADC instances belonging to the same ADC common instance) + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and multimode (for devices with several ADC instances available). + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note The setting of ADC common parameters is conditioned to + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * ADC instances state: + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * All ADC instances belonging to the same ADC common instance + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * must be disabled. + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADCxy_COMMON ADC common instance + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval An ErrorStatus enumeration value: + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - SUCCESS: ADC common registers are initialized + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - ERROR: ADC common registers are not initialized + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_Commo + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 78 .loc 1 239 0 + 79 .cfi_startproc + 80 @ args = 0, pretend = 0, frame = 0 + 81 @ frame_needed = 0, uses_anonymous_args = 0 + 82 @ link register save eliminated. + 83 .LVL4: + 84 .LBB34: + 85 .LBB35: + 86 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @file stm32l0xx_ll_adc.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Header file of ADC LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this list of conditions and the following disclaimer. + ARM GAS /tmp/ccBKcv9L.s page 23 + + + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #ifndef __STM32L0xx_LL_ADC_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __STM32L0xx_LL_ADC_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined (ADC1) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL ADC + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Private constants ---------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Constants ADC Private Constants + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal mask for ADC group regular trigger: */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - regular trigger source */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - regular trigger edge */ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Mask containing trigger source masks for each of possible */ + ARM GAS /tmp/ccBKcv9L.s page 24 + + + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_CFGR1_EXTSEL) << (4U + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_CFGR1_EXTSEL) << (4U + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_CFGR1_EXTSEL) << (4U + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Mask containing trigger edge masks for each of possible */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Definition of ADC group regular trigger bits information. */ + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal mask for ADC channel: */ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - channel identifier defined by number */ + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - channel identifier defined by bitfield */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - channel differentiation between external channels (connected to */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* GPIO pins) and internal channels (connected to internal paths) */ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH) + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MA + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHA + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Channel differentiation between external and internal channels */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Definition of channels ID number information to be inserted into */ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* channels literals definition. */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U) + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_1_NUMBER ( + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_2_NUMBER ( + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_3_NUMBER ( + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 + ARM GAS /tmp/ccBKcv9L.s page 25 + + + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Definition of channels ID bitfield information to be inserted into */ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* channels literals definition. */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18) + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal mask for ADC analog watchdog: */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (concatenation of multiple bits used in different analog watchdogs, */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (feature of several watchdogs not available on all STM32 families)). */ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - analog watchdog 1: monitored channel defined by number, */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* selection of ADC group (ADC group regular). */ + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog channel configuration */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog threshold configuration */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET) + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* ADC registers bits positions */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CFGR1_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CFGR1_AWDSGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_ + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_ + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_ + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_ + ARM GAS /tmp/ccBKcv9L.s page 26 + + + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL10_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL11_BITOFFSET_POS ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL12_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL13_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL14_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL15_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL16_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL17_BITOFFSET_POS ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CHSELR_CHSEL18_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* ADC registers bits groups */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_A + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* ADC internal channels related definitions */ + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Internal voltage reference VrefInt */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FF80078U)) /* Internal voltag + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Temperature sensor */ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if !defined(STM32L011xx) + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FF8007AU)) /* Internal temper + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FF8007EU)) /* Internal temper + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if !defined(STM32L011xx) + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temper + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temper + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(USE_FULL_LL_DRIVER) + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Private macros ------------------------------------------------------------*/ + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Macros ADC Private Macros + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Exported types ------------------------------------------------------------*/ + ARM GAS /tmp/ccBKcv9L.s page 27 + + + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(USE_FULL_LL_DRIVER) + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Structure definition of some features of ADC common parameters + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and multimode + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (all ADC instances belonging to the same ADC common instance). + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is conditioned to ADC instances state (all ADC instances + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * sharing the same ADC common instance): + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * All ADC instances sharing the same ADC common instance must be + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * disabled. + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** typedef struct + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_COMMON + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } LL_ADC_CommonInitTypeDef; + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Structure definition of some features of ADC instance. + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note These parameters have an impact on ADC scope: ADC instance. + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to corresponding unitary functions into + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref ADC_LL_EF_Configuration_ADC_Instance . + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_Init() + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is conditioned to ADC state: + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC instance must be disabled. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This condition is applied to all ADC features, for efficiency + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and compatibility over all STM32 families. However, the different + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * features can be set under different ADC state conditions + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (setting possible with ADC enabled without conversion on going, + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC enabled with conversion on going, ...) + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Each feature can be updated afterwards with a unitary function + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and potentially with ADC in a different state than disabled, + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * refer to description of each function for setting + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conditioned to ADC state. + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** typedef struct + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t Clock; /*!< Set ADC instance clock source and prescaler. + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_CLOCK_ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** @note On this STM32 serie, this parameter has some clo + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC clock synchronous (from PCLK) with prescaler + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (APB prescaler configured inside the RCC must be + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** For more details, refer to description of this functio + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t Resolution; /*!< Set ADC resolution. + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_RESOLU + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + ARM GAS /tmp/ccBKcv9L.s page 28 + + + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_DATA_A + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t LowPowerMode; /*!< Set ADC low power mode. + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_LP_MOD + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } LL_ADC_InitTypeDef; + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Structure definition of some features of ADC group regular. + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note These parameters have an impact on ADC scope: ADC group regular. + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to corresponding unitary functions into + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (functions with prefix "REG"). + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is conditioned to ADC state: + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC instance must be disabled. + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This condition is applied to all ADC features, for efficiency + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and compatibility over all STM32 families. However, the different + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * features can be set under different ADC state conditions + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (setting possible with ADC enabled without conversion on going, + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC enabled with conversion on going, ...) + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Each feature can be updated afterwards with a unitary function + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and potentially with ADC in a different state than disabled, + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * refer to description of each function for setting + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conditioned to ADC state. + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** typedef struct + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: inter + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_TR + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** @note On this STM32 serie, setting trigger source to e + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (default setting for compatibility with some ADC + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** In case of need to modify trigger edge, use func + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: se + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_SE + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** @note This parameter has an effect only if group regul + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (several ADC channels enabled in group regular s + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regula + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_CO + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** Note: It is not possible to enable both ADC group regu + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no tra + ARM GAS /tmp/ccBKcv9L.s page 29 + + + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_DM + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** data preserved or overwritten. + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_OV + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** This feature can be modified afterwards using unitary + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } LL_ADC_REG_InitTypeDef; + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif /* USE_FULL_LL_DRIVER */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Exported constants --------------------------------------------------------*/ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_FLAG ADC flags + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Flags defines which can be used with LL_ADC_ReadReg function + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end o + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end o + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overr + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end o + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 * + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance re + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regul + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regul + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regul + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regul + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_AWD1 ADC_IER_AWDIE /*!< ADC interruption ADC analog watc + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of cali + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* List of ADC registers intended to be used (most commonly) with */ + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* DMA transfer. */ + ARM GAS /tmp/ccBKcv9L.s page 30 + + + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversio + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /* + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /* + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /* + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /* + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /* + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /* + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /* + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /* + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /* + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /* + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /* + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /* + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_FREQ_MODE_HIGH ((uint32_t)0x00000000U)/*!< ADC clock mode to high frequ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low freque + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Other measurement paths to internal channels may be available */ + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (connections to other peripherals). */ + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* If they are not listed below, they do not require any specific */ + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* path enable. In this case, Access to measurement path is done */ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* only by selecting the corresponding ADC internal channel. */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all d + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to inte + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to inte + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VLCD (ADC_CCR_VLCDEN) /*!< ADC measurement path to inte + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /* + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /* + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /* + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC ((uint32_t)0x00000000U) /* + ARM GAS /tmp/ccBKcv9L.s page 31 + + + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignmen + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignmen + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low powe + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power m + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power m + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power m + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (availabl + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< A + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< A + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< A + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< A + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< A + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< A + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< A + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< A + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< A + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< A + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< A + ARM GAS /tmp/ccBKcv9L.s page 32 + + + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< A + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< A + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< A + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< A + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< A + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< A + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< A + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< A + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< A + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< A + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_CHANNEL_VLCD (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< A + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM21_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_ + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM22_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_ + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_ + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXT + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group r + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group r + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group r + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are perform + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are perform + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversion + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion + ARM GAS /tmp/ccBKcv9L.s page 33 + + + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion d + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior i + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior i + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD ((uint32_t)0x00000000U)/*!< ADC group regular sequencer + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /* + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP_0) /* + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_1) /* + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /* + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP_2) /* + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /* + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1) /* + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /* + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + ARM GAS /tmp/ccBKcv9L.s page 34 + + + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_CH_VLCD_REG ((LL_ADC_CHANNEL_VLCD & ADC_CHANNEL_ID_MASK) | ADC + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog thr + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog thr + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog bot + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U) /* + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /* + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)/*!< ADC oversampling discontinuo + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuo + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + ARM GAS /tmp/ccBKcv9L.s page 35 + + + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U) + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U) + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_1 ( + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Only ADC IP HW delays are defined in ADC LL driver driver, + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * not timeout values. + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * For details on delays values, refer to descriptions in source code + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * above each literal definition. + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* not timeout values. */ + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Timeout values for ADC operations are dependent to device clock */ + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* configuration (system clock versus ADC clock), */ + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* and therefore must be defined in user application. */ + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Indications for estimation of ADC timeout delays, for this */ + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* STM32 serie: */ + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - ADC calibration time: maximum delay is 83/fADC. */ + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (refer to device datasheet, parameter "tCAL") */ + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - ADC enable time: maximum delay is 1 conversion cycle. */ + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (refer to device datasheet, parameter "tSTAB") */ + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - ADC disable time: maximum delay should be a few ADC clock cycles */ + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - ADC stop conversion time: maximum delay should be a few ADC clock */ + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* cycles */ + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* - ADC conversion time: duration depending on ADC clock and ADC */ + ARM GAS /tmp/ccBKcv9L.s page 36 + + + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* configuration. */ + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* (refer to device reference manual, section "Timing") */ + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet, */ + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* parameter "tUP_LDO"). */ + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization tim + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay for internal voltage reference stabilization time. */ + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet, */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* parameter "TADC_BUF"). */ + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Unit: us */ + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage refer + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay for temperature sensor stabilization time. */ + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Literal set to maximum value (refer to device datasheet, */ + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* parameter "tSTART"). */ + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Unit: us */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for temperature sensor sta + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Delay required between ADC end of calibration and ADC enable. */ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* are required between ADC end of calibration and ADC enable. */ + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Wait time can be computed in user application by waiting for the */ + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* equivalent number of CPU cycles, by taking into account */ + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* ratio of CPU clock versus ADC clock prescalers. */ + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Unit: ADC clock cycles. */ + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC end o + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Exported macro ------------------------------------------------------------*/ + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Write a value in ADC register + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __INSTANCE__ ADC Instance + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __REG__ Register to be written + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __VALUE__ Value to be written in the register + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + ARM GAS /tmp/ccBKcv9L.s page 37 + + + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Read a value in ADC register + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __INSTANCE__ ADC Instance + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __REG__ Register to be read + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Register value + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to get ADC channel number in decimal format + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from literals LL_ADC_CHANNEL_x. + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Example: + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * will return decimal number "4". + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The input can be a value from functions where a channel + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * number is returned, either defined with number + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or with bitfield (only one bit must be set). + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value between Min_Data=0 and Max_Data=18 + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ? ( + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** : + ARM GAS /tmp/ccBKcv9L.s page 38 + + + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13 + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? ( + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL1 + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSE + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (0U) + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + ARM GAS /tmp/ccBKcv9L.s page 39 + + + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #else + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ? ( + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** : + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13 + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? ( + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL1 + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (0U) + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + ARM GAS /tmp/ccBKcv9L.s page 40 + + + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from number in decimal format. + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Example: + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * will return a data equivalent to "LL_ADC_CHANNEL_4". +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (2) +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1)(2) +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (2) For ADC channel read back from ADC register, +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * comparison with internal channel parameter to be done +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( \ +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \ +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to determine whether the selected channel +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * corresponds to literal definitions of driver. +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The different literal definitions of ADC channels are: +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC internal channel: + ARM GAS /tmp/ccBKcv9L.s page 41 + + +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC external channel (channel connected to a GPIO pin): +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The channel parameter must be a value defined from literal +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...), +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * must not be a value from functions where a channel number is +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * returned from ADC registers, +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * because internal and external channels share the same channel +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * number in ADC registers. The differentiation is made only with +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * parameters definitions of driver. +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values: +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channe +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Value "1" if the channel corresponds to a parameter definition of a ADC internal channe +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to convert a channel defined from parameter +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...), +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * to its equivalent parameter definition of a ADC external channel +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The channel parameter can be, additionally to a value +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * defined from parameter definition of a ADC internal channel +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a value defined from parameter definition of +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or a value from functions where a channel number is returned +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from ADC registers. +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values: + ARM GAS /tmp/ccBKcv9L.s page 42 + + +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to determine whether the internal channel +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * selected is available on the ADC instance selected. +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note The channel parameter must be a value defined from parameter +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...), +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * must not be a value defined from parameter definition of +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or a value from functions where a channel number is + ARM GAS /tmp/ccBKcv9L.s page 43 + + +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * returned from ADC registers, +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * because internal and external channels share the same channel +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * number in ADC registers. The differentiation is made only with +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * parameters definitions of driver. +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_INSTANCE__ ADC instance +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values: +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value "0" if the internal channel selected is not available on the ADC instance selecte +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Value "1" if the internal channel selected is available on the ADC instance selected. +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( \ +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_VLCD) \ +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #else +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ( \ +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to define ADC analog watchdog parameter: +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * define a single channel to monitor with analog watchdog +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from sequencer channel and groups definition. +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_SetAnalogWDMonitChannels( +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC1, LL_ADC_AWD1, +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values: +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) + ARM GAS /tmp/ccBKcv9L.s page 44 + + +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (2) +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1)(2) +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (2) For ADC channel read back from ADC register, +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * comparison with internal channel parameter to be done +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __GROUP__ This parameter can be one of the following values: +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_GROUP_REGULAR +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_DISABLE +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_REG +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_REG +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_REG +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_REG +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_REG +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_REG +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_REG +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_REG +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_REG +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_REG +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_REG +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_REG +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_REG +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_REG +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_REG +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_REG +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (1) +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_REG +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_18_REG +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VREFINT_REG +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VLCD_REG (1) +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to set the value of ADC analog watchdog threshold high +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or low in function of ADC resolution, when ADC resolution is +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * different of 12 bits. +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or @ref LL_ADC_SetAnalogWDThresholds(). +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example, with a ADC resolution of 8 bits, to set the value of +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * analog watchdog threshold high (on 8 bits): +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_SetAnalogWDThresholds +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (< ADCx param >, +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, > (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to get the value of ADC analog watchdog threshold high +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or low in function of ADC resolution, when ADC resolution is +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * different of 12 bits. +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example, with a ADC resolution of 8 bits, to get the value of +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * analog watchdog threshold high (on 8 bits): +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (LL_ADC_RESOLUTION_8B, +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ); +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values: +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to get the ADC analog watchdog threshold high +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or low from raw value containing both thresholds concatenated. +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example, to get analog watchdog threshold high from the register raw value: +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, > ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \ +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) \ +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to select the ADC common instance +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * to which is belonging the selected ADC instance. + ARM GAS /tmp/ccBKcv9L.s page 46 + + +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note ADC common register instance can be used for: +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Set parameters common to several ADC instances +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Multimode (for devices with several ADC instances) +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to functions having argument "ADCxy_COMMON" as parameter. +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADCx__ ADC instance +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval ADC common register instance +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (ADC1_COMMON) +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to check if all ADC instances sharing the same +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC common instance are disabled. +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This check is required by functions with setting conditioned to +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * All ADC instances of the ADC common group must be disabled. +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to functions having argument "ADCxy_COMMON" as parameter. +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On devices with only 1 ADC common instance, parameter of this macro +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is useless and can be ignored (parameter kept for compatibility +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * with devices featuring several ADC common instances). +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADCXY_COMMON__ ADC common instance +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value "0" if all ADC instances sharing the same ADC common instance +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * are disabled. +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Value "1" if at least one ADC instance sharing the same ADC common instance +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is enabled. +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** LL_ADC_IsEnabled(ADC1) +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to define the ADC conversion data full-scale digital +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * value corresponding to the selected ADC resolution. +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note ADC conversion data full-scale corresponds to voltage range +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * determined by analog voltage references Vref+ and Vref- +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (refer to reference manual). +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values: +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval ADC conversion data equivalent voltage value (unit: mVolt) +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to convert the ADC conversion data from +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a resolution to another resolution. +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __DATA__ ADC conversion data to be converted +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This parameter can be one of the following values: +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + ARM GAS /tmp/ccBKcv9L.s page 47 + + +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This parameter can be one of the following values: +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval ADC conversion data to the requested resolution +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TAR +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((__DATA__) \ +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \ +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \ +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to calculate the voltage (unit: mVolt) +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * corresponding to a ADC conversion data (unit: digital value). +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Analog reference voltage (Vref+) must be either known from +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * user board environment or can be calculated using ADC measurement +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (unit: digital value). +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values: +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval ADC conversion data equivalent voltage value (unit: mVolt) +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __ADC_DATA__,\ +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __ADC_RESOLUTION__) \ +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to calculate analog reference voltage (Vref+) +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (unit: mVolt) from ADC conversion data of internal voltage +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * reference VrefInt. +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Computation is using VrefInt calibration value +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * stored in system memory for each device during production. +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This voltage depends on user board environment: voltage level +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * connected to pin Vref+. +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * On devices with small package, the pin Vref+ is not present +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and internally bonded to pin Vdda. +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, calibration data of internal voltage reference +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * VrefInt corresponds to a resolution of 12 bits, +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this is the recommended ADC resolution to convert voltage of +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * internal voltage reference VrefInt. +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Otherwise, this macro performs the processing to scale +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversion data to 12 bits. +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of internal voltage reference VrefInt (unit: digital value). +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values: +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B + ARM GAS /tmp/ccBKcv9L.s page 48 + + +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Analog reference voltage (unit: mV) +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __ADC_RESOLUTION__) \ +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (__ADC_RESOLUTION__), \ +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** LL_ADC_RESOLUTION_12B) \ +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */ +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/ +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */ +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if !defined(STM32L011xx) +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to calculate the temperature (unit: degree Celsius) +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from ADC conversion data of internal temperature sensor. +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Computation is using temperature sensor calibration values +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * stored in system memory for each device during production. +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Calculation formula: +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Temperature = ((TS_ADC_DATA - TS_CAL1) +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * with TS_ADC_DATA = temperature sensor raw data measured by ADC +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Avg_Slope = (TS_CAL2 - TS_CAL1) +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * / (TS_CAL2_TEMP - TS_CAL1_TEMP) +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TS_CAL1 = equivalent TS_ADC_DATA at temperature +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TEMP_DEGC_CAL1 (calibrated in factory) +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TS_CAL2 = equivalent TS_ADC_DATA at temperature +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TEMP_DEGC_CAL2 (calibrated in factory) +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Caution: Calculation relevancy under reserve that calibration +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * parameters are correct (address and data). +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * To calculate temperature using temperature sensor +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * datasheet typical values (generic values less, therefore +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * less accurate than calibrated values), +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note As calculation input, the analog reference voltage (Vref+) must be +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * defined as it impacts the ADC LSB equivalent voltage. +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Analog reference voltage (Vref+) must be either known from +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * user board environment or can be calculated using ADC measurement +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, calibration data of temperature sensor +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * corresponds to a resolution of 12 bits, +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this is the recommended ADC resolution to convert voltage of +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature sensor. +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Otherwise, this macro performs the processing to scale +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversion data to 12 bits. +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature sensor (unit: digital value). +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * sensor voltage has been measured. +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This parameter can be one of the following values: +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B + ARM GAS /tmp/ccBKcv9L.s page 49 + + +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Temperature (unit: degree Celsius) +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __TEMPSENSOR_ADC_DATA__,\ +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __ADC_RESOLUTION__) \ +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (__ADC_RESOLUTION__), \ +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** LL_ADC_RESOLUTION_12B) \ +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (__VREFANALOG_VOLTAGE__)) \ +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** / TEMPSENSOR_CAL_VREFANALOG) \ +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + TEMPSENSOR_CAL1_TEMP \ +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Helper macro to calculate the temperature (unit: degree Celsius) +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * from ADC conversion data of internal temperature sensor. +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Computation is using temperature sensor typical values +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (refer to device datasheet). +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Calculation formula: +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * / Avg_Slope + CALx_TEMP +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * with TS_ADC_DATA = temperature sensor raw data measured by ADC +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (unit: digital value) +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Avg_Slope = temperature sensor slope +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (unit: uV/Degree Celsius) +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TS_TYP_CALx_VOLT = temperature sensor digital value at +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature CALx_TEMP (unit: mV) +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Caution: Calculation relevancy under reserve the temperature sensor +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of the current device has characteristics in line with +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * datasheet typical values. +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * If temperature sensor calibration values are available on +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature calculation will be more accurate using +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note As calculation input, the analog reference voltage (Vref+) must be +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * defined as it impacts the ADC LSB equivalent voltage. +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Analog reference voltage (Vref+) must be either known from +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * user board environment or can be calculated using ADC measurement +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note ADC measurement data must correspond to a resolution of 12bits +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (full scale digital value 4095). If not the case, the data must be +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * preliminarily rescaled to an equivalent resolution of 12 bits. +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical v +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * On STM32L0, refer to device datasheet parameter "Avg_Slop +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * On STM32L0, refer to device datasheet parameter "V130" (c +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature s +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor volta +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This parameter can be one of the following values: + ARM GAS /tmp/ccBKcv9L.s page 50 + + +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Temperature (unit: degree Celsius) +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __TEMPSENSOR_TYP_CALX_V__,\ +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __TEMPSENSOR_CALX_TEMP__,\ +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __VREFANALOG_VOLTAGE__,\ +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __TEMPSENSOR_ADC_DATA__,\ +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __ADC_RESOLUTION__) \ +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ((( ( \ +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 1000) \ +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** - \ +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 1000) \ +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) \ +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) + (__TEMPSENSOR_CALX_TEMP__) \ +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ) +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Exported functions --------------------------------------------------------*/ +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: LL ADC functions to set DMA transfer are located into sections of */ +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* configuration of ADC instance, groups and multimode (if available): */ +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* @ref LL_ADC_REG_SetDMATransfer(), ... */ +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Function to help to configure DMA transfer from ADC: retrieve the +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC register address from ADC instance and a list of ADC registers +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * intended to be used (most commonly) with DMA transfer. +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note These ADC registers are data registers: +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * when ADC conversion data is available in ADC data registers, +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC generates a DMA transfer request. +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This macro is intended to be used with LL DMA driver, refer to +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * function "LL_DMA_ConfigAddresses()". +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_DMA_ConfigAddresses(DMA1, +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_DMA_CHANNEL_1, + ARM GAS /tmp/ccBKcv9L.s page 51 + + +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (uint32_t)&< array or variable >, +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note For devices with several ADC: in multimode, some devices +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use a different data register outside of ADC instance scope +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (common data register). This macro manages this register difference, +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * only ADC instance has to be set as parameter. +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Register This parameter can be one of the following values: +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval ADC register address +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Retrieve address of register DR */ +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)&(ADCx->DR); +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set parameter common to several ADC: Clock source and prescaler. +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * All ADC instances of the ADC common group must be disabled. +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This check can be done with function @ref LL_ADC_IsEnabled() for each +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC instance or by using helper macro helper macro +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR PRESC LL_ADC_SetCommonClock +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param CommonClock This parameter can be one of the following values: +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) ADC common clock asynchonous prescaler is applied to +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * each ADC instance if the corresponding ADC instance clock +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is set to clock source asynchronous. +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (refer to function @ref LL_ADC_SetClock() ). +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None + ARM GAS /tmp/ccBKcv9L.s page 52 + + +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get parameter common to several ADC: Clock source and prescaler. +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR PRESC LL_ADC_GetCommonClock +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) ADC common clock asynchonous prescaler is applied to +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * each ADC instance if the corresponding ADC instance clock +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is set to clock source asynchronous. +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (refer to function @ref LL_ADC_SetClock() ). +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set parameter common to several ADC: Clock low frequency mode. +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual for alignments formats +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR LFMEN LL_ADC_SetCommonFrequencyMode +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Resolution This parameter can be one of the following values: +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Resol +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, Resolution); +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + ARM GAS /tmp/ccBKcv9L.s page 53 + + +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get parameter common to several ADC: Clock low frequency mode. +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual for alignments formats +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR LFMEN LL_ADC_GetCommonFrequencyMode +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON) +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN)); +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set parameter common to several ADC: measurement path to internal +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channels (VrefInt, temperature sensor, ...). +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be selected. +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_PATH_INTERNAL_VREFINT | +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_PATH_INTERNAL_TEMPSENSOR) +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Stabilization time of measurement path to internal channel: +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * After enabling internal paths, before starting ADC conversion, +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a delay is required for internal voltage reference and +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature sensor stabilization time. +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet. +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note ADC internal channel sampling time constraint: +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * For ADC conversion of internal channels, +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a sampling time minimum value is required. +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet. +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * All ADC instances of the ADC common group must be disabled. +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This check can be done with function @ref LL_ADC_IsEnabled() for each +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC instance or by using helper macro helper macro +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CCR TSEN LL_ADC_SetCommonPathInternalCh\n +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CCR VLCDEN LL_ADC_SetCommonPathInternalCh +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param PathInternal This parameter can be a combination of the following values: +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_NONE +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VLCD (*) +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (*) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, ST +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Path +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined (ADC_CCR_VLCDEN) +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal); +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #else + ARM GAS /tmp/ccBKcv9L.s page 54 + + +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get parameter common to several ADC: measurement path to internal +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channels (VrefInt, temperature sensor, ...). +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be selected. +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_PATH_INTERNAL_VREFINT | +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * LL_ADC_PATH_INTERNAL_TEMPSENSOR) +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CCR TSEN LL_ADC_GetCommonPathInternalCh\n +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CCR VLCDEN LL_ADC_GetCommonPathInternalCh +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be a combination of the following values: +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_NONE +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VLCD (*) +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (*) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, ST +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN)); +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #else +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC ins +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC instance clock source and prescaler. +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled. +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 CKMODE LL_ADC_SetClock +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ClockSource This parameter can be one of the following values: +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC (1) +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) Asynchronous clock prescaler can be configured using +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * function @ref LL_ADC_SetCommonClock().\n +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (2) Caution: This parameter has some clock ratio constraints: +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This configuration must be enabled only if PCLK has a 50% + ARM GAS /tmp/ccBKcv9L.s page 55 + + +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * duty clock cycle (APB prescaler configured inside the RCC +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * must be bypassed and the system clock must by 50% duty +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * cycle). +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual. +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC instance clock source and prescaler. +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 CKMODE LL_ADC_GetClock +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CLOCK_ASYNC (1) +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) Asynchronous clock prescaler can be retrieved using +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * function @ref LL_ADC_GetCommonClock().\n +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (2) Caution: This parameter has some clock ratio constraints: +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This configuration must be enabled only if PCLK has a 50% +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * duty clock cycle (APB prescaler configured inside the RCC +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * must be bypassed and the system clock must by 50% duty +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * cycle). +1867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual. +1868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +1870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); +1872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC calibration factor in the mode single-ended +1876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or differential (for devices with differential mode available). +1877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function is intended to set calibration parameters +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * without having to perform a new calibration using +1879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref LL_ADC_StartCalibration(). +1880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be enabled, without calibration on going, without conversion +1883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on going on group regular. +1884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor +1885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F +1887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) +1890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CALFACT, +1892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CALFACT_CALFACT, +1893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** CalibrationFactor); +1894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + ARM GAS /tmp/ccBKcv9L.s page 56 + + +1896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC calibration factor in the mode single-ended +1898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or differential (for devices with differential mode available). +1899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Calibration factors are set by hardware after performing +1900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a calibration run using function @ref LL_ADC_StartCalibration(). +1901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor +1902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x7F +1904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +1906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); +1908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC resolution. +1912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual for alignments formats +1913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. +1914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +1917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +1918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 RES LL_ADC_SetResolution +1919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Resolution This parameter can be one of the following values: +1921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +1928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); +1930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC resolution. +1934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual for alignments formats +1935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. +1936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 RES LL_ADC_GetResolution +1937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B +1940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_10B +1941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_8B +1942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_6B +1943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +1945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); +1947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC conversion data alignment. +1951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Refer to reference manual for alignments formats +1952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. + ARM GAS /tmp/ccBKcv9L.s page 57 + + +1953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +1954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +1955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +1956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +1957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment +1958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param DataAlignment This parameter can be one of the following values: +1960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_RIGHT +1961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_LEFT +1962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +1963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +1965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +1967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC conversion data alignment. +1971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Refer to reference manual for alignments formats +1972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * dependencies to ADC resolutions. +1973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment +1974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +1975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +1976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_RIGHT +1977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_LEFT +1978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +1979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +1980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +1981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +1982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +1983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +1984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +1985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC low power mode. +1986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Description of ADC low power modes: +1987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC low power mode "auto wait": Dynamic low power mode, +1988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions occurrences are limited to the minimum necessary +1989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * in order to reduce power consumption. +1990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * New ADC conversion starts only when the previous +1991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * unitary conversion data (for ADC group regular) +1992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * has been retrieved by user software. +1993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * In the meantime, ADC remains idle: does not performs any +1994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * other conversion. +1995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This mode allows to automatically adapt the ADC conversions +1996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * triggers to the speed of the software that reads the data. +1997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Moreover, this avoids risk of overrun for low frequency +1998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * applications. +1999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * How to use this low power mode: +2000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Do not use with interruption or DMA since these modes +2001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * have to clear immediately the EOC flag to free the +2002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * IRQ vector sequencer. +2003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Do use with polling: 1. Start conversion, +2004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 2. Later on, when conversion data is needed: poll for end of +2005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conversion to ensure that conversion is completed and +2006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * retrieve ADC conversion data. This will trig another +2007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversion start. +2008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC low power mode "auto power-off" (feature available on +2009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): + ARM GAS /tmp/ccBKcv9L.s page 58 + + +2010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the ADC automatically powers-off after a conversion and +2011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * automatically wakes up when a new conversion is triggered +2012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (with startup time between trigger and start of sampling). +2013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This feature can be combined with low power mode "auto wait". +2014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note With ADC low power mode "auto wait", the ADC conversion data read +2015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is corresponding to previous ADC conversion start, independently +2016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of delay during which ADC was idle. +2017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Therefore, the ADC conversion data may be outdated: does not +2018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * correspond to the current voltage level on the selected +2019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC channel. +2020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n +2025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AUTOFF LL_ADC_SetLowPowerMode +2026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param LowPowerMode This parameter can be one of the following values: +2028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_MODE_NONE +2029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOWAIT +2030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOPOWEROFF +2031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF +2032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +2035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); +2037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC low power mode: +2041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Description of ADC low power modes: +2042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC low power mode "auto wait": Dynamic low power mode, +2043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions occurrences are limited to the minimum necessary +2044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * in order to reduce power consumption. +2045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * New ADC conversion starts only when the previous +2046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * unitary conversion data (for ADC group regular) +2047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * has been retrieved by user software. +2048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * In the meantime, ADC remains idle: does not performs any +2049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * other conversion. +2050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This mode allows to automatically adapt the ADC conversions +2051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * triggers to the speed of the software that reads the data. +2052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Moreover, this avoids risk of overrun for low frequency +2053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * applications. +2054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * How to use this low power mode: +2055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Do not use with interruption or DMA since these modes +2056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * have to clear immediately the EOC flag to free the +2057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * IRQ vector sequencer. +2058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Do use with polling: 1. Start conversion, +2059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * 2. Later on, when conversion data is needed: poll for end of +2060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conversion to ensure that conversion is completed and +2061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * retrieve ADC conversion data. This will trig another +2062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversion start. +2063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ADC low power mode "auto power-off" (feature available on +2064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): +2065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the ADC automatically powers-off after a conversion and +2066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * automatically wakes up when a new conversion is triggered + ARM GAS /tmp/ccBKcv9L.s page 59 + + +2067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (with startup time between trigger and start of sampling). +2068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This feature can be combined with low power mode "auto wait". +2069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note With ADC low power mode "auto wait", the ADC conversion data read +2070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is corresponding to previous ADC conversion start, independently +2071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of delay during which ADC was idle. +2072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Therefore, the ADC conversion data may be outdated: does not +2073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * correspond to the current voltage level on the selected +2074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC channel. +2075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n +2076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AUTOFF LL_ADC_GetLowPowerMode +2077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_MODE_NONE +2080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOWAIT +2081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOPOWEROFF +2082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF +2083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +2085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); +2087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set sampling time common to a group of channels. +2091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Unit: ADC clock cycles. +2092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, sampling time scope is on ADC instance: +2093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Sampling time common to all channels. +2094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (on some other STM32 families, sampling time is channel wise) +2095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of internal channel (VrefInt, TempSensor, ...) to be +2096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * converted: +2097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * sampling time constraints must be respected (sampling time can be +2098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * adjusted in function of ADC clock frequency and sampling time +2099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * setting). +2100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet for timings values (parameters TS_vrefint, +2101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TS_temp, ...). +2102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Conversion time is the addition of sampling time and processing time. +2103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * On this STM32 serie, ADC processing time is: +2104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - 12.5 ADC clock cycles at ADC resolution 12 bits +2105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - 10.5 ADC clock cycles at ADC resolution 10 bits +2106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - 8.5 ADC clock cycles at ADC resolution 8 bits +2107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - 6.5 ADC clock cycles at ADC resolution 6 bits +2108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of ADC conversion of internal channel (VrefInt, +2109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * temperature sensor, ...), a sampling time minimum value +2110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is required. +2111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet. +2112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels +2117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param SamplingTime This parameter can be one of the following values: +2119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 +2120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 +2121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 +2122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 +2123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + ARM GAS /tmp/ccBKcv9L.s page 60 + + +2124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 +2125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 +2126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 +2127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime) +2130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime); +2132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get sampling time common to a group of channels. +2136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Unit: ADC clock cycles. +2137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, sampling time scope is on ADC instance: +2138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Sampling time common to all channels. +2139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (on some other STM32 families, sampling time is channel wise) +2140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Conversion time is the addition of sampling time and processing time. +2141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to reference manual for ADC processing time of +2142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * this STM32 serie. +2143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels +2144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 +2147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 +2148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 +2149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 +2150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 +2151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 +2152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 +2153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 +2154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx) +2156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP)); +2158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +2162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: gr +2165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +2166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular conversion trigger source: +2170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * internal (SW start) or from external IP (timer event, +2171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * external interrupt line). +2172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting trigger source to external trigger +2173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * also set trigger polarity to rising edge +2174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (default setting for compatibility with some ADC on other +2175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * STM32 families having this setting set by HW default value). +2176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * In case of need to modify trigger edge, use +2177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * function @ref LL_ADC_REG_SetTriggerEdge(). +2178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer +2179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * depends on timers availability on the selected device. +2180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to + ARM GAS /tmp/ccBKcv9L.s page 61 + + +2181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n +2185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource +2186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param TriggerSource This parameter can be one of the following values: +2188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_SOFTWARE +2189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO +2190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2 +2191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO +2192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 +2193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO +2194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*) +2195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO +2196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 +2197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (*) value not defined in all devices +2199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +2202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +2204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular conversion trigger source: +2208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * internal (SW start) or from external IP (timer event, +2209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * external interrupt line). +2210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To determine whether group regular trigger source is +2211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * internal (SW start) or external, without detail +2212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of which peripheral is selected as external trigger, +2213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (equivalent to +2214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") +2215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. +2216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer +2217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * depends on timers availability on the selected device. +2218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n +2219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource +2220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_SOFTWARE +2223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO +2224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2 +2225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO +2226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 +2227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO +2228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*) +2229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO +2230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 +2231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (*) value not defined in all devices +2233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +2235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); +2237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + ARM GAS /tmp/ccBKcv9L.s page 62 + + +2238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ +2239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ +2240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSE +2241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ +2243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to match with triggers literals definition. */ +2244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return ((TriggerSource +2245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) +2246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) +2247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ); +2248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular conversion trigger source internal (SW start) +2252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** or external. +2253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of group regular trigger source set to external trigger, +2254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * to determine which peripheral is selected as external trigger, +2255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_REG_GetTriggerSource(). +2256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart +2257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value "0" if trigger source external trigger +2259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Value "1" if trigger source SW start. +2260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +2262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)); +2264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular conversion trigger polarity. +2268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Applicable only for trigger source set to external trigger. +2269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge +2274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ExternalTriggerEdge This parameter can be one of the following values: +2276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_RISING +2277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING +2278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING +2279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +2282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +2284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular conversion trigger polarity. +2288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Applicable only for trigger source set to external trigger. +2289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge +2290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_RISING +2293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING +2294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + ARM GAS /tmp/ccBKcv9L.s page 63 + + +2295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +2297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +2299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular sequencer scan direction. +2304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On some other STM32 families, this setting is not available and +2305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the default scan direction is forward. +2306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection +2311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ScanDirection This parameter can be one of the following values: +2313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD +2314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD +2315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection +2318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +2320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular sequencer scan direction. +2324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On some other STM32 families, this setting is not available and +2325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the default scan direction is forward. +2326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection +2327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD +2330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD +2331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +2333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +2335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular sequencer discontinuous mode: +2339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected +2340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * number of ranks. +2341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note It is not possible to enable both ADC group regular +2342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * continuous mode and sequencer discontinuous mode. +2343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n +2348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param SeqDiscont This parameter can be one of the following values: +2350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE +2351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + ARM GAS /tmp/ccBKcv9L.s page 64 + + +2352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +2355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +2357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular sequencer discontinuous mode: +2361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected +2362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * number of ranks. +2363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n +2364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE +2367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK +2368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +2370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +2372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular sequence: channel on rank corresponding to +2376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channel number. +2377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function performs: +2378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Channels ordering into each rank of scan sequence: +2379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * rank of each channel is fixed by channel HW number +2380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). +2381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Set channels selected by overwriting the current sequencer +2382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * configuration. +2383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, ADC group regular sequencer is +2384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * not fully configurable: sequencer length and each rank +2385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * affectation to a channel are fixed by channel HW number. +2386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available. +2387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet for channels availability. +2388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, to measure internal channels (VrefInt, +2389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be +2390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * enabled separately. +2391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). +2392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be selected. +2397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) +2398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n +2399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n +2400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n +2401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n +2402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n +2403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n +2404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n +2405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n +2406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n +2407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n +2408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + ARM GAS /tmp/ccBKcv9L.s page 65 + + +2409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n +2410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n +2411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n +2412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n +2413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n +2414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n +2415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n +2416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels +2417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Channel This parameter can be a combination of the following values: +2419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +2420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +2421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +2422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +2423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +2424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +2425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +2426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +2427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +2428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +2429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +2430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +2431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +2432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +2433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +2434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +2435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +2436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +2437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +2438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +2439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +2440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +2441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +2443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +2446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Parameter "Channel" is used with masks because containing */ +2448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* other bits reserved for other purpose. */ +2449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +2450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Add channel to ADC group regular sequence: channel on rank corresponding to +2454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channel number. +2455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function performs: +2456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Channels ordering into each rank of scan sequence: +2457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * rank of each channel is fixed by channel HW number +2458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). +2459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Set channels selected by adding them to the current sequencer +2460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * configuration. +2461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, ADC group regular sequencer is +2462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * not fully configurable: sequencer length and each rank +2463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * affectation to a channel are fixed by channel HW number. +2464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available. +2465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet for channels availability. + ARM GAS /tmp/ccBKcv9L.s page 66 + + +2466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, to measure internal channels (VrefInt, +2467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be +2468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * enabled separately. +2469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). +2470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be selected. +2475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) +2476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n +2477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n +2478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n +2479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n +2480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n +2481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n +2482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n +2483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n +2484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n +2485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n +2486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n +2487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n +2488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n +2489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n +2490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n +2491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n +2492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n +2493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n +2494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd +2495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Channel This parameter can be a combination of the following values: +2497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +2498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +2499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +2500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +2501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +2502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +2503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +2504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +2505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +2506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +2507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +2508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +2509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +2510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +2511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +2512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +2513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +2514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +2515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +2516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +2517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +2518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +2519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +2521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + ARM GAS /tmp/ccBKcv9L.s page 67 + + +2523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +2524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Parameter "Channel" is used with masks because containing */ +2526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* other bits reserved for other purpose. */ +2527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +2528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to +2532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channel number. +2533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function performs: +2534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Channels ordering into each rank of scan sequence: +2535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * rank of each channel is fixed by channel HW number +2536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). +2537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Set channels selected by removing them to the current sequencer +2538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * configuration. +2539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, ADC group regular sequencer is +2540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * not fully configurable: sequencer length and each rank +2541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * affectation to a channel are fixed by channel HW number. +2542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available. +2543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet for channels availability. +2544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, to measure internal channels (VrefInt, +2545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be +2546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * enabled separately. +2547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). +2548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be selected. +2553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) +2554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n +2555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n +2556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n +2557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n +2558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n +2559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n +2560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n +2561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n +2562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n +2563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n +2564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n +2565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n +2566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n +2567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n +2568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n +2569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n +2570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n +2571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n +2572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem +2573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Channel This parameter can be a combination of the following values: +2575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +2576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +2577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +2578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +2579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 + ARM GAS /tmp/ccBKcv9L.s page 68 + + +2580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +2581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +2582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +2583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +2584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +2585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +2586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +2587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +2588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +2589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +2590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +2591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +2592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +2593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +2594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +2595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +2596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +2597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +2599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +2602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Parameter "Channel" is used with masks because containing */ +2604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* other bits reserved for other purpose. */ +2605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +2606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular sequence: channel on rank corresponding to +2610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * channel number. +2611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function performs: +2612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Channels order reading into each rank of scan sequence: +2613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * rank of each channel is fixed by channel HW number +2614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). +2615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, ADC group regular sequencer is +2616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * not fully configurable: sequencer length and each rank +2617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * affectation to a channel are fixed by channel HW number. +2618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available. +2619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet for channels availability. +2620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, to measure internal channels (VrefInt, +2621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be +2622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * enabled separately. +2623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). +2624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note One or several values can be retrieved. +2629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) +2630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n +2631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n +2632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n +2633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n +2634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n +2635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n +2636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + ARM GAS /tmp/ccBKcv9L.s page 69 + + +2637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n +2638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n +2639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n +2640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n +2641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n +2642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n +2643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n +2644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n +2645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n +2646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n +2647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n +2648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels +2649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be a combination of the following values: +2651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0 +2652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1 +2653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2 +2654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3 +2655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4 +2656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5 +2657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6 +2658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7 +2659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8 +2660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9 +2661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10 +2662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11 +2663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12 +2664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13 +2665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14 +2666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15 +2667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16 (1) +2668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17 +2669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_18 +2670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT +2671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR +2672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VLCD (1) +2673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +2675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +2677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); +2679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_ +2681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_ +2682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_ +2683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_ +2684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_ +2685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_ +2686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_ +2687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_ +2688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_ +2689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_ +2690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_AD +2691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_AD +2692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_AD +2693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_AD + ARM GAS /tmp/ccBKcv9L.s page 70 + + +2694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_AD +2695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_AD +2696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #if defined(ADC_CCR_VLCDEN) +2697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_AD +2698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** #endif +2699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_AD +2700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_AD +2701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ); +2702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC continuous conversion mode on ADC group regular. +2705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Description of ADC continuous conversion mode: +2706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - single mode: one conversion per trigger +2707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - continuous mode: after the first trigger, following +2708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conversions launched successively automatically. +2709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note It is not possible to enable both ADC group regular +2710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * continuous mode and sequencer discontinuous mode. +2711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode +2716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Continuous This parameter can be one of the following values: +2718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_SINGLE +2719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_CONTINUOUS +2720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +2723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +2725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC continuous conversion mode on ADC group regular. +2729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Description of ADC continuous conversion mode: +2730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - single mode: one conversion per trigger +2731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - continuous mode: after the first trigger, following +2732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * conversions launched successively automatically. +2733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode +2734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_SINGLE +2737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_CONTINUOUS +2738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +2740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +2742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular conversion data transfer: no transfer or +2746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * transfer by DMA, and DMA requests mode. +2747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If transfer by DMA selected, specifies the DMA requests +2748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * mode: +2749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Limited mode (One shot mode): DMA transfer requests are stopped +2750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * when number of DMA data transfers (number of + ARM GAS /tmp/ccBKcv9L.s page 71 + + +2751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions) is reached. +2752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode non-circular. +2753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Unlimited mode: DMA transfer requests are unlimited, +2754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * whatever number of DMA data transfers (number of +2755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions). +2756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode circular. +2757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If ADC DMA requests mode is set to unlimited and DMA is set to +2758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * mode non-circular: +2759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * when DMA transfers size will be reached, DMA will stop transfers of +2760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions data ADC will raise an overrun error +2761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (overrun flag and interruption if enabled). +2762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To configure DMA source address (peripheral address), +2763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_DMA_GetRegAddr(). +2764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n +2769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer +2770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param DMATransfer This parameter can be one of the following values: +2772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE +2773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED +2774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED +2775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +2778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +2780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular conversion data transfer: no transfer or +2784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * transfer by DMA, and DMA requests mode. +2785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If transfer by DMA selected, specifies the DMA requests +2786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * mode: +2787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Limited mode (One shot mode): DMA transfer requests are stopped +2788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * when number of DMA data transfers (number of +2789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions) is reached. +2790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode non-circular. +2791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - Unlimited mode: DMA transfer requests are unlimited, +2792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * whatever number of DMA data transfers (number of +2793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions). +2794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode circular. +2795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If ADC DMA requests mode is set to unlimited and DMA is set to +2796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * mode non-circular: +2797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * when DMA transfers size will be reached, DMA will stop transfers of +2798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversions data ADC will raise an overrun error +2799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (overrun flag and interruption if enabled). +2800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note To configure DMA source address (peripheral address), +2801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_DMA_GetRegAddr(). +2802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n +2803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer +2804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE +2807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + ARM GAS /tmp/ccBKcv9L.s page 72 + + +2808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED +2809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +2811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +2813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC group regular behavior in case of overrun: +2817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * data preserved or overwritten. +2818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Compatibility with devices without feature overrun: +2819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * other devices without this feature have a behavior +2820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * equivalent to data overwritten. +2821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * The default setting of overrun is data preserved. +2822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Therefore, for compatibility with all devices, parameter +2823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * overrun should be set to data overwritten. +2824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun +2829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Overrun This parameter can be one of the following values: +2831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED +2832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN +2833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +2836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +2838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular behavior in case of overrun: +2842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * data preserved or overwritten. +2843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun +2844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED +2847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN +2848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +2850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +2852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +2856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: an +2860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +2861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC analog watchdog monitored channels: + ARM GAS /tmp/ccBKcv9L.s page 73 + + +2865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a single channel or all channels, +2866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on ADC group regular. +2867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Once monitored channels are selected, analog watchdog +2868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is enabled. +2869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of need to define a single channel to monitor +2870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * with analog watchdog from sequencer channel definition, +2871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). +2872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, there is only 1 kind of analog watchdog +2873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * instance: +2874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - AWD standard (instance AWD1): +2875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - channels monitored: can monitor 1 channel or all channels. +2876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - groups monitored: ADC group regular. +2877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - resolution: resolution is not limited (corresponds to +2878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC resolution configured). +2879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n +2884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n +2885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels +2886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDChannelGroup This parameter can be one of the following values: +2888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_DISABLE +2889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG +2890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_REG +2891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_REG +2892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_REG +2893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_REG +2894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_REG +2895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_REG +2896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_REG +2897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_REG +2898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_REG +2899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_REG +2900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_REG +2901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_REG +2902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_REG +2903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_REG +2904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_REG +2905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_REG +2906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (1) +2907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_REG +2908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_18_REG +2909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VREFINT_REG +2910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG +2911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VLCD_REG (1) +2912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * +2913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063x +2914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +2915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +2917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR1, +2919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN), +2920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK)); +2921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + ARM GAS /tmp/ccBKcv9L.s page 74 + + +2922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC analog watchdog monitored channel. +2925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Usage of the returned channel number: +2926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - To reinject this channel into another function LL_ADC_xxx: +2927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the returned channel number is only partly formatted on definition +2928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared +2929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * with parts of literals LL_ADC_CHANNEL_x or using +2930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). +2931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Then the selected literal LL_ADC_CHANNEL_x can be used +2932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * as parameter for another function. +2933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - To get the channel number in decimal format: +2934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * process the returned value with the helper macro +2935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). +2936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Applicable only when the analog watchdog is set to monitor +2937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * one channel. +2938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, there is only 1 kind of analog watchdog +2939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * instance: +2940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - AWD standard (instance AWD1): +2941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - channels monitored: can monitor 1 channel or all channels. +2942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - groups monitored: ADC group regular. +2943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - resolution: resolution is not limited (corresponds to +2944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC resolution configured). +2945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +2946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +2947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +2948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +2949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n +2950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n +2951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels +2952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +2953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +2954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_DISABLE +2955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG +2956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_REG +2957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_REG +2958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_REG +2959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_REG +2960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_REG +2961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_REG +2962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_REG +2963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_REG +2964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_REG +2965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_REG +2966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_REG +2967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_REG +2968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_REG +2969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_REG +2970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_REG +2971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_REG +2972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_REG +2973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_REG +2974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_18_REG +2975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +2976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +2977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +2978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | A + ARM GAS /tmp/ccBKcv9L.s page 75 + + +2979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Set variable according to channel definition including channel ID */ +2981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* with bitfield. */ +2982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BI +2983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL +2984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle)); +2986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +2987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +2988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +2989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC analog watchdog thresholds value of both thresholds +2990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * high and low. +2991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If value of only one threshold high or low must be set, +2992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_SetAnalogWDThresholds(). +2993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of ADC resolution different of 12 bits, +2994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * analog watchdog thresholds data require a specific shift. +2995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). +2996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, there is only 1 kind of analog watchdog +2997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * instance: +2998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - AWD standard (instance AWD1): +2999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - channels monitored: can monitor 1 channel or all channels. +3000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - groups monitored: ADC group regular. +3001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - resolution: resolution is not limited (corresponds to +3002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC resolution configured). +3003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +3006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n +3008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TR LT LL_ADC_ConfigAnalogWDThresholds +3009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF +3011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF +3012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighVa +3015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->TR, +3017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_TR_HT | ADC_TR_LT, +3018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue); +3019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC analog watchdog threshold value of threshold +3023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * high or low. +3024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If values of both thresholds high or low must be set, +3025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * use function @ref LL_ADC_ConfigAnalogWDThresholds(). +3026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of ADC resolution different of 12 bits, +3027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * analog watchdog thresholds data require a specific shift. +3028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). +3029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, there is only 1 kind of analog watchdog +3030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * instance: +3031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - AWD standard (instance AWD1): +3032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - channels monitored: can monitor 1 channel or all channels. +3033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - groups monitored: ADC group regular. +3034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - resolution: resolution is not limited (corresponds to +3035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC resolution configured). + ARM GAS /tmp/ccBKcv9L.s page 76 + + +3036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +3039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n +3041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TR LT LL_ADC_SetAnalogWDThresholds +3042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDThresholdsHighLow This parameter can be one of the following values: +3044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH +3045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_THRESHOLD_LOW +3046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF +3047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, +3050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ +3052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ +3053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* high is selected, then data is shifted to LSB. Else(threshold low), */ +3054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* data is not shifted. */ +3055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->TR, +3056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** AWDThresholdsHighLow, +3057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0 +3058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC analog watchdog threshold value of threshold high, +3062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * threshold low or raw data with ADC thresholds high and low +3063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * concatenated. +3064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note If raw data with ADC thresholds high and low is retrieved, +3065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the data of each threshold high or low can be isolated +3066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using helper macro: +3067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). +3068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of ADC resolution different of 12 bits, +3069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * analog watchdog thresholds data require a specific shift. +3070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). +3071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll TR HT LL_ADC_GetAnalogWDThresholds\n +3072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * TR LT LL_ADC_GetAnalogWDThresholds +3073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param AWDThresholdsHighLow This parameter can be one of the following values: +3075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH +3076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_THRESHOLD_LOW +3077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW +3078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +3079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHigh +3081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ +3083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ +3084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* high is selected, then data is shifted to LSB. Else(threshold low or */ +3085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* both thresholds), data is not shifted. */ +3086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->TR, +3087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** (AWDThresholdsHighLow | ADC_TR_LT)) +3088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U)) +3089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ); +3090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** + ARM GAS /tmp/ccBKcv9L.s page 77 + + +3093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +3094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: over +3097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +3098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC oversampling scope. +3102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +3105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope +3107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param OvsScope This parameter can be one of the following values: +3109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_DISABLE +3110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED +3111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) +3114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); +3116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC oversampling scope. +3120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope +3121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +3123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_DISABLE +3124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED +3125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +3127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); +3129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC oversampling discontinuous mode (triggered mode) +3133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on the selected ADC group. +3134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Number of oversampled conversions are done either in: +3135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - continuous mode (all conversions of oversampling ratio +3136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * are done from 1 trigger) +3137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - discontinuous mode (each conversion of oversampling ratio +3138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * needs a trigger) +3139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +3142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont +3144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param OverSamplingDiscont This parameter can be one of the following values: +3146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_REG_CONT +3147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_REG_DISCONT +3148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + ARM GAS /tmp/ccBKcv9L.s page 78 + + +3150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) +3151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); +3153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC oversampling discontinuous mode (triggered mode) +3157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on the selected ADC group. +3158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note Number of oversampled conversions are done either in: +3159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - continuous mode (all conversions of oversampling ratio +3160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * are done from 1 trigger) +3161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - discontinuous mode (each conversion of oversampling ratio +3162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * needs a trigger) +3163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont +3164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Returned value can be one of the following values: +3166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_REG_CONT +3167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_REG_DISCONT +3168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +3170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); +3172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Set ADC oversampling +3176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note This function set the 2 items of oversampling configuration: +3177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - ratio +3178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - shift +3179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be disabled or enabled without conversion on going +3182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n +3184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift +3185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Ratio This parameter can be one of the following values: +3187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_2 +3188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_4 +3189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_8 +3190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_16 +3191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_32 +3192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_64 +3193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_128 +3194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_256 +3195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param Shift This parameter can be one of the following values: +3196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_NONE +3197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 +3198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 +3199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 +3200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 +3201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 +3202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 +3203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 +3204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 +3205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + ARM GAS /tmp/ccBKcv9L.s page 79 + + +3207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_ +3208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); +3210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC oversampling ratio +3214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio +3215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Ratio This parameter can be one of the following values: +3217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_2 +3218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_4 +3219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_8 +3220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_16 +3221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_32 +3222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_64 +3223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_128 +3224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_RATIO_256 +3225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +3227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); +3229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC oversampling shift +3233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift +3234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval Shift This parameter can be one of the following values: +3236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_NONE +3237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 +3238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 +3239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 +3240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 +3241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 +3242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 +3243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 +3244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 +3245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +3247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); +3249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +3253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance +3256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +3257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Enable ADC instance internal voltage regulator. +3261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, there are three possibilities to enable +3262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * the voltage regulator: +3263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - by enabling it manually + ARM GAS /tmp/ccBKcv9L.s page 80 + + +3264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using function @ref LL_ADC_EnableInternalRegulator(). +3265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - by launching a calibration +3266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using function @ref LL_ADC_StartCalibration(). +3267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - by enabling the ADC +3268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * using function @ref LL_ADC_Enable(). +3269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, after ADC internal voltage regulator enable, +3270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * a delay for ADC internal voltage regulator stabilization +3271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is required before performing a ADC calibration or ADC enable. +3272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet, parameter "tUP_LDO". +3273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. +3274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be ADC disabled. +3277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator +3278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +3282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADVREGEN); +3289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Disable ADC internal voltage regulator. +3293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be ADC disabled. +3296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator +3297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) +3301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); +3303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get the selected ADC instance internal voltage regulator state. +3307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled +3308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. +3310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +3312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); +3314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Enable the selected ADC instance. +3318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, after ADC enable, a delay for +3319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC internal analog stabilization is required before performing a +3320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC conversion start. + ARM GAS /tmp/ccBKcv9L.s page 81 + + +3321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to device datasheet, parameter tSTAB. +3322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC +3323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is enabled and when conversion clock is active. +3324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (not only core clock: this ADC has a dual clock domain) +3325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be ADC disabled and ADC internal voltage regulator enabled. +3328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADEN LL_ADC_Enable +3329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +3333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADEN); +3340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Disable the selected ADC instance. +3344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be not disabled. Must be enabled without conversion on going +3347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * on group regular. +3348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADDIS LL_ADC_Disable +3349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +3353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADDIS); +3360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get the selected ADC instance enable state. +3364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC +3365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * is enabled and when conversion clock is active. +3366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (not only core clock: this ADC has a dual clock domain) +3367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADEN LL_ADC_IsEnabled +3368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: ADC is disabled, 1: ADC is enabled. +3370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +3372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); + 87 .loc 3 3373 0 + 88 0000 064B ldr r3, .L7 + 89 0002 9B68 ldr r3, [r3, #8] + 90 .LVL5: + ARM GAS /tmp/ccBKcv9L.s page 82 + + + 91 .LBE35: + 92 .LBE34: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check the parameters */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: Hardware constraint (refer to description of functions */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* "LL_ADC_SetCommonXXX()": */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* On this STM32 serie, setting of these features is conditioned to */ + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC state: */ + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* All ADC instances of the ADC common group must be disabled. */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) + 93 .loc 1 251 0 + 94 0004 DB07 lsls r3, r3, #31 + 95 0006 07D4 bmi .L6 + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Configuration of ADC hierarchical scope: */ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - common to several ADC */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* (all ADC instances belonging to the same ADC common instance) */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC clock (conversion clock) */ + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); + 96 .loc 1 257 0 + 97 0008 0B68 ldr r3, [r1] + 98 .LVL6: + 99 .LBB36: + 100 .LBB37: +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + 101 .loc 3 1671 0 + 102 000a 0268 ldr r2, [r0] + 103 000c 0449 ldr r1, .L7+4 + 104 .LVL7: + 105 000e 0A40 ands r2, r1 + 106 0010 1343 orrs r3, r2 + 107 .LVL8: + 108 0012 0360 str r3, [r0] + 109 .LVL9: + 110 .LBE37: + 111 .LBE36: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 112 .loc 1 240 0 + 113 0014 0120 movs r0, #1 + 114 .LVL10: + 115 .L5: + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** else + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Initialization error: One or several ADC instances belonging to */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* the same ADC common instance are not disabled. */ + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** return status; + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 116 .loc 1 267 0 + 117 @ sp needed + ARM GAS /tmp/ccBKcv9L.s page 83 + + + 118 0016 7047 bx lr + 119 .LVL11: + 120 .L6: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 121 .loc 1 263 0 + 122 0018 0020 movs r0, #0 + 123 .LVL12: + 124 001a FCE7 b .L5 + 125 .L8: + 126 .align 2 + 127 .L7: + 128 001c 00240140 .word 1073816576 + 129 0020 FFFFC3FF .word -3932161 + 130 .cfi_endproc + 131 .LFE171: + 133 .section .text.LL_ADC_CommonStructInit,"ax",%progbits + 134 .align 1 + 135 .global LL_ADC_CommonStructInit + 136 .syntax unified + 137 .code 16 + 138 .thumb_func + 139 .fpu softvfp + 141 LL_ADC_CommonStructInit: + 142 .LFB172: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * whose fields will be set to default values. + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval None + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 143 .loc 1 276 0 + 144 .cfi_startproc + 145 @ args = 0, pretend = 0, frame = 0 + 146 @ frame_needed = 0, uses_anonymous_args = 0 + 147 @ link register save eliminated. + 148 .LVL13: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set ADC_CommonInitStruct fields to default values */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set fields of ADC common */ + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* (all ADC instances belonging to the same ADC common instance) */ + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + 149 .loc 1 280 0 + 150 0000 8023 movs r3, #128 + 151 0002 DB02 lsls r3, r3, #11 + 152 0004 0360 str r3, [r0] + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 153 .loc 1 282 0 + 154 @ sp needed + 155 0006 7047 bx lr + 156 .cfi_endproc + 157 .LFE172: + 159 .section .text.LL_ADC_DeInit,"ax",%progbits + 160 .align 1 + 161 .global LL_ADC_DeInit + ARM GAS /tmp/ccBKcv9L.s page 84 + + + 162 .syntax unified + 163 .code 16 + 164 .thumb_func + 165 .fpu softvfp + 167 LL_ADC_DeInit: + 168 .LFB173: + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief De-initialize registers of the selected ADC instance + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * to their default reset values. + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note To reset all ADC instances quickly (perform a hard reset), + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * use function @ref LL_ADC_CommonDeInit(). + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note If this functions returns error status, it means that ADC instance + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * is in an unknown state. + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * In this case, perform a hard reset using high level + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * clock source RCC ADC reset. + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to function @ref LL_ADC_CommonDeInit(). + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADCx ADC instance + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval An ErrorStatus enumeration value: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - SUCCESS: ADC registers are de-initialized + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - ERROR: ADC registers are not de-initialized + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 169 .loc 1 300 0 + 170 .cfi_startproc + 171 @ args = 0, pretend = 0, frame = 8 + 172 @ frame_needed = 0, uses_anonymous_args = 0 + 173 .LVL14: + 174 0000 10B5 push {r4, lr} + 175 .LCFI0: + 176 .cfi_def_cfa_offset 8 + 177 .cfi_offset 4, -8 + 178 .cfi_offset 14, -4 + 179 0002 82B0 sub sp, sp, #8 + 180 .LCFI1: + 181 .cfi_def_cfa_offset 16 + 182 0004 0300 movs r3, r0 + 183 .LVL15: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** __IO uint32_t timeout_cpu_cycles = 0U; + 184 .loc 1 303 0 + 185 0006 0022 movs r2, #0 + 186 0008 0192 str r2, [sp, #4] + 187 .LVL16: + 188 .LBB38: + 189 .LBB39: + 190 .loc 3 3373 0 + 191 000a 8268 ldr r2, [r0, #8] + 192 .LVL17: + 193 .LBE39: + 194 .LBE38: + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check the parameters */ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + ARM GAS /tmp/ccBKcv9L.s page 85 + + + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Disable ADC instance if not already disabled. */ + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(LL_ADC_IsEnabled(ADCx) == 1U) + 195 .loc 1 309 0 + 196 000c D207 lsls r2, r2, #31 + 197 000e 30D5 bpl .L20 + 198 .LVL18: + 199 .LBB40: + 200 .LBB41: +2203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + 201 .loc 3 2203 0 + 202 0010 C268 ldr r2, [r0, #12] + 203 0012 2F49 ldr r1, .L25 + 204 0014 0A40 ands r2, r1 + 205 0016 C260 str r2, [r0, #12] + 206 .LVL19: + 207 .LBE41: + 208 .LBE40: + 209 .LBB42: + 210 .LBB43: +3374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get the selected ADC instance disable state. +3378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing +3379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: no ADC disable command on going. +3381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +3383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); +3385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Start ADC calibration in the mode single-ended +3389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * or differential (for devices with differential mode available). +3390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, a minimum number of ADC clock cycles +3391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * are required between ADC end of calibration and ADC enable. +3392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. +3393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note In case of usage of ADC with DMA transfer: +3394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * On this STM32 serie, ADC DMA transfer request should be disabled +3395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * during calibration: +3396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Calibration factor is available in data register +3397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * and also transfered by DMA. +3398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * To not insert ADC calibration factor among ADC conversion data +3399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * in array variable, DMA transfer must be disabled during +3400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * calibration. +3401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * (DMA transfer setting backup and disable before calibration, +3402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * DMA transfer setting restore after calibration. +3403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), +3404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @ref LL_ADC_REG_SetDMATransfer() ). +3405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be ADC disabled. +3408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADCAL LL_ADC_StartCalibration +3409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ + ARM GAS /tmp/ccBKcv9L.s page 86 + + +3412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +3413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADCAL); +3420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC calibration state. +3424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing +3425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: calibration complete, 1: calibration in progress. +3427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +3429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); +3431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @} +3435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regu +3438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @{ +3439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Start ADC group regular conversion. +3443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, this function is relevant for both +3444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * internal trigger (SW start) and external trigger: +3445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - If ADC trigger has been set to software start, ADC conversion +3446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * starts immediately. +3447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * - If ADC trigger has been set to external trigger, ADC conversion +3448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * will start at next trigger event (on the selected trigger edge) +3449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * following the ADC start conversion command. +3450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be enabled without conversion on going on group regular, +3453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * without conversion stop command on going on group regular, +3454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * without ADC disable command on going. +3455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADSTART LL_ADC_REG_StartConversion +3456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +3460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADSTART); +3467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** + ARM GAS /tmp/ccBKcv9L.s page 87 + + +3469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Stop ADC group regular conversion. +3471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @note On this STM32 serie, setting of this feature is conditioned to +3472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC state: +3473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * ADC must be enabled with conversion on going on group regular, +3474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * without ADC disable command on going. +3475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADSTP LL_ADC_REG_StopConversion +3476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval None +3478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +3480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* Note: Write register with some additional bits forced to state reset */ +3482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* instead of modifying only the selected bit for this function, */ +3483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /* to not interfere with bits with HW property "rs". */ +3484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** MODIFY_REG(ADCx->CR, +3485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, +3486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_ADSTP); +3487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular conversion state. +3491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing +3492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: no conversion is on going on ADC group regular. +3494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +3496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); + 211 .loc 3 3497 0 + 212 0018 8268 ldr r2, [r0, #8] + 213 .LVL20: + 214 .LBE43: + 215 .LBE42: + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set ADC group regular trigger source to SW start to ensure to not */ + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* have an external trigger event occurring during the conversion stop */ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC disable process. */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Stop potential ADC conversion on going on ADC group regular. */ + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) + 216 .loc 1 317 0 + 217 001a 5207 lsls r2, r2, #29 + 218 001c 08D5 bpl .L12 + 219 .LVL21: + 220 .LBB44: + 221 .LBB45: +3498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } +3499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** +3500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** /** +3501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @brief Get ADC group regular command of conversion stop state +3502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing +3503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @param ADCx ADC instance +3504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** * @retval 0: no command of conversion stop is on going on ADC group regular. +3505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** */ +3506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) + ARM GAS /tmp/ccBKcv9L.s page 88 + + +3507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** { +3508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); + 222 .loc 3 3508 0 + 223 001e 8268 ldr r2, [r0, #8] + 224 .LVL22: + 225 .LBE45: + 226 .LBE44: + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) + 227 .loc 1 319 0 + 228 0020 D206 lsls r2, r2, #27 + 229 0022 05D4 bmi .L12 + 230 .LVL23: + 231 .LBB46: + 232 .LBB47: +3484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, + 233 .loc 3 3484 0 + 234 0024 8268 ldr r2, [r0, #8] + 235 0026 2B49 ldr r1, .L25+4 + 236 0028 0A40 ands r2, r1 + 237 002a 1021 movs r1, #16 + 238 002c 0A43 orrs r2, r1 + 239 002e 8260 str r2, [r0, #8] + 240 .LVL24: + 241 .L12: + 242 .LBE47: + 243 .LBE46: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_ADC_REG_StopConversion(ADCx); + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Wait for ADC conversions are effectively stopped */ + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + 244 .loc 1 326 0 + 245 0030 8022 movs r2, #128 + 246 0032 1202 lsls r2, r2, #8 + 247 0034 0192 str r2, [sp, #4] + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 248 .loc 1 301 0 + 249 0036 0120 movs r0, #1 + 250 .LVL25: + 251 .L13: + 252 .LBB48: + 253 .LBB49: + 254 .loc 3 3508 0 + 255 0038 9A68 ldr r2, [r3, #8] + 256 .LVL26: + 257 .LBE49: + 258 .LBE48: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) + 259 .loc 1 327 0 + 260 003a D206 lsls r2, r2, #27 + 261 003c 06D5 bpl .L24 + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(timeout_cpu_cycles-- == 0U) + 262 .loc 1 329 0 + ARM GAS /tmp/ccBKcv9L.s page 89 + + + 263 003e 019A ldr r2, [sp, #4] + 264 0040 511E subs r1, r2, #1 + 265 0042 0191 str r1, [sp, #4] + 266 0044 002A cmp r2, #0 + 267 0046 F7D1 bne .L13 + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Time-out error */ + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 268 .loc 1 332 0 + 269 0048 0020 movs r0, #0 + 270 .LVL27: + 271 004a F5E7 b .L13 + 272 .LVL28: + 273 .L24: + 274 .LBB50: + 275 .LBB51: +3357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** ADC_CR_BITS_PROPERTY_RS, + 276 .loc 3 3357 0 + 277 004c 9A68 ldr r2, [r3, #8] + 278 004e 2149 ldr r1, .L25+4 + 279 0050 0A40 ands r2, r1 + 280 0052 0221 movs r1, #2 + 281 0054 0A43 orrs r2, r1 + 282 0056 9A60 str r2, [r3, #8] + 283 .LVL29: + 284 .LBE51: + 285 .LBE50: + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Disable the ADC instance */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** LL_ADC_Disable(ADCx); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Wait for ADC instance is effectively disabled */ + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; + 286 .loc 1 340 0 + 287 0058 8022 movs r2, #128 + 288 005a 1202 lsls r2, r2, #8 + 289 005c 0192 str r2, [sp, #4] + 290 .LVL30: + 291 .L16: + 292 .LBB52: + 293 .LBB53: +3384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + 294 .loc 3 3384 0 + 295 005e 9A68 ldr r2, [r3, #8] + 296 .LVL31: + 297 .LBE53: + 298 .LBE52: + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** while (LL_ADC_IsDisableOngoing(ADCx) == 1U) + 299 .loc 1 341 0 + 300 0060 9207 lsls r2, r2, #30 + 301 0062 07D5 bpl .L11 + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(timeout_cpu_cycles-- == 0U) + 302 .loc 1 343 0 + 303 0064 019A ldr r2, [sp, #4] + ARM GAS /tmp/ccBKcv9L.s page 90 + + + 304 0066 511E subs r1, r2, #1 + 305 0068 0191 str r1, [sp, #4] + 306 006a 002A cmp r2, #0 + 307 006c F7D1 bne .L16 + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Time-out error */ + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 308 .loc 1 346 0 + 309 006e 0020 movs r0, #0 + 310 .LVL32: + 311 0070 F5E7 b .L16 + 312 .LVL33: + 313 .L20: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 314 .loc 1 301 0 + 315 0072 0120 movs r0, #1 + 316 .LVL34: + 317 .L11: + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check whether ADC state is compliant with expected state */ + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(READ_BIT(ADCx->CR, + 318 .loc 1 352 0 + 319 0074 9A68 ldr r2, [r3, #8] + 320 0076 1721 movs r1, #23 + 321 0078 1142 tst r1, r2 + 322 007a 27D1 bne .L23 + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ADC_CR_ADSTP | ADC_CR_ADSTART + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CR_ADDIS | ADC_CR_ADEN ) + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ) + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** == 0U) + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ========== Reset ADC registers ========== */ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register IER */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->IER, + 323 .loc 1 360 0 + 324 007c 5968 ldr r1, [r3, #4] + 325 007e 9F24 movs r4, #159 + 326 0080 A143 bics r1, r4 + 327 0082 5960 str r1, [r3, #4] + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( LL_ADC_IT_ADRDY + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_IT_EOC + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_IT_EOS + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_IT_OVR + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_IT_EOSMP + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_IT_AWD1 ) + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register ISR */ + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** SET_BIT(ADCx->ISR, + 328 .loc 1 370 0 + 329 0084 1A68 ldr r2, [r3] + 330 0086 2243 orrs r2, r4 + 331 0088 1A60 str r2, [r3] + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( LL_ADC_FLAG_ADRDY + ARM GAS /tmp/ccBKcv9L.s page 91 + + + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_FLAG_EOC + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_FLAG_EOS + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_FLAG_OVR + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_FLAG_EOSMP + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | LL_ADC_FLAG_AWD1 ) + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register CR */ + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* "read-set": no direct reset applicable. */ + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN); + 332 .loc 1 382 0 + 333 008a 9A68 ldr r2, [r3, #8] + 334 008c 1249 ldr r1, .L25+8 + 335 008e 0A40 ands r2, r1 + 336 0090 9A60 str r2, [r3, #8] + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register CFGR1 */ + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CFGR1, + 337 .loc 1 385 0 + 338 0092 DA68 ldr r2, [r3, #12] + 339 0094 1149 ldr r1, .L25+12 + 340 0096 0A40 ands r2, r1 + 341 0098 DA60 str r2, [r3, #12] + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register CFGR2 */ + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* already done above. */ + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CFGR2, + 342 .loc 1 395 0 + 343 009a 1A69 ldr r2, [r3, #16] + 344 009c 1049 ldr r1, .L25+16 + 345 009e 0A40 ands r2, r1 + 346 00a0 1A61 str r2, [r3, #16] + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ADC_CFGR2_CKMODE + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE ) + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register SMPR */ + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP); + 347 .loc 1 402 0 + 348 00a2 5A69 ldr r2, [r3, #20] + 349 00a4 0721 movs r1, #7 + 350 00a6 8A43 bics r2, r1 + 351 00a8 5A61 str r2, [r3, #20] + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register TR */ + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT); + 352 .loc 1 405 0 + 353 00aa 1A6A ldr r2, [r3, #32] + 354 00ac 0D49 ldr r1, .L25+20 + ARM GAS /tmp/ccBKcv9L.s page 92 + + + 355 00ae 1140 ands r1, r2 + 356 00b0 0D4A ldr r2, .L25+24 + 357 00b2 0A43 orrs r2, r1 + 358 00b4 1A62 str r2, [r3, #32] + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register CHSELR */ + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #if defined(ADC_CCR_VLCDEN) + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CHSELR, + 359 .loc 1 409 0 + 360 00b6 9A6A ldr r2, [r3, #40] + 361 00b8 D20C lsrs r2, r2, #19 + 362 00ba D204 lsls r2, r2, #19 + 363 00bc 9A62 str r2, [r3, #40] + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #else + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CHSELR, + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** #endif + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register DR */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* bits in access mode read only, no direct reset applicable */ + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Reset register CALFACT */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT); + 364 .loc 1 430 0 + 365 00be B421 movs r1, #180 + 366 00c0 5A58 ldr r2, [r3, r1] + 367 00c2 203C subs r4, r4, #32 + 368 00c4 A243 bics r2, r4 + 369 00c6 5A50 str r2, [r3, r1] + 370 .LVL35: + 371 .L19: + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** else + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC instance is in an unknown state */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Need to performing a hard reset of ADC instance, using high level */ + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* clock source RCC ADC reset. */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Caution: On this STM32 serie, if several ADC instances are available */ + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* on the selected device, RCC ADC reset will reset */ + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* all ADC instances belonging to the common ADC instance. */ + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** return status; + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + ARM GAS /tmp/ccBKcv9L.s page 93 + + + 372 .loc 1 445 0 + 373 00c8 02B0 add sp, sp, #8 + 374 @ sp needed + 375 00ca 10BD pop {r4, pc} + 376 .L23: + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 377 .loc 1 441 0 + 378 00cc 0020 movs r0, #0 + 379 .LVL36: + 380 00ce FBE7 b .L19 + 381 .L26: + 382 .align 2 + 383 .L25: + 384 00d0 3FF2FFFF .word -3521 + 385 00d4 E8FFFF7F .word 2147483624 + 386 00d8 FFFFFFEF .word -268435457 + 387 00dc 00023E83 .word -2093088256 + 388 00e0 02FCFF3F .word 1073740802 + 389 00e4 00F000F0 .word -268374016 + 390 00e8 0000FF0F .word 268369920 + 391 .cfi_endproc + 392 .LFE173: + 394 .section .text.LL_ADC_Init,"ax",%progbits + 395 .align 1 + 396 .global LL_ADC_Init + 397 .syntax unified + 398 .code 16 + 399 .thumb_func + 400 .fpu softvfp + 402 LL_ADC_Init: + 403 .LFB174: + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Initialize some features of ADC instance. + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note These parameters have an impact on ADC scope: ADC instance. + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to corresponding unitary functions into + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @ref ADC_LL_EF_Configuration_ADC_Instance . + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note The setting of these parameters by function @ref LL_ADC_Init() + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * is conditioned to ADC state: + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * ADC instance must be disabled. + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * This condition is applied to all ADC features, for efficiency + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and compatibility over all STM32 families. However, the different + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * features can be set under different ADC state conditions + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (setting possible with ADC enabled without conversion on going, + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * ADC enabled with conversion on going, ...) + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Each feature can be updated afterwards with a unitary function + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and potentially with ADC in a different state than disabled, + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * refer to description of each function for setting + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * conditioned to ADC state. + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note After using this function, some other features must be configured + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * using LL unitary functions. + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * The minimum configuration remaining to be done is: + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - Set ADC group regular sequencer: + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * map channel on rank corresponding to channel number. + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - Set ADC channel sampling time + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to function LL_ADC_SetChannelSamplingTime(); + ARM GAS /tmp/ccBKcv9L.s page 94 + + + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADCx ADC instance + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval An ErrorStatus enumeration value: + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - SUCCESS: ADC registers are initialized + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - ERROR: ADC registers are not initialized + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 404 .loc 1 479 0 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 0 + 407 @ frame_needed = 0, uses_anonymous_args = 0 + 408 .LVL37: + 409 0000 10B5 push {r4, lr} + 410 .LCFI2: + 411 .cfi_def_cfa_offset 8 + 412 .cfi_offset 4, -8 + 413 .cfi_offset 14, -4 + 414 .LVL38: + 415 .LBB54: + 416 .LBB55: +3373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + 417 .loc 3 3373 0 + 418 0002 8368 ldr r3, [r0, #8] + 419 .LVL39: + 420 .LBE55: + 421 .LBE54: + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check the parameters */ + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: Hardware constraint (refer to description of this function): */ + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC instance must be disabled. */ + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(LL_ADC_IsEnabled(ADCx) == 0U) + 422 .loc 1 492 0 + 423 0004 DB07 lsls r3, r3, #31 + 424 0006 0BD4 bmi .L29 + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Configuration of ADC hierarchical scope: */ + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - ADC instance */ + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC data resolution */ + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC conversion data alignment */ + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC low power mode */ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** MODIFY_REG(ADCx->CFGR1, + 425 .loc 1 499 0 + 426 0008 C368 ldr r3, [r0, #12] + 427 000a 064A ldr r2, .L30 + 428 000c 1340 ands r3, r2 + 429 000e 4A68 ldr r2, [r1, #4] + 430 0010 8C68 ldr r4, [r1, #8] + 431 0012 2243 orrs r2, r4 + ARM GAS /tmp/ccBKcv9L.s page 95 + + + 432 0014 C968 ldr r1, [r1, #12] + 433 .LVL40: + 434 0016 0A43 orrs r2, r1 + 435 0018 1343 orrs r3, r2 + 436 001a C360 str r3, [r0, #12] + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 437 .loc 1 480 0 + 438 001c 0120 movs r0, #1 + 439 .LVL41: + 440 .L28: + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_CFGR1_RES + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_ALIGN + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_WAIT + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_AUTOFF + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** , + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_InitStruct->Resolution + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_InitStruct->DataAlignment + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_InitStruct->LowPowerMode + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** else + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Initialization error: ADC instance is not disabled. */ + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** return status; + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 441 .loc 1 517 0 + 442 @ sp needed + 443 001e 10BD pop {r4, pc} + 444 .LVL42: + 445 .L29: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 446 .loc 1 514 0 + 447 0020 0020 movs r0, #0 + 448 .LVL43: + 449 0022 FCE7 b .L28 + 450 .L31: + 451 .align 2 + 452 .L30: + 453 0024 C73FFFFF .word -49209 + 454 .cfi_endproc + 455 .LFE174: + 457 .section .text.LL_ADC_StructInit,"ax",%progbits + 458 .align 1 + 459 .global LL_ADC_StructInit + 460 .syntax unified + 461 .code 16 + 462 .thumb_func + 463 .fpu softvfp + 465 LL_ADC_StructInit: + 466 .LFB175: + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + ARM GAS /tmp/ccBKcv9L.s page 96 + + + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * whose fields will be set to default values. + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval None + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 467 .loc 1 526 0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 0 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 471 @ link register save eliminated. + 472 .LVL44: + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set ADC_InitStruct fields to default values */ + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set fields of ADC instance */ + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + 473 .loc 1 529 0 + 474 0000 8023 movs r3, #128 + 475 0002 DB05 lsls r3, r3, #23 + 476 0004 0360 str r3, [r0] + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + 477 .loc 1 530 0 + 478 0006 0023 movs r3, #0 + 479 0008 4360 str r3, [r0, #4] + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + 480 .loc 1 531 0 + 481 000a 8360 str r3, [r0, #8] + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + 482 .loc 1 532 0 + 483 000c C360 str r3, [r0, #12] + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 484 .loc 1 534 0 + 485 @ sp needed + 486 000e 7047 bx lr + 487 .cfi_endproc + 488 .LFE175: + 490 .section .text.LL_ADC_REG_Init,"ax",%progbits + 491 .align 1 + 492 .global LL_ADC_REG_Init + 493 .syntax unified + 494 .code 16 + 495 .thumb_func + 496 .fpu softvfp + 498 LL_ADC_REG_Init: + 499 .LFB176: + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Initialize some features of ADC group regular. + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note These parameters have an impact on ADC scope: ADC group regular. + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to corresponding unitary functions into + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (functions with prefix "REG"). + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note The setting of these parameters by function @ref LL_ADC_Init() + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * is conditioned to ADC state: + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * ADC instance must be disabled. + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * This condition is applied to all ADC features, for efficiency + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and compatibility over all STM32 families. However, the different + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * features can be set under different ADC state conditions + ARM GAS /tmp/ccBKcv9L.s page 97 + + + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * (setting possible with ADC enabled without conversion on going, + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * ADC enabled with conversion on going, ...) + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Each feature can be updated afterwards with a unitary function + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * and potentially with ADC in a different state than disabled, + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * refer to description of each function for setting + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * conditioned to ADC state. + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @note After using this function, other features must be configured + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * using LL unitary functions. + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * The minimum configuration remaining to be done is: + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - Set ADC group regular sequencer: + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * map channel on rank corresponding to channel number. + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - Set ADC channel sampling time + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * Refer to function LL_ADC_SetChannelSamplingTime(); + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADCx ADC instance + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval An ErrorStatus enumeration value: + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - SUCCESS: ADC registers are initialized + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * - ERROR: ADC registers are not initialized + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 500 .loc 1 569 0 + 501 .cfi_startproc + 502 @ args = 0, pretend = 0, frame = 0 + 503 @ frame_needed = 0, uses_anonymous_args = 0 + 504 .LVL45: + 505 0000 10B5 push {r4, lr} + 506 .LCFI3: + 507 .cfi_def_cfa_offset 8 + 508 .cfi_offset 4, -8 + 509 .cfi_offset 14, -4 + 510 .LVL46: + 511 .LBB56: + 512 .LBB57: +3373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h **** } + 513 .loc 3 3373 0 + 514 0002 8368 ldr r3, [r0, #8] + 515 .LVL47: + 516 .LBE57: + 517 .LBE56: + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Check the parameters */ + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: Hardware constraint (refer to description of this function): */ + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* ADC instance must be disabled. */ + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** if(LL_ADC_IsEnabled(ADCx) == 0U) + 518 .loc 1 582 0 + 519 0004 DB07 lsls r3, r3, #31 + 520 0006 0FD4 bmi .L35 + ARM GAS /tmp/ccBKcv9L.s page 98 + + + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Configuration of ADC hierarchical scope: */ + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - ADC group regular */ + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC group regular trigger source */ + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC group regular sequencer discontinuous mode */ + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC group regular continuous mode */ + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC group regular conversion data transfer: no transfer or */ + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* transfer by DMA, and DMA requests mode */ + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* - Set ADC group regular overrun behavior */ + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* setting of trigger source to SW start. */ + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** MODIFY_REG(ADCx->CFGR1, + 521 .loc 1 594 0 + 522 0008 C368 ldr r3, [r0, #12] + 523 000a 084A ldr r2, .L36 + 524 000c 1A40 ands r2, r3 + 525 000e 0B68 ldr r3, [r1] + 526 0010 4C68 ldr r4, [r1, #4] + 527 0012 2343 orrs r3, r4 + 528 0014 8C68 ldr r4, [r1, #8] + 529 0016 2343 orrs r3, r4 + 530 0018 CC68 ldr r4, [r1, #12] + 531 001a 2343 orrs r3, r4 + 532 001c 0969 ldr r1, [r1, #16] + 533 .LVL48: + 534 001e 0B43 orrs r3, r1 + 535 0020 1343 orrs r3, r2 + 536 0022 C360 str r3, [r0, #12] + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ErrorStatus status = SUCCESS; + 537 .loc 1 570 0 + 538 0024 0120 movs r0, #1 + 539 .LVL49: + 540 .L34: + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_CFGR1_EXTSEL + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_EXTEN + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_DISCEN + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_CONT + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_DMAEN + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_DMACFG + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_CFGR1_OVRMOD + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** , + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->TriggerSource + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_REG_InitStruct->SequencerDiscont + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_REG_InitStruct->ContinuousMode + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_REG_InitStruct->DMATransfer + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** | ADC_REG_InitStruct->Overrun + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ); + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** else + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Initialization error: ADC instance is not disabled. */ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** status = ERROR; + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** return status; + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 541 .loc 1 617 0 + ARM GAS /tmp/ccBKcv9L.s page 99 + + + 542 @ sp needed + 543 0026 10BD pop {r4, pc} + 544 .LVL50: + 545 .L35: + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 546 .loc 1 614 0 + 547 0028 0020 movs r0, #0 + 548 .LVL51: + 549 002a FCE7 b .L34 + 550 .L37: + 551 .align 2 + 552 .L36: + 553 002c 3CC2FEFF .word -81348 + 554 .cfi_endproc + 555 .LFE176: + 557 .section .text.LL_ADC_REG_StructInit,"ax",%progbits + 558 .align 1 + 559 .global LL_ADC_REG_StructInit + 560 .syntax unified + 561 .code 16 + 562 .thumb_func + 563 .fpu softvfp + 565 LL_ADC_REG_StructInit: + 566 .LFB177: + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /** + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * whose fields will be set to default values. + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** * @retval None + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** */ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** { + 567 .loc 1 626 0 + 568 .cfi_startproc + 569 @ args = 0, pretend = 0, frame = 0 + 570 @ frame_needed = 0, uses_anonymous_args = 0 + 571 @ link register save eliminated. + 572 .LVL52: + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set ADC_REG_InitStruct fields to default values */ + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Set fields of ADC group regular */ + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** /* setting of trigger source to SW start. */ + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + 573 .loc 1 631 0 + 574 0000 0023 movs r3, #0 + 575 0002 0360 str r3, [r0] + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + 576 .loc 1 632 0 + 577 0004 4360 str r3, [r0, #4] + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + 578 .loc 1 633 0 + 579 0006 8360 str r3, [r0, #8] + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + 580 .loc 1 634 0 + 581 0008 C360 str r3, [r0, #12] + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; + ARM GAS /tmp/ccBKcv9L.s page 100 + + + 582 .loc 1 635 0 + 583 000a 8023 movs r3, #128 + 584 000c 5B01 lsls r3, r3, #5 + 585 000e 0361 str r3, [r0, #16] + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c **** } + 586 .loc 1 636 0 + 587 @ sp needed + 588 0010 7047 bx lr + 589 .cfi_endproc + 590 .LFE177: + 592 .text + 593 .Letext0: + 594 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 595 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 596 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 597 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 598 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 599 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 600 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 601 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 602 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccBKcv9L.s page 101 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_adc.c + /tmp/ccBKcv9L.s:16 .text.LL_ADC_CommonDeInit:0000000000000000 $t + /tmp/ccBKcv9L.s:23 .text.LL_ADC_CommonDeInit:0000000000000000 LL_ADC_CommonDeInit + /tmp/ccBKcv9L.s:63 .text.LL_ADC_CommonDeInit:0000000000000018 $d + /tmp/ccBKcv9L.s:69 .text.LL_ADC_CommonInit:0000000000000000 $t + /tmp/ccBKcv9L.s:76 .text.LL_ADC_CommonInit:0000000000000000 LL_ADC_CommonInit + /tmp/ccBKcv9L.s:128 .text.LL_ADC_CommonInit:000000000000001c $d + /tmp/ccBKcv9L.s:134 .text.LL_ADC_CommonStructInit:0000000000000000 $t + /tmp/ccBKcv9L.s:141 .text.LL_ADC_CommonStructInit:0000000000000000 LL_ADC_CommonStructInit + /tmp/ccBKcv9L.s:160 .text.LL_ADC_DeInit:0000000000000000 $t + /tmp/ccBKcv9L.s:167 .text.LL_ADC_DeInit:0000000000000000 LL_ADC_DeInit + /tmp/ccBKcv9L.s:384 .text.LL_ADC_DeInit:00000000000000d0 $d + /tmp/ccBKcv9L.s:395 .text.LL_ADC_Init:0000000000000000 $t + /tmp/ccBKcv9L.s:402 .text.LL_ADC_Init:0000000000000000 LL_ADC_Init + /tmp/ccBKcv9L.s:453 .text.LL_ADC_Init:0000000000000024 $d + /tmp/ccBKcv9L.s:458 .text.LL_ADC_StructInit:0000000000000000 $t + /tmp/ccBKcv9L.s:465 .text.LL_ADC_StructInit:0000000000000000 LL_ADC_StructInit + /tmp/ccBKcv9L.s:491 .text.LL_ADC_REG_Init:0000000000000000 $t + /tmp/ccBKcv9L.s:498 .text.LL_ADC_REG_Init:0000000000000000 LL_ADC_REG_Init + /tmp/ccBKcv9L.s:553 .text.LL_ADC_REG_Init:000000000000002c $d + /tmp/ccBKcv9L.s:558 .text.LL_ADC_REG_StructInit:0000000000000000 $t + /tmp/ccBKcv9L.s:565 .text.LL_ADC_REG_StructInit:0000000000000000 LL_ADC_REG_StructInit + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_comp.d b/build/stm32l0xx_ll_comp.d new file mode 100644 index 0000000..87ac0e0 --- /dev/null +++ b/build/stm32l0xx_ll_comp.d @@ -0,0 +1,106 @@ +build/stm32l0xx_ll_comp.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_ll_comp.lst b/build/stm32l0xx_ll_comp.lst new file mode 100644 index 0000000..8fd7644 --- /dev/null +++ b/build/stm32l0xx_ll_comp.lst @@ -0,0 +1,1249 @@ +ARM GAS /tmp/ccwmSZef.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_comp.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_COMP_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_COMP_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_COMP_DeInit: + 24 .LFB58: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @file stm32l0xx_ll_comp.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @brief COMP LL module driver + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ****************************************************************************** + ARM GAS /tmp/ccwmSZef.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #include "stm32l0xx_ll_comp.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #ifdef USE_FULL_ASSERT + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #include "stm32_assert.h" + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #else + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define assert_param(expr) ((void)0U) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #endif + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** @addtogroup STM32L0xx_LL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #if defined (COMP1) || defined (COMP2) + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** @addtogroup COMP_LL COMP + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Private types -------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Private constants ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Private macros ------------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** @addtogroup COMP_LL_Private_Macros + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @{ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Check of parameters for configuration of COMP hierarchical scope: */ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* COMP instance. */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #if defined (STM32L011xx) || defined (STM32L021xx) + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** (((__COMP_INSTANCE__) == COMP1) \ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ? ( \ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1 \ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** : \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5) \ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6) \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #else + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + ARM GAS /tmp/ccwmSZef.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** (((__COMP_INSTANCE__) == COMP1) \ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ? ( \ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1 \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** : \ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #endif + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Note: On this STM32 serie, comparator input minus parameters are */ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* the different depending on COMP instances. */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** (((__COMP_INSTANCE__) == COMP1) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ? ( \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** : \ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( \ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) \ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @} + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Private function prototypes -----------------------------------------------*/ + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Exported functions --------------------------------------------------------*/ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** @addtogroup COMP_LL_Exported_Functions + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @{ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** @addtogroup COMP_LL_EF_Init + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @{ + ARM GAS /tmp/ccwmSZef.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @brief De-initialize registers of the selected COMP instance + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * to their default reset values. + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @note If comparator is locked, de-initialization by software is + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * not possible. + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * The only way to unlock the comparator is a device hardware reset. + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @param COMPx COMP instance + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @retval An ErrorStatus enumeration value: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * - SUCCESS: COMP registers are de-initialized + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * - ERROR: COMP registers are not de-initialized + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 26 .loc 1 162 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB6: + 33 .LBB7: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @file stm32l0xx_ll_comp.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Header file of COMP LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** ****************************************************************************** + ARM GAS /tmp/ccwmSZef.s page 5 + + + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #ifndef __STM32L0xx_LL_COMP_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define __STM32L0xx_LL_COMP_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #if defined (COMP1) || defined (COMP2) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL COMP + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_Private_Constants COMP Private Constants + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* COMP registers bits positions */ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Private macros ------------------------------------------------------------*/ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Exported types ------------------------------------------------------------*/ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #if defined(USE_FULL_LL_DRIVER) + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Structure definition of some features of COMP instance. + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** typedef struct + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and spee + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This parameter can be a value of @ref COMP_LL_EC_POWER + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This feature can be modified afterwards using unitary + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This parameter can be a value of @ref COMP_LL_EC_INPUT + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + ARM GAS /tmp/ccwmSZef.s page 6 + + + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This feature can be modified afterwards using unitary + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** uint32_t InputMinus; /*!< Set comparator input minus (inverting input). + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This parameter can be a value of @ref COMP_LL_EC_INPUT + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This feature can be modified afterwards using unitary + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** uint32_t OutputPolarity; /*!< Set comparator output polarity. + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This parameter can be a value of @ref COMP_LL_EC_OUTPU + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** This feature can be modified afterwards using unitary + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } LL_COMP_InitTypeDef; + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #endif /* USE_FULL_LL_DRIVER */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Exported constants --------------------------------------------------------*/ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM) /*!< Window mode enable: + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_POWERMODE_ULTRALOWPOWER ((uint32_t)0x00000000U) /*!< COMP power mode to low s + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP2SPEED) /*!< COMP power mode to fast + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Com + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMP2INPSEL_0) /*!< Com + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_COMP2INPSEL_1) /*!< Com + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO4 (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1) /*!< Com + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO5 (COMP_CSR_COMP2INPSEL_2) /*!< Com + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #if defined (STM32L011xx) || defined (STM32L021xx) + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_PLUS_IO6 (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0) /*!< Com + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #endif + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + ARM GAS /tmp/ccwmSZef.s page 7 + + + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_1_4VREFINT (COMP_CSR_COMP2INNSEL_2 + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_1_2VREFINT (COMP_CSR_COMP2INNSEL_2 | COMP_CSR + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_3_4VREFINT (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_VREFINT ((uint32_t)0x00000000U) + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_COMP2INNSEL_1 + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_COMP2INNSEL_1 | COMP_CSR + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_OUTPUT_SELECTION_LPTIM Comparator output - Output selection specific to LP + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (COMP_CSR_COMP1LPTIM1IN1) + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (COMP_CSR_COMP2LPTIM1IN1) + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (COMP_CSR_COMP2LPTIM1IN2) + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not i + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POLARITY) /*!< COMP output polarity is inver + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (i + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high ( + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Only COMP IP HW delays are defined in COMP LL driver driver, + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * not timeout values. + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * For details on delays values, refer to descriptions in source code + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * above each literal definition. + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Delay for comparator startup time. */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Note: Delay required to reach propagation delay specification. */ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Literal set to maximum value (refer to device datasheet, */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* parameter "tSTART"). */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Unit: us */ + ARM GAS /tmp/ccwmSZef.s page 8 + + + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_DELAY_STARTUP_US ((uint32_t) 25U) /*!< Delay for COMP startup time */ + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Delay for comparator voltage scaler stabilization time */ + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* (voltage from VrefInt, delay based on VrefInt startup time). */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Literal set to maximum value (refer to device datasheet, */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* parameter "TVREFINT"). */ + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Unit: us */ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U) /*!< Delay for COMP voltage scaler + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Exported macro ------------------------------------------------------------*/ + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Write a value in COMP register + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __INSTANCE__ comparator instance + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __REG__ Register to be written + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __VALUE__ Value to be written in the register + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Read a value in COMP register + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __INSTANCE__ comparator instance + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __REG__ Register to be read + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Register value + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Helper macro to select the COMP common instance + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * to which is belonging the selected COMP instance. + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note COMP common register instance can be used to + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * set parameters common to several COMP instances. + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Refer to functions having argument "COMPxy_COMMON" as parameter. + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param __COMPx__ COMP instance + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval COMP common instance or value "0" if there is no COMP common instance. + ARM GAS /tmp/ccwmSZef.s page 9 + + + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** (COMP12_COMMON) + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /* Exported functions --------------------------------------------------------*/ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set window mode of a pair of comparators instances + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (2 consecutive COMP instances odd and even COMP and COMP). + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1WM LL_COMP_SetCommonWindowMode + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPxy_COMMON Comparator common instance + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMM + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param WindowMode This parameter can be one of the following values: + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_WINDOWMODE_DISABLE + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t Windo + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM, WindowMode); + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get window mode of a pair of comparators instances + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (2 consecutive COMP instances odd and even COMP and COMP). + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1WM LL_COMP_GetCommonWindowMode + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPxy_COMMON Comparator common instance + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMM + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_WINDOWMODE_DISABLE + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM)); + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes + ARM GAS /tmp/ccwmSZef.s page 10 + + + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator instance operating mode to adjust power and speed. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP2_CSR COMP2SPEED LL_COMP_SetPowerMode + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param PowerMode This parameter can be one of the following values: + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1) + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (1) Available only on COMP instance: COMP2. + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode) + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2SPEED, PowerMode); + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator instance operating mode to adjust power and speed. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Available only on COMP instance: COMP2. + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP2_CSR COMP2SPEED LL_COMP_GetPowerMode\n + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1) + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (1) Available only on COMP instance: COMP2. + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2SPEED)); + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator inputs minus (inverting) and plus (non-inverting). + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note This function shall only be used for COMP2. + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * For setting COMP1 input it is recommended to use LL_COMP_SetInputMinus() + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Plus (non-inverting) input is not configurable on COMP1. + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Using this function for COMP1 will corrupt COMP1WM register + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note On this STM32 serie, specificity if using COMP instance COMP2 + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * with COMP input based on VrefInt (VrefInt or subdivision + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * of VrefInt): scaler bridge is based on VrefInt and requires + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * to enable path from VrefInt (refer to literal + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP). + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP2_CSR COMP2INNSEL LL_COMP_ConfigInputs\n + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2INPSEL LL_COMP_ConfigInputs + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + ARM GAS /tmp/ccwmSZef.s page 11 + + + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param InputMinus This parameter can be one of the following values: + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO1 + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO2 + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param InputPlus This parameter can be one of the following values: + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO3 (1) + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO4 (1) + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO5 (1) + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (1) Available only on COMP instance: COMP2. + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (2) Available only on devices STM32L0 category 1. + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputP + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** COMP_CSR_COMP2INNSEL | COMP_CSR_COMP2INPSEL, + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** InputMinus | InputPlus); + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator input plus (non-inverting). + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Only COMP2 allows to set the input plus (non-inverting). + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * For COMP1 it is always PA1 IO, except when Windows Mode is selected. + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP2_CSR COMP2INPSEL LL_COMP_SetInputPlus + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param InputPlus This parameter can be one of the following values: + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO3 (1) + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO4 (1) + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO5 (1) + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2) + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (1) Available only on COMP instance: COMP2. + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (2) Available only on devices STM32L0 category 1. + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus) + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INPSEL, InputPlus); + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator input plus (non-inverting). + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Only COMP2 allows to set the input plus (non-inverting). + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * For COMP1 it is always PA1 IO, except when Windows Mode is selected. + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP2_CSR COMP2INPSEL LL_COMP_GetInputPlus + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + ARM GAS /tmp/ccwmSZef.s page 12 + + + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO3 (1) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO4 (1) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO5 (1) + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (1) Available only on COMP instance: COMP2. + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (2) Available only on devices STM32L0 category 1. + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INPSEL)); + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator input minus (inverting). + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note In case of comparator input selected to be connected to IO: + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * GPIO pins are specific to each comparator instance. + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Refer to description of parameters or to reference manual. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note On this STM32 serie, specificity if using COMP instance COMP2 + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * with COMP input based on VrefInt (VrefInt or subdivision + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * of VrefInt): scaler bridge is based on VrefInt and requires + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * to enable path from VrefInt (refer to literal + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP). + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1INNSEL LL_COMP_SetInputMinus\n + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2INNSEL LL_COMP_SetInputMinus + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param InputMinus This parameter can be one of the following values: + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO1 + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*) + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*) + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*) + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO2 (*) + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (*) Available only on COMP instance: COMP2. + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus) + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INNSEL, InputMinus); + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator input minus (inverting). + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note In case of comparator input selected to be connected to IO: + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * GPIO pins are specific to each comparator instance. + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Refer to description of parameters or to reference manual. + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1INNSEL LL_COMP_GetInputMinus\n + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2INNSEL LL_COMP_GetInputMinus + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + ARM GAS /tmp/ccwmSZef.s page 13 + + + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO1 + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*) + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*) + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_INPUT_MINUS_IO2 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (*) Available only on COMP instance: COMP2. + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INNSEL)); + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator output LPTIM. + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_SetOutputLPTIM\n + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LPTIMIN1 LL_COMP_SetOutputLPTIM\n + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LPTIMIN2 LL_COMP_SetOutputLPTIM + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param OutputLptim This parameter can be one of the following values: + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*) + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**) + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**) + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (*) Available only on COMP instance: COMP1.\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (**) Available only on COMP instance: COMP2. + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetOutputLPTIM(COMP_TypeDef *COMPx, uint32_t OutputLptim) + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1I + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator output LPTIM. + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_GetOutputLPTIM\n + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LPTIMIN1 LL_COMP_GetOutputLPTIM\n + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LPTIMIN2 LL_COMP_GetOutputLPTIM + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**) + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (*) Available only on COMP instance: COMP1.\n + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (**) Available only on COMP instance: COMP2. + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + ARM GAS /tmp/ccwmSZef.s page 14 + + + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetOutputLPTIM(COMP_TypeDef *COMPx) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_ + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Set comparator instance output polarity. + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP COMP1POLARITY LL_COMP_SetOutputPolarity + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param OutputPolarity This parameter can be one of the following values: + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity) + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOLARITY, OutputPolarity); + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator instance output polarity. + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP COMP1POLARITY LL_COMP_GetOutputPolarity + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval Returned value can be one of the following values: + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOLARITY)); + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @} + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** @defgroup COMP_LL_EF_Operation Operation on comparator instance + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @{ + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Enable comparator instance. + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note After enable from off state, comparator requires a delay + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * to reach reach propagation delay specification. + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * Refer to device datasheet, parameter "tSTART". + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1EN LL_COMP_Enable\n + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2EN LL_COMP_Enable + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN); + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Disable comparator instance. + ARM GAS /tmp/ccwmSZef.s page 15 + + + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1EN LL_COMP_Disable\n + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2EN LL_COMP_Disable + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN); + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator enable state + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (0: COMP is disabled, 1: COMP is enabled) + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1EN LL_COMP_IsEnabled\n + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2EN LL_COMP_IsEnabled + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval State of bit (1 or 0). + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN)); + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Lock comparator instance. + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Once locked, comparator configuration can be accessed in read-only. + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note The only way to unlock the comparator is a device hardware reset. + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1LOCK LL_COMP_Lock\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LOCK LL_COMP_Lock + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval None + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK); + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** } + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** /** + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @brief Get comparator lock state + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * (0: COMP is unlocked, 1: COMP is locked). + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note Once locked, comparator configuration can be accessed in read-only. + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @note The only way to unlock the comparator is a device hardware reset. + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @rmtoll COMP1_CSR COMP1LOCK LL_COMP_IsLocked\n + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * COMP2_CSR COMP2LOCK LL_COMP_IsLocked + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @param COMPx Comparator instance + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** * @retval State of bit (1 or 0). + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** */ + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** { + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h **** return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK)); + 35 .loc 2 653 0 + 36 0000 0368 ldr r3, [r0] + 37 .LVL1: + 38 .LBE7: + 39 .LBE6: + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ErrorStatus status = SUCCESS; + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + ARM GAS /tmp/ccwmSZef.s page 16 + + + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Check the parameters */ + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Note: Hardware constraint (refer to description of this function): */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* COMP instance must not be locked. */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** if(LL_COMP_IsLocked(COMPx) == 0U) + 40 .loc 1 170 0 + 41 0002 002B cmp r3, #0 + 42 0004 0EDB blt .L4 + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** if(COMPx == COMP1) + 43 .loc 1 172 0 + 44 0006 084B ldr r3, .L6 + 45 0008 9842 cmp r0, r3 + 46 000a 05D0 beq .L5 + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** CLEAR_BIT(COMPx->CSR, + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP1EN + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1INNSEL + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1WM + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1LPTIM1IN1 + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1POLARITY + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1LOCK + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** else + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** CLEAR_BIT(COMPx->CSR, + 47 .loc 1 186 0 + 48 000c 0368 ldr r3, [r0] + 49 000e 074A ldr r2, .L6+4 + 50 0010 1340 ands r3, r2 + 51 0012 0360 str r3, [r0] + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 52 .loc 1 163 0 + 53 0014 0120 movs r0, #1 + 54 .LVL2: + 55 .L2: + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP2EN + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2SPEED + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2INNSEL + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2INPSEL + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2LPTIM1IN2 + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2LPTIM1IN1 + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2POLARITY + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2LOCK + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ); + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** else + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Comparator instance is locked: de-initialization by software is */ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* not possible. */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* The only way to unlock the comparator is a device hardware reset. */ + ARM GAS /tmp/ccwmSZef.s page 17 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** status = ERROR; + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** return status; + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 56 .loc 1 209 0 + 57 @ sp needed + 58 0016 7047 bx lr + 59 .LVL3: + 60 .L5: + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP1EN + 61 .loc 1 174 0 + 62 0018 0368 ldr r3, [r0] + 63 001a 054A ldr r2, .L6+8 + 64 001c 1340 ands r3, r2 + 65 001e 0360 str r3, [r0] + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 66 .loc 1 163 0 + 67 0020 0120 movs r0, #1 + 68 .LVL4: + 69 0022 F8E7 b .L2 + 70 .LVL5: + 71 .L4: + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 72 .loc 1 205 0 + 73 0024 0020 movs r0, #0 + 74 .LVL6: + 75 0026 F6E7 b .L2 + 76 .L7: + 77 .align 2 + 78 .L6: + 79 0028 18000140 .word 1073807384 + 80 002c 8648FF7F .word 2147436678 + 81 0030 CE6EFF7F .word 2147446478 + 82 .cfi_endproc + 83 .LFE58: + 85 .section .text.LL_COMP_Init,"ax",%progbits + 86 .align 1 + 87 .global LL_COMP_Init + 88 .syntax unified + 89 .code 16 + 90 .thumb_func + 91 .fpu softvfp + 93 LL_COMP_Init: + 94 .LFB59: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @brief Initialize some features of COMP instance. + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @note This function configures features of the selected COMP instance. + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * Some features are also available at scope COMP common instance + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * (common to several COMP instances). + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * Refer to functions having argument "COMPxy_COMMON" as parameter. + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @param COMPx COMP instance + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @retval An ErrorStatus enumeration value: + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * - SUCCESS: COMP registers are initialized + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * - ERROR: COMP registers are not initialized + ARM GAS /tmp/ccwmSZef.s page 18 + + + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 95 .loc 1 224 0 + 96 .cfi_startproc + 97 @ args = 0, pretend = 0, frame = 0 + 98 @ frame_needed = 0, uses_anonymous_args = 0 + 99 .LVL7: + 100 0000 10B5 push {r4, lr} + 101 .LCFI0: + 102 .cfi_def_cfa_offset 8 + 103 .cfi_offset 4, -8 + 104 .cfi_offset 14, -4 + 105 .LVL8: + 106 .LBB8: + 107 .LBB9: + 108 .loc 2 653 0 + 109 0002 0368 ldr r3, [r0] + 110 .LVL9: + 111 .LBE9: + 112 .LBE8: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ErrorStatus status = SUCCESS; + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Check the parameters */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** if(COMPx == COMP2) + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus)); + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus)); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Note: Hardware constraint (refer to description of this function) */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* COMP instance must not be locked. */ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** if(LL_COMP_IsLocked(COMPx) == 0U) + 113 .loc 1 239 0 + 114 0004 002B cmp r3, #0 + 115 0006 1ADB blt .L11 + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Configuration of comparator instance : */ + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* - PowerMode */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* - InputPlus */ + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* - InputMinus */ + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* - OutputPolarity */ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Note: Connection switch is applicable only to COMP instance COMP1, */ + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* therefore is COMP2 is selected the equivalent bit is */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* kept unmodified. */ + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** if(COMPx == COMP1) + 116 .loc 1 249 0 + 117 0008 0E4B ldr r3, .L13 + 118 000a 9842 cmp r0, r3 + 119 000c 0DD0 beq .L12 + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** MODIFY_REG(COMPx->CSR, + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP1INNSEL + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP1POLARITY + ARM GAS /tmp/ccwmSZef.s page 19 + + + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** , + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_InitStruct->InputMinus + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_InitStruct->OutputPolarity + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ); + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** else + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** MODIFY_REG(COMPx->CSR, + 120 .loc 1 263 0 + 121 000e 0368 ldr r3, [r0] + 122 0010 0D4A ldr r2, .L13+4 + 123 0012 1A40 ands r2, r3 + 124 0014 0B68 ldr r3, [r1] + 125 0016 4C68 ldr r4, [r1, #4] + 126 0018 2343 orrs r3, r4 + 127 001a 8C68 ldr r4, [r1, #8] + 128 001c 2343 orrs r3, r4 + 129 001e C968 ldr r1, [r1, #12] + 130 .LVL10: + 131 0020 0B43 orrs r3, r1 + 132 0022 1343 orrs r3, r2 + 133 0024 0360 str r3, [r0] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 134 .loc 1 225 0 + 135 0026 0120 movs r0, #1 + 136 .LVL11: + 137 .L9: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP2SPEED + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2INPSEL + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2INNSEL + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_CSR_COMP2POLARITY + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** , + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_InitStruct->PowerMode + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_InitStruct->InputPlus + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_InitStruct->InputMinus + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** | COMP_InitStruct->OutputPolarity + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ) + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ); + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** else + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Initialization error: COMP instance is locked. */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** status = ERROR; + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** return status; + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 138 .loc 1 286 0 + 139 @ sp needed + 140 0028 10BD pop {r4, pc} + 141 .LVL12: + 142 .L12: + ARM GAS /tmp/ccwmSZef.s page 20 + + + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** ( COMP_CSR_COMP1INNSEL + 143 .loc 1 251 0 + 144 002a 0368 ldr r3, [r0] + 145 002c 074A ldr r2, .L13+8 + 146 002e 1340 ands r3, r2 + 147 0030 8A68 ldr r2, [r1, #8] + 148 0032 C968 ldr r1, [r1, #12] + 149 .LVL13: + 150 0034 0A43 orrs r2, r1 + 151 0036 1343 orrs r3, r2 + 152 0038 0360 str r3, [r0] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 153 .loc 1 225 0 + 154 003a 0120 movs r0, #1 + 155 .LVL14: + 156 003c F4E7 b .L9 + 157 .LVL15: + 158 .L11: + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 159 .loc 1 282 0 + 160 003e 0020 movs r0, #0 + 161 .LVL16: + 162 0040 F2E7 b .L9 + 163 .L14: + 164 0042 C046 .align 2 + 165 .L13: + 166 0044 18000140 .word 1073807384 + 167 0048 8778FFFF .word -34681 + 168 004c CF7FFFFF .word -32817 + 169 .cfi_endproc + 170 .LFE59: + 172 .section .text.LL_COMP_StructInit,"ax",%progbits + 173 .align 1 + 174 .global LL_COMP_StructInit + 175 .syntax unified + 176 .code 16 + 177 .thumb_func + 178 .fpu softvfp + 180 LL_COMP_StructInit: + 181 .LFB60: + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /** + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @brief Set each @ref LL_COMP_InitTypeDef field to default value. + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * whose fields will be set to default values. + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** * @retval None + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** */ + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** { + 182 .loc 1 295 0 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 0 + 185 @ frame_needed = 0, uses_anonymous_args = 0 + 186 @ link register save eliminated. + 187 .LVL17: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** /* Set COMP_InitStruct fields to default values */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_MEDIUMSPEED; + ARM GAS /tmp/ccwmSZef.s page 21 + + + 188 .loc 1 297 0 + 189 0000 0823 movs r3, #8 + 190 0002 0360 str r3, [r0] + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1; + 191 .loc 1 298 0 + 192 0004 0023 movs r3, #0 + 193 0006 4360 str r3, [r0, #4] + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT; + 194 .loc 1 299 0 + 195 0008 8360 str r3, [r0, #8] + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED; + 196 .loc 1 300 0 + 197 000a C360 str r3, [r0, #12] + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c **** } + 198 .loc 1 301 0 + 199 @ sp needed + 200 000c 7047 bx lr + 201 .cfi_endproc + 202 .LFE60: + 204 .text + 205 .Letext0: + 206 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 207 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 208 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 209 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 210 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 211 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 212 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 213 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 214 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccwmSZef.s page 22 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_comp.c + /tmp/ccwmSZef.s:16 .text.LL_COMP_DeInit:0000000000000000 $t + /tmp/ccwmSZef.s:23 .text.LL_COMP_DeInit:0000000000000000 LL_COMP_DeInit + /tmp/ccwmSZef.s:79 .text.LL_COMP_DeInit:0000000000000028 $d + /tmp/ccwmSZef.s:86 .text.LL_COMP_Init:0000000000000000 $t + /tmp/ccwmSZef.s:93 .text.LL_COMP_Init:0000000000000000 LL_COMP_Init + /tmp/ccwmSZef.s:166 .text.LL_COMP_Init:0000000000000044 $d + /tmp/ccwmSZef.s:173 .text.LL_COMP_StructInit:0000000000000000 $t + /tmp/ccwmSZef.s:180 .text.LL_COMP_StructInit:0000000000000000 LL_COMP_StructInit + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_crc.d b/build/stm32l0xx_ll_crc.d new file mode 100644 index 0000000..82ec740 --- /dev/null +++ b/build/stm32l0xx_ll_crc.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_crc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_crc.lst b/build/stm32l0xx_ll_crc.lst new file mode 100644 index 0000000..20af7f8 --- /dev/null +++ b/build/stm32l0xx_ll_crc.lst @@ -0,0 +1,574 @@ +ARM GAS /tmp/cca0JcEC.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_crc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_CRC_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_CRC_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_CRC_DeInit: + 24 .LFB87: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @file stm32l0xx_ll_crc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @brief CRC LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** ****************************************************************************** + ARM GAS /tmp/cca0JcEC.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #include "stm32l0xx_ll_crc.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** #if defined (CRC) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** @addtogroup CRC_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Private macros ------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Private function prototypes -----------------------------------------------*/ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Exported functions --------------------------------------------------------*/ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** @addtogroup CRC_LL_Exported_Functions + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @{ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** @addtogroup CRC_LL_EF_Init + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @{ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @brief De-initialize CRC registers (Registers restored to their default values). + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @param CRCx CRC Instance + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * @retval An ErrorStatus enumeration value: + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * - SUCCESS: CRC registers are de-initialized + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** * - ERROR: CRC registers are not de-initialized + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** { + 26 .loc 1 80 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** ErrorStatus status = SUCCESS; + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Check the parameters */ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + ARM GAS /tmp/cca0JcEC.s page 3 + + + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** if (CRCx == CRC) + 32 .loc 1 86 0 + 33 0000 084B ldr r3, .L5 + 34 0002 9842 cmp r0, r3 + 35 0004 01D0 beq .L4 + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** { + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Force CRC reset */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** /* Release CRC reset */ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** } + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** else + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** { + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** status = ERROR; + 36 .loc 1 96 0 + 37 0006 0020 movs r0, #0 + 38 .LVL1: + 39 .L2: + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** } + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** return (status); + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** } + 40 .loc 1 100 0 + 41 @ sp needed + 42 0008 7047 bx lr + 43 .LVL2: + 44 .L4: + 45 .LBB6: + 46 .LBB7: + 47 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + ARM GAS /tmp/cca0JcEC.s page 4 + + + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + ARM GAS /tmp/cca0JcEC.s page 5 + + + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + ARM GAS /tmp/cca0JcEC.s page 6 + + + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + ARM GAS /tmp/cca0JcEC.s page 7 + + + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/cca0JcEC.s page 8 + + + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + ARM GAS /tmp/cca0JcEC.s page 9 + + + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 48 .loc 2 319 0 + 49 000a 074B ldr r3, .L5+4 + 50 000c 196A ldr r1, [r3, #32] + 51 000e 8022 movs r2, #128 + 52 0010 5201 lsls r2, r2, #5 + 53 0012 0A43 orrs r2, r1 + 54 0014 1A62 str r2, [r3, #32] + 55 .LVL3: + 56 .LBE7: + 57 .LBE6: + 58 .LBB8: + 59 .LBB9: + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 60 .loc 2 344 0 + 61 0016 1A6A ldr r2, [r3, #32] + 62 0018 0449 ldr r1, .L5+8 + 63 001a 0A40 ands r2, r1 + 64 001c 1A62 str r2, [r3, #32] + 65 .LBE9: + 66 .LBE8: + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c **** + 67 .loc 1 81 0 + 68 001e 0120 movs r0, #1 + 69 .LVL4: + ARM GAS /tmp/cca0JcEC.s page 10 + + + 70 0020 F2E7 b .L2 + 71 .L6: + 72 0022 C046 .align 2 + 73 .L5: + 74 0024 00300240 .word 1073885184 + 75 0028 00100240 .word 1073876992 + 76 002c FFEFFFFF .word -4097 + 77 .cfi_endproc + 78 .LFE87: + 80 .text + 81 .Letext0: + 82 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 83 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 84 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 85 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 86 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 87 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 88 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 89 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 90 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cca0JcEC.s page 11 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_crc.c + /tmp/cca0JcEC.s:16 .text.LL_CRC_DeInit:0000000000000000 $t + /tmp/cca0JcEC.s:23 .text.LL_CRC_DeInit:0000000000000000 LL_CRC_DeInit + /tmp/cca0JcEC.s:74 .text.LL_CRC_DeInit:0000000000000024 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_crs.d b/build/stm32l0xx_ll_crs.d new file mode 100644 index 0000000..a7ff70c --- /dev/null +++ b/build/stm32l0xx_ll_crs.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_crs.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_crs.lst b/build/stm32l0xx_ll_crs.lst new file mode 100644 index 0000000..1dc29ca --- /dev/null +++ b/build/stm32l0xx_ll_crs.lst @@ -0,0 +1,873 @@ +ARM GAS /tmp/cccoVMjM.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_crs.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_CRS_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_CRS_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_CRS_DeInit: + 24 .LFB112: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @file stm32l0xx_ll_crs.h + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @brief CRS LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** ****************************************************************************** + ARM GAS /tmp/cccoVMjM.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** #include "stm32l0xx_ll_crs.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** @addtogroup STM32L0xx_LL_Driver + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @{ + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** #if defined(CRS) + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** @defgroup CRS_LL CRS + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Private types -------------------------------------------------------------*/ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Private variables ---------------------------------------------------------*/ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Private constants ---------------------------------------------------------*/ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Private macros ------------------------------------------------------------*/ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Private function prototypes -----------------------------------------------*/ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /* Exported functions --------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** @addtogroup CRS_LL_Exported_Functions + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @{ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** @addtogroup CRS_LL_EF_Init + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @{ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** /** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @brief De-Initializes CRS peripheral registers to their default reset values. + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * @retval An ErrorStatus enumeration value: + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * - SUCCESS: CRS registers are de-initialized + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** * - ERROR: not applicable + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** ErrorStatus LL_CRS_DeInit(void) + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** { + 26 .loc 1 73 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB6: + 33 .LBB7: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + ARM GAS /tmp/cccoVMjM.s page 3 + + + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + ARM GAS /tmp/cccoVMjM.s page 4 + + + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + ARM GAS /tmp/cccoVMjM.s page 5 + + + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cccoVMjM.s page 6 + + + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + ARM GAS /tmp/cccoVMjM.s page 7 + + + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/cccoVMjM.s page 8 + + + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/cccoVMjM.s page 9 + + + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + ARM GAS /tmp/cccoVMjM.s page 10 + + + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cccoVMjM.s page 11 + + + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/cccoVMjM.s page 12 + + + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/cccoVMjM.s page 13 + + + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 35 .loc 2 613 0 + 36 0000 054B ldr r3, .L2 + 37 0002 996A ldr r1, [r3, #40] + 38 0004 8022 movs r2, #128 + 39 0006 1205 lsls r2, r2, #20 + 40 0008 0A43 orrs r2, r1 + 41 000a 9A62 str r2, [r3, #40] + 42 .LVL1: + 43 .LBE7: + 44 .LBE6: + 45 .LBB8: + 46 .LBB9: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/cccoVMjM.s page 14 + + + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 47 .loc 2 664 0 + 48 000c 9A6A ldr r2, [r3, #40] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 9A62 str r2, [r3, #40] + 52 .LVL2: + 53 .LBE9: + 54 .LBE8: + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS); + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS); + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** return SUCCESS; + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c **** } + 55 .loc 1 78 0 + 56 0014 0120 movs r0, #1 + 57 @ sp needed + ARM GAS /tmp/cccoVMjM.s page 15 + + + 58 0016 7047 bx lr + 59 .L3: + 60 .align 2 + 61 .L2: + 62 0018 00100240 .word 1073876992 + 63 001c FFFFFFF7 .word -134217729 + 64 .cfi_endproc + 65 .LFE112: + 67 .text + 68 .Letext0: + 69 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 70 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 71 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 72 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 73 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 74 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 75 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 76 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 77 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cccoVMjM.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_crs.c + /tmp/cccoVMjM.s:16 .text.LL_CRS_DeInit:0000000000000000 $t + /tmp/cccoVMjM.s:23 .text.LL_CRS_DeInit:0000000000000000 LL_CRS_DeInit + /tmp/cccoVMjM.s:62 .text.LL_CRS_DeInit:0000000000000018 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_dac.d b/build/stm32l0xx_ll_dac.d new file mode 100644 index 0000000..00d28ab --- /dev/null +++ b/build/stm32l0xx_ll_dac.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_dac.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_dac.lst b/build/stm32l0xx_ll_dac.lst new file mode 100644 index 0000000..365c7a0 --- /dev/null +++ b/build/stm32l0xx_ll_dac.lst @@ -0,0 +1,2263 @@ +ARM GAS /tmp/cc2GBi0Q.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_dac.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_DAC_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_DAC_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_DAC_DeInit: + 24 .LFB105: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @file stm32l0xx_ll_dac.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @brief DAC LL module driver + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ****************************************************************************** + ARM GAS /tmp/cc2GBi0Q.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #include "stm32l0xx_ll_dac.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #if defined (DAC1) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** @addtogroup DAC_LL DAC + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Private macros ------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** @addtogroup DAC_LL_Private_Macros + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @{ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #if defined(DAC_CHANNEL2_SUPPORT) + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( \ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #else + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( \ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #endif /* DAC_CHANNEL2_SUPPORT */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_CH3) \ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM21_TRGO) \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ARM GAS /tmp/cc2GBi0Q.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @} + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Private function prototypes -----------------------------------------------*/ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Exported functions --------------------------------------------------------*/ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** @addtogroup DAC_LL_Exported_Functions + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @{ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** @addtogroup DAC_LL_EF_Init + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @{ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @brief De-initialize registers of the selected DAC instance + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * to their default reset values. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @param DACx DAC instance + ARM GAS /tmp/cc2GBi0Q.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @retval An ErrorStatus enumeration value: + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * - SUCCESS: DAC registers are de-initialized + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * - ERROR: not applicable + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 26 .loc 1 153 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB8: + 33 .LBB9: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + ARM GAS /tmp/cc2GBi0Q.s page 5 + + + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + ARM GAS /tmp/cc2GBi0Q.s page 6 + + + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/cc2GBi0Q.s page 7 + + + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + ARM GAS /tmp/cc2GBi0Q.s page 8 + + + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + ARM GAS /tmp/cc2GBi0Q.s page 9 + + + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/cc2GBi0Q.s page 10 + + + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + ARM GAS /tmp/cc2GBi0Q.s page 11 + + + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + ARM GAS /tmp/cc2GBi0Q.s page 12 + + + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + ARM GAS /tmp/cc2GBi0Q.s page 13 + + + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + ARM GAS /tmp/cc2GBi0Q.s page 14 + + + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/cc2GBi0Q.s page 15 + + + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 35 .loc 2 613 0 + 36 0000 054B ldr r3, .L2 + 37 0002 996A ldr r1, [r3, #40] + 38 0004 8022 movs r2, #128 + 39 0006 9205 lsls r2, r2, #22 + 40 0008 0A43 orrs r2, r1 + 41 000a 9A62 str r2, [r3, #40] + 42 .LVL1: + 43 .LBE9: + 44 .LBE8: + 45 .LBB10: + 46 .LBB11: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + ARM GAS /tmp/cc2GBi0Q.s page 16 + + + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 47 .loc 2 664 0 + 48 000c 9A6A ldr r2, [r3, #40] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 9A62 str r2, [r3, #40] + 52 .LVL2: + 53 .LBE11: + 54 .LBE10: + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Check the parameters */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_DAC_ALL_INSTANCE(DACx)); + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Force reset of DAC clock */ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Release reset of DAC clock */ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** return SUCCESS; + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 55 .loc 1 164 0 + 56 0014 0120 movs r0, #1 + 57 .LVL3: + 58 @ sp needed + 59 0016 7047 bx lr + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0018 00100240 .word 1073876992 + 64 001c FFFFFFDF .word -536870913 + 65 .cfi_endproc + 66 .LFE105: + 68 .section .text.LL_DAC_Init,"ax",%progbits + 69 .align 1 + 70 .global LL_DAC_Init + 71 .syntax unified + 72 .code 16 + 73 .thumb_func + 74 .fpu softvfp + 76 LL_DAC_Init: + 77 .LFB106: + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @brief Initialize some features of DAC instance. + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @note The setting of these parameters by function @ref LL_DAC_Init() + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * is conditioned to DAC state: + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * DAC instance must be disabled. + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @param DACx DAC instance + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @param DAC_Channel This parameter can be one of the following values: + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @arg @ref LL_DAC_CHANNEL_1 + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @arg @ref LL_DAC_CHANNEL_2 (1) + ARM GAS /tmp/cc2GBi0Q.s page 17 + + + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * (1) On this STM32 serie, parameter not available on all devices. + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * Refer to device datasheet for channels availability. + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @retval An ErrorStatus enumeration value: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * - SUCCESS: DAC registers are initialized + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * - ERROR: DAC registers are not initialized + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 78 .loc 1 184 0 + 79 .cfi_startproc + 80 @ args = 0, pretend = 0, frame = 0 + 81 @ frame_needed = 0, uses_anonymous_args = 0 + 82 .LVL4: + 83 0000 30B5 push {r4, r5, lr} + 84 .LCFI0: + 85 .cfi_def_cfa_offset 12 + 86 .cfi_offset 4, -12 + 87 .cfi_offset 5, -8 + 88 .cfi_offset 14, -4 + 89 .LVL5: + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ErrorStatus status = SUCCESS; + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Check the parameters */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_DAC_ALL_INSTANCE(DACx)); + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + 90 .loc 1 193 0 + 91 0002 5468 ldr r4, [r2, #4] + 92 .LVL6: + 93 .LBB12: + 94 .LBB13: + 95 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @file stm32l0xx_ll_dac.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Header file of DAC LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * without specific prior written permission. + ARM GAS /tmp/cc2GBi0Q.s page 18 + + + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #ifndef __STM32L0xx_LL_DAC_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __STM32L0xx_LL_DAC_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined (DAC1) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL DAC + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Private constants ---------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_Private_Constants DAC Private Constants + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Internal masks for DAC channels definition */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - channel bits position into register CR */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - channel bits position into register SWTRIG */ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - channel register offset of data holding register DHRx */ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - channel register offset of data output register DORx */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CC + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CC + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR o + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR o + ARM GAS /tmp/cc2GBi0Q.s page 19 + + + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #else + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channe + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channe + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channe + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channe + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channe + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #else + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12R + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* DAC registers bits positions */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL( + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL( + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL( + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Miscellaneous data */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a r + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Private macros ------------------------------------------------------------*/ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_Private_Macros DAC Private Macros + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Driver macro reserved for internal use: set a pointer to + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * a register from a register basis from which an offset + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * is applied. + ARM GAS /tmp/cc2GBi0Q.s page 20 + + + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __REG__ Register basis from which the offset is applied. + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Pointer to register address + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Exported types ------------------------------------------------------------*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(USE_FULL_LL_DRIVER) + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Structure definition of some features of DAC instance. + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** typedef struct + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This parameter can be a value of @ref DAC_LL_EC_TRIGGE + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This feature can be modified afterwards using unitary + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the sel + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This parameter can be a value of @ref DAC_LL_EC_WAVE_A + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This feature can be modified afterwards using unitary + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the sel + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** If waveform automatic generation mode is set to noise, + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** If waveform automatic generation mode is set to triang + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** @note If waveform automatic generation mode is disable + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This feature can be modified afterwards using unitary + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This parameter can be a value of @ref DAC_LL_EC_OUTPUT + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** This feature can be modified afterwards using unitary + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } LL_DAC_InitTypeDef; + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* USE_FULL_LL_DRIVER */ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Exported constants --------------------------------------------------------*/ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + ARM GAS /tmp/cc2GBi0Q.s page 21 + + + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_GET_FLAG DAC flags + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Flags defines which can be used with LL_DAC_ReadReg function + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* DAC channel 1 flags */ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* DAC channel 2 flags */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_IT DAC interruptions + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA u + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA u + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_CHANNEL DAC channels + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DA + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DA + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM3_CH3 ( DAC_CR_TSEL1_1 ) /*!< + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_TIM21_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto gen + ARM GAS /tmp/cc2GBi0Q.s page 22 + + + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto gen + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto gen + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_ + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_ + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_ + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_ + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_ + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_ + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel ou + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel ou + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + ARM GAS /tmp/cc2GBi0Q.s page 23 + + + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 b + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bi + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* List of DAC registers intended to be used (most commonly) with */ + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* DMA transfer. */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note Only DAC IP HW delays are defined in DAC LL driver driver, + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * not timeout values. + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * For details on delays values, refer to descriptions in source code + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * above each literal definition. + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Delay for DAC channel voltage settling time from DAC channel startup */ + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* (transition from disable to enable). */ + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Note: DAC channel startup time depends on board application environment: */ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* impedance connected to DAC channel output. */ + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* The delay below is specified under conditions: */ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - voltage maximum transition (lowest to highest value) */ + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - until voltage reaches final value +-1LSB */ + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - DAC channel output buffer enabled */ + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - load impedance of 5kOhm (min), 50pF (max) */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Literal set to maximum value (refer to device datasheet, */ + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* parameter "tWAKEUP"). */ + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Unit: us */ + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltag + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Delay for DAC channel voltage settling time. */ + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Note: DAC channel startup time depends on board application environment: */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* impedance connected to DAC channel output. */ + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* The delay below is specified under conditions: */ + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - voltage maximum transition (lowest to highest value) */ + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - until voltage reaches final value +-1LSB */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - DAC channel output buffer enabled */ + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* - load impedance of 5kOhm min, 50pF max */ + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Literal set to maximum value (refer to device datasheet, */ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* parameter "tSETTLING"). */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Unit: us */ + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + ARM GAS /tmp/cc2GBi0Q.s page 24 + + + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Exported macro ------------------------------------------------------------*/ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Write a value in DAC register + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __INSTANCE__ DAC Instance + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __REG__ Register to be written + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __VALUE__ Value to be written in the register + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Read a value in DAC register + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __INSTANCE__ DAC Instance + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __REG__ Register to be read + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Register value + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Helper macro to get DAC channel number in decimal format + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * from literals LL_DAC_CHANNEL_x. + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Example: + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * will return decimal number "1". + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note The input can be a value from functions where a channel + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * number is returned. + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval 1...2 (value "2" depending on DAC channel 2 availability) + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ((__CHANNEL__) & DAC_SWTR_CHX_MASK) + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + ARM GAS /tmp/cc2GBi0Q.s page 25 + + + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * from number in decimal format. + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Example: + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * will return a data equivalent to "LL_DAC_CHANNEL_1". + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note If the input parameter does not correspond to a DAC channel, + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * this macro returns value '0'. + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #if defined(DAC_CHANNEL2_SUPPORT) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** (((__DECIMAL_NB__) == 1U) \ + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ? ( \ + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** LL_DAC_CHANNEL_1 \ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** : \ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** (((__DECIMAL_NB__) == 2U) \ + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ? ( \ + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** LL_DAC_CHANNEL_2 \ + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** : \ + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ( \ + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** 0 \ + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #else + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** (((__DECIMAL_NB__) == 1U) \ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ? ( \ + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** LL_DAC_CHANNEL_1 \ + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** : \ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ( \ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** 0 \ + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) \ + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #endif /* DAC_CHANNEL2_SUPPORT */ + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Helper macro to define the DAC conversion data full-scale digital + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * value corresponding to the selected DAC resolution. + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note DAC conversion data full-scale corresponds to voltage range + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * determined by analog voltage references Vref+ and Vref- + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (refer to reference manual). + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_RESOLUTION_12B + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_RESOLUTION_8B + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval ADC conversion data equivalent voltage value (unit: mVolt) + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + ARM GAS /tmp/cc2GBi0Q.s page 26 + + + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Helper macro to calculate the DAC conversion data (unit: digital + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * value) corresponding to a voltage (unit: mVolt). + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note This helper macro is intended to provide input data in voltage + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * rather than digital value, + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * to be used with LL DAC functions such as + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @ref LL_DAC_ConvertData12RightAligned(). + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note Analog reference voltage (Vref+) must be either known from + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * user board environment or can be calculated using ADC measurement + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (unit: mVolt). + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_RESOLUTION_12B + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_RESOLUTION_8B + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval DAC conversion data (unit: digital value) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __DAC_VOLTAGE__,\ + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __DAC_RESOLUTION__) \ + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** / (__VREFANALOG_VOLTAGE__) \ + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Exported functions --------------------------------------------------------*/ + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the conversion trigger source for the selected DAC channel. + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note For conversion trigger source to be effective, DAC trigger + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * must be enabled using function @ref LL_DAC_EnableTrigger(). + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note To set conversion trigger source, DAC channel must be disabled. + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Otherwise, the setting is discarded. + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note Availability of parameters of trigger sources from timer + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * depends on timers availability on the selected device. + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR TSEL2 LL_DAC_SetTriggerSource + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + ARM GAS /tmp/cc2GBi0Q.s page 27 + + + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param TriggerSource This parameter can be one of the following values: + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_SOFTWARE + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3 + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Trig + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** MODIFY_REG(DACx->CR, + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Get the conversion trigger source for the selected DAC channel. + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note For conversion trigger source to be effective, DAC trigger + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * must be enabled using function @ref LL_DAC_EnableTrigger(). + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note Availability of parameters of trigger sources from timer + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * depends on timers availability on the selected device. + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR TSEL2 LL_DAC_GetTriggerSource + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_SOFTWARE + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3 + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ); + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the waveform automatic generation mode + ARM GAS /tmp/cc2GBi0Q.s page 28 + + + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * for the selected DAC channel. + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR WAVE2 LL_DAC_SetWaveAutoGeneration + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param WaveAutoGeneration This parameter can be one of the following values: + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** MODIFY_REG(DACx->CR, + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Get the waveform automatic generation mode + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * for the selected DAC channel. + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR WAVE2 LL_DAC_GetWaveAutoGeneration + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ); + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the noise waveform generation for the selected DAC channel: + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Noise mode and parameters LFSR (linear feedback shift register). + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note For wave generation to be effective, DAC channel + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * wave generation mode must be enabled using + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * function @ref LL_DAC_SetWaveAutoGeneration(). + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note This setting can be set when the selected DAC channel is disabled + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (otherwise, the setting operation is ignored). + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + ARM GAS /tmp/cc2GBi0Q.s page 29 + + + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param NoiseLFSRMask This parameter can be one of the following values: + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Nois + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** MODIFY_REG(DACx->CR, + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the noise waveform generation for the selected DAC channel: + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Noise mode and parameters LFSR (linear feedback shift register). + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + ARM GAS /tmp/cc2GBi0Q.s page 30 + + + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ); + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the triangle waveform generation for the selected DAC channel: + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * triangle mode and amplitude. + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note For wave generation to be effective, DAC channel + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * wave generation mode must be enabled using + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * function @ref LL_DAC_SetWaveAutoGeneration(). + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note This setting can be set when the selected DAC channel is disabled + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (otherwise, the setting operation is ignored). + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param TriangleAmplitude This parameter can be one of the following values: + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint3 + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** MODIFY_REG(DACx->CR, + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the triangle waveform generation for the selected DAC channel: + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * triangle mode and amplitude. + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/cc2GBi0Q.s page 31 + + + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ); + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Set the output buffer for the selected DAC channel. + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR BOFF2 LL_DAC_SetOutputBuffer + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param OutputBuffer This parameter can be one of the following values: + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Outpu + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** MODIFY_REG(DACx->CR, + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Get the output buffer state for the selected DAC channel. + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR BOFF2 LL_DAC_GetOutputBuffer + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval Returned value can be one of the following values: + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + ARM GAS /tmp/cc2GBi0Q.s page 32 + + + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** ); + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EF_DMA_Management DMA Management + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Enable DAC DMA transfer request of the selected channel. + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note To configure DMA source address (peripheral address), + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * use function @ref LL_DAC_DMA_GetRegAddr(). + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR DMAEN2 LL_DAC_EnableDMAReq + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** SET_BIT(DACx->CR, + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Disable DAC DMA transfer request of the selected channel. + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note To configure DMA source address (peripheral address), + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * use function @ref LL_DAC_DMA_GetRegAddr(). + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR DMAEN2 LL_DAC_DisableDMAReq + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** CLEAR_BIT(DACx->CR, + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + ARM GAS /tmp/cc2GBi0Q.s page 33 + + + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Get DAC DMA transfer request state of the selected channel. + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR DMAEN2 LL_DAC_IsDMAReqEnabled + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval State of bit (1 or 0). + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (READ_BIT(DACx->CR, + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Function to help to configure DMA transfer to DAC: retrieve the + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DAC register address from DAC instance and a list of DAC registers + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * intended to be used (most commonly) with DMA transfer. + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note These DAC registers are data holding registers: + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * when DAC conversion is requested, DAC generates a DMA transfer + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * request to have data available in DAC data holding registers. + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note This macro is intended to be used with LL DMA driver, refer to + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * function "LL_DMA_ConfigAddresses()". + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Example: + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * LL_DMA_ConfigAddresses(DMA1, + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * LL_DMA_CHANNEL_1, + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (uint32_t)&< array or variable >, + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_D + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param Register This parameter can be one of the following values: + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval DAC register address + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Re + ARM GAS /tmp/cc2GBi0Q.s page 34 + + + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /* DAC channel selected. */ + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REG + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @} + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** @defgroup DAC_LL_EF_Operation Operation on DAC channels + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @{ + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Enable DAC selected channel. + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR EN1 LL_DAC_Enable\n + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR EN2 LL_DAC_Enable + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @note After enable from off state, DAC channel requires a delay + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * for output voltage to reach accuracy +/- 1 LSB. + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet, parameter "tWAKEUP". + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** SET_BIT(DACx->CR, + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Disable DAC selected channel. + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR EN1 LL_DAC_Disable\n + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR EN2 LL_DAC_Disable + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval None + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** CLEAR_BIT(DACx->CR, + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** } + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** /** + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @brief Get DAC enable state of the selected channel. + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (0: DAC channel is disabled, 1: DAC channel is enabled) + ARM GAS /tmp/cc2GBi0Q.s page 35 + + + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @rmtoll CR EN1 LL_DAC_IsEnabled\n + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * CR EN2 LL_DAC_IsEnabled + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DACx DAC instance + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @param DAC_Channel This parameter can be one of the following values: + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_1 + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @arg @ref LL_DAC_CHANNEL_2 (1) + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * (1) On this STM32 serie, parameter not available on all devices. + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * Refer to device datasheet for channels availability. + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** * @retval State of bit (1 or 0). +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** */ +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** { +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h **** return (READ_BIT(DACx->CR, + 96 .loc 3 1003 0 + 97 0004 0568 ldr r5, [r0] + 98 0006 1023 movs r3, #16 + 99 0008 1940 ands r1, r3 + 100 .LVL7: + 101 000a 0F3B subs r3, r3, #15 + 102 000c 8B40 lsls r3, r3, r1 + 103 000e 1D40 ands r5, r3 + 104 .LVL8: + 105 .LBE13: + 106 .LBE12: + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Note: Hardware constraint (refer to description of this function) */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* DAC instance must be disabled. */ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + 107 .loc 1 200 0 + 108 0010 AB42 cmp r3, r5 + 109 0012 1CD0 beq .L7 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Configuration of DAC channel: */ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* - TriggerSource */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* - WaveAutoGeneration */ + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* - OutputBuffer */ + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + 110 .loc 1 206 0 + 111 0014 002C cmp r4, #0 + 112 0016 0BD1 bne .L8 + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** MODIFY_REG(DACx->CR, + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( DAC_CR_TSEL1 + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_CR_WAVE1 + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_CR_MAMP1 + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_CR_BOFF1 + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** , + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( DAC_InitStruct->TriggerSource + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_InitStruct->WaveAutoGeneration + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_InitStruct->WaveAutoGenerationConfig + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_InitStruct->OutputBuffer + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ARM GAS /tmp/cc2GBi0Q.s page 36 + + + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ); + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** else + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** MODIFY_REG(DACx->CR, + 113 .loc 1 224 0 + 114 0018 0368 ldr r3, [r0] + 115 001a FA24 movs r4, #250 + 116 001c 8C40 lsls r4, r4, r1 + 117 001e A343 bics r3, r4 + 118 0020 1468 ldr r4, [r2] + 119 0022 D268 ldr r2, [r2, #12] + 120 .LVL9: + 121 0024 2243 orrs r2, r4 + 122 0026 8A40 lsls r2, r2, r1 + 123 0028 1343 orrs r3, r2 + 124 002a 0360 str r3, [r0] + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 125 .loc 1 185 0 + 126 002c 0120 movs r0, #1 + 127 .LVL10: + 128 .L5: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( DAC_CR_TSEL1 + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_CR_WAVE1 + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_CR_BOFF1 + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** , + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( DAC_InitStruct->TriggerSource + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | LL_DAC_WAVE_AUTO_GENERATION_NONE + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** | DAC_InitStruct->OutputBuffer + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** else + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Initialization error: DAC instance is not disabled. */ + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** status = ERROR; + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** return status; + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 129 .loc 1 243 0 + 130 @ sp needed + 131 002e 30BD pop {r4, r5, pc} + 132 .LVL11: + 133 .L8: + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** ( DAC_CR_TSEL1 + 134 .loc 1 208 0 + 135 0030 0368 ldr r3, [r0] + 136 0032 084D ldr r5, .L9 + 137 0034 8D40 lsls r5, r5, r1 + 138 0036 AB43 bics r3, r5 + 139 0038 1568 ldr r5, [r2] + 140 003a 2C43 orrs r4, r5 + 141 003c 9568 ldr r5, [r2, #8] + 142 003e 2C43 orrs r4, r5 + 143 0040 D268 ldr r2, [r2, #12] + ARM GAS /tmp/cc2GBi0Q.s page 37 + + + 144 .LVL12: + 145 0042 1443 orrs r4, r2 + 146 0044 8C40 lsls r4, r4, r1 + 147 0046 1C43 orrs r4, r3 + 148 0048 0460 str r4, [r0] + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 149 .loc 1 185 0 + 150 004a 0120 movs r0, #1 + 151 .LVL13: + 152 004c EFE7 b .L5 + 153 .LVL14: + 154 .L7: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 155 .loc 1 240 0 + 156 004e 0020 movs r0, #0 + 157 .LVL15: + 158 0050 EDE7 b .L5 + 159 .L10: + 160 0052 C046 .align 2 + 161 .L9: + 162 0054 FA0F0000 .word 4090 + 163 .cfi_endproc + 164 .LFE106: + 166 .section .text.LL_DAC_StructInit,"ax",%progbits + 167 .align 1 + 168 .global LL_DAC_StructInit + 169 .syntax unified + 170 .code 16 + 171 .thumb_func + 172 .fpu softvfp + 174 LL_DAC_StructInit: + 175 .LFB107: + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @brief Set each @ref LL_DAC_InitTypeDef field to default value. + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * whose fields will be set to default values. + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** * @retval None + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** { + 176 .loc 1 252 0 + 177 .cfi_startproc + 178 @ args = 0, pretend = 0, frame = 0 + 179 @ frame_needed = 0, uses_anonymous_args = 0 + 180 @ link register save eliminated. + 181 .LVL16: + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Set DAC_InitStruct fields to default values */ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE; + 182 .loc 1 254 0 + 183 0000 3823 movs r3, #56 + 184 0002 0360 str r3, [r0] + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; + 185 .loc 1 255 0 + 186 0004 0023 movs r3, #0 + 187 0006 4360 str r3, [r0, #4] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* Note: Parameter discarded if wave auto generation is disabled, */ + ARM GAS /tmp/cc2GBi0Q.s page 38 + + + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** /* set anyway to its default value. */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0; + 188 .loc 1 258 0 + 189 0008 8360 str r3, [r0, #8] + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; + 190 .loc 1 259 0 + 191 000a C360 str r3, [r0, #12] + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c **** } + 192 .loc 1 260 0 + 193 @ sp needed + 194 000c 7047 bx lr + 195 .cfi_endproc + 196 .LFE107: + 198 .text + 199 .Letext0: + 200 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 201 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 202 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 203 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 204 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 205 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 206 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 207 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 208 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc2GBi0Q.s page 39 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_dac.c + /tmp/cc2GBi0Q.s:16 .text.LL_DAC_DeInit:0000000000000000 $t + /tmp/cc2GBi0Q.s:23 .text.LL_DAC_DeInit:0000000000000000 LL_DAC_DeInit + /tmp/cc2GBi0Q.s:63 .text.LL_DAC_DeInit:0000000000000018 $d + /tmp/cc2GBi0Q.s:69 .text.LL_DAC_Init:0000000000000000 $t + /tmp/cc2GBi0Q.s:76 .text.LL_DAC_Init:0000000000000000 LL_DAC_Init + /tmp/cc2GBi0Q.s:162 .text.LL_DAC_Init:0000000000000054 $d + /tmp/cc2GBi0Q.s:167 .text.LL_DAC_StructInit:0000000000000000 $t + /tmp/cc2GBi0Q.s:174 .text.LL_DAC_StructInit:0000000000000000 LL_DAC_StructInit + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_dma.d b/build/stm32l0xx_ll_dma.d new file mode 100644 index 0000000..47fad5a --- /dev/null +++ b/build/stm32l0xx_ll_dma.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_dma.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_dma.lst b/build/stm32l0xx_ll_dma.lst new file mode 100644 index 0000000..e446dc6 --- /dev/null +++ b/build/stm32l0xx_ll_dma.lst @@ -0,0 +1,3142 @@ +ARM GAS /tmp/ccak0twC.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_dma.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_DMA_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_DMA_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_DMA_DeInit: + 24 .LFB163: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @file stm32l0xx_ll_dma.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @brief DMA LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ****************************************************************************** + ARM GAS /tmp/ccak0twC.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #include "stm32l0xx_ll_dma.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #ifdef USE_FULL_ASSERT + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #include "stm32_assert.h" + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #else + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define assert_param(expr) ((void)0U) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #endif + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** @addtogroup STM32L0xx_LL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined (DMA1) + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** @defgroup DMA_LL DMA + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Private types -------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Private constants ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Private macros ------------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** @addtogroup DMA_LL_Private_Macros + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_1) || \ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_2) || \ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_3) || \ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_4) || \ + ARM GAS /tmp/ccak0twC.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_5) || \ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_6) || \ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_7) || \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_8) || \ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_9) || \ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_10) || \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_11) || \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_12) || \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_13) || \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_14) || \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_REQUEST_15)) + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined (DMA1_Channel6) && defined (DMA1_Channel7) + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_7)))) + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #elif defined (DMA1_Channel6) + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_6)))) + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #else + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ((CHANNEL) == LL_DMA_CHANNEL_5)))) + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #endif /* DMA1_Channel6 && DMA1_Channel7 */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @} + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Exported functions --------------------------------------------------------*/ + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** @addtogroup DMA_LL_Exported_Functions + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @{ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** @addtogroup DMA_LL_EF_Init + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @{ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + ARM GAS /tmp/ccak0twC.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @brief De-initialize the DMA registers to their default reset values. + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param DMAx DMAx Instance + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param Channel This parameter can be one of the following values: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_1 + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_2 + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_3 + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_4 + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_5 + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_6 (*) + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_7 (*) + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_ALL + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * (*) value not defined in all devices + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @retval An ErrorStatus enumeration value: + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - SUCCESS: DMA registers are de-initialized + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - ERROR: DMA registers are not de-initialized + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 26 .loc 1 167 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 30B5 push {r4, r5, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 12 + 34 .cfi_offset 4, -12 + 35 .cfi_offset 5, -8 + 36 .cfi_offset 14, -4 + 37 .LVL1: + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** ErrorStatus status = SUCCESS; + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Check the DMA Instance DMAx and Channel parameters*/ + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** if (Channel == LL_DMA_CHANNEL_ALL) + 38 .loc 1 174 0 + 39 0002 484B ldr r3, .L40 + 40 0004 9942 cmp r1, r3 + 41 0006 35D0 beq .L25 + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** if (DMAx == DMA1) + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Force reset of DMA clock */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Release reset of DMA clock */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined(DMA2) + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (DMAx == DMA2) + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Force reset of DMA clock */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + ARM GAS /tmp/ccak0twC.s page 5 + + + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Release reset of DMA clock */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #endif + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** status = ERROR; + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + 42 .loc 1 201 0 + 43 0008 474B ldr r3, .L40+4 + 44 000a 9842 cmp r0, r3 + 45 000c 41D0 beq .L26 + 46 .L4: + 47 .loc 1 201 0 is_stmt 0 discriminator 3 + 48 000e 464B ldr r3, .L40+4 + 49 0010 9842 cmp r0, r3 + 50 0012 42D0 beq .L27 + 51 .L6: + 52 .loc 1 201 0 discriminator 7 + 53 0014 444B ldr r3, .L40+4 + 54 0016 9842 cmp r0, r3 + 55 0018 43D0 beq .L28 + 56 .L7: + 57 .loc 1 201 0 discriminator 11 + 58 001a 434B ldr r3, .L40+4 + 59 001c 9842 cmp r0, r3 + 60 001e 44D0 beq .L29 + 61 .L8: + 62 .loc 1 201 0 discriminator 15 + 63 0020 414B ldr r3, .L40+4 + 64 0022 9842 cmp r0, r3 + 65 0024 45D0 beq .L30 + 66 .L9: + 67 .loc 1 201 0 discriminator 19 + 68 0026 404B ldr r3, .L40+4 + 69 0028 9842 cmp r0, r3 + 70 002a 46D0 beq .L31 + 71 .loc 1 201 0 + 72 002c 3F4B ldr r3, .L40+8 + 73 .L5: + 74 .LVL2: + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Disable the selected DMAx_Channely */ + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + 75 .loc 1 204 0 is_stmt 1 discriminator 36 + 76 002e 1A68 ldr r2, [r3] + 77 0030 0124 movs r4, #1 + 78 0032 A243 bics r2, r4 + 79 0034 1A60 str r2, [r3] + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset DMAx_Channely control register */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_WriteReg(tmp, CCR, 0U); + ARM GAS /tmp/ccak0twC.s page 6 + + + 80 .loc 1 207 0 discriminator 36 + 81 0036 0022 movs r2, #0 + 82 0038 1A60 str r2, [r3] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset DMAx_Channely remaining bytes register */ + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_WriteReg(tmp, CNDTR, 0U); + 83 .loc 1 210 0 discriminator 36 + 84 003a 5A60 str r2, [r3, #4] + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset DMAx_Channely peripheral address register */ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_WriteReg(tmp, CPAR, 0U); + 85 .loc 1 213 0 discriminator 36 + 86 003c 9A60 str r2, [r3, #8] + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset DMAx_Channely memory address register */ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_WriteReg(tmp, CMAR, 0U); + 87 .loc 1 216 0 discriminator 36 + 88 003e DA60 str r2, [r3, #12] + 89 .LVL3: + 90 .LBB32: + 91 .LBB33: + 92 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @file stm32l0xx_ll_dma.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Header file of DMA LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + ARM GAS /tmp/ccak0twC.s page 7 + + + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #ifndef __STM32L0xx_LL_DMA_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __STM32L0xx_LL_DMA_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined (DMA1) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL DMA + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** static const uint8_t CHANNEL_OFFSET_TAB[] = + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /*DMA1_Channel6*/ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /*DMA1_Channel7*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** }; + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Define used to get CSELR register offset */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Defines used for the bit position in the register and perform offsets */ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + ARM GAS /tmp/ccak0twC.s page 8 + + + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Macros DMA Private Macros + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** typedef struct + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** or as Source base address in case of memory to memory trans + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** or as Destination base address in case of memory to memory + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** from memory to memory or from peripheral to memory. + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** @note: The circular buffer mode cannot be used if the memor + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** data transfer direction is configured on the selecte + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** is incremented or not. + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** is incremented or not. + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** in case of memory to memory transfer direction. + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + ARM GAS /tmp/ccak0twC.s page 9 + + + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** in case of memory to memory transfer direction. + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** The data unit is equal to the source buffer configuration s + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t PeriphRequest; /*!< Specifies the peripheral request. + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_REQUEST + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } LL_DMA_InitTypeDef; + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Flags defines which can be used with LL_DMA_WriteReg function + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete fl + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete fl + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete fl + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete fl + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete fl + ARM GAS /tmp/ccak0twC.s page 10 + + + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete fl + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete fl + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Flags defines which can be used with LL_DMA_ReadReg function + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete fl + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete fl + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete fl + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete fl + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete fl + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete fl + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete fl + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + ARM GAS /tmp/ccak0twC.s page 11 + + + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_IT IT Defines + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only f + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory directi + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral directi + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE Transfer mode + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode En + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Di + ARM GAS /tmp/ccak0twC.s page 12 + + + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY Memory increment mode + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disabl + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : Half + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low * + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium * + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High * + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High * + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /*!< DMA peripheral request 8 */ + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /*!< DMA peripheral request 9 */ + ARM GAS /tmp/ccak0twC.s page 13 + + + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */ + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */ + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */ + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */ + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */ + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Write a value in DMA register + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __REG__ Register to be written + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Read a value in DMA register + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __REG__ Register to be read + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Register value + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Convert DMAx_Channely into DMAx + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __CHANNEL_INSTANCE__ DMAx_Channely + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval DMAx + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __CHANNEL_INSTANCE__ DMAx_Channely + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + ARM GAS /tmp/ccak0twC.s page 14 + + + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined (DMA1_Channel6) && defined (DMA1_Channel7) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** LL_DMA_CHANNEL_7) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #elif defined (DMA1_Channel6) + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** LL_DMA_CHANNEL_6) + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #else + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** LL_DMA_CHANNEL_5) + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /* DMA1_Channel6 && DMA1_Channel7 */ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param __CHANNEL__ LL_DMA_CHANNEL_y + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval DMAx_Channely + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined (DMA1_Channel6) && defined (DMA1_Channel7) + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA1_Channel7) + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #elif defined (DMA1_Channel6) + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA1_Channel6) + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #else + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA1_Channel5) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif /* DMA1_Channel6 && DMA1_Channel7 */ + ARM GAS /tmp/ccak0twC.s page 15 + + + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Enable DMA channel. + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_EnableChannel + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))- + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Disable DMA channel. + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_DisableChannel + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])) + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Check if DMA channel is enabled or disabled. + ARM GAS /tmp/ccak0twC.s page 16 + + + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_IsEnabledChannel + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_EN) == (DMA_CCR_EN)); + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Configure all parameters link to DMA transfer. + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_ConfigTransfer\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR CIRC LL_DMA_ConfigTransfer\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR PINC LL_DMA_ConfigTransfer\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR MINC LL_DMA_ConfigTransfer\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR PSIZE LL_DMA_ConfigTransfer\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR MSIZE LL_DMA_ConfigTransfer\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR PL LL_DMA_ConfigTransfer + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configurat + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_P + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** Configuration); + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + ARM GAS /tmp/ccak0twC.s page 17 + + + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_SetDataTransferDirection + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_GetDataTransferDirection + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set DMA mode circular or normal. + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note The circular buffer mode cannot be used if the memory-to-memory + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * data transfer is configured on the selected Channel. + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR CIRC LL_DMA_SetMode + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + ARM GAS /tmp/ccak0twC.s page 18 + + + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** Mode); + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get DMA mode circular or normal. + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR CIRC LL_DMA_GetMode + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_CIRC)); + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Peripheral increment mode. + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOr + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** PeriphOrM2MSrcIncMode); + ARM GAS /tmp/ccak0twC.s page 19 + + + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Peripheral increment mode. + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_PINC)); + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Memory increment mode. + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOr + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryOrM2MDstIncMode); + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Memory increment mode. + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + ARM GAS /tmp/ccak0twC.s page 20 + + + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_MINC)); + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Peripheral size. + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2M + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** PeriphOrM2MSrcDataSize); + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Peripheral size. + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_PSIZE)); + ARM GAS /tmp/ccak0twC.s page 21 + + + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Memory size. + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2M + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryOrM2MDstDataSize); + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Memory size. + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_MSIZE)); + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Channel priority level. + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + ARM GAS /tmp/ccak0twC.s page 22 + + + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t P + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** Priority); + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel priority level. + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_PL)); + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set Number of data to transfer. + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note This action has no effect if + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * channel is enabled. + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CNDTR NDT LL_DMA_SetDataLength + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + ARM GAS /tmp/ccak0twC.s page 23 + + + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CNDTR_NDT, NbData); + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Number of data to transfer. + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Once the channel is enabled, the return value indicate the + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * remaining bytes to be transmitted. + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CNDTR NDT LL_DMA_GetDataLength + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CNDTR_NDT)); + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRe + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CMAR MA LL_DMA_ConfigAddresses + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddres +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** uint32_t DstAddress, uint32_t Direction) +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Direction Memory to Periph */ +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { + ARM GAS /tmp/ccak0twC.s page 24 + + +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SrcAddress); +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DstAddress); +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** else +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SrcAddress); +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DstAddress); +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set the Memory address. +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CMAR MA LL_DMA_SetMemoryAddress +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAd +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryAddress); +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set the Peripheral address. +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CPAR PA LL_DMA_SetPeriphAddress +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAd +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** PeriphAddress); + ARM GAS /tmp/ccak0twC.s page 25 + + +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Memory address. +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CMAR MA LL_DMA_GetMemoryAddress +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CMAR_MA)); +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Peripheral address. +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CPAR PA LL_DMA_GetPeriphAddress +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CPAR_PA)); +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 + ARM GAS /tmp/ccak0twC.s page 26 + + +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAd +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryAddress); +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAd +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]) +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryAddress); +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CPAR_PA)); +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccak0twC.s page 27 + + +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CMAR_MA)); +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Set DMA request for DMA instance on Channel x. +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @note Please refer to Reference Manual to get the available mapping of Request value link to +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C2S LL_DMA_SetPeriphRequest\n +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C3S LL_DMA_SetPeriphRequest\n +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C4S LL_DMA_SetPeriphRequest\n +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C5S LL_DMA_SetPeriphRequest\n +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C6S LL_DMA_SetPeriphRequest\n +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C7S LL_DMA_SetPeriphRequest +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param PeriphRequest This parameter can be one of the following values: +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_0 +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_1 +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_2 +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_3 +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_4 +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_5 +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_6 +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_7 +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_8 +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_9 +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_10 +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_11 +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_12 +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_13 +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_14 +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_15 +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRe +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + ARM GAS /tmp/ccak0twC.s page 28 + + + 93 .loc 2 1232 0 discriminator 36 + 94 0040 0500 movs r5, r0 + 95 0042 A835 adds r5, r5, #168 + 96 0044 2B68 ldr r3, [r5] + 97 .LVL4: + 98 0046 3A4A ldr r2, .L40+12 + 99 0048 8C18 adds r4, r1, r2 + 100 004a A400 lsls r4, r4, #2 + 101 004c 0F22 movs r2, #15 + 102 004e A240 lsls r2, r2, r4 + 103 0050 9343 bics r3, r2 + 104 0052 2B60 str r3, [r5] + 105 .LVL5: + 106 .LBE33: + 107 .LBE32: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset Request register field for DMAx Channel */ + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** if (Channel == LL_DMA_CHANNEL_1) + 108 .loc 1 221 0 discriminator 36 + 109 0054 0129 cmp r1, #1 + 110 0056 36D0 beq .L32 + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel1 */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI1(DMAx); + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_2) + 111 .loc 1 226 0 + 112 0058 0229 cmp r1, #2 + 113 005a 3AD0 beq .L33 + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel2 */ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI2(DMAx); + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_3) + 114 .loc 1 231 0 + 115 005c 0329 cmp r1, #3 + 116 005e 3ED0 beq .L34 + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel3 */ + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI3(DMAx); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_4) + 117 .loc 1 236 0 + 118 0060 0429 cmp r1, #4 + 119 0062 43D0 beq .L35 + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel4 */ + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI4(DMAx); + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_5) + 120 .loc 1 241 0 + 121 0064 0529 cmp r1, #5 + 122 0066 48D0 beq .L36 + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel5 */ + ARM GAS /tmp/ccak0twC.s page 29 + + + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI5(DMAx); + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined(DMA1_Channel6) + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_6) + 123 .loc 1 248 0 + 124 0068 0629 cmp r1, #6 + 125 006a 4DD0 beq .L37 + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel6 */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI6(DMAx); + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #endif + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #if defined(DMA1_Channel7) + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else if (Channel == LL_DMA_CHANNEL_7) + 126 .loc 1 255 0 + 127 006c 0729 cmp r1, #7 + 128 006e 52D0 beq .L38 + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Reset interrupt pending bits for DMAx Channel7 */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ClearFlag_GI7(DMAx); + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** #endif + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** else + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** status = ERROR; + 129 .loc 1 263 0 + 130 0070 0020 movs r0, #0 + 131 .LVL6: + 132 0072 03E0 b .L3 + 133 .LVL7: + 134 .L25: + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 135 .loc 1 176 0 + 136 0074 2C4B ldr r3, .L40+4 + 137 0076 9842 cmp r0, r3 + 138 0078 01D0 beq .L39 + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 139 .loc 1 196 0 + 140 007a 0020 movs r0, #0 + 141 .LVL8: + 142 .L3: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** return status; + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 143 .loc 1 268 0 + 144 @ sp needed + 145 007c 30BD pop {r4, r5, pc} + 146 .LVL9: + 147 .L39: + 148 .LBB34: + 149 .LBB35: + 150 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + ARM GAS /tmp/ccak0twC.s page 30 + + + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + ARM GAS /tmp/ccak0twC.s page 31 + + + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + ARM GAS /tmp/ccak0twC.s page 32 + + + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + ARM GAS /tmp/ccak0twC.s page 33 + + + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + ARM GAS /tmp/ccak0twC.s page 34 + + + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + ARM GAS /tmp/ccak0twC.s page 35 + + + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 151 .loc 3 319 0 + 152 007e 2D4B ldr r3, .L40+16 + 153 0080 1A6A ldr r2, [r3, #32] + 154 0082 0121 movs r1, #1 + 155 .LVL10: + 156 0084 0A43 orrs r2, r1 + 157 0086 1A62 str r2, [r3, #32] + 158 .LVL11: + 159 .LBE35: + 160 .LBE34: + 161 .LBB36: + 162 .LBB37: + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + ARM GAS /tmp/ccak0twC.s page 36 + + + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 163 .loc 3 344 0 + 164 0088 1A6A ldr r2, [r3, #32] + 165 008a 8A43 bics r2, r1 + 166 008c 1A62 str r2, [r3, #32] + 167 .LBE37: + 168 .LBE36: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 169 .loc 1 169 0 + 170 008e 0120 movs r0, #1 + 171 .LVL12: + 172 0090 F4E7 b .L3 + 173 .LVL13: + 174 .L26: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 175 .loc 1 201 0 discriminator 2 + 176 0092 0129 cmp r1, #1 + 177 0094 BBD1 bne .L4 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 178 .loc 1 201 0 is_stmt 0 + 179 0096 284B ldr r3, .L40+20 + 180 0098 C9E7 b .L5 + 181 .L27: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 182 .loc 1 201 0 discriminator 6 + 183 009a 0229 cmp r1, #2 + 184 009c BAD1 bne .L6 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 185 .loc 1 201 0 + 186 009e 274B ldr r3, .L40+24 + 187 00a0 C5E7 b .L5 + 188 .L28: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 189 .loc 1 201 0 discriminator 10 + 190 00a2 0329 cmp r1, #3 + 191 00a4 B9D1 bne .L7 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 192 .loc 1 201 0 + 193 00a6 264B ldr r3, .L40+28 + 194 00a8 C1E7 b .L5 + 195 .L29: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 196 .loc 1 201 0 discriminator 14 + 197 00aa 0429 cmp r1, #4 + 198 00ac B8D1 bne .L8 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + ARM GAS /tmp/ccak0twC.s page 37 + + + 199 .loc 1 201 0 + 200 00ae 254B ldr r3, .L40+32 + 201 00b0 BDE7 b .L5 + 202 .L30: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 203 .loc 1 201 0 discriminator 18 + 204 00b2 0529 cmp r1, #5 + 205 00b4 B7D1 bne .L9 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 206 .loc 1 201 0 + 207 00b6 244B ldr r3, .L40+36 + 208 00b8 B9E7 b .L5 + 209 .L31: + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 210 .loc 1 201 0 discriminator 21 + 211 00ba 0629 cmp r1, #6 + 212 00bc 01D0 beq .L23 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 213 .loc 1 201 0 + 214 00be 1B4B ldr r3, .L40+8 + 215 00c0 B5E7 b .L5 + 216 .L23: + 217 00c2 224B ldr r3, .L40+40 + 218 00c4 B3E7 b .L5 + 219 .LVL14: + 220 .L32: + 221 .LBB38: + 222 .LBB39: +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get DMA request for DMA instance on Channel x. +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C2S LL_DMA_GetPeriphRequest\n +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C3S LL_DMA_GetPeriphRequest\n +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C4S LL_DMA_GetPeriphRequest\n +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C5S LL_DMA_GetPeriphRequest\n +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C6S LL_DMA_GetPeriphRequest\n +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * CSELR C7S LL_DMA_GetPeriphRequest +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_0 +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_1 +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_2 +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_3 +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_4 +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_5 +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_6 + ARM GAS /tmp/ccak0twC.s page 38 + + +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_7 +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_8 +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_9 +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_10 +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_11 +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_12 +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_13 +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_14 +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @arg @ref LL_DMA_REQUEST_15 +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @} +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @{ +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 1 global interrupt flag. +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 2 global interrupt flag. +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 3 global interrupt flag. +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** + ARM GAS /tmp/ccak0twC.s page 39 + + +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 4 global interrupt flag. +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 5 global interrupt flag. +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 6 global interrupt flag. +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 7 global interrupt flag. +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 1 transfer complete flag. +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); + ARM GAS /tmp/ccak0twC.s page 40 + + +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 2 transfer complete flag. +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 3 transfer complete flag. +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 4 transfer complete flag. +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 5 transfer complete flag. +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 6 transfer complete flag. +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } + ARM GAS /tmp/ccak0twC.s page 41 + + +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 7 transfer complete flag. +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 1 half transfer flag. +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 2 half transfer flag. +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 3 half transfer flag. +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 4 half transfer flag. +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); + ARM GAS /tmp/ccak0twC.s page 42 + + +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 5 half transfer flag. +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 6 half transfer flag. +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 7 half transfer flag. +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 1 transfer error flag. +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 2 transfer error flag. +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) + ARM GAS /tmp/ccak0twC.s page 43 + + +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 3 transfer error flag. +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 4 transfer error flag. +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 5 transfer error flag. +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 6 transfer error flag. +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Get Channel 7 transfer error flag. +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval State of bit (1 or 0). +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ + ARM GAS /tmp/ccak0twC.s page 44 + + +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 1 global interrupt flag. +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); + 223 .loc 2 1618 0 is_stmt 1 + 224 00c6 4368 ldr r3, [r0, #4] + 225 00c8 0122 movs r2, #1 + 226 00ca 1343 orrs r3, r2 + 227 00cc 4360 str r3, [r0, #4] + 228 .LBE39: + 229 .LBE38: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 230 .loc 1 169 0 + 231 00ce 0120 movs r0, #1 + 232 .LVL15: + 233 00d0 D4E7 b .L3 + 234 .LVL16: + 235 .L33: + 236 .LBB40: + 237 .LBB41: +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 2 global interrupt flag. +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); + 238 .loc 2 1629 0 + 239 00d2 4368 ldr r3, [r0, #4] + 240 00d4 1022 movs r2, #16 + 241 00d6 1343 orrs r3, r2 + 242 00d8 4360 str r3, [r0, #4] + 243 .LBE41: + 244 .LBE40: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 245 .loc 1 169 0 + 246 00da 0120 movs r0, #1 + 247 .LVL17: + 248 00dc CEE7 b .L3 + 249 .LVL18: + 250 .L34: + 251 .LBB42: + ARM GAS /tmp/ccak0twC.s page 45 + + + 252 .LBB43: +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 3 global interrupt flag. +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); + 253 .loc 2 1640 0 + 254 00de 4268 ldr r2, [r0, #4] + 255 00e0 8023 movs r3, #128 + 256 00e2 5B00 lsls r3, r3, #1 + 257 00e4 1343 orrs r3, r2 + 258 00e6 4360 str r3, [r0, #4] + 259 .LBE43: + 260 .LBE42: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 261 .loc 1 169 0 + 262 00e8 0120 movs r0, #1 + 263 .LVL19: + 264 00ea C7E7 b .L3 + 265 .LVL20: + 266 .L35: + 267 .LBB44: + 268 .LBB45: +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 4 global interrupt flag. +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); + 269 .loc 2 1651 0 + 270 00ec 4268 ldr r2, [r0, #4] + 271 00ee 8023 movs r3, #128 + 272 00f0 5B01 lsls r3, r3, #5 + 273 00f2 1343 orrs r3, r2 + 274 00f4 4360 str r3, [r0, #4] + 275 .LBE45: + 276 .LBE44: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 277 .loc 1 169 0 + 278 00f6 0120 movs r0, #1 + 279 .LVL21: + 280 00f8 C0E7 b .L3 + 281 .LVL22: + 282 .L36: + 283 .LBB46: + 284 .LBB47: + ARM GAS /tmp/ccak0twC.s page 46 + + +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 5 global interrupt flag. +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); + 285 .loc 2 1662 0 + 286 00fa 4268 ldr r2, [r0, #4] + 287 00fc 8023 movs r3, #128 + 288 00fe 5B02 lsls r3, r3, #9 + 289 0100 1343 orrs r3, r2 + 290 0102 4360 str r3, [r0, #4] + 291 .LBE47: + 292 .LBE46: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 293 .loc 1 169 0 + 294 0104 0120 movs r0, #1 + 295 .LVL23: + 296 0106 B9E7 b .L3 + 297 .LVL24: + 298 .L37: + 299 .LBB48: + 300 .LBB49: +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel6) +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 6 global interrupt flag. +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); + 301 .loc 2 1674 0 + 302 0108 4268 ldr r2, [r0, #4] + 303 010a 8023 movs r3, #128 + 304 010c 5B03 lsls r3, r3, #13 + 305 010e 1343 orrs r3, r2 + 306 0110 4360 str r3, [r0, #4] + 307 .LBE49: + 308 .LBE48: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 309 .loc 1 169 0 + 310 0112 0120 movs r0, #1 + 311 .LVL25: + 312 0114 B2E7 b .L3 + 313 .LVL26: + 314 .L38: + 315 .LBB50: + 316 .LBB51: + ARM GAS /tmp/ccak0twC.s page 47 + + +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** } +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #endif +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** #if defined(DMA1_Channel7) +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** /** +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @brief Clear Channel 7 global interrupt flag. +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @param DMAx DMAx Instance +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** * @retval None +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** */ +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** { +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); + 317 .loc 2 1687 0 + 318 0116 4268 ldr r2, [r0, #4] + 319 0118 8023 movs r3, #128 + 320 011a 5B04 lsls r3, r3, #17 + 321 011c 1343 orrs r3, r2 + 322 011e 4360 str r3, [r0, #4] + 323 .LBE51: + 324 .LBE50: + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 325 .loc 1 169 0 + 326 0120 0120 movs r0, #1 + 327 .LVL27: + 328 0122 ABE7 b .L3 + 329 .L41: + 330 .align 2 + 331 .L40: + 332 0124 0000FFFF .word -65536 + 333 0128 00000240 .word 1073872896 + 334 012c 80000240 .word 1073873024 + 335 0130 FFFFFF3F .word 1073741823 + 336 0134 00100240 .word 1073876992 + 337 0138 08000240 .word 1073872904 + 338 013c 1C000240 .word 1073872924 + 339 0140 30000240 .word 1073872944 + 340 0144 44000240 .word 1073872964 + 341 0148 58000240 .word 1073872984 + 342 014c 6C000240 .word 1073873004 + 343 .cfi_endproc + 344 .LFE163: + 346 .section .text.LL_DMA_Init,"ax",%progbits + 347 .align 1 + 348 .global LL_DMA_Init + 349 .syntax unified + 350 .code 16 + 351 .thumb_func + 352 .fpu softvfp + 354 LL_DMA_Init: + 355 .LFB164: + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref __LL_DMA_GET_INSTANCE + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref __LL_DMA_GET_CHANNEL + ARM GAS /tmp/ccak0twC.s page 48 + + + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param DMAx DMAx Instance + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param Channel This parameter can be one of the following values: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_1 + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_2 + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_3 + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_4 + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_5 + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_6 (*) + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @arg @ref LL_DMA_CHANNEL_7 (*) + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * (*) value not defined in all devices + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @retval An ErrorStatus enumeration value: + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - SUCCESS: DMA registers are initialized + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - ERROR: Not applicable + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 356 .loc 1 292 0 + 357 .cfi_startproc + 358 @ args = 0, pretend = 0, frame = 0 + 359 @ frame_needed = 0, uses_anonymous_args = 0 + 360 .LVL28: + 361 0000 70B5 push {r4, r5, r6, lr} + 362 .LCFI1: + 363 .cfi_def_cfa_offset 16 + 364 .cfi_offset 4, -16 + 365 .cfi_offset 5, -12 + 366 .cfi_offset 6, -8 + 367 .cfi_offset 14, -4 + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Check the DMA Instance DMAx and Channel parameters*/ + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Check the DMA parameters from DMA_InitStruct */ + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /*---------------------------- DMAx CCR Configuration ------------------------ + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Configure DMAx_Channely: data transfer direction, data transfer mode, + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * peripheral and memory increment mode, + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * data size alignment and priority level with parameters : + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - Mode: DMA_CCR_CIRC bit + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - Priority: DMA_CCR_PL[1:0] bits + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + ARM GAS /tmp/ccak0twC.s page 49 + + + 368 .loc 1 319 0 + 369 0002 9368 ldr r3, [r2, #8] + 370 0004 D468 ldr r4, [r2, #12] + 371 0006 2343 orrs r3, r4 + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 372 .loc 1 320 0 + 373 0008 1469 ldr r4, [r2, #16] + 374 000a 2343 orrs r3, r4 + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + 375 .loc 1 321 0 + 376 000c 5469 ldr r4, [r2, #20] + 377 000e 2343 orrs r3, r4 + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstIncMode | \ + 378 .loc 1 322 0 + 379 0010 9469 ldr r4, [r2, #24] + 380 0012 2343 orrs r3, r4 + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + 381 .loc 1 323 0 + 382 0014 D469 ldr r4, [r2, #28] + 383 0016 2343 orrs r3, r4 + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 384 .loc 1 319 0 + 385 0018 946A ldr r4, [r2, #40] + 386 001a 2343 orrs r3, r4 + 387 .LVL29: + 388 .LBB52: + 389 .LBB53: + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_P + 390 .loc 2 598 0 + 391 001c 4C1E subs r4, r1, #1 + 392 001e 114D ldr r5, .L43 + 393 0020 2C5D ldrb r4, [r5, r4] + 394 0022 2418 adds r4, r4, r0 + 395 0024 2568 ldr r5, [r4] + 396 0026 104E ldr r6, .L43+4 + 397 0028 3540 ands r5, r6 + 398 002a 2B43 orrs r3, r5 + 399 .LVL30: + 400 002c 2360 str r3, [r4] + 401 .LVL31: + 402 .LBE53: + 403 .LBE52: + 404 .LBB54: + 405 .LBB55: +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** MemoryAddress); + 406 .loc 2 1038 0 + 407 002e E368 ldr r3, [r4, #12] + 408 0030 5368 ldr r3, [r2, #4] + 409 0032 E360 str r3, [r4, #12] + 410 .LVL32: + 411 .LBE55: + 412 .LBE54: + 413 .LBB56: + 414 .LBB57: +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** PeriphAddress); + 415 .loc 2 1060 0 + 416 0034 A368 ldr r3, [r4, #8] + ARM GAS /tmp/ccak0twC.s page 50 + + + 417 0036 1368 ldr r3, [r2] + 418 0038 A360 str r3, [r4, #8] + 419 .LVL33: + 420 .LBE57: + 421 .LBE56: + 422 .LBB58: + 423 .LBB59: + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CNDTR_NDT, NbData); + 424 .loc 2 951 0 + 425 003a 6368 ldr r3, [r4, #4] + 426 003c 1B0C lsrs r3, r3, #16 + 427 003e 1B04 lsls r3, r3, #16 + 428 0040 156A ldr r5, [r2, #32] + 429 0042 2B43 orrs r3, r5 + 430 0044 6360 str r3, [r4, #4] + 431 .LVL34: + 432 .LBE59: + 433 .LBE58: + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstDataSize | \ + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Priority); + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /*-------------------------- DMAx CMAR Configuration ------------------------- + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Configure the memory or destination base address with parameter : + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /*-------------------------- DMAx CPAR Configuration ------------------------- + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Configure the peripheral or source base address with parameter : + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /*--------------------------- DMAx CNDTR Configuration ----------------------- + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Configure the peripheral base address with parameter : + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - NbData: DMA_CNDTR_NDT[15:0] bits + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /*--------------------------- DMAx CSELR Configuration ----------------------- + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * Configure the peripheral base address with parameter : + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * - PeriphRequest: DMA_CSELR[31:0] bits + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); + 434 .loc 1 349 0 + 435 0046 526A ldr r2, [r2, #36] + 436 .LVL35: + 437 .LBB60: + 438 .LBB61: +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h **** DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); + 439 .loc 2 1232 0 + 440 0048 A830 adds r0, r0, #168 + 441 .LVL36: + 442 004a 0368 ldr r3, [r0] + 443 004c 074C ldr r4, .L43+8 + 444 004e A446 mov ip, r4 + 445 0050 6144 add r1, r1, ip + ARM GAS /tmp/ccak0twC.s page 51 + + + 446 .LVL37: + 447 0052 8900 lsls r1, r1, #2 + 448 .LVL38: + 449 0054 0F24 movs r4, #15 + 450 0056 8C40 lsls r4, r4, r1 + 451 0058 A343 bics r3, r4 + 452 005a 8A40 lsls r2, r2, r1 + 453 .LVL39: + 454 005c 1343 orrs r3, r2 + 455 005e 0360 str r3, [r0] + 456 .LVL40: + 457 .LBE61: + 458 .LBE60: + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** return SUCCESS; + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 459 .loc 1 352 0 + 460 0060 0120 movs r0, #1 + 461 .LVL41: + 462 @ sp needed + 463 0062 70BD pop {r4, r5, r6, pc} + 464 .L44: + 465 .align 2 + 466 .L43: + 467 0064 00000000 .word .LANCHOR0 + 468 0068 0F80FFFF .word -32753 + 469 006c FFFFFF3F .word 1073741823 + 470 .cfi_endproc + 471 .LFE164: + 473 .section .text.LL_DMA_StructInit,"ax",%progbits + 474 .align 1 + 475 .global LL_DMA_StructInit + 476 .syntax unified + 477 .code 16 + 478 .thumb_func + 479 .fpu softvfp + 481 LL_DMA_StructInit: + 482 .LFB165: + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /** + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** * @retval None + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** */ + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** { + 483 .loc 1 360 0 + 484 .cfi_startproc + 485 @ args = 0, pretend = 0, frame = 0 + 486 @ frame_needed = 0, uses_anonymous_args = 0 + 487 @ link register save eliminated. + 488 .LVL42: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** /* Set DMA_InitStruct fields to default values */ + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; + 489 .loc 1 362 0 + 490 0000 0023 movs r3, #0 + 491 0002 0360 str r3, [r0] + ARM GAS /tmp/ccak0twC.s page 52 + + + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + 492 .loc 1 363 0 + 493 0004 4360 str r3, [r0, #4] + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + 494 .loc 1 364 0 + 495 0006 8360 str r3, [r0, #8] + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + 496 .loc 1 365 0 + 497 0008 C360 str r3, [r0, #12] + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + 498 .loc 1 366 0 + 499 000a 0361 str r3, [r0, #16] + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + 500 .loc 1 367 0 + 501 000c 4361 str r3, [r0, #20] + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + 502 .loc 1 368 0 + 503 000e 8361 str r3, [r0, #24] + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + 504 .loc 1 369 0 + 505 0010 C361 str r3, [r0, #28] + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->NbData = (uint32_t)0x00000000U; + 506 .loc 1 370 0 + 507 0012 0362 str r3, [r0, #32] + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; + 508 .loc 1 371 0 + 509 0014 4362 str r3, [r0, #36] + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; + 510 .loc 1 372 0 + 511 0016 8362 str r3, [r0, #40] + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c **** } + 512 .loc 1 373 0 + 513 @ sp needed + 514 0018 7047 bx lr + 515 .cfi_endproc + 516 .LFE165: + 518 .section .rodata.CHANNEL_OFFSET_TAB,"a",%progbits + 519 .align 2 + 520 .set .LANCHOR0,. + 0 + 523 CHANNEL_OFFSET_TAB: + 524 0000 08 .byte 8 + 525 0001 1C .byte 28 + 526 0002 30 .byte 48 + 527 0003 44 .byte 68 + 528 0004 58 .byte 88 + 529 0005 6C .byte 108 + 530 0006 80 .byte -128 + 531 .text + 532 .Letext0: + 533 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 534 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 535 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 536 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 537 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 538 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 539 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 540 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + ARM GAS /tmp/ccak0twC.s page 53 + + + 541 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccak0twC.s page 54 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_dma.c + /tmp/ccak0twC.s:16 .text.LL_DMA_DeInit:0000000000000000 $t + /tmp/ccak0twC.s:23 .text.LL_DMA_DeInit:0000000000000000 LL_DMA_DeInit + /tmp/ccak0twC.s:332 .text.LL_DMA_DeInit:0000000000000124 $d + /tmp/ccak0twC.s:347 .text.LL_DMA_Init:0000000000000000 $t + /tmp/ccak0twC.s:354 .text.LL_DMA_Init:0000000000000000 LL_DMA_Init + /tmp/ccak0twC.s:467 .text.LL_DMA_Init:0000000000000064 $d + /tmp/ccak0twC.s:474 .text.LL_DMA_StructInit:0000000000000000 $t + /tmp/ccak0twC.s:481 .text.LL_DMA_StructInit:0000000000000000 LL_DMA_StructInit + /tmp/ccak0twC.s:519 .rodata.CHANNEL_OFFSET_TAB:0000000000000000 $d + /tmp/ccak0twC.s:523 .rodata.CHANNEL_OFFSET_TAB:0000000000000000 CHANNEL_OFFSET_TAB + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_exti.d b/build/stm32l0xx_ll_exti.d new file mode 100644 index 0000000..1a81d5e --- /dev/null +++ b/build/stm32l0xx_ll_exti.d @@ -0,0 +1,106 @@ +build/stm32l0xx_ll_exti.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_ll_exti.lst b/build/stm32l0xx_ll_exti.lst new file mode 100644 index 0000000..1a43fda --- /dev/null +++ b/build/stm32l0xx_ll_exti.lst @@ -0,0 +1,1445 @@ +ARM GAS /tmp/ccuBrfDN.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_exti.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_EXTI_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_EXTI_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_EXTI_DeInit: + 24 .LFB55: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @file stm32l0xx_ll_exti.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @brief EXTI LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** ****************************************************************************** + ARM GAS /tmp/ccuBrfDN.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #include "stm32l0xx_ll_exti.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #ifdef USE_FULL_ASSERT + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #include "stm32_assert.h" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #else + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #define assert_param(expr) ((void)0U) + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #endif + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** @addtogroup STM32L0xx_LL_Driver + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @{ + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #if defined (EXTI) + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** @defgroup EXTI_LL EXTI + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @{ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Private types -------------------------------------------------------------*/ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Private variables ---------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Private constants ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Private macros ------------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** @addtogroup EXTI_LL_Private_Macros + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @{ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x0 + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLIN + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @} + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Exported functions --------------------------------------------------------*/ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** @addtogroup EXTI_LL_Exported_Functions + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @{ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** @addtogroup EXTI_LL_EF_Init + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @{ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** + ARM GAS /tmp/ccuBrfDN.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @brief De-initialize the EXTI registers to their default reset values. + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * - SUCCESS: EXTI registers are de-initialized + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * - ERROR: not applicable + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** uint32_t LL_EXTI_DeInit(void) + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 26 .loc 1 97 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Interrupt mask register set to default reset values */ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x3F840000U); + 31 .loc 1 99 0 + 32 0000 054B ldr r3, .L2 + 33 0002 064A ldr r2, .L2+4 + 34 0004 1A60 str r2, [r3] + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Event mask register set to default reset values */ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(EMR, 0x00000000U); + 35 .loc 1 101 0 + 36 0006 0022 movs r2, #0 + 37 0008 5A60 str r2, [r3, #4] + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Rising Trigger selection register set to default reset values */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(RTSR, 0x00000000U); + 38 .loc 1 103 0 + 39 000a 9A60 str r2, [r3, #8] + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Falling Trigger selection register set to default reset values */ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(FTSR, 0x00000000U); + 40 .loc 1 105 0 + 41 000c DA60 str r2, [r3, #12] + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Software interrupt event register set to default reset values */ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(SWIER, 0x00000000U); + 42 .loc 1 107 0 + 43 000e 1A61 str r2, [r3, #16] + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Pending register set to default reset values */ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_WriteReg(PR, 0x007BFFFFU); + 44 .loc 1 109 0 + 45 0010 034A ldr r2, .L2+8 + 46 0012 5A61 str r2, [r3, #20] + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** return SUCCESS; + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 47 .loc 1 112 0 + 48 0014 0120 movs r0, #1 + 49 @ sp needed + 50 0016 7047 bx lr + 51 .L3: + 52 .align 2 + 53 .L2: + 54 0018 00040140 .word 1073808384 + 55 001c 0000843F .word 1065615360 + 56 0020 FFFF7B00 .word 8126463 + 57 .cfi_endproc + 58 .LFE55: + 60 .section .text.LL_EXTI_Init,"ax",%progbits + 61 .align 1 + ARM GAS /tmp/ccuBrfDN.s page 4 + + + 62 .global LL_EXTI_Init + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 LL_EXTI_Init: + 69 .LFB56: + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * - SUCCESS: EXTI registers are initialized + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * - ERROR: not applicable + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 70 .loc 1 122 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .LVL0: + 75 0000 10B5 push {r4, lr} + 76 .LCFI0: + 77 .cfi_def_cfa_offset 8 + 78 .cfi_offset 4, -8 + 79 .cfi_offset 14, -4 + 80 .LVL1: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** ErrorStatus status = SUCCESS; + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* ENABLE LineCommand */ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** if (EXTI_InitStruct->LineCommand != DISABLE) + 81 .loc 1 130 0 + 82 0002 0379 ldrb r3, [r0, #4] + 83 0004 002B cmp r3, #0 + 84 0006 51D0 beq .L5 + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Configure EXTI Lines in range from 0 to 31 */ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + 85 .loc 1 135 0 + 86 0008 0368 ldr r3, [r0] + 87 000a 002B cmp r3, #0 + 88 000c 5AD0 beq .L14 + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** switch (EXTI_InitStruct->Mode) + 89 .loc 1 137 0 + 90 000e 4279 ldrb r2, [r0, #5] + 91 0010 012A cmp r2, #1 + 92 0012 19D0 beq .L8 + 93 0014 002A cmp r2, #0 + 94 0016 03D0 beq .L9 + ARM GAS /tmp/ccuBrfDN.s page 5 + + + 95 0018 022A cmp r2, #2 + 96 001a 1FD0 beq .L10 + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_MODE_IT: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* First Disable Event on provided Lines */ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Then Enable IT on provided Lines */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_MODE_EVENT: + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* First Disable IT on provided Lines */ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Then Enable Event on provided Lines */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_MODE_IT_EVENT: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Directly Enable IT & Event on provided Lines */ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** default: + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** status = ERROR; + 97 .loc 1 157 0 + 98 001c 0023 movs r3, #0 + 99 001e 08E0 b .L7 + 100 .L9: + 101 .LVL2: + 102 .LBB30: + 103 .LBB31: + 104 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @file stm32l0xx_ll_exti.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Header file of EXTI LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + ARM GAS /tmp/ccuBrfDN.s page 6 + + + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #ifndef __STM32L0xx_LL_EXTI_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define __STM32L0xx_LL_EXTI_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined (EXTI) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL EXTI + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Private Macros ------------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Exported types ------------------------------------------------------------*/ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** typedef struct + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines i + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** This parameter can be any combination of @ref EXTI_LL_EC_LINE + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** This parameter can be set either to ENABLE or DISABLE */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + ARM GAS /tmp/ccuBrfDN.s page 7 + + + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } LL_EXTI_InitTypeDef; + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Exported constants --------------------------------------------------------*/ + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_LINE LINE + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM16) + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM18) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM20) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM21) + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM22) + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM24) + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM25) + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ + ARM GAS /tmp/ccuBrfDN.s page 8 + + + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM26) + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM27) + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM28) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM29) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM30) + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(EXTI_IMR_IM31) + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_MODE Mode + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + ARM GAS /tmp/ccuBrfDN.s page 9 + + + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Exported macro ------------------------------------------------------------*/ + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Write a value in EXTI register + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param __REG__ Register to be written + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param __VALUE__ Value to be written in the register + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Read a value in EXTI register + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param __REG__ Register to be read + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval Register value + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /* Exported functions --------------------------------------------------------*/ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_IT_Management IT_Management + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Bits are set automatically at Power on. + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + ARM GAS /tmp/ccuBrfDN.s page 10 + + + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** SET_BIT(EXTI->IMR, ExtiLine); + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Bits are set automatically at Power on. + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + ARM GAS /tmp/ccuBrfDN.s page 11 + + + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** CLEAR_BIT(EXTI->IMR, ExtiLine); + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Bits are set automatically at Power on. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + ARM GAS /tmp/ccuBrfDN.s page 12 + + + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Event_Management Event_Management + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + ARM GAS /tmp/ccuBrfDN.s page 13 + + + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** SET_BIT(EXTI->EMR, ExtiLine); + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + ARM GAS /tmp/ccuBrfDN.s page 14 + + + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** CLEAR_BIT(EXTI->EMR, ExtiLine); + 105 .loc 2 490 0 + 106 0020 294A ldr r2, .L20 + 107 0022 5168 ldr r1, [r2, #4] + 108 0024 9943 bics r1, r3 + 109 0026 5160 str r1, [r2, #4] + 110 .LVL3: + 111 .LBE31: + 112 .LBE30: + 113 .LBB32: + 114 .LBB33: + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 115 .loc 2 292 0 + 116 0028 1368 ldr r3, [r2] + 117 002a 0168 ldr r1, [r0] + 118 002c 0B43 orrs r3, r1 + 119 002e 1360 str r3, [r2] + 120 .LVL4: + 121 .LBE33: + 122 .LBE32: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 123 .loc 1 123 0 + 124 0030 0123 movs r3, #1 + 125 .LVL5: + 126 .L7: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + 127 .loc 1 160 0 + 128 0032 8279 ldrb r2, [r0, #6] + 129 0034 002A cmp r2, #0 + 130 0036 43D0 beq .L6 + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** switch (EXTI_InitStruct->Trigger) + 131 .loc 1 162 0 + 132 0038 022A cmp r2, #2 + 133 003a 23D0 beq .L11 + 134 003c 032A cmp r2, #3 + 135 003e 2BD0 beq .L12 + 136 0040 012A cmp r2, #1 + 137 0042 15D0 beq .L19 + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING: + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* First Disable Falling Trigger on provided Lines */ + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Then Enable Rising Trigger on provided Lines */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_TRIGGER_FALLING: + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* First Disable Rising Trigger on provided Lines */ + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + ARM GAS /tmp/ccuBrfDN.s page 15 + + + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Then Enable Falling Trigger on provided Lines */ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING_FALLING: + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** default: + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** status = ERROR; + 138 .loc 1 181 0 + 139 0044 0023 movs r3, #0 + 140 .LVL6: + 141 0046 3BE0 b .L6 + 142 .LVL7: + 143 .L8: + 144 .LBB34: + 145 .LBB35: + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 146 .loc 2 340 0 + 147 0048 1F4A ldr r2, .L20 + 148 004a 1168 ldr r1, [r2] + 149 004c 9943 bics r1, r3 + 150 004e 1160 str r1, [r2] + 151 .LVL8: + 152 .LBE35: + 153 .LBE34: + 154 .LBB36: + 155 .LBB37: + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 156 .loc 2 443 0 + 157 0050 5368 ldr r3, [r2, #4] + 158 0052 0168 ldr r1, [r0] + 159 0054 0B43 orrs r3, r1 + 160 0056 5360 str r3, [r2, #4] + 161 .LVL9: + 162 .LBE37: + 163 .LBE36: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 164 .loc 1 123 0 + 165 0058 0123 movs r3, #1 + 166 005a EAE7 b .L7 + 167 .LVL10: + 168 .L10: + 169 .LBB38: + 170 .LBB39: + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 171 .loc 2 292 0 + 172 005c 1A4A ldr r2, .L20 + 173 005e 1168 ldr r1, [r2] + 174 0060 0B43 orrs r3, r1 + 175 .LVL11: + 176 0062 1360 str r3, [r2] + 177 .LVL12: + 178 .LBE39: + 179 .LBE38: + 180 .LBB40: + 181 .LBB41: + ARM GAS /tmp/ccuBrfDN.s page 16 + + + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 182 .loc 2 443 0 + 183 0064 5368 ldr r3, [r2, #4] + 184 0066 0168 ldr r1, [r0] + 185 0068 0B43 orrs r3, r1 + 186 006a 5360 str r3, [r2, #4] + 187 .LVL13: + 188 .LBE41: + 189 .LBE40: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 190 .loc 1 123 0 + 191 006c 0123 movs r3, #1 + 192 006e E0E7 b .L7 + 193 .LVL14: + 194 .L19: + 195 .LBB42: + 196 .LBB43: + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + ARM GAS /tmp/ccuBrfDN.s page 17 + + + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * pending bit is not set. + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * condition. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + ARM GAS /tmp/ccuBrfDN.s page 18 + + + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** SET_BIT(EXTI->RTSR, ExtiLine); + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * pending bit is not set. + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * condition. + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** CLEAR_BIT(EXTI->RTSR, ExtiLine); + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + ARM GAS /tmp/ccuBrfDN.s page 19 + + + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @} + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @{ + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * generated on these lines. If a falling edge on a configurable interrupt + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * pending bit is not set. + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * condition. + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + ARM GAS /tmp/ccuBrfDN.s page 20 + + + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** SET_BIT(EXTI->FTSR, ExtiLine); + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** /** + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * generated on these lines. If a Falling edge on a configurable interrupt + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * pending bit is not set. + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * Rising and falling edge triggers can be set for the same interrupt line. + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * In this case, both generate a trigger condition. + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + ARM GAS /tmp/ccuBrfDN.s page 21 + + + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** * @retval None + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** */ + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** { + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** CLEAR_BIT(EXTI->FTSR, ExtiLine); + 197 .loc 2 772 0 + 198 0070 154A ldr r2, .L20 + 199 0072 D168 ldr r1, [r2, #12] + 200 0074 0468 ldr r4, [r0] + 201 0076 A143 bics r1, r4 + 202 0078 D160 str r1, [r2, #12] + 203 .LVL15: + 204 .LBE43: + 205 .LBE42: + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 206 .loc 1 168 0 + 207 007a 0168 ldr r1, [r0] + 208 .LVL16: + 209 .LBB44: + 210 .LBB45: + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 211 .loc 2 590 0 + 212 007c 9068 ldr r0, [r2, #8] + 213 .LVL17: + 214 007e 0143 orrs r1, r0 + 215 .LVL18: + 216 0080 9160 str r1, [r2, #8] + 217 .LVL19: + 218 0082 1DE0 b .L6 + 219 .LVL20: + 220 .L11: + 221 .LBE45: + 222 .LBE44: + 223 .LBB46: + 224 .LBB47: + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 225 .loc 2 636 0 + 226 0084 104A ldr r2, .L20 + 227 0086 9168 ldr r1, [r2, #8] + 228 0088 0468 ldr r4, [r0] + 229 008a A143 bics r1, r4 + 230 008c 9160 str r1, [r2, #8] + 231 .LVL21: + 232 .LBE47: + 233 .LBE46: + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 234 .loc 1 174 0 + 235 008e 0168 ldr r1, [r0] + ARM GAS /tmp/ccuBrfDN.s page 22 + + + 236 .LVL22: + 237 .LBB48: + 238 .LBB49: + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 239 .loc 2 728 0 + 240 0090 D068 ldr r0, [r2, #12] + 241 .LVL23: + 242 0092 0143 orrs r1, r0 + 243 .LVL24: + 244 0094 D160 str r1, [r2, #12] + 245 .LVL25: + 246 0096 13E0 b .L6 + 247 .LVL26: + 248 .L12: + 249 .LBE49: + 250 .LBE48: + 251 .LBB50: + 252 .LBB51: + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** + 253 .loc 2 590 0 + 254 0098 0B4A ldr r2, .L20 + 255 009a 9168 ldr r1, [r2, #8] + 256 009c 0468 ldr r4, [r0] + 257 009e 2143 orrs r1, r4 + 258 00a0 9160 str r1, [r2, #8] + 259 .LVL27: + 260 .LBE51: + 261 .LBE50: + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 262 .loc 1 178 0 + 263 00a2 0168 ldr r1, [r0] + 264 .LVL28: + 265 .LBB52: + 266 .LBB53: + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 267 .loc 2 728 0 + 268 00a4 D068 ldr r0, [r2, #12] + 269 .LVL29: + 270 00a6 0143 orrs r1, r0 + 271 .LVL30: + 272 00a8 D160 str r1, [r2, #12] + 273 .LVL31: + 274 00aa 09E0 b .L6 + 275 .LVL32: + 276 .L5: + 277 .LBE53: + 278 .LBE52: + 279 .LBB54: + 280 .LBB55: + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 281 .loc 2 340 0 + 282 00ac 064B ldr r3, .L20 + 283 00ae 1A68 ldr r2, [r3] + 284 00b0 0168 ldr r1, [r0] + 285 00b2 8A43 bics r2, r1 + 286 00b4 1A60 str r2, [r3] + 287 .LVL33: + ARM GAS /tmp/ccuBrfDN.s page 23 + + + 288 .LBE55: + 289 .LBE54: + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** break; + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* DISABLE LineCommand */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** else + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* De-configure EXTI Lines in range from 0 to 31 */ + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + 290 .loc 1 192 0 + 291 00b6 0168 ldr r1, [r0] + 292 .LVL34: + 293 .LBB56: + 294 .LBB57: + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h **** } + 295 .loc 2 490 0 + 296 00b8 5A68 ldr r2, [r3, #4] + 297 00ba 8A43 bics r2, r1 + 298 00bc 5A60 str r2, [r3, #4] + 299 .LBE57: + 300 .LBE56: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 301 .loc 1 123 0 + 302 00be 0123 movs r3, #1 + 303 .LVL35: + 304 .L6: + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** return status; + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 305 .loc 1 195 0 + 306 00c0 1800 movs r0, r3 + 307 @ sp needed + 308 00c2 10BD pop {r4, pc} + 309 .LVL36: + 310 .L14: + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /* Check the parameters */ + 311 .loc 1 123 0 + 312 00c4 0123 movs r3, #1 + 313 00c6 FBE7 b .L6 + 314 .L21: + 315 .align 2 + 316 .L20: + 317 00c8 00040140 .word 1073808384 + 318 .cfi_endproc + 319 .LFE56: + 321 .section .text.LL_EXTI_StructInit,"ax",%progbits + 322 .align 1 + 323 .global LL_EXTI_StructInit + 324 .syntax unified + 325 .code 16 + 326 .thumb_func + 327 .fpu softvfp + 329 LL_EXTI_StructInit: + ARM GAS /tmp/ccuBrfDN.s page 24 + + + 330 .LFB57: + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** /** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** * @retval None + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** */ + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** { + 331 .loc 1 203 0 + 332 .cfi_startproc + 333 @ args = 0, pretend = 0, frame = 0 + 334 @ frame_needed = 0, uses_anonymous_args = 0 + 335 @ link register save eliminated. + 336 .LVL37: + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + 337 .loc 1 204 0 + 338 0000 0023 movs r3, #0 + 339 0002 0360 str r3, [r0] + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** EXTI_InitStruct->LineCommand = DISABLE; + 340 .loc 1 205 0 + 341 0004 0371 strb r3, [r0, #4] + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + 342 .loc 1 206 0 + 343 0006 4371 strb r3, [r0, #5] + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; + 344 .loc 1 207 0 + 345 0008 0233 adds r3, r3, #2 + 346 000a 8371 strb r3, [r0, #6] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c **** } + 347 .loc 1 208 0 + 348 @ sp needed + 349 000c 7047 bx lr + 350 .cfi_endproc + 351 .LFE57: + 353 .text + 354 .Letext0: + 355 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 356 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 357 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 358 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 359 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 360 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 361 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 362 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 363 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccuBrfDN.s page 25 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_exti.c + /tmp/ccuBrfDN.s:16 .text.LL_EXTI_DeInit:0000000000000000 $t + /tmp/ccuBrfDN.s:23 .text.LL_EXTI_DeInit:0000000000000000 LL_EXTI_DeInit + /tmp/ccuBrfDN.s:54 .text.LL_EXTI_DeInit:0000000000000018 $d + /tmp/ccuBrfDN.s:61 .text.LL_EXTI_Init:0000000000000000 $t + /tmp/ccuBrfDN.s:68 .text.LL_EXTI_Init:0000000000000000 LL_EXTI_Init + /tmp/ccuBrfDN.s:317 .text.LL_EXTI_Init:00000000000000c8 $d + /tmp/ccuBrfDN.s:322 .text.LL_EXTI_StructInit:0000000000000000 $t + /tmp/ccuBrfDN.s:329 .text.LL_EXTI_StructInit:0000000000000000 LL_EXTI_StructInit + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_gpio.d b/build/stm32l0xx_ll_gpio.d new file mode 100644 index 0000000..75462b6 --- /dev/null +++ b/build/stm32l0xx_ll_gpio.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_gpio.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_gpio.lst b/build/stm32l0xx_ll_gpio.lst new file mode 100644 index 0000000..2bfe091 --- /dev/null +++ b/build/stm32l0xx_ll_gpio.lst @@ -0,0 +1,2610 @@ +ARM GAS /tmp/ccKYQ5mH.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_gpio.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_GPIO_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_GPIO_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_GPIO_DeInit: + 24 .LFB90: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @file stm32l0xx_ll_gpio.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @brief GPIO LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ****************************************************************************** + ARM GAS /tmp/ccKYQ5mH.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #include "stm32l0xx_ll_gpio.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #ifdef USE_FULL_ASSERT + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #include "stm32_assert.h" + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #else + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define assert_param(expr) ((void)0U) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #endif + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** @addtogroup STM32L0xx_LL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** @addtogroup GPIO_LL + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Private types -------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Private constants ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Private_Macros + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_DOWN)) + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_7 )) + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** + ARM GAS /tmp/ccKYQ5mH.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @} + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Exported_Functions + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @{ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_EF_Init + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @{ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @brief De-initialize GPIO registers (Registers restored to their default values). + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @param GPIOx GPIO Port + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * - SUCCESS: GPIO registers are de-initialized + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * - ERROR: Wrong GPIO Port + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 26 .loc 1 113 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ErrorStatus status = SUCCESS; + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Check the parameters */ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Force and Release reset on clock of GPIOx Port */ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if (GPIOx == GPIOA) + 32 .loc 1 120 0 + 33 0000 A023 movs r3, #160 + 34 0002 DB05 lsls r3, r3, #23 + 35 0004 9842 cmp r0, r3 + 36 0006 10D0 beq .L9 + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA); + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA); + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else if (GPIOx == GPIOB) + 37 .loc 1 125 0 + 38 0008 264B ldr r3, .L15 + 39 000a 9842 cmp r0, r3 + 40 000c 17D0 beq .L10 + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB); + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB); + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else if (GPIOx == GPIOC) + 41 .loc 1 130 0 + 42 000e 264B ldr r3, .L15+4 + ARM GAS /tmp/ccKYQ5mH.s page 4 + + + 43 0010 9842 cmp r0, r3 + 44 0012 1ED0 beq .L11 + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC); + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC); + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #if defined(GPIOD) + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else if (GPIOx == GPIOD) + 45 .loc 1 136 0 + 46 0014 254B ldr r3, .L15+8 + 47 0016 9842 cmp r0, r3 + 48 0018 25D0 beq .L12 + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD); + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD); + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #endif /* GPIOD */ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #if defined(GPIOE) + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else if (GPIOx == GPIOE) + 49 .loc 1 143 0 + 50 001a 254B ldr r3, .L15+12 + 51 001c 9842 cmp r0, r3 + 52 001e 2CD0 beq .L13 + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE); + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE); + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #endif /* GPIOE */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #if defined(GPIOH) + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else if (GPIOx == GPIOH) + 53 .loc 1 150 0 + 54 0020 244B ldr r3, .L15+16 + 55 0022 9842 cmp r0, r3 + 56 0024 33D0 beq .L14 + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOH); + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOH); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** #endif /* GPIOH */ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** status = ERROR; + 57 .loc 1 158 0 + 58 0026 0020 movs r0, #0 + 59 .LVL1: + 60 0028 08E0 b .L3 + 61 .LVL2: + 62 .L9: + 63 .LBB38: + 64 .LBB39: + 65 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/ccKYQ5mH.s page 5 + + + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/ccKYQ5mH.s page 6 + + + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + ARM GAS /tmp/ccKYQ5mH.s page 7 + + + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + ARM GAS /tmp/ccKYQ5mH.s page 8 + + + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + ARM GAS /tmp/ccKYQ5mH.s page 9 + + + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + ARM GAS /tmp/ccKYQ5mH.s page 10 + + + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + ARM GAS /tmp/ccKYQ5mH.s page 11 + + + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + ARM GAS /tmp/ccKYQ5mH.s page 12 + + + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + ARM GAS /tmp/ccKYQ5mH.s page 13 + + + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/ccKYQ5mH.s page 14 + + + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccKYQ5mH.s page 15 + + + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccKYQ5mH.s page 16 + + + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + ARM GAS /tmp/ccKYQ5mH.s page 17 + + + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1SMENR, Periphs); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + ARM GAS /tmp/ccKYQ5mH.s page 18 + + + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1SMENR, Periphs); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + ARM GAS /tmp/ccKYQ5mH.s page 19 + + + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + ARM GAS /tmp/ccKYQ5mH.s page 20 + + + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB2 peripherals reset. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB2 peripherals reset. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + ARM GAS /tmp/ccKYQ5mH.s page 21 + + + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2SMENR, Periphs); + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2SMENR, Periphs); + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + ARM GAS /tmp/ccKYQ5mH.s page 22 + + + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_IOP IOP + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable IOP peripherals clock. + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->IOPENR, Periphs); +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->IOPENR, Periphs); +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if IOP peripheral clock is enabled or not +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/ccKYQ5mH.s page 23 + + +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->IOPENR, Periphs) == Periphs); +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable IOP peripherals clock. +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->IOPENR, Periphs); +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable IOP peripherals clock. +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_ALL +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->IOPRSTR, Periphs); + 66 .loc 2 1082 0 + 67 002a 234B ldr r3, .L15+20 + 68 002c DA69 ldr r2, [r3, #28] + 69 002e 0121 movs r1, #1 + 70 0030 0A43 orrs r2, r1 + 71 0032 DA61 str r2, [r3, #28] + 72 .LVL3: + ARM GAS /tmp/ccKYQ5mH.s page 24 + + + 73 .LBE39: + 74 .LBE38: + 75 .LBB40: + 76 .LBB41: +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release IOP peripherals reset. +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_ALL +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->IOPRSTR, Periphs); + 77 .loc 2 1107 0 + 78 0034 DA69 ldr r2, [r3, #28] + 79 0036 8A43 bics r2, r1 + 80 0038 DA61 str r2, [r3, #28] + 81 .LBE41: + 82 .LBE40: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 83 .loc 1 114 0 + 84 003a 0120 movs r0, #1 + 85 .LVL4: + 86 .L3: + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** return (status); + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 87 .loc 1 162 0 + 88 @ sp needed + 89 003c 7047 bx lr + 90 .LVL5: + 91 .L10: + 92 .LBB42: + 93 .LBB43: +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 94 .loc 2 1082 0 + 95 003e 1E4B ldr r3, .L15+20 + 96 0040 DA69 ldr r2, [r3, #28] + 97 0042 0221 movs r1, #2 + 98 0044 0A43 orrs r2, r1 + ARM GAS /tmp/ccKYQ5mH.s page 25 + + + 99 0046 DA61 str r2, [r3, #28] + 100 .LVL6: + 101 .LBE43: + 102 .LBE42: + 103 .LBB44: + 104 .LBB45: + 105 .loc 2 1107 0 + 106 0048 DA69 ldr r2, [r3, #28] + 107 004a 8A43 bics r2, r1 + 108 004c DA61 str r2, [r3, #28] + 109 .LBE45: + 110 .LBE44: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 111 .loc 1 114 0 + 112 004e 0120 movs r0, #1 + 113 .LVL7: + 114 0050 F4E7 b .L3 + 115 .LVL8: + 116 .L11: + 117 .LBB46: + 118 .LBB47: +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 119 .loc 2 1082 0 + 120 0052 194B ldr r3, .L15+20 + 121 0054 DA69 ldr r2, [r3, #28] + 122 0056 0421 movs r1, #4 + 123 0058 0A43 orrs r2, r1 + 124 005a DA61 str r2, [r3, #28] + 125 .LVL9: + 126 .LBE47: + 127 .LBE46: + 128 .LBB48: + 129 .LBB49: + 130 .loc 2 1107 0 + 131 005c DA69 ldr r2, [r3, #28] + 132 005e 8A43 bics r2, r1 + 133 0060 DA61 str r2, [r3, #28] + 134 .LBE49: + 135 .LBE48: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 136 .loc 1 114 0 + 137 0062 0120 movs r0, #1 + 138 .LVL10: + 139 0064 EAE7 b .L3 + 140 .LVL11: + 141 .L12: + 142 .LBB50: + 143 .LBB51: +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 144 .loc 2 1082 0 + 145 0066 144B ldr r3, .L15+20 + 146 0068 DA69 ldr r2, [r3, #28] + 147 006a 0821 movs r1, #8 + 148 006c 0A43 orrs r2, r1 + 149 006e DA61 str r2, [r3, #28] + 150 .LVL12: + 151 .LBE51: + ARM GAS /tmp/ccKYQ5mH.s page 26 + + + 152 .LBE50: + 153 .LBB52: + 154 .LBB53: + 155 .loc 2 1107 0 + 156 0070 DA69 ldr r2, [r3, #28] + 157 0072 8A43 bics r2, r1 + 158 0074 DA61 str r2, [r3, #28] + 159 .LBE53: + 160 .LBE52: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 161 .loc 1 114 0 + 162 0076 0120 movs r0, #1 + 163 .LVL13: + 164 0078 E0E7 b .L3 + 165 .LVL14: + 166 .L13: + 167 .LBB54: + 168 .LBB55: +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 169 .loc 2 1082 0 + 170 007a 0F4B ldr r3, .L15+20 + 171 007c DA69 ldr r2, [r3, #28] + 172 007e 1021 movs r1, #16 + 173 0080 0A43 orrs r2, r1 + 174 0082 DA61 str r2, [r3, #28] + 175 .LVL15: + 176 .LBE55: + 177 .LBE54: + 178 .LBB56: + 179 .LBB57: + 180 .loc 2 1107 0 + 181 0084 DA69 ldr r2, [r3, #28] + 182 0086 8A43 bics r2, r1 + 183 0088 DA61 str r2, [r3, #28] + 184 .LBE57: + 185 .LBE56: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 186 .loc 1 114 0 + 187 008a 0120 movs r0, #1 + 188 .LVL16: + 189 008c D6E7 b .L3 + 190 .LVL17: + 191 .L14: + 192 .LBB58: + 193 .LBB59: +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 194 .loc 2 1082 0 + 195 008e 0A4B ldr r3, .L15+20 + 196 0090 DA69 ldr r2, [r3, #28] + 197 0092 8021 movs r1, #128 + 198 0094 0A43 orrs r2, r1 + 199 0096 DA61 str r2, [r3, #28] + 200 .LVL18: + 201 .LBE59: + 202 .LBE58: + 203 .LBB60: + 204 .LBB61: + ARM GAS /tmp/ccKYQ5mH.s page 27 + + + 205 .loc 2 1107 0 + 206 0098 DA69 ldr r2, [r3, #28] + 207 009a 8A43 bics r2, r1 + 208 009c DA61 str r2, [r3, #28] + 209 .LBE61: + 210 .LBE60: + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 211 .loc 1 114 0 + 212 009e 0120 movs r0, #1 + 213 .LVL19: + 214 00a0 CCE7 b .L3 + 215 .L16: + 216 00a2 C046 .align 2 + 217 .L15: + 218 00a4 00040050 .word 1342178304 + 219 00a8 00080050 .word 1342179328 + 220 00ac 000C0050 .word 1342180352 + 221 00b0 00100050 .word 1342181376 + 222 00b4 001C0050 .word 1342184448 + 223 00b8 00100240 .word 1073876992 + 224 .cfi_endproc + 225 .LFE90: + 227 .section .text.LL_GPIO_Init,"ax",%progbits + 228 .align 1 + 229 .global LL_GPIO_Init + 230 .syntax unified + 231 .code 16 + 232 .thumb_func + 233 .fpu softvfp + 235 LL_GPIO_Init: + 236 .LFB91: + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @param GPIOx GPIO Port + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * that contains the configuration information for the specified GPIO peripheral. + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * - ERROR: Not applicable + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 237 .loc 1 174 0 + 238 .cfi_startproc + 239 @ args = 0, pretend = 0, frame = 0 + 240 @ frame_needed = 0, uses_anonymous_args = 0 + 241 .LVL20: + 242 0000 F0B5 push {r4, r5, r6, r7, lr} + 243 .LCFI0: + 244 .cfi_def_cfa_offset 20 + 245 .cfi_offset 4, -20 + 246 .cfi_offset 5, -16 + 247 .cfi_offset 6, -12 + 248 .cfi_offset 7, -8 + 249 .cfi_offset 14, -4 + 250 .LVL21: + ARM GAS /tmp/ccKYQ5mH.s page 28 + + + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** uint32_t pinpos = 0x00000000U; + 251 .loc 1 175 0 + 252 0002 0022 movs r2, #0 + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** uint32_t currentpin = 0x00000000U; + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Check the parameters */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* ------------------------- Configure the port pins ---------------- */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Initialize pinpos on first pin set */ + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* pinpos = 0; useless as already done in default initialization */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Configure the port pins */ + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + 253 .loc 1 189 0 + 254 0004 09E0 b .L18 + 255 .LVL22: + 256 .L20: + 257 .LBB62: + 258 .LBB63: + 259 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @file stm32l0xx_ll_gpio.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Header file of GPIO LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** ****************************************************************************** + ARM GAS /tmp/ccKYQ5mH.s page 29 + + + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #ifndef __STM32L0xx_LL_GPIO_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define __STM32L0xx_LL_GPIO_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL GPIO + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Private macros ------------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #endif /*USE_FULL_LL_DRIVER*/ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Exported types ------------------------------------------------------------*/ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief LL GPIO Init Structure definition + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** typedef struct + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be any value of @ref GPIO_LL_EC_PIN */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_MODE. + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t Speed; /*!< Specifies the speed for the selected pins. + ARM GAS /tmp/ccKYQ5mH.s page 30 + + + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_SPEED. + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_PULL. + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_AF. + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } LL_GPIO_InitTypeDef; + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #endif /* USE_FULL_LL_DRIVER */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Exported constants --------------------------------------------------------*/ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PIN PIN + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** GPIO_BSRR_BS_15) /*!< Select all pins */ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + ARM GAS /tmp/ccKYQ5mH.s page 31 + + + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_MODE Mode + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_OUTPUT Output Type + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type * + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_SPEED Output Speed + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEED0_0 /*!< Select I/O medium output sp + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEED0_1 /*!< Select I/O fast output spee + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEED0 /*!< Select I/O high output spee + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_AF Alternate Function + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_0 ((uint32_t)0x0000000U) /*!< Select alternate function 0 + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_1 ((uint32_t)0x0000001U) /*!< Select alternate function 1 + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_2 ((uint32_t)0x0000002U) /*!< Select alternate function 2 + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_3 ((uint32_t)0x0000003U) /*!< Select alternate function 3 + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_4 ((uint32_t)0x0000004U) /*!< Select alternate function 4 + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_5 ((uint32_t)0x0000005U) /*!< Select alternate function 5 + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_6 ((uint32_t)0x0000006U) /*!< Select alternate function 6 + ARM GAS /tmp/ccKYQ5mH.s page 32 + + + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_AF_7 ((uint32_t)0x0000007U) /*!< Select alternate function 7 + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Exported macro ------------------------------------------------------------*/ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Write a value in GPIO register + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param __REG__ Register to be written + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param __VALUE__ Value to be written in the register + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Read a value in GPIO register + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param __REG__ Register to be read + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Register value + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @} + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @{ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio mode for a dedicated pin on dedicated port. + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_SetPinMode + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + ARM GAS /tmp/ccKYQ5mH.s page 33 + + + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Mode This parameter can be one of the following values: + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Return gpio mode for a dedicated pin on dedicated port. + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_GetPinMode + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + ARM GAS /tmp/ccKYQ5mH.s page 34 + + + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio output type for several pins on dedicated port. + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param OutputType This parameter can be one of the following values: + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t Outpu + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Return gpio output type for several pins on dedicated port. + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + ARM GAS /tmp/ccKYQ5mH.s page 35 + + + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio speed for a dedicated pin on dedicated port. + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * supply and load conditions for each speed. + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Speed This parameter can be one of the following values: + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed)); + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Return gpio speed for a dedicated pin on dedicated port. + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + ARM GAS /tmp/ccKYQ5mH.s page 36 + + + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * supply and load conditions for each speed. + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0)) / (Pin * Pin)); + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pull This parameter can be one of the following values: + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + ARM GAS /tmp/ccKYQ5mH.s page 37 + + + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); + 260 .loc 3 496 0 + 261 0006 C668 ldr r6, [r0, #12] + 262 0008 3440 ands r4, r6 + 263 000a 0E69 ldr r6, [r1, #16] + 264 000c 6E43 muls r6, r5 + 265 000e 3443 orrs r4, r6 + 266 0010 C460 str r4, [r0, #12] + 267 .LVL23: + 268 .LBE63: + 269 .LBE62: + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Get current io position */ + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if (currentpin) + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Pin Mode configuration */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Check Speed mode parameters */ + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Speed mode configuration */ + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Pull-up Pull down resistor configuration*/ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + 270 .loc 1 211 0 + 271 0012 4C68 ldr r4, [r1, #4] + 272 0014 022C cmp r4, #2 + 273 0016 1ED0 beq .L24 + 274 .LVL24: + 275 .L19: + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Check Alternate parameter */ + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Speed mode configuration */ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if (currentpin < LL_GPIO_PIN_8) + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** else + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + ARM GAS /tmp/ccKYQ5mH.s page 38 + + + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** pinpos++; + 276 .loc 1 227 0 + 277 0018 0132 adds r2, r2, #1 + 278 .LVL25: + 279 .L18: + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 280 .loc 1 189 0 + 281 001a 0B68 ldr r3, [r1] + 282 001c 1C00 movs r4, r3 + 283 001e D440 lsrs r4, r4, r2 + 284 0020 34D0 beq .L25 + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 285 .loc 1 192 0 + 286 0022 0124 movs r4, #1 + 287 0024 9440 lsls r4, r4, r2 + 288 0026 2340 ands r3, r4 + 289 .LVL26: + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 290 .loc 1 194 0 + 291 0028 F6D0 beq .L19 + 292 .LVL27: + 293 .LBB64: + 294 .LBB65: + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 295 .loc 3 288 0 + 296 002a 0668 ldr r6, [r0] + 297 002c 1D00 movs r5, r3 + 298 002e 5D43 muls r5, r3 + 299 0030 6C00 lsls r4, r5, #1 + 300 0032 6419 adds r4, r4, r5 + 301 0034 E443 mvns r4, r4 + 302 0036 2640 ands r6, r4 + 303 0038 4F68 ldr r7, [r1, #4] + 304 003a 6F43 muls r7, r5 + 305 003c 3E43 orrs r6, r7 + 306 003e 0660 str r6, [r0] + 307 .LVL28: + 308 .LBE65: + 309 .LBE64: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 310 .loc 1 199 0 + 311 0040 4E68 ldr r6, [r1, #4] + 312 0042 013E subs r6, r6, #1 + 313 0044 012E cmp r6, #1 + 314 0046 DED8 bhi .L20 + 315 .LVL29: + 316 .LBB66: + 317 .LBB67: + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 318 .loc 3 427 0 + 319 0048 8668 ldr r6, [r0, #8] + 320 004a 2640 ands r6, r4 + 321 004c 8F68 ldr r7, [r1, #8] + 322 004e 6F43 muls r7, r5 + ARM GAS /tmp/ccKYQ5mH.s page 39 + + + 323 0050 3E43 orrs r6, r7 + 324 0052 8660 str r6, [r0, #8] + 325 .LVL30: + 326 0054 D7E7 b .L20 + 327 .LVL31: + 328 .L24: + 329 .LBE67: + 330 .LBE66: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 331 .loc 1 217 0 + 332 0056 FF2B cmp r3, #255 + 333 0058 0AD8 bhi .L21 + 334 .LVL32: + 335 .LBB68: + 336 .LBB69: + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + ARM GAS /tmp/ccKYQ5mH.s page 40 + + + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0), + 337 .loc 3 559 0 + 338 005a 046A ldr r4, [r0, #32] + 339 005c 5D43 muls r5, r3 + 340 005e 6B43 muls r3, r5 + 341 .LVL33: + 342 0060 1D01 lsls r5, r3, #4 + 343 0062 ED1A subs r5, r5, r3 + 344 0064 AC43 bics r4, r5 + 345 0066 4D69 ldr r5, [r1, #20] + 346 0068 6B43 muls r3, r5 + 347 006a 2343 orrs r3, r4 + 348 006c 0362 str r3, [r0, #32] + 349 .LVL34: + 350 006e D3E7 b .L19 + 351 .LVL35: + 352 .L21: + 353 .LBE69: + 354 .LBE68: + 355 .LBB70: + 356 .LBB71: + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * Alternate)); + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + ARM GAS /tmp/ccKYQ5mH.s page 41 + + + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->AFR[0], + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0)) / (((Pin * Pin) * Pin + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** /** + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** * @retval None + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** */ + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** { + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFR + 357 .loc 3 620 0 + 358 0070 456A ldr r5, [r0, #36] + 359 0072 1B0A lsrs r3, r3, #8 + 360 .LVL36: + 361 0074 1C00 movs r4, r3 + 362 0076 5C43 muls r4, r3 + 363 0078 5C43 muls r4, r3 + 364 007a 6343 muls r3, r4 + 365 007c 1C01 lsls r4, r3, #4 + 366 007e E41A subs r4, r4, r3 + 367 0080 A543 bics r5, r4 + 368 0082 4C69 ldr r4, [r1, #20] + ARM GAS /tmp/ccKYQ5mH.s page 42 + + + 369 0084 6343 muls r3, r4 + 370 0086 2B43 orrs r3, r5 + 371 0088 4362 str r3, [r0, #36] + 372 .LVL37: + 373 008a C5E7 b .L19 + 374 .LVL38: + 375 .L25: + 376 .LBE71: + 377 .LBE70: + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTE + 378 .loc 1 230 0 + 379 008c 4A68 ldr r2, [r1, #4] + 380 .LVL39: + 381 008e 013A subs r2, r2, #1 + 382 0090 012A cmp r2, #1 + 383 0092 01D9 bls .L26 + 384 .LVL40: + 385 .L23: + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Check Output mode parameters */ + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Output mode configuration*/ + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** return (SUCCESS); + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 386 .loc 1 240 0 + 387 0094 0120 movs r0, #1 + 388 .LVL41: + 389 @ sp needed + 390 0096 F0BD pop {r4, r5, r6, r7, pc} + 391 .LVL42: + 392 .L26: + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 393 .loc 1 236 0 + 394 0098 C968 ldr r1, [r1, #12] + 395 .LVL43: + 396 .LBB72: + 397 .LBB73: + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h **** } + 398 .loc 3 356 0 + 399 009a 4268 ldr r2, [r0, #4] + 400 009c 9A43 bics r2, r3 + 401 009e 4B43 muls r3, r1 + 402 .LVL44: + 403 00a0 1343 orrs r3, r2 + 404 00a2 4360 str r3, [r0, #4] + 405 .LVL45: + 406 00a4 F6E7 b .L23 + 407 .LBE73: + 408 .LBE72: + 409 .cfi_endproc + 410 .LFE91: + ARM GAS /tmp/ccKYQ5mH.s page 43 + + + 412 .section .text.LL_GPIO_StructInit,"ax",%progbits + 413 .align 1 + 414 .global LL_GPIO_StructInit + 415 .syntax unified + 416 .code 16 + 417 .thumb_func + 418 .fpu softvfp + 420 LL_GPIO_StructInit: + 421 .LFB92: + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * whose fields will be set to default values. + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** * @retval None + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** { + 422 .loc 1 250 0 + 423 .cfi_startproc + 424 @ args = 0, pretend = 0, frame = 0 + 425 @ frame_needed = 0, uses_anonymous_args = 0 + 426 @ link register save eliminated. + 427 .LVL46: + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** /* Reset GPIO init structure parameters values */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + 428 .loc 1 252 0 + 429 0000 044B ldr r3, .L28 + 430 0002 0360 str r3, [r0] + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + 431 .loc 1 253 0 + 432 0004 0323 movs r3, #3 + 433 0006 4360 str r3, [r0, #4] + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + 434 .loc 1 254 0 + 435 0008 0023 movs r3, #0 + 436 000a 8360 str r3, [r0, #8] + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 437 .loc 1 255 0 + 438 000c C360 str r3, [r0, #12] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + 439 .loc 1 256 0 + 440 000e 0361 str r3, [r0, #16] + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** GPIO_InitStruct->Alternate = LL_GPIO_AF_0; + 441 .loc 1 257 0 + 442 0010 4361 str r3, [r0, #20] + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c **** } + 443 .loc 1 258 0 + 444 @ sp needed + 445 0012 7047 bx lr + 446 .L29: + 447 .align 2 + 448 .L28: + 449 0014 FFFF0000 .word 65535 + 450 .cfi_endproc + 451 .LFE92: + ARM GAS /tmp/ccKYQ5mH.s page 44 + + + 453 .text + 454 .Letext0: + 455 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 456 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 457 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 458 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 459 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 460 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 461 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 462 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 463 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccKYQ5mH.s page 45 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_gpio.c + /tmp/ccKYQ5mH.s:16 .text.LL_GPIO_DeInit:0000000000000000 $t + /tmp/ccKYQ5mH.s:23 .text.LL_GPIO_DeInit:0000000000000000 LL_GPIO_DeInit + /tmp/ccKYQ5mH.s:218 .text.LL_GPIO_DeInit:00000000000000a4 $d + /tmp/ccKYQ5mH.s:228 .text.LL_GPIO_Init:0000000000000000 $t + /tmp/ccKYQ5mH.s:235 .text.LL_GPIO_Init:0000000000000000 LL_GPIO_Init + /tmp/ccKYQ5mH.s:413 .text.LL_GPIO_StructInit:0000000000000000 $t + /tmp/ccKYQ5mH.s:420 .text.LL_GPIO_StructInit:0000000000000000 LL_GPIO_StructInit + /tmp/ccKYQ5mH.s:449 .text.LL_GPIO_StructInit:0000000000000014 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_i2c.d b/build/stm32l0xx_ll_i2c.d new file mode 100644 index 0000000..d8685e3 --- /dev/null +++ b/build/stm32l0xx_ll_i2c.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_i2c.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_i2c.lst b/build/stm32l0xx_ll_i2c.lst new file mode 100644 index 0000000..74215de --- /dev/null +++ b/build/stm32l0xx_ll_i2c.lst @@ -0,0 +1,3383 @@ +ARM GAS /tmp/ccUXNvYH.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_i2c.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_I2C_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_I2C_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_I2C_DeInit: + 24 .LFB201: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @file stm32l0xx_ll_i2c.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @brief I2C LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ****************************************************************************** + ARM GAS /tmp/ccUXNvYH.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #include "stm32l0xx_ll_i2c.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #ifdef USE_FULL_ASSERT + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #include "stm32_assert.h" + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #else + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define assert_param(expr) ((void)0U) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #endif + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** @addtogroup STM32L0xx_LL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #if defined (I2C1) || defined (I2C2) || defined (I2C3) + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** @defgroup I2C_LL I2C + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Private types -------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Private constants ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Private macros ------------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** @addtogroup I2C_LL_Private_Macros + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_NACK)) + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @} + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** @addtogroup I2C_LL_Exported_Functions + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @{ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + ARM GAS /tmp/ccUXNvYH.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** @addtogroup I2C_LL_EF_Init + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @{ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @brief De-initialize the I2C registers to their default reset values. + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @param I2Cx I2C Instance. + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @retval An ErrorStatus enumeration value: + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - SUCCESS: I2C registers are de-initialized + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - ERROR: I2C registers are not de-initialized + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 26 .loc 1 104 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** ErrorStatus status = SUCCESS; + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Check the I2C Instance I2Cx */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** if (I2Cx == I2C1) + 32 .loc 1 110 0 + 33 0000 174B ldr r3, .L9 + 34 0002 9842 cmp r0, r3 + 35 0004 07D0 beq .L6 + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Force reset of I2C clock */ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Release reset of I2C clock */ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #if defined(I2C2) + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** else if (I2Cx == I2C2) + 36 .loc 1 119 0 + 37 0006 174B ldr r3, .L9+4 + 38 0008 9842 cmp r0, r3 + 39 000a 10D0 beq .L7 + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Force reset of I2C clock */ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Release reset of I2C clock */ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #endif + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #if defined(I2C3) + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** else if (I2Cx == I2C3) + 40 .loc 1 130 0 + 41 000c 164B ldr r3, .L9+8 + 42 000e 9842 cmp r0, r3 + ARM GAS /tmp/ccUXNvYH.s page 4 + + + 43 0010 19D0 beq .L8 + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Force reset of I2C clock */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3); + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Release reset of I2C clock */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** #endif + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** else + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** status = ERROR; + 44 .loc 1 141 0 + 45 0012 0020 movs r0, #0 + 46 .LVL1: + 47 .L3: + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** return status; + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 48 .loc 1 145 0 + 49 @ sp needed + 50 0014 7047 bx lr + 51 .LVL2: + 52 .L6: + 53 .LBB32: + 54 .LBB33: + 55 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + ARM GAS /tmp/ccUXNvYH.s page 5 + + + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/ccUXNvYH.s page 6 + + + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + ARM GAS /tmp/ccUXNvYH.s page 7 + + + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + ARM GAS /tmp/ccUXNvYH.s page 8 + + + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccUXNvYH.s page 9 + + + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/ccUXNvYH.s page 10 + + + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + ARM GAS /tmp/ccUXNvYH.s page 11 + + + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/ccUXNvYH.s page 12 + + + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + ARM GAS /tmp/ccUXNvYH.s page 13 + + + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + ARM GAS /tmp/ccUXNvYH.s page 14 + + + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + ARM GAS /tmp/ccUXNvYH.s page 15 + + + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 56 .loc 2 613 0 + 57 0016 154B ldr r3, .L9+12 + 58 0018 996A ldr r1, [r3, #40] + 59 001a 8022 movs r2, #128 + 60 001c 9203 lsls r2, r2, #14 + 61 001e 0A43 orrs r2, r1 + 62 0020 9A62 str r2, [r3, #40] + 63 .LVL3: + 64 .LBE33: + 65 .LBE32: + 66 .LBB34: + 67 .LBB35: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + ARM GAS /tmp/ccUXNvYH.s page 16 + + + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 68 .loc 2 664 0 + 69 0022 9A6A ldr r2, [r3, #40] + 70 0024 1249 ldr r1, .L9+16 + 71 0026 0A40 ands r2, r1 + 72 0028 9A62 str r2, [r3, #40] + 73 .LBE35: + 74 .LBE34: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 75 .loc 1 105 0 + 76 002a 0120 movs r0, #1 + 77 .LVL4: + 78 002c F2E7 b .L3 + 79 .LVL5: + 80 .L7: + 81 .LBB36: + 82 .LBB37: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 83 .loc 2 613 0 + 84 002e 0F4B ldr r3, .L9+12 + 85 0030 996A ldr r1, [r3, #40] + 86 0032 8022 movs r2, #128 + 87 0034 D203 lsls r2, r2, #15 + 88 0036 0A43 orrs r2, r1 + 89 0038 9A62 str r2, [r3, #40] + 90 .LVL6: + 91 .LBE37: + 92 .LBE36: + 93 .LBB38: + 94 .LBB39: + 95 .loc 2 664 0 + 96 003a 9A6A ldr r2, [r3, #40] + 97 003c 0D49 ldr r1, .L9+20 + 98 003e 0A40 ands r2, r1 + 99 0040 9A62 str r2, [r3, #40] + 100 .LBE39: + 101 .LBE38: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + ARM GAS /tmp/ccUXNvYH.s page 17 + + + 102 .loc 1 105 0 + 103 0042 0120 movs r0, #1 + 104 .LVL7: + 105 0044 E6E7 b .L3 + 106 .LVL8: + 107 .L8: + 108 .LBB40: + 109 .LBB41: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 110 .loc 2 613 0 + 111 0046 094B ldr r3, .L9+12 + 112 0048 996A ldr r1, [r3, #40] + 113 004a 8022 movs r2, #128 + 114 004c D205 lsls r2, r2, #23 + 115 004e 0A43 orrs r2, r1 + 116 0050 9A62 str r2, [r3, #40] + 117 .LVL9: + 118 .LBE41: + 119 .LBE40: + 120 .LBB42: + 121 .LBB43: + 122 .loc 2 664 0 + 123 0052 9A6A ldr r2, [r3, #40] + 124 0054 0849 ldr r1, .L9+24 + 125 0056 0A40 ands r2, r1 + 126 0058 9A62 str r2, [r3, #40] + 127 .LBE43: + 128 .LBE42: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 129 .loc 1 105 0 + 130 005a 0120 movs r0, #1 + 131 .LVL10: + 132 005c DAE7 b .L3 + 133 .L10: + 134 005e C046 .align 2 + 135 .L9: + 136 0060 00540040 .word 1073763328 + 137 0064 00580040 .word 1073764352 + 138 0068 00780040 .word 1073772544 + 139 006c 00100240 .word 1073876992 + 140 0070 FFFFDFFF .word -2097153 + 141 0074 FFFFBFFF .word -4194305 + 142 0078 FFFFFFBF .word -1073741825 + 143 .cfi_endproc + 144 .LFE201: + 146 .section .text.LL_I2C_Init,"ax",%progbits + 147 .align 1 + 148 .global LL_I2C_Init + 149 .syntax unified + 150 .code 16 + 151 .thumb_func + 152 .fpu softvfp + 154 LL_I2C_Init: + 155 .LFB202: + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + ARM GAS /tmp/ccUXNvYH.s page 18 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @param I2Cx I2C Instance. + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @retval An ErrorStatus enumeration value: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - SUCCESS: I2C registers are initialized + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - ERROR: Not applicable + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 156 .loc 1 156 0 + 157 .cfi_startproc + 158 @ args = 0, pretend = 0, frame = 0 + 159 @ frame_needed = 0, uses_anonymous_args = 0 + 160 .LVL11: + 161 0000 30B5 push {r4, r5, lr} + 162 .LCFI0: + 163 .cfi_def_cfa_offset 12 + 164 .cfi_offset 4, -12 + 165 .cfi_offset 5, -8 + 166 .cfi_offset 14, -4 + 167 .LVL12: + 168 .LBB44: + 169 .LBB45: + 170 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @file stm32l0xx_ll_i2c.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Header file of I2C LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + ARM GAS /tmp/ccUXNvYH.s page 19 + + + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #ifndef __STM32L0xx_LL_I2C_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define __STM32L0xx_LL_I2C_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #if defined (I2C1) || defined (I2C2) || defined (I2C3) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL I2C + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Private constants ---------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_Private_Constants I2C Private Constants + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Private macros ------------------------------------------------------------*/ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #if defined(USE_FULL_LL_DRIVER) + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_Private_Macros I2C Private Macros + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #endif /*USE_FULL_LL_DRIVER*/ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Exported types ------------------------------------------------------------*/ + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #if defined(USE_FULL_LL_DRIVER) + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** typedef struct + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MOD + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low perio + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter must be set by referring to the STM32CubeMX Too + ARM GAS /tmp/ccUXNvYH.s page 20 + + + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_S + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t DigitalFilter; /*!< Configures the digital noise filter. + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter can be a number between Min_Data = 0x00 and Max + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t OwnAddress1; /*!< Specifies the device own address 1. + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter must be a value between Min_Data = 0x00 and Max + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after t + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDG + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** This feature can be modified afterwards using unitary function + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } LL_I2C_InitTypeDef; + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #endif /*USE_FULL_LL_DRIVER*/ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Exported constants --------------------------------------------------------*/ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Flags defines which can be used with LL_I2C_WriteReg function + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + ARM GAS /tmp/ccUXNvYH.s page 21 + + + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Flags defines which can be used with LL_I2C_ReadReg function + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register emp + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mod + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received f + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mo + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SM + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SM + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_IT IT Defines + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt en + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received I + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt e + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrup + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowl + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default addre + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + ARM GAS /tmp/ccUXNvYH.s page 22 + + + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit a + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] ar + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] ar + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] ar + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] ar + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] ar + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after curren + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. * + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.* + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write tr + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read tra + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + ARM GAS /tmp/ccUXNvYH.s page 23 + + + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_MODE Transfer End Mode + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*! + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*! + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SOFTEND 0x00000000U /*! + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*! + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*! + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*! + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*! + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*! + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detec + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detec + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + ARM GAS /tmp/ccUXNvYH.s page 24 + + + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Exported macro ------------------------------------------------------------*/ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Write a value in I2C register + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __INSTANCE__ I2C Instance + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __REG__ Register to be written + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __VALUE__ Value to be written in the register + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Read a value in I2C register + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __INSTANCE__ I2C Instance + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __REG__ Register to be read + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Register value + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the SDA setup, hold time and the SCL high, low period. + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0x + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0x + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + ARM GAS /tmp/ccUXNvYH.s page 25 + + + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HI + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* Exported functions --------------------------------------------------------*/ + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EF_Configuration Configuration + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable I2C peripheral (PE = 1). + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PE LL_I2C_Enable + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_PE); + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable I2C peripheral (PE = 0). + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note When PE = 0, the I2C SCL and SDA lines are released. + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Internal state machines and status bits are put back to their reset value. + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * When cleared, PE must be kept low for at least 3 APB clock cycles. + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PE LL_I2C_Disable + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); + 171 .loc 3 423 0 + 172 0002 0268 ldr r2, [r0] + 173 0004 0124 movs r4, #1 + 174 0006 A243 bics r2, r4 + 175 0008 0260 str r2, [r0] + 176 .LVL13: + 177 .LBE45: + 178 .LBE44: + 179 .LBB46: + 180 .LBB47: + ARM GAS /tmp/ccUXNvYH.s page 26 + + + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if the I2C peripheral is enabled or disabled. + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PE LL_I2C_IsEnabled + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure Noise Filters (Analog and Digital). + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note If the analog filter is also enabled, the digital filter is added to analog filter. + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * The filters can only be programmed when the I2C is disabled (PE = 0). + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * CR1 DNF LL_I2C_ConfigFilters + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param AnalogFilter This parameter can be one of the following values: + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disa + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * This parameter is used to configure the digital noise filter on SDA and SCL input. + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t Digita + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_ + 181 .loc 3 454 0 + 182 000a 0368 ldr r3, [r0] + 183 000c 174A ldr r2, .L13 + 184 000e 1340 ands r3, r2 + 185 0010 CA68 ldr r2, [r1, #12] + 186 0012 1202 lsls r2, r2, #8 + 187 0014 8D68 ldr r5, [r1, #8] + 188 0016 2A43 orrs r2, r5 + 189 0018 1343 orrs r3, r2 + 190 001a 0360 str r3, [r0] + 191 .LVL14: + 192 .LBE47: + 193 .LBE46: + 194 .LBB48: + 195 .LBB49: + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure Digital Noise Filter. + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note If the analog filter is also enabled, the digital filter is added to analog filter. + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * This filter can only be programmed when the I2C is disabled (PE = 0). + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disa + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * This parameter is used to configure the digital noise filter on SDA and SCL input. + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + ARM GAS /tmp/ccUXNvYH.s page 27 + + + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the current Digital Noise Filter configuration. + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x0 and Max_Data=0xF + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Analog Noise Filter. + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This filter can only be programmed when the I2C is disabled (PE = 0). + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Analog Noise Filter. + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This filter can only be programmed when the I2C is disabled (PE = 0). + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Analog Noise Filter is enabled or disabled. + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)); + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable DMA transmission requests. + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + ARM GAS /tmp/ccUXNvYH.s page 28 + + + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable DMA transmission requests. + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if DMA transmission requests are enabled or disabled. + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)); + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable DMA reception requests. + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable DMA reception requests. + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if DMA reception requests are enabled or disabled. + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + ARM GAS /tmp/ccUXNvYH.s page 29 + + + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)); + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the data register address used for DMA transfer + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * RXDR RXDATA LL_I2C_DMA_GetRegAddr + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param Direction This parameter can be one of the following values: + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Address of data register + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** register uint32_t data_reg_addr = 0U; + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* return address of TXDR register */ + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** data_reg_addr = (uint32_t) & (I2Cx->TXDR); + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** else + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /* return address of RXDR register */ + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** data_reg_addr = (uint32_t) & (I2Cx->RXDR); + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return data_reg_addr; + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Clock stretching. + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can only be programmed when the I2C is disabled (PE = 0). + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Clock stretching. + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can only be programmed when the I2C is disabled (PE = 0). + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + ARM GAS /tmp/ccUXNvYH.s page 30 + + + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Clock stretching is enabled or disabled. + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable hardware byte control in slave mode. + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_SBC); + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable hardware byte control in slave mode. + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if hardware byte control in slave mode is enabled or disabled. + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)); + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Wakeup from STOP. + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * WakeUpFromStop feature is supported by the I2Cx Instance. + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can only be programmed when Digital Filter is disabled. + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + ARM GAS /tmp/ccUXNvYH.s page 31 + + + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Wakeup from STOP. + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * WakeUpFromStop feature is supported by the I2Cx Instance. + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Wakeup from STOP is enabled or disabled. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * WakeUpFromStop feature is supported by the I2Cx Instance. + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)); + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable General Call. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note When enabled the Address 0x00 is ACKed. + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable General Call. + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note When disabled the Address 0x00 is NACKed. + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if General Call is enabled or disabled. + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + ARM GAS /tmp/ccUXNvYH.s page 32 + + + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)); + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Changing this bit is not allowed, when the START bit is set. + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param AddressingMode This parameter can be one of the following values: + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the Master addressing mode. + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Returned value can be one of the following values: + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Set the Own Address1. + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param OwnAddrSize This parameter can be one of the following values: + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS1_7BIT + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS1_10BIT + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAdd + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable acknowledge on Own Address1 match address. + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + ARM GAS /tmp/ccUXNvYH.s page 33 + + + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable acknowledge on Own Address1 match address. + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Own Address1 acknowledge is enabled or disabled. + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)); + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Set the 7bits Own Address2. + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This action has no effect if own address2 is enabled. + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param OwnAddrMask This parameter can be one of the following values: + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAdd + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable acknowledge on Own Address2 match address. + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); + ARM GAS /tmp/ccUXNvYH.s page 34 + + + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable acknowledge on Own Address2 match address. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Own Address1 acknowledge is enabled or disabled. + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)); + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the SDA setup, hold time and the SCL high, low period. + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can only be programmed when the I2C is disabled (PE = 0). + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This parameter is computed with the STM32CubeMX Tool. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** WRITE_REG(I2Cx->TIMINGR, Timing); + 196 .loc 3 900 0 + 197 001c 4B68 ldr r3, [r1, #4] + 198 001e 0361 str r3, [r0, #16] + 199 .LVL15: + 200 .LBE49: + 201 .LBE48: + 202 .LBB50: + 203 .LBB51: + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 204 .loc 3 409 0 + 205 0020 0368 ldr r3, [r0] + 206 0022 2343 orrs r3, r4 + 207 0024 0360 str r3, [r0] + 208 .LVL16: + 209 .LBE51: + 210 .LBE50: + 211 .LBB52: + 212 .LBB53: + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 213 .loc 3 819 0 + 214 0026 8368 ldr r3, [r0, #8] + ARM GAS /tmp/ccUXNvYH.s page 35 + + + 215 0028 114A ldr r2, .L13+4 + 216 002a 1340 ands r3, r2 + 217 002c 8360 str r3, [r0, #8] + 218 .LVL17: + 219 .LBE53: + 220 .LBE52: + 221 .LBB54: + 222 .LBB55: + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 223 .loc 3 797 0 + 224 002e 8368 ldr r3, [r0, #8] + 225 0030 DB0A lsrs r3, r3, #11 + 226 0032 DB02 lsls r3, r3, #11 + 227 0034 0A69 ldr r2, [r1, #16] + 228 0036 8C69 ldr r4, [r1, #24] + 229 0038 2243 orrs r2, r4 + 230 003a 1343 orrs r3, r2 + 231 003c 8360 str r3, [r0, #8] + 232 .LVL18: + 233 .LBE55: + 234 .LBE54: + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Check the I2C Instance I2Cx */ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Check the I2C parameters from I2C_InitStruct */ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Disable the selected I2Cx Peripheral */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_Disable(I2Cx); + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ------------------------ + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Configure the analog and digital noise filters with parameters : + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - AnalogFilter: I2C_CR1_ANFOFF bit + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - DigitalFilter: I2C_CR1_DNF[3:0] bits + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration -------------------- + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Configure the SDA setup, hold time and the SCL high, low period with parameter : + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Enable the selected I2Cx Peripheral */ + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_Enable(I2Cx); + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ----------------------- + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Disable, Configure and Enable I2Cx device own address 1 with parameters : + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - OwnAddrSize: I2C_OAR1_OA1MODE bit + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + ARM GAS /tmp/ccUXNvYH.s page 36 + + + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_DisableOwnAddress1(I2Cx); + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* OwnAdress1 == 0 is reserved for General Call address */ + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** if (I2C_InitStruct->OwnAddress1 != 0U) + 235 .loc 1 197 0 + 236 003e 0B69 ldr r3, [r1, #16] + 237 0040 002B cmp r3, #0 + 238 0042 04D0 beq .L12 + 239 .LVL19: + 240 .LBB56: + 241 .LBB57: + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 242 .loc 3 808 0 + 243 0044 8268 ldr r2, [r0, #8] + 244 0046 8023 movs r3, #128 + 245 0048 1B02 lsls r3, r3, #8 + 246 004a 1343 orrs r3, r2 + 247 004c 8360 str r3, [r0, #8] + 248 .LVL20: + 249 .L12: + 250 .LBE57: + 251 .LBE56: + 252 .LBB58: + 253 .LBB59: + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the Timing Prescaler setting. + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x0 and Max_Data=0xF + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SCL low period setting. + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SCL high period setting. + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + ARM GAS /tmp/ccUXNvYH.s page 37 + + + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SDA hold time. + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x0 and Max_Data=0xF + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SDA setup time. + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x0 and Max_Data=0xF + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure peripheral mode. + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * CR1 SMBDEN LL_I2C_SetMode + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param PeripheralMode This parameter can be one of the following values: + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_I2C + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_HOST + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); + 254 .loc 3 974 0 + 255 004e 0368 ldr r3, [r0] + 256 0050 084A ldr r2, .L13+8 + 257 0052 1340 ands r3, r2 + 258 0054 0A68 ldr r2, [r1] + 259 0056 1343 orrs r3, r2 + 260 0058 0360 str r3, [r0] + 261 .LVL21: + 262 .LBE59: + 263 .LBE58: + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_EnableOwnAddress1(I2Cx); + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /*---------------------------- I2Cx MODE Configuration ----------------------- + ARM GAS /tmp/ccUXNvYH.s page 38 + + + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Configure I2Cx peripheral mode with parameter : + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ------------------------ + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * Configure the ACKnowledge or Non ACKnowledge condition + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * after the address receive match code or next received byte with parameter : + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * - TypeAcknowledge: I2C_CR2_NACK bit + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + 264 .loc 1 213 0 + 265 005a 4B69 ldr r3, [r1, #20] + 266 .LVL22: + 267 .LBB60: + 268 .LBB61: + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get peripheral mode. + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * CR1 SMBDEN LL_I2C_GetMode + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Returned value can be one of the following values: + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_I2C + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_HOST + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable SMBus alert (Host or Device mode) + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note SMBus Device mode: +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * - SMBus Alert pin is drived low and +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Alert Response Address Header acknowledge is enabled. +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Host mode: +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * - SMBus Alert pin management is supported. +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable SMBus alert (Host or Device mode) +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + ARM GAS /tmp/ccUXNvYH.s page 39 + + +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note SMBus Device mode: +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * - SMBus Alert pin is not drived (can be used as a standard GPIO) and +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Alert Response Address Header acknowledge is disabled. +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Host mode: +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * - SMBus Alert pin management is not supported. +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)); +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable SMBus Packet Error Calculation (PEC). +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable SMBus Packet Error Calculation (PEC). +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + ARM GAS /tmp/ccUXNvYH.s page 40 + + +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)); +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the SMBus Clock Timeout. +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutAMode This parameter can be one of the following values: +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutB +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t Timeo +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** uint32_t TimeoutB) +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note These bits can only be programmed when TimeoutA is disabled. +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SMBus Clock TimeoutA setting. +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0 and Max_Data=0xFFF +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) + ARM GAS /tmp/ccUXNvYH.s page 41 + + +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Set the SMBus Clock TimeoutA mode. +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can only be programmed when TimeoutA is disabled. +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutAMode This parameter can be one of the following values: +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SMBus Clock TimeoutA mode. +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Returned value can be one of the following values: +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note These bits can only be programmed when TimeoutB is disabled. +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. + ARM GAS /tmp/ccUXNvYH.s page 42 + + +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0 and Max_Data=0xFFF +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable the SMBus Clock Timeout. +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param ClockTimeout This parameter can be one of the following values: +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTB +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable the SMBus Clock Timeout. +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param ClockTimeout This parameter can be one of the following values: +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTB +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if the SMBus Clock Timeout is enabled or disabled. +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param ClockTimeout This parameter can be one of the following values: +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTA +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_TIMEOUTB +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) + ARM GAS /tmp/ccUXNvYH.s page 43 + + +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout) +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EF_IT_Management IT_Management +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable TXIS interrupt. +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable TXIS interrupt. +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if the TXIS Interrupt is enabled or disabled. +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)); +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable RXNE interrupt. +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** + ARM GAS /tmp/ccUXNvYH.s page 44 + + +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable RXNE interrupt. +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if the RXNE Interrupt is enabled or disabled. +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)); +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Address match interrupt (slave mode only). +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Address match interrupt (slave mode only). +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Address match interrupt is enabled or disabled. +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)); +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Not acknowledge received interrupt. +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + ARM GAS /tmp/ccUXNvYH.s page 45 + + +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Not acknowledge received interrupt. +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Not acknowledge received interrupt is enabled or disabled. +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)); +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable STOP detection interrupt. +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable STOP detection interrupt. +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if STOP detection interrupt is enabled or disabled. +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccUXNvYH.s page 46 + + +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)); +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Transfer Complete interrupt. +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Any of these events will generate interrupt : +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Transfer Complete (TC) +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Transfer Complete Reload (TCR) +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Transfer Complete interrupt. +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Any of these events will generate interrupt : +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Transfer Complete (TC) +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Transfer Complete Reload (TCR) +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Transfer Complete interrupt is enabled or disabled. +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)); +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable Error interrupts. +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Any of these errors will generate interrupt : +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Arbitration Loss (ARLO) +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Bus Error detection (BERR) +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Overrun/Underrun (OVR) +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Timeout detection (TIMEOUT) +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus PEC error detection (PECERR) +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Alert pin event detection (ALERT) +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + ARM GAS /tmp/ccUXNvYH.s page 47 + + +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable Error interrupts. +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Any of these errors will generate interrupt : +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Arbitration Loss (ARLO) +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Bus Error detection (BERR) +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * Overrun/Underrun (OVR) +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Timeout detection (TIMEOUT) +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus PEC error detection (PECERR) +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus Alert pin event detection (ALERT) +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if Error interrupts are enabled or disabled. +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)); +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EF_FLAG_management FLAG_management +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Transmit data register empty flag. +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: When next data is written in Transmit data register. +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When Transmit data register is empty. +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { + ARM GAS /tmp/ccUXNvYH.s page 48 + + +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)); +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Transmit interrupt flag. +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: When next data is written in Transmit data register. +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When Transmit data register is empty. +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)); +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Receive data register not empty flag. +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: When Receive data register is read. +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When the received data is copied in Receive data register. +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)); +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Address matched flag (slave mode). +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When the received slave address matched with one of the enabled slave address. +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)); +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Not Acknowledge received flag. +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When a NACK is received after a byte transmission. +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)); +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Stop detection flag. + ARM GAS /tmp/ccUXNvYH.s page 49 + + +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When a Stop condition is detected. +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)); +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Transfer complete flag (master mode). +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)); +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Transfer complete flag (master mode). +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When RELOAD=1 and NBYTES date have been transferred. +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)); +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Bus error flag. +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When a misplaced Start or Stop condition is detected. +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)); +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Arbitration lost flag. +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When arbitration lost. +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccUXNvYH.s page 50 + + +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)); +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Overrun/Underrun flag (slave mode). +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)); +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of SMBus PEC error flag in reception. +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When the received PEC does not match with the PEC register content. +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)); +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of SMBus Timeout detection flag. +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When a timeout or extended clock timeout occurs. +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)); +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of SMBus alert flag. +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When SMBus host configuration, SMBus alert enabled and +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * a falling edge event occurs on SMBA pin. +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + ARM GAS /tmp/ccUXNvYH.s page 51 + + +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)); +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Indicate the status of Bus Busy flag. +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note RESET: Clear default value. +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SET: When a Start condition is detected. +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)); +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Address Matched flag. +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Not Acknowledge flag. +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Stop detection flag. +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Transmit data register empty flag (TXE). +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + ARM GAS /tmp/ccUXNvYH.s page 52 + + +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Bus error flag. +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Arbitration lost flag. +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear Overrun/Underrun flag. +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear SMBus PEC error flag. +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear SMBus Timeout detection flag. + ARM GAS /tmp/ccUXNvYH.s page 53 + + +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Clear SMBus Alert flag. +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * SMBus feature is supported by the I2Cx Instance. +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @} +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** @defgroup I2C_LL_EF_Data_Management Data_Management +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @{ +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable automatic STOP condition generation (master mode). +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transf +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * This bit has no effect in slave mode or when RELOAD bit is set. +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable automatic STOP condition generation (master mode). +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +1867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +1869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** + ARM GAS /tmp/ccUXNvYH.s page 54 + + +1871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if automatic STOP condition is enabled or disabled. +1873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode +1874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)); +1880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Enable reload mode (master mode). +1884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded w +1885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode +1886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +1890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +1892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Disable reload mode (master mode). +1896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode +1898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +1902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +1904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Check if reload mode is enabled or disabled. +1908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode +1909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval State of bit (1 or 0). +1911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +1913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)); +1915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Configure the number of bytes for transfer. +1919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Changing these bits when START bit is set is not allowed. +1920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize +1921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. +1923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +1926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); + ARM GAS /tmp/ccUXNvYH.s page 55 + + +1928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Get the number of bytes configured for transfer. +1932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize +1933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval Value between Min_Data=0x0 and Max_Data=0xFF +1935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +1937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +1939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** } +1940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** +1941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** /** +1942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address +1943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @note Usage in Slave mode only. +1944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData +1945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param I2Cx I2C Instance. +1946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @param TypeAcknowledge This parameter can be one of the following values: +1947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_ACK +1948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @arg @ref LL_I2C_NACK +1949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** * @retval None +1950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** */ +1951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +1952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** { +1953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h **** MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); + 269 .loc 3 1953 0 + 270 005c 4268 ldr r2, [r0, #4] + 271 005e 0449 ldr r1, .L13+4 + 272 .LVL23: + 273 0060 0A40 ands r2, r1 + 274 0062 1343 orrs r3, r2 + 275 .LVL24: + 276 0064 4360 str r3, [r0, #4] + 277 .LVL25: + 278 .LBE61: + 279 .LBE60: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** return SUCCESS; + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 280 .loc 1 216 0 + 281 0066 0120 movs r0, #1 + 282 .LVL26: + 283 @ sp needed + 284 0068 30BD pop {r4, r5, pc} + 285 .L14: + 286 006a C046 .align 2 + 287 .L13: + 288 006c FFE0FFFF .word -7937 + 289 0070 FF7FFFFF .word -32769 + 290 0074 FFFFCFFF .word -3145729 + 291 .cfi_endproc + 292 .LFE202: + 294 .section .text.LL_I2C_StructInit,"ax",%progbits + 295 .align 1 + 296 .global LL_I2C_StructInit + 297 .syntax unified + ARM GAS /tmp/ccUXNvYH.s page 56 + + + 298 .code 16 + 299 .thumb_func + 300 .fpu softvfp + 302 LL_I2C_StructInit: + 303 .LFB203: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** * @retval None + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** */ + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** { + 304 .loc 1 224 0 + 305 .cfi_startproc + 306 @ args = 0, pretend = 0, frame = 0 + 307 @ frame_needed = 0, uses_anonymous_args = 0 + 308 @ link register save eliminated. + 309 .LVL27: + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** /* Set I2C_InitStruct fields to default values */ + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + 310 .loc 1 226 0 + 311 0000 0023 movs r3, #0 + 312 0002 0360 str r3, [r0] + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->Timing = 0U; + 313 .loc 1 227 0 + 314 0004 4360 str r3, [r0, #4] + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + 315 .loc 1 228 0 + 316 0006 8360 str r3, [r0, #8] + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->DigitalFilter = 0U; + 317 .loc 1 229 0 + 318 0008 C360 str r3, [r0, #12] + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->OwnAddress1 = 0U; + 319 .loc 1 230 0 + 320 000a 0361 str r3, [r0, #16] + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + 321 .loc 1 231 0 + 322 000c 8022 movs r2, #128 + 323 000e 1202 lsls r2, r2, #8 + 324 0010 4261 str r2, [r0, #20] + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; + 325 .loc 1 232 0 + 326 0012 8361 str r3, [r0, #24] + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c **** } + 327 .loc 1 233 0 + 328 @ sp needed + 329 0014 7047 bx lr + 330 .cfi_endproc + 331 .LFE203: + 333 .text + 334 .Letext0: + 335 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 336 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 337 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 338 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 339 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + ARM GAS /tmp/ccUXNvYH.s page 57 + + + 340 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 341 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 342 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 343 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccUXNvYH.s page 58 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_i2c.c + /tmp/ccUXNvYH.s:16 .text.LL_I2C_DeInit:0000000000000000 $t + /tmp/ccUXNvYH.s:23 .text.LL_I2C_DeInit:0000000000000000 LL_I2C_DeInit + /tmp/ccUXNvYH.s:136 .text.LL_I2C_DeInit:0000000000000060 $d + /tmp/ccUXNvYH.s:147 .text.LL_I2C_Init:0000000000000000 $t + /tmp/ccUXNvYH.s:154 .text.LL_I2C_Init:0000000000000000 LL_I2C_Init + /tmp/ccUXNvYH.s:288 .text.LL_I2C_Init:000000000000006c $d + /tmp/ccUXNvYH.s:295 .text.LL_I2C_StructInit:0000000000000000 $t + /tmp/ccUXNvYH.s:302 .text.LL_I2C_StructInit:0000000000000000 LL_I2C_StructInit + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_lptim.d b/build/stm32l0xx_ll_lptim.d new file mode 100644 index 0000000..8a48a98 --- /dev/null +++ b/build/stm32l0xx_ll_lptim.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_lptim.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_lptim.lst b/build/stm32l0xx_ll_lptim.lst new file mode 100644 index 0000000..330db56 --- /dev/null +++ b/build/stm32l0xx_ll_lptim.lst @@ -0,0 +1,1486 @@ +ARM GAS /tmp/cc2Dksgr.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_lptim.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_LPTIM_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_LPTIM_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_LPTIM_DeInit: + 24 .LFB140: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @file stm32l0xx_ll_lptim.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @brief LPTIM LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ****************************************************************************** + ARM GAS /tmp/cc2Dksgr.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #include "stm32l0xx_ll_lptim.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #if defined (LPTIM1) || defined (LPTIM2) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** @addtogroup LPTIM_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Private macros ------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** @addtogroup LPTIM_LL_Private_Macros + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @{ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @} + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Private function prototypes -----------------------------------------------*/ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Exported functions --------------------------------------------------------*/ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** @addtogroup LPTIM_LL_Exported_Functions + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @{ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + ARM GAS /tmp/cc2Dksgr.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** @addtogroup LPTIM_LL_EF_Init + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @{ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @brief Set LPTIMx registers to their reset values. + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @param LPTIMx LP Timer instance + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @retval An ErrorStatus enumeration value: + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * - SUCCESS: LPTIMx registers are de-initialized + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * - ERROR: invalid LPTIMx instance + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 26 .loc 1 104 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ErrorStatus result = SUCCESS; + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Check the parameters */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** if (LPTIMx == LPTIM1) + 32 .loc 1 110 0 + 33 0000 084B ldr r3, .L5 + 34 0002 9842 cmp r0, r3 + 35 0004 01D0 beq .L4 + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #if defined(LPTIM2) + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** else if (LPTIMx == LPTIM2) + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** #endif + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** else + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** result = ERROR; + 36 .loc 1 124 0 + 37 0006 0020 movs r0, #0 + 38 .LVL1: + 39 .L2: + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** return result; + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 40 .loc 1 128 0 + 41 @ sp needed + 42 0008 7047 bx lr + 43 .LVL2: + 44 .L4: + ARM GAS /tmp/cc2Dksgr.s page 4 + + + 45 .LBB8: + 46 .LBB9: + 47 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + ARM GAS /tmp/cc2Dksgr.s page 5 + + + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + ARM GAS /tmp/cc2Dksgr.s page 6 + + + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + ARM GAS /tmp/cc2Dksgr.s page 7 + + + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/cc2Dksgr.s page 8 + + + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + ARM GAS /tmp/cc2Dksgr.s page 9 + + + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/cc2Dksgr.s page 10 + + + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + ARM GAS /tmp/cc2Dksgr.s page 11 + + + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/cc2Dksgr.s page 12 + + + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + ARM GAS /tmp/cc2Dksgr.s page 13 + + + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/cc2Dksgr.s page 14 + + + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 48 .loc 2 613 0 + 49 000a 074A ldr r2, .L5+4 + 50 000c 916A ldr r1, [r2, #40] + 51 000e 8023 movs r3, #128 + 52 0010 1B06 lsls r3, r3, #24 + 53 0012 0B43 orrs r3, r1 + 54 0014 9362 str r3, [r2, #40] + 55 .LVL3: + 56 .LBE9: + 57 .LBE8: + 58 .LBB10: + ARM GAS /tmp/cc2Dksgr.s page 15 + + + 59 .LBB11: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 60 .loc 2 664 0 + 61 0016 936A ldr r3, [r2, #40] + 62 0018 5B00 lsls r3, r3, #1 + 63 001a 5B08 lsrs r3, r3, #1 + 64 001c 9362 str r3, [r2, #40] + ARM GAS /tmp/cc2Dksgr.s page 16 + + + 65 .LBE11: + 66 .LBE10: + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 67 .loc 1 105 0 + 68 001e 0120 movs r0, #1 + 69 .LVL4: + 70 0020 F2E7 b .L2 + 71 .L6: + 72 0022 C046 .align 2 + 73 .L5: + 74 0024 007C0040 .word 1073773568 + 75 0028 00100240 .word 1073876992 + 76 .cfi_endproc + 77 .LFE140: + 79 .section .text.LL_LPTIM_StructInit,"ax",%progbits + 80 .align 1 + 81 .global LL_LPTIM_StructInit + 82 .syntax unified + 83 .code 16 + 84 .thumb_func + 85 .fpu softvfp + 87 LL_LPTIM_StructInit: + 88 .LFB141: + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @brief Set each fields of the LPTIM_InitStruct structure to its default + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * value. + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @retval None + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 89 .loc 1 137 0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 0 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 93 @ link register save eliminated. + 94 .LVL5: + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Set the default configuration */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; + 95 .loc 1 139 0 + 96 0000 0023 movs r3, #0 + 97 0002 0360 str r3, [r0] + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1; + 98 .loc 1 140 0 + 99 0004 4360 str r3, [r0, #4] + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM; + 100 .loc 1 141 0 + 101 0006 8360 str r3, [r0, #8] + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Polarity = LL_LPTIM_OUTPUT_POLARITY_REGULAR; + 102 .loc 1 142 0 + 103 0008 C360 str r3, [r0, #12] + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 104 .loc 1 143 0 + 105 @ sp needed + 106 000a 7047 bx lr + 107 .cfi_endproc + ARM GAS /tmp/cc2Dksgr.s page 17 + + + 108 .LFE141: + 110 .section .text.LL_LPTIM_Init,"ax",%progbits + 111 .align 1 + 112 .global LL_LPTIM_Init + 113 .syntax unified + 114 .code 16 + 115 .thumb_func + 116 .fpu softvfp + 118 LL_LPTIM_Init: + 119 .LFB142: + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @brief Configure the LPTIMx peripheral according to the specified parameters. + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled. + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable(). + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @param LPTIMx LP Timer Instance + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * @retval An ErrorStatus enumeration value: + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * - SUCCESS: LPTIMx instance has been initialized + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** * - ERROR: LPTIMx instance hasn't been initialized + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct) + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 120 .loc 1 156 0 + 121 .cfi_startproc + 122 @ args = 0, pretend = 0, frame = 0 + 123 @ frame_needed = 0, uses_anonymous_args = 0 + 124 .LVL6: + 125 0000 10B5 push {r4, lr} + 126 .LCFI0: + 127 .cfi_def_cfa_offset 8 + 128 .cfi_offset 4, -8 + 129 .cfi_offset 14, -4 + 130 .LVL7: + 131 .LBB12: + 132 .LBB13: + 133 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @file stm32l0xx_ll_lptim.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Header file of LPTIM LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * without specific prior written permission. + ARM GAS /tmp/cc2Dksgr.s page 18 + + + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #ifndef __STM32L0xx_LL_LPTIM_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define __STM32L0xx_LL_LPTIM_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #if defined (LPTIM1) + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL LPTIM + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Private macros ------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Private macros ------------------------------------------------------------*/ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #if defined(USE_FULL_LL_DRIVER) + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #endif /*USE_FULL_LL_DRIVER*/ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Exported types ------------------------------------------------------------*/ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #if defined(USE_FULL_LL_DRIVER) + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + ARM GAS /tmp/cc2Dksgr.s page 19 + + + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief LPTIM Init structure definition + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** typedef struct + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** { + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This feature can be modified afterwards using unitary function @ref + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This feature can be modified afterwards using using unitary functio + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** uint32_t Waveform; /*!< Specifies the waveform shape. + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This feature can be modified afterwards using unitary function @ref + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** uint32_t Polarity; /*!< Specifies waveform polarity. + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** This feature can be modified afterwards using unitary function @ref + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** } LL_LPTIM_InitTypeDef; + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #endif /* USE_FULL_LL_DRIVER */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Exported constants --------------------------------------------------------*/ + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Flags defines which can be used with LL_LPTIM_ReadReg function + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event * + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up t + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_EC_IT IT Defines + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt E + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrup + ARM GAS /tmp/cc2Dksgr.s page 20 + + + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid ed + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update O + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register updat + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP In + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VAL + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Read a value in LPTIM register + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @param __INSTANCE__ LPTIM Instance + ARM GAS /tmp/cc2Dksgr.s page 23 + + + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @param __REG__ Register to be read + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @retval Register value + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @} + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /* Exported functions --------------------------------------------------------*/ + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @{ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Enable the LPTIM instance + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @note After setting the ENABLE bit, a delay of two counter clock is needed + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * before the LPTIM instance is actually enabled. + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @rmtoll CR ENABLE LL_LPTIM_Enable + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @param LPTIMx Low-Power Timer instance + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @retval None + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** { + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** } + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Disable the LPTIM instance + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @rmtoll CR ENABLE LL_LPTIM_Disable + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @param LPTIMx Low-Power Timer instance + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @retval None + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** { + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** } + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** /** + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @brief Indicates whether the LPTIM instance is enabled. + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @rmtoll CR ENABLE LL_LPTIM_IsEnabled + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @param LPTIMx Low-Power Timer instance + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** * @retval State of bit (1 or 0). + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** */ + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** { + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h **** return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE)); + 134 .loc 3 360 0 + 135 0002 0369 ldr r3, [r0, #16] + ARM GAS /tmp/cc2Dksgr.s page 24 + + + 136 .LVL8: + 137 .LBE13: + 138 .LBE12: + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ErrorStatus result = SUCCESS; + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** (ENABLE bit is reset to 0). + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** if (LL_LPTIM_IsEnabled(LPTIMx)) + 139 .loc 1 162 0 + 140 0004 DB07 lsls r3, r3, #31 + 141 0006 0DD4 bmi .L10 + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** result = ERROR; + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** else + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** { + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Check the parameters */ + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Set CKSEL bitfield according to ClockSource value */ + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Set PRESC bitfield according to Prescaler value */ + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Set WAVE bitfield according to Waveform value */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** /* Set WAVEPOL bitfield according to Polarity value */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** MODIFY_REG(LPTIMx->CFGR, + 142 .loc 1 179 0 + 143 0008 C368 ldr r3, [r0, #12] + 144 000a 074A ldr r2, .L11 + 145 000c 1A40 ands r2, r3 + 146 000e 0B68 ldr r3, [r1] + 147 0010 4C68 ldr r4, [r1, #4] + 148 0012 2343 orrs r3, r4 + 149 0014 8C68 ldr r4, [r1, #8] + 150 0016 2343 orrs r3, r4 + 151 0018 C968 ldr r1, [r1, #12] + 152 .LVL9: + 153 001a 0B43 orrs r3, r1 + 154 001c 1343 orrs r3, r2 + 155 001e C360 str r3, [r0, #12] + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** ErrorStatus result = SUCCESS; + 156 .loc 1 157 0 + 157 0020 0120 movs r0, #1 + 158 .LVL10: + 159 .L9: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->ClockSource | \ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Prescaler | \ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Waveform | \ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** LPTIM_InitStruct->Polarity); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** return result; + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + ARM GAS /tmp/cc2Dksgr.s page 25 + + + 160 .loc 1 188 0 + 161 @ sp needed + 162 0022 10BD pop {r4, pc} + 163 .LVL11: + 164 .L10: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c **** } + 165 .loc 1 164 0 + 166 0024 0020 movs r0, #0 + 167 .LVL12: + 168 0026 FCE7 b .L9 + 169 .L12: + 170 .align 2 + 171 .L11: + 172 0028 FEF1CFFF .word -3149314 + 173 .cfi_endproc + 174 .LFE142: + 176 .text + 177 .Letext0: + 178 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 179 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 180 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 181 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 182 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 183 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 184 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 185 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 186 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc2Dksgr.s page 26 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_lptim.c + /tmp/cc2Dksgr.s:16 .text.LL_LPTIM_DeInit:0000000000000000 $t + /tmp/cc2Dksgr.s:23 .text.LL_LPTIM_DeInit:0000000000000000 LL_LPTIM_DeInit + /tmp/cc2Dksgr.s:74 .text.LL_LPTIM_DeInit:0000000000000024 $d + /tmp/cc2Dksgr.s:80 .text.LL_LPTIM_StructInit:0000000000000000 $t + /tmp/cc2Dksgr.s:87 .text.LL_LPTIM_StructInit:0000000000000000 LL_LPTIM_StructInit + /tmp/cc2Dksgr.s:111 .text.LL_LPTIM_Init:0000000000000000 $t + /tmp/cc2Dksgr.s:118 .text.LL_LPTIM_Init:0000000000000000 LL_LPTIM_Init + /tmp/cc2Dksgr.s:172 .text.LL_LPTIM_Init:0000000000000028 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_lpuart.d b/build/stm32l0xx_ll_lpuart.d new file mode 100644 index 0000000..bbac7e3 --- /dev/null +++ b/build/stm32l0xx_ll_lpuart.d @@ -0,0 +1,112 @@ +build/stm32l0xx_ll_lpuart.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_lpuart.lst b/build/stm32l0xx_ll_lpuart.lst new file mode 100644 index 0000000..958b958 --- /dev/null +++ b/build/stm32l0xx_ll_lpuart.lst @@ -0,0 +1,2394 @@ +ARM GAS /tmp/ccHfYm8W.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_lpuart.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_LPUART_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_LPUART_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_LPUART_DeInit: + 24 .LFB336: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @file stm32l0xx_ll_lpuart.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @brief LPUART LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ****************************************************************************** + ARM GAS /tmp/ccHfYm8W.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #include "stm32l0xx_ll_lpuart.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #include "stm32l0xx_ll_rcc.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #include "stm32l0xx_ll_bus.h" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #if defined (LPUART1) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup LPUART_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup LPUART_LL_Private_Constants + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @} + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Private macros ------------------------------------------------------------*/ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup LPUART_LL_Private_Macros + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Check of parameters for configuration of LPUART registers */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* value : */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* - LPUART_BRR register value should be >= 0x300 */ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Baudrate specified by the user should belong to [8, 10600000].*/ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 10600000U) && ((__BAUDRATE__) >= 8U + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + ARM GAS /tmp/ccHfYm8W.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @} + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Private function prototypes -----------------------------------------------*/ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Exported functions --------------------------------------------------------*/ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup LPUART_LL_Exported_Functions + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** @addtogroup LPUART_LL_EF_Init + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @{ + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @brief De-initialize LPUART registers (Registers restored to their default values). + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @param LPUARTx LPUART Instance + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @retval An ErrorStatus enumeration value: + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - SUCCESS: LPUART registers are de-initialized + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - ERROR: not applicable + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 26 .loc 1 128 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB14: + 33 .LBB15: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + ARM GAS /tmp/ccHfYm8W.s page 4 + + + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/ccHfYm8W.s page 5 + + + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + ARM GAS /tmp/ccHfYm8W.s page 6 + + + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + ARM GAS /tmp/ccHfYm8W.s page 7 + + + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + ARM GAS /tmp/ccHfYm8W.s page 8 + + + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + ARM GAS /tmp/ccHfYm8W.s page 9 + + + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/ccHfYm8W.s page 10 + + + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + ARM GAS /tmp/ccHfYm8W.s page 11 + + + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + ARM GAS /tmp/ccHfYm8W.s page 12 + + + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/ccHfYm8W.s page 13 + + + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccHfYm8W.s page 14 + + + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 35 .loc 2 613 0 + 36 0000 054B ldr r3, .L2 + 37 0002 996A ldr r1, [r3, #40] + 38 0004 8022 movs r2, #128 + 39 0006 D202 lsls r2, r2, #11 + 40 0008 0A43 orrs r2, r1 + 41 000a 9A62 str r2, [r3, #40] + 42 .LVL1: + 43 .LBE15: + 44 .LBE14: + 45 .LBB16: + 46 .LBB17: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccHfYm8W.s page 15 + + + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 47 .loc 2 664 0 + 48 000c 9A6A ldr r2, [r3, #40] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 9A62 str r2, [r3, #40] + 52 .LVL2: + 53 .LBE17: + 54 .LBE16: + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ErrorStatus status = SUCCESS; + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Check the parameters */ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LPUART_INSTANCE(LPUARTx)); + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Force reset of LPUART peripheral */ + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1); + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Release reset of LPUART peripheral */ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1); + ARM GAS /tmp/ccHfYm8W.s page 16 + + + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** return (status); + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** } + 55 .loc 1 141 0 + 56 0014 0120 movs r0, #1 + 57 .LVL3: + 58 @ sp needed + 59 0016 7047 bx lr + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0018 00100240 .word 1073876992 + 64 001c FFFFFBFF .word -262145 + 65 .cfi_endproc + 66 .LFE336: + 68 .global __aeabi_uldivmod + 69 .section .text.LL_LPUART_Init,"ax",%progbits + 70 .align 1 + 71 .global LL_LPUART_Init + 72 .syntax unified + 73 .code 16 + 74 .thumb_func + 75 .fpu softvfp + 77 LL_LPUART_Init: + 78 .LFB337: + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @brief Initialize LPUART registers according to the specified + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * parameters in LPUART_InitStruct. + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @note As some bits in LPUART configuration registers can only be written when the LPUART is d + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR res + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @param LPUARTx LPUART Instance + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * that contains the configuration information for the specified LPUART peripheral. + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @retval An ErrorStatus enumeration value: + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - ERROR: Problem occurred during LPUART Registers initialization + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 79 .loc 1 157 0 + 80 .cfi_startproc + 81 @ args = 0, pretend = 0, frame = 0 + 82 @ frame_needed = 0, uses_anonymous_args = 0 + 83 .LVL4: + 84 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 85 .LCFI0: + 86 .cfi_def_cfa_offset 24 + 87 .cfi_offset 3, -24 + 88 .cfi_offset 4, -20 + 89 .cfi_offset 5, -16 + 90 .cfi_offset 6, -12 + 91 .cfi_offset 7, -8 + 92 .cfi_offset 14, -4 + 93 0002 0400 movs r4, r0 + 94 0004 0D00 movs r5, r1 + ARM GAS /tmp/ccHfYm8W.s page 17 + + + 95 .LVL5: + 96 .LBB18: + 97 .LBB19: + 98 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @file stm32l0xx_ll_lpuart.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Header file of LPUART LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #ifndef __STM32L0xx_LL_LPUART_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define __STM32L0xx_LL_LPUART_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #if defined (LPUART1) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL LPUART + ARM GAS /tmp/ccHfYm8W.s page 18 + + + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Private constants ---------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Defines used for the bit position in the register and perform offsets*/ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_POSITION_CR1_DEDT (uint32_t)16U + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_POSITION_CR1_DEAT (uint32_t)21U + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_POSITION_CR2_ADD (uint32_t)24U + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Defines used in Baud Rate related macros and corresponding register setting computation */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U) + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_BRR_MASK (uint32_t)(0x000FFFFFU) + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U) + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #if defined(USE_FULL_LL_DRIVER) + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Exported types ------------------------------------------------------------*/ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #if defined(USE_FULL_LL_DRIVER) + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief LL LPUART Init Structure definition + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** typedef struct + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t BaudRate; /*!< This field defines expected LPUART communication baud ra + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This parameter can be a value of @ref LPUART_LL_EC_DATAW + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This parameter can be a value of @ref LPUART_LL_EC_STOPB + ARM GAS /tmp/ccHfYm8W.s page 19 + + + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t Parity; /*!< Specifies the parity mode. + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This parameter can be a value of @ref LPUART_LL_EC_PARIT + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This parameter can be a value of @ref LPUART_LL_EC_DIREC + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This parameter can be a value of @ref LPUART_LL_EC_HWCON + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** This feature can be modified afterwards using unitary fu + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } LL_LPUART_InitTypeDef; + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #endif /* USE_FULL_LL_DRIVER */ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Exported constants --------------------------------------------------------*/ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Flags defines which can be used with LL_LPUART_WriteReg function + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag * + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected fl + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Flags defines which can be used with LL_LPUART_ReadReg function + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag * + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected fl + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register no + ARM GAS /tmp/ccHfYm8W.s page 20 + + + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data registe + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable ackno + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknow + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_IT IT Defines + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register no + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data registe + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match inter + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enabl + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_DIRECTION Direction + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter and + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is d + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is e + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_PARITY Parity Control + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity control d + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control e + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control e + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_WAKEUP Wakeup + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< LPUART wake up + ARM GAS /tmp/ccHfYm8W.s page 21 + + + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word leng + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word leng + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word leng + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 stop bit */ + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are u + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins f + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal wo + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal va + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal wo + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal va + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data fro + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data fro + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + ARM GAS /tmp/ccHfYm8W.s page 22 + + + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_BITORDER Bit Order + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmit + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmit + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address de + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address de + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and RTS hard + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabl + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hard + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake up act + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up act + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up act + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is act + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is act + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of d + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of d + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + ARM GAS /tmp/ccHfYm8W.s page 23 + + + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Exported macro ------------------------------------------------------------*/ + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Write a value in LPUART register + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __INSTANCE__ LPUART Instance + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __REG__ Register to be written + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __VALUE__ Value to be written in the register + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VA + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Read a value in LPUART register + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __INSTANCE__ LPUART Instance + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __REG__ Register to be read + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Register value + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Compute LPUARTDIV value according to Peripheral Clock and + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * expected Baud Rate (20-bit value of LPUARTDIV is returned) + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param __BAUDRATE__ Baud Rate value to achieve + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval LPUARTDIV value to be used for BRR register filling + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @} + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + ARM GAS /tmp/ccHfYm8W.s page 24 + + + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /* Exported functions --------------------------------------------------------*/ + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** @defgroup LPUART_LL_EF_Configuration Configuration functions + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @{ + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief LPUART Enable + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UE LL_LPUART_Enable + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR1, USART_CR1_UE); + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief LPUART Disable + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * and current operations are discarded. The configuration of the LPUART is kept, but all + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * flags, in the LPUARTx_ISR are set to their default values. + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note In order to go into low-power mode without generating errors on the line, + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * the TE bit must be reset before and the software must wait + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * The DMA requests are also reset when UE = 0 so the DMA channel must + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * be disabled before resetting the UE bit. + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UE LL_LPUART_Disable + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Indicate if LPUART is enabled + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UE LL_LPUART_IsEnabled + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval State of bit (1 or 0). + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); + 99 .loc 3 443 0 + 100 0006 0368 ldr r3, [r0] + 101 .LVL6: + 102 .LBE19: + 103 .LBE18: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ErrorStatus status = ERROR; + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Check the parameters */ + ARM GAS /tmp/ccHfYm8W.s page 25 + + + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LPUART_INSTANCE(LPUARTx)); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* LPUART needs to be in disabled state, in order to be able to configure some bits in + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + 104 .loc 1 172 0 + 105 0008 DB07 lsls r3, r3, #31 + 106 000a 01D5 bpl .L9 + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** ErrorStatus status = ERROR; + 107 .loc 1 158 0 + 108 000c 0020 movs r0, #0 + 109 .LVL7: + 110 .L5: + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /*---------------------------- LPUART CR1 Configuration ----------------------- + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with paramete + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parit + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->Transf + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** MODIFY_REG(LPUARTx->CR1, + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->Trans + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /*---------------------------- LPUART CR2 Configuration ----------------------- + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * Configure LPUARTx CR2 (Stop bits) with parameters: + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /*---------------------------- LPUART CR3 Configuration ----------------------- + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->H + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /*---------------------------- LPUART BRR Configuration ----------------------- + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * Retrieve Clock frequency used for LPUART Peripheral + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Configure the LPUART Baud Rate : + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** - valid baud rate value (different from 0) is required + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** - Peripheral clock as returned by RCC service, should be valid (different from 0). + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** && (LPUART_InitStruct->BaudRate != 0U)) + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** status = SUCCESS; + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_LPUART_SetBaudRate(LPUARTx, + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** periphclk, + ARM GAS /tmp/ccHfYm8W.s page 26 + + + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->BaudRate); + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** } + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** } + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** return (status); + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** } + 111 .loc 1 216 0 + 112 @ sp needed + 113 .LVL8: + 114 .LVL9: + 115 000e F8BD pop {r3, r4, r5, r6, r7, pc} + 116 .LVL10: + 117 .L9: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + 118 .loc 1 180 0 + 119 0010 0368 ldr r3, [r0] + 120 0012 184A ldr r2, .L10 + 121 0014 1340 ands r3, r2 + 122 0016 4A68 ldr r2, [r1, #4] + 123 0018 C968 ldr r1, [r1, #12] + 124 .LVL11: + 125 001a 0A43 orrs r2, r1 + 126 001c 2969 ldr r1, [r5, #16] + 127 001e 0A43 orrs r2, r1 + 128 0020 1343 orrs r3, r2 + 129 0022 0360 str r3, [r0] + 130 .LVL12: + 131 .LBB20: + 132 .LBB21: + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief LPUART enabled in STOP Mode + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provid + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * LPUART clock selection is HSI or LSE in RCC. + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR1, USART_CR1_UESM); + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief LPUART disabled in STOP Mode + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + ARM GAS /tmp/ccHfYm8W.s page 27 + + + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Indicate if LPUART is enabled in STOP Mode + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * (able to wake up MCU from Stop mode or not) + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval State of bit (1 or 0). + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR1, USART_CR1_RE); + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Receiver Disable + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Transmitter Enable + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR1, USART_CR1_TE); + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Transmitter Disable + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure simultaneously enabled/disabled states + ARM GAS /tmp/ccHfYm8W.s page 28 + + + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * of Transmitter and Receiver + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 TE LL_LPUART_SetTransferDirection + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param TransferDirection This parameter can be one of the following values: + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_NONE + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_RX + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_TX + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_TX_RX + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirect + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 TE LL_LPUART_GetTransferDirection + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_NONE + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_RX + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_TX + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DIRECTION_TX_RX + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled) + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * (depending on data width) and parity is checked on the received data. + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 PS LL_LPUART_SetParity\n + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 PCE LL_LPUART_SetParity + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param Parity This parameter can be one of the following values: + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_NONE + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_EVEN + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_ODD + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 PS LL_LPUART_GetParity\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 PCE LL_LPUART_GetParity + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccHfYm8W.s page 29 + + + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_NONE + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_EVEN + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_ODD + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Set Receiver Wake Up method from Mute mode. + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param Method This parameter can be one of the following values: + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_IDLELINE + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return Receiver Wake Up method from Mute mode + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_IDLELINE + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Set Word length (nb of data bits, excluding start and stop bits) + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 M LL_LPUART_SetDataWidth + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param DataWidth This parameter can be one of the following values: + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_7B + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_8B + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_9B + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 M LL_LPUART_GetDataWidth + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_7B + ARM GAS /tmp/ccHfYm8W.s page 30 + + + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_8B + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_9B + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Allow switch between Mute Mode and Active mode + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR1, USART_CR1_MME); + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval State of bit (1 or 0). + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Set the length of the stop bits + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param StopBits This parameter can be one of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_1 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_2 + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); + 133 .loc 3 695 0 + 134 0024 4368 ldr r3, [r0, #4] + 135 0026 144A ldr r2, .L10+4 + 136 0028 1340 ands r3, r2 + ARM GAS /tmp/ccHfYm8W.s page 31 + + + 137 002a AA68 ldr r2, [r5, #8] + 138 002c 1343 orrs r3, r2 + 139 002e 4360 str r3, [r0, #4] + 140 .LVL13: + 141 .LBE21: + 142 .LBE20: + 143 .LBB22: + 144 .LBB23: + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Retrieve the length of the stop bits + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_1 + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_2 + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note Call of this function is equivalent to following function call sequence : + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 PCE LL_LPUART_ConfigCharacter\n + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR1 M LL_LPUART_ConfigCharacter\n + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR2 STOP LL_LPUART_ConfigCharacter + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param DataWidth This parameter can be one of the following values: + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_7B + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_8B + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_DATAWIDTH_9B + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param Parity This parameter can be one of the following values: + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_NONE + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_EVEN + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_PARITY_ODD + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param StopBits This parameter can be one of the following values: + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_1 + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_STOPBITS_2 + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** uint32_t StopBits) + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure TX/RX pins swapping setting. + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + ARM GAS /tmp/ccHfYm8W.s page 32 + + + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param SwapConfig This parameter can be one of the following values: + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXRX_STANDARD + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXRX_SWAPPED + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Retrieve TX/RX pins swapping configuration. + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXRX_STANDARD + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXRX_SWAPPED + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure RX pin active level logic + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param PinInvMethod This parameter can be one of the following values: + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Retrieve RX pin active level logic configuration + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure TX pin active level logic + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param PinInvMethod This parameter can be one of the following values: + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + ARM GAS /tmp/ccHfYm8W.s page 33 + + + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Retrieve TX pin active level logic configuration + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure Binary data logic. + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note Allow to define how Logical data from the data register are send/received : + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param DataLogic This parameter can be one of the following values: + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Retrieve Binary data configuration + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + ARM GAS /tmp/ccHfYm8W.s page 34 + + + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param BitOrder This parameter can be one of the following values: + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BITORDER_LSBFIRST + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BITORDER_MSBFIRST + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BITORDER_LSBFIRST + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_BITORDER_MSBFIRST + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Set Address of the LPUART node. + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * for wake up with address mark detection. + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * (b7-b4 should be set to 0) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * for wake up with 7-bit address mark detection. + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * The MSB of the character sent by the transmitter should be equal to 1. + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * It may also be used for character detection during normal reception, + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * value and CMF flag is set on match) + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param AddressLen This parameter can be one of the following values: + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param NodeAddress 4 or 7 bit Address of the LPUART node. + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint3 + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** (uint32_t)(AddressLen | (NodeAddress << LPUART_POSITION_CR2_ADD))); + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note If 4-bit Address Detection is selected in ADDM7, + ARM GAS /tmp/ccHfYm8W.s page 35 + + + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * If 7-bit Address Detection is selected in ADDM7, + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD); + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Enable RTS HW Flow Control + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Disable RTS HW Flow Control + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Enable CTS HW Flow Control + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + ARM GAS /tmp/ccHfYm8W.s page 36 + + + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Disable CTS HW Flow Control + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR3 CTSE LL_LPUART_SetHWFlowCtrl + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param HardwareFlowControl This parameter can be one of the following values: + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_NONE + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_RTS + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_CTS + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); + 145 .loc 3 999 0 + 146 0030 8368 ldr r3, [r0, #8] + 147 0032 124A ldr r2, .L10+8 + 148 0034 1340 ands r3, r2 + 149 0036 6A69 ldr r2, [r5, #20] + 150 0038 1343 orrs r3, r2 + 151 003a 8360 str r3, [r0, #8] + 152 .LVL14: + 153 .LBE23: + 154 .LBE22: + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 155 .loc 1 199 0 + 156 003c C020 movs r0, #192 + 157 .LVL15: + 158 003e 0001 lsls r0, r0, #4 + 159 0040 FFF7FEFF bl LL_RCC_GetLPUARTClockFreq + 160 .LVL16: + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** && (LPUART_InitStruct->BaudRate != 0U)) + 161 .loc 1 205 0 + 162 0044 0028 cmp r0, #0 + 163 0046 10D0 beq .L7 + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 164 .loc 1 206 0 + 165 0048 2A68 ldr r2, [r5] + 166 004a 002A cmp r2, #0 + 167 004c 0FD0 beq .L8 + 168 .LVL17: + 169 .LBB24: + 170 .LBB25: +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } + ARM GAS /tmp/ccHfYm8W.s page 37 + + +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * CR3 CTSE LL_LPUART_GetHWFlowCtrl +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_NONE +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_RTS +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_CTS +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Enable Overrun detection +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Disable Overrun detection +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Indicate if Overrun detection is enabled +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval State of bit (1 or 0). +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 WUS LL_LPUART_SetWKUPType +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param Type This parameter can be one of the following values: +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + ARM GAS /tmp/ccHfYm8W.s page 38 + + +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_RXNE +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll CR3 WUS LL_LPUART_GetWKUPType +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval Returned value can be one of the following values: +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @arg @ref LL_LPUART_WAKEUP_ON_RXNE +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** } +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** /** +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @brief Configure LPUART BRR register for achieving expected Baud Rate value. +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * according to used Peripheral Clock and expected Baud Rate values +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note Peripheral clock and Baud Rate values provided as function parameters should be valid +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * (Baud rate value != 0). +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * a care should be taken when generating high baud rates using high PeriphClk +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @rmtoll BRR BRR LL_LPUART_SetBaudRate +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param LPUARTx LPUART Instance +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param PeriphClk Peripheral Clock +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @param BaudRate Baud Rate +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** * @retval None +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** */ +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t Bau +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** { +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h **** LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); + 171 .loc 3 1098 0 + 172 004e 070E lsrs r7, r0, #24 + 173 0050 0602 lsls r6, r0, #8 + 174 0052 5008 lsrs r0, r2, #1 + 175 .LVL18: + 176 0054 0021 movs r1, #0 + 177 0056 8019 adds r0, r0, r6 + 178 0058 7941 adcs r1, r1, r7 + 179 005a 0023 movs r3, #0 + 180 005c FFF7FEFF bl __aeabi_uldivmod + 181 .LVL19: + 182 0060 0003 lsls r0, r0, #12 + 183 0062 000B lsrs r0, r0, #12 + 184 0064 E060 str r0, [r4, #12] + 185 .LBE25: + 186 .LBE24: + ARM GAS /tmp/ccHfYm8W.s page 39 + + + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LL_LPUART_SetBaudRate(LPUARTx, + 187 .loc 1 208 0 + 188 0066 0120 movs r0, #1 + 189 0068 D1E7 b .L5 + 190 .LVL20: + 191 .L7: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 192 .loc 1 158 0 + 193 006a 0020 movs r0, #0 + 194 .LVL21: + 195 006c CFE7 b .L5 + 196 .LVL22: + 197 .L8: + 198 006e 0020 movs r0, #0 + 199 .LVL23: + 200 0070 CDE7 b .L5 + 201 .L11: + 202 0072 C046 .align 2 + 203 .L10: + 204 0074 F3E9FFEF .word -268441101 + 205 0078 FFCFFFFF .word -12289 + 206 007c FFFCFFFF .word -769 + 207 .cfi_endproc + 208 .LFE337: + 210 .section .text.LL_LPUART_StructInit,"ax",%progbits + 211 .align 1 + 212 .global LL_LPUART_StructInit + 213 .syntax unified + 214 .code 16 + 215 .thumb_func + 216 .fpu softvfp + 218 LL_LPUART_StructInit: + 219 .LFB338: + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @brief Set each @ref LL_LPUART_InitTypeDef field to default value. + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * whose fields will be set to default values. + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** * @retval None + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** { + 220 .loc 1 226 0 + 221 .cfi_startproc + 222 @ args = 0, pretend = 0, frame = 0 + 223 @ frame_needed = 0, uses_anonymous_args = 0 + 224 @ link register save eliminated. + 225 .LVL24: + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** /* Set LPUART_InitStruct fields to default values */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->BaudRate = 9600U; + 226 .loc 1 228 0 + 227 0000 9623 movs r3, #150 + 228 0002 9B01 lsls r3, r3, #6 + 229 0004 0360 str r3, [r0] + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; + 230 .loc 1 229 0 + ARM GAS /tmp/ccHfYm8W.s page 40 + + + 231 0006 0023 movs r3, #0 + 232 0008 4360 str r3, [r0, #4] + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; + 233 .loc 1 230 0 + 234 000a 8360 str r3, [r0, #8] + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; + 235 .loc 1 231 0 + 236 000c C360 str r3, [r0, #12] + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX; + 237 .loc 1 232 0 + 238 000e 0C22 movs r2, #12 + 239 0010 0261 str r2, [r0, #16] + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; + 240 .loc 1 233 0 + 241 0012 4361 str r3, [r0, #20] + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c **** } + 242 .loc 1 234 0 + 243 @ sp needed + 244 0014 7047 bx lr + 245 .cfi_endproc + 246 .LFE338: + 248 .text + 249 .Letext0: + 250 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 251 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 252 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 253 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 254 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 255 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 256 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 257 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 258 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + 259 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h" + ARM GAS /tmp/ccHfYm8W.s page 41 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_lpuart.c + /tmp/ccHfYm8W.s:16 .text.LL_LPUART_DeInit:0000000000000000 $t + /tmp/ccHfYm8W.s:23 .text.LL_LPUART_DeInit:0000000000000000 LL_LPUART_DeInit + /tmp/ccHfYm8W.s:63 .text.LL_LPUART_DeInit:0000000000000018 $d + /tmp/ccHfYm8W.s:70 .text.LL_LPUART_Init:0000000000000000 $t + /tmp/ccHfYm8W.s:77 .text.LL_LPUART_Init:0000000000000000 LL_LPUART_Init + /tmp/ccHfYm8W.s:204 .text.LL_LPUART_Init:0000000000000074 $d + /tmp/ccHfYm8W.s:211 .text.LL_LPUART_StructInit:0000000000000000 $t + /tmp/ccHfYm8W.s:218 .text.LL_LPUART_StructInit:0000000000000000 LL_LPUART_StructInit + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uldivmod +LL_RCC_GetLPUARTClockFreq diff --git a/build/stm32l0xx_ll_pwr.d b/build/stm32l0xx_ll_pwr.d new file mode 100644 index 0000000..6f48df0 --- /dev/null +++ b/build/stm32l0xx_ll_pwr.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_pwr.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_pwr.lst b/build/stm32l0xx_ll_pwr.lst new file mode 100644 index 0000000..fbb2373 --- /dev/null +++ b/build/stm32l0xx_ll_pwr.lst @@ -0,0 +1,876 @@ +ARM GAS /tmp/cc6mZCRa.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_pwr.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_PWR_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_PWR_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_PWR_DeInit: + 24 .LFB106: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @file stm32l0xx_ll_pwr.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @brief PWR LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** ****************************************************************************** + ARM GAS /tmp/cc6mZCRa.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** #include "stm32l0xx_ll_pwr.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** @addtogroup STM32L0xx_LL_Driver + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @{ + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** #if defined(PWR) + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** @defgroup PWR_LL PWR + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Private types -------------------------------------------------------------*/ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Private constants ---------------------------------------------------------*/ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Private macros ------------------------------------------------------------*/ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Exported functions --------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** @addtogroup PWR_LL_Exported_Functions + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @{ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** @addtogroup PWR_LL_EF_Init + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @{ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /** + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @brief De-initialize the PWR registers to their default reset values. + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * @retval An ErrorStatus enumeration value: + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * - SUCCESS: PWR registers are de-initialized + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** * - ERROR: not applicable + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** ErrorStatus LL_PWR_DeInit(void) + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** { + 26 .loc 1 73 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB6: + 33 .LBB7: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + ARM GAS /tmp/cc6mZCRa.s page 3 + + + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + ARM GAS /tmp/cc6mZCRa.s page 4 + + + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + ARM GAS /tmp/cc6mZCRa.s page 5 + + + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cc6mZCRa.s page 6 + + + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + ARM GAS /tmp/cc6mZCRa.s page 7 + + + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/cc6mZCRa.s page 8 + + + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/cc6mZCRa.s page 9 + + + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + ARM GAS /tmp/cc6mZCRa.s page 10 + + + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cc6mZCRa.s page 11 + + + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/cc6mZCRa.s page 12 + + + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/cc6mZCRa.s page 13 + + + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 35 .loc 2 613 0 + 36 0000 054B ldr r3, .L2 + 37 0002 996A ldr r1, [r3, #40] + 38 0004 8022 movs r2, #128 + 39 0006 5205 lsls r2, r2, #21 + 40 0008 0A43 orrs r2, r1 + 41 000a 9A62 str r2, [r3, #40] + 42 .LVL1: + 43 .LBE7: + 44 .LBE6: + 45 .LBB8: + 46 .LBB9: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/cc6mZCRa.s page 14 + + + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 47 .loc 2 664 0 + 48 000c 9A6A ldr r2, [r3, #40] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 9A62 str r2, [r3, #40] + 52 .LVL2: + 53 .LBE9: + 54 .LBE8: + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Force reset of PWR clock */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** /* Release reset of PWR clock */ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** return SUCCESS; + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c **** } + ARM GAS /tmp/cc6mZCRa.s page 15 + + + 55 .loc 1 81 0 + 56 0014 0120 movs r0, #1 + 57 @ sp needed + 58 0016 7047 bx lr + 59 .L3: + 60 .align 2 + 61 .L2: + 62 0018 00100240 .word 1073876992 + 63 001c FFFFFFEF .word -268435457 + 64 .cfi_endproc + 65 .LFE106: + 67 .text + 68 .Letext0: + 69 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 70 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 71 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 72 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 73 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 74 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 75 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 76 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 77 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc6mZCRa.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_pwr.c + /tmp/cc6mZCRa.s:16 .text.LL_PWR_DeInit:0000000000000000 $t + /tmp/cc6mZCRa.s:23 .text.LL_PWR_DeInit:0000000000000000 LL_PWR_DeInit + /tmp/cc6mZCRa.s:62 .text.LL_PWR_DeInit:0000000000000018 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_rcc.d b/build/stm32l0xx_ll_rcc.d new file mode 100644 index 0000000..811d69e --- /dev/null +++ b/build/stm32l0xx_ll_rcc.d @@ -0,0 +1,106 @@ +build/stm32l0xx_ll_rcc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/stm32l0xx_ll_rcc.lst b/build/stm32l0xx_ll_rcc.lst new file mode 100644 index 0000000..314e6b9 --- /dev/null +++ b/build/stm32l0xx_ll_rcc.lst @@ -0,0 +1,4950 @@ +ARM GAS /tmp/cc0YOhsX.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_rcc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_RCC_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_RCC_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_RCC_DeInit: + 24 .LFB176: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @file stm32l0xx_ll_rcc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief RCC LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** ****************************************************************************** + ARM GAS /tmp/cc0YOhsX.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #include "stm32l0xx_ll_rcc.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #ifdef USE_FULL_ASSERT + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #include "stm32_assert.h" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #else + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define assert_param(expr) ((void)0U) + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* USE_FULL_ASSERT */ + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup STM32L0xx_LL_Driver + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC) + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @defgroup RCC_LL RCC + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Private types -------------------------------------------------------------*/ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Private constants ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Private macros ------------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Macros + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL) + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL) + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #else + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CCIPR_I2C3SEL) + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #else + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* RCC_CCIPR_I2C3SEL */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(USB) + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* USB */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @} + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + ARM GAS /tmp/cc0YOhsX.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @defgroup RCC_LL_Private_Functions RCC Private functions + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void); + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void); + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @} + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Exported functions --------------------------------------------------------*/ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Exported_Functions + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Init + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Reset the RCC clock configuration to the default reset state. + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note The default reset state of the clock configuration is given below: + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - MSI ON and used as system clock source + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - HSE, HSI and PLL OFF + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - CSS, MCO OFF + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - All interrupts disabled + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note This function doesn't modify the configuration of the + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - Peripheral clocks + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - LSI, LSE and RTC clocks + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval An ErrorStatus enumeration value: + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - SUCCESS: RCC registers are de-initialized + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * - ERROR: not applicable + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** ErrorStatus LL_RCC_DeInit(void) + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 26 .loc 1 129 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB154: + 33 .LBB155: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @file stm32l0xx_ll_rcc.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ ARM GAS /tmp/cc0YOhsX.s page 4 + + + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #ifndef __STM32L0xx_LL_RCC_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __STM32L0xx_LL_RCC_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/cc0YOhsX.s page 5 + + + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Constants RCC Private Constants + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Defines used for the bit position in the register and perform offsets*/ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PPRE2 (uint32_t)11U /*!< field position in register RCC_CFGR */ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PLLDIV (uint32_t)22U /*!< field position in register RCC_CFGR */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSICAL (uint32_t)0U /*!< field position in register RCC_ICSCR */ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSITRIM (uint32_t)8U /*!< field position in register RCC_ICSCR */ + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSIRANGE (uint32_t)13U /*!< field position in register RCC_ICSCR */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSICAL (uint32_t)16U /*!< field position in register RCC_ICSCR */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSITRIM (uint32_t)24U /*!< field position in register RCC_ICSCR */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSI48CAL (uint32_t)8U /*!< field position in register RCC_CRRCR */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** typedef struct + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/cc0YOhsX.s page 6 + + + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * HW set-up. + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LSI_VALUE ((uint32_t)37000U) /*!< Value of the LSI oscillator in Hz */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Inte + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrup + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + ARM GAS /tmp/cc0YOhsX.s page 7 + + + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Inter + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset f + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag * + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable * + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable * + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable * + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable * + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable * + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable * + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving cap + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capab + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capa + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /*!< Xtal mode higher driving capabilit + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + ARM GAS /tmp/cc0YOhsX.s page 8 + + + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC cl + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC cl + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC cl + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC c + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + ARM GAS /tmp/cc0YOhsX.s page 9 + + + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, n + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MC + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO s + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO s + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO s + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO s + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO s + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_HSI48) + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_HSI48 */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MC + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + ARM GAS /tmp/cc0YOhsX.s page 10 + + + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be prov + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART1SEL) + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART1SEL */ + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000U /*!< PCLK1 selected as LPUART1 c + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK selected as LPUART1 + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clo + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clo + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc0YOhsX.s page 11 + + + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4 + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SE + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SE + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C3SEL) + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4 + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SE + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SE + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CCIPR_I2C3SEL*/ + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(0x00000000U) /*!< PCLK1 selected as + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)RCC_CCIPR_LPTIM1SEL_0 /*!< LSI selected as LP + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)RCC_CCIPR_LPTIM1SEL_1 /*!< HSI selected as LP + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)RCC_CCIPR_LPTIM1SEL /*!< LSE selected as LP + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as RN + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as US + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART1SEL) + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selectio + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART1SEL */ + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selectio + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + ARM GAS /tmp/cc0YOhsX.s page 12 + + + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selecti + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bit + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C3SEL) + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bit + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CCIPR_I2C3SEL*/ + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selectio + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc0YOhsX.s page 13 + + + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** (selection through @re + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI c + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE c + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/cc0YOhsX.s page 14 + + + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Write a value in RCC register + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __REG__ Register to be written + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Read a value in RCC register + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __REG__ Register to be read + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Register value + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetMultiplicator (), + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetDivider ()); + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_24 + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_32 + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_48 + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __PLLDIV__ This parameter can be one of the following values: + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_2 + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_3 + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_4 + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMu + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __AHBPRESCALER__: This parameter can be one of the following values: + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 + ARM GAS /tmp/cc0YOhsX.s page 15 + + + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __APB1PRESCALER__: This parameter can be one of the following values: + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __APB2PRESCALER__: This parameter can be one of the following values: + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PCLK2 clock frequency (in Hz) + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the MSI frequency (in Hz) + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __MSIRANGE__: This parameter can be one of the following values: + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval MSI clock frequency (in Hz) + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MS + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc0YOhsX.s page 16 + + + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSECSS_SUPPORT) + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable the Clock Security System. + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSECSS_SUPPORT */ + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + ARM GAS /tmp/cc0YOhsX.s page 17 + + + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the RTC prescaler (divider) + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Div This parameter can be one of the following values: + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the RTC divider (prescaler) + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + ARM GAS /tmp/cc0YOhsX.s page 18 + + + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI oscillator + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI oscillator + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI clock is ready + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI even in stop mode + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note HSI oscillator is forced ON even in Stop mode + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIKERON); + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI in stop mode + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI Divider (it divides by 4) + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableDivider(void) + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + ARM GAS /tmp/cc0YOhsX.s page 19 + + + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIDIVEN); + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI Divider (it divides by 4) + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableDivider(void) + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN); + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CR_HSIOUTEN) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI Output + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableOutput(void) + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI Output + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableOutput(void) + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CR_HSIOUTEN */ + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI Calibration value + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * HSITRIM and the factory trim value + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL); + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/cc0YOhsX.s page 20 + + + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM); + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI48 + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI48 + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value + ARM GAS /tmp/cc0YOhsX.s page 21 + + + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL); + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CRRCR_HSI48DIV6OUTEN) + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI48 Divider (it divides by 6) + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void) + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI48 Divider (it divides by 6) +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void) +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI48 Divider is enabled (it divides by 6) +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void) +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == (RCC_CRRCR_HSI48DIV6OUTEN)); +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CRRCR_HSI48DIV6OUTEN*/ +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEON LL_RCC_LSE_Enable +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) + ARM GAS /tmp/cc0YOhsX.s page 22 + + +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSEON); +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEON LL_RCC_LSE_Disable +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive); +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + ARM GAS /tmp/cc0YOhsX.s page 23 + + +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV)); +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable Clock security system on LSE. +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable Clock security system on LSE. +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Clock security system can be disabled only after a LSE +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * failure detection. In that case it MUST be disabled by software. +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY)); +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if CSS on LSE failure Detection +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD)); +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/cc0YOhsX.s page 24 + + +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MSI MSI +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable MSI oscillator +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSION LL_RCC_MSI_Enable +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_Enable(void) +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_MSION); + 35 .loc 2 1195 0 + 36 0000 1A4A ldr r2, .L4 + 37 0002 1168 ldr r1, [r2] + 38 0004 8023 movs r3, #128 + 39 0006 5B00 lsls r3, r3, #1 + 40 0008 0B43 orrs r3, r1 + 41 000a 1360 str r3, [r2] + 42 000c 00E0 b .L2 + 43 .L3: + 44 .LBE155: + 45 .LBE154: + ARM GAS /tmp/cc0YOhsX.s page 25 + + + 46 .LBB156: + 47 .LBB157: + 48 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + ARM GAS /tmp/cc0YOhsX.s page 26 + + + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/cc0YOhsX.s page 27 + + + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc0YOhsX.s page 28 + + + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc0YOhsX.s page 29 + + + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + ARM GAS /tmp/cc0YOhsX.s page 30 + + + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */ + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0); + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */ + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + ARM GAS /tmp/cc0YOhsX.s page 31 + + + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile (""); + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop"); + 49 .loc 3 375 0 + 50 .syntax divided + 51 @ 375 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 52 000e C046 nop + 53 @ 0 "" 2 + 54 .thumb + 55 .syntax unified + 56 .L2: + 57 .LBE157: + 58 .LBE156: + 59 .LBB158: + 60 .LBB159: +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable MSI oscillator +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSION LL_RCC_MSI_Disable +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_Disable(void) +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + ARM GAS /tmp/cc0YOhsX.s page 32 + + +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_MSION); +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if MSI oscillator Ready +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); + 61 .loc 2 1215 0 + 62 0010 164B ldr r3, .L4 + 63 0012 1B68 ldr r3, [r3] + 64 .LBE159: + 65 .LBE158: + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t vl_mask = 0U; + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Set MSION bit */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_MSI_Enable(); + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Insure MSIRDY bit is set before writing default MSIRANGE value */ + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** while (LL_RCC_MSI_IsReady() == 0U) + 66 .loc 1 136 0 + 67 0014 9B05 lsls r3, r3, #22 + 68 0016 FAD5 bpl .L3 + 69 .LVL1: + 70 .LBB160: + 71 .LBB161: +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Range This parameter can be one of the following values: +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); + 72 .loc 2 1233 0 + 73 0018 144B ldr r3, .L4 + 74 001a 5A68 ldr r2, [r3, #4] + 75 001c 1449 ldr r1, .L4+4 + 76 001e 1140 ands r1, r2 + 77 0020 A022 movs r2, #160 + 78 0022 1202 lsls r2, r2, #8 + 79 0024 0A43 orrs r2, r1 + 80 0026 5A60 str r2, [r3, #4] + 81 .LVL2: + ARM GAS /tmp/cc0YOhsX.s page 33 + + + 82 .LBE161: + 83 .LBE160: + 84 .LBB162: + 85 .LBB163: +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get MSI Calibration value +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note When MSITRIM is written, MSICAL is updated with the sum of +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * MSITRIM and the factory trim value +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL); +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set MSI Calibration trimming +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the MSICAL +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0xFF +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); + 86 .loc 2 1274 0 + 87 0028 5A68 ldr r2, [r3, #4] + 88 002a 1202 lsls r2, r2, #8 + 89 002c 120A lsrs r2, r2, #8 + 90 002e 5A60 str r2, [r3, #4] + 91 .LVL3: + 92 .LBE163: + 93 .LBE162: + 94 .LBB164: + 95 .LBB165: + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 96 .loc 2 925 0 + ARM GAS /tmp/cc0YOhsX.s page 34 + + + 97 0030 5A68 ldr r2, [r3, #4] + 98 0032 1049 ldr r1, .L4+8 + 99 0034 1140 ands r1, r2 + 100 0036 8022 movs r2, #128 + 101 0038 5201 lsls r2, r2, #5 + 102 003a 0A43 orrs r2, r1 + 103 003c 5A60 str r2, [r3, #4] + 104 .LVL4: + 105 .LBE165: + 106 .LBE164: + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** __NOP(); + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Set MSIRANGE default value */ + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5); + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Set MSITRIM bits to the reset value*/ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_MSI_SetCalibTrimming(0U); + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Set HSITRIM bits to the reset value*/ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_HSI_SetCalibTrimming(0x10U); + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Reset SW, HPRE, PPRE and MCOSEL bits */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** vl_mask = 0xFFFFFFFFU; + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOS + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR, vl_mask); + 107 .loc 1 152 0 + 108 003e 0E4A ldr r2, .L4+12 + 109 0040 DA60 str r2, [r3, #12] + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Reset HSI, HSE, PLL */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** vl_mask = LL_RCC_ReadReg(CR); + 110 .loc 1 155 0 + 111 0042 1A68 ldr r2, [r3] + 112 .LVL5: + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CR_HSIOUTEN) + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + 113 .loc 1 157 0 + 114 0044 0D49 ldr r1, .L4+16 + 115 0046 0A40 ands r2, r1 + 116 .LVL6: + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_CR_HSEON | RCC_CR_PLLON); + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #else + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_CR_HSEON | RCC_CR_PLLON); + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CR, vl_mask); + 117 .loc 1 163 0 + 118 0048 1A60 str r2, [r3] + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Delay after an RCC peripheral clock */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** vl_mask = LL_RCC_ReadReg(CR); + 119 .loc 1 165 0 + 120 004a 1A68 ldr r2, [r3] + 121 .LVL7: + 122 .LBB166: + 123 .LBB167: + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + ARM GAS /tmp/cc0YOhsX.s page 35 + + + 124 .loc 2 737 0 + 125 004c 1968 ldr r1, [r3] + 126 004e 0C48 ldr r0, .L4+20 + 127 0050 0140 ands r1, r0 + 128 0052 1960 str r1, [r3] + 129 .LBE167: + 130 .LBE166: + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Reset HSEBYP bit */ + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_HSE_DisableBypass(); + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Set RCC_CR_RTCPRE to 0b00*/ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, RCC_CR_RTCPRE); + 131 .loc 1 171 0 + 132 0054 0B49 ldr r1, .L4+24 + 133 0056 0A40 ands r2, r1 + 134 .LVL8: + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CR, vl_mask); + 135 .loc 1 172 0 + 136 0058 1A60 str r2, [r3] + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Reset CFGR register */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR, 0x00000000U); + 137 .loc 1 175 0 + 138 005a 0022 movs r2, #0 + 139 .LVL9: + 140 005c DA60 str r2, [r3, #12] + 141 .LVL10: + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Reset CRRCR register */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CRRCR, 0x00000000U); + 142 .loc 1 179 0 + 143 005e 9A60 str r2, [r3, #8] + 144 .LBB168: + 145 .LBB169: + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 146 .loc 2 964 0 + 147 0060 9968 ldr r1, [r3, #8] + 148 0062 0120 movs r0, #1 + 149 0064 8143 bics r1, r0 + 150 0066 9960 str r1, [r3, #8] + 151 .LBE169: + 152 .LBE168: + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Disable HSI48 */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_HSI48_Disable(); + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /*RCC_HSI48_SUPPORT*/ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Disable all interrupts */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** LL_RCC_WriteReg(CIER, 0x00000000U); + 153 .loc 1 187 0 + 154 0068 1A61 str r2, [r3, #16] + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return SUCCESS; + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + ARM GAS /tmp/cc0YOhsX.s page 36 + + + 155 .loc 1 190 0 + 156 @ sp needed + 157 006a 7047 bx lr + 158 .L5: + 159 .align 2 + 160 .L4: + 161 006c 00100240 .word 1073876992 + 162 0070 FF1FFFFF .word -57345 + 163 0074 FFE0FFFF .word -7937 + 164 0078 0CC0FFF0 .word -251674612 + 165 007c D4FFFEFE .word -16842796 + 166 0080 FFFFFBFF .word -262145 + 167 0084 FFFFCFFF .word -3145729 + 168 .cfi_endproc + 169 .LFE176: + 171 .global __aeabi_uidiv + 172 .section .text.LL_RCC_GetUSBClockFreq,"ax",%progbits + 173 .align 1 + 174 .global LL_RCC_GetUSBClockFreq + 175 .syntax unified + 176 .code 16 + 177 .thumb_func + 178 .fpu softvfp + 180 LL_RCC_GetUSBClockFreq: + 181 .LFB182: + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @} + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Get_Freq + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses c + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * and different peripheral clocks available on the device. + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note If SYSCLK source is MSI, function returns values based on MSI clock(*) + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note (*) MSI clock depends on the selected MSI range but the real value + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * may vary depending on the variations in voltage and temperature. + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note (**) HSI_VALUE is a defined constant but the real value may vary + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * depending on the variations in voltage and temperature. + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note (***) HSE_VALUE is a defined constant, user has to ensure that + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * HSE_VALUE is same as the real frequency of the crystal used. + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * Otherwise, this function may have wrong result. + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note The result of this function could be incorrect when using fractional + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * value for HSE crystal. + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note This function can be used by the user application to compute the + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses c + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * must be called to update structure fields. Otherwise, any + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * configuration based on this function will be incorrect. + ARM GAS /tmp/cc0YOhsX.s page 37 + + + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval None + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* HCLK clock frequency */ + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK2 clock frequency */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return USARTx clock frequency + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param USARTxSource This parameter can be one of the following values: + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_USART1_CLKSOURCE + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * (*) value not defined in all devices. + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval USART clock frequency (in Hz) + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not read + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Check parameter */ + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CCIPR_USART1SEL) + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* USART1CLK clock frequency */ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + ARM GAS /tmp/cc0YOhsX.s page 38 + + + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* RCC_CCIPR_USART1SEL */ + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CCIPR_USART2SEL) + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* USART2CLK clock frequency */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* RCC_CCIPR_USART2SEL */ + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return usart_frequency; + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return I2Cx clock frequency + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param I2CxSource This parameter can be one of the following values: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C1_CLKSOURCE + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * (*) value not defined in all devices + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval I2C clock frequency (in Hz) + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + ARM GAS /tmp/cc0YOhsX.s page 39 + + + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Check parameter */ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* I2C1 CLK clock frequency */ + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(RCC_CCIPR_I2C3SEL) + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* I2C3 CLK clock frequency */ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /*RCC_CCIPR_I2C3SEL*/ + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return i2c_frequency; + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return LPUARTx clock frequency + ARM GAS /tmp/cc0YOhsX.s page 40 + + + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param LPUARTxSource This parameter can be one of the following values: + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval LPUART clock frequency (in Hz) + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not read + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Check parameter */ + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* LPUART1CLK clock frequency */ + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lpuart_frequency = RCC_GetSystemClockFreq(); + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lpuart_frequency = HSI_VALUE; + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lpuart_frequency = LSE_VALUE; + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return lpuart_frequency; + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return LPTIMx clock frequency + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param LPTIMxSource This parameter can be one of the following values: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval LPTIM clock frequency (in Hz) + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not read + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Check parameter */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + ARM GAS /tmp/cc0YOhsX.s page 41 + + + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* LPTIM1CLK clock frequency */ + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_LSI_IsReady()) + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lptim_frequency = LSI_VALUE; + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lptim_frequency = HSI_VALUE; + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lptim_frequency = LSE_VALUE; + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return lptim_frequency; + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #if defined(USB) + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return USBx clock frequency + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param USBxSource This parameter can be one of the following values: + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_USB_CLKSOURCE + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval USB clock frequency (in Hz) + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not re + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 182 .loc 1 496 0 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 0 + 185 @ frame_needed = 0, uses_anonymous_args = 0 + 186 .LVL11: + 187 0000 10B5 push {r4, lr} + 188 .LCFI0: + 189 .cfi_def_cfa_offset 8 + 190 .cfi_offset 4, -8 + 191 .cfi_offset 14, -4 + 192 .LVL12: + ARM GAS /tmp/cc0YOhsX.s page 42 + + + 193 .LBB170: + 194 .LBB171: +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get MSI Calibration trimming +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM); +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the system clock source +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the system clock source +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set AHB prescaler +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + ARM GAS /tmp/cc0YOhsX.s page 43 + + +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set APB2 prescaler +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get AHB prescaler +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + ARM GAS /tmp/cc0YOhsX.s page 44 + + +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get APB1 prescaler +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get APB2 prescaler +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set Clock After Wake-Up From Stop mode +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Clock This parameter can be one of the following values: +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get Clock After Wake-Up From Stop mode +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + ARM GAS /tmp/cc0YOhsX.s page 45 + + +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure MCOx +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR MCOPRE LL_RCC_ConfigMCO +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_MSI +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSI +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_8 +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_16 +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure USARTx clock source +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) + ARM GAS /tmp/cc0YOhsX.s page 46 + + +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure LPUART1x clock source +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPUARTxSource This parameter can be one of the following values: +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure I2Cx clock source +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U)); +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure LPTIMx clock source +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPTIMxSource This parameter can be one of the following values: +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + ARM GAS /tmp/cc0YOhsX.s page 47 + + +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource); +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure RNG clock source +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param RNGxSource This parameter can be one of the following values: +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource); +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure USB clock source +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource); +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get USARTx clock source +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE (*) +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. + ARM GAS /tmp/cc0YOhsX.s page 48 + + +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LPUARTx clock source +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPUARTx This parameter can be one of the following values: +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get I2Cx clock source +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U)); +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LPTIMx clock source +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPTIMx This parameter can be one of the following values: +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) + ARM GAS /tmp/cc0YOhsX.s page 49 + + +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx)); +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get RNGx clock source +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param RNGx This parameter can be one of the following values: +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get USBx clock source +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); + 195 .loc 2 1705 0 + 196 0002 164B ldr r3, .L16 + 197 0004 DB6C ldr r3, [r3, #76] + 198 .LVL13: + 199 .LBE171: + 200 .LBE170: + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Check parameter */ + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* USBCLK clock frequency */ + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetUSBClockSource(USBxSource)) + 201 .loc 1 503 0 + 202 0006 0342 tst r3, r0 + 203 0008 1FD1 bne .L14 + 204 .LBB172: + 205 .LBB173: +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/cc0YOhsX.s page 50 + + +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set RTC Clock Source +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed any more unless +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * set). The RTCRST bit can be used to reset them. +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get RTC Clock Source +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable RTC +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_EnableRTC +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_RTCEN); +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable RTC +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_DisableRTC +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + ARM GAS /tmp/cc0YOhsX.s page 51 + + +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN)); +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Force the Backup domain reset +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_RTCRST); +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Release the Backup domain reset +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable PLL +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable PLL +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc0YOhsX.s page 52 + + +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if PLL Ready +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 206 .loc 2 1837 0 + 207 000a 144B ldr r3, .L16 + 208 000c 1868 ldr r0, [r3] + 209 .LVL14: + 210 000e 8023 movs r3, #128 + 211 0010 9B04 lsls r3, r3, #18 + 212 0012 1840 ands r0, r3 + 213 .LBE173: + 214 .LBE172: + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) + 215 .loc 1 506 0 + 216 0014 1ED0 beq .L6 + 217 .LVL15: + 218 .LBB174: + 219 .LBB175: + 220 .LBB176: + 221 .LBB177: +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values: +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_24 +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_32 +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_48 +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param PLLDiv This parameter can be one of the following values: +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_2 +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_3 +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_4 +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/cc0YOhsX.s page 53 + + +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLD +1867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the oscillator used as PLL clock source. +1871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource +1872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +1874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +1877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); + 222 .loc 2 1878 0 + 223 0016 114B ldr r3, .L16 + 224 0018 DB68 ldr r3, [r3, #12] + 225 001a 8022 movs r2, #128 + 226 001c 5202 lsls r2, r2, #9 + 227 001e 1340 ands r3, r2 + 228 .LVL16: + 229 .LBE177: + 230 .LBE176: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** if (LL_RCC_HSI48_IsReady()) + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** usb_frequency = HSI48_VALUE; + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return usb_frequency; + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* USB */ + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @} + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @} + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Functions + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @{ + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return SYSTEM clock frequency + ARM GAS /tmp/cc0YOhsX.s page 54 + + + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval SYSTEM clock frequency (in Hz) + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void) + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t frequency = 0U; + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (LL_RCC_GetSysClkSource()) + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** frequency = HSI_VALUE; + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** frequency = HSE_VALUE; + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** frequency = RCC_PLL_GetFreqDomain_SYS(); + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return frequency; + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return HCLK clock frequency + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param SYSCLK_Frequency SYSCLK clock frequency + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval HCLK clock frequency (in Hz) + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* HCLK clock frequency */ + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return PCLK1 clock frequency + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param HCLK_Frequency HCLK clock frequency + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval PCLK1 clock frequency (in Hz) + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return PCLK2 clock frequency + ARM GAS /tmp/cc0YOhsX.s page 55 + + + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @param HCLK_Frequency HCLK clock frequency + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval PCLK2 clock frequency (in Hz) + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK2 clock frequency */ + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /** + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @brief Return PLL clock frequency used for system domain + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** * @retval PLL clock frequency (in Hz) + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** */ + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void) + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Get PLL source */ + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** switch (pllsource) + 231 .loc 1 618 0 + 232 0020 9342 cmp r3, r2 + 233 0022 01D0 beq .L12 + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 234 .loc 1 621 0 + 235 0024 0E48 ldr r0, .L16+4 + 236 0026 00E0 b .L11 + 237 .L12: + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; + 238 .loc 1 625 0 + 239 0028 0E48 ldr r0, .L16+8 + 240 .L11: + 241 .LVL17: + 242 .LBB178: + 243 .LBB179: +1879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get PLL multiplication Factor +1883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator +1884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_24 +1892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_32 + ARM GAS /tmp/cc0YOhsX.s page 56 + + +1893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_48 +1894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +1896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); + 244 .loc 2 1897 0 + 245 002a 0C49 ldr r1, .L16 + 246 002c CA68 ldr r2, [r1, #12] + 247 .LBE179: + 248 .LBE178: + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** default: + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivid + 249 .loc 1 632 0 + 250 002e 920C lsrs r2, r2, #18 + 251 0030 0F23 movs r3, #15 + 252 0032 1340 ands r3, r2 + 253 0034 0C4A ldr r2, .L16+12 + 254 0036 D35C ldrb r3, [r2, r3] + 255 0038 5843 muls r0, r3 + 256 .LVL18: + 257 .LBB180: + 258 .LBB181: +1898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get Division factor for the main PLL and other PLL +1902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider +1903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_2 +1905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_3 +1906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_4 +1907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +1909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); + 259 .loc 2 1910 0 + 260 003a CB68 ldr r3, [r1, #12] + 261 .LBE181: + 262 .LBE180: + 263 .loc 1 632 0 + 264 003c 9B0D lsrs r3, r3, #22 + 265 003e 0321 movs r1, #3 + 266 0040 1940 ands r1, r3 + 267 0042 0131 adds r1, r1, #1 + 268 0044 FFF7FEFF bl __aeabi_uidiv + 269 .LVL19: + 270 0048 04E0 b .L6 + 271 .LVL20: + 272 .L14: + 273 .LBE175: + 274 .LBE174: + 275 .LBB182: + ARM GAS /tmp/cc0YOhsX.s page 57 + + + 276 .LBB183: + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 277 .loc 2 974 0 + 278 004a 044B ldr r3, .L16 + 279 004c 9B68 ldr r3, [r3, #8] + 280 004e 0220 movs r0, #2 + 281 .LVL21: + 282 0050 1840 ands r0, r3 + 283 .LBE183: + 284 .LBE182: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 285 .loc 1 514 0 + 286 0052 00D1 bne .L15 + 287 .LVL22: + 288 .L6: + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** #endif /* USB */ + 289 .loc 1 522 0 + 290 @ sp needed + 291 0054 10BD pop {r4, pc} + 292 .LVL23: + 293 .L15: + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 294 .loc 1 516 0 + 295 0056 0548 ldr r0, .L16+16 + 296 .LVL24: + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 297 .loc 1 521 0 + 298 0058 FCE7 b .L6 + 299 .L17: + 300 005a C046 .align 2 + 301 .L16: + 302 005c 00100240 .word 1073876992 + 303 0060 0024F400 .word 16000000 + 304 0064 00127A00 .word 8000000 + 305 0068 00000000 .word PLLMulTable + 306 006c 006CDC02 .word 48000000 + 307 .cfi_endproc + 308 .LFE182: + 310 .section .text.RCC_GetSystemClockFreq,"ax",%progbits + 311 .align 1 + 312 .global RCC_GetSystemClockFreq + 313 .syntax unified + 314 .code 16 + 315 .thumb_func + 316 .fpu softvfp + 318 RCC_GetSystemClockFreq: + 319 .LFB183: + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t frequency = 0U; + 320 .loc 1 542 0 + 321 .cfi_startproc + 322 @ args = 0, pretend = 0, frame = 0 + 323 @ frame_needed = 0, uses_anonymous_args = 0 + 324 0000 10B5 push {r4, lr} + 325 .LCFI1: + 326 .cfi_def_cfa_offset 8 + 327 .cfi_offset 4, -8 + 328 .cfi_offset 14, -4 + ARM GAS /tmp/cc0YOhsX.s page 58 + + + 329 .LVL25: + 330 .LBB184: + 331 .LBB185: +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 332 .loc 2 1321 0 + 333 0002 1F4B ldr r3, .L30 + 334 0004 DA68 ldr r2, [r3, #12] + 335 0006 0C23 movs r3, #12 + 336 0008 1340 ands r3, r2 + 337 .LBE185: + 338 .LBE184: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 339 .loc 1 546 0 + 340 000a 042B cmp r3, #4 + 341 000c 19D0 beq .L20 + 342 000e 0CD9 bls .L29 + 343 0010 082B cmp r3, #8 + 344 0012 33D0 beq .L27 + 345 0014 0C2B cmp r3, #12 + 346 0016 27D1 bne .L19 + 347 .LVL26: + 348 .LBB186: + 349 .LBB187: + 350 .LBB188: + 351 .LBB189: +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 352 .loc 2 1878 0 + 353 0018 194B ldr r3, .L30 + 354 001a DB68 ldr r3, [r3, #12] + 355 001c 8022 movs r2, #128 + 356 001e 5202 lsls r2, r2, #9 + 357 0020 1340 ands r3, r2 + 358 .LVL27: + 359 .LBE189: + 360 .LBE188: + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 361 .loc 1 618 0 + 362 0022 9342 cmp r3, r2 + 363 0024 0FD0 beq .L28 + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 364 .loc 1 621 0 + 365 0026 1748 ldr r0, .L30+4 + 366 0028 0EE0 b .L26 + 367 .LVL28: + 368 .L29: + 369 .LBE187: + 370 .LBE186: + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 371 .loc 1 546 0 + 372 002a 002B cmp r3, #0 + 373 002c 1CD1 bne .L19 + 374 .LBB195: + 375 .LBB196: +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 376 .loc 2 1250 0 + 377 002e 144B ldr r3, .L30 + 378 0030 5A68 ldr r2, [r3, #4] + ARM GAS /tmp/cc0YOhsX.s page 59 + + + 379 .LBE196: + 380 .LBE195: + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 381 .loc 1 549 0 + 382 0032 520B lsrs r2, r2, #13 + 383 0034 0723 movs r3, #7 + 384 0036 1340 ands r3, r2 + 385 0038 0133 adds r3, r3, #1 + 386 003a 8020 movs r0, #128 + 387 003c 0002 lsls r0, r0, #8 + 388 003e 9840 lsls r0, r0, r3 + 389 .LVL29: + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 390 .loc 1 550 0 + 391 0040 00E0 b .L18 + 392 .LVL30: + 393 .L20: + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 394 .loc 1 553 0 + 395 0042 1048 ldr r0, .L30+4 + 396 .LVL31: + 397 .L18: + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 398 .loc 1 570 0 + 399 @ sp needed + 400 0044 10BD pop {r4, pc} + 401 .LVL32: + 402 .L28: + 403 .LBB197: + 404 .LBB194: + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 405 .loc 1 625 0 + 406 0046 1048 ldr r0, .L30+8 + 407 .L26: + 408 .LVL33: + 409 .LBB190: + 410 .LBB191: +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 411 .loc 2 1897 0 + 412 0048 0D49 ldr r1, .L30 + 413 004a CA68 ldr r2, [r1, #12] + 414 .LBE191: + 415 .LBE190: + 416 .loc 1 632 0 + 417 004c 920C lsrs r2, r2, #18 + 418 004e 0F23 movs r3, #15 + 419 0050 1340 ands r3, r2 + 420 0052 0E4A ldr r2, .L30+12 + 421 0054 D35C ldrb r3, [r2, r3] + 422 0056 5843 muls r0, r3 + 423 .LVL34: + 424 .LBB192: + 425 .LBB193: + 426 .loc 2 1910 0 + 427 0058 CB68 ldr r3, [r1, #12] + 428 .LBE193: + 429 .LBE192: + ARM GAS /tmp/cc0YOhsX.s page 60 + + + 430 .loc 1 632 0 + 431 005a 9B0D lsrs r3, r3, #22 + 432 005c 0321 movs r1, #3 + 433 005e 1940 ands r1, r3 + 434 0060 0131 adds r1, r1, #1 + 435 0062 FFF7FEFF bl __aeabi_uidiv + 436 .LVL35: + 437 .LBE194: + 438 .LBE197: + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 439 .loc 1 562 0 + 440 0066 EDE7 b .L18 + 441 .LVL36: + 442 .L19: + 443 .LBB198: + 444 .LBB199: +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 445 .loc 2 1250 0 + 446 0068 054B ldr r3, .L30 + 447 006a 5A68 ldr r2, [r3, #4] + 448 .LBE199: + 449 .LBE198: + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 450 .loc 1 565 0 + 451 006c 520B lsrs r2, r2, #13 + 452 006e 0723 movs r3, #7 + 453 0070 1340 ands r3, r2 + 454 0072 0133 adds r3, r3, #1 + 455 0074 8020 movs r0, #128 + 456 0076 0002 lsls r0, r0, #8 + 457 0078 9840 lsls r0, r0, r3 + 458 .LVL37: + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 459 .loc 1 566 0 + 460 007a E3E7 b .L18 + 461 .LVL38: + 462 .L27: + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 463 .loc 1 557 0 + 464 007c 0248 ldr r0, .L30+8 + 465 .LVL39: + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 466 .loc 1 569 0 + 467 007e E1E7 b .L18 + 468 .L31: + 469 .align 2 + 470 .L30: + 471 0080 00100240 .word 1073876992 + 472 0084 0024F400 .word 16000000 + 473 0088 00127A00 .word 8000000 + 474 008c 00000000 .word PLLMulTable + 475 .cfi_endproc + 476 .LFE183: + 478 .section .text.LL_RCC_GetSystemClocksFreq,"ax",%progbits + 479 .align 1 + 480 .global LL_RCC_GetSystemClocksFreq + 481 .syntax unified + ARM GAS /tmp/cc0YOhsX.s page 61 + + + 482 .code 16 + 483 .thumb_func + 484 .fpu softvfp + 486 LL_RCC_GetSystemClocksFreq: + 487 .LFB177: + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 488 .loc 1 227 0 + 489 .cfi_startproc + 490 @ args = 0, pretend = 0, frame = 0 + 491 @ frame_needed = 0, uses_anonymous_args = 0 + 492 .LVL40: + 493 0000 70B5 push {r4, r5, r6, lr} + 494 .LCFI2: + 495 .cfi_def_cfa_offset 16 + 496 .cfi_offset 4, -16 + 497 .cfi_offset 5, -12 + 498 .cfi_offset 6, -8 + 499 .cfi_offset 14, -4 + 500 0002 0400 movs r4, r0 + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 501 .loc 1 229 0 + 502 0004 FFF7FEFF bl RCC_GetSystemClockFreq + 503 .LVL41: + 504 0008 2060 str r0, [r4] + 505 .LVL42: + 506 .LBB200: + 507 .LBB201: + 508 .LBB202: + 509 .LBB203: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 510 .loc 2 1392 0 + 511 000a 0C4D ldr r5, .L33 + 512 000c EA68 ldr r2, [r5, #12] + 513 .LBE203: + 514 .LBE202: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 515 .loc 1 580 0 + 516 000e 1209 lsrs r2, r2, #4 + 517 0010 0F23 movs r3, #15 + 518 0012 1340 ands r3, r2 + 519 0014 0A4A ldr r2, .L33+4 + 520 0016 D35C ldrb r3, [r2, r3] + 521 0018 D840 lsrs r0, r0, r3 + 522 .LVL43: + 523 .LBE201: + 524 .LBE200: + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 525 .loc 1 232 0 + 526 001a 6060 str r0, [r4, #4] + 527 .LVL44: + 528 .LBB204: + 529 .LBB205: + 530 .LBB206: + 531 .LBB207: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 532 .loc 2 1407 0 + 533 001c EB68 ldr r3, [r5, #12] + ARM GAS /tmp/cc0YOhsX.s page 62 + + + 534 .LBE207: + 535 .LBE206: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 536 .loc 1 591 0 + 537 001e 1B0A lsrs r3, r3, #8 + 538 0020 0722 movs r2, #7 + 539 0022 1340 ands r3, r2 + 540 0024 0749 ldr r1, .L33+8 + 541 0026 CB5C ldrb r3, [r1, r3] + 542 0028 0600 movs r6, r0 + 543 002a DE40 lsrs r6, r6, r3 + 544 .LVL45: + 545 .LBE205: + 546 .LBE204: + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 547 .loc 1 235 0 + 548 002c A660 str r6, [r4, #8] + 549 .LVL46: + 550 .LBB208: + 551 .LBB209: + 552 .LBB210: + 553 .LBB211: +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 554 .loc 2 1422 0 + 555 002e EB68 ldr r3, [r5, #12] + 556 .LBE211: + 557 .LBE210: + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 558 .loc 1 602 0 + 559 0030 DB0A lsrs r3, r3, #11 + 560 0032 1A40 ands r2, r3 + 561 0034 8B5C ldrb r3, [r1, r2] + 562 0036 D840 lsrs r0, r0, r3 + 563 .LVL47: + 564 .LBE209: + 565 .LBE208: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 566 .loc 1 238 0 + 567 0038 E060 str r0, [r4, #12] + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 568 .loc 1 239 0 + 569 @ sp needed + 570 .LVL48: + 571 003a 70BD pop {r4, r5, r6, pc} + 572 .L34: + 573 .align 2 + 574 .L33: + 575 003c 00100240 .word 1073876992 + 576 0040 00000000 .word AHBPrescTable + 577 0044 00000000 .word APBPrescTable + 578 .cfi_endproc + 579 .LFE177: + 581 .section .text.LL_RCC_GetUSARTClockFreq,"ax",%progbits + 582 .align 1 + 583 .global LL_RCC_GetUSARTClockFreq + 584 .syntax unified + 585 .code 16 + ARM GAS /tmp/cc0YOhsX.s page 63 + + + 586 .thumb_func + 587 .fpu softvfp + 589 LL_RCC_GetUSARTClockFreq: + 590 .LFB178: + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 591 .loc 1 252 0 + 592 .cfi_startproc + 593 @ args = 0, pretend = 0, frame = 0 + 594 @ frame_needed = 0, uses_anonymous_args = 0 + 595 .LVL49: + 596 0000 10B5 push {r4, lr} + 597 .LCFI3: + 598 .cfi_def_cfa_offset 8 + 599 .cfi_offset 4, -8 + 600 .cfi_offset 14, -4 + 601 0002 0400 movs r4, r0 + 602 .LVL50: + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 603 .loc 1 258 0 + 604 0004 0328 cmp r0, #3 + 605 0006 03D0 beq .L53 + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 606 .loc 1 253 0 + 607 0008 0020 movs r0, #0 + 608 .LVL51: + 609 .L36: + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 610 .loc 1 290 0 + 611 000a 0C2C cmp r4, #12 + 612 000c 33D0 beq .L54 + 613 .LVL52: + 614 .L35: + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 615 .loc 1 322 0 + 616 @ sp needed + 617 000e 10BD pop {r4, pc} + 618 .LVL53: + 619 .L53: + 620 .LBB212: + 621 .LBB213: +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 622 .loc 2 1618 0 + 623 0010 314B ldr r3, .L57 + 624 0012 DB6C ldr r3, [r3, #76] + 625 0014 0340 ands r3, r0 + 626 0016 0204 lsls r2, r0, #16 + 627 0018 1343 orrs r3, r2 + 628 .LVL54: + 629 .LBE213: + 630 .LBE212: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 631 .loc 1 261 0 + 632 001a 304A ldr r2, .L57+4 + 633 001c 9342 cmp r3, r2 + 634 001e 1AD0 beq .L38 + 635 0020 2F4A ldr r2, .L57+8 + 636 0022 9342 cmp r3, r2 + ARM GAS /tmp/cc0YOhsX.s page 64 + + + 637 0024 1ED0 beq .L39 + 638 0026 2F4A ldr r2, .L57+12 + 639 0028 9342 cmp r3, r2 + 640 002a 11D0 beq .L55 + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 641 .loc 1 283 0 + 642 002c FFF7FEFF bl RCC_GetSystemClockFreq + 643 .LVL55: + 644 .LBB214: + 645 .LBB215: + 646 .LBB216: + 647 .LBB217: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 648 .loc 2 1392 0 + 649 0030 2949 ldr r1, .L57 + 650 0032 CA68 ldr r2, [r1, #12] + 651 .LBE217: + 652 .LBE216: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 653 .loc 1 580 0 + 654 0034 1209 lsrs r2, r2, #4 + 655 0036 0F23 movs r3, #15 + 656 0038 1340 ands r3, r2 + 657 003a 2B4A ldr r2, .L57+16 + 658 003c D35C ldrb r3, [r2, r3] + 659 003e D840 lsrs r0, r0, r3 + 660 .LVL56: + 661 .LBE215: + 662 .LBE214: + 663 .LBB218: + 664 .LBB219: + 665 .LBB220: + 666 .LBB221: +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 667 .loc 2 1422 0 + 668 0040 CA68 ldr r2, [r1, #12] + 669 .LBE221: + 670 .LBE220: + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 671 .loc 1 602 0 + 672 0042 D20A lsrs r2, r2, #11 + 673 0044 0723 movs r3, #7 + 674 0046 1340 ands r3, r2 + 675 0048 284A ldr r2, .L57+20 + 676 004a D35C ldrb r3, [r2, r3] + 677 004c D840 lsrs r0, r0, r3 + 678 .LVL57: + 679 .LBE219: + 680 .LBE218: + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 681 .loc 1 284 0 + 682 004e DCE7 b .L36 + 683 .LVL58: + 684 .L55: + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 685 .loc 1 264 0 + 686 0050 FFF7FEFF bl RCC_GetSystemClockFreq + ARM GAS /tmp/cc0YOhsX.s page 65 + + + 687 .LVL59: + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 688 .loc 1 265 0 + 689 0054 D9E7 b .L36 + 690 .LVL60: + 691 .L38: + 692 .LBB222: + 693 .LBB223: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 694 .loc 2 834 0 + 695 0056 204B ldr r3, .L57 + 696 0058 1868 ldr r0, [r3] + 697 .LVL61: + 698 005a 0423 movs r3, #4 + 699 005c 1840 ands r0, r3 + 700 .LBE223: + 701 .LBE222: + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 702 .loc 1 268 0 + 703 005e D4D0 beq .L36 + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 704 .loc 1 270 0 + 705 0060 2348 ldr r0, .L57+24 + 706 0062 D2E7 b .L36 + 707 .LVL62: + 708 .L39: + 709 .LBB224: + 710 .LBB225: +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 711 .loc 2 1129 0 + 712 0064 1C4B ldr r3, .L57 + 713 0066 1B6D ldr r3, [r3, #80] + 714 0068 8020 movs r0, #128 + 715 .LVL63: + 716 006a 8000 lsls r0, r0, #2 + 717 006c 1840 ands r0, r3 + 718 .LBE225: + 719 .LBE224: + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 720 .loc 1 275 0 + 721 006e CCD0 beq .L36 + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 722 .loc 1 277 0 + 723 0070 8020 movs r0, #128 + 724 0072 0002 lsls r0, r0, #8 + 725 0074 C9E7 b .L36 + 726 .LVL64: + 727 .L54: + 728 .LBB226: + 729 .LBB227: +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 730 .loc 2 1618 0 + 731 0076 184B ldr r3, .L57 + 732 0078 DB6C ldr r3, [r3, #76] + 733 007a 2340 ands r3, r4 + 734 007c 2404 lsls r4, r4, #16 + 735 .LVL65: + ARM GAS /tmp/cc0YOhsX.s page 66 + + + 736 007e 1C43 orrs r4, r3 + 737 .LVL66: + 738 .LBE227: + 739 .LBE226: + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 740 .loc 1 293 0 + 741 0080 1C4B ldr r3, .L57+28 + 742 0082 9C42 cmp r4, r3 + 743 0084 1AD0 beq .L43 + 744 0086 1C4B ldr r3, .L57+32 + 745 0088 9C42 cmp r4, r3 + 746 008a 1DD0 beq .L44 + 747 008c 1B4B ldr r3, .L57+36 + 748 008e 9C42 cmp r4, r3 + 749 0090 11D0 beq .L56 + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 750 .loc 1 315 0 + 751 0092 FFF7FEFF bl RCC_GetSystemClockFreq + 752 .LVL67: + 753 .LBB228: + 754 .LBB229: + 755 .LBB230: + 756 .LBB231: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 757 .loc 2 1392 0 + 758 0096 1049 ldr r1, .L57 + 759 0098 CA68 ldr r2, [r1, #12] + 760 .LBE231: + 761 .LBE230: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 762 .loc 1 580 0 + 763 009a 1209 lsrs r2, r2, #4 + 764 009c 0F23 movs r3, #15 + 765 009e 1340 ands r3, r2 + 766 00a0 114A ldr r2, .L57+16 + 767 00a2 D35C ldrb r3, [r2, r3] + 768 00a4 D840 lsrs r0, r0, r3 + 769 .LVL68: + 770 .LBE229: + 771 .LBE228: + 772 .LBB232: + 773 .LBB233: + 774 .LBB234: + 775 .LBB235: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 776 .loc 2 1407 0 + 777 00a6 CA68 ldr r2, [r1, #12] + 778 .LBE235: + 779 .LBE234: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 780 .loc 1 591 0 + 781 00a8 120A lsrs r2, r2, #8 + 782 00aa 0723 movs r3, #7 + 783 00ac 1340 ands r3, r2 + 784 00ae 0F4A ldr r2, .L57+20 + 785 00b0 D35C ldrb r3, [r2, r3] + 786 00b2 D840 lsrs r0, r0, r3 + ARM GAS /tmp/cc0YOhsX.s page 67 + + + 787 .LBE233: + 788 .LBE232: + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 789 .loc 1 316 0 + 790 00b4 ABE7 b .L35 + 791 .LVL69: + 792 .L56: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 793 .loc 1 296 0 + 794 00b6 FFF7FEFF bl RCC_GetSystemClockFreq + 795 .LVL70: + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 796 .loc 1 297 0 + 797 00ba A8E7 b .L35 + 798 .L43: + 799 .LBB236: + 800 .LBB237: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 801 .loc 2 834 0 + 802 00bc 064B ldr r3, .L57 + 803 00be 1B68 ldr r3, [r3] + 804 .LBE237: + 805 .LBE236: + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 806 .loc 1 300 0 + 807 00c0 5B07 lsls r3, r3, #29 + 808 00c2 A4D5 bpl .L35 + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 809 .loc 1 302 0 + 810 00c4 0A48 ldr r0, .L57+24 + 811 .LVL71: + 812 00c6 A2E7 b .L35 + 813 .LVL72: + 814 .L44: + 815 .LBB238: + 816 .LBB239: +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 817 .loc 2 1129 0 + 818 00c8 034B ldr r3, .L57 + 819 00ca 1B6D ldr r3, [r3, #80] + 820 .LBE239: + 821 .LBE238: + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 822 .loc 1 307 0 + 823 00cc 9B05 lsls r3, r3, #22 + 824 00ce 9ED5 bpl .L35 + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 825 .loc 1 309 0 + 826 00d0 8020 movs r0, #128 + 827 .LVL73: + 828 00d2 0002 lsls r0, r0, #8 + 829 .LVL74: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 830 .loc 1 321 0 + 831 00d4 9BE7 b .L35 + 832 .L58: + 833 00d6 C046 .align 2 + ARM GAS /tmp/cc0YOhsX.s page 68 + + + 834 .L57: + 835 00d8 00100240 .word 1073876992 + 836 00dc 02000300 .word 196610 + 837 00e0 03000300 .word 196611 + 838 00e4 01000300 .word 196609 + 839 00e8 00000000 .word AHBPrescTable + 840 00ec 00000000 .word APBPrescTable + 841 00f0 0024F400 .word 16000000 + 842 00f4 08000C00 .word 786440 + 843 00f8 0C000C00 .word 786444 + 844 00fc 04000C00 .word 786436 + 845 .cfi_endproc + 846 .LFE178: + 848 .section .text.LL_RCC_GetI2CClockFreq,"ax",%progbits + 849 .align 1 + 850 .global LL_RCC_GetI2CClockFreq + 851 .syntax unified + 852 .code 16 + 853 .thumb_func + 854 .fpu softvfp + 856 LL_RCC_GetI2CClockFreq: + 857 .LFB179: + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 858 .loc 1 335 0 + 859 .cfi_startproc + 860 @ args = 0, pretend = 0, frame = 0 + 861 @ frame_needed = 0, uses_anonymous_args = 0 + 862 .LVL75: + 863 0000 10B5 push {r4, lr} + 864 .LCFI4: + 865 .cfi_def_cfa_offset 8 + 866 .cfi_offset 4, -8 + 867 .cfi_offset 14, -4 + 868 0002 0400 movs r4, r0 + 869 .LVL76: + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 870 .loc 1 342 0 + 871 0004 C023 movs r3, #192 + 872 0006 9B01 lsls r3, r3, #6 + 873 0008 9842 cmp r0, r3 + 874 000a 05D0 beq .L73 + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 875 .loc 1 336 0 + 876 000c 0020 movs r0, #0 + 877 .LVL77: + 878 .L60: + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 879 .loc 1 366 0 + 880 000e C023 movs r3, #192 + 881 0010 9B02 lsls r3, r3, #10 + 882 0012 9C42 cmp r4, r3 + 883 0014 28D0 beq .L74 + 884 .LVL78: + 885 .L59: + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 886 .loc 1 390 0 + 887 @ sp needed + ARM GAS /tmp/cc0YOhsX.s page 69 + + + 888 0016 10BD pop {r4, pc} + 889 .LVL79: + 890 .L73: + 891 .LBB240: + 892 .LBB241: +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 893 .loc 2 1657 0 + 894 0018 274B ldr r3, .L75 + 895 001a DB6C ldr r3, [r3, #76] + 896 001c 0340 ands r3, r0 + 897 001e 1B09 lsrs r3, r3, #4 + 898 0020 0201 lsls r2, r0, #4 + 899 0022 1343 orrs r3, r2 + 900 .LVL80: + 901 .LBE241: + 902 .LBE240: + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 903 .loc 1 344 0 + 904 0024 254A ldr r2, .L75+4 + 905 0026 9342 cmp r3, r2 + 906 0028 14D0 beq .L62 + 907 002a 254A ldr r2, .L75+8 + 908 002c 9342 cmp r3, r2 + 909 002e 14D0 beq .L63 + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 910 .loc 1 359 0 + 911 0030 FFF7FEFF bl RCC_GetSystemClockFreq + 912 .LVL81: + 913 .LBB242: + 914 .LBB243: + 915 .LBB244: + 916 .LBB245: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 917 .loc 2 1392 0 + 918 0034 2049 ldr r1, .L75 + 919 0036 CA68 ldr r2, [r1, #12] + 920 .LBE245: + 921 .LBE244: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 922 .loc 1 580 0 + 923 0038 1209 lsrs r2, r2, #4 + 924 003a 0F23 movs r3, #15 + 925 003c 1340 ands r3, r2 + 926 003e 214A ldr r2, .L75+12 + 927 0040 D35C ldrb r3, [r2, r3] + 928 0042 D840 lsrs r0, r0, r3 + 929 .LVL82: + 930 .LBE243: + 931 .LBE242: + 932 .LBB246: + 933 .LBB247: + 934 .LBB248: + 935 .LBB249: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 936 .loc 2 1407 0 + 937 0044 CA68 ldr r2, [r1, #12] + 938 .LBE249: + ARM GAS /tmp/cc0YOhsX.s page 70 + + + 939 .LBE248: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 940 .loc 1 591 0 + 941 0046 120A lsrs r2, r2, #8 + 942 0048 0723 movs r3, #7 + 943 004a 1340 ands r3, r2 + 944 004c 1E4A ldr r2, .L75+16 + 945 004e D35C ldrb r3, [r2, r3] + 946 0050 D840 lsrs r0, r0, r3 + 947 .LVL83: + 948 .LBE247: + 949 .LBE246: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 950 .loc 1 360 0 + 951 0052 DCE7 b .L60 + 952 .LVL84: + 953 .L62: + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 954 .loc 1 347 0 + 955 0054 FFF7FEFF bl RCC_GetSystemClockFreq + 956 .LVL85: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 957 .loc 1 348 0 + 958 0058 D9E7 b .L60 + 959 .LVL86: + 960 .L63: + 961 .LBB250: + 962 .LBB251: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 963 .loc 2 834 0 + 964 005a 174B ldr r3, .L75 + 965 005c 1868 ldr r0, [r3] + 966 .LVL87: + 967 005e 0423 movs r3, #4 + 968 0060 1840 ands r0, r3 + 969 .LBE251: + 970 .LBE250: + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 971 .loc 1 351 0 + 972 0062 D4D0 beq .L60 + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 973 .loc 1 353 0 + 974 0064 1948 ldr r0, .L75+20 + 975 0066 D2E7 b .L60 + 976 .LVL88: + 977 .L74: + 978 .LBB252: + 979 .LBB253: +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 980 .loc 2 1657 0 + 981 0068 134B ldr r3, .L75 + 982 006a DB6C ldr r3, [r3, #76] + 983 006c 2340 ands r3, r4 + 984 006e 1B09 lsrs r3, r3, #4 + 985 0070 2401 lsls r4, r4, #4 + 986 .LVL89: + 987 0072 1C43 orrs r4, r3 + ARM GAS /tmp/cc0YOhsX.s page 71 + + + 988 .LVL90: + 989 .LBE253: + 990 .LBE252: + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 991 .loc 1 368 0 + 992 0074 164B ldr r3, .L75+24 + 993 0076 9C42 cmp r4, r3 + 994 0078 14D0 beq .L66 + 995 007a 164B ldr r3, .L75+28 + 996 007c 9C42 cmp r4, r3 + 997 007e 14D0 beq .L67 + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 998 .loc 1 383 0 + 999 0080 FFF7FEFF bl RCC_GetSystemClockFreq + 1000 .LVL91: + 1001 .LBB254: + 1002 .LBB255: + 1003 .LBB256: + 1004 .LBB257: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1005 .loc 2 1392 0 + 1006 0084 0C49 ldr r1, .L75 + 1007 0086 CA68 ldr r2, [r1, #12] + 1008 .LBE257: + 1009 .LBE256: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1010 .loc 1 580 0 + 1011 0088 1209 lsrs r2, r2, #4 + 1012 008a 0F23 movs r3, #15 + 1013 008c 1340 ands r3, r2 + 1014 008e 0D4A ldr r2, .L75+12 + 1015 0090 D35C ldrb r3, [r2, r3] + 1016 0092 D840 lsrs r0, r0, r3 + 1017 .LVL92: + 1018 .LBE255: + 1019 .LBE254: + 1020 .LBB258: + 1021 .LBB259: + 1022 .LBB260: + 1023 .LBB261: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1024 .loc 2 1407 0 + 1025 0094 CA68 ldr r2, [r1, #12] + 1026 .LBE261: + 1027 .LBE260: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1028 .loc 1 591 0 + 1029 0096 120A lsrs r2, r2, #8 + 1030 0098 0723 movs r3, #7 + 1031 009a 1340 ands r3, r2 + 1032 009c 0A4A ldr r2, .L75+16 + 1033 009e D35C ldrb r3, [r2, r3] + 1034 00a0 D840 lsrs r0, r0, r3 + 1035 .LBE259: + 1036 .LBE258: + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1037 .loc 1 384 0 + ARM GAS /tmp/cc0YOhsX.s page 72 + + + 1038 00a2 B8E7 b .L59 + 1039 .LVL93: + 1040 .L66: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1041 .loc 1 371 0 + 1042 00a4 FFF7FEFF bl RCC_GetSystemClockFreq + 1043 .LVL94: + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1044 .loc 1 372 0 + 1045 00a8 B5E7 b .L59 + 1046 .L67: + 1047 .LBB262: + 1048 .LBB263: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1049 .loc 2 834 0 + 1050 00aa 034B ldr r3, .L75 + 1051 00ac 1B68 ldr r3, [r3] + 1052 .LBE263: + 1053 .LBE262: + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1054 .loc 1 375 0 + 1055 00ae 5B07 lsls r3, r3, #29 + 1056 00b0 B1D5 bpl .L59 + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1057 .loc 1 377 0 + 1058 00b2 0648 ldr r0, .L75+20 + 1059 .LVL95: + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1060 .loc 1 389 0 + 1061 00b4 AFE7 b .L59 + 1062 .L76: + 1063 00b6 C046 .align 2 + 1064 .L75: + 1065 00b8 00100240 .word 1073876992 + 1066 00bc 00010300 .word 196864 + 1067 00c0 00020300 .word 197120 + 1068 00c4 00000000 .word AHBPrescTable + 1069 00c8 00000000 .word APBPrescTable + 1070 00cc 0024F400 .word 16000000 + 1071 00d0 00103000 .word 3149824 + 1072 00d4 00203000 .word 3153920 + 1073 .cfi_endproc + 1074 .LFE179: + 1076 .section .text.LL_RCC_GetLPUARTClockFreq,"ax",%progbits + 1077 .align 1 + 1078 .global LL_RCC_GetLPUARTClockFreq + 1079 .syntax unified + 1080 .code 16 + 1081 .thumb_func + 1082 .fpu softvfp + 1084 LL_RCC_GetLPUARTClockFreq: + 1085 .LFB180: + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1086 .loc 1 400 0 + 1087 .cfi_startproc + 1088 @ args = 0, pretend = 0, frame = 0 + 1089 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc0YOhsX.s page 73 + + + 1090 .LVL96: + 1091 0000 10B5 push {r4, lr} + 1092 .LCFI5: + 1093 .cfi_def_cfa_offset 8 + 1094 .cfi_offset 4, -8 + 1095 .cfi_offset 14, -4 + 1096 .LVL97: + 1097 .LBB264: + 1098 .LBB265: +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1099 .loc 2 1636 0 + 1100 0002 1A4B ldr r3, .L87 + 1101 0004 DB6C ldr r3, [r3, #76] + 1102 0006 1840 ands r0, r3 + 1103 .LVL98: + 1104 .LBE265: + 1105 .LBE264: + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1106 .loc 1 407 0 + 1107 0008 8023 movs r3, #128 + 1108 000a 1B01 lsls r3, r3, #4 + 1109 000c 9842 cmp r0, r3 + 1110 000e 1CD0 beq .L79 + 1111 0010 C023 movs r3, #192 + 1112 0012 1B01 lsls r3, r3, #4 + 1113 0014 9842 cmp r0, r3 + 1114 0016 1FD0 beq .L80 + 1115 0018 8023 movs r3, #128 + 1116 001a DB00 lsls r3, r3, #3 + 1117 001c 9842 cmp r0, r3 + 1118 001e 11D0 beq .L86 + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1119 .loc 1 429 0 + 1120 0020 FFF7FEFF bl RCC_GetSystemClockFreq + 1121 .LVL99: + 1122 .LBB266: + 1123 .LBB267: + 1124 .LBB268: + 1125 .LBB269: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1126 .loc 2 1392 0 + 1127 0024 1149 ldr r1, .L87 + 1128 0026 CA68 ldr r2, [r1, #12] + 1129 .LBE269: + 1130 .LBE268: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1131 .loc 1 580 0 + 1132 0028 1209 lsrs r2, r2, #4 + 1133 002a 0F23 movs r3, #15 + 1134 002c 1340 ands r3, r2 + 1135 002e 104A ldr r2, .L87+4 + 1136 0030 D35C ldrb r3, [r2, r3] + 1137 0032 D840 lsrs r0, r0, r3 + 1138 .LVL100: + 1139 .LBE267: + 1140 .LBE266: + 1141 .LBB270: + ARM GAS /tmp/cc0YOhsX.s page 74 + + + 1142 .LBB271: + 1143 .LBB272: + 1144 .LBB273: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1145 .loc 2 1407 0 + 1146 0034 CA68 ldr r2, [r1, #12] + 1147 .LBE273: + 1148 .LBE272: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1149 .loc 1 591 0 + 1150 0036 120A lsrs r2, r2, #8 + 1151 0038 0723 movs r3, #7 + 1152 003a 1340 ands r3, r2 + 1153 003c 0D4A ldr r2, .L87+8 + 1154 003e D35C ldrb r3, [r2, r3] + 1155 0040 D840 lsrs r0, r0, r3 + 1156 .LVL101: + 1157 .LBE271: + 1158 .LBE270: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1159 .loc 1 430 0 + 1160 0042 01E0 b .L77 + 1161 .LVL102: + 1162 .L86: + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1163 .loc 1 410 0 + 1164 0044 FFF7FEFF bl RCC_GetSystemClockFreq + 1165 .LVL103: + 1166 .L77: + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1167 .loc 1 434 0 + 1168 @ sp needed + 1169 0048 10BD pop {r4, pc} + 1170 .LVL104: + 1171 .L79: + 1172 .LBB274: + 1173 .LBB275: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1174 .loc 2 834 0 + 1175 004a 084B ldr r3, .L87 + 1176 004c 1B68 ldr r3, [r3] + 1177 004e 0420 movs r0, #4 + 1178 0050 1840 ands r0, r3 + 1179 .LBE275: + 1180 .LBE274: + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1181 .loc 1 414 0 + 1182 0052 F9D0 beq .L77 + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1183 .loc 1 416 0 + 1184 0054 0848 ldr r0, .L87+12 + 1185 0056 F7E7 b .L77 + 1186 .L80: + 1187 .LBB276: + 1188 .LBB277: +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1189 .loc 2 1129 0 + ARM GAS /tmp/cc0YOhsX.s page 75 + + + 1190 0058 044B ldr r3, .L87 + 1191 005a 186D ldr r0, [r3, #80] + 1192 005c 8023 movs r3, #128 + 1193 005e 9B00 lsls r3, r3, #2 + 1194 0060 1840 ands r0, r3 + 1195 .LBE277: + 1196 .LBE276: + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1197 .loc 1 421 0 + 1198 0062 F1D0 beq .L77 + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1199 .loc 1 423 0 + 1200 0064 8020 movs r0, #128 + 1201 0066 0002 lsls r0, r0, #8 + 1202 .LVL105: + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1203 .loc 1 433 0 + 1204 0068 EEE7 b .L77 + 1205 .L88: + 1206 006a C046 .align 2 + 1207 .L87: + 1208 006c 00100240 .word 1073876992 + 1209 0070 00000000 .word AHBPrescTable + 1210 0074 00000000 .word APBPrescTable + 1211 0078 0024F400 .word 16000000 + 1212 .cfi_endproc + 1213 .LFE180: + 1215 .section .text.LL_RCC_GetLPTIMClockFreq,"ax",%progbits + 1216 .align 1 + 1217 .global LL_RCC_GetLPTIMClockFreq + 1218 .syntax unified + 1219 .code 16 + 1220 .thumb_func + 1221 .fpu softvfp + 1223 LL_RCC_GetLPTIMClockFreq: + 1224 .LFB181: + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1225 .loc 1 444 0 + 1226 .cfi_startproc + 1227 @ args = 0, pretend = 0, frame = 0 + 1228 @ frame_needed = 0, uses_anonymous_args = 0 + 1229 .LVL106: + 1230 0000 10B5 push {r4, lr} + 1231 .LCFI6: + 1232 .cfi_def_cfa_offset 8 + 1233 .cfi_offset 4, -8 + 1234 .cfi_offset 14, -4 + 1235 .LVL107: + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1236 .loc 1 450 0 + 1237 0002 C023 movs r3, #192 + 1238 0004 1B03 lsls r3, r3, #12 + 1239 0006 9842 cmp r0, r3 + 1240 0008 01D0 beq .L100 + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1241 .loc 1 445 0 + 1242 000a 0020 movs r0, #0 + ARM GAS /tmp/cc0YOhsX.s page 76 + + + 1243 .LVL108: + 1244 .L89: + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1245 .loc 1 484 0 + 1246 @ sp needed + 1247 000c 10BD pop {r4, pc} + 1248 .LVL109: + 1249 .L100: + 1250 .LBB278: + 1251 .LBB279: +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1252 .loc 2 1673 0 + 1253 000e 1C4B ldr r3, .L102 + 1254 0010 DB6C ldr r3, [r3, #76] + 1255 0012 1840 ands r0, r3 + 1256 .LVL110: + 1257 .LBE279: + 1258 .LBE278: + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1259 .loc 1 453 0 + 1260 0014 8023 movs r3, #128 + 1261 0016 1B03 lsls r3, r3, #12 + 1262 0018 9842 cmp r0, r3 + 1263 001a 20D0 beq .L92 + 1264 001c C023 movs r3, #192 + 1265 001e 1B03 lsls r3, r3, #12 + 1266 0020 9842 cmp r0, r3 + 1267 0022 23D0 beq .L93 + 1268 0024 8023 movs r3, #128 + 1269 0026 DB02 lsls r3, r3, #11 + 1270 0028 9842 cmp r0, r3 + 1271 002a 11D0 beq .L101 + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1272 .loc 1 478 0 + 1273 002c FFF7FEFF bl RCC_GetSystemClockFreq + 1274 .LVL111: + 1275 .LBB280: + 1276 .LBB281: + 1277 .LBB282: + 1278 .LBB283: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1279 .loc 2 1392 0 + 1280 0030 1349 ldr r1, .L102 + 1281 0032 CA68 ldr r2, [r1, #12] + 1282 .LBE283: + 1283 .LBE282: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1284 .loc 1 580 0 + 1285 0034 1209 lsrs r2, r2, #4 + 1286 0036 0F23 movs r3, #15 + 1287 0038 1340 ands r3, r2 + 1288 003a 124A ldr r2, .L102+4 + 1289 003c D35C ldrb r3, [r2, r3] + 1290 003e D840 lsrs r0, r0, r3 + 1291 .LVL112: + 1292 .LBE281: + 1293 .LBE280: + ARM GAS /tmp/cc0YOhsX.s page 77 + + + 1294 .LBB284: + 1295 .LBB285: + 1296 .LBB286: + 1297 .LBB287: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1298 .loc 2 1407 0 + 1299 0040 CA68 ldr r2, [r1, #12] + 1300 .LBE287: + 1301 .LBE286: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1302 .loc 1 591 0 + 1303 0042 120A lsrs r2, r2, #8 + 1304 0044 0723 movs r3, #7 + 1305 0046 1340 ands r3, r2 + 1306 0048 0F4A ldr r2, .L102+8 + 1307 004a D35C ldrb r3, [r2, r3] + 1308 004c D840 lsrs r0, r0, r3 + 1309 .LVL113: + 1310 .LBE285: + 1311 .LBE284: + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1312 .loc 1 479 0 + 1313 004e DDE7 b .L89 + 1314 .LVL114: + 1315 .L101: + 1316 .LBB288: + 1317 .LBB289: +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1318 .loc 2 1177 0 + 1319 0050 0B4B ldr r3, .L102 + 1320 0052 1B6D ldr r3, [r3, #80] + 1321 0054 0220 movs r0, #2 + 1322 0056 1840 ands r0, r3 + 1323 .LBE289: + 1324 .LBE288: + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1325 .loc 1 456 0 + 1326 0058 D8D0 beq .L89 + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1327 .loc 1 458 0 + 1328 005a 0C48 ldr r0, .L102+12 + 1329 005c D6E7 b .L89 + 1330 .L92: + 1331 .LBB290: + 1332 .LBB291: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1333 .loc 2 834 0 + 1334 005e 084B ldr r3, .L102 + 1335 0060 1B68 ldr r3, [r3] + 1336 0062 0420 movs r0, #4 + 1337 0064 1840 ands r0, r3 + 1338 .LBE291: + 1339 .LBE290: + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1340 .loc 1 463 0 + 1341 0066 D1D0 beq .L89 + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + ARM GAS /tmp/cc0YOhsX.s page 78 + + + 1342 .loc 1 465 0 + 1343 0068 0948 ldr r0, .L102+16 + 1344 006a CFE7 b .L89 + 1345 .L93: + 1346 .LBB292: + 1347 .LBB293: +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1348 .loc 2 1129 0 + 1349 006c 044B ldr r3, .L102 + 1350 006e 186D ldr r0, [r3, #80] + 1351 0070 8023 movs r3, #128 + 1352 0072 9B00 lsls r3, r3, #2 + 1353 0074 1840 ands r0, r3 + 1354 .LBE293: + 1355 .LBE292: + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1356 .loc 1 470 0 + 1357 0076 C9D0 beq .L89 + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1358 .loc 1 472 0 + 1359 0078 8020 movs r0, #128 + 1360 007a 0002 lsls r0, r0, #8 + 1361 .LVL115: + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1362 .loc 1 483 0 + 1363 007c C6E7 b .L89 + 1364 .L103: + 1365 007e C046 .align 2 + 1366 .L102: + 1367 0080 00100240 .word 1073876992 + 1368 0084 00000000 .word AHBPrescTable + 1369 0088 00000000 .word APBPrescTable + 1370 008c 88900000 .word 37000 + 1371 0090 0024F400 .word 16000000 + 1372 .cfi_endproc + 1373 .LFE181: + 1375 .section .text.RCC_GetHCLKClockFreq,"ax",%progbits + 1376 .align 1 + 1377 .global RCC_GetHCLKClockFreq + 1378 .syntax unified + 1379 .code 16 + 1380 .thumb_func + 1381 .fpu softvfp + 1383 RCC_GetHCLKClockFreq: + 1384 .LFB184: + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* HCLK clock frequency */ + 1385 .loc 1 578 0 + 1386 .cfi_startproc + 1387 @ args = 0, pretend = 0, frame = 0 + 1388 @ frame_needed = 0, uses_anonymous_args = 0 + 1389 @ link register save eliminated. + 1390 .LVL116: + 1391 .LBB294: + 1392 .LBB295: +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1393 .loc 2 1392 0 + 1394 0000 044B ldr r3, .L105 + ARM GAS /tmp/cc0YOhsX.s page 79 + + + 1395 0002 DA68 ldr r2, [r3, #12] + 1396 .LBE295: + 1397 .LBE294: + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1398 .loc 1 580 0 + 1399 0004 1209 lsrs r2, r2, #4 + 1400 0006 0F23 movs r3, #15 + 1401 0008 1340 ands r3, r2 + 1402 000a 034A ldr r2, .L105+4 + 1403 000c D35C ldrb r3, [r2, r3] + 1404 000e D840 lsrs r0, r0, r3 + 1405 .LVL117: + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1406 .loc 1 581 0 + 1407 @ sp needed + 1408 0010 7047 bx lr + 1409 .L106: + 1410 0012 C046 .align 2 + 1411 .L105: + 1412 0014 00100240 .word 1073876992 + 1413 0018 00000000 .word AHBPrescTable + 1414 .cfi_endproc + 1415 .LFE184: + 1417 .section .text.RCC_GetPCLK1ClockFreq,"ax",%progbits + 1418 .align 1 + 1419 .global RCC_GetPCLK1ClockFreq + 1420 .syntax unified + 1421 .code 16 + 1422 .thumb_func + 1423 .fpu softvfp + 1425 RCC_GetPCLK1ClockFreq: + 1426 .LFB185: + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 1427 .loc 1 589 0 + 1428 .cfi_startproc + 1429 @ args = 0, pretend = 0, frame = 0 + 1430 @ frame_needed = 0, uses_anonymous_args = 0 + 1431 @ link register save eliminated. + 1432 .LVL118: + 1433 .LBB296: + 1434 .LBB297: +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1435 .loc 2 1407 0 + 1436 0000 044B ldr r3, .L108 + 1437 0002 DA68 ldr r2, [r3, #12] + 1438 .LBE297: + 1439 .LBE296: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1440 .loc 1 591 0 + 1441 0004 120A lsrs r2, r2, #8 + 1442 0006 0723 movs r3, #7 + 1443 0008 1340 ands r3, r2 + 1444 000a 034A ldr r2, .L108+4 + 1445 000c D35C ldrb r3, [r2, r3] + 1446 000e D840 lsrs r0, r0, r3 + 1447 .LVL119: + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + ARM GAS /tmp/cc0YOhsX.s page 80 + + + 1448 .loc 1 592 0 + 1449 @ sp needed + 1450 0010 7047 bx lr + 1451 .L109: + 1452 0012 C046 .align 2 + 1453 .L108: + 1454 0014 00100240 .word 1073876992 + 1455 0018 00000000 .word APBPrescTable + 1456 .cfi_endproc + 1457 .LFE185: + 1459 .section .text.RCC_GetPCLK2ClockFreq,"ax",%progbits + 1460 .align 1 + 1461 .global RCC_GetPCLK2ClockFreq + 1462 .syntax unified + 1463 .code 16 + 1464 .thumb_func + 1465 .fpu softvfp + 1467 RCC_GetPCLK2ClockFreq: + 1468 .LFB186: + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** /* PCLK2 clock frequency */ + 1469 .loc 1 600 0 + 1470 .cfi_startproc + 1471 @ args = 0, pretend = 0, frame = 0 + 1472 @ frame_needed = 0, uses_anonymous_args = 0 + 1473 @ link register save eliminated. + 1474 .LVL120: + 1475 .LBB298: + 1476 .LBB299: +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1477 .loc 2 1422 0 + 1478 0000 044B ldr r3, .L111 + 1479 0002 DA68 ldr r2, [r3, #12] + 1480 .LBE299: + 1481 .LBE298: + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1482 .loc 1 602 0 + 1483 0004 D20A lsrs r2, r2, #11 + 1484 0006 0723 movs r3, #7 + 1485 0008 1340 ands r3, r2 + 1486 000a 034A ldr r2, .L111+4 + 1487 000c D35C ldrb r3, [r2, r3] + 1488 000e D840 lsrs r0, r0, r3 + 1489 .LVL121: + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** + 1490 .loc 1 603 0 + 1491 @ sp needed + 1492 0010 7047 bx lr + 1493 .L112: + 1494 0012 C046 .align 2 + 1495 .L111: + 1496 0014 00100240 .word 1073876992 + 1497 0018 00000000 .word APBPrescTable + 1498 .cfi_endproc + 1499 .LFE186: + 1501 .section .text.RCC_PLL_GetFreqDomain_SYS,"ax",%progbits + 1502 .align 1 + 1503 .global RCC_PLL_GetFreqDomain_SYS + ARM GAS /tmp/cc0YOhsX.s page 81 + + + 1504 .syntax unified + 1505 .code 16 + 1506 .thumb_func + 1507 .fpu softvfp + 1509 RCC_PLL_GetFreqDomain_SYS: + 1510 .LFB187: + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 1511 .loc 1 610 0 + 1512 .cfi_startproc + 1513 @ args = 0, pretend = 0, frame = 0 + 1514 @ frame_needed = 0, uses_anonymous_args = 0 + 1515 0000 10B5 push {r4, lr} + 1516 .LCFI7: + 1517 .cfi_def_cfa_offset 8 + 1518 .cfi_offset 4, -8 + 1519 .cfi_offset 14, -4 + 1520 .LVL122: + 1521 .LBB300: + 1522 .LBB301: +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1523 .loc 2 1878 0 + 1524 0002 0D4B ldr r3, .L117 + 1525 0004 DB68 ldr r3, [r3, #12] + 1526 0006 8022 movs r2, #128 + 1527 0008 5202 lsls r2, r2, #9 + 1528 000a 1340 ands r3, r2 + 1529 .LVL123: + 1530 .LBE301: + 1531 .LBE300: + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** { + 1532 .loc 1 618 0 + 1533 000c 9342 cmp r3, r2 + 1534 000e 01D0 beq .L116 + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1535 .loc 1 621 0 + 1536 0010 0A48 ldr r0, .L117+4 + 1537 0012 00E0 b .L115 + 1538 .L116: + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** break; + 1539 .loc 1 625 0 + 1540 0014 0A48 ldr r0, .L117+8 + 1541 .L115: + 1542 .LVL124: + 1543 .LBB302: + 1544 .LBB303: +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 1545 .loc 2 1897 0 + 1546 0016 0849 ldr r1, .L117 + 1547 0018 CA68 ldr r2, [r1, #12] + 1548 .LBE303: + 1549 .LBE302: + 1550 .loc 1 632 0 + 1551 001a 920C lsrs r2, r2, #18 + 1552 001c 0F23 movs r3, #15 + 1553 001e 1340 ands r3, r2 + 1554 0020 084A ldr r2, .L117+12 + 1555 0022 D35C ldrb r3, [r2, r3] + ARM GAS /tmp/cc0YOhsX.s page 82 + + + 1556 0024 5843 muls r0, r3 + 1557 .LVL125: + 1558 .LBB304: + 1559 .LBB305: + 1560 .loc 2 1910 0 + 1561 0026 CB68 ldr r3, [r1, #12] + 1562 .LBE305: + 1563 .LBE304: + 1564 .loc 1 632 0 + 1565 0028 9B0D lsrs r3, r3, #22 + 1566 002a 0321 movs r1, #3 + 1567 002c 1940 ands r1, r3 + 1568 002e 0131 adds r1, r1, #1 + 1569 0030 FFF7FEFF bl __aeabi_uidiv + 1570 .LVL126: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c **** } + 1571 .loc 1 633 0 + 1572 @ sp needed + 1573 0034 10BD pop {r4, pc} + 1574 .L118: + 1575 0036 C046 .align 2 + 1576 .L117: + 1577 0038 00100240 .word 1073876992 + 1578 003c 0024F400 .word 16000000 + 1579 0040 00127A00 .word 8000000 + 1580 0044 00000000 .word PLLMulTable + 1581 .cfi_endproc + 1582 .LFE187: + 1584 .text + 1585 .Letext0: + 1586 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1587 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1588 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1589 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1590 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1591 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 1592 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 1593 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1594 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc0YOhsX.s page 83 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_rcc.c + /tmp/cc0YOhsX.s:16 .text.LL_RCC_DeInit:0000000000000000 $t + /tmp/cc0YOhsX.s:23 .text.LL_RCC_DeInit:0000000000000000 LL_RCC_DeInit + /tmp/cc0YOhsX.s:161 .text.LL_RCC_DeInit:000000000000006c $d + /tmp/cc0YOhsX.s:173 .text.LL_RCC_GetUSBClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:180 .text.LL_RCC_GetUSBClockFreq:0000000000000000 LL_RCC_GetUSBClockFreq + /tmp/cc0YOhsX.s:302 .text.LL_RCC_GetUSBClockFreq:000000000000005c $d + /tmp/cc0YOhsX.s:311 .text.RCC_GetSystemClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:318 .text.RCC_GetSystemClockFreq:0000000000000000 RCC_GetSystemClockFreq + /tmp/cc0YOhsX.s:471 .text.RCC_GetSystemClockFreq:0000000000000080 $d + /tmp/cc0YOhsX.s:479 .text.LL_RCC_GetSystemClocksFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:486 .text.LL_RCC_GetSystemClocksFreq:0000000000000000 LL_RCC_GetSystemClocksFreq + /tmp/cc0YOhsX.s:575 .text.LL_RCC_GetSystemClocksFreq:000000000000003c $d + /tmp/cc0YOhsX.s:582 .text.LL_RCC_GetUSARTClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:589 .text.LL_RCC_GetUSARTClockFreq:0000000000000000 LL_RCC_GetUSARTClockFreq + /tmp/cc0YOhsX.s:835 .text.LL_RCC_GetUSARTClockFreq:00000000000000d8 $d + /tmp/cc0YOhsX.s:849 .text.LL_RCC_GetI2CClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:856 .text.LL_RCC_GetI2CClockFreq:0000000000000000 LL_RCC_GetI2CClockFreq + /tmp/cc0YOhsX.s:1065 .text.LL_RCC_GetI2CClockFreq:00000000000000b8 $d + /tmp/cc0YOhsX.s:1077 .text.LL_RCC_GetLPUARTClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:1084 .text.LL_RCC_GetLPUARTClockFreq:0000000000000000 LL_RCC_GetLPUARTClockFreq + /tmp/cc0YOhsX.s:1208 .text.LL_RCC_GetLPUARTClockFreq:000000000000006c $d + /tmp/cc0YOhsX.s:1216 .text.LL_RCC_GetLPTIMClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:1223 .text.LL_RCC_GetLPTIMClockFreq:0000000000000000 LL_RCC_GetLPTIMClockFreq + /tmp/cc0YOhsX.s:1367 .text.LL_RCC_GetLPTIMClockFreq:0000000000000080 $d + /tmp/cc0YOhsX.s:1376 .text.RCC_GetHCLKClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:1383 .text.RCC_GetHCLKClockFreq:0000000000000000 RCC_GetHCLKClockFreq + /tmp/cc0YOhsX.s:1412 .text.RCC_GetHCLKClockFreq:0000000000000014 $d + /tmp/cc0YOhsX.s:1418 .text.RCC_GetPCLK1ClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:1425 .text.RCC_GetPCLK1ClockFreq:0000000000000000 RCC_GetPCLK1ClockFreq + /tmp/cc0YOhsX.s:1454 .text.RCC_GetPCLK1ClockFreq:0000000000000014 $d + /tmp/cc0YOhsX.s:1460 .text.RCC_GetPCLK2ClockFreq:0000000000000000 $t + /tmp/cc0YOhsX.s:1467 .text.RCC_GetPCLK2ClockFreq:0000000000000000 RCC_GetPCLK2ClockFreq + /tmp/cc0YOhsX.s:1496 .text.RCC_GetPCLK2ClockFreq:0000000000000014 $d + /tmp/cc0YOhsX.s:1502 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 $t + /tmp/cc0YOhsX.s:1509 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 RCC_PLL_GetFreqDomain_SYS + /tmp/cc0YOhsX.s:1577 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000038 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +PLLMulTable +AHBPrescTable +APBPrescTable diff --git a/build/stm32l0xx_ll_rng.d b/build/stm32l0xx_ll_rng.d new file mode 100644 index 0000000..562d99d --- /dev/null +++ b/build/stm32l0xx_ll_rng.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_rng.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_rng.lst b/build/stm32l0xx_ll_rng.lst new file mode 100644 index 0000000..ffe6be0 --- /dev/null +++ b/build/stm32l0xx_ll_rng.lst @@ -0,0 +1,549 @@ +ARM GAS /tmp/ccdITogO.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_rng.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_RNG_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_RNG_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_RNG_DeInit: + 24 .LFB81: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @file stm32l0xx_ll_rng.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @brief RNG LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** ****************************************************************************** + ARM GAS /tmp/ccdITogO.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #include "stm32l0xx_ll_rng.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** #if defined (RNG) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** @addtogroup RNG_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Private macros ------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Private function prototypes -----------------------------------------------*/ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Exported functions --------------------------------------------------------*/ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** @addtogroup RNG_LL_Exported_Functions + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @{ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** @addtogroup RNG_LL_EF_Init + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @{ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @brief De-initialize RNG registers (Registers restored to their default values). + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @param RNGx RNG Instance + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * @retval An ErrorStatus enumeration value: + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * - SUCCESS: RNG registers are de-initialized + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** * - ERROR: not applicable + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** { + 26 .loc 1 80 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB6: + 33 .LBB7: + 34 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/ccdITogO.s page 3 + + + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + ARM GAS /tmp/ccdITogO.s page 4 + + + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + ARM GAS /tmp/ccdITogO.s page 5 + + + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + ARM GAS /tmp/ccdITogO.s page 6 + + + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccdITogO.s page 7 + + + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + ARM GAS /tmp/ccdITogO.s page 8 + + + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 35 .loc 2 319 0 + 36 0000 054B ldr r3, .L2 + 37 0002 196A ldr r1, [r3, #32] + 38 0004 8022 movs r2, #128 + 39 0006 5203 lsls r2, r2, #13 + 40 0008 0A43 orrs r2, r1 + 41 000a 1A62 str r2, [r3, #32] + 42 .LVL1: + 43 .LBE7: + 44 .LBE6: + 45 .LBB8: + 46 .LBB9: + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + ARM GAS /tmp/ccdITogO.s page 9 + + + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 47 .loc 2 344 0 + 48 000c 1A6A ldr r2, [r3, #32] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 1A62 str r2, [r3, #32] + 52 .LVL2: + 53 .LBE9: + 54 .LBE8: + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Check the parameters */ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Enable RNG reset state */ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** /* Release RNG from reset state */ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** return (SUCCESS); + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c **** } + 55 .loc 1 91 0 + 56 0014 0120 movs r0, #1 + 57 .LVL3: + 58 @ sp needed + 59 0016 7047 bx lr + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0018 00100240 .word 1073876992 + 64 001c FFFFEFFF .word -1048577 + 65 .cfi_endproc + 66 .LFE81: + 68 .text + 69 .Letext0: + 70 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 71 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 72 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 73 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 74 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 75 .file 8 "/usr/arm-none-eabi/include/sys/lock.h" + 76 .file 9 "/usr/arm-none-eabi/include/sys/_types.h" + 77 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 78 .file 11 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccdITogO.s page 10 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_rng.c + /tmp/ccdITogO.s:16 .text.LL_RNG_DeInit:0000000000000000 $t + /tmp/ccdITogO.s:23 .text.LL_RNG_DeInit:0000000000000000 LL_RNG_DeInit + /tmp/ccdITogO.s:63 .text.LL_RNG_DeInit:0000000000000018 $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_rtc.d b/build/stm32l0xx_ll_rtc.d new file mode 100644 index 0000000..2b20660 --- /dev/null +++ b/build/stm32l0xx_ll_rtc.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_rtc.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h: diff --git a/build/stm32l0xx_ll_rtc.lst b/build/stm32l0xx_ll_rtc.lst new file mode 100644 index 0000000..7f048eb --- /dev/null +++ b/build/stm32l0xx_ll_rtc.lst @@ -0,0 +1,6985 @@ +ARM GAS /tmp/ccnIlCuV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_rtc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_RTC_StructInit,"ax",%progbits + 16 .align 1 + 17 .global LL_RTC_StructInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_RTC_StructInit: + 24 .LFB260: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @file stm32l0xx_ll_rtc.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief RTC LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ****************************************************************************** + ARM GAS /tmp/ccnIlCuV.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #include "stm32l0xx_ll_rtc.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #include "stm32l0xx_ll_cortex.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #ifdef USE_FULL_ASSERT + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #include "stm32_assert.h" + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #else + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define assert_param(expr) ((void)0U) + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #endif + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup STM32L0xx_LL_Driver + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #if defined(RTC) + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup RTC_LL + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Private types -------------------------------------------------------------*/ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Private constants ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup RTC_LL_Private_Constants + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Default values used for prescaler */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Values used for timeout */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @} + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Private macros ------------------------------------------------------------*/ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup RTC_LL_Private_Macros + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU) + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU) + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + ARM GAS /tmp/ccnIlCuV.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_MAY) \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_JULY) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY) + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY) + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @} + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Private function prototypes -----------------------------------------------*/ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Exported functions --------------------------------------------------------*/ + ARM GAS /tmp/ccnIlCuV.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup RTC_LL_Exported_Functions + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** @addtogroup RTC_LL_EF_Init + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @{ + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief De-Initializes the RTC registers to their default reset values. + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note This function doesn't reset the RTC Clock source and RTC Backup Data + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * registers. + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC registers are de-initialized + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC registers are not de-initialized + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameter */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set Initialization mode */ + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_EnterInitMode(RTCx) != ERROR) + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset TR, DR and CR registers */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, TR, 0x00000000U); + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #if defined(RTC_WAKEUP_SUPPORT) + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #endif /* RTC_WAKEUP_SUPPORT */ + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset All CR bits except CR[2:0] */ + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #if defined(RTC_WAKEUP_SUPPORT) + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #else + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, CR, 0x00000000U); + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #endif /* RTC_WAKEUP_SUPPORT */ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset ISR register and exit initialization mode */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset Tamper and alternate functions configuration register */ + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U); + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset Option register */ + ARM GAS /tmp/ccnIlCuV.s page 5 + + + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, OR, 0x00000000U); + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Wait till the RTC RSF flag is set */ + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = LL_RTC_WaitForSynchro(RTCx); + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return status; + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Initializes the RTC registers according to the specified parameters + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * in RTC_InitStruct. + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * the configuration information for the RTC peripheral. + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The RTC Prescaler register is write protected and can be written in + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * initialization mode only. + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC registers are initialized + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC registers are not initialized + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameters */ + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set Initialization mode */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_EnterInitMode(RTCx) != ERROR) + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set Hour Format */ + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Configure Synchronous and Asynchronous prescaler factor */ + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Exit Initialization mode */ + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableInitMode(RTCx); + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = SUCCESS; + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return status; + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + ARM GAS /tmp/ccnIlCuV.s page 6 + + + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval None + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 26 .loc 1 269 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set RTC_InitStruct fields to default values */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + 32 .loc 1 271 0 + 33 0000 0023 movs r3, #0 + 34 0002 0360 str r3, [r0] + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + 35 .loc 1 272 0 + 36 0004 7F33 adds r3, r3, #127 + 37 0006 4360 str r3, [r0, #4] + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; + 38 .loc 1 273 0 + 39 0008 8033 adds r3, r3, #128 + 40 000a 8360 str r3, [r0, #8] + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 41 .loc 1 274 0 + 42 @ sp needed + 43 000c 7047 bx lr + 44 .cfi_endproc + 45 .LFE260: + 47 .section .text.LL_RTC_TIME_StructInit,"ax",%progbits + 48 .align 1 + 49 .global LL_RTC_TIME_StructInit + 50 .syntax unified + 51 .code 16 + 52 .thumb_func + 53 .fpu softvfp + 55 LL_RTC_TIME_StructInit: + 56 .LFB262: + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set the RTC current time. + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_Format This parameter can be one of the following values: + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BIN + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BCD + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * the time configuration information for the RTC. + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC Time register is configured + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC Time register is not configured + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeSt + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + ARM GAS /tmp/ccnIlCuV.s page 7 + + + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameters */ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format == LL_RTC_FORMAT_BIN) + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->TimeFormat = 0x00U; + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->TimeFormat = 0x00U; + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set Initialization mode */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_EnterInitMode(RTCx) != ERROR) + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the input parameters format */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct- + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Exit Initialization mode */ + ARM GAS /tmp/ccnIlCuV.s page 8 + + + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableInitMode(RTC); + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = LL_RTC_WaitForSynchro(RTCx); + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = SUCCESS; + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return status; + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval None + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 57 .loc 1 371 0 + 58 .cfi_startproc + 59 @ args = 0, pretend = 0, frame = 0 + 60 @ frame_needed = 0, uses_anonymous_args = 0 + 61 @ link register save eliminated. + 62 .LVL1: + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Time = 00h:00min:00sec */ + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + 63 .loc 1 373 0 + 64 0000 0023 movs r3, #0 + 65 0002 0360 str r3, [r0] + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->Hours = 0U; + 66 .loc 1 374 0 + 67 0004 0371 strb r3, [r0, #4] + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->Minutes = 0U; + 68 .loc 1 375 0 + 69 0006 4371 strb r3, [r0, #5] + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->Seconds = 0U; + 70 .loc 1 376 0 + 71 0008 8371 strb r3, [r0, #6] + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 72 .loc 1 377 0 + 73 @ sp needed + 74 000a 7047 bx lr + 75 .cfi_endproc + 76 .LFE262: + 78 .section .text.LL_RTC_DATE_StructInit,"ax",%progbits + 79 .align 1 + 80 .global LL_RTC_DATE_StructInit + 81 .syntax unified + 82 .code 16 + 83 .thumb_func + ARM GAS /tmp/ccnIlCuV.s page 9 + + + 84 .fpu softvfp + 86 LL_RTC_DATE_StructInit: + 87 .LFB264: + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set the RTC current date. + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_Format This parameter can be one of the following values: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BIN + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BCD + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * the date configuration information for the RTC. + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC Day register is configured + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC Day register is not configured + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateSt + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameters */ + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format == LL_RTC_FORMAT_BIN) + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set Initialization mode */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_EnterInitMode(RTCx) != ERROR) + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the input parameters format */ + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Da + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD( + ARM GAS /tmp/ccnIlCuV.s page 10 + + + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Exit Initialization mode */ + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableInitMode(RTC); + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = LL_RTC_WaitForSynchro(RTCx); + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = SUCCESS; + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return status; + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00 + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval None + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 88 .loc 1 459 0 + 89 .cfi_startproc + 90 @ args = 0, pretend = 0, frame = 0 + 91 @ frame_needed = 0, uses_anonymous_args = 0 + 92 @ link register save eliminated. + 93 .LVL2: + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Monday, January 01 xx00 */ + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + 94 .loc 1 461 0 + 95 0000 0123 movs r3, #1 + 96 0002 0370 strb r3, [r0] + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_DateStruct->Day = 1U; + 97 .loc 1 462 0 + 98 0004 8370 strb r3, [r0, #2] + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + 99 .loc 1 463 0 + 100 0006 4370 strb r3, [r0, #1] + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_DateStruct->Year = 0U; + 101 .loc 1 464 0 + 102 0008 0023 movs r3, #0 + 103 000a C370 strb r3, [r0, #3] + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 104 .loc 1 465 0 + 105 @ sp needed + 106 000c 7047 bx lr + 107 .cfi_endproc + 108 .LFE264: + 110 .global __aeabi_uidiv + 111 .global __aeabi_uidivmod + ARM GAS /tmp/ccnIlCuV.s page 11 + + + 112 .section .text.LL_RTC_ALMA_Init,"ax",%progbits + 113 .align 1 + 114 .global LL_RTC_ALMA_Init + 115 .syntax unified + 116 .code 16 + 117 .thumb_func + 118 .fpu softvfp + 120 LL_RTC_ALMA_Init: + 121 .LFB265: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set the RTC Alarm A. + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The Alarm register can only be written when the corresponding Alarm + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * is disabled (Use @ref LL_RTC_ALMA_Disable function). + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_Format This parameter can be one of the following values: + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BIN + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BCD + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * contains the alarm configuration parameters. + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: ALARMA registers are configured + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: ALARMA registers are not configured + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_Alarm + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 122 .loc 1 482 0 + 123 .cfi_startproc + 124 @ args = 0, pretend = 0, frame = 0 + 125 @ frame_needed = 0, uses_anonymous_args = 0 + 126 .LVL3: + 127 0000 F0B5 push {r4, r5, r6, r7, lr} + 128 .LCFI0: + 129 .cfi_def_cfa_offset 20 + 130 .cfi_offset 4, -20 + 131 .cfi_offset 5, -16 + 132 .cfi_offset 6, -12 + 133 .cfi_offset 7, -8 + 134 .cfi_offset 14, -4 + 135 0002 D646 mov lr, r10 + 136 0004 4F46 mov r7, r9 + 137 0006 4646 mov r6, r8 + 138 0008 C0B5 push {r6, r7, lr} + 139 .LCFI1: + 140 .cfi_def_cfa_offset 32 + 141 .cfi_offset 8, -32 + 142 .cfi_offset 9, -28 + 143 .cfi_offset 10, -24 + 144 000a 0400 movs r4, r0 + 145 000c 0E00 movs r6, r1 + 146 000e 1500 movs r5, r2 + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameters */ + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + ARM GAS /tmp/ccnIlCuV.s page 12 + + + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format == LL_RTC_FORMAT_BIN) + 147 .loc 1 489 0 + 148 0010 0029 cmp r1, #0 + 149 0012 19D1 bne .L5 + 150 .LVL4: + 151 .LBB120: + 152 .LBB121: + 153 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @file stm32l0xx_ll_rtc.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Header file of RTC LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #ifndef __STM32L0xx_LL_RTC_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __STM32L0xx_LL_RTC_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + ARM GAS /tmp/ccnIlCuV.s page 13 + + + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL RTC + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_Private_Constants RTC Private Constants + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Masks Definition */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Write protection defines */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Defines used for the bit position in the register and perform offsets */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_HT (uint32_t)20U + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_HU (uint32_t)16U + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_MT (uint32_t)12U + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_MU (uint32_t)8U + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_ST (uint32_t)4U + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TR_SU (uint32_t)0U + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_YT (uint32_t)20U + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_YU (uint32_t)16U + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_MT (uint32_t)12U + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_MU (uint32_t)8U + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_DT (uint32_t)4U + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_DU (uint32_t)0U + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_DR_WDU (uint32_t)13U + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_DT (uint32_t)28U + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_DU (uint32_t)24U + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_HT (uint32_t)20U + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_HU (uint32_t)16U + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_MT (uint32_t)12U + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_MU (uint32_t)8U + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_SU (uint32_t)0U + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_ST (uint32_t)4U + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_DT (uint32_t)28U + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_DU (uint32_t)24U + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_HT (uint32_t)20U + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_HU (uint32_t)16U + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_MT (uint32_t)12U + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_MU (uint32_t)8U + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_SU (uint32_t)0U + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_ST (uint32_t)4U + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_PRER_PREDIV_A (uint32_t)16U + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMA_MASKSS (uint32_t)24U + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_ALMB_MASKSS (uint32_t)24U + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TS_HU (uint32_t)16U + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TS_MNU (uint32_t)8U + ARM GAS /tmp/ccnIlCuV.s page 14 + + + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TS_WDU (uint32_t)13U + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_POSITION_TS_MU (uint32_t)8U + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Defines used to combine date & time */ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_OFFSET_WEEKDAY (uint32_t)24U + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_OFFSET_DAY (uint32_t)16U + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_OFFSET_MONTH (uint32_t)8U + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_OFFSET_HOUR (uint32_t)16U + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define RTC_OFFSET_MINUTE (uint32_t)8U + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Private macros ------------------------------------------------------------*/ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(USE_FULL_LL_DRIVER) + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_Private_Macros RTC Private Macros + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Exported types ------------------------------------------------------------*/ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(USE_FULL_LL_DRIVER) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief RTC Init structures definition + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** typedef struct + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** @ref LL_RTC_SetHourFormat(). */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0x00 and Max_Data + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** @ref LL_RTC_SetAsynchPrescaler(). */ + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0x00 and Max_Data + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** @ref LL_RTC_SetSynchPrescaler(). */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } LL_RTC_InitTypeDef; + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief RTC Time structure definition + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + ARM GAS /tmp/ccnIlCuV.s page 15 + + + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** typedef struct + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Hours; /*!< Specifies the RTC Time Hours. + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0 and Max_Data = 12 + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0 and Max_Data = 23 + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_ + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0 and Max_Data = 59 + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_ + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0 and Max_Data = 59 + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } LL_RTC_TimeTypeDef; + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief RTC Date structure definition + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** typedef struct + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_RTC + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Month; /*!< Specifies the RTC Date Month. + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_MONTH + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_RTC + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Day; /*!< Specifies the RTC Date Day. + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 1 and Max_Data = 31 + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_RTC + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t Year; /*!< Specifies the RTC Date Year. + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter must be a number between Min_Data = 0 and Max_Data = 99 + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary function @ref LL_RTC + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } LL_RTC_DateTypeDef; + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief RTC Alarm structure definition + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** typedef struct + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + ARM GAS /tmp/ccnIlCuV.s page 16 + + + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary functio + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** or @ref LL_RTC_ALMB_SetMask() for ALARM B + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_ + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary functio + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RT + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** If AlarmDateWeekDaySel set to day, this parameter must be a + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary functio + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** If AlarmDateWeekDaySel set to Weekday, this parameter can be + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** This feature can be modified afterwards using unitary functio + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } LL_RTC_AlarmTypeDef; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* USE_FULL_LL_DRIVER */ + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Exported constants --------------------------------------------------------*/ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(USE_FULL_LL_DRIVER) + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_FORMAT FORMAT + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U) /*!< Binary data format */ + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U) /*!< BCD data format */ + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */ + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + ARM GAS /tmp/ccnIlCuV.s page 17 + + + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm B Date is selected */ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* USE_FULL_LL_DRIVER */ + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Flags defines which can be used with LL_RTC_ReadReg function + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_TSF RTC_ISR_TSF + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_WUTF RTC_ISR_WUTF + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_INITF RTC_ISR_INITF + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_RSF RTC_ISR_RSF + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_INITS RTC_ISR_INITS + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_SHPF RTC_ISR_SHPF + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_IT IT Defines + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CR_TSIE RTC_CR_TSIE + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CR_WUTIE RTC_CR_WUTIE + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */ + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */ + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */ + ARM GAS /tmp/ccnIlCuV.s page 18 + + + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_MONTH MONTH + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */ + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */ + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */ + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */ + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */ + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */ + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */ + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */ + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U /*!< 24 hour/day format */ + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U) /*!< Output disabled */ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U /*!< RTC_ALARM, when mapped on PC + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + ARM GAS /tmp/ccnIlCuV.s page 19 + + + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/ + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/W + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U /*!< AM or 24-hour format */ + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PRED + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Ala + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alar + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alar + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | R + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm B + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Ala + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alar + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alar + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | R + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + ARM GAS /tmp/ccnIlCuV.s page 20 + + + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U /*!< RTC_TS input rising edge gene + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge gen + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER TAMPER + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigg + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigg + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigg + ARM GAS /tmp/ccnIlCuV.s page 21 + + + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not era + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not era + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not era + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPPRCH) + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPPRCH */ + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPFLT) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPFLT */ + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPFREQ) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U) /*!< Ea + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Eac + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Eac + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Eac + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Eac + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Eac + ARM GAS /tmp/ccnIlCuV.s page 22 + + + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Eac + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ /*!< Eac + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPFREQ */ + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (i + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (i + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (i + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U) /*!< RTC/16 clock + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock i + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock i + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock i + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usua + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usua + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_BACKUP_SUPPORT) + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_BKP BACKUP + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_BKP_DR0 ((uint32_t)0x00000000U) + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_BKP_DR1 ((uint32_t)0x00000001U) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_BKP_DR2 ((uint32_t)0x00000002U) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_BKP_DR3 ((uint32_t)0x00000003U) + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_BKP_DR4 ((uint32_t)0x00000004U) + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_BACKUP_SUPPORT */ + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U /*!< Calibration output disa + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 5 + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + ARM GAS /tmp/ccnIlCuV.s page 23 + + + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */ + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effective + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U /*!< Use a 32-second calibration c + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration c + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cy + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Exported macro ------------------------------------------------------------*/ + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Write a value in RTC register + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __INSTANCE__ RTC Instance + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __REG__ Register to be written + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __VALUE__ Value to be written in the register + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Read a value in RTC register + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __INSTANCE__ RTC Instance + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __REG__ Register to be read + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Register value + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EM_Convert Convert helper Macros + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + ARM GAS /tmp/ccnIlCuV.s page 24 + + + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __VALUE__ Byte to be converted + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Converted byte + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __VALUE__ BCD value to be converted + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Converted byte + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> ( + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EM_Date Date helper Macros + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve weekday. + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve Year in BCD format + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Year in BCD format (0x00 . . . 0x99) + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve Month in BCD format + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JANUARY + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_FEBRUARY + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MARCH + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_APRIL + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MAY + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JUNE + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JULY + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_AUGUST + ARM GAS /tmp/ccnIlCuV.s page 25 + + + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_SEPTEMBER + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_OCTOBER + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_NOVEMBER + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_DECEMBER + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve Day in BCD format + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Day in BCD format (0x01 . . . 0x31) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EM_Time Time helper Macros + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve hour in BCD format + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve minute in BCD format + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Minutes in BCD format (0x00. . .0x59) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Helper macro to retrieve second in BCD format + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Seconds in format (0x00. . .0x59) + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Exported functions --------------------------------------------------------*/ + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Configuration Configuration + ARM GAS /tmp/ccnIlCuV.s page 26 + + + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Hours format (24 hour/day or AM/PM hour format) + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR FMT LL_RTC_SetHourFormat + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param HourFormat This parameter can be one of the following values: + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_HOURFORMAT_24HOUR + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_HOURFORMAT_AMPM + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Hours format (24 hour/day or AM/PM hour format) + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR FMT LL_RTC_GetHourFormat + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_HOURFORMAT_24HOUR + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_HOURFORMAT_AMPM + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); + 154 .loc 2 820 0 + 155 0014 8368 ldr r3, [r0, #8] + 156 .LVL5: + 157 .LBE121: + 158 .LBE120: + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 159 .loc 1 491 0 + 160 0016 5B06 lsls r3, r3, #25 + 161 0018 01D4 bmi .L7 + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + 162 .loc 1 498 0 + 163 001a 0023 movs r3, #0 + 164 001c 1360 str r3, [r2] + 165 .L7: + 166 .LVL6: + 167 .LBB122: + 168 .LBB123: + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + ARM GAS /tmp/ccnIlCuV.s page 27 + + + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Select the flag to be routed to RTC_ALARM output + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param AlarmOutput This parameter can be one of the following values: + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_DISABLE + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_ALMA + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_ALMB + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_WAKEUP + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get the flag to be routed to RTC_ALARM output + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_DISABLE + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_ALMA + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_ALMB + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARMOUT_WAKEUP + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Used only when RTC_ALARM is mapped on PC13 + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Output This parameter can be one of the following values: + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note used only when RTC_ALARM is mapped on PC13 + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + ARM GAS /tmp/ccnIlCuV.s page 28 + + + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable initialization mode + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * and prescaler register (RTC_PRER). + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * Counters are stopped and start counting from the new value when INIT is reset. + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR INIT LL_RTC_EnableInitMode + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Set the Initialization mode */ + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, RTC_INIT_MASK); + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable initialization mode (Free running mode) + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR INIT LL_RTC_DisableInitMode + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Exit Initialization mode */ + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR POL LL_RTC_SetOutputPolarity + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Polarity This parameter can be one of the following values: + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Output polarity + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR POL LL_RTC_GetOutputPolarity + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + ARM GAS /tmp/ccnIlCuV.s page 29 + + + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Bypass the shadow registers + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Bypass the shadow registers + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Check if Shadow registers bypass is enabled or not. + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)); + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR REFCKON LL_RTC_EnableRefClock + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_REFCKON); + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR REFCKON LL_RTC_DisableRefClock + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 30 + + + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Asynchronous prescaler factor +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A); +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Synchronous prescaler factor +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Asynchronous prescaler factor +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data = 0 and Max_Data = 0x7F +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A); +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Synchronous prescaler factor +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable the write protection for RTC registers. +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll WPR KEY LL_RTC_EnableWriteProtection +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 31 + + +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable the write protection for RTC registers. +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll WPR KEY LL_RTC_DisableWriteProtection +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + 169 .loc 2 1064 0 + 170 001e CA23 movs r3, #202 + 171 0020 6362 str r3, [r4, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 172 .loc 2 1065 0 + 173 0022 773B subs r3, r3, #119 + 174 0024 6362 str r3, [r4, #36] + 175 .LVL7: + 176 .LBE123: + 177 .LBE122: + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + ARM GAS /tmp/ccnIlCuV.s page 32 + + + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Select weekday selection */ + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + 178 .loc 1 543 0 + 179 0026 EB68 ldr r3, [r5, #12] + 180 0028 002B cmp r3, #0 + 181 002a 28D1 bne .L9 + 182 .LVL8: + 183 .LBB124: + 184 .LBB125: +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable RTC_OUT remap +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll OR OUT_RMP LL_RTC_EnableOutRemap +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx) +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->OR, RTC_OR_OUT_RMP); +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable RTC_OUT remap +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll OR OUT_RMP LL_RTC_DisableOutRemap +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP); +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Time Time +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set time format (AM/24-hour or PM notation) +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR PM LL_RTC_TIME_SetFormat +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param TimeFormat This parameter can be one of the following values: + ARM GAS /tmp/ccnIlCuV.s page 33 + + +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_PM +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get time format (AM or PM notation) +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR PM LL_RTC_TIME_GetFormat +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_PM +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Hours in BCD format +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD for +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR HT LL_RTC_TIME_SetHour\n +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR HU LL_RTC_TIME_SetHour +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_ +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Hours in BCD format +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * Binary format +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR HT LL_RTC_TIME_GetHour\n +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR HU LL_RTC_TIME_GetHour +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x2 +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 34 + + +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Minutes in BCD format +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNU LL_RTC_TIME_SetMinute +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Minutes in BCD format +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * to Binary format +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNU LL_RTC_TIME_GetMinute +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> R +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Seconds in BCD format +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR ST LL_RTC_TIME_SetSecond\n +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR SU LL_RTC_TIME_SetSecond +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) + ARM GAS /tmp/ccnIlCuV.s page 35 + + +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Seconds in BCD format +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * to Binary format +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR ST LL_RTC_TIME_GetSecond\n +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR SU LL_RTC_TIME_GetSecond +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set time (hour, minute and second) in BCD format +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note TimeFormat and Hours should follow the same format +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR PM LL_RTC_TIME_Config\n +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR HT LL_RTC_TIME_Config\n +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR HU LL_RTC_TIME_Config\n +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNT LL_RTC_TIME_Config\n +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNU LL_RTC_TIME_Config\n +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR ST LL_RTC_TIME_Config\n +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR SU LL_RTC_TIME_Config +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Format12_24 This parameter can be one of the following values: +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIME_FORMAT_PM +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, ui +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = Format12_24 +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_ +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_ +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | R +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + ARM GAS /tmp/ccnIlCuV.s page 36 + + +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get time (hour, minute and second) in BCD format +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * are available to get independently each parameter. +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TR HT LL_RTC_TIME_Get\n +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR HU LL_RTC_TIME_Get\n +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNT LL_RTC_TIME_Get\n +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR MNU LL_RTC_TIME_Get\n +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR ST LL_RTC_TIME_Get\n +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TR SU LL_RTC_TIME_Get +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) < +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Memorize whether the daylight saving time change has been performed +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BCK LL_RTC_TIME_EnableDayLightStore +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_BCK); +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable memorization whether the daylight saving time change has been performed. +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BCK LL_RTC_TIME_DisableDayLightStore +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_BCK); +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Check if RTC Day Light Saving stored operation has been enabled or not +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR BCK LL_RTC_TIME_IsDayLightStoreEnabled +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK)); +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + ARM GAS /tmp/ccnIlCuV.s page 37 + + +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Subtract 1 hour (winter time change) +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR SUB1H LL_RTC_TIME_DecHour +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_SUB1H); +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Add 1 hour (summer time change) +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR ADD1H LL_RTC_TIME_IncHour +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_ADD1H); +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Sub second value in the synchronous prescaler counter. +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * SubSeconds value in second fraction ratio with time unit following +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * generic formula: +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1 +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * This conversion can be performed only if no shift operation is pending +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (ie. SHFP=0) when PREDIV_S >= SS. +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Sub second value (number between 0 and 65535) +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Synchronize to a remote clock with a high degree of precision. +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note This operation effectively subtracts from (delays) or advance the clock of a fraction o +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note When REFCKON is set, firmware must not write to Shift control register. +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * SHIFTR SUBFS LL_RTC_TIME_Synchronize +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param ShiftSecond This parameter can be one of the following values: +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_SHIFT_SECOND_DELAY +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + ARM GAS /tmp/ccnIlCuV.s page 38 + + +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Frac +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Date Date +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Year in BCD format +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD for +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR YT LL_RTC_DATE_SetYear\n +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YU LL_RTC_DATE_SetYear +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Year Value between Min_Data=0x00 and Max_Data=0x99 +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Year in BCD format +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary for +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR YT LL_RTC_DATE_GetYear\n +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YU LL_RTC_DATE_GetYear +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x99 +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Week day +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param WeekDay This parameter can be one of the following values: +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY + ARM GAS /tmp/ccnIlCuV.s page 39 + + +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU); +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Week day +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU); +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Month in BCD format +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD fo +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR MT LL_RTC_DATE_SetMonth\n +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MU LL_RTC_DATE_SetMonth +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Month This parameter can be one of the following values: +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JANUARY +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_FEBRUARY +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MARCH +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_APRIL +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MAY +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JUNE +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JULY +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_AUGUST +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_SEPTEMBER +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_OCTOBER +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_NOVEMBER +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_DECEMBER +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_ +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Month in BCD format + ARM GAS /tmp/ccnIlCuV.s page 40 + + +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary fo +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR MT LL_RTC_DATE_GetMonth\n +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MU LL_RTC_DATE_GetMonth +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JANUARY +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_FEBRUARY +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MARCH +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_APRIL +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MAY +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JUNE +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JULY +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_AUGUST +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_SEPTEMBER +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_OCTOBER +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_NOVEMBER +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_DECEMBER +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Day in BCD format +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD form +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR DT LL_RTC_DATE_SetDay\n +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DU LL_RTC_DATE_SetDay +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Day Value between Min_Data=0x01 and Max_Data=0x31 +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)) +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Day in BCD format +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary form +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR DT LL_RTC_DATE_GetDay\n +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DU LL_RTC_DATE_GetDay +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x31 +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + ARM GAS /tmp/ccnIlCuV.s page 41 + + +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set date (WeekDay, Day, Month and Year) in BCD format +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR WDU LL_RTC_DATE_Config\n +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MT LL_RTC_DATE_Config\n +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MU LL_RTC_DATE_Config\n +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DT LL_RTC_DATE_Config\n +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DU LL_RTC_DATE_Config\n +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YT LL_RTC_DATE_Config\n +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YU LL_RTC_DATE_Config +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param WeekDay This parameter can be one of the following values: +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Day Value between Min_Data=0x01 and Max_Data=0x31 +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Month This parameter can be one of the following values: +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JANUARY +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_FEBRUARY +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MARCH +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_APRIL +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MAY +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JUNE +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JULY +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_AUGUST +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_SEPTEMBER +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_OCTOBER +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_NOVEMBER +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_DECEMBER +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Year Value between Min_Data=0x00 and Max_Data=0x99 +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = (WeekDay << RTC_POSITION_DR_WDU) | +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)); +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RT +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get date (WeekDay, Day, Month and Year) in BCD format +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * before reading this bit +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * and __LL_RTC_GET_DAY are available to get independently each parameter. + ARM GAS /tmp/ccnIlCuV.s page 42 + + +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll DR WDU LL_RTC_DATE_Get\n +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MT LL_RTC_DATE_Get\n +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR MU LL_RTC_DATE_Get\n +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DT LL_RTC_DATE_Get\n +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR DU LL_RTC_DATE_Get\n +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YT LL_RTC_DATE_Get\n +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * DR YU LL_RTC_DATE_Get +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_ALARMA ALARMA +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Alarm A +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR ALRAE LL_RTC_ALMA_Enable +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_ALRAE); +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Alarm A +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR ALRAE LL_RTC_ALMA_Disable +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Specify the Alarm A masks. +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK1 LL_RTC_ALMA_SetMask +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask This parameter can be a combination of the following values: +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_NONE +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + ARM GAS /tmp/ccnIlCuV.s page 43 + + +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_HOURS +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_MINUTES +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_SECONDS +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_ALL +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, M +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get the Alarm A masks. +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MSK1 LL_RTC_ALMA_GetMask +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be can be a combination of the following values: +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_NONE +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_HOURS +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_MINUTES +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_SECONDS +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_MASK_ALL +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RT +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not ca +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); + 185 .loc 2 1725 0 + 186 002c E369 ldr r3, [r4, #28] + 187 002e 454A ldr r2, .L15 + 188 .LVL9: + 189 0030 1340 ands r3, r2 + 190 0032 E361 str r3, [r4, #28] + ARM GAS /tmp/ccnIlCuV.s page 44 + + + 191 .LVL10: + 192 .LBE125: + 193 .LBE124: + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set the date for ALARM */ + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_DisableWeekday(RTCx); + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 194 .loc 1 547 0 + 195 0034 002E cmp r6, #0 + 196 0036 0DD0 beq .L10 + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + 197 .loc 1 549 0 + 198 0038 2A7C ldrb r2, [r5, #16] + 199 .LVL11: + 200 .LBB126: + 201 .LBB127: +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM A Day in BCD format +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD form +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR DU LL_RTC_ALMA_SetDay +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Day Value between Min_Data=0x01 and Max_Data=0x31 +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + 202 .loc 2 1739 0 + 203 003a E369 ldr r3, [r4, #28] + 204 003c 4249 ldr r1, .L15+4 + 205 .LVL12: + 206 003e 0B40 ands r3, r1 + 207 0040 1206 lsls r2, r2, #24 + 208 .LVL13: + 209 0042 1343 orrs r3, r2 + 210 0044 E361 str r3, [r4, #28] + 211 .LVL14: + 212 0046 26E0 b .L11 + 213 .LVL15: + 214 .L5: + 215 .LBE127: + 216 .LBE126: + 217 .LBB128: + 218 .LBB129: + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 219 .loc 2 820 0 + 220 0048 8368 ldr r3, [r0, #8] + 221 .LVL16: + 222 .LBE129: + 223 .LBE128: + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 224 .loc 1 515 0 + 225 004a 5B06 lsls r3, r3, #25 + ARM GAS /tmp/ccnIlCuV.s page 45 + + + 226 004c E7D4 bmi .L7 + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 227 .loc 1 522 0 + 228 004e 0023 movs r3, #0 + 229 0050 1360 str r3, [r2] + 230 0052 E4E7 b .L7 + 231 .LVL17: + 232 .L10: + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + 233 .loc 1 553 0 + 234 0054 2F7C ldrb r7, [r5, #16] + 235 0056 0A21 movs r1, #10 + 236 .LVL18: + 237 0058 3800 movs r0, r7 + 238 .LVL19: + 239 005a FFF7FEFF bl __aeabi_uidiv + 240 .LVL20: + 241 005e 0001 lsls r0, r0, #4 + 242 0060 C3B2 uxtb r3, r0 + 243 0062 9846 mov r8, r3 + 244 0064 0A21 movs r1, #10 + 245 0066 3800 movs r0, r7 + 246 0068 FFF7FEFF bl __aeabi_uidivmod + 247 .LVL21: + 248 006c 4346 mov r3, r8 + 249 006e 1943 orrs r1, r3 + 250 .LVL22: + 251 .LBB130: + 252 .LBB131: + 253 .loc 2 1739 0 + 254 0070 E369 ldr r3, [r4, #28] + 255 0072 354A ldr r2, .L15+4 + 256 0074 1340 ands r3, r2 + 257 0076 0906 lsls r1, r1, #24 + 258 .LVL23: + 259 0078 1943 orrs r1, r3 + 260 007a E161 str r1, [r4, #28] + 261 007c 0BE0 b .L11 + 262 .LVL24: + 263 .L9: + 264 .LBE131: + 265 .LBE130: + 266 .LBB132: + 267 .LBB133: +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 268 .loc 2 1714 0 + 269 007e E269 ldr r2, [r4, #28] + 270 .LVL25: + 271 0080 8023 movs r3, #128 + 272 0082 DB05 lsls r3, r3, #23 + 273 0084 1343 orrs r3, r2 + 274 0086 E361 str r3, [r4, #28] + 275 .LVL26: + 276 .LBE133: + ARM GAS /tmp/ccnIlCuV.s page 46 + + + 277 .LBE132: + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set the week day for ALARM */ + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_EnableWeekday(RTCx); + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + 278 .loc 1 560 0 + 279 0088 2A7C ldrb r2, [r5, #16] + 280 .LVL27: + 281 .LBB134: + 282 .LBB135: +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_ +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM A Day in BCD format +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary form +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR DU LL_RTC_ALMA_GetDay +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x31 +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_ +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM A Weekday +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param WeekDay This parameter can be one of the following values: +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU); + 283 .loc 2 1775 0 + 284 008a E369 ldr r3, [r4, #28] + 285 008c 2F49 ldr r1, .L15+8 + 286 .LVL28: + 287 008e 0B40 ands r3, r1 + 288 0090 1206 lsls r2, r2, #24 + 289 .LVL29: + 290 0092 1343 orrs r3, r2 + ARM GAS /tmp/ccnIlCuV.s page 47 + + + 291 0094 E361 str r3, [r4, #28] + 292 .LVL30: + 293 .L11: + 294 .LBE135: + 295 .LBE134: + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Configure the Alarm register */ + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 296 .loc 1 564 0 + 297 0096 002E cmp r6, #0 + 298 0098 45D1 bne .L14 + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime. + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + 299 .loc 1 571 0 + 300 009a 2B68 ldr r3, [r5] + 301 009c 9946 mov r9, r3 + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + 302 .loc 1 572 0 + 303 009e 2F79 ldrb r7, [r5, #4] + 304 00a0 0A21 movs r1, #10 + 305 00a2 3800 movs r0, r7 + 306 00a4 FFF7FEFF bl __aeabi_uidiv + 307 .LVL31: + 308 00a8 0001 lsls r0, r0, #4 + 309 00aa C6B2 uxtb r6, r0 + 310 .LVL32: + 311 00ac 0A21 movs r1, #10 + 312 00ae 3800 movs r0, r7 + 313 00b0 FFF7FEFF bl __aeabi_uidivmod + 314 .LVL33: + 315 00b4 0E43 orrs r6, r1 + 316 00b6 F3B2 uxtb r3, r6 + 317 00b8 9846 mov r8, r3 + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + 318 .loc 1 573 0 + 319 00ba 6F79 ldrb r7, [r5, #5] + 320 00bc 0A21 movs r1, #10 + 321 00be 3800 movs r0, r7 + 322 00c0 FFF7FEFF bl __aeabi_uidiv + 323 .LVL34: + 324 00c4 0001 lsls r0, r0, #4 + 325 00c6 C6B2 uxtb r6, r0 + 326 00c8 0A21 movs r1, #10 + 327 00ca 3800 movs r0, r7 + 328 00cc FFF7FEFF bl __aeabi_uidivmod + 329 .LVL35: + 330 00d0 0E43 orrs r6, r1 + 331 00d2 F3B2 uxtb r3, r6 + 332 00d4 9A46 mov r10, r3 + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + 333 .loc 1 574 0 + ARM GAS /tmp/ccnIlCuV.s page 48 + + + 334 00d6 AF79 ldrb r7, [r5, #6] + 335 00d8 0A21 movs r1, #10 + 336 00da 3800 movs r0, r7 + 337 00dc FFF7FEFF bl __aeabi_uidiv + 338 .LVL36: + 339 00e0 0001 lsls r0, r0, #4 + 340 00e2 C6B2 uxtb r6, r0 + 341 00e4 0A21 movs r1, #10 + 342 00e6 3800 movs r0, r7 + 343 00e8 FFF7FEFF bl __aeabi_uidivmod + 344 .LVL37: + 345 00ec 0E43 orrs r6, r1 + 346 00ee F6B2 uxtb r6, r6 + 347 .LVL38: + 348 .LBB136: + 349 .LBB137: +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM A Weekday +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU); +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm A time format (AM/24-hour or PM notation) +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param TimeFormat This parameter can be one of the following values: +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm A time format (AM or PM notation) +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + ARM GAS /tmp/ccnIlCuV.s page 49 + + +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM A Hours in BCD format +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD fo +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR HU LL_RTC_ALMA_SetHour +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_A +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM A Hours in BCD format +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary fo +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR HU LL_RTC_ALMA_GetHour +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x2 +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_ +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM A Minutes in BCD format +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNU LL_RTC_ALMA_SetMinute +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITI +1867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM A Minutes in BCD format +1871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary +1872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n +1873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNU LL_RTC_ALMA_GetMinute + ARM GAS /tmp/ccnIlCuV.s page 50 + + +1874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +1876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); +1882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR +1883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM A Seconds in BCD format +1887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD +1888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n +1889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR SU LL_RTC_ALMA_SetSecond +1890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +1892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +1895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITI +1898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM A Seconds in BCD format +1902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary +1903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n +1904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR SU LL_RTC_ALMA_GetSecond +1905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +1907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +1909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); +1913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_ +1914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm A Time (hour, minute and second) in BCD format +1918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n +1919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR HT LL_RTC_ALMA_ConfigTime\n +1920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR HU LL_RTC_ALMA_ConfigTime\n +1921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n +1922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n +1923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR ST LL_RTC_ALMA_ConfigTime\n +1924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR SU LL_RTC_ALMA_ConfigTime +1925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Format12_24 This parameter can be one of the following values: +1927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM +1928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM +1929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +1930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + ARM GAS /tmp/ccnIlCuV.s page 51 + + +1931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +1932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours +1935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +1937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_ + 350 .loc 2 1938 0 + 351 00f0 4346 mov r3, r8 + 352 00f2 1904 lsls r1, r3, #16 + 353 00f4 4B46 mov r3, r9 + 354 00f6 1943 orrs r1, r3 +1939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 355 .loc 2 1939 0 + 356 00f8 5346 mov r3, r10 + 357 00fa 1802 lsls r0, r3, #8 +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 358 .loc 2 1938 0 + 359 00fc 0143 orrs r1, r0 + 360 00fe 0E43 orrs r6, r1 + 361 .LVL39: +1940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_A +1941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALR + 362 .loc 2 1942 0 + 363 0100 E169 ldr r1, [r4, #28] + 364 0102 134B ldr r3, .L15+12 + 365 0104 1940 ands r1, r3 + 366 0106 0E43 orrs r6, r1 + 367 .LVL40: + 368 0108 E661 str r6, [r4, #28] + 369 .LVL41: + 370 .L13: + 371 .LBE137: + 372 .LBE136: + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set ALARM mask */ + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + 373 .loc 1 577 0 + 374 010a AB68 ldr r3, [r5, #8] + 375 .LVL42: + 376 .LBB138: + 377 .LBB139: +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 378 .loc 2 1683 0 + 379 010c E269 ldr r2, [r4, #28] + 380 010e 1149 ldr r1, .L15+16 + 381 0110 0A40 ands r2, r1 + 382 0112 1343 orrs r3, r2 + 383 .LVL43: + 384 0114 E361 str r3, [r4, #28] + 385 .LVL44: + 386 .LBE139: + 387 .LBE138: + 388 .LBB140: + 389 .LBB141: + ARM GAS /tmp/ccnIlCuV.s page 52 + + +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 390 .loc 2 1053 0 + 391 0116 FF23 movs r3, #255 + 392 0118 6362 str r3, [r4, #36] + 393 .LVL45: + 394 .LBE141: + 395 .LBE140: + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return SUCCESS; + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 396 .loc 1 583 0 + 397 011a 0120 movs r0, #1 + 398 @ sp needed + 399 .LVL46: + 400 .LVL47: + 401 011c 1CBC pop {r2, r3, r4} + 402 011e 9046 mov r8, r2 + 403 0120 9946 mov r9, r3 + 404 0122 A246 mov r10, r4 + 405 0124 F0BD pop {r4, r5, r6, r7, pc} + 406 .LVL48: + 407 .L14: + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + 408 .loc 1 566 0 + 409 0126 2A79 ldrb r2, [r5, #4] + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 410 .loc 1 567 0 + 411 0128 6979 ldrb r1, [r5, #5] + 412 012a AB79 ldrb r3, [r5, #6] + 413 .LVL49: + 414 .LBB142: + 415 .LBB143: +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 416 .loc 2 1938 0 + 417 012c 1204 lsls r2, r2, #16 + 418 .LVL50: + 419 012e 2868 ldr r0, [r5] + 420 0130 0243 orrs r2, r0 +1939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_A + 421 .loc 2 1939 0 + 422 0132 0902 lsls r1, r1, #8 + 423 .LVL51: +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 424 .loc 2 1938 0 + 425 0134 0A43 orrs r2, r1 + 426 0136 1343 orrs r3, r2 + 427 .LVL52: + 428 .loc 2 1942 0 + 429 0138 E269 ldr r2, [r4, #28] + 430 013a 0549 ldr r1, .L15+12 + 431 013c 0A40 ands r2, r1 + 432 013e 1343 orrs r3, r2 + 433 .LVL53: + 434 0140 E361 str r3, [r4, #28] + ARM GAS /tmp/ccnIlCuV.s page 53 + + + 435 .LVL54: + 436 0142 E2E7 b .L13 + 437 .L16: + 438 .align 2 + 439 .L15: + 440 0144 FFFFFFBF .word -1073741825 + 441 0148 FFFFFFC0 .word -1056964609 + 442 014c FFFFFFF0 .word -251658241 + 443 0150 808080FF .word -8355712 + 444 0154 7F7F7F7F .word 2139062143 + 445 .LBE143: + 446 .LBE142: + 447 .cfi_endproc + 448 .LFE265: + 450 .section .text.LL_RTC_ALMB_Init,"ax",%progbits + 451 .align 1 + 452 .global LL_RTC_ALMB_Init + 453 .syntax unified + 454 .code 16 + 455 .thumb_func + 456 .fpu softvfp + 458 LL_RTC_ALMB_Init: + 459 .LFB266: + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set the RTC Alarm B. + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The Alarm register can only be written when the corresponding Alarm + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * is disabled (@ref LL_RTC_ALMB_Disable function). + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_Format This parameter can be one of the following values: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BIN + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @arg @ref LL_RTC_FORMAT_BCD + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * contains the alarm configuration parameters. + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: ALARMB registers are configured + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: ALARMB registers are not configured + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_Alarm + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 460 .loc 1 600 0 + 461 .cfi_startproc + 462 @ args = 0, pretend = 0, frame = 0 + 463 @ frame_needed = 0, uses_anonymous_args = 0 + 464 .LVL55: + 465 0000 F0B5 push {r4, r5, r6, r7, lr} + 466 .LCFI2: + 467 .cfi_def_cfa_offset 20 + 468 .cfi_offset 4, -20 + 469 .cfi_offset 5, -16 + 470 .cfi_offset 6, -12 + 471 .cfi_offset 7, -8 + 472 .cfi_offset 14, -4 + 473 0002 D646 mov lr, r10 + 474 0004 4F46 mov r7, r9 + 475 0006 4646 mov r6, r8 + 476 0008 C0B5 push {r6, r7, lr} + ARM GAS /tmp/ccnIlCuV.s page 54 + + + 477 .LCFI3: + 478 .cfi_def_cfa_offset 32 + 479 .cfi_offset 8, -32 + 480 .cfi_offset 9, -28 + 481 .cfi_offset 10, -24 + 482 000a 0400 movs r4, r0 + 483 000c 0E00 movs r6, r1 + 484 000e 1500 movs r5, r2 + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameters */ + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format == LL_RTC_FORMAT_BIN) + 485 .loc 1 607 0 + 486 0010 0029 cmp r1, #0 + 487 0012 1AD1 bne .L18 + 488 .LVL56: + 489 .LBB144: + 490 .LBB145: + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 491 .loc 2 820 0 + 492 0014 8368 ldr r3, [r0, #8] + 493 .LVL57: + 494 .LBE145: + 495 .LBE144: + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 496 .loc 1 609 0 + 497 0016 5B06 lsls r3, r3, #25 + 498 0018 01D4 bmi .L20 + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + 499 .loc 1 616 0 + 500 001a 0023 movs r3, #0 + 501 001c 1360 str r3, [r2] + 502 .L20: + 503 .LVL58: + 504 .LBB146: + 505 .LBB147: +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 506 .loc 2 1064 0 + 507 001e CA23 movs r3, #202 + 508 0020 6362 str r3, [r4, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 509 .loc 2 1065 0 + 510 0022 773B subs r3, r3, #119 + 511 0024 6362 str r3, [r4, #36] + 512 .LVL59: + 513 .LBE147: + 514 .LBE146: + ARM GAS /tmp/ccnIlCuV.s page 55 + + + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable the write protection for RTC registers */ + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableWriteProtection(RTCx); + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Select weekday selection */ + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + 515 .loc 1 661 0 + 516 0026 EB68 ldr r3, [r5, #12] + 517 0028 002B cmp r3, #0 + 518 002a 2AD1 bne .L22 + 519 .LVL60: + 520 .LBB148: + 521 .LBB149: +1943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm B Time (hour, minute and second) in BCD format +1947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + ARM GAS /tmp/ccnIlCuV.s page 56 + + +1948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * are available to get independently each parameter. +1949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n +1950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR HU LL_RTC_ALMA_GetTime\n +1951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNT LL_RTC_ALMA_GetTime\n +1952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR MNU LL_RTC_ALMA_GetTime\n +1953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR ST LL_RTC_ALMA_GetTime\n +1954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMAR SU LL_RTC_ALMA_GetTime +1955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of hours, minutes and seconds. +1957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +1959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) < +1961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm A Mask the most-significant bits starting at this bit +1965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note This register can be written only when ALRAE is reset in RTC_CR register, +1966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * or in initialization mode. +1967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask +1968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask Value between Min_Data=0x00 and Max_Data=0xF +1970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +1973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS); +1975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm A Mask the most-significant bits starting at this bit +1979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask +1980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xF +1982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +1984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS); +1986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +1988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +1989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm A Sub seconds value +1990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond +1991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +1992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF +1993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +1994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +1995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +1996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +1997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +1998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +1999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm A Sub seconds value +2002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond +2003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + ARM GAS /tmp/ccnIlCuV.s page 57 + + +2005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +2007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +2009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +2013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_ALARMB ALARMB +2016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +2017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Alarm B +2021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR ALRBE LL_RTC_ALMB_Enable +2023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +2027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_ALRBE); +2029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Alarm B +2033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR ALRBE LL_RTC_ALMB_Disable +2035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +2039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +2041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Specify the Alarm B masks. +2045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n +2046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n +2047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n +2048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK1 LL_RTC_ALMB_SetMask +2049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask This parameter can be a combination of the following values: +2051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_NONE +2052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY +2053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_HOURS +2054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_MINUTES +2055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_SECONDS +2056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_ALL +2057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +2060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, M + ARM GAS /tmp/ccnIlCuV.s page 58 + + +2062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get the Alarm B masks. +2066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n +2067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n +2068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n +2069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MSK1 LL_RTC_ALMB_GetMask +2070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be can be a combination of the following values: +2072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_NONE +2073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY +2074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_HOURS +2075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_MINUTES +2076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_SECONDS +2077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_MASK_ALL +2078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +2080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RT +2082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not ca +2086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday +2087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +2091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +2093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) +2097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday +2098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +2102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); + 522 .loc 2 2103 0 + 523 002c 236A ldr r3, [r4, #32] + 524 002e 464A ldr r2, .L28 + 525 .LVL61: + 526 0030 1340 ands r3, r2 + 527 0032 2362 str r3, [r4, #32] + 528 .LVL62: + 529 .LBE149: + 530 .LBE148: + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set the date for ALARM */ + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_DisableWeekday(RTCx); + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 531 .loc 1 665 0 + 532 0034 002E cmp r6, #0 + ARM GAS /tmp/ccnIlCuV.s page 59 + + + 533 0036 0ED0 beq .L23 + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + 534 .loc 1 667 0 + 535 0038 2A7C ldrb r2, [r5, #16] + 536 .LVL63: + 537 .LBB150: + 538 .LBB151: +2104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B Day in BCD format +2108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD form +2109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n +2110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR DU LL_RTC_ALMB_SetDay +2111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Day Value between Min_Data=0x01 and Max_Data=0x31 +2113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +2116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + 539 .loc 2 2117 0 + 540 003a 4449 ldr r1, .L28+4 + 541 .LVL64: + 542 003c 0B6A ldr r3, [r1, #32] + 543 003e 4448 ldr r0, .L28+8 + 544 .LVL65: + 545 0040 0340 ands r3, r0 + 546 0042 1206 lsls r2, r2, #24 + 547 .LVL66: + 548 0044 1343 orrs r3, r2 + 549 0046 0B62 str r3, [r1, #32] + 550 .LVL67: + 551 0048 27E0 b .L24 + 552 .LVL68: + 553 .L18: + 554 .LBE151: + 555 .LBE150: + 556 .LBB152: + 557 .LBB153: + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 558 .loc 2 820 0 + 559 004a 8368 ldr r3, [r0, #8] + 560 .LVL69: + 561 .LBE153: + 562 .LBE152: + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 563 .loc 1 633 0 + 564 004c 5B06 lsls r3, r3, #25 + 565 004e E6D4 bmi .L20 + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + 566 .loc 1 640 0 + 567 0050 0023 movs r3, #0 + 568 0052 1360 str r3, [r2] + 569 0054 E3E7 b .L20 + 570 .LVL70: + ARM GAS /tmp/ccnIlCuV.s page 60 + + + 571 .L23: + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + 572 .loc 1 671 0 + 573 0056 2F7C ldrb r7, [r5, #16] + 574 0058 0A21 movs r1, #10 + 575 .LVL71: + 576 005a 3800 movs r0, r7 + 577 .LVL72: + 578 005c FFF7FEFF bl __aeabi_uidiv + 579 .LVL73: + 580 0060 0001 lsls r0, r0, #4 + 581 0062 C3B2 uxtb r3, r0 + 582 0064 9846 mov r8, r3 + 583 0066 0A21 movs r1, #10 + 584 0068 3800 movs r0, r7 + 585 006a FFF7FEFF bl __aeabi_uidivmod + 586 .LVL74: + 587 006e 4346 mov r3, r8 + 588 0070 1943 orrs r1, r3 + 589 .LVL75: + 590 .LBB154: + 591 .LBB155: + 592 .loc 2 2117 0 + 593 0072 364A ldr r2, .L28+4 + 594 0074 136A ldr r3, [r2, #32] + 595 0076 3648 ldr r0, .L28+8 + 596 0078 0340 ands r3, r0 + 597 007a 0906 lsls r1, r1, #24 + 598 .LVL76: + 599 007c 1943 orrs r1, r3 + 600 007e 1162 str r1, [r2, #32] + 601 0080 0BE0 b .L24 + 602 .LVL77: + 603 .L22: + 604 .LBE155: + 605 .LBE154: + 606 .LBB156: + 607 .LBB157: +2092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 608 .loc 2 2092 0 + 609 0082 226A ldr r2, [r4, #32] + 610 .LVL78: + 611 0084 8023 movs r3, #128 + 612 0086 DB05 lsls r3, r3, #23 + 613 0088 1343 orrs r3, r2 + 614 008a 2362 str r3, [r4, #32] + 615 .LVL79: + 616 .LBE157: + 617 .LBE156: + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set the week day for ALARM */ + ARM GAS /tmp/ccnIlCuV.s page 61 + + + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_EnableWeekday(RTCx); + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + 618 .loc 1 678 0 + 619 008c 2A7C ldrb r2, [r5, #16] + 620 .LVL80: + 621 .LBB158: + 622 .LBB159: +2118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_ALMB_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMB_ +2119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B Day in BCD format +2123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary form +2124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n +2125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR DU LL_RTC_ALMB_GetDay +2126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x31 +2128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +2130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +2132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); +2134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_POSITION_ALMB_DT) << 4U) | ((temp & RTC_ALRMBR_ +2135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B Weekday +2139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay +2140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param WeekDay This parameter can be one of the following values: +2142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +2143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +2144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +2145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +2146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +2147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +2148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +2149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +2152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_POSITION_ALMB_DU); + 623 .loc 2 2153 0 + 624 008e 236A ldr r3, [r4, #32] + 625 0090 3049 ldr r1, .L28+12 + 626 .LVL81: + 627 0092 0B40 ands r3, r1 + 628 0094 1206 lsls r2, r2, #24 + 629 .LVL82: + 630 0096 1343 orrs r3, r2 + 631 0098 2362 str r3, [r4, #32] + 632 .LVL83: + 633 .L24: + 634 .LBE159: + 635 .LBE158: + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + ARM GAS /tmp/ccnIlCuV.s page 62 + + + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Configure the Alarm register */ + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (RTC_Format != LL_RTC_FORMAT_BIN) + 636 .loc 1 682 0 + 637 009a 002E cmp r6, #0 + 638 009c 45D1 bne .L27 + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime. + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** else + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + 639 .loc 1 689 0 + 640 009e 2B68 ldr r3, [r5] + 641 00a0 9946 mov r9, r3 + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + 642 .loc 1 690 0 + 643 00a2 2F79 ldrb r7, [r5, #4] + 644 00a4 0A21 movs r1, #10 + 645 00a6 3800 movs r0, r7 + 646 00a8 FFF7FEFF bl __aeabi_uidiv + 647 .LVL84: + 648 00ac 0001 lsls r0, r0, #4 + 649 00ae C6B2 uxtb r6, r0 + 650 .LVL85: + 651 00b0 0A21 movs r1, #10 + 652 00b2 3800 movs r0, r7 + 653 00b4 FFF7FEFF bl __aeabi_uidivmod + 654 .LVL86: + 655 00b8 0E43 orrs r6, r1 + 656 00ba F3B2 uxtb r3, r6 + 657 00bc 9846 mov r8, r3 + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + 658 .loc 1 691 0 + 659 00be 6F79 ldrb r7, [r5, #5] + 660 00c0 0A21 movs r1, #10 + 661 00c2 3800 movs r0, r7 + 662 00c4 FFF7FEFF bl __aeabi_uidiv + 663 .LVL87: + 664 00c8 0001 lsls r0, r0, #4 + 665 00ca C6B2 uxtb r6, r0 + 666 00cc 0A21 movs r1, #10 + 667 00ce 3800 movs r0, r7 + 668 00d0 FFF7FEFF bl __aeabi_uidivmod + 669 .LVL88: + 670 00d4 0E43 orrs r6, r1 + 671 00d6 F3B2 uxtb r3, r6 + 672 00d8 9A46 mov r10, r3 + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + 673 .loc 1 692 0 + 674 00da AF79 ldrb r7, [r5, #6] + 675 00dc 0A21 movs r1, #10 + 676 00de 3800 movs r0, r7 + 677 00e0 FFF7FEFF bl __aeabi_uidiv + 678 .LVL89: + 679 00e4 0001 lsls r0, r0, #4 + ARM GAS /tmp/ccnIlCuV.s page 63 + + + 680 00e6 C6B2 uxtb r6, r0 + 681 00e8 0A21 movs r1, #10 + 682 00ea 3800 movs r0, r7 + 683 00ec FFF7FEFF bl __aeabi_uidivmod + 684 .LVL90: + 685 00f0 0E43 orrs r6, r1 + 686 00f2 F6B2 uxtb r6, r6 + 687 .LVL91: + 688 .LBB160: + 689 .LBB161: +2154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B Weekday +2158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay +2159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +2162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +2163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +2164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +2165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +2166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +2167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +2168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +2170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU); +2172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B time format (AM/24-hour or PM notation) +2176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat +2177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param TimeFormat This parameter can be one of the following values: +2179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM +2180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM +2181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +2184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +2186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B time format (AM or PM notation) +2190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat +2191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM +2194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM +2195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +2197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +2199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** + ARM GAS /tmp/ccnIlCuV.s page 64 + + +2201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B Hours in BCD format +2203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD fo +2204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n +2205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR HU LL_RTC_ALMB_SetHour +2206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +2208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +2211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), +2213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_A +2214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B Hours in BCD format +2218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary fo +2219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n +2220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR HU LL_RTC_ALMB_GetHour +2221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x2 +2223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +2225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +2227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); +2229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_POSITION_ALMB_HT) << 4U) | ((temp & RTC_ALRMBR_ +2230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B Minutes in BCD format +2234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD +2235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n +2236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNU LL_RTC_ALMB_SetMinute +2237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes between Min_Data=0x00 and Max_Data=0x59 +2239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +2242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), +2244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITI +2245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B Minutes in BCD format +2249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary +2250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n +2251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNU LL_RTC_ALMB_GetMinute +2252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +2254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +2256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; + ARM GAS /tmp/ccnIlCuV.s page 65 + + +2258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); +2260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_POSITION_ALMB_MT) << 4U) | ((temp & RTC_ALRMBR +2261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set ALARM B Seconds in BCD format +2265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD +2266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n +2267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR SU LL_RTC_ALMB_SetSecond +2268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +2270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +2273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), +2275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITI +2276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get ALARM B Seconds in BCD format +2280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary +2281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n +2282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR SU LL_RTC_ALMB_GetSecond +2283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +2285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +2287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; +2289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); +2291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_POSITION_ALMB_ST) << 4U) | ((temp & RTC_ALRMBR_ +2292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm B Time (hour, minute and second) in BCD format +2296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n +2297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR HT LL_RTC_ALMB_ConfigTime\n +2298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR HU LL_RTC_ALMB_ConfigTime\n +2299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n +2300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n +2301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR ST LL_RTC_ALMB_ConfigTime\n +2302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR SU LL_RTC_ALMB_ConfigTime +2303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Format12_24 This parameter can be one of the following values: +2305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM +2306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM +2307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Da +2308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 +2309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 +2310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours +2313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t temp = 0U; + ARM GAS /tmp/ccnIlCuV.s page 66 + + +2315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_ + 690 .loc 2 2316 0 + 691 00f4 4346 mov r3, r8 + 692 00f6 1904 lsls r1, r3, #16 + 693 00f8 4B46 mov r3, r9 + 694 00fa 1943 orrs r1, r3 +2317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 695 .loc 2 2317 0 + 696 00fc 5346 mov r3, r10 + 697 00fe 1802 lsls r0, r3, #8 +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 698 .loc 2 2316 0 + 699 0100 0143 orrs r1, r0 + 700 0102 0E43 orrs r6, r1 + 701 .LVL92: +2318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_A +2319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRM + 702 .loc 2 2320 0 + 703 0104 216A ldr r1, [r4, #32] + 704 0106 144B ldr r3, .L28+16 + 705 0108 1940 ands r1, r3 + 706 010a 0E43 orrs r6, r1 + 707 .LVL93: + 708 010c 2662 str r6, [r4, #32] + 709 .LVL94: + 710 .L26: + 711 .LBE161: + 712 .LBE160: + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set ALARM mask */ + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + 713 .loc 1 695 0 + 714 010e AB68 ldr r3, [r5, #8] + 715 .LVL95: + 716 .LBB162: + 717 .LBB163: +2061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 718 .loc 2 2061 0 + 719 0110 226A ldr r2, [r4, #32] + 720 0112 1249 ldr r1, .L28+20 + 721 0114 0A40 ands r2, r1 + 722 0116 1343 orrs r3, r2 + 723 .LVL96: + 724 0118 2362 str r3, [r4, #32] + 725 .LVL97: + 726 .LBE163: + 727 .LBE162: + 728 .LBB164: + 729 .LBB165: +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 730 .loc 2 1053 0 + 731 011a FF23 movs r3, #255 + 732 011c 6362 str r3, [r4, #36] + 733 .LVL98: + 734 .LBE165: + ARM GAS /tmp/ccnIlCuV.s page 67 + + + 735 .LBE164: + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Enable the write protection for RTC registers */ + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableWriteProtection(RTCx); + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return SUCCESS; + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 736 .loc 1 701 0 + 737 011e 0120 movs r0, #1 + 738 @ sp needed + 739 .LVL99: + 740 .LVL100: + 741 0120 1CBC pop {r2, r3, r4} + 742 0122 9046 mov r8, r2 + 743 0124 9946 mov r9, r3 + 744 0126 A246 mov r10, r4 + 745 0128 F0BD pop {r4, r5, r6, r7, pc} + 746 .LVL101: + 747 .L27: + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + 748 .loc 1 684 0 + 749 012a 2A79 ldrb r2, [r5, #4] + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 750 .loc 1 685 0 + 751 012c 6979 ldrb r1, [r5, #5] + 752 012e AB79 ldrb r3, [r5, #6] + 753 .LVL102: + 754 .LBB166: + 755 .LBB167: +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 756 .loc 2 2316 0 + 757 0130 1204 lsls r2, r2, #16 + 758 .LVL103: + 759 0132 2868 ldr r0, [r5] + 760 0134 0243 orrs r2, r0 +2317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_A + 761 .loc 2 2317 0 + 762 0136 0902 lsls r1, r1, #8 + 763 .LVL104: +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_A + 764 .loc 2 2316 0 + 765 0138 0A43 orrs r2, r1 + 766 013a 1343 orrs r3, r2 + 767 .LVL105: + 768 .loc 2 2320 0 + 769 013c 226A ldr r2, [r4, #32] + 770 013e 0649 ldr r1, .L28+16 + 771 0140 0A40 ands r2, r1 + 772 0142 1343 orrs r3, r2 + 773 .LVL106: + 774 0144 2362 str r3, [r4, #32] + 775 .LVL107: + 776 0146 E2E7 b .L26 + 777 .L29: + 778 .align 2 + 779 .L28: + 780 0148 FFFFFFBF .word -1073741825 + ARM GAS /tmp/ccnIlCuV.s page 68 + + + 781 014c 00280040 .word 1073752064 + 782 0150 FFFFFFC0 .word -1056964609 + 783 0154 FFFFFFF0 .word -251658241 + 784 0158 808080FF .word -8355712 + 785 015c 7F7F7F7F .word 2139062143 + 786 .LBE167: + 787 .LBE166: + 788 .cfi_endproc + 789 .LFE266: + 791 .section .text.LL_RTC_ALMA_StructInit,"ax",%progbits + 792 .align 1 + 793 .global LL_RTC_ALMA_StructInit + 794 .syntax unified + 795 .code 16 + 796 .thumb_func + 797 .fpu softvfp + 799 LL_RTC_ALMA_StructInit: + 800 .LFB267: + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00s + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * Day = 1st day of the month/Mask = all fields are masked). + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initializ + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval None + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 801 .loc 1 710 0 + 802 .cfi_startproc + 803 @ args = 0, pretend = 0, frame = 0 + 804 @ frame_needed = 0, uses_anonymous_args = 0 + 805 @ link register save eliminated. + 806 .LVL108: + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Time Settings : Time = 00h:00mn:00sec */ + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + 807 .loc 1 712 0 + 808 0000 0023 movs r3, #0 + 809 0002 0360 str r3, [r0] + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Hours = 0U; + 810 .loc 1 713 0 + 811 0004 0371 strb r3, [r0, #4] + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes = 0U; + 812 .loc 1 714 0 + 813 0006 4371 strb r3, [r0, #5] + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Seconds = 0U; + 814 .loc 1 715 0 + 815 0008 8371 strb r3, [r0, #6] + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Day Settings : Day = 1st day of the month */ + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + 816 .loc 1 718 0 + 817 000a C360 str r3, [r0, #12] + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmDateWeekDay = 1U; + 818 .loc 1 719 0 + 819 000c 0122 movs r2, #1 + 820 000e 0274 strb r2, [r0, #16] + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + ARM GAS /tmp/ccnIlCuV.s page 69 + + + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Masks Settings : Mask = all fields are not masked */ + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; + 821 .loc 1 722 0 + 822 0010 8360 str r3, [r0, #8] + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 823 .loc 1 723 0 + 824 @ sp needed + 825 0012 7047 bx lr + 826 .cfi_endproc + 827 .LFE267: + 829 .section .text.LL_RTC_ALMB_StructInit,"ax",%progbits + 830 .align 1 + 831 .global LL_RTC_ALMB_StructInit + 832 .syntax unified + 833 .code 16 + 834 .thumb_func + 835 .fpu softvfp + 837 LL_RTC_ALMB_StructInit: + 838 .LFB268: + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00s + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * Day = 1st day of the month/Mask = all fields are masked). + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initializ + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval None + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 839 .loc 1 732 0 + 840 .cfi_startproc + 841 @ args = 0, pretend = 0, frame = 0 + 842 @ frame_needed = 0, uses_anonymous_args = 0 + 843 @ link register save eliminated. + 844 .LVL109: + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Time Settings : Time = 00h:00mn:00sec */ + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + 845 .loc 1 734 0 + 846 0000 0023 movs r3, #0 + 847 0002 0360 str r3, [r0] + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Hours = 0U; + 848 .loc 1 735 0 + 849 0004 0371 strb r3, [r0, #4] + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Minutes = 0U; + 850 .loc 1 736 0 + 851 0006 4371 strb r3, [r0, #5] + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmTime.Seconds = 0U; + 852 .loc 1 737 0 + 853 0008 8371 strb r3, [r0, #6] + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Day Settings : Day = 1st day of the month */ + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + 854 .loc 1 740 0 + 855 000a C360 str r3, [r0, #12] + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmDateWeekDay = 1U; + 856 .loc 1 741 0 + 857 000c 0122 movs r2, #1 + 858 000e 0274 strb r2, [r0, #16] + ARM GAS /tmp/ccnIlCuV.s page 70 + + + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Alarm Masks Settings : Mask = all fields are not masked */ + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; + 859 .loc 1 744 0 + 860 0010 8360 str r3, [r0, #8] + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 861 .loc 1 745 0 + 862 @ sp needed + 863 0012 7047 bx lr + 864 .cfi_endproc + 865 .LFE268: + 867 .section .text.LL_RTC_EnterInitMode,"ax",%progbits + 868 .align 1 + 869 .global LL_RTC_EnterInitMode + 870 .syntax unified + 871 .code 16 + 872 .thumb_func + 873 .fpu softvfp + 875 LL_RTC_EnterInitMode: + 876 .LFB269: + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Enters the RTC Initialization mode. + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The RTC Initialization mode is write protected, use the + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @ref LL_RTC_DisableWriteProtection before calling this function. + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC is in Init mode + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC is not in Init mode + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 877 .loc 1 757 0 + 878 .cfi_startproc + 879 @ args = 0, pretend = 0, frame = 8 + 880 @ frame_needed = 0, uses_anonymous_args = 0 + 881 @ link register save eliminated. + 882 .LVL110: + 883 0000 82B0 sub sp, sp, #8 + 884 .LCFI4: + 885 .cfi_def_cfa_offset 8 + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + 886 .loc 1 758 0 + 887 0002 FA23 movs r3, #250 + 888 0004 9B00 lsls r3, r3, #2 + 889 0006 0193 str r3, [sp, #4] + 890 .LVL111: + 891 .LBB168: + 892 .LBB169: +2321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm B Time (hour, minute and second) in BCD format +2325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND +2326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * are available to get independently each parameter. +2327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n +2328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR HU LL_RTC_ALMB_GetTime\n + ARM GAS /tmp/ccnIlCuV.s page 71 + + +2329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNT LL_RTC_ALMB_GetTime\n +2330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR MNU LL_RTC_ALMB_GetTime\n +2331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR ST LL_RTC_ALMB_GetTime\n +2332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * ALRMBR SU LL_RTC_ALMB_GetTime +2333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of hours, minutes and seconds. +2335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +2337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) < +2339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm B Mask the most-significant bits starting at this bit +2343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note This register can be written only when ALRBE is reset in RTC_CR register, +2344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * or in initialization mode. +2345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask +2346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask Value between Min_Data=0x00 and Max_Data=0xF +2348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +2351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_POSITION_ALMB_MASKSS); +2353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm B Mask the most-significant bits starting at this bit +2357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask +2358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xF +2360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +2362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_POSITION_ALMB_MASKSS); +2364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Alarm B Sub seconds value +2368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond +2369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF +2371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +2374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +2376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm B Sub seconds value +2380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond +2381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF +2383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +2385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + ARM GAS /tmp/ccnIlCuV.s page 72 + + +2386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +2387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +2391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Timestamp Timestamp +2394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +2395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Timestamp +2399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR TSE LL_RTC_TS_Enable +2401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +2405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_TSE); +2407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Timestamp +2411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR TSE LL_RTC_TS_Disable +2413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +2417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +2419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Time-stamp event active edge +2423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting +2425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge +2426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Edge This parameter can be one of the following values: +2428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING +2429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING +2430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +2433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +2435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Time-stamp event active edge +2439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge +2441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccnIlCuV.s page 73 + + +2443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING +2444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING +2445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +2447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +2449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp AM/PM notation (AM or 24-hour format) +2453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat +2454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TS_TIME_FORMAT_AM +2457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TS_TIME_FORMAT_PM +2458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +2460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +2462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Hours in BCD format +2466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary fo +2467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSTR HT LL_RTC_TS_GetHour\n +2468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR HU LL_RTC_TS_GetHour +2469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x2 +2471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +2473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU); +2475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Minutes in BCD format +2479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary +2480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n +2481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR MNU LL_RTC_TS_GetMinute +2482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +2484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +2486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU); +2488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Seconds in BCD format +2492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary +2493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n +2494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR SU LL_RTC_TS_GetSecond +2495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x59 +2497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +2499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + ARM GAS /tmp/ccnIlCuV.s page 74 + + +2500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +2501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp time (hour, minute and second) in BCD format +2505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND +2506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * are available to get independently each parameter. +2507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSTR HT LL_RTC_TS_GetTime\n +2508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR HU LL_RTC_TS_GetTime\n +2509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR MNT LL_RTC_TS_GetTime\n +2510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR MNU LL_RTC_TS_GetTime\n +2511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR ST LL_RTC_TS_GetTime\n +2512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSTR SU LL_RTC_TS_GetTime +2513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of hours, minutes and seconds. +2515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +2517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSTR, +2519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST +2520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Week day +2524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay +2525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_MONDAY +2528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_TUESDAY +2529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY +2530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_THURSDAY +2531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_FRIDAY +2532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SATURDAY +2533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WEEKDAY_SUNDAY +2534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +2536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU); +2538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Month in BCD format +2542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary fo +2543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n +2544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR MU LL_RTC_TS_GetMonth +2545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JANUARY +2548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_FEBRUARY +2549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MARCH +2550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_APRIL +2551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_MAY +2552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JUNE +2553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_JULY +2554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_AUGUST +2555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_SEPTEMBER +2556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_OCTOBER + ARM GAS /tmp/ccnIlCuV.s page 75 + + +2557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_NOVEMBER +2558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_MONTH_DECEMBER +2559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +2561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU); +2563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp Day in BCD format +2567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary form +2568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSDR DT LL_RTC_TS_GetDay\n +2569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR DU LL_RTC_TS_GetDay +2570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x01 and Max_Data=0x31 +2572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +2574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +2576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format +2580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, +2581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * and __LL_RTC_GET_DAY are available to get independently each parameter. +2582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n +2583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR MT LL_RTC_TS_GetDate\n +2584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR MU LL_RTC_TS_GetDate\n +2585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR DT LL_RTC_TS_GetDate\n +2586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TSDR DU LL_RTC_TS_GetDate +2587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Combination of Weekday, Day and Month +2589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +2591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | R +2593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get time-stamp sub second value +2597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond +2598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF +2600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +2602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +2604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPTS) +2607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Activate timestamp on tamper detection event +2609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper +2610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 76 + + +2614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +2616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable timestamp on tamper detection event +2620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper +2621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +2625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +2627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPTS */ +2629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +2632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Tamper Tamper +2635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +2636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable RTC_TAMPx input detection +2640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable\n +2641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2E LL_RTC_TAMPER_Enable\n +2642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3E LL_RTC_TAMPER_Enable +2643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_1 (*) +2646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_2 +2647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_3 (*) +2648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +2653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, Tamper); +2655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear RTC_TAMPx input detection +2659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable\n +2660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2E LL_RTC_TAMPER_Disable\n +2661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3E LL_RTC_TAMPER_Disable +2662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_1 (*) +2665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_2 +2666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_3 (*) +2667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ + ARM GAS /tmp/ccnIlCuV.s page 77 + + +2671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +2672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, Tamper); +2674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Tamper mask flag +2678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Associated Tamper IT must not enabled when tamper mask is set. +2679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask\n +2680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask\n +2681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask +2682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask This parameter can be a combination of the following values: +2684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*) +2685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 +2686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*) +2687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +2692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, Mask); +2694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Tamper mask flag +2698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask\n +2699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask\n +2700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask +2701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Mask This parameter can be a combination of the following values: +2703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*) +2704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 +2705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*) +2706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +2711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, Mask); +2713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable backup register erase after Tamper event detection +2717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n +2718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP\n +2719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP +2720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*) +2723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 +2724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*) +2725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None + ARM GAS /tmp/ccnIlCuV.s page 78 + + +2728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +2730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, Tamper); +2732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable backup register erase after Tamper event detection +2736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n +2737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP\n +2738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP +2739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*) +2742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 +2743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*) +2744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +2749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, Tamper); +2751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPPUDIS) +2754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) +2756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp +2757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +2761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +2763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) +2767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp +2768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +2772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +2774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPPUDIS */ +2776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPPRCH) +2778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set RTC_TAMPx precharge duration +2780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge +2781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Duration This parameter can be one of the following values: +2783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK +2784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + ARM GAS /tmp/ccnIlCuV.s page 79 + + +2785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK +2786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK +2787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +2790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration); +2792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_TAMPx precharge duration +2796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge +2797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK +2800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK +2801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK +2802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK +2803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +2805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); +2807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPPRCH */ +2809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPFLT) +2811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set RTC_TAMPx filter count +2813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount +2814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param FilterCount This parameter can be one of the following values: +2816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE +2817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE +2818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE +2819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE +2820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +2823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount); +2825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_TAMPx filter count +2829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount +2830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE +2833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE +2834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE +2835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE +2836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +2838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); +2840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPFLT */ + ARM GAS /tmp/ccnIlCuV.s page 80 + + +2842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPCR_TAMPFREQ) +2844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Tamper sampling frequency +2846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq +2847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param SamplingFreq This parameter can be one of the following values: +2849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 +2850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 +2851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 +2852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 +2853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 +2854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 +2855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 +2856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 +2857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +2860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq); +2862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Tamper sampling frequency +2866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq +2867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 +2870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 +2871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 +2872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 +2873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 +2874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 +2875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 +2876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 +2877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +2879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); +2881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPCR_TAMPFREQ */ +2883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Active level for Tamper input +2886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n +2887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n +2888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel +2889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 (*) +2892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 +2893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*) +2894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) + ARM GAS /tmp/ccnIlCuV.s page 81 + + +2899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->TAMPCR, Tamper); +2901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Active level for Tamper input +2905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n +2906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n +2907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel +2908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Tamper This parameter can be a combination of the following values: +2910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 (*) +2911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 +2912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*) +2913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * +2914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * (*) value not defined in all devices. +2915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +2918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->TAMPCR, Tamper); +2920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +2924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_WAKEUP_SUPPORT) +2927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Wakeup Wakeup +2928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +2929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Enable Wakeup timer +2933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable +2935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +2939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** SET_BIT(RTCx->CR, RTC_CR_WUTE); +2941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Disable Wakeup timer +2945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable +2947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +2951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +2953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** + ARM GAS /tmp/ccnIlCuV.s page 82 + + +2956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Check if Wakeup timer is enabled or not +2957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled +2958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +2960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +2962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); +2964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Select Wakeup clock +2968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +2969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 +2970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock +2971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param WakeupClock This parameter can be one of the following values: +2973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 +2974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 +2975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 +2976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 +2977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE +2978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT +2979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +2980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +2982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +2983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +2984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +2985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +2986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +2987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Wakeup clock +2988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock +2989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +2990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +2991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 +2992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 +2993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 +2994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 +2995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE +2996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT +2997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +2998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +2999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +3001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Wakeup auto-reload value +3005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR +3006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload +3007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF +3009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +3012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { + ARM GAS /tmp/ccnIlCuV.s page 83 + + +3013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +3014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Wakeup auto-reload value +3018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload +3019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF +3021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +3023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +3025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +3029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_WAKEUP_SUPPORT */ +3031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_BACKUP_SUPPORT) +3033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers +3034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +3035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Writes a data in a specified RTC Backup data register. +3039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister +3040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param BackupRegister This parameter can be one of the following values: +3042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR0 +3043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR1 +3044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR2 +3045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR3 +3046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR4 +3047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF +3048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Da +3051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t tmp = 0U; +3053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** tmp = (uint32_t)(&(RTCx->BKP0R)); +3055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** tmp += (BackupRegister * 4U); +3056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Write the specified register */ +3058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** *(__IO uint32_t *)tmp = (uint32_t)Data; +3059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Reads data from the specified RTC Backup data Register. +3063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister +3064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param BackupRegister This parameter can be one of the following values: +3066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR0 +3067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR1 +3068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR2 +3069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR3 + ARM GAS /tmp/ccnIlCuV.s page 84 + + +3070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_BKP_DR4 +3071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF +3072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +3074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** register uint32_t tmp = 0U; +3076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** tmp = (uint32_t)(&(RTCx->BKP0R)); +3078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** tmp += (BackupRegister * 4U); +3079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /* Read the specified register */ +3081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (*(__IO uint32_t *)tmp); +3082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +3086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_BACKUP_SUPPORT */ +3088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_Calibration Calibration +3090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +3091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Calibration output frequency (1 Hz or 512 Hz) +3095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +3096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n +3097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * CR COSEL LL_RTC_CAL_SetOutputFreq +3098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Frequency This parameter can be one of the following values: +3100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_NONE +3101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ +3102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ +3103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +3106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +3108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Calibration output frequency (1 Hz or 512 Hz) +3112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n +3113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * CR COSEL LL_RTC_CAL_GetOutputFreq +3114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +3116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_NONE +3117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ +3118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ +3119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +3121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +3123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + ARM GAS /tmp/ccnIlCuV.s page 85 + + +3127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +3128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR +3129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALP LL_RTC_CAL_SetPulse +3130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Pulse This parameter can be one of the following values: +3132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE +3133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET +3134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +3137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +3139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased b +3143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted +3144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +3148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); +3150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set the calibration cycle period +3154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +3155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR +3156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n +3157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * CALR CALW16 LL_RTC_CAL_SetPeriod +3158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param Period This parameter can be one of the following values: +3160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_32SEC +3161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_16SEC +3162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_8SEC +3163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +3166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +3168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get the calibration cycle period +3172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n +3173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * CALR CALW16 LL_RTC_CAL_GetPeriod +3174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Returned value can be one of the following values: +3176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_32SEC +3177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_16SEC +3178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @arg @ref LL_RTC_CALIB_PERIOD_8SEC +3179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +3181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +3183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + ARM GAS /tmp/ccnIlCuV.s page 86 + + +3184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Set Calibration minus +3187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called be +3188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR +3189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALM LL_RTC_CAL_SetMinus +3190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF +3192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +3195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +3197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Calibration minus +3201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll CALR CALM LL_RTC_CAL_GetMinus +3202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF +3204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +3206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +3208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @} +3212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management +3215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @{ +3216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Recalibration pending Flag +3220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP +3221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +3225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)); +3227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) +3230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_TAMP3 detection flag +3232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3 +3233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +3237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)); +3239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ + ARM GAS /tmp/ccnIlCuV.s page 87 + + +3241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) +3243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_TAMP2 detection flag +3245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 +3246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +3250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)); +3252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ +3254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) +3256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get RTC_TAMP1 detection flag +3258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1 +3259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +3263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)); +3265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ +3267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Time-stamp overflow flag +3270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV +3271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +3275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)); +3277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Time-stamp flag +3281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS +3282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +3286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)); +3288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_WAKEUP_SUPPORT) +3291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Wakeup timer flag +3293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT +3294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 88 + + +3298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)); +3300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_WAKEUP_SUPPORT */ +3302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm B flag +3305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB +3306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +3310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)); +3312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Alarm A flag +3316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA +3317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +3321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)); +3323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER3_SUPPORT) +3326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear RTC_TAMP3 detection flag +3328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3 +3329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +3333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INI +3335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER3_SUPPORT */ +3337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER2_SUPPORT) +3339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear RTC_TAMP2 detection flag +3341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 +3342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +3346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INI +3348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER2_SUPPORT */ +3350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_TAMPER1_SUPPORT) +3352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear RTC_TAMP1 detection flag +3354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1 + ARM GAS /tmp/ccnIlCuV.s page 89 + + +3355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +3359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INI +3361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_TAMPER1_SUPPORT */ +3363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Time-stamp overflow flag +3366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV +3367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +3371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT +3373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Time-stamp flag +3377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR TSF LL_RTC_ClearFlag_TS +3378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +3382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)) +3384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #if defined(RTC_WAKEUP_SUPPORT) +3387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Wakeup timer flag +3389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT +3390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +3394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT) +3396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** #endif /* RTC_WAKEUP_SUPPORT */ +3398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Alarm B flag +3401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB +3402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +3406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT +3408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Alarm A flag + ARM GAS /tmp/ccnIlCuV.s page 90 + + +3412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA +3413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +3417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT +3419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Initialization flag +3423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT +3424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +3428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)); + 893 .loc 2 3429 0 + 894 0008 C368 ldr r3, [r0, #12] + 895 .LVL112: + 896 .LBE169: + 897 .LBE168: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = SUCCESS; + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** uint32_t tmp = 0U; + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameter */ + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check if the Initialization mode is set */ + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + 898 .loc 1 766 0 + 899 000a 5B06 lsls r3, r3, #25 + 900 000c 1ED4 bmi .L38 + 901 .LVL113: + 902 .LBB170: + 903 .LBB171: + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 904 .loc 2 896 0 + 905 000e 0123 movs r3, #1 + 906 0010 5B42 rsbs r3, r3, #0 + 907 0012 C360 str r3, [r0, #12] + 908 .LVL114: + 909 .LBE171: + 910 .LBE170: + 911 .LBB172: + 912 .LBB173: + 913 .loc 2 3429 0 + 914 0014 C268 ldr r2, [r0, #12] + 915 0016 4133 adds r3, r3, #65 + 916 0018 1340 ands r3, r2 + 917 001a 5A1E subs r2, r3, #1 + 918 001c 9341 sbcs r3, r3, r2 + 919 .LVL115: + 920 .LBE173: + 921 .LBE172: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = SUCCESS; + ARM GAS /tmp/ccnIlCuV.s page 91 + + + 922 .loc 1 759 0 + 923 001e 0121 movs r1, #1 + 924 .LVL116: + 925 .L34: + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Set the Initialization mode */ + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_EnableInitMode(RTCx); + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Wait till RTC is in INIT state and if Time out is reached exit */ + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** while ((timeout != 0U) && (tmp != 1U)) + 926 .loc 1 773 0 + 927 0020 019A ldr r2, [sp, #4] + 928 0022 002A cmp r2, #0 + 929 0024 13D0 beq .L33 + 930 .loc 1 773 0 is_stmt 0 discriminator 1 + 931 0026 012B cmp r3, #1 + 932 0028 11D0 beq .L33 + 933 .LBB174: + 934 .LBB175: + 935 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @file stm32l0xx_ll_cortex.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @brief Header file of CORTEX LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** @verbatim + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ============================================================================== + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ##### How to use this driver ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** The LL CORTEX driver contains a set of generic APIs that can be + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** used by user: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** functions + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** (+) Low power mode configuration (SCB register of Cortex-MCU) + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** (+) MPU API to configure and enable regions + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** (+) API to access to MCU info (CPUID register) + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** @endverbatim + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ****************************************************************************** + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @attention + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * Redistribution and use in source and binary forms, with or without modification, + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * are permitted provided that the following conditions are met: + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * 1. Redistributions of source code must retain the above copyright notice, + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * this list of conditions and the following disclaimer. + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * this list of conditions and the following disclaimer in the documentation + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * and/or other materials provided with the distribution. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * may be used to endorse or promote products derived from this software + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * without specific prior written permission. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + ARM GAS /tmp/ccnIlCuV.s page 92 + + + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** ****************************************************************************** + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #ifndef __STM32L0xx_LL_CORTEX_H + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define __STM32L0xx_LL_CORTEX_H + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #ifdef __cplusplus + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** extern "C" { + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #endif + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Includes ------------------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #include "stm32l0xx.h" + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @addtogroup STM32L0xx_LL_Driver + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL CORTEX + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Private types -------------------------------------------------------------*/ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Private variables ---------------------------------------------------------*/ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Private constants ---------------------------------------------------------*/ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Private macros ------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Exported types ------------------------------------------------------------*/ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Exported constants --------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock d + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock se + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #if __MPU_PRESENT + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + ARM GAS /tmp/ccnIlCuV.s page 93 + + + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< E + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< E + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< E + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_REGION MPU Region Number + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */ + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size o + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size o + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size o + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size o + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size o + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size o + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size o + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size o + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size o + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size o + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size o + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size o + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size o + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + ARM GAS /tmp/ccnIlCuV.s page 94 + + + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privilege + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privilege + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privilege + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privilege + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privilege + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TE + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TE + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TE + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TE + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */ + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + ARM GAS /tmp/ccnIlCuV.s page 95 + + + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute * + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** #endif /* __MPU_PRESENT */ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @} + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Exported macro ------------------------------------------------------------*/ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /* Exported functions --------------------------------------------------------*/ + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @{ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** /** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @brief This function checks if the Systick counter flag is active or not. + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @note It can be used in timeout function on application side. + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** * @retval State of bit (1 or 0). + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** */ + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** { + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h **** return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); + 936 .loc 3 237 0 is_stmt 1 + 937 002a 0A4B ldr r3, .L40 + 938 .LVL117: + 939 002c 1B68 ldr r3, [r3] + 940 .LBE175: + 941 .LBE174: + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + 942 .loc 1 775 0 + 943 002e DB03 lsls r3, r3, #15 + 944 0030 02D5 bpl .L35 + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** timeout --; + 945 .loc 1 777 0 + 946 0032 019B ldr r3, [sp, #4] + 947 0034 013B subs r3, r3, #1 + 948 0036 0193 str r3, [sp, #4] + 949 .L35: + 950 .LVL118: + 951 .LBB176: + 952 .LBB177: + 953 .loc 2 3429 0 + 954 0038 C268 ldr r2, [r0, #12] + 955 003a 4023 movs r3, #64 + 956 003c 1340 ands r3, r2 + 957 003e 5A1E subs r2, r3, #1 + 958 0040 9341 sbcs r3, r3, r2 + ARM GAS /tmp/ccnIlCuV.s page 96 + + + 959 .LVL119: + 960 .LBE177: + 961 .LBE176: + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (timeout == 0U) + 962 .loc 1 780 0 + 963 0042 019A ldr r2, [sp, #4] + 964 0044 002A cmp r2, #0 + 965 0046 EBD1 bne .L34 + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = ERROR; + 966 .loc 1 782 0 + 967 0048 0021 movs r1, #0 + 968 .LVL120: + 969 004a E9E7 b .L34 + 970 .LVL121: + 971 .L38: + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** uint32_t tmp = 0U; + 972 .loc 1 759 0 + 973 004c 0121 movs r1, #1 + 974 .LVL122: + 975 .L33: + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return status; + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 976 .loc 1 787 0 + 977 004e 0800 movs r0, r1 + 978 .LVL123: + 979 0050 02B0 add sp, sp, #8 + 980 @ sp needed + 981 0052 7047 bx lr + 982 .L41: + 983 .align 2 + 984 .L40: + 985 0054 10E000E0 .word -536813552 + 986 .cfi_endproc + 987 .LFE269: + 989 .section .text.LL_RTC_Init,"ax",%progbits + 990 .align 1 + 991 .global LL_RTC_Init + 992 .syntax unified + 993 .code 16 + 994 .thumb_func + 995 .fpu softvfp + 997 LL_RTC_Init: + 998 .LFB259: + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 999 .loc 1 230 0 + 1000 .cfi_startproc + 1001 @ args = 0, pretend = 0, frame = 0 + 1002 @ frame_needed = 0, uses_anonymous_args = 0 + 1003 .LVL124: + 1004 0000 70B5 push {r4, r5, r6, lr} + 1005 .LCFI5: + ARM GAS /tmp/ccnIlCuV.s page 97 + + + 1006 .cfi_def_cfa_offset 16 + 1007 .cfi_offset 4, -16 + 1008 .cfi_offset 5, -12 + 1009 .cfi_offset 6, -8 + 1010 .cfi_offset 14, -4 + 1011 0002 0400 movs r4, r0 + 1012 0004 0D00 movs r5, r1 + 1013 .LVL125: + 1014 .LBB178: + 1015 .LBB179: +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 1016 .loc 2 1064 0 + 1017 0006 CA23 movs r3, #202 + 1018 0008 4362 str r3, [r0, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1019 .loc 2 1065 0 + 1020 000a 773B subs r3, r3, #119 + 1021 000c 4362 str r3, [r0, #36] + 1022 .LVL126: + 1023 .LBE179: + 1024 .LBE178: + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1025 .loc 1 243 0 + 1026 000e FFF7FEFF bl LL_RTC_EnterInitMode + 1027 .LVL127: + 1028 0012 0028 cmp r0, #0 + 1029 0014 16D0 beq .L43 + 1030 .LVL128: + 1031 .LBB180: + 1032 .LBB181: + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1033 .loc 2 807 0 + 1034 0016 A368 ldr r3, [r4, #8] + 1035 0018 4022 movs r2, #64 + 1036 001a 9343 bics r3, r2 + 1037 001c 2A68 ldr r2, [r5] + 1038 001e 1343 orrs r3, r2 + 1039 0020 A360 str r3, [r4, #8] + 1040 .LVL129: + 1041 .LBE181: + 1042 .LBE180: + 1043 .LBB182: + 1044 .LBB183: +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1045 .loc 2 1020 0 + 1046 0022 2369 ldr r3, [r4, #16] + 1047 0024 DB0B lsrs r3, r3, #15 + 1048 0026 DB03 lsls r3, r3, #15 + 1049 0028 AA68 ldr r2, [r5, #8] + 1050 002a 1343 orrs r3, r2 + 1051 002c 2361 str r3, [r4, #16] + 1052 .LVL130: + 1053 .LBE183: + 1054 .LBE182: + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1055 .loc 1 250 0 + 1056 002e 6A68 ldr r2, [r5, #4] + ARM GAS /tmp/ccnIlCuV.s page 98 + + + 1057 .LVL131: + 1058 .LBB184: + 1059 .LBB185: +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1060 .loc 2 1008 0 + 1061 0030 2369 ldr r3, [r4, #16] + 1062 0032 0649 ldr r1, .L44 + 1063 0034 0B40 ands r3, r1 + 1064 0036 1204 lsls r2, r2, #16 + 1065 .LVL132: + 1066 0038 1343 orrs r3, r2 + 1067 003a 2361 str r3, [r4, #16] + 1068 .LVL133: + 1069 .LBE185: + 1070 .LBE184: + 1071 .LBB186: + 1072 .LBB187: + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1073 .loc 2 908 0 + 1074 003c 8123 movs r3, #129 + 1075 003e 5B42 rsbs r3, r3, #0 + 1076 0040 E360 str r3, [r4, #12] + 1077 .LVL134: + 1078 .LBE187: + 1079 .LBE186: + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1080 .loc 1 255 0 + 1081 0042 0120 movs r0, #1 + 1082 .LVL135: + 1083 .L43: + 1084 .LBB188: + 1085 .LBB189: +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1086 .loc 2 1053 0 + 1087 0044 FF23 movs r3, #255 + 1088 0046 6362 str r3, [r4, #36] + 1089 .LVL136: + 1090 .LBE189: + 1091 .LBE188: + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1092 .loc 1 261 0 + 1093 @ sp needed + 1094 .LVL137: + 1095 .LVL138: + 1096 0048 70BD pop {r4, r5, r6, pc} + 1097 .L45: + 1098 004a C046 .align 2 + 1099 .L44: + 1100 004c FFFF80FF .word -8323073 + 1101 .cfi_endproc + 1102 .LFE259: + 1104 .section .text.LL_RTC_ExitInitMode,"ax",%progbits + 1105 .align 1 + 1106 .global LL_RTC_ExitInitMode + 1107 .syntax unified + 1108 .code 16 + 1109 .thumb_func + ARM GAS /tmp/ccnIlCuV.s page 99 + + + 1110 .fpu softvfp + 1112 LL_RTC_ExitInitMode: + 1113 .LFB270: + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Exit the RTC Initialization mode. + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note When the initialization sequence is complete, the calendar restarts + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * counting after 4 RTCCLK cycles. + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The RTC Initialization mode is write protected, use the + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @ref LL_RTC_DisableWriteProtection before calling this function. + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC exited from in Init mode + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: Not applicable + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1114 .loc 1 801 0 + 1115 .cfi_startproc + 1116 @ args = 0, pretend = 0, frame = 0 + 1117 @ frame_needed = 0, uses_anonymous_args = 0 + 1118 @ link register save eliminated. + 1119 .LVL139: + 1120 .LBB190: + 1121 .LBB191: + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1122 .loc 2 908 0 + 1123 0000 8123 movs r3, #129 + 1124 0002 5B42 rsbs r3, r3, #0 + 1125 0004 C360 str r3, [r0, #12] + 1126 .LVL140: + 1127 .LBE191: + 1128 .LBE190: + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameter */ + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Disable initialization mode */ + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_DisableInitMode(RTCx); + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return SUCCESS; + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1129 .loc 1 809 0 + 1130 0006 0120 movs r0, #1 + 1131 .LVL141: + 1132 @ sp needed + 1133 0008 7047 bx lr + 1134 .cfi_endproc + 1135 .LFE270: + 1137 .section .text.LL_RTC_WaitForSynchro,"ax",%progbits + 1138 .align 1 + 1139 .global LL_RTC_WaitForSynchro + 1140 .syntax unified + 1141 .code 16 + 1142 .thumb_func + 1143 .fpu softvfp + 1145 LL_RTC_WaitForSynchro: + 1146 .LFB271: + ARM GAS /tmp/ccnIlCuV.s page 100 + + + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /** + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * synchronized with RTC APB clock. + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note The RTC Resynchronization mode is write protected, use the + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @ref LL_RTC_DisableWriteProtection before calling this function. + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @note To read the calendar through the shadow registers after Calendar + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * initialization, calendar update or after wakeup from low power modes + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * the software must first clear the RSF flag. + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * The software must then wait until it is set again before reading + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * the calendar, which means that the calendar registers have been + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * correctly copied into the RTC_TR and RTC_DR shadow registers. + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @param RTCx RTC Instance + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * @retval An ErrorStatus enumeration value: + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - SUCCESS: RTC registers are synchronised + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** * - ERROR: RTC registers are not synchronised + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** */ + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1147 .loc 1 828 0 + 1148 .cfi_startproc + 1149 @ args = 0, pretend = 0, frame = 8 + 1150 @ frame_needed = 0, uses_anonymous_args = 0 + 1151 @ link register save eliminated. + 1152 .LVL142: + 1153 0000 82B0 sub sp, sp, #8 + 1154 .LCFI6: + 1155 .cfi_def_cfa_offset 8 + 1156 0002 0100 movs r1, r0 + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + 1157 .loc 1 829 0 + 1158 0004 FA23 movs r3, #250 + 1159 0006 9B00 lsls r3, r3, #2 + 1160 0008 0193 str r3, [sp, #4] + 1161 .LVL143: + 1162 .LBB192: + 1163 .LBB193: +3430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Get Registers synchronization flag +3434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS +3435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval State of bit (1 or 0). +3437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +3439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)); +3441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } +3442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** +3443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** /** +3444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @brief Clear Registers synchronization flag +3445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @rmtoll ISR RSF LL_RTC_ClearFlag_RS +3446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @param RTCx RTC Instance +3447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** * @retval None +3448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** */ +3449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) + ARM GAS /tmp/ccnIlCuV.s page 101 + + +3450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** { +3451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)) + 1164 .loc 2 3451 0 + 1165 000a C268 ldr r2, [r0, #12] + 1166 000c 8023 movs r3, #128 + 1167 000e 1A40 ands r2, r3 + 1168 0010 223B subs r3, r3, #34 + 1169 0012 FF3B subs r3, r3, #255 + 1170 0014 1343 orrs r3, r2 + 1171 0016 C360 str r3, [r0, #12] + 1172 .LVL144: + 1173 .LBE193: + 1174 .LBE192: + 1175 .LBB194: + 1176 .LBB195: +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1177 .loc 2 3440 0 + 1178 0018 C268 ldr r2, [r0, #12] + 1179 001a 2023 movs r3, #32 + 1180 001c 1340 ands r3, r2 + 1181 001e 5A1E subs r2, r3, #1 + 1182 0020 9341 sbcs r3, r3, r2 + 1183 .LVL145: + 1184 .LBE195: + 1185 .LBE194: + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = SUCCESS; + 1186 .loc 1 830 0 + 1187 0022 0120 movs r0, #1 + 1188 .LVL146: + 1189 .L48: + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** uint32_t tmp = 0U; + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Check the parameter */ + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Clear RSF flag */ + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_ClearFlag_RS(RTCx); + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Wait the registers to be synchronised */ + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_RS(RTCx); + 841:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** while ((timeout != 0U) && (tmp != 0U)) + 1190 .loc 1 841 0 + 1191 0024 019A ldr r2, [sp, #4] + 1192 0026 002A cmp r2, #0 + 1193 0028 12D0 beq .L51 + 1194 .loc 1 841 0 is_stmt 0 discriminator 1 + 1195 002a 002B cmp r3, #0 + 1196 002c 10D0 beq .L51 + 1197 .LBB196: + 1198 .LBB197: + 1199 .loc 3 237 0 is_stmt 1 + 1200 002e 194B ldr r3, .L60 + 1201 .LVL147: + 1202 0030 1B68 ldr r3, [r3] + 1203 .LBE197: + 1204 .LBE196: + 842:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + ARM GAS /tmp/ccnIlCuV.s page 102 + + + 843:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + 1205 .loc 1 843 0 + 1206 0032 DB03 lsls r3, r3, #15 + 1207 0034 02D5 bpl .L49 + 844:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 845:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** timeout--; + 1208 .loc 1 845 0 + 1209 0036 019B ldr r3, [sp, #4] + 1210 0038 013B subs r3, r3, #1 + 1211 003a 0193 str r3, [sp, #4] + 1212 .L49: + 1213 .LVL148: + 1214 .LBB198: + 1215 .LBB199: +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1216 .loc 2 3440 0 + 1217 003c CA68 ldr r2, [r1, #12] + 1218 003e 2023 movs r3, #32 + 1219 0040 1340 ands r3, r2 + 1220 0042 5A1E subs r2, r3, #1 + 1221 0044 9341 sbcs r3, r3, r2 + 1222 .LVL149: + 1223 .LBE199: + 1224 .LBE198: + 846:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 847:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_RS(RTCx); + 848:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (timeout == 0U) + 1225 .loc 1 848 0 + 1226 0046 019A ldr r2, [sp, #4] + 1227 0048 002A cmp r2, #0 + 1228 004a EBD1 bne .L48 + 849:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 850:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = ERROR; + 1229 .loc 1 850 0 + 1230 004c 0020 movs r0, #0 + 1231 .LVL150: + 1232 004e E9E7 b .L48 + 1233 .LVL151: + 1234 .L51: + 851:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 852:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 853:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 854:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (status != ERROR) + 1235 .loc 1 854 0 + 1236 0050 0028 cmp r0, #0 + 1237 0052 1DD0 beq .L53 + 855:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 856:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** timeout = RTC_SYNCHRO_TIMEOUT; + 1238 .loc 1 856 0 + 1239 0054 FA23 movs r3, #250 + 1240 .LVL152: + 1241 0056 9B00 lsls r3, r3, #2 + 1242 0058 0193 str r3, [sp, #4] + 1243 .LVL153: + 1244 .LBB200: + 1245 .LBB201: +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + ARM GAS /tmp/ccnIlCuV.s page 103 + + + 1246 .loc 2 3440 0 + 1247 005a CA68 ldr r2, [r1, #12] + 1248 005c 2023 movs r3, #32 + 1249 005e 1340 ands r3, r2 + 1250 0060 5A1E subs r2, r3, #1 + 1251 0062 9341 sbcs r3, r3, r2 + 1252 .LVL154: + 1253 .L54: + 1254 .LBE201: + 1255 .LBE200: + 857:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_RS(RTCx); + 858:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** while ((timeout != 0U) && (tmp != 1U)) + 1256 .loc 1 858 0 + 1257 0064 019A ldr r2, [sp, #4] + 1258 0066 002A cmp r2, #0 + 1259 0068 12D0 beq .L53 + 1260 .loc 1 858 0 is_stmt 0 discriminator 1 + 1261 006a 012B cmp r3, #1 + 1262 006c 10D0 beq .L53 + 1263 .LBB202: + 1264 .LBB203: + 1265 .loc 3 237 0 is_stmt 1 + 1266 006e 094B ldr r3, .L60 + 1267 .LVL155: + 1268 0070 1B68 ldr r3, [r3] + 1269 .LBE203: + 1270 .LBE202: + 859:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 860:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + 1271 .loc 1 860 0 + 1272 0072 DB03 lsls r3, r3, #15 + 1273 0074 02D5 bpl .L55 + 861:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 862:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** timeout--; + 1274 .loc 1 862 0 + 1275 0076 019B ldr r3, [sp, #4] + 1276 0078 013B subs r3, r3, #1 + 1277 007a 0193 str r3, [sp, #4] + 1278 .L55: + 1279 .LVL156: + 1280 .LBB204: + 1281 .LBB205: +3440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1282 .loc 2 3440 0 + 1283 007c CA68 ldr r2, [r1, #12] + 1284 007e 2023 movs r3, #32 + 1285 0080 1340 ands r3, r2 + 1286 0082 5A1E subs r2, r3, #1 + 1287 0084 9341 sbcs r3, r3, r2 + 1288 .LVL157: + 1289 .LBE205: + 1290 .LBE204: + 863:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 864:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** tmp = LL_RTC_IsActiveFlag_RS(RTCx); + 865:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** if (timeout == 0U) + 1291 .loc 1 865 0 + 1292 0086 019A ldr r2, [sp, #4] + ARM GAS /tmp/ccnIlCuV.s page 104 + + + 1293 0088 002A cmp r2, #0 + 1294 008a EBD1 bne .L54 + 866:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 867:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** status = ERROR; + 1295 .loc 1 867 0 + 1296 008c 0020 movs r0, #0 + 1297 .LVL158: + 1298 008e E9E7 b .L54 + 1299 .LVL159: + 1300 .L53: + 868:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 869:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 870:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 871:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 872:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** return (status); + 873:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1301 .loc 1 873 0 + 1302 0090 02B0 add sp, sp, #8 + 1303 @ sp needed + 1304 0092 7047 bx lr + 1305 .L61: + 1306 .align 2 + 1307 .L60: + 1308 0094 10E000E0 .word -536813552 + 1309 .cfi_endproc + 1310 .LFE271: + 1312 .section .text.LL_RTC_DeInit,"ax",%progbits + 1313 .align 1 + 1314 .global LL_RTC_DeInit + 1315 .syntax unified + 1316 .code 16 + 1317 .thumb_func + 1318 .fpu softvfp + 1320 LL_RTC_DeInit: + 1321 .LFB258: + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 1322 .loc 1 166 0 + 1323 .cfi_startproc + 1324 @ args = 0, pretend = 0, frame = 0 + 1325 @ frame_needed = 0, uses_anonymous_args = 0 + 1326 .LVL160: + 1327 0000 10B5 push {r4, lr} + 1328 .LCFI7: + 1329 .cfi_def_cfa_offset 8 + 1330 .cfi_offset 4, -8 + 1331 .cfi_offset 14, -4 + 1332 0002 0400 movs r4, r0 + 1333 .LVL161: + 1334 .LBB206: + 1335 .LBB207: +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 1336 .loc 2 1064 0 + 1337 0004 CA23 movs r3, #202 + 1338 0006 4362 str r3, [r0, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1339 .loc 2 1065 0 + 1340 0008 773B subs r3, r3, #119 + ARM GAS /tmp/ccnIlCuV.s page 105 + + + 1341 000a 4362 str r3, [r0, #36] + 1342 .LVL162: + 1343 .LBE207: + 1344 .LBE206: + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1345 .loc 1 176 0 + 1346 000c FFF7FEFF bl LL_RTC_EnterInitMode + 1347 .LVL163: + 1348 0010 0028 cmp r0, #0 + 1349 0012 02D1 bne .L64 + 1350 .LVL164: + 1351 .L63: + 1352 .LBB208: + 1353 .LBB209: +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1354 .loc 2 1053 0 + 1355 0014 FF23 movs r3, #255 + 1356 0016 6362 str r3, [r4, #36] + 1357 .LVL165: + 1358 .LBE209: + 1359 .LBE208: + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1360 .loc 1 215 0 + 1361 @ sp needed + 1362 .LVL166: + 1363 0018 10BD pop {r4, pc} + 1364 .LVL167: + 1365 .L64: + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #if defined(RTC_WAKEUP_SUPPORT) + 1366 .loc 1 179 0 + 1367 001a 0023 movs r3, #0 + 1368 001c 2360 str r3, [r4] + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #endif /* RTC_WAKEUP_SUPPORT */ + 1369 .loc 1 181 0 + 1370 001e 0B4A ldr r2, .L65 + 1371 0020 6261 str r2, [r4, #20] + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** /* Reset All CR bits except CR[2:0] */ + 1372 .loc 1 183 0 + 1373 0022 0B4A ldr r2, .L65+4 + 1374 0024 6260 str r2, [r4, #4] + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** #else + 1375 .loc 1 186 0 + 1376 0026 A168 ldr r1, [r4, #8] + 1377 0028 0722 movs r2, #7 + 1378 002a 0A40 ands r2, r1 + 1379 002c A260 str r2, [r4, #8] + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); + 1380 .loc 1 190 0 + 1381 002e 094A ldr r2, .L65+8 + 1382 0030 2261 str r2, [r4, #16] + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); + 1383 .loc 1 191 0 + 1384 0032 E361 str r3, [r4, #28] + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); + 1385 .loc 1 192 0 + 1386 0034 2362 str r3, [r4, #32] + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + ARM GAS /tmp/ccnIlCuV.s page 106 + + + 1387 .loc 1 193 0 + 1388 0036 E362 str r3, [r4, #44] + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); + 1389 .loc 1 194 0 + 1390 0038 E363 str r3, [r4, #60] + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); + 1391 .loc 1 195 0 + 1392 003a 6364 str r3, [r4, #68] + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1393 .loc 1 196 0 + 1394 003c A364 str r3, [r4, #72] + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1395 .loc 1 199 0 + 1396 003e E360 str r3, [r4, #12] + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1397 .loc 1 202 0 + 1398 0040 2364 str r3, [r4, #64] + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1399 .loc 1 205 0 + 1400 0042 E364 str r3, [r4, #76] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1401 .loc 1 208 0 + 1402 0044 2000 movs r0, r4 + 1403 0046 FFF7FEFF bl LL_RTC_WaitForSynchro + 1404 .LVL168: + 1405 004a E3E7 b .L63 + 1406 .L66: + 1407 .align 2 + 1408 .L65: + 1409 004c FFFF0000 .word 65535 + 1410 0050 01210000 .word 8449 + 1411 0054 FF007F00 .word 8323327 + 1412 .cfi_endproc + 1413 .LFE258: + 1415 .section .text.LL_RTC_TIME_Init,"ax",%progbits + 1416 .align 1 + 1417 .global LL_RTC_TIME_Init + 1418 .syntax unified + 1419 .code 16 + 1420 .thumb_func + 1421 .fpu softvfp + 1423 LL_RTC_TIME_Init: + 1424 .LFB261: + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 1425 .loc 1 289 0 + 1426 .cfi_startproc + 1427 @ args = 0, pretend = 0, frame = 0 + 1428 @ frame_needed = 0, uses_anonymous_args = 0 + 1429 .LVL169: + 1430 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1431 .LCFI8: + 1432 .cfi_def_cfa_offset 24 + 1433 .cfi_offset 3, -24 + 1434 .cfi_offset 4, -20 + 1435 .cfi_offset 5, -16 + 1436 .cfi_offset 6, -12 + 1437 .cfi_offset 7, -8 + ARM GAS /tmp/ccnIlCuV.s page 107 + + + 1438 .cfi_offset 14, -4 + 1439 0002 CE46 mov lr, r9 + 1440 0004 4746 mov r7, r8 + 1441 0006 80B5 push {r7, lr} + 1442 .LCFI9: + 1443 .cfi_def_cfa_offset 32 + 1444 .cfi_offset 8, -32 + 1445 .cfi_offset 9, -28 + 1446 0008 0400 movs r4, r0 + 1447 000a 0E00 movs r6, r1 + 1448 000c 1500 movs r5, r2 + 1449 .LVL170: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1450 .loc 1 296 0 + 1451 000e 0029 cmp r1, #0 + 1452 0010 2BD1 bne .L68 + 1453 .LVL171: + 1454 .LBB210: + 1455 .LBB211: + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1456 .loc 2 820 0 + 1457 0012 8368 ldr r3, [r0, #8] + 1458 .LVL172: + 1459 .LBE211: + 1460 .LBE210: + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1461 .loc 1 298 0 + 1462 0014 5B06 lsls r3, r3, #25 + 1463 0016 01D4 bmi .L69 + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + 1464 .loc 1 305 0 + 1465 0018 0023 movs r3, #0 + 1466 001a 1360 str r3, [r2] + 1467 .L69: + 1468 .LVL173: + 1469 .LBB212: + 1470 .LBB213: +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 1471 .loc 2 1064 0 + 1472 001c CA23 movs r3, #202 + 1473 001e 6362 str r3, [r4, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1474 .loc 2 1065 0 + 1475 0020 773B subs r3, r3, #119 + 1476 0022 6362 str r3, [r4, #36] + 1477 .LVL174: + 1478 .LBE213: + 1479 .LBE212: + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1480 .loc 1 331 0 + 1481 0024 2000 movs r0, r4 + 1482 .LVL175: + 1483 0026 FFF7FEFF bl LL_RTC_EnterInitMode + 1484 .LVL176: + 1485 002a 0028 cmp r0, #0 + 1486 002c 17D0 beq .L70 + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + ARM GAS /tmp/ccnIlCuV.s page 108 + + + 1487 .loc 1 334 0 + 1488 002e 002E cmp r6, #0 + 1489 0030 21D0 beq .L71 + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + 1490 .loc 1 336 0 + 1491 0032 2A68 ldr r2, [r5] + 1492 0034 2879 ldrb r0, [r5, #4] + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1493 .loc 1 337 0 + 1494 0036 6979 ldrb r1, [r5, #5] + 1495 0038 AB79 ldrb r3, [r5, #6] + 1496 .LVL177: + 1497 .LBB214: + 1498 .LBB215: +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_ + 1499 .loc 2 1271 0 + 1500 003a 0004 lsls r0, r0, #16 + 1501 .LVL178: +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) + 1502 .loc 2 1270 0 + 1503 003c 0243 orrs r2, r0 + 1504 .LVL179: +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_ + 1505 .loc 2 1272 0 + 1506 003e 0902 lsls r1, r1, #8 + 1507 .LVL180: +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_ + 1508 .loc 2 1271 0 + 1509 0040 0A43 orrs r2, r1 +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) + 1510 .loc 2 1270 0 + 1511 0042 1343 orrs r3, r2 + 1512 .LVL181: +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1513 .loc 2 1274 0 + 1514 0044 2268 ldr r2, [r4] + 1515 0046 2949 ldr r1, .L75 + 1516 0048 0A40 ands r2, r1 + 1517 004a 1343 orrs r3, r2 + 1518 .LVL182: + 1519 004c 2360 str r3, [r4] + 1520 .LVL183: + 1521 .L72: + 1522 .LBE215: + 1523 .LBE214: + 1524 .LBB216: + 1525 .LBB217: + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1526 .loc 2 908 0 + 1527 004e 284B ldr r3, .L75+4 + 1528 0050 8122 movs r2, #129 + 1529 0052 5242 rsbs r2, r2, #0 + 1530 0054 DA60 str r2, [r3, #12] + 1531 .LVL184: + 1532 .LBE217: + 1533 .LBE216: + 1534 .LBB218: + ARM GAS /tmp/ccnIlCuV.s page 109 + + + 1535 .LBB219: + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1536 .loc 2 970 0 + 1537 0056 A368 ldr r3, [r4, #8] + 1538 .LVL185: + 1539 .LBE219: + 1540 .LBE218: + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1541 .loc 1 350 0 + 1542 0058 9B06 lsls r3, r3, #26 + 1543 005a 43D5 bpl .L74 + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1544 .loc 1 356 0 + 1545 005c 0120 movs r0, #1 + 1546 .LVL186: + 1547 .L70: + 1548 .LBB220: + 1549 .LBB221: +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1550 .loc 2 1053 0 + 1551 005e FF23 movs r3, #255 + 1552 0060 6362 str r3, [r4, #36] + 1553 .LVL187: + 1554 .LBE221: + 1555 .LBE220: + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1556 .loc 1 363 0 + 1557 @ sp needed + 1558 .LVL188: + 1559 0062 0CBC pop {r2, r3} + 1560 0064 9046 mov r8, r2 + 1561 0066 9946 mov r9, r3 + 1562 0068 F8BD pop {r3, r4, r5, r6, r7, pc} + 1563 .LVL189: + 1564 .L68: + 1565 .LBB222: + 1566 .LBB223: + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1567 .loc 2 820 0 + 1568 006a 8368 ldr r3, [r0, #8] + 1569 .LVL190: + 1570 .LBE223: + 1571 .LBE222: + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1572 .loc 1 313 0 + 1573 006c 5B06 lsls r3, r3, #25 + 1574 006e D5D4 bmi .L69 + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + 1575 .loc 1 320 0 + 1576 0070 0023 movs r3, #0 + 1577 0072 1360 str r3, [r2] + 1578 0074 D2E7 b .L69 + 1579 .LVL191: + 1580 .L71: + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + 1581 .loc 1 341 0 + 1582 0076 2B68 ldr r3, [r5] + ARM GAS /tmp/ccnIlCuV.s page 110 + + + 1583 0078 9946 mov r9, r3 + 1584 007a 2E79 ldrb r6, [r5, #4] + 1585 .LVL192: + 1586 007c 0A21 movs r1, #10 + 1587 007e 3000 movs r0, r6 + 1588 0080 FFF7FEFF bl __aeabi_uidiv + 1589 .LVL193: + 1590 0084 0001 lsls r0, r0, #4 + 1591 0086 C7B2 uxtb r7, r0 + 1592 0088 0A21 movs r1, #10 + 1593 008a 3000 movs r0, r6 + 1594 008c FFF7FEFF bl __aeabi_uidivmod + 1595 .LVL194: + 1596 0090 0F43 orrs r7, r1 + 1597 0092 FBB2 uxtb r3, r7 + 1598 0094 9846 mov r8, r3 + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + 1599 .loc 1 342 0 + 1600 0096 6F79 ldrb r7, [r5, #5] + 1601 0098 0A21 movs r1, #10 + 1602 009a 3800 movs r0, r7 + 1603 009c FFF7FEFF bl __aeabi_uidiv + 1604 .LVL195: + 1605 00a0 0001 lsls r0, r0, #4 + 1606 00a2 C6B2 uxtb r6, r0 + 1607 00a4 0A21 movs r1, #10 + 1608 00a6 3800 movs r0, r7 + 1609 00a8 FFF7FEFF bl __aeabi_uidivmod + 1610 .LVL196: + 1611 00ac 0E43 orrs r6, r1 + 1612 00ae F6B2 uxtb r6, r6 + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1613 .loc 1 343 0 + 1614 00b0 AF79 ldrb r7, [r5, #6] + 1615 00b2 0A21 movs r1, #10 + 1616 00b4 3800 movs r0, r7 + 1617 00b6 FFF7FEFF bl __aeabi_uidiv + 1618 .LVL197: + 1619 00ba 0001 lsls r0, r0, #4 + 1620 00bc C5B2 uxtb r5, r0 + 1621 .LVL198: + 1622 00be 0A21 movs r1, #10 + 1623 00c0 3800 movs r0, r7 + 1624 00c2 FFF7FEFF bl __aeabi_uidivmod + 1625 .LVL199: + 1626 00c6 0D43 orrs r5, r1 + 1627 00c8 EDB2 uxtb r5, r5 + 1628 .LVL200: + 1629 .LBB224: + 1630 .LBB225: +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_ + 1631 .loc 2 1271 0 + 1632 00ca 4346 mov r3, r8 + 1633 00cc 1B04 lsls r3, r3, #16 +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) + 1634 .loc 2 1270 0 + 1635 00ce 4A46 mov r2, r9 + ARM GAS /tmp/ccnIlCuV.s page 111 + + + 1636 00d0 1343 orrs r3, r2 +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_ + 1637 .loc 2 1272 0 + 1638 00d2 3602 lsls r6, r6, #8 + 1639 .LVL201: +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_ + 1640 .loc 2 1271 0 + 1641 00d4 1E43 orrs r6, r3 +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) + 1642 .loc 2 1270 0 + 1643 00d6 3543 orrs r5, r6 + 1644 .LVL202: +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1645 .loc 2 1274 0 + 1646 00d8 2168 ldr r1, [r4] + 1647 00da 044B ldr r3, .L75 + 1648 00dc 1940 ands r1, r3 + 1649 00de 0D43 orrs r5, r1 + 1650 .LVL203: + 1651 00e0 2560 str r5, [r4] + 1652 00e2 B4E7 b .L72 + 1653 .LVL204: + 1654 .L74: + 1655 .LBE225: + 1656 .LBE224: + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1657 .loc 1 352 0 + 1658 00e4 2000 movs r0, r4 + 1659 00e6 FFF7FEFF bl LL_RTC_WaitForSynchro + 1660 .LVL205: + 1661 00ea B8E7 b .L70 + 1662 .L76: + 1663 .align 2 + 1664 .L75: + 1665 00ec 808080FF .word -8355712 + 1666 00f0 00280040 .word 1073752064 + 1667 .cfi_endproc + 1668 .LFE261: + 1670 .section .text.LL_RTC_DATE_Init,"ax",%progbits + 1671 .align 1 + 1672 .global LL_RTC_DATE_Init + 1673 .syntax unified + 1674 .code 16 + 1675 .thumb_func + 1676 .fpu softvfp + 1678 LL_RTC_DATE_Init: + 1679 .LFB263: + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** ErrorStatus status = ERROR; + 1680 .loc 1 392 0 + 1681 .cfi_startproc + 1682 @ args = 0, pretend = 0, frame = 0 + 1683 @ frame_needed = 0, uses_anonymous_args = 0 + 1684 .LVL206: + 1685 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1686 .LCFI10: + 1687 .cfi_def_cfa_offset 24 + 1688 .cfi_offset 3, -24 + ARM GAS /tmp/ccnIlCuV.s page 112 + + + 1689 .cfi_offset 4, -20 + 1690 .cfi_offset 5, -16 + 1691 .cfi_offset 6, -12 + 1692 .cfi_offset 7, -8 + 1693 .cfi_offset 14, -4 + 1694 0002 CE46 mov lr, r9 + 1695 0004 4746 mov r7, r8 + 1696 0006 80B5 push {r7, lr} + 1697 .LCFI11: + 1698 .cfi_def_cfa_offset 32 + 1699 .cfi_offset 8, -32 + 1700 .cfi_offset 9, -28 + 1701 0008 0400 movs r4, r0 + 1702 000a 0E00 movs r6, r1 + 1703 000c 1500 movs r5, r2 + 1704 .LVL207: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1705 .loc 1 399 0 + 1706 000e 0029 cmp r1, #0 + 1707 0010 06D1 bne .L78 + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1708 .loc 1 399 0 is_stmt 0 discriminator 1 + 1709 0012 5378 ldrb r3, [r2, #1] + 1710 0014 DA06 lsls r2, r3, #27 + 1711 0016 03D5 bpl .L78 + 1712 .LVL208: + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1713 .loc 1 401 0 is_stmt 1 + 1714 0018 1022 movs r2, #16 + 1715 001a 9343 bics r3, r2 + 1716 001c 0A33 adds r3, r3, #10 + 1717 001e 6B70 strb r3, [r5, #1] + 1718 .L78: + 1719 .LVL209: + 1720 .LBB226: + 1721 .LBB227: +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 1722 .loc 2 1064 0 + 1723 0020 CA23 movs r3, #202 + 1724 0022 6362 str r3, [r4, #36] +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1725 .loc 2 1065 0 + 1726 0024 773B subs r3, r3, #119 + 1727 0026 6362 str r3, [r4, #36] + 1728 .LVL210: + 1729 .LBE227: + 1730 .LBE226: + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1731 .loc 1 421 0 + 1732 0028 2000 movs r0, r4 + 1733 .LVL211: + 1734 002a FFF7FEFF bl LL_RTC_EnterInitMode + 1735 .LVL212: + 1736 002e 0028 cmp r0, #0 + 1737 0030 18D0 beq .L79 + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1738 .loc 1 424 0 + ARM GAS /tmp/ccnIlCuV.s page 113 + + + 1739 0032 002E cmp r6, #0 + 1740 0034 1CD0 beq .L80 + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1741 .loc 1 426 0 + 1742 0036 2B78 ldrb r3, [r5] + 1743 0038 AA78 ldrb r2, [r5, #2] + 1744 003a 6978 ldrb r1, [r5, #1] + 1745 003c E878 ldrb r0, [r5, #3] + 1746 .LVL213: + 1747 .LBB228: + 1748 .LBB229: +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1749 .loc 2 1604 0 + 1750 003e 5B03 lsls r3, r3, #13 + 1751 .LVL214: +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) + 1752 .loc 2 1605 0 + 1753 0040 0004 lsls r0, r0, #16 + 1754 .LVL215: +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1755 .loc 2 1604 0 + 1756 0042 0343 orrs r3, r0 +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)); + 1757 .loc 2 1606 0 + 1758 0044 0902 lsls r1, r1, #8 + 1759 .LVL216: +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) + 1760 .loc 2 1605 0 + 1761 0046 0B43 orrs r3, r1 +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1762 .loc 2 1604 0 + 1763 0048 1343 orrs r3, r2 + 1764 .LVL217: +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1765 .loc 2 1609 0 + 1766 004a 6268 ldr r2, [r4, #4] + 1767 .LVL218: + 1768 004c 2749 ldr r1, .L84 + 1769 004e 0A40 ands r2, r1 + 1770 0050 1343 orrs r3, r2 + 1771 .LVL219: + 1772 0052 6360 str r3, [r4, #4] + 1773 .LVL220: + 1774 .L81: + 1775 .LBE229: + 1776 .LBE228: + 1777 .LBB230: + 1778 .LBB231: + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1779 .loc 2 908 0 + 1780 0054 264B ldr r3, .L84+4 + 1781 0056 8122 movs r2, #129 + 1782 0058 5242 rsbs r2, r2, #0 + 1783 005a DA60 str r2, [r3, #12] + 1784 .LVL221: + 1785 .LBE231: + 1786 .LBE230: + ARM GAS /tmp/ccnIlCuV.s page 114 + + + 1787 .LBB232: + 1788 .LBB233: + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1789 .loc 2 970 0 + 1790 005c A368 ldr r3, [r4, #8] + 1791 .LVL222: + 1792 .LBE233: + 1793 .LBE232: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** { + 1794 .loc 1 438 0 + 1795 005e 9B06 lsls r3, r3, #26 + 1796 0060 40D5 bpl .L83 + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1797 .loc 1 444 0 + 1798 0062 0120 movs r0, #1 + 1799 .LVL223: + 1800 .L79: + 1801 .LBB234: + 1802 .LBB235: +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1803 .loc 2 1053 0 + 1804 0064 FF23 movs r3, #255 + 1805 0066 6362 str r3, [r4, #36] + 1806 .LVL224: + 1807 .LBE235: + 1808 .LBE234: + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** + 1809 .loc 1 451 0 + 1810 @ sp needed + 1811 .LVL225: + 1812 0068 0CBC pop {r2, r3} + 1813 006a 9046 mov r8, r2 + 1814 006c 9946 mov r9, r3 + 1815 006e F8BD pop {r3, r4, r5, r6, r7, pc} + 1816 .LVL226: + 1817 .L80: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD( + 1818 .loc 1 430 0 + 1819 0070 2B78 ldrb r3, [r5] + 1820 0072 9946 mov r9, r3 + 1821 0074 AF78 ldrb r7, [r5, #2] + 1822 0076 0A21 movs r1, #10 + 1823 0078 3800 movs r0, r7 + 1824 007a FFF7FEFF bl __aeabi_uidiv + 1825 .LVL227: + 1826 007e 0001 lsls r0, r0, #4 + 1827 0080 C6B2 uxtb r6, r0 + 1828 .LVL228: + 1829 0082 0A21 movs r1, #10 + 1830 0084 3800 movs r0, r7 + 1831 0086 FFF7FEFF bl __aeabi_uidivmod + 1832 .LVL229: + 1833 008a 0E43 orrs r6, r1 + 1834 008c F6B2 uxtb r6, r6 + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1835 .loc 1 431 0 + 1836 008e 6F78 ldrb r7, [r5, #1] + ARM GAS /tmp/ccnIlCuV.s page 115 + + + 1837 0090 0A21 movs r1, #10 + 1838 0092 3800 movs r0, r7 + 1839 0094 FFF7FEFF bl __aeabi_uidiv + 1840 .LVL230: + 1841 0098 0001 lsls r0, r0, #4 + 1842 009a C3B2 uxtb r3, r0 + 1843 009c 9846 mov r8, r3 + 1844 009e 0A21 movs r1, #10 + 1845 00a0 3800 movs r0, r7 + 1846 00a2 FFF7FEFF bl __aeabi_uidivmod + 1847 .LVL231: + 1848 00a6 4346 mov r3, r8 + 1849 00a8 1943 orrs r1, r3 + 1850 00aa CFB2 uxtb r7, r1 + 1851 00ac ED78 ldrb r5, [r5, #3] + 1852 .LVL232: + 1853 00ae 0A21 movs r1, #10 + 1854 00b0 2800 movs r0, r5 + 1855 00b2 FFF7FEFF bl __aeabi_uidiv + 1856 .LVL233: + 1857 00b6 0001 lsls r0, r0, #4 + 1858 00b8 C3B2 uxtb r3, r0 + 1859 00ba 9846 mov r8, r3 + 1860 00bc 0A21 movs r1, #10 + 1861 00be 2800 movs r0, r5 + 1862 00c0 FFF7FEFF bl __aeabi_uidivmod + 1863 .LVL234: + 1864 00c4 4346 mov r3, r8 + 1865 00c6 1943 orrs r1, r3 + 1866 00c8 C9B2 uxtb r1, r1 + 1867 .LVL235: + 1868 .LBB236: + 1869 .LBB237: +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1870 .loc 2 1604 0 + 1871 00ca 4B46 mov r3, r9 + 1872 00cc 5B03 lsls r3, r3, #13 +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) + 1873 .loc 2 1605 0 + 1874 00ce 0904 lsls r1, r1, #16 + 1875 .LVL236: +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1876 .loc 2 1604 0 + 1877 00d0 1943 orrs r1, r3 +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)); + 1878 .loc 2 1606 0 + 1879 00d2 3F02 lsls r7, r7, #8 + 1880 .LVL237: +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) + 1881 .loc 2 1605 0 + 1882 00d4 0F43 orrs r7, r1 +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) + 1883 .loc 2 1604 0 + 1884 00d6 3E43 orrs r6, r7 + 1885 .LVL238: +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h **** } + 1886 .loc 2 1609 0 + ARM GAS /tmp/ccnIlCuV.s page 116 + + + 1887 00d8 6768 ldr r7, [r4, #4] + 1888 00da 0449 ldr r1, .L84 + 1889 00dc 0F40 ands r7, r1 + 1890 00de 3E43 orrs r6, r7 + 1891 .LVL239: + 1892 00e0 6660 str r6, [r4, #4] + 1893 00e2 B7E7 b .L81 + 1894 .LVL240: + 1895 .L83: + 1896 .LBE237: + 1897 .LBE236: + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c **** } + 1898 .loc 1 440 0 + 1899 00e4 2000 movs r0, r4 + 1900 00e6 FFF7FEFF bl LL_RTC_WaitForSynchro + 1901 .LVL241: + 1902 00ea BBE7 b .L79 + 1903 .L85: + 1904 .align 2 + 1905 .L84: + 1906 00ec C00000FF .word -16777024 + 1907 00f0 00280040 .word 1073752064 + 1908 .cfi_endproc + 1909 .LFE263: + 1911 .text + 1912 .Letext0: + 1913 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1914 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1915 .file 6 "Drivers/CMSIS/Include/core_cm0plus.h" + 1916 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1917 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1918 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1919 .file 10 "/usr/arm-none-eabi/include/sys/lock.h" + 1920 .file 11 "/usr/arm-none-eabi/include/sys/_types.h" + 1921 .file 12 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1922 .file 13 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccnIlCuV.s page 117 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_rtc.c + /tmp/ccnIlCuV.s:16 .text.LL_RTC_StructInit:0000000000000000 $t + /tmp/ccnIlCuV.s:23 .text.LL_RTC_StructInit:0000000000000000 LL_RTC_StructInit + /tmp/ccnIlCuV.s:48 .text.LL_RTC_TIME_StructInit:0000000000000000 $t + /tmp/ccnIlCuV.s:55 .text.LL_RTC_TIME_StructInit:0000000000000000 LL_RTC_TIME_StructInit + /tmp/ccnIlCuV.s:79 .text.LL_RTC_DATE_StructInit:0000000000000000 $t + /tmp/ccnIlCuV.s:86 .text.LL_RTC_DATE_StructInit:0000000000000000 LL_RTC_DATE_StructInit + /tmp/ccnIlCuV.s:113 .text.LL_RTC_ALMA_Init:0000000000000000 $t + /tmp/ccnIlCuV.s:120 .text.LL_RTC_ALMA_Init:0000000000000000 LL_RTC_ALMA_Init + /tmp/ccnIlCuV.s:440 .text.LL_RTC_ALMA_Init:0000000000000144 $d + /tmp/ccnIlCuV.s:451 .text.LL_RTC_ALMB_Init:0000000000000000 $t + /tmp/ccnIlCuV.s:458 .text.LL_RTC_ALMB_Init:0000000000000000 LL_RTC_ALMB_Init + /tmp/ccnIlCuV.s:780 .text.LL_RTC_ALMB_Init:0000000000000148 $d + /tmp/ccnIlCuV.s:792 .text.LL_RTC_ALMA_StructInit:0000000000000000 $t + /tmp/ccnIlCuV.s:799 .text.LL_RTC_ALMA_StructInit:0000000000000000 LL_RTC_ALMA_StructInit + /tmp/ccnIlCuV.s:830 .text.LL_RTC_ALMB_StructInit:0000000000000000 $t + /tmp/ccnIlCuV.s:837 .text.LL_RTC_ALMB_StructInit:0000000000000000 LL_RTC_ALMB_StructInit + /tmp/ccnIlCuV.s:868 .text.LL_RTC_EnterInitMode:0000000000000000 $t + /tmp/ccnIlCuV.s:875 .text.LL_RTC_EnterInitMode:0000000000000000 LL_RTC_EnterInitMode + /tmp/ccnIlCuV.s:985 .text.LL_RTC_EnterInitMode:0000000000000054 $d + /tmp/ccnIlCuV.s:990 .text.LL_RTC_Init:0000000000000000 $t + /tmp/ccnIlCuV.s:997 .text.LL_RTC_Init:0000000000000000 LL_RTC_Init + /tmp/ccnIlCuV.s:1100 .text.LL_RTC_Init:000000000000004c $d + /tmp/ccnIlCuV.s:1105 .text.LL_RTC_ExitInitMode:0000000000000000 $t + /tmp/ccnIlCuV.s:1112 .text.LL_RTC_ExitInitMode:0000000000000000 LL_RTC_ExitInitMode + /tmp/ccnIlCuV.s:1138 .text.LL_RTC_WaitForSynchro:0000000000000000 $t + /tmp/ccnIlCuV.s:1145 .text.LL_RTC_WaitForSynchro:0000000000000000 LL_RTC_WaitForSynchro + /tmp/ccnIlCuV.s:1308 .text.LL_RTC_WaitForSynchro:0000000000000094 $d + /tmp/ccnIlCuV.s:1313 .text.LL_RTC_DeInit:0000000000000000 $t + /tmp/ccnIlCuV.s:1320 .text.LL_RTC_DeInit:0000000000000000 LL_RTC_DeInit + /tmp/ccnIlCuV.s:1409 .text.LL_RTC_DeInit:000000000000004c $d + /tmp/ccnIlCuV.s:1416 .text.LL_RTC_TIME_Init:0000000000000000 $t + /tmp/ccnIlCuV.s:1423 .text.LL_RTC_TIME_Init:0000000000000000 LL_RTC_TIME_Init + /tmp/ccnIlCuV.s:1665 .text.LL_RTC_TIME_Init:00000000000000ec $d + /tmp/ccnIlCuV.s:1671 .text.LL_RTC_DATE_Init:0000000000000000 $t + /tmp/ccnIlCuV.s:1678 .text.LL_RTC_DATE_Init:0000000000000000 LL_RTC_DATE_Init + /tmp/ccnIlCuV.s:1906 .text.LL_RTC_DATE_Init:00000000000000ec $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +__aeabi_uidivmod diff --git a/build/stm32l0xx_ll_spi.d b/build/stm32l0xx_ll_spi.d new file mode 100644 index 0000000..007d775 --- /dev/null +++ b/build/stm32l0xx_ll_spi.d @@ -0,0 +1,112 @@ +build/stm32l0xx_ll_spi.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: diff --git a/build/stm32l0xx_ll_spi.lst b/build/stm32l0xx_ll_spi.lst new file mode 100644 index 0000000..1a15a6a --- /dev/null +++ b/build/stm32l0xx_ll_spi.lst @@ -0,0 +1,3709 @@ +ARM GAS /tmp/ccIphHaE.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_spi.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_SPI_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_SPI_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_SPI_DeInit: + 24 .LFB312: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @file stm32l0xx_ll_spi.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief SPI LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ****************************************************************************** + ARM GAS /tmp/ccIphHaE.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #include "stm32l0xx_ll_spi.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #include "stm32l0xx_ll_rcc.h" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #ifdef USE_FULL_ASSERT + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #include "stm32_assert.h" + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #else + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define assert_param(expr) ((void)0U) + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #endif + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup STM32L0xx_LL_Driver + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined (SPI1) || defined (SPI2) + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup SPI_LL + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Constants SPI Private Constants + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* SPI registers Masks */ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_CR1_BIDIMODE) + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Macros SPI Private Macros + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ + ARM GAS /tmp/ccIphHaE.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_MSB_FIRST)) + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup SPI_LL_Exported_Functions + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup SPI_LL_EF_Init + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief De-initialize the SPI registers to their default reset values. + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPIx SPI Instance + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - SUCCESS: SPI registers are de-initialized + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ERROR: SPI registers are not de-initialized + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 26 .loc 1 140 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus status = ERROR; + ARM GAS /tmp/ccIphHaE.s page 4 + + + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the parameters */ + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined(SPI1) + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (SPIx == SPI1) + 32 .loc 1 147 0 + 33 0000 104B ldr r3, .L7 + 34 0002 9842 cmp r0, r3 + 35 0004 05D0 beq .L5 + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus status = ERROR; + 36 .loc 1 141 0 + 37 0006 0023 movs r3, #0 + 38 .LVL1: + 39 .L2: + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Force reset of SPI clock */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Release reset of SPI clock */ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** status = SUCCESS; + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #endif /* SPI1 */ + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined(SPI2) + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (SPIx == SPI2) + 40 .loc 1 159 0 + 41 0008 0F4A ldr r2, .L7+4 + 42 000a 9042 cmp r0, r2 + 43 000c 0DD0 beq .L6 + 44 .LVL2: + 45 .L3: + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Force reset of SPI clock */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Release reset of SPI clock */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** status = SUCCESS; + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #endif /* SPI2 */ + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** return status; + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 46 .loc 1 172 0 + 47 000e 1800 movs r0, r3 + 48 .LVL3: + 49 @ sp needed + 50 0010 7047 bx lr + 51 .LVL4: + 52 .L5: + 53 .LBB26: + 54 .LBB27: + 55 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/ccIphHaE.s page 5 + + + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + ARM GAS /tmp/ccIphHaE.s page 6 + + + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + ARM GAS /tmp/ccIphHaE.s page 7 + + + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + ARM GAS /tmp/ccIphHaE.s page 8 + + + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccIphHaE.s page 9 + + + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + ARM GAS /tmp/ccIphHaE.s page 10 + + + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/ccIphHaE.s page 11 + + + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + ARM GAS /tmp/ccIphHaE.s page 12 + + + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/ccIphHaE.s page 13 + + + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/ccIphHaE.s page 14 + + + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccIphHaE.s page 15 + + + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccIphHaE.s page 16 + + + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/ccIphHaE.s page 17 + + + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1SMENR, Periphs); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccIphHaE.s page 18 + + + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1SMENR, Periphs); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/ccIphHaE.s page 19 + + + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + ARM GAS /tmp/ccIphHaE.s page 20 + + + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB2 peripherals reset. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 56 .loc 2 891 0 + 57 0012 0E4B ldr r3, .L7+8 + 58 0014 596A ldr r1, [r3, #36] + 59 0016 8022 movs r2, #128 + 60 0018 5201 lsls r2, r2, #5 + 61 001a 0A43 orrs r2, r1 + 62 001c 5A62 str r2, [r3, #36] + 63 .LVL5: + 64 .LBE27: + 65 .LBE26: + 66 .LBB28: + 67 .LBB29: + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB2 peripherals reset. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + ARM GAS /tmp/ccIphHaE.s page 21 + + + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 68 .loc 2 918 0 + 69 001e 5A6A ldr r2, [r3, #36] + 70 0020 0B49 ldr r1, .L7+12 + 71 0022 0A40 ands r2, r1 + 72 0024 5A62 str r2, [r3, #36] + 73 .LVL6: + 74 .LBE29: + 75 .LBE28: + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 76 .loc 1 155 0 + 77 0026 0123 movs r3, #1 + 78 0028 EEE7 b .L2 + 79 .LVL7: + 80 .L6: + 81 .LBB30: + 82 .LBB31: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 83 .loc 2 613 0 + 84 002a 084B ldr r3, .L7+8 + 85 .LVL8: + 86 002c 996A ldr r1, [r3, #40] + 87 002e 8022 movs r2, #128 + 88 0030 D201 lsls r2, r2, #7 + 89 0032 0A43 orrs r2, r1 + 90 0034 9A62 str r2, [r3, #40] + 91 .LVL9: + 92 .LBE31: + 93 .LBE30: + 94 .LBB32: + 95 .LBB33: + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 96 .loc 2 664 0 + 97 0036 9A6A ldr r2, [r3, #40] + 98 0038 0649 ldr r1, .L7+16 + 99 003a 0A40 ands r2, r1 + 100 003c 9A62 str r2, [r3, #40] + 101 .LVL10: + 102 .LBE33: + 103 .LBE32: + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + ARM GAS /tmp/ccIphHaE.s page 22 + + + 104 .loc 1 167 0 + 105 003e 0123 movs r3, #1 + 106 0040 E5E7 b .L3 + 107 .L8: + 108 0042 C046 .align 2 + 109 .L7: + 110 0044 00300140 .word 1073819648 + 111 0048 00380040 .word 1073756160 + 112 004c 00100240 .word 1073876992 + 113 0050 FFEFFFFF .word -4097 + 114 0054 FFBFFFFF .word -16385 + 115 .cfi_endproc + 116 .LFE312: + 118 .section .text.LL_SPI_Init,"ax",%progbits + 119 .align 1 + 120 .global LL_SPI_Init + 121 .syntax unified + 122 .code 16 + 123 .thumb_func + 124 .fpu softvfp + 126 LL_SPI_Init: + 127 .LFB313: + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @note As some bits in SPI configuration registers can only be written when the SPI is disable + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPIx SPI Instance + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 128 .loc 1 183 0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 .LVL11: + 133 0000 10B5 push {r4, lr} + 134 .LCFI0: + 135 .cfi_def_cfa_offset 8 + 136 .cfi_offset 4, -8 + 137 .cfi_offset 14, -4 + 138 .LVL12: + 139 .LBB34: + 140 .LBB35: + 141 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @file stm32l0xx_ll_spi.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Header file of SPI LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * + ARM GAS /tmp/ccIphHaE.s page 23 + + + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #ifndef __STM32L0xx_LL_SPI_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define __STM32L0xx_LL_SPI_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL SPI + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + ARM GAS /tmp/ccIphHaE.s page 24 + + + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief SPI Init structures definition + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** typedef struct + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** @note The communication clock is derived from the master c + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } LL_SPI_InitTypeDef; + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + ARM GAS /tmp/ccIphHaE.s page 25 + + + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as de + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + ARM GAS /tmp/ccIphHaE.s page 26 + + + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< Baud + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/recei + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mo + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in I + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O + ARM GAS /tmp/ccIphHaE.s page 27 + + + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /*!< Data length for S + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for S + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation d + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation e + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Write a value in SPI register + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __REG__ Register to be written + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Read a value in SPI register + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __REG__ Register to be read + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Register value + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + ARM GAS /tmp/ccIphHaE.s page 28 + + + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable SPI peripheral + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable SPI peripheral + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); + 142 .loc 3 340 0 + 143 0002 0368 ldr r3, [r0] + 144 .LVL13: + 145 .LBE35: + 146 .LBE34: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus status = ERROR; + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the SPI Instance SPIx*/ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the SPI parameters from SPI_InitStruct*/ + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + ARM GAS /tmp/ccIphHaE.s page 29 + + + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) + 147 .loc 1 200 0 + 148 0004 5B06 lsls r3, r3, #25 + 149 0006 28D4 bmi .L11 + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*---------------------------- SPIx CR1 Configuration ------------------------ + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Configure SPIx CR1 with parameters: + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - Master/Slave Mode: SPI_CR1_MSTR bit + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - DataWidth: SPI_CR1_DFF bit + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ClockPolarity: SPI_CR1_CPOL bit + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ClockPhase: SPI_CR1_CPHA bit + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - NSS management: SPI_CR1_SSM bit + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - BaudRate prescaler: SPI_CR1_BR[2:0] bits + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - BitOrder: SPI_CR1_LSBFIRST bit + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - CRCCalculation: SPI_CR1_CRCEN bit + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** MODIFY_REG(SPIx->CR1, + 150 .loc 1 214 0 + 151 0008 0368 ldr r3, [r0] + 152 000a 174A ldr r2, .L14 + 153 000c 1A40 ands r2, r3 + 154 000e 0B68 ldr r3, [r1] + 155 0010 4C68 ldr r4, [r1, #4] + 156 0012 2343 orrs r3, r4 + 157 0014 8C68 ldr r4, [r1, #8] + 158 0016 2343 orrs r3, r4 + 159 0018 CC68 ldr r4, [r1, #12] + 160 001a 2343 orrs r3, r4 + 161 001c 0C69 ldr r4, [r1, #16] + 162 001e 2343 orrs r3, r4 + 163 0020 4C69 ldr r4, [r1, #20] + 164 0022 2343 orrs r3, r4 + 165 0024 8C69 ldr r4, [r1, #24] + 166 0026 2343 orrs r3, r4 + 167 0028 CC69 ldr r4, [r1, #28] + 168 002a 2343 orrs r3, r4 + 169 002c 0C6A ldr r4, [r1, #32] + 170 002e 2343 orrs r3, r4 + 171 0030 1343 orrs r3, r2 + 172 0032 0360 str r3, [r0] + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_CR1_CLEAR_MASK, + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*---------------------------- SPIx CR2 Configuration ------------------------ + ARM GAS /tmp/ccIphHaE.s page 30 + + + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Configure SPIx CR2 with parameters: + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - NSS management: SSOE bit + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U)); + 173 .loc 1 225 0 + 174 0034 4368 ldr r3, [r0, #4] + 175 0036 0422 movs r2, #4 + 176 0038 9343 bics r3, r2 + 177 003a CA8A ldrh r2, [r1, #22] + 178 003c 1343 orrs r3, r2 + 179 003e 4360 str r3, [r0, #4] + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*---------------------------- SPIx CRCPR Configuration ---------------------- + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Configure SPIx CRCPR with parameters: + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - CRCPoly: CRCPOLY[15:0] bits + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + 180 .loc 1 231 0 + 181 0040 8023 movs r3, #128 + 182 0042 9B01 lsls r3, r3, #6 + 183 0044 0A6A ldr r2, [r1, #32] + 184 0046 9A42 cmp r2, r3 + 185 0048 01D0 beq .L13 + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** status = SUCCESS; + 186 .loc 1 236 0 + 187 004a 0121 movs r1, #1 + 188 .LVL14: + 189 004c 06E0 b .L10 + 190 .LVL15: + 191 .L13: + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 192 .loc 1 234 0 + 193 004e 4B6A ldr r3, [r1, #36] + 194 .LVL16: + 195 0050 1B04 lsls r3, r3, #16 + 196 .LVL17: + 197 0052 1B0C lsrs r3, r3, #16 + 198 .LBB36: + 199 .LBB37: + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) + ARM GAS /tmp/ccIphHaE.s page 31 + + + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set serial protocol used + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get serial protocol used + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set clock phase + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + ARM GAS /tmp/ccIphHaE.s page 32 + + + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get clock phase + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set clock polarity + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get clock polarity + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set baud rate prescaler + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + ARM GAS /tmp/ccIphHaE.s page 33 + + + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get baud rate prescaler + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set transfer bit order + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get transfer bit order + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + ARM GAS /tmp/ccIphHaE.s page 34 + + + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set transfer direction mode + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get transfer direction mode + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set frame data width + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 DFF LL_SPI_SetDataWidth + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth); + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get frame data width + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 DFF LL_SPI_GetDataWidth + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccIphHaE.s page 35 + + + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable CRC + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable CRC + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if CRC is enabled + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + ARM GAS /tmp/ccIphHaE.s page 36 + + + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set polynomial for CRC calculation + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); + 200 .loc 3 656 0 + 201 0054 0361 str r3, [r0, #16] + 202 .LVL18: + 203 .LBE37: + 204 .LBE36: + 205 .loc 1 236 0 + 206 0056 0121 movs r1, #1 + 207 .LVL19: + 208 0058 00E0 b .L10 + 209 .LVL20: + 210 .L11: + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 211 .loc 1 184 0 + 212 005a 0021 movs r1, #0 + 213 .LVL21: + 214 .L10: + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined (SPI_I2S_SUPPORT) + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 215 .loc 1 241 0 + 216 005c C369 ldr r3, [r0, #28] + 217 005e 034A ldr r2, .L14+4 + 218 0060 1340 ands r3, r2 + 219 0062 C361 str r3, [r0, #28] + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #endif /* SPI_I2S_SUPPORT */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** return status; + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 220 .loc 1 244 0 + 221 0064 0800 movs r0, r1 + 222 .LVL22: + 223 @ sp needed + 224 0066 10BD pop {r4, pc} + 225 .L15: + 226 .align 2 + 227 .L14: + 228 0068 4000FFFF .word -65472 + 229 006c FFF7FFFF .word -2049 + 230 .cfi_endproc + ARM GAS /tmp/ccIphHaE.s page 37 + + + 231 .LFE313: + 233 .section .text.LL_SPI_StructInit,"ax",%progbits + 234 .align 1 + 235 .global LL_SPI_StructInit + 236 .syntax unified + 237 .code 16 + 238 .thumb_func + 239 .fpu softvfp + 241 LL_SPI_StructInit: + 242 .LFB314: + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * whose fields will be set to default values. + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval None + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 243 .loc 1 253 0 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 0 + 246 @ frame_needed = 0, uses_anonymous_args = 0 + 247 @ link register save eliminated. + 248 .LVL23: + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Set SPI_InitStruct fields to default values */ + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + 249 .loc 1 255 0 + 250 0000 0023 movs r3, #0 + 251 0002 0360 str r3, [r0] + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + 252 .loc 1 256 0 + 253 0004 4360 str r3, [r0, #4] + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + 254 .loc 1 257 0 + 255 0006 8360 str r3, [r0, #8] + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + 256 .loc 1 258 0 + 257 0008 C360 str r3, [r0, #12] + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + 258 .loc 1 259 0 + 259 000a 0361 str r3, [r0, #16] + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + 260 .loc 1 260 0 + 261 000c 4361 str r3, [r0, #20] + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + 262 .loc 1 261 0 + 263 000e 8361 str r3, [r0, #24] + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + 264 .loc 1 262 0 + 265 0010 C361 str r3, [r0, #28] + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 266 .loc 1 263 0 + 267 0012 0362 str r3, [r0, #32] + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_InitStruct->CRCPoly = 7U; + 268 .loc 1 264 0 + 269 0014 0733 adds r3, r3, #7 + ARM GAS /tmp/ccIphHaE.s page 38 + + + 270 0016 4362 str r3, [r0, #36] + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 271 .loc 1 265 0 + 272 @ sp needed + 273 0018 7047 bx lr + 274 .cfi_endproc + 275 .LFE314: + 277 .section .text.LL_I2S_DeInit,"ax",%progbits + 278 .align 1 + 279 .global LL_I2S_DeInit + 280 .syntax unified + 281 .code 16 + 282 .thumb_func + 283 .fpu softvfp + 285 LL_I2S_DeInit: + 286 .LFB315: + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #if defined(SPI_I2S_SUPPORT) + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup I2S_LL + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/ + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Constants I2S Private Constants + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* I2S registers Masks */ + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define I2S_I2SPR_CLEAR_MASK 0x0002U + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/ + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Macros I2S Private Macros + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + ARM GAS /tmp/ccIphHaE.s page 39 + + + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @} + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/ + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup I2S_LL_Exported_Functions + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** @addtogroup I2S_LL_EF_Init + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @{ + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief De-initialize the SPI/I2S registers to their default reset values. + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPIx SPI Instance + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - SUCCESS: SPI registers are de-initialized + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ERROR: SPI registers are not de-initialized + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 287 .loc 1 357 0 + 288 .cfi_startproc + 289 @ args = 0, pretend = 0, frame = 0 + 290 @ frame_needed = 0, uses_anonymous_args = 0 + 291 @ link register save eliminated. + 292 .LVL24: + ARM GAS /tmp/ccIphHaE.s page 40 + + + 293 .LBB38: + 294 .LBB39: + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 295 .loc 1 147 0 + 296 0000 104B ldr r3, .L23 + 297 0002 9842 cmp r0, r3 + 298 0004 05D0 beq .L21 + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 299 .loc 1 141 0 + 300 0006 0023 movs r3, #0 + 301 .LVL25: + 302 .L18: + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 303 .loc 1 159 0 + 304 0008 0F4A ldr r2, .L23+4 + 305 000a 9042 cmp r0, r2 + 306 000c 0DD0 beq .L22 + 307 .LVL26: + 308 .L19: + 309 .LBE39: + 310 .LBE38: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** return LL_SPI_DeInit(SPIx); + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 311 .loc 1 359 0 + 312 000e 1800 movs r0, r3 + 313 .LVL27: + 314 @ sp needed + 315 0010 7047 bx lr + 316 .LVL28: + 317 .L21: + 318 .LBB49: + 319 .LBB48: + 320 .LBB40: + 321 .LBB41: + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 322 .loc 2 891 0 + 323 0012 0E4B ldr r3, .L23+8 + 324 0014 596A ldr r1, [r3, #36] + 325 0016 8022 movs r2, #128 + 326 0018 5201 lsls r2, r2, #5 + 327 001a 0A43 orrs r2, r1 + 328 001c 5A62 str r2, [r3, #36] + 329 .LVL29: + 330 .LBE41: + 331 .LBE40: + 332 .LBB42: + 333 .LBB43: + 334 .loc 2 918 0 + 335 001e 5A6A ldr r2, [r3, #36] + 336 0020 0B49 ldr r1, .L23+12 + 337 0022 0A40 ands r2, r1 + 338 0024 5A62 str r2, [r3, #36] + 339 .LVL30: + 340 .LBE43: + 341 .LBE42: + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 342 .loc 1 155 0 + ARM GAS /tmp/ccIphHaE.s page 41 + + + 343 0026 0123 movs r3, #1 + 344 0028 EEE7 b .L18 + 345 .LVL31: + 346 .L22: + 347 .LBB44: + 348 .LBB45: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 349 .loc 2 613 0 + 350 002a 084B ldr r3, .L23+8 + 351 .LVL32: + 352 002c 996A ldr r1, [r3, #40] + 353 002e 8022 movs r2, #128 + 354 0030 D201 lsls r2, r2, #7 + 355 0032 0A43 orrs r2, r1 + 356 0034 9A62 str r2, [r3, #40] + 357 .LVL33: + 358 .LBE45: + 359 .LBE44: + 360 .LBB46: + 361 .LBB47: + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 362 .loc 2 664 0 + 363 0036 9A6A ldr r2, [r3, #40] + 364 0038 0649 ldr r1, .L23+16 + 365 003a 0A40 ands r2, r1 + 366 003c 9A62 str r2, [r3, #40] + 367 .LVL34: + 368 .LBE47: + 369 .LBE46: + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 370 .loc 1 167 0 + 371 003e 0123 movs r3, #1 + 372 0040 E5E7 b .L19 + 373 .L24: + 374 0042 C046 .align 2 + 375 .L23: + 376 0044 00300140 .word 1073819648 + 377 0048 00380040 .word 1073756160 + 378 004c 00100240 .word 1073876992 + 379 0050 FFEFFFFF .word -4097 + 380 0054 FFBFFFFF .word -16385 + 381 .LBE48: + 382 .LBE49: + 383 .cfi_endproc + 384 .LFE315: + 386 .global __aeabi_uidiv + 387 .section .text.LL_I2S_Init,"ax",%progbits + 388 .align 1 + 389 .global LL_I2S_Init + 390 .syntax unified + 391 .code 16 + 392 .thumb_func + 393 .fpu softvfp + 395 LL_I2S_Init: + 396 .LFB316: + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + ARM GAS /tmp/ccIphHaE.s page 42 + + + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStru + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @note As some bits in SPI configuration registers can only be written when the SPI is disable + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPIx SPI Instance + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - SUCCESS: SPI registers are Initialized + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ERROR: SPI registers are not Initialized + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 397 .loc 1 372 0 + 398 .cfi_startproc + 399 @ args = 0, pretend = 0, frame = 16 + 400 @ frame_needed = 0, uses_anonymous_args = 0 + 401 .LVL35: + 402 0000 70B5 push {r4, r5, r6, lr} + 403 .LCFI1: + 404 .cfi_def_cfa_offset 16 + 405 .cfi_offset 4, -16 + 406 .cfi_offset 5, -12 + 407 .cfi_offset 6, -8 + 408 .cfi_offset 14, -4 + 409 0002 84B0 sub sp, sp, #16 + 410 .LCFI2: + 411 .cfi_def_cfa_offset 32 + 412 0004 0500 movs r5, r0 + 413 0006 0C00 movs r4, r1 + 414 .LVL36: + 415 .LBB50: + 416 .LBB51: + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get polynomial for CRC calculation + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get Rx CRC + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get Tx CRC + ARM GAS /tmp/ccIphHaE.s page 43 + + + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Set NSS mode + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get NSS mode + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (Ssm | Ssoe); + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + ARM GAS /tmp/ccIphHaE.s page 44 + + + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if Rx buffer is not empty + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if Tx buffer is empty + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get CRC error flag + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get mode fault error flag + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get overrun error flag + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + ARM GAS /tmp/ccIphHaE.s page 45 + + + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get busy flag + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * -When the SPI is correctly disabled + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * sent + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * each data transfer. + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get frame format error flag + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Clear CRC error flag + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Clear mode fault error flag + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __IO uint32_t tmpreg; + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** tmpreg = SPIx->SR; + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** (void) tmpreg; + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** (void) tmpreg; + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + ARM GAS /tmp/ccIphHaE.s page 46 + + + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Clear overrun error flag + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __IO uint32_t tmpreg; + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** tmpreg = SPIx->DR; + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** (void) tmpreg; + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** tmpreg = SPIx->SR; + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** (void) tmpreg; + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Clear frame format error flag + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __IO uint32_t tmpreg; + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** tmpreg = SPIx->SR; + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** (void) tmpreg; + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable error interrupt + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + ARM GAS /tmp/ccIphHaE.s page 47 + + + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable error interrupt + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if error interrupt is enabled + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + ARM GAS /tmp/ccIphHaE.s page 48 + + + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable DMA Rx +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable DMA Rx +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + ARM GAS /tmp/ccIphHaE.s page 49 + + +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if DMA Rx is enabled +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Enable DMA Tx +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable DMA Tx +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if DMA Tx is enabled +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Address of data register +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint32_t) & (SPIx->DR); +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} + ARM GAS /tmp/ccIphHaE.s page 50 + + +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Read 8-Bits in the data register +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint8_t)(READ_REG(SPIx->DR)); +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Read 16-Bits in the data register +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Write 8-Bits in the data register +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Write 16-Bits in the data register +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** *((__IO uint16_t *)&SPIx->DR) = TxData; +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + ARM GAS /tmp/ccIphHaE.s page 51 + + +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(SPI_I2S_SUPPORT) +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL I2S +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private constants ---------------------------------------------------------*/ +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief I2S Init structure definition +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** typedef struct +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the I2S operating mode. +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_MODE +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t Standard; /*!< Specifies the standard used for the I2S communication. +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_STANDARD +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_DATA_FORMA +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** + ARM GAS /tmp/ccIphHaE.s page 52 + + +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPU +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** Audio Frequency can be modified afterwards using Reference +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** and unitary functions @ref LL_I2S_SetPrescalerLinear() and +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_POLARITY +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } LL_I2S_InitTypeDef; +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif /*USE_FULL_LL_DRIVER*/ +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Flags defines which can be used with LL_I2S_ReadReg function +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format erro +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty inter +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_DATA_FORMAT Data format +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ + ARM GAS /tmp/ccIphHaE.s page 53 + + +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_POLARITY Clock Polarity +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is hig +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_STANDARD I2s Standard +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCF +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MODE Operation Mode +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Maste +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Maste +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is di +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is en + ARM GAS /tmp/ccIphHaE.s page 54 + + +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configura +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configura +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configura +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configura +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configura +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configura +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configura +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configura +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configura +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Write a value in I2S register +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __INSTANCE__ I2S Instance +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __REG__ Register to be written +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Read a value in I2S register +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __INSTANCE__ I2S Instance +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param __REG__ Register to be read +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval Register value +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** + ARM GAS /tmp/ccIphHaE.s page 55 + + +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @} +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** @defgroup I2S_LL_EF_Configuration Configuration +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @{ +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Select I2S mode and Enable I2S peripheral +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * I2SCFGR I2SE LL_I2S_Enable +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Disable I2S peripheral +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll I2SCFGR I2SE LL_I2S_Disable +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval None +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** } +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** /** +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @brief Check if I2S peripheral is enabled +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @param SPIx SPI Instance +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** * @retval State of bit (1 or 0). +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** */ +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** { +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h **** return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)); + 417 .loc 3 1412 0 + 418 0008 C369 ldr r3, [r0, #28] + 419 .LVL37: + 420 .LBE51: + 421 .LBE50: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** uint32_t tmp = 0U; + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_RCC_ClocksTypeDef rcc_clocks; + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** uint32_t sourceclock = 0U; + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** ErrorStatus status = ERROR; + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + ARM GAS /tmp/ccIphHaE.s page 56 + + + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the I2S parameters */ + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + 422 .loc 1 388 0 + 423 000a 5B05 lsls r3, r3, #21 + 424 000c 4FD4 bmi .L32 + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*---------------------------- SPIx I2SCFGR Configuration -------------------- + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Configure SPIx I2SCFGR with parameters: + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Write to SPIx I2SCFGR */ + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** MODIFY_REG(SPIx->I2SCFGR, + 425 .loc 1 399 0 + 426 000e C369 ldr r3, [r0, #28] + 427 0010 284A ldr r2, .L37 + 428 0012 1A40 ands r2, r3 + 429 0014 0B68 ldr r3, [r1] + 430 0016 4968 ldr r1, [r1, #4] + 431 .LVL38: + 432 0018 0B43 orrs r3, r1 + 433 001a A168 ldr r1, [r4, #8] + 434 001c 0B43 orrs r3, r1 + 435 001e 6169 ldr r1, [r4, #20] + 436 0020 0B43 orrs r3, r1 + 437 0022 1343 orrs r3, r2 + 438 0024 8022 movs r2, #128 + 439 0026 1201 lsls r2, r2, #4 + 440 0028 1343 orrs r3, r2 + 441 002a C361 str r3, [r0, #28] + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_I2SCFGR_CLEAR_MASK, + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->Mode | I2S_InitStruct->Standard | + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** SPI_I2SCFGR_I2SMOD); + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*---------------------------- SPIx I2SPR Configuration ---------------------- + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Configure SPIx I2SPR with parameters: + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - MCLKOutput: SPI_I2SPR_MCKOE bit + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + 442 .loc 1 414 0 + ARM GAS /tmp/ccIphHaE.s page 57 + + + 443 002c 2369 ldr r3, [r4, #16] + 444 002e 022B cmp r3, #2 + 445 0030 3AD0 beq .L33 + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the frame length (For the Prescaler computing) + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + 446 .loc 1 419 0 + 447 0032 A368 ldr r3, [r4, #8] + 448 0034 002B cmp r3, #0 + 449 0036 2AD1 bne .L34 + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** uint32_t tmp = 0U; + 450 .loc 1 373 0 + 451 0038 0126 movs r6, #1 + 452 .L28: + 453 .LVL39: + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Packet length is 32 bits */ + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** packetlength = 2U; + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* I2S Clock source is System clock: Get System Clock frequency */ + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** LL_RCC_GetSystemClocksFreq(&rcc_clocks); + 454 .loc 1 426 0 + 455 003a 6846 mov r0, sp + 456 .LVL40: + 457 003c FFF7FEFF bl LL_RCC_GetSystemClocksFreq + 458 .LVL41: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Get the source clock value: based on System Clock value */ + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** sourceclock = rcc_clocks.SYSCLK_Frequency; + 459 .loc 1 429 0 + 460 0040 0098 ldr r0, [sp] + 461 .LVL42: + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Compute the Real divider depending on the MCLK output state with a floating point */ + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + 462 .loc 1 432 0 + 463 0042 8023 movs r3, #128 + 464 0044 9B00 lsls r3, r3, #2 + 465 0046 E268 ldr r2, [r4, #12] + 466 0048 9A42 cmp r2, r3 + 467 004a 22D0 beq .L36 + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* MCLK output is enabled */ + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** else + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* MCLK output is disabled */ + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq + 468 .loc 1 440 0 + 469 004c 7101 lsls r1, r6, #5 + 470 004e FFF7FEFF bl __aeabi_uidiv + 471 .LVL43: + 472 0052 8300 lsls r3, r0, #2 + ARM GAS /tmp/ccIphHaE.s page 58 + + + 473 0054 1B18 adds r3, r3, r0 + 474 0056 5800 lsls r0, r3, #1 + 475 0058 2169 ldr r1, [r4, #16] + 476 005a FFF7FEFF bl __aeabi_uidiv + 477 .LVL44: + 478 005e 0530 adds r0, r0, #5 + 479 0060 80B2 uxth r0, r0 + 480 .LVL45: + 481 .L30: + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Remove the floating point */ + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** tmp = tmp / 10U; + 482 .loc 1 444 0 + 483 0062 0A21 movs r1, #10 + 484 0064 FFF7FEFF bl __aeabi_uidiv + 485 .LVL46: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the parity of the divider */ + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); + 486 .loc 1 447 0 + 487 0068 0122 movs r2, #1 + 488 006a 0240 ands r2, r0 + 489 .LVL47: + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Compute the i2sdiv prescaler */ + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); + 490 .loc 1 450 0 + 491 006c 831A subs r3, r0, r2 + 492 006e 5B08 lsrs r3, r3, #1 + 493 0070 98B2 uxth r0, r3 + 494 .LVL48: + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sodd = (uint16_t)(i2sodd << 8U); + 495 .loc 1 453 0 + 496 0072 1302 lsls r3, r2, #8 + 497 .LVL49: + 498 .L27: + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Test if the divider is 1 or 0 or greater than 0xFF */ + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + 499 .loc 1 457 0 + 500 0074 821E subs r2, r0, #2 + 501 0076 92B2 uxth r2, r2 + 502 0078 FD2A cmp r2, #253 + 503 007a 01D9 bls .L31 + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Set the default values */ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sdiv = 2U; + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sodd = 0U; + 504 .loc 1 461 0 + 505 007c 0023 movs r3, #0 + 506 .LVL50: + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** i2sodd = 0U; + 507 .loc 1 460 0 + ARM GAS /tmp/ccIphHaE.s page 59 + + + 508 007e 0220 movs r0, #2 + 509 .LVL51: + 510 .L31: + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Write to SPIx I2SPR register the computed value */ + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + 511 .loc 1 465 0 + 512 0080 1843 orrs r0, r3 + 513 .LVL52: + 514 0082 E368 ldr r3, [r4, #12] + 515 .LVL53: + 516 0084 1843 orrs r0, r3 + 517 0086 2862 str r0, [r5, #32] + 518 .LVL54: + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** status = SUCCESS; + 519 .loc 1 467 0 + 520 0088 0120 movs r0, #1 + 521 .LVL55: + 522 .L26: + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** return status; + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 523 .loc 1 470 0 + 524 008a 04B0 add sp, sp, #16 + 525 @ sp needed + 526 .LVL56: + 527 .LVL57: + 528 008c 70BD pop {r4, r5, r6, pc} + 529 .LVL58: + 530 .L34: + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 531 .loc 1 422 0 + 532 008e 0226 movs r6, #2 + 533 0090 D3E7 b .L28 + 534 .LVL59: + 535 .L36: + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 536 .loc 1 435 0 + 537 0092 000A lsrs r0, r0, #8 + 538 .LVL60: + 539 0094 8300 lsls r3, r0, #2 + 540 0096 1818 adds r0, r3, r0 + 541 0098 4300 lsls r3, r0, #1 + 542 009a 1800 movs r0, r3 + 543 009c 2169 ldr r1, [r4, #16] + 544 009e FFF7FEFF bl __aeabi_uidiv + 545 .LVL61: + 546 00a2 0530 adds r0, r0, #5 + 547 00a4 80B2 uxth r0, r0 + 548 .LVL62: + 549 00a6 DCE7 b .L30 + 550 .LVL63: + 551 .L33: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** uint32_t tmp = 0U; + 552 .loc 1 373 0 + ARM GAS /tmp/ccIphHaE.s page 60 + + + 553 00a8 0023 movs r3, #0 + 554 00aa 0220 movs r0, #2 + 555 .LVL64: + 556 00ac E2E7 b .L27 + 557 .LVL65: + 558 .L32: + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 559 .loc 1 377 0 + 560 00ae 0020 movs r0, #0 + 561 .LVL66: + 562 00b0 EBE7 b .L26 + 563 .L38: + 564 00b2 C046 .align 2 + 565 .L37: + 566 00b4 C0F4FFFF .word -2880 + 567 .cfi_endproc + 568 .LFE316: + 570 .section .text.LL_I2S_StructInit,"ax",%progbits + 571 .align 1 + 572 .global LL_I2S_StructInit + 573 .syntax unified + 574 .code 16 + 575 .thumb_func + 576 .fpu softvfp + 578 LL_I2S_StructInit: + 579 .LFB317: + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * whose fields will be set to default values. + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval None + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 580 .loc 1 479 0 + 581 .cfi_startproc + 582 @ args = 0, pretend = 0, frame = 0 + 583 @ frame_needed = 0, uses_anonymous_args = 0 + 584 @ link register save eliminated. + 585 .LVL67: + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /*--------------- Reset I2S init structure parameters values -----------------*/ + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + 586 .loc 1 481 0 + 587 0000 0023 movs r3, #0 + 588 0002 0360 str r3, [r0] + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + 589 .loc 1 482 0 + 590 0004 4360 str r3, [r0, #4] + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + 591 .loc 1 483 0 + 592 0006 8360 str r3, [r0, #8] + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + 593 .loc 1 484 0 + 594 0008 C360 str r3, [r0, #12] + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + 595 .loc 1 485 0 + ARM GAS /tmp/ccIphHaE.s page 61 + + + 596 000a 0222 movs r2, #2 + 597 000c 0261 str r2, [r0, #16] + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; + 598 .loc 1 486 0 + 599 000e 4361 str r3, [r0, #20] + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 600 .loc 1 487 0 + 601 @ sp needed + 602 0010 7047 bx lr + 603 .cfi_endproc + 604 .LFE317: + 606 .section .text.LL_I2S_ConfigPrescaler,"ax",%progbits + 607 .align 1 + 608 .global LL_I2S_ConfigPrescaler + 609 .syntax unified + 610 .code 16 + 611 .thumb_func + 612 .fpu softvfp + 614 LL_I2S_ConfigPrescaler: + 615 .LFB318: + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /** + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @brief Set linear and parity prescaler. + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param SPIx SPI Instance + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @param PrescalerParity This parameter can be one of the following values: + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** * @retval None + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** */ + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** { + 616 .loc 1 501 0 + 617 .cfi_startproc + 618 @ args = 0, pretend = 0, frame = 0 + 619 @ frame_needed = 0, uses_anonymous_args = 0 + 620 @ link register save eliminated. + 621 .LVL68: + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Check the I2S parameters */ + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** /* Write to SPIx I2SPR */ + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8 + 622 .loc 1 508 0 + 623 0000 036A ldr r3, [r0, #32] + 624 0002 5B0A lsrs r3, r3, #9 + 625 0004 5B02 lsls r3, r3, #9 + 626 0006 1202 lsls r2, r2, #8 + 627 .LVL69: + 628 0008 1143 orrs r1, r2 + 629 .LVL70: + 630 000a 1943 orrs r1, r3 + 631 000c 0162 str r1, [r0, #32] + ARM GAS /tmp/ccIphHaE.s page 62 + + + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c **** } + 632 .loc 1 509 0 + 633 @ sp needed + 634 000e 7047 bx lr + 635 .cfi_endproc + 636 .LFE318: + 638 .text + 639 .Letext0: + 640 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 641 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 642 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 643 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 644 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 645 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 646 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 647 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 648 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + 649 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h" + ARM GAS /tmp/ccIphHaE.s page 63 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_spi.c + /tmp/ccIphHaE.s:16 .text.LL_SPI_DeInit:0000000000000000 $t + /tmp/ccIphHaE.s:23 .text.LL_SPI_DeInit:0000000000000000 LL_SPI_DeInit + /tmp/ccIphHaE.s:110 .text.LL_SPI_DeInit:0000000000000044 $d + /tmp/ccIphHaE.s:119 .text.LL_SPI_Init:0000000000000000 $t + /tmp/ccIphHaE.s:126 .text.LL_SPI_Init:0000000000000000 LL_SPI_Init + /tmp/ccIphHaE.s:228 .text.LL_SPI_Init:0000000000000068 $d + /tmp/ccIphHaE.s:234 .text.LL_SPI_StructInit:0000000000000000 $t + /tmp/ccIphHaE.s:241 .text.LL_SPI_StructInit:0000000000000000 LL_SPI_StructInit + /tmp/ccIphHaE.s:278 .text.LL_I2S_DeInit:0000000000000000 $t + /tmp/ccIphHaE.s:285 .text.LL_I2S_DeInit:0000000000000000 LL_I2S_DeInit + /tmp/ccIphHaE.s:376 .text.LL_I2S_DeInit:0000000000000044 $d + /tmp/ccIphHaE.s:388 .text.LL_I2S_Init:0000000000000000 $t + /tmp/ccIphHaE.s:395 .text.LL_I2S_Init:0000000000000000 LL_I2S_Init + /tmp/ccIphHaE.s:566 .text.LL_I2S_Init:00000000000000b4 $d + /tmp/ccIphHaE.s:571 .text.LL_I2S_StructInit:0000000000000000 $t + /tmp/ccIphHaE.s:578 .text.LL_I2S_StructInit:0000000000000000 LL_I2S_StructInit + /tmp/ccIphHaE.s:607 .text.LL_I2S_ConfigPrescaler:0000000000000000 $t + /tmp/ccIphHaE.s:614 .text.LL_I2S_ConfigPrescaler:0000000000000000 LL_I2S_ConfigPrescaler + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +LL_RCC_GetSystemClocksFreq diff --git a/build/stm32l0xx_ll_tim.d b/build/stm32l0xx_ll_tim.d new file mode 100644 index 0000000..ff8408e --- /dev/null +++ b/build/stm32l0xx_ll_tim.d @@ -0,0 +1,109 @@ +build/stm32l0xx_ll_tim.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_tim.lst b/build/stm32l0xx_ll_tim.lst new file mode 100644 index 0000000..1c69e15 --- /dev/null +++ b/build/stm32l0xx_ll_tim.lst @@ -0,0 +1,6609 @@ +ARM GAS /tmp/cc5G6dGG.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_tim.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_TIM_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_TIM_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_TIM_DeInit: + 24 .LFB211: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @file stm32l0xx_ll_tim.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief TIM LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ****************************************************************************** + ARM GAS /tmp/cc5G6dGG.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #include "stm32l0xx_ll_tim.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #include "stm32l0xx_ll_bus.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || def + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup TIM_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Private macros ------------------------------------------------------------*/ + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Macros + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + ARM GAS /tmp/cc5G6dGG.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @} + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Private function prototypes -----------------------------------------------*/ + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @defgroup TIM_LL_Private_Functions TIM Private Functions + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @} + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Exported functions --------------------------------------------------------*/ + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup TIM_LL_Exported_Functions + ARM GAS /tmp/cc5G6dGG.s page 4 + + + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup TIM_LL_EF_Init + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Set TIMx registers to their reset values. + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer instance + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: invalid TIMx instance + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 26 .loc 1 163 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus result = SUCCESS; + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_INSTANCE(TIMx)); + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** if (TIMx == TIM2) + 32 .loc 1 169 0 + 33 0000 8023 movs r3, #128 + 34 0002 DB05 lsls r3, r3, #23 + 35 0004 9842 cmp r0, r3 + 36 0006 10D0 beq .L9 + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined(TIM3) + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else if (TIMx == TIM3) + 37 .loc 1 175 0 + 38 0008 264B ldr r3, .L15 + 39 000a 9842 cmp r0, r3 + 40 000c 17D0 beq .L10 + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #endif /* TIM3 */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined(TIM6) + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else if (TIMx == TIM6) + 41 .loc 1 182 0 + 42 000e 264B ldr r3, .L15+4 + 43 0010 9842 cmp r0, r3 + 44 0012 1ED0 beq .L11 + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + ARM GAS /tmp/cc5G6dGG.s page 5 + + + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #endif /* TIM6 */ + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined(TIM7) + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else if (TIMx == TIM7) + 45 .loc 1 189 0 + 46 0014 254B ldr r3, .L15+8 + 47 0016 9842 cmp r0, r3 + 48 0018 25D0 beq .L12 + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #endif /* TIM7 */ + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else if (TIMx == TIM21) + 49 .loc 1 195 0 + 50 001a 254B ldr r3, .L15+12 + 51 001c 9842 cmp r0, r3 + 52 001e 2CD0 beq .L13 + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21); + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21); + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #if defined(TIM22) + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else if (TIMx == TIM22) + 53 .loc 1 201 0 + 54 0020 244B ldr r3, .L15+16 + 55 0022 9842 cmp r0, r3 + 56 0024 33D0 beq .L14 + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22); + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22); + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** #endif /* TIM22 */ + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** else + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = ERROR; + 57 .loc 1 209 0 + 58 0026 0020 movs r0, #0 + 59 .LVL1: + 60 0028 08E0 b .L3 + 61 .LVL2: + 62 .L9: + 63 .LBB66: + 64 .LBB67: + 65 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + ARM GAS /tmp/cc5G6dGG.s page 6 + + + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cc5G6dGG.s page 7 + + + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + ARM GAS /tmp/cc5G6dGG.s page 8 + + + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cc5G6dGG.s page 9 + + + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + ARM GAS /tmp/cc5G6dGG.s page 10 + + + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 11 + + + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + ARM GAS /tmp/cc5G6dGG.s page 12 + + + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 13 + + + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/cc5G6dGG.s page 14 + + + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/cc5G6dGG.s page 15 + + + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/cc5G6dGG.s page 16 + + + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 66 .loc 2 613 0 + 67 002a 234B ldr r3, .L15+20 + 68 002c 9A6A ldr r2, [r3, #40] + 69 002e 0121 movs r1, #1 + 70 0030 0A43 orrs r2, r1 + 71 0032 9A62 str r2, [r3, #40] + 72 .LVL3: + 73 .LBE67: + 74 .LBE66: + 75 .LBB68: + 76 .LBB69: + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/cc5G6dGG.s page 17 + + + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 77 .loc 2 664 0 + 78 0034 9A6A ldr r2, [r3, #40] + 79 0036 8A43 bics r2, r1 + 80 0038 9A62 str r2, [r3, #40] + 81 .LBE69: + 82 .LBE68: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 83 .loc 1 164 0 + 84 003a 0120 movs r0, #1 + 85 .LVL4: + 86 .L3: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return result; + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 87 .loc 1 213 0 + 88 @ sp needed + 89 003c 7047 bx lr + 90 .LVL5: + 91 .L10: + 92 .LBB70: + ARM GAS /tmp/cc5G6dGG.s page 18 + + + 93 .LBB71: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 94 .loc 2 613 0 + 95 003e 1E4B ldr r3, .L15+20 + 96 0040 9A6A ldr r2, [r3, #40] + 97 0042 0221 movs r1, #2 + 98 0044 0A43 orrs r2, r1 + 99 0046 9A62 str r2, [r3, #40] + 100 .LVL6: + 101 .LBE71: + 102 .LBE70: + 103 .LBB72: + 104 .LBB73: + 105 .loc 2 664 0 + 106 0048 9A6A ldr r2, [r3, #40] + 107 004a 8A43 bics r2, r1 + 108 004c 9A62 str r2, [r3, #40] + 109 .LBE73: + 110 .LBE72: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 111 .loc 1 164 0 + 112 004e 0120 movs r0, #1 + 113 .LVL7: + 114 0050 F4E7 b .L3 + 115 .LVL8: + 116 .L11: + 117 .LBB74: + 118 .LBB75: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 119 .loc 2 613 0 + 120 0052 194B ldr r3, .L15+20 + 121 0054 9A6A ldr r2, [r3, #40] + 122 0056 1021 movs r1, #16 + 123 0058 0A43 orrs r2, r1 + 124 005a 9A62 str r2, [r3, #40] + 125 .LVL9: + 126 .LBE75: + 127 .LBE74: + 128 .LBB76: + 129 .LBB77: + 130 .loc 2 664 0 + 131 005c 9A6A ldr r2, [r3, #40] + 132 005e 8A43 bics r2, r1 + 133 0060 9A62 str r2, [r3, #40] + 134 .LBE77: + 135 .LBE76: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 136 .loc 1 164 0 + 137 0062 0120 movs r0, #1 + 138 .LVL10: + 139 0064 EAE7 b .L3 + 140 .LVL11: + 141 .L12: + 142 .LBB78: + 143 .LBB79: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 144 .loc 2 613 0 + ARM GAS /tmp/cc5G6dGG.s page 19 + + + 145 0066 144B ldr r3, .L15+20 + 146 0068 9A6A ldr r2, [r3, #40] + 147 006a 2021 movs r1, #32 + 148 006c 0A43 orrs r2, r1 + 149 006e 9A62 str r2, [r3, #40] + 150 .LVL12: + 151 .LBE79: + 152 .LBE78: + 153 .LBB80: + 154 .LBB81: + 155 .loc 2 664 0 + 156 0070 9A6A ldr r2, [r3, #40] + 157 0072 8A43 bics r2, r1 + 158 0074 9A62 str r2, [r3, #40] + 159 .LBE81: + 160 .LBE80: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 161 .loc 1 164 0 + 162 0076 0120 movs r0, #1 + 163 .LVL13: + 164 0078 E0E7 b .L3 + 165 .LVL14: + 166 .L13: + 167 .LBB82: + 168 .LBB83: + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + ARM GAS /tmp/cc5G6dGG.s page 20 + + + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1SMENR, Periphs); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + ARM GAS /tmp/cc5G6dGG.s page 21 + + + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1SMENR, Periphs); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + ARM GAS /tmp/cc5G6dGG.s page 22 + + + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 23 + + + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB2 peripherals reset. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 169 .loc 2 891 0 + 170 007a 0F4B ldr r3, .L15+20 + 171 007c 5A6A ldr r2, [r3, #36] + 172 007e 0421 movs r1, #4 + 173 0080 0A43 orrs r2, r1 + 174 0082 5A62 str r2, [r3, #36] + 175 .LVL15: + 176 .LBE83: + 177 .LBE82: + 178 .LBB84: + 179 .LBB85: + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB2 peripherals reset. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/cc5G6dGG.s page 24 + + + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 180 .loc 2 918 0 + 181 0084 5A6A ldr r2, [r3, #36] + 182 0086 8A43 bics r2, r1 + 183 0088 5A62 str r2, [r3, #36] + 184 .LBE85: + 185 .LBE84: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 186 .loc 1 164 0 + 187 008a 0120 movs r0, #1 + 188 .LVL16: + 189 008c D6E7 b .L3 + 190 .LVL17: + 191 .L14: + 192 .LBB86: + 193 .LBB87: + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 194 .loc 2 891 0 + 195 008e 0A4B ldr r3, .L15+20 + 196 0090 5A6A ldr r2, [r3, #36] + 197 0092 2021 movs r1, #32 + 198 0094 0A43 orrs r2, r1 + 199 0096 5A62 str r2, [r3, #36] + 200 .LVL18: + 201 .LBE87: + 202 .LBE86: + 203 .LBB88: + 204 .LBB89: + 205 .loc 2 918 0 + 206 0098 5A6A ldr r2, [r3, #36] + 207 009a 8A43 bics r2, r1 + 208 009c 5A62 str r2, [r3, #36] + 209 .LBE89: + 210 .LBE88: + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 211 .loc 1 164 0 + 212 009e 0120 movs r0, #1 + 213 .LVL19: + 214 00a0 CCE7 b .L3 + 215 .L16: + 216 00a2 C046 .align 2 + 217 .L15: + 218 00a4 00040040 .word 1073742848 + 219 00a8 00100040 .word 1073745920 + 220 00ac 00140040 .word 1073746944 + 221 00b0 00080140 .word 1073809408 + 222 00b4 00140140 .word 1073812480 + 223 00b8 00100240 .word 1073876992 + 224 .cfi_endproc + 225 .LFE211: + 227 .section .text.LL_TIM_StructInit,"ax",%progbits + 228 .align 1 + 229 .global LL_TIM_StructInit + ARM GAS /tmp/cc5G6dGG.s page 25 + + + 230 .syntax unified + 231 .code 16 + 232 .thumb_func + 233 .fpu softvfp + 235 LL_TIM_StructInit: + 236 .LFB212: + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Set the fields of the time base unit configuration data structure + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * to their default values. + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configura + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval None + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 237 .loc 1 222 0 + 238 .cfi_startproc + 239 @ args = 0, pretend = 0, frame = 0 + 240 @ frame_needed = 0, uses_anonymous_args = 0 + 241 @ link register save eliminated. + 242 .LVL20: + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_InitStruct->Prescaler = (uint16_t)0x0000U; + 243 .loc 1 224 0 + 244 0000 0023 movs r3, #0 + 245 0002 0380 strh r3, [r0] + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + 246 .loc 1 225 0 + 247 0004 4360 str r3, [r0, #4] + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU; + 248 .loc 1 226 0 + 249 0006 0122 movs r2, #1 + 250 0008 5242 rsbs r2, r2, #0 + 251 000a 8260 str r2, [r0, #8] + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 252 .loc 1 227 0 + 253 000c C360 str r3, [r0, #12] + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 254 .loc 1 228 0 + 255 @ sp needed + 256 000e 7047 bx lr + 257 .cfi_endproc + 258 .LFE212: + 260 .section .text.LL_TIM_Init,"ax",%progbits + 261 .align 1 + 262 .global LL_TIM_Init + 263 .syntax unified + 264 .code 16 + 265 .thumb_func + 266 .fpu softvfp + 268 LL_TIM_Init: + 269 .LFB213: + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx time base unit. + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit conf + ARM GAS /tmp/cc5G6dGG.s page 26 + + + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 270 .loc 1 239 0 + 271 .cfi_startproc + 272 @ args = 0, pretend = 0, frame = 0 + 273 @ frame_needed = 0, uses_anonymous_args = 0 + 274 @ link register save eliminated. + 275 .LVL21: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpcr1 = 0U; + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_INSTANCE(TIMx)); + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + 276 .loc 1 247 0 + 277 0000 0368 ldr r3, [r0] + 278 .LVL22: + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 279 .loc 1 249 0 + 280 0002 8022 movs r2, #128 + 281 0004 D205 lsls r2, r2, #23 + 282 0006 9042 cmp r0, r2 + 283 0008 08D0 beq .L19 + 284 .loc 1 249 0 is_stmt 0 discriminator 1 + 285 000a 144A ldr r2, .L23 + 286 000c 9042 cmp r0, r2 + 287 000e 05D0 beq .L19 + 288 .loc 1 249 0 discriminator 2 + 289 0010 134A ldr r2, .L23+4 + 290 0012 9042 cmp r0, r2 + 291 0014 02D0 beq .L19 + 292 .loc 1 249 0 discriminator 3 + 293 0016 134A ldr r2, .L23+8 + 294 0018 9042 cmp r0, r2 + 295 001a 03D1 bne .L20 + 296 .L19: + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Counter Mode */ + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + 297 .loc 1 252 0 is_stmt 1 + 298 001c 7022 movs r2, #112 + 299 001e 9343 bics r3, r2 + 300 .LVL23: + 301 0020 4A68 ldr r2, [r1, #4] + 302 0022 1343 orrs r3, r2 + 303 .LVL24: + 304 .L20: + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + ARM GAS /tmp/cc5G6dGG.s page 27 + + + 305 .loc 1 255 0 + 306 0024 8022 movs r2, #128 + 307 0026 D205 lsls r2, r2, #23 + 308 0028 9042 cmp r0, r2 + 309 002a 08D0 beq .L21 + 310 .loc 1 255 0 is_stmt 0 discriminator 1 + 311 002c 0B4A ldr r2, .L23 + 312 002e 9042 cmp r0, r2 + 313 0030 05D0 beq .L21 + 314 .loc 1 255 0 discriminator 2 + 315 0032 0B4A ldr r2, .L23+4 + 316 0034 9042 cmp r0, r2 + 317 0036 02D0 beq .L21 + 318 .loc 1 255 0 discriminator 3 + 319 0038 0A4A ldr r2, .L23+8 + 320 003a 9042 cmp r0, r2 + 321 003c 03D1 bne .L22 + 322 .L21: + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the clock division */ + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + 323 .loc 1 258 0 is_stmt 1 + 324 003e 0A4A ldr r2, .L23+12 + 325 0040 1340 ands r3, r2 + 326 .LVL25: + 327 0042 CA68 ldr r2, [r1, #12] + 328 0044 1343 orrs r3, r2 + 329 .LVL26: + 330 .L22: + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CR1 */ + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + 331 .loc 1 262 0 + 332 0046 0360 str r3, [r0] + 333 .LVL27: + 334 .LBB90: + 335 .LBB91: + 336 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @file stm32l0xx_ll_tim.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Header file of TIM LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + ARM GAS /tmp/cc5G6dGG.s page 28 + + + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #ifndef __STM32L0xx_LL_TIM_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __STM32L0xx_LL_TIM_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || def + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL TIM + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x00U, /* 1: NA */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x00U, /* 3: NA */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x00U, /* 5: NA */ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0x04U /* 6: TIMx_CH4 */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** }; + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ + ARM GAS /tmp/cc5G6dGG.s page 29 + + + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 1: - NA */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 3: - NA */ + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 5: - NA */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 8U /* 6: OC4M, OC4FE, OC4PE */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** }; + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 1: - NA */ + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 3: - NA */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 5: - NA */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 8U /* 6: CC4S, IC4PSC, IC4F */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** }; + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 0: CC1P */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 1: NA */ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 4U, /* 2: CC2P */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 3: NA */ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 8U, /* 4: CC3P */ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 0U, /* 5: NA */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** 12U /* 6: CC4P */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** }; + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Remap mask definitions */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT ((uint32_t)16U) + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU) + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIM2_OR_RMP_MASK ((uint32_t)((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT)) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIM21_OR_RMP_MASK ((uint32_t)((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIM22_OR_RMP_MASK ((uint32_t)((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)) + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #if defined(TIM3) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIM3_OR_RMP_MASK ((uint32_t)((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #endif /* TIM3 */ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + ARM GAS /tmp/cc5G6dGG.s page 30 + + + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @brief Convert channel id into channel index. + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval none + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** typedef struct + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** Auto-Reload Register at the next update event. + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } LL_TIM_InitTypeDef; + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + ARM GAS /tmp/cc5G6dGG.s page 31 + + + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** typedef struct + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary functions @ref + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function LL_TI + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** typedef struct + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @ref + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 32 + + + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** typedef struct + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** This feature can be modified afterwards using unitary function @re + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + ARM GAS /tmp/cc5G6dGG.s page 33 + + + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underf + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/un + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped a + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + ARM GAS /tmp/cc5G6dGG.s page 34 + + + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!__REG__, (__VALUE + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Read a value in TIM register. + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __REG__ Register to be read + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Register value + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __PSC__ prescaler + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U) + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __PSC__ prescaler + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration ( + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __PSC__ prescaler + ARM GAS /tmp/cc5G6dGG.s page 43 + + + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable timer counter. + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable timer counter. + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) + ARM GAS /tmp/cc5G6dGG.s page 44 + + + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable update event generation. + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable update event generation. + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set update event source + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * - Counter overflow/underflow + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * - Setting the UG bit + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * - Update generation through the slave mode controller + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. + ARM GAS /tmp/cc5G6dGG.s page 45 + + + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get actual event update source +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get actual one pulse mode. +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the timer counter counting mode. +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * by a timer instance. + ARM GAS /tmp/cc5G6dGG.s page 46 + + +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get actual counter mode. +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * by a timer instance. +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + ARM GAS /tmp/cc5G6dGG.s page 47 + + +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * instance. +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * instance. +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the counter value. +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); + ARM GAS /tmp/cc5G6dGG.s page 48 + + +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the counter value. +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the current direction of the counter +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the prescaler value. +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the prescaler value. +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the auto-reload value. +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + ARM GAS /tmp/cc5G6dGG.s page 49 + + +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); + 337 .loc 3 1223 0 + 338 0048 8B68 ldr r3, [r1, #8] + 339 .LVL28: + 340 004a C362 str r3, [r0, #44] + 341 .LVL29: + 342 .LBE91: + 343 .LBE90: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Autoreload value */ + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Prescaler value */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + 344 .loc 1 268 0 + 345 004c 0B88 ldrh r3, [r1] + 346 .LVL30: + 347 .LBB92: + 348 .LBB93: +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 349 .loc 3 1198 0 + 350 004e 8362 str r3, [r0, #40] + 351 .LVL31: + 352 .LBE93: + 353 .LBE92: + 354 .LBB94: + 355 .LBB95: +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the auto-reload value. +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Auto-reload value +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + ARM GAS /tmp/cc5G6dGG.s page 50 + + +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare channels. +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare channels. +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + ARM GAS /tmp/cc5G6dGG.s page 51 + + +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, Channels) == (Channels)); +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Configure an output channel. +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + ARM GAS /tmp/cc5G6dGG.s page 52 + + +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIF +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) + ARM GAS /tmp/cc5G6dGG.s page 53 + + +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIF +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the polarity of an output channel. +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the polarity of an output channel. +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable fast mode for the output channel. +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + ARM GAS /tmp/cc5G6dGG.s page 54 + + +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable fast mode for the output channel. +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh + ARM GAS /tmp/cc5G6dGG.s page 55 + + +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(*pReg, bitfield) == bitfield); +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + ARM GAS /tmp/cc5G6dGG.s page 56 + + +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(*pReg, bitfield) == bitfield); +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + ARM GAS /tmp/cc5G6dGG.s page 57 + + +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(*pReg, bitfield) == bitfield); +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). + ARM GAS /tmp/cc5G6dGG.s page 58 + + +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel is supported by a timer instance. +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 3 is supported by a timer instance. +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + ARM GAS /tmp/cc5G6dGG.s page 59 + + +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Configure input channel. +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: + ARM GAS /tmp/cc5G6dGG.s page 60 + + +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SH +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the active input. +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the current active input. +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +1872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +1873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC + ARM GAS /tmp/cc5G6dGG.s page 61 + + +1874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +1876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +1880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the prescaler of input channel. +1884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n +1885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n +1886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n +1887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler +1888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: +1895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +1896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +1897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +1898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +1899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal +1902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT +1906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. +1910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n +1911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n +1912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n +1913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler +1914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +1922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +1923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +1924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +1925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +1927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha + ARM GAS /tmp/cc5G6dGG.s page 62 + + +1931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the input filter duration. +1935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n +1936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n +1937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n +1938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter +1939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: +1946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +1947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +1948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +1949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +1950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +1951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +1952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +1953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +1954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +1955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +1956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +1957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +1958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +1959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +1960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +1961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +1962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +1963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +1964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +1965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +1966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +1968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ +1969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +1970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +1971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +1972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the input filter duration. +1973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n +1974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n +1975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n +1976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter +1977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +1978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +1985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +1986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +1987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + ARM GAS /tmp/cc5G6dGG.s page 63 + + +1988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +1989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +1990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +1991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +1992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +1993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +1994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +1995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +1996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +1997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +1998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +1999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +2002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh +2005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the input channel polarity. +2010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n +2011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n +2012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n +2013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n +2014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n +2015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n +2016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n +2017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity +2018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: +2025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity +2031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); +2035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get the current input channel polarity. +2039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n +2040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n +2041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n +2042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n +2043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n +2044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n + ARM GAS /tmp/cc5G6dGG.s page 64 + + +2045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n +2046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity +2047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +2059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> +2062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); +2063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). +2067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance provides an XOR input. +2069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination +2070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +2074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +2076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. +2080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance provides an XOR input. +2082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination +2083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +2087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +2089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. +2093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance provides an XOR input. +2095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination +2096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +2100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); + ARM GAS /tmp/cc5G6dGG.s page 65 + + +2102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get captured value for input channel 1. +2106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * input channel 1 is supported by a timer instance. +2108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 +2109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +2113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get captured value for input channel 2. +2119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * input channel 2 is supported by a timer instance. +2121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 +2122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +2126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get captured value for input channel 3. +2132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * input channel 3 is supported by a timer instance. +2134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 +2135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +2139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +2141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Get captured value for input channel 4. +2145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * input channel 4 is supported by a timer instance. +2147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 +2148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +2152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +2154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + ARM GAS /tmp/cc5G6dGG.s page 66 + + +2159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection +2161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable external clock mode 2. +2165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET +2166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +2167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +2168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock +2169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +2173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +2175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable external clock mode 2. +2179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +2180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +2181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock +2182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +2186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +2188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. +2192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +2193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +2194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock +2195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +2199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); +2201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the clock source of the counter clock. +2205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input +2206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() +2207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * function. This timer input must be configured by calling +2208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. +2209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check +2210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. +2211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +2212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +2213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n +2214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource +2215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/cc5G6dGG.s page 67 + + +2216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: +2217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL +2218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 +2219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 +2220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +2223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +2225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the encoder interface mode. +2229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check +2230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. +2231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode +2232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: +2234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 +2235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 +2236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 +2237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +2240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +2242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration +2249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . +2253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check +2254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. +2255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput +2256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: +2258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET +2259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE +2260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE +2261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF +2262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF +2263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF +2264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF +2265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF +2266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +2269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +2271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + ARM GAS /tmp/cc5G6dGG.s page 68 + + +2273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. +2275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +2276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance can operate as a slave timer. +2277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode +2278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: +2280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED +2281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET +2282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED +2283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER +2284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +2287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +2289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. +2293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +2294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance can operate as a slave timer. +2295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput +2296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: +2298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 +2299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 +2300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 +2301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 +2302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED +2303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 +2304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 +2305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF +2306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +2309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +2311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable the Master/Slave mode. +2315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +2316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance can operate as a slave timer. +2317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode +2318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +2322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +2324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable the Master/Slave mode. +2328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +2329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance can operate as a slave timer. + ARM GAS /tmp/cc5G6dGG.s page 69 + + +2330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode +2331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +2335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +2337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. +2341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +2342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance can operate as a slave timer. +2343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode +2344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +2348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); +2350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. +2354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not +2355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a timer instance provides an external trigger input. +2356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n +2357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n +2358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR +2359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: +2361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED +2362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED +2363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: +2364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 +2365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 +2366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 +2367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 +2368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: +2369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 +2370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 +2371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 +2372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 +2373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 +2374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 +2375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 +2376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 +2377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 +2378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 +2379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 +2380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 +2381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 +2382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 +2383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 +2384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 +2385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + ARM GAS /tmp/cc5G6dGG.s page 70 + + +2387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale +2388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** uint32_t ETRFilter) +2389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | +2391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration +2398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. +2402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or +2403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. +2404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n +2405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst +2406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: +2408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 +2409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 +2410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR +2411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER +2412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR +2413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR +2414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 +2415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 +2416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER +2417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT +2418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC +2419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR +2420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR +2421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 +2422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 +2423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 +2424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 +2425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR +2426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 +2427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 +2428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 +2429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 +2430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 +2431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 +2432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: +2433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER +2434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS +2435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS +2436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS +2437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS +2438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS +2439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS +2440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS +2441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS +2442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS +2443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + ARM GAS /tmp/cc5G6dGG.s page 71 + + +2444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS +2445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS +2446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS +2447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS +2448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS +2449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS +2450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS +2451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ +2454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); +2456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping +2463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). +2467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not +2468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * a some timer inputs can be remapped. +2469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll TIM2_OR ETR_RMP LL_TIM_SetRemap\n +2470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM2_OR TI4_RMP LL_TIM_SetRemap\n +2471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM21_OR ETR_RMP LL_TIM_SetRemap\n +2472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM21_OR TI1_RMP LL_TIM_SetRemap\n +2473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM21_OR TI2_RMP LL_TIM_SetRemap\n +2474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM22_OR ETR_RMP LL_TIM_SetRemap\n +2475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM22_OR TI1_RMP LL_TIM_SetRemap\n +2476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM3_OR ETR_RMP LL_TIM_SetRemap\n +2477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM3_OR TI1_RMP LL_TIM_SetRemap\n +2478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM3_OR TI2_RMP LL_TIM_SetRemap\n +2479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM3_OR TI4_RMP LL_TIM_SetRemap +2480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param Remap Remap params depends on the TIMx. Description available only +2482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). +2483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. +2484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: +2486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM2: any combination of ETR_RMP, TI4_RMP where +2488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . ETR_RMP can be one of the following values +2490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO +2491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI (*) +2492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*) +2493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE +2494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2 +2495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1 +2496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI4_RMP can be one of the following values +2498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO +2499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 +2500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 + ARM GAS /tmp/cc5G6dGG.s page 72 + + +2501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM3: any combination of the following values (**) +2503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . ETR_RMP can be one of the following values (**) +2505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO +2506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6 +2507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI_RMP_TI1 can be one of the following values (**) +2509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF +2510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO +2511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI_RMP_TI2 can be one of the following values (**) +2513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF +2514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4 +2515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI_RMP_TI4 can be one of the following values (**) +2517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF +2518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2 +2519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where +2521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . ETR_RMP can be one of the following values +2523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO +2524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2 +2525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1 +2526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_ETR_RMP_LSE +2527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI1_RMP can be one of the following values +2529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO +2530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK +2531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC +2532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_MSI +2533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_LSE +2534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_LSI +2535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1 +2536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI1_RMP_MCO +2537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI2_RMP can be one of the following values +2539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO +2540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2 +2541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * TIM22: any combination of ETR_RMP, TI1_RMP where (**) +2543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . ETR_RMP can be one of the following values (**) +2545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO +2546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2 +2547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1 +2548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_ETR_RMP_LSE +2549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * . . TI1_RMP can be one of the following values (**) +2551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1 +2552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2 +2553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1 +2554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2 +2555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * +2556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * (*) Value not defined in all devices. \n +2557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * (*) Register not available in all devices. + ARM GAS /tmp/cc5G6dGG.s page 73 + + +2558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +2561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +2563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management +2570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Set the OCREF clear input source +2574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the O +2575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. +2576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource +2577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param OCRefClearInputSource This parameter can be one of the following values: +2579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCREF_CLR_INT_NC +2580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @arg @ref LL_TIM_OCREF_CLR_INT_ETR +2581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSou +2584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); +2586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management +2592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). +2596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE +2597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +2601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +2603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). +2607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE +2608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +2612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); +2614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + ARM GAS /tmp/cc5G6dGG.s page 74 + + +2615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). +2618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 +2619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +2623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +2625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte +2629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 +2630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +2634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); +2636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). +2640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 +2641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +2645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +2647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte +2651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 +2652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +2656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); +2658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). +2662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 +2663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +2667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +2669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 75 + + +2672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte +2673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 +2674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +2678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); +2680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). +2684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 +2685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +2689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +2691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte +2695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 +2696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +2700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); +2702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). +2706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG +2707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +2711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +2713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). +2717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG +2718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +2722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); +2724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). +2728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + ARM GAS /tmp/cc5G6dGG.s page 76 + + +2729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +2733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +2735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/ +2739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR +2740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +2744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); +2746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). +2750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR +2751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +2755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +2757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/ +2761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR +2762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +2766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); +2768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). +2772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR +2773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +2777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +2779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/ +2783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR +2784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc5G6dGG.s page 77 + + +2786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +2788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); +2790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). +2794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR +2795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +2799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +2801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/ +2805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR +2806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +2810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); +2812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +2816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management +2819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +2820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable update interrupt (UIE). +2823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE +2824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +2828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); +2830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable update interrupt (UIE). +2834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE +2835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +2839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +2841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** + ARM GAS /tmp/cc5G6dGG.s page 78 + + +2843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the update interrupt (UIE) is enabled. +2845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE +2846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +2850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); +2852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 1 interrupt (CC1IE). +2856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 +2857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +2861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +2863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 1 interrupt (CC1IE). +2867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 +2868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +2872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +2874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. +2878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 +2879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +2883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); +2885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 2 interrupt (CC2IE). +2889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 +2890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +2894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +2896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 2 interrupt (CC2IE). + ARM GAS /tmp/cc5G6dGG.s page 79 + + +2900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 +2901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +2905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +2907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. +2911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 +2912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +2916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); +2918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 3 interrupt (CC3IE). +2922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 +2923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +2927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +2929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 3 interrupt (CC3IE). +2933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 +2934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +2938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +2940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. +2944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 +2945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +2949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); +2951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 4 interrupt (CC4IE). +2955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 +2956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/cc5G6dGG.s page 80 + + +2957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +2960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +2962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 4 interrupt (CC4IE). +2966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 +2967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +2971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +2973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. +2977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 +2978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +2980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +2982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); +2984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable trigger interrupt (TIE). +2988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG +2989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +2990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +2991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +2992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +2993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +2994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_TIE); +2995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +2996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +2997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +2998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable trigger interrupt (TIE). +2999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG +3000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +3004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +3006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the trigger interrupt (TIE) is enabled. +3010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG +3011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ + ARM GAS /tmp/cc5G6dGG.s page 81 + + +3014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +3015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); +3017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +3021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Management DMA-Management +3024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +3025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable update DMA request (UDE). +3028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE +3029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +3033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UDE); +3035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable update DMA request (UDE). +3039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE +3040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +3044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +3046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the update DMA request (UDE) is enabled. +3050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE +3051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +3055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); +3057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 1 DMA request (CC1DE). +3061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 +3062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +3066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +3068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** + ARM GAS /tmp/cc5G6dGG.s page 82 + + +3071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 1 DMA request (CC1DE). +3072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 +3073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +3077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +3079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. +3083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 +3084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +3088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); +3090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 2 DMA request (CC2DE). +3094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 +3095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +3099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +3101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 2 DMA request (CC2DE). +3105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 +3106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +3110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +3112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. +3116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 +3117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +3121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); +3123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 3 DMA request (CC3DE). +3127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + ARM GAS /tmp/cc5G6dGG.s page 83 + + +3128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +3132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +3134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 3 DMA request (CC3DE). +3138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 +3139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +3143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +3145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. +3149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 +3150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +3154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); +3156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable capture/compare 4 DMA request (CC4DE). +3160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 +3161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +3165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +3167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable capture/compare 4 DMA request (CC4DE). +3171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 +3172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +3176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +3178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. +3182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 +3183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc5G6dGG.s page 84 + + +3185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +3187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); +3189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Enable trigger interrupt (TDE). +3193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG +3194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +3198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_TDE); +3200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Disable trigger interrupt (TDE). +3204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG +3205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +3209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +3211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Indicates whether the trigger interrupt (TDE) is enabled. +3215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG +3216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval State of bit (1 or 0). +3218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +3220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); +3222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } +3223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @} +3226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** +3228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management +3229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @{ +3230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** /** +3232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @brief Generate an update event. +3233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE +3234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @param TIMx Timer instance +3235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** * @retval None +3236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** */ +3237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +3238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** { +3239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** SET_BIT(TIMx->EGR, TIM_EGR_UG); + 356 .loc 3 3239 0 + 357 0050 4369 ldr r3, [r0, #20] + ARM GAS /tmp/cc5G6dGG.s page 85 + + + 358 0052 0122 movs r2, #1 + 359 0054 1343 orrs r3, r2 + 360 0056 4361 str r3, [r0, #20] + 361 .LVL32: + 362 .LBE95: + 363 .LBE94: + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Generate an update event to reload the Prescaler + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** and the repetition counter value (if applicable) immediately */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_GenerateEvent_UPDATE(TIMx); + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 364 .loc 1 274 0 + 365 0058 0120 movs r0, #1 + 366 .LVL33: + 367 @ sp needed + 368 005a 7047 bx lr + 369 .L24: + 370 .align 2 + 371 .L23: + 372 005c 00040040 .word 1073742848 + 373 0060 00080140 .word 1073809408 + 374 0064 00140140 .word 1073812480 + 375 0068 FFFCFFFF .word -769 + 376 .cfi_endproc + 377 .LFE213: + 379 .section .text.LL_TIM_OC_StructInit,"ax",%progbits + 380 .align 1 + 381 .global LL_TIM_OC_StructInit + 382 .syntax unified + 383 .code 16 + 384 .thumb_func + 385 .fpu softvfp + 387 LL_TIM_OC_StructInit: + 388 .LFB214: + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Set the fields of the TIMx output channel configuration data + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * structure to their default values. + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval None + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 389 .loc 1 283 0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 @ link register save eliminated. + 394 .LVL34: + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + 395 .loc 1 285 0 + 396 0000 0023 movs r3, #0 + 397 0002 0360 str r3, [r0] + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + 398 .loc 1 286 0 + ARM GAS /tmp/cc5G6dGG.s page 86 + + + 399 0004 4360 str r3, [r0, #4] + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U; + 400 .loc 1 287 0 + 401 0006 8360 str r3, [r0, #8] + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + 402 .loc 1 288 0 + 403 0008 C360 str r3, [r0, #12] + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 404 .loc 1 289 0 + 405 @ sp needed + 406 000a 7047 bx lr + 407 .cfi_endproc + 408 .LFE214: + 410 .section .text.LL_TIM_OC_Init,"ax",%progbits + 411 .align 1 + 412 .global LL_TIM_OC_Init + 413 .syntax unified + 414 .code 16 + 415 .thumb_func + 416 .fpu softvfp + 418 LL_TIM_OC_Init: + 419 .LFB215: + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx output channel. + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param Channel This parameter can be one of the following values: + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH1 + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH2 + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH3 + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH4 + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channe + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx output channel is initialized + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: TIMx output channel is not initialized + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitS + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 420 .loc 1 305 0 + 421 .cfi_startproc + 422 @ args = 0, pretend = 0, frame = 0 + 423 @ frame_needed = 0, uses_anonymous_args = 0 + 424 .LVL35: + 425 0000 70B5 push {r4, r5, r6, lr} + 426 .LCFI0: + 427 .cfi_def_cfa_offset 16 + 428 .cfi_offset 4, -16 + 429 .cfi_offset 5, -12 + 430 .cfi_offset 6, -8 + 431 .cfi_offset 14, -4 + 432 .LVL36: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus result = ERROR; + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** switch (Channel) + 433 .loc 1 308 0 + 434 0002 1029 cmp r1, #16 + 435 0004 40D0 beq .L28 + ARM GAS /tmp/cc5G6dGG.s page 87 + + + 436 0006 24D9 bls .L34 + 437 0008 8023 movs r3, #128 + 438 000a 5B00 lsls r3, r3, #1 + 439 000c 9942 cmp r1, r3 + 440 000e 57D0 beq .L31 + 441 0010 8023 movs r3, #128 + 442 0012 5B01 lsls r3, r3, #5 + 443 0014 9942 cmp r1, r3 + 444 0016 00D0 beq .LCB386 + 445 0018 6DE0 b .L33 @long jump + 446 .LCB386: + 447 .LVL37: + 448 .LBB96: + 449 .LBB97: + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH1: + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = OC1Config(TIMx, TIM_OC_InitStruct); + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = OC2Config(TIMx, TIM_OC_InitStruct); + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = OC3Config(TIMx, TIM_OC_InitStruct); + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = OC4Config(TIMx, TIM_OC_InitStruct); + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** default: + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return result; + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Set the fields of the TIMx input channel configuration data + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * structure to their default values. + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel c + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval None + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx input channel. + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param Channel This parameter can be one of the following values: + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH1 + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH2 + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH3 + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH4 + ARM GAS /tmp/cc5G6dGG.s page 88 + + + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx output channel is initialized + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: TIMx output channel is not initialized + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitS + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus result = ERROR; + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** switch (Channel) + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH1: + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = IC1Config(TIMx, TIM_IC_InitStruct); + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = IC2Config(TIMx, TIM_IC_InitStruct); + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = IC3Config(TIMx, TIM_IC_InitStruct); + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** result = IC4Config(TIMx, TIM_IC_InitStruct); + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** default: + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return result; + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Fills each TIM_EncoderInitStruct field with its default value + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder i + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval None + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the encoder interface of the timer instance. + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx enco + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + ARM GAS /tmp/cc5G6dGG.s page 89 + + + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruc + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr1 = 0U; + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccer = 0U; + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Configure TI1 */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Configure TI2 */ + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set encoder mode */ + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCER */ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + ARM GAS /tmp/cc5G6dGG.s page 90 + + + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @} + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @} + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Functions TIM Private Functions + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Private functions + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @{ + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx output channel 1. + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr1 = 0U; + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccer = 0U; + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpcr2 = 0U; + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output Compare Mode */ + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output Compare Polarity */ + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output State */ + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CR2 */ + ARM GAS /tmp/cc5G6dGG.s page 91 + + + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCER */ + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx output channel 2. + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr1 = 0U; + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccer = 0U; + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpcr2 = 0U; + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + 571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Output Compare Mode */ + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + 574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output Compare Polarity */ + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + 577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output State */ + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + ARM GAS /tmp/cc5G6dGG.s page 92 + + + 580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CR2 */ + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + 589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCER */ + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx output channel 3. + 598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + 600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr2 = 0U; + 607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccer = 0U; + 608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpcr2 = 0U; + 609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + 612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + 618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCMR2 register value */ + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + 627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + 630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Output Compare Mode */ + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + 633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output Compare Polarity */ + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + 636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + ARM GAS /tmp/cc5G6dGG.s page 93 + + + 637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output State */ + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + 639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CR2 */ + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCMR2 */ + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + 645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + 648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCER */ + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx output channel 4. + 657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + 659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr2 = 0U; + 666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccer = 0U; + 667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpcr2 = 0U; + 668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + 671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ + 676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + 450 .loc 1 676 0 + 451 001a 016A ldr r1, [r0, #32] + 452 .LVL38: + 453 001c 374E ldr r6, .L35 + 454 001e 3140 ands r1, r6 + 455 0020 0162 str r1, [r0, #32] + 677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 456 .loc 1 679 0 + 457 0022 036A ldr r3, [r0, #32] + 458 .LVL39: + 680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 459 .loc 1 682 0 + 460 0024 4568 ldr r5, [r0, #4] + ARM GAS /tmp/cc5G6dGG.s page 94 + + + 461 .LVL40: + 683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Get the TIMx CCMR2 register value */ + 685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + 462 .loc 1 685 0 + 463 0026 C169 ldr r1, [r0, #28] + 464 .LVL41: + 686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + 689:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 690:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Output Compare Mode */ + 691:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + 465 .loc 1 691 0 + 466 0028 354C ldr r4, .L35+4 + 467 002a 2140 ands r1, r4 + 468 .LVL42: + 469 002c 1468 ldr r4, [r2] + 470 002e 2402 lsls r4, r4, #8 + 471 0030 2143 orrs r1, r4 + 472 .LVL43: + 692:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 693:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output Compare Polarity */ + 694:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + 473 .loc 1 694 0 + 474 0032 344C ldr r4, .L35+8 + 475 0034 2340 ands r3, r4 + 476 .LVL44: + 477 0036 D468 ldr r4, [r2, #12] + 478 0038 2403 lsls r4, r4, #12 + 479 003a 2343 orrs r3, r4 + 480 .LVL45: + 695:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 696:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Output State */ + 697:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + 481 .loc 1 697 0 + 482 003c 3340 ands r3, r6 + 483 .LVL46: + 484 003e 5468 ldr r4, [r2, #4] + 485 0040 2403 lsls r4, r4, #12 + 486 0042 2343 orrs r3, r4 + 487 .LVL47: + 698:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 699:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CR2 */ + 700:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 488 .loc 1 700 0 + 489 0044 4560 str r5, [r0, #4] + 701:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 702:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCMR2 */ + 703:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + 490 .loc 1 703 0 + 491 0046 C161 str r1, [r0, #28] + 704:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 705:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 706:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + 492 .loc 1 706 0 + 493 0048 9268 ldr r2, [r2, #8] + ARM GAS /tmp/cc5G6dGG.s page 95 + + + 494 .LVL48: + 495 .LBB98: + 496 .LBB99: +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 497 .loc 3 1726 0 + 498 004a 0264 str r2, [r0, #64] + 499 .LVL49: + 500 .LBE99: + 501 .LBE98: + 707:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 708:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Write to TIMx CCER */ + 709:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 502 .loc 1 709 0 + 503 004c 0362 str r3, [r0, #32] + 504 .LVL50: + 505 .LBE97: + 506 .LBE96: + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 507 .loc 1 320 0 + 508 004e 0120 movs r0, #1 + 509 .LVL51: + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** default: + 510 .loc 1 321 0 + 511 0050 19E0 b .L27 + 512 .LVL52: + 513 .L34: + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 514 .loc 1 308 0 + 515 0052 0129 cmp r1, #1 + 516 0054 4FD1 bne .L33 + 517 .LVL53: + 518 .LBB100: + 519 .LBB101: + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 520 .loc 1 499 0 + 521 0056 036A ldr r3, [r0, #32] + 522 0058 0124 movs r4, #1 + 523 005a A343 bics r3, r4 + 524 005c 0362 str r3, [r0, #32] + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 525 .loc 1 502 0 + 526 005e 036A ldr r3, [r0, #32] + 527 .LVL54: + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 528 .loc 1 505 0 + 529 0060 4568 ldr r5, [r0, #4] + 530 .LVL55: + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 531 .loc 1 508 0 + 532 0062 8169 ldr r1, [r0, #24] + 533 .LVL56: + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 534 .loc 1 514 0 + 535 0064 7326 movs r6, #115 + 536 0066 B143 bics r1, r6 + 537 .LVL57: + 538 0068 1668 ldr r6, [r2] + ARM GAS /tmp/cc5G6dGG.s page 96 + + + 539 006a 3143 orrs r1, r6 + 540 .LVL58: + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 541 .loc 1 517 0 + 542 006c 0226 movs r6, #2 + 543 006e B343 bics r3, r6 + 544 .LVL59: + 545 0070 D668 ldr r6, [r2, #12] + 546 0072 3343 orrs r3, r6 + 547 .LVL60: + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 548 .loc 1 520 0 + 549 0074 A343 bics r3, r4 + 550 .LVL61: + 551 0076 5468 ldr r4, [r2, #4] + 552 0078 2343 orrs r3, r4 + 553 .LVL62: + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 554 .loc 1 523 0 + 555 007a 4560 str r5, [r0, #4] + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 556 .loc 1 526 0 + 557 007c 8161 str r1, [r0, #24] + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 558 .loc 1 529 0 + 559 007e 9268 ldr r2, [r2, #8] + 560 .LVL63: + 561 .LBB102: + 562 .LBB103: +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 563 .loc 3 1684 0 + 564 0080 4263 str r2, [r0, #52] + 565 .LVL64: + 566 .LBE103: + 567 .LBE102: + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 568 .loc 1 532 0 + 569 0082 0362 str r3, [r0, #32] + 570 .LVL65: + 571 .LBE101: + 572 .LBE100: + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 573 .loc 1 311 0 + 574 0084 0120 movs r0, #1 + 575 .LVL66: + 576 .L27: + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 577 .loc 1 327 0 + 578 @ sp needed + 579 0086 70BD pop {r4, r5, r6, pc} + 580 .LVL67: + 581 .L28: + 582 .LBB104: + 583 .LBB105: + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 584 .loc 1 558 0 + 585 0088 036A ldr r3, [r0, #32] + ARM GAS /tmp/cc5G6dGG.s page 97 + + + 586 008a 1026 movs r6, #16 + 587 008c B343 bics r3, r6 + 588 008e 0362 str r3, [r0, #32] + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 589 .loc 1 561 0 + 590 0090 036A ldr r3, [r0, #32] + 591 .LVL68: + 564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 592 .loc 1 564 0 + 593 0092 4568 ldr r5, [r0, #4] + 594 .LVL69: + 567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 595 .loc 1 567 0 + 596 0094 8169 ldr r1, [r0, #24] + 597 .LVL70: + 573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 598 .loc 1 573 0 + 599 0096 1A4C ldr r4, .L35+4 + 600 0098 2140 ands r1, r4 + 601 .LVL71: + 602 009a 1468 ldr r4, [r2] + 603 009c 2402 lsls r4, r4, #8 + 604 009e 2143 orrs r1, r4 + 605 .LVL72: + 576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 606 .loc 1 576 0 + 607 00a0 2024 movs r4, #32 + 608 00a2 A343 bics r3, r4 + 609 .LVL73: + 610 00a4 D468 ldr r4, [r2, #12] + 611 00a6 2401 lsls r4, r4, #4 + 612 00a8 2343 orrs r3, r4 + 613 .LVL74: + 579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 614 .loc 1 579 0 + 615 00aa B343 bics r3, r6 + 616 .LVL75: + 617 00ac 5468 ldr r4, [r2, #4] + 618 00ae 2401 lsls r4, r4, #4 + 619 00b0 2343 orrs r3, r4 + 620 .LVL76: + 582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 621 .loc 1 582 0 + 622 00b2 4560 str r5, [r0, #4] + 585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 623 .loc 1 585 0 + 624 00b4 8161 str r1, [r0, #24] + 588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 625 .loc 1 588 0 + 626 00b6 9268 ldr r2, [r2, #8] + 627 .LVL77: + 628 .LBB106: + 629 .LBB107: +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 630 .loc 3 1698 0 + 631 00b8 8263 str r2, [r0, #56] + 632 .LVL78: + ARM GAS /tmp/cc5G6dGG.s page 98 + + + 633 .LBE107: + 634 .LBE106: + 591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 635 .loc 1 591 0 + 636 00ba 0362 str r3, [r0, #32] + 637 .LVL79: + 638 .LBE105: + 639 .LBE104: + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 640 .loc 1 314 0 + 641 00bc 0120 movs r0, #1 + 642 .LVL80: + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 643 .loc 1 315 0 + 644 00be E2E7 b .L27 + 645 .LVL81: + 646 .L31: + 647 .LBB108: + 648 .LBB109: + 617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 649 .loc 1 617 0 + 650 00c0 016A ldr r1, [r0, #32] + 651 .LVL82: + 652 00c2 114E ldr r6, .L35+12 + 653 00c4 3140 ands r1, r6 + 654 00c6 0162 str r1, [r0, #32] + 620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 655 .loc 1 620 0 + 656 00c8 036A ldr r3, [r0, #32] + 657 .LVL83: + 623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 658 .loc 1 623 0 + 659 00ca 4568 ldr r5, [r0, #4] + 660 .LVL84: + 626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 661 .loc 1 626 0 + 662 00cc C169 ldr r1, [r0, #28] + 663 .LVL85: + 632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 664 .loc 1 632 0 + 665 00ce 7324 movs r4, #115 + 666 00d0 A143 bics r1, r4 + 667 .LVL86: + 668 00d2 1468 ldr r4, [r2] + 669 00d4 2143 orrs r1, r4 + 670 .LVL87: + 635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 671 .loc 1 635 0 + 672 00d6 0D4C ldr r4, .L35+16 + 673 00d8 2340 ands r3, r4 + 674 .LVL88: + 675 00da D468 ldr r4, [r2, #12] + 676 00dc 2402 lsls r4, r4, #8 + 677 00de 2343 orrs r3, r4 + 678 .LVL89: + 638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 679 .loc 1 638 0 + ARM GAS /tmp/cc5G6dGG.s page 99 + + + 680 00e0 3340 ands r3, r6 + 681 .LVL90: + 682 00e2 5468 ldr r4, [r2, #4] + 683 00e4 2402 lsls r4, r4, #8 + 684 00e6 2343 orrs r3, r4 + 685 .LVL91: + 641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 686 .loc 1 641 0 + 687 00e8 4560 str r5, [r0, #4] + 644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 688 .loc 1 644 0 + 689 00ea C161 str r1, [r0, #28] + 647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 690 .loc 1 647 0 + 691 00ec 9268 ldr r2, [r2, #8] + 692 .LVL92: + 693 .LBB110: + 694 .LBB111: +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 695 .loc 3 1712 0 + 696 00ee C263 str r2, [r0, #60] + 697 .LVL93: + 698 .LBE111: + 699 .LBE110: + 650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 700 .loc 1 650 0 + 701 00f0 0362 str r3, [r0, #32] + 702 .LVL94: + 703 .LBE109: + 704 .LBE108: + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 705 .loc 1 317 0 + 706 00f2 0120 movs r0, #1 + 707 .LVL95: + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 708 .loc 1 318 0 + 709 00f4 C7E7 b .L27 + 710 .LVL96: + 711 .L33: + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 712 .loc 1 306 0 + 713 00f6 0020 movs r0, #0 + 714 .LVL97: + 715 00f8 C5E7 b .L27 + 716 .L36: + 717 00fa C046 .align 2 + 718 .L35: + 719 00fc FFEFFFFF .word -4097 + 720 0100 FF8CFFFF .word -29441 + 721 0104 FFDFFFFF .word -8193 + 722 0108 FFFEFFFF .word -257 + 723 010c FFFDFFFF .word -513 + 724 .cfi_endproc + 725 .LFE215: + 727 .section .text.LL_TIM_IC_StructInit,"ax",%progbits + 728 .align 1 + 729 .global LL_TIM_IC_StructInit + ARM GAS /tmp/cc5G6dGG.s page 100 + + + 730 .syntax unified + 731 .code 16 + 732 .thumb_func + 733 .fpu softvfp + 735 LL_TIM_IC_StructInit: + 736 .LFB216: + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 737 .loc 1 336 0 + 738 .cfi_startproc + 739 @ args = 0, pretend = 0, frame = 0 + 740 @ frame_needed = 0, uses_anonymous_args = 0 + 741 @ link register save eliminated. + 742 .LVL98: + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 743 .loc 1 338 0 + 744 0000 0023 movs r3, #0 + 745 0002 0360 str r3, [r0] + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + 746 .loc 1 339 0 + 747 0004 8022 movs r2, #128 + 748 0006 5202 lsls r2, r2, #9 + 749 0008 4260 str r2, [r0, #4] + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; + 750 .loc 1 340 0 + 751 000a 8360 str r3, [r0, #8] + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 752 .loc 1 341 0 + 753 000c C360 str r3, [r0, #12] + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 754 .loc 1 342 0 + 755 @ sp needed + 756 000e 7047 bx lr + 757 .cfi_endproc + 758 .LFE216: + 760 .section .text.LL_TIM_IC_Init,"ax",%progbits + 761 .align 1 + 762 .global LL_TIM_IC_Init + 763 .syntax unified + 764 .code 16 + 765 .thumb_func + 766 .fpu softvfp + 768 LL_TIM_IC_Init: + 769 .LFB217: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ErrorStatus result = ERROR; + 770 .loc 1 358 0 + 771 .cfi_startproc + 772 @ args = 0, pretend = 0, frame = 0 + 773 @ frame_needed = 0, uses_anonymous_args = 0 + 774 .LVL99: + 775 0000 30B5 push {r4, r5, lr} + 776 .LCFI1: + 777 .cfi_def_cfa_offset 12 + 778 .cfi_offset 4, -12 + 779 .cfi_offset 5, -8 + 780 .cfi_offset 14, -4 + 781 .LVL100: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + ARM GAS /tmp/cc5G6dGG.s page 101 + + + 782 .loc 1 361 0 + 783 0002 1029 cmp r1, #16 + 784 0004 3DD0 beq .L40 + 785 0006 22D9 bls .L46 + 786 0008 8023 movs r3, #128 + 787 000a 5B00 lsls r3, r3, #1 + 788 000c 9942 cmp r1, r3 + 789 000e 51D0 beq .L43 + 790 0010 8023 movs r3, #128 + 791 0012 5B01 lsls r3, r3, #5 + 792 0014 9942 cmp r1, r3 + 793 0016 69D1 bne .L45 + 794 .LVL101: + 795 .LBB112: + 796 .LBB113: + 710:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 711:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 712:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 713:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 714:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 715:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 716:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx input channel 1. + 717:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 718:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + 719:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 720:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 721:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 722:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 723:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 724:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 725:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 726:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + 727:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 728:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 729:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 730:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 731:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 732:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + 734:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 735:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR1, + 737:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + 738:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr + 739:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 740:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Polarity and set the CC1E Bit */ + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 742:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC1P | TIM_CCER_CC1NP), + 743:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + 744:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 745:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 746:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 747:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 748:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 749:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx input channel 2. + 750:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 751:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + ARM GAS /tmp/cc5G6dGG.s page 102 + + + 752:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 753:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 754:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 755:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 756:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 757:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 758:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 759:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + 760:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 761:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 762:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 763:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 764:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 765:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + 767:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 768:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR1, + 770:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + 771:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr + 772:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 773:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Polarity and set the CC2E Bit */ + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 775:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC2P | TIM_CCER_CC2NP), + 776:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + 777:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 778:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 779:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 780:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 781:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 782:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx input channel 3. + 783:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 784:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + 785:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 786:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 787:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 788:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 789:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 790:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 791:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 792:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + 793:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 794:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 795:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 796:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 797:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 798:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + 800:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 801:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR2, + 803:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + 804:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr + 805:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 806:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Polarity and set the CC3E Bit */ + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 808:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ARM GAS /tmp/cc5G6dGG.s page 103 + + + 809:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + 810:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 811:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** return SUCCESS; + 812:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 813:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 814:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /** + 815:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @brief Configure the TIMx input channel 4. + 816:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIMx Timer Instance + 817:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + 818:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 819:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 820:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** * - ERROR: not applicable + 821:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** */ + 822:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 823:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 824:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Check the parameters */ + 825:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + 826:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 827:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 828:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 829:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 830:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 831:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ + 832:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + 797 .loc 1 832 0 + 798 0018 036A ldr r3, [r0, #32] + 799 001a 3549 ldr r1, .L47 + 800 .LVL102: + 801 001c 0B40 ands r3, r1 + 802 001e 0362 str r3, [r0, #32] + 833:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 834:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ + 835:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR2, + 803 .loc 1 835 0 + 804 0020 C369 ldr r3, [r0, #28] + 805 0022 3449 ldr r1, .L47+4 + 806 0024 1940 ands r1, r3 + 807 0026 5368 ldr r3, [r2, #4] + 808 0028 D468 ldr r4, [r2, #12] + 809 002a 2343 orrs r3, r4 + 810 002c 9468 ldr r4, [r2, #8] + 811 002e 2343 orrs r3, r4 + 812 0030 1B0A lsrs r3, r3, #8 + 813 0032 0B43 orrs r3, r1 + 814 0034 C361 str r3, [r0, #28] + 836:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + 837:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr + 838:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 839:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Select the Polarity and set the CC2E Bit */ + 840:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 815 .loc 1 840 0 + 816 0036 036A ldr r3, [r0, #32] + 817 0038 2F49 ldr r1, .L47+8 + 818 003a 0B40 ands r3, r1 + 819 003c 1268 ldr r2, [r2] + 820 .LVL103: + 821 003e 1203 lsls r2, r2, #12 + ARM GAS /tmp/cc5G6dGG.s page 104 + + + 822 0040 1343 orrs r3, r2 + 823 0042 8022 movs r2, #128 + 824 0044 5201 lsls r2, r2, #5 + 825 0046 1343 orrs r3, r2 + 826 0048 0362 str r3, [r0, #32] + 827 .LVL104: + 828 .LBE113: + 829 .LBE112: + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 830 .loc 1 373 0 + 831 004a 0120 movs r0, #1 + 832 .LVL105: + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** default: + 833 .loc 1 374 0 + 834 004c 18E0 b .L39 + 835 .LVL106: + 836 .L46: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** { + 837 .loc 1 361 0 + 838 004e 0129 cmp r1, #1 + 839 0050 4CD1 bne .L45 + 840 .LVL107: + 841 .LBB114: + 842 .LBB115: + 733:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 843 .loc 1 733 0 + 844 0052 016A ldr r1, [r0, #32] + 845 .LVL108: + 846 0054 0125 movs r5, #1 + 847 0056 A943 bics r1, r5 + 848 0058 0162 str r1, [r0, #32] + 736:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + 849 .loc 1 736 0 + 850 005a 8469 ldr r4, [r0, #24] + 851 005c FF23 movs r3, #255 + 852 005e 9C43 bics r4, r3 + 853 0060 5168 ldr r1, [r2, #4] + 854 0062 D368 ldr r3, [r2, #12] + 855 0064 1943 orrs r1, r3 + 856 0066 9368 ldr r3, [r2, #8] + 857 0068 1943 orrs r1, r3 + 858 006a 090C lsrs r1, r1, #16 + 859 006c 2143 orrs r1, r4 + 860 006e 8161 str r1, [r0, #24] + 741:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC1P | TIM_CCER_CC1NP), + 861 .loc 1 741 0 + 862 0070 036A ldr r3, [r0, #32] + 863 0072 0A21 movs r1, #10 + 864 0074 8B43 bics r3, r1 + 865 0076 1268 ldr r2, [r2] + 866 .LVL109: + 867 0078 1343 orrs r3, r2 + 868 007a 2B43 orrs r3, r5 + 869 007c 0362 str r3, [r0, #32] + 870 .LVL110: + 871 .LBE115: + 872 .LBE114: + ARM GAS /tmp/cc5G6dGG.s page 105 + + + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 873 .loc 1 364 0 + 874 007e 0120 movs r0, #1 + 875 .LVL111: + 876 .L39: + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 877 .loc 1 380 0 + 878 @ sp needed + 879 0080 30BD pop {r4, r5, pc} + 880 .LVL112: + 881 .L40: + 882 .LBB116: + 883 .LBB117: + 766:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 884 .loc 1 766 0 + 885 0082 036A ldr r3, [r0, #32] + 886 0084 1025 movs r5, #16 + 887 0086 AB43 bics r3, r5 + 888 0088 0362 str r3, [r0, #32] + 769:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + 889 .loc 1 769 0 + 890 008a 8169 ldr r1, [r0, #24] + 891 .LVL113: + 892 008c 194C ldr r4, .L47+4 + 893 008e 0C40 ands r4, r1 + 894 0090 5168 ldr r1, [r2, #4] + 895 0092 D368 ldr r3, [r2, #12] + 896 0094 1943 orrs r1, r3 + 897 0096 9368 ldr r3, [r2, #8] + 898 0098 1943 orrs r1, r3 + 899 009a 090A lsrs r1, r1, #8 + 900 009c 2143 orrs r1, r4 + 901 009e 8161 str r1, [r0, #24] + 774:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC2P | TIM_CCER_CC2NP), + 902 .loc 1 774 0 + 903 00a0 036A ldr r3, [r0, #32] + 904 00a2 A021 movs r1, #160 + 905 00a4 8B43 bics r3, r1 + 906 00a6 1268 ldr r2, [r2] + 907 .LVL114: + 908 00a8 1201 lsls r2, r2, #4 + 909 00aa 1343 orrs r3, r2 + 910 00ac 2B43 orrs r3, r5 + 911 00ae 0362 str r3, [r0, #32] + 912 .LVL115: + 913 .LBE117: + 914 .LBE116: + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 915 .loc 1 367 0 + 916 00b0 0120 movs r0, #1 + 917 .LVL116: + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 918 .loc 1 368 0 + 919 00b2 E5E7 b .L39 + 920 .LVL117: + 921 .L43: + 922 .LBB118: + ARM GAS /tmp/cc5G6dGG.s page 106 + + + 923 .LBB119: + 799:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 924 .loc 1 799 0 + 925 00b4 036A ldr r3, [r0, #32] + 926 00b6 1149 ldr r1, .L47+12 + 927 .LVL118: + 928 00b8 0B40 ands r3, r1 + 929 00ba 0362 str r3, [r0, #32] + 802:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + 930 .loc 1 802 0 + 931 00bc C369 ldr r3, [r0, #28] + 932 00be FF21 movs r1, #255 + 933 00c0 8B43 bics r3, r1 + 934 00c2 1900 movs r1, r3 + 935 00c4 5368 ldr r3, [r2, #4] + 936 00c6 D468 ldr r4, [r2, #12] + 937 00c8 2343 orrs r3, r4 + 938 00ca 9468 ldr r4, [r2, #8] + 939 00cc 2343 orrs r3, r4 + 940 00ce 1B0C lsrs r3, r3, #16 + 941 00d0 0B43 orrs r3, r1 + 942 00d2 C361 str r3, [r0, #28] + 807:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** (TIM_CCER_CC3P | TIM_CCER_CC3NP), + 943 .loc 1 807 0 + 944 00d4 036A ldr r3, [r0, #32] + 945 00d6 0A49 ldr r1, .L47+16 + 946 00d8 0B40 ands r3, r1 + 947 00da 1268 ldr r2, [r2] + 948 .LVL119: + 949 00dc 1202 lsls r2, r2, #8 + 950 00de 1343 orrs r3, r2 + 951 00e0 8022 movs r2, #128 + 952 00e2 5200 lsls r2, r2, #1 + 953 00e4 1343 orrs r3, r2 + 954 00e6 0362 str r3, [r0, #32] + 955 .LVL120: + 956 .LBE119: + 957 .LBE118: + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** break; + 958 .loc 1 370 0 + 959 00e8 0120 movs r0, #1 + 960 .LVL121: + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 961 .loc 1 371 0 + 962 00ea C9E7 b .L39 + 963 .LVL122: + 964 .L45: + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 965 .loc 1 359 0 + 966 00ec 0020 movs r0, #0 + 967 .LVL123: + 968 00ee C7E7 b .L39 + 969 .L48: + 970 .align 2 + 971 .L47: + 972 00f0 FFEFFFFF .word -4097 + 973 00f4 FF00FFFF .word -65281 + ARM GAS /tmp/cc5G6dGG.s page 107 + + + 974 00f8 FF5FFFFF .word -40961 + 975 00fc FFFEFFFF .word -257 + 976 0100 FFF5FFFF .word -2561 + 977 .cfi_endproc + 978 .LFE217: + 980 .section .text.LL_TIM_ENCODER_StructInit,"ax",%progbits + 981 .align 1 + 982 .global LL_TIM_ENCODER_StructInit + 983 .syntax unified + 984 .code 16 + 985 .thumb_func + 986 .fpu softvfp + 988 LL_TIM_ENCODER_StructInit: + 989 .LFB218: + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** /* Set the default configuration */ + 990 .loc 1 388 0 + 991 .cfi_startproc + 992 @ args = 0, pretend = 0, frame = 0 + 993 @ frame_needed = 0, uses_anonymous_args = 0 + 994 @ link register save eliminated. + 995 .LVL124: + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 996 .loc 1 390 0 + 997 0000 0123 movs r3, #1 + 998 0002 0360 str r3, [r0] + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 999 .loc 1 391 0 + 1000 0004 0023 movs r3, #0 + 1001 0006 4360 str r3, [r0, #4] + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 1002 .loc 1 392 0 + 1003 0008 8022 movs r2, #128 + 1004 000a 5202 lsls r2, r2, #9 + 1005 000c 8260 str r2, [r0, #8] + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 1006 .loc 1 393 0 + 1007 000e C360 str r3, [r0, #12] + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + 1008 .loc 1 394 0 + 1009 0010 0361 str r3, [r0, #16] + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 1010 .loc 1 395 0 + 1011 0012 4361 str r3, [r0, #20] + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + 1012 .loc 1 396 0 + 1013 0014 8261 str r2, [r0, #24] + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; + 1014 .loc 1 397 0 + 1015 0016 C361 str r3, [r0, #28] + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** } + 1016 .loc 1 398 0 + 1017 0018 0362 str r3, [r0, #32] + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1018 .loc 1 399 0 + 1019 @ sp needed + 1020 001a 7047 bx lr + 1021 .cfi_endproc + ARM GAS /tmp/cc5G6dGG.s page 108 + + + 1022 .LFE218: + 1024 .section .text.LL_TIM_ENCODER_Init,"ax",%progbits + 1025 .align 1 + 1026 .global LL_TIM_ENCODER_Init + 1027 .syntax unified + 1028 .code 16 + 1029 .thumb_func + 1030 .fpu softvfp + 1032 LL_TIM_ENCODER_Init: + 1033 .LFB219: + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** uint32_t tmpccmr1 = 0U; + 1034 .loc 1 410 0 + 1035 .cfi_startproc + 1036 @ args = 0, pretend = 0, frame = 0 + 1037 @ frame_needed = 0, uses_anonymous_args = 0 + 1038 .LVL125: + 1039 0000 30B5 push {r4, r5, lr} + 1040 .LCFI2: + 1041 .cfi_def_cfa_offset 12 + 1042 .cfi_offset 4, -12 + 1043 .cfi_offset 5, -8 + 1044 .cfi_offset 14, -4 + 1045 .LVL126: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1046 .loc 1 427 0 + 1047 0002 036A ldr r3, [r0, #32] + 1048 0004 1125 movs r5, #17 + 1049 0006 AB43 bics r3, r5 + 1050 0008 0362 str r3, [r0, #32] + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1051 .loc 1 430 0 + 1052 000a 8269 ldr r2, [r0, #24] + 1053 .LVL127: + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1054 .loc 1 433 0 + 1055 000c 036A ldr r3, [r0, #32] + 1056 .LVL128: + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + 1057 .loc 1 436 0 + 1058 000e FF24 movs r4, #255 + 1059 0010 A243 bics r2, r4 + 1060 .LVL129: + 1061 0012 1400 movs r4, r2 + 1062 .LVL130: + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 1063 .loc 1 437 0 + 1064 0014 4A89 ldrh r2, [r1, #10] + 1065 .LVL131: + 1066 0016 2243 orrs r2, r4 + 1067 .LVL132: + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 1068 .loc 1 438 0 + 1069 0018 4C8A ldrh r4, [r1, #18] + 1070 001a 2243 orrs r2, r4 + 1071 .LVL133: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1072 .loc 1 439 0 + ARM GAS /tmp/cc5G6dGG.s page 109 + + + 1073 001c CC89 ldrh r4, [r1, #14] + 1074 001e 1443 orrs r4, r2 + 1075 .LVL134: + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + 1076 .loc 1 442 0 + 1077 0020 0E4A ldr r2, .L51 + 1078 0022 1440 ands r4, r2 + 1079 .LVL135: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 1080 .loc 1 443 0 + 1081 0024 8A69 ldr r2, [r1, #24] + 1082 0026 120A lsrs r2, r2, #8 + 1083 0028 1443 orrs r4, r2 + 1084 .LVL136: + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 1085 .loc 1 444 0 + 1086 002a 0A6A ldr r2, [r1, #32] + 1087 002c 120A lsrs r2, r2, #8 + 1088 002e 2243 orrs r2, r4 + 1089 .LVL137: + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1090 .loc 1 445 0 + 1091 0030 CC69 ldr r4, [r1, #28] + 1092 0032 240A lsrs r4, r4, #8 + 1093 0034 2243 orrs r2, r4 + 1094 .LVL138: + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + 1095 .loc 1 448 0 + 1096 0036 AA24 movs r4, #170 + 1097 0038 A343 bics r3, r4 + 1098 .LVL139: + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 1099 .loc 1 449 0 + 1100 003a 4C68 ldr r4, [r1, #4] + 1101 003c 1C43 orrs r4, r3 + 1102 .LVL140: + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 1103 .loc 1 450 0 + 1104 003e 4B69 ldr r3, [r1, #20] + 1105 0040 1B01 lsls r3, r3, #4 + 1106 0042 2343 orrs r3, r4 + 1107 .LVL141: + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1108 .loc 1 451 0 + 1109 0044 2B43 orrs r3, r5 + 1110 .LVL142: + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1111 .loc 1 454 0 + 1112 0046 0968 ldr r1, [r1] + 1113 .LVL143: + 1114 .LBB120: + 1115 .LBB121: +2241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h **** } + 1116 .loc 3 2241 0 + 1117 0048 8468 ldr r4, [r0, #8] + 1118 004a 0A3D subs r5, r5, #10 + 1119 004c AC43 bics r4, r5 + ARM GAS /tmp/cc5G6dGG.s page 110 + + + 1120 004e 2143 orrs r1, r4 + 1121 .LVL144: + 1122 0050 8160 str r1, [r0, #8] + 1123 .LVL145: + 1124 .LBE121: + 1125 .LBE120: + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1126 .loc 1 457 0 + 1127 0052 8261 str r2, [r0, #24] + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1128 .loc 1 460 0 + 1129 0054 0362 str r3, [r0, #32] + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c **** + 1130 .loc 1 463 0 + 1131 0056 0120 movs r0, #1 + 1132 .LVL146: + 1133 @ sp needed + 1134 0058 30BD pop {r4, r5, pc} + 1135 .L52: + 1136 005a C046 .align 2 + 1137 .L51: + 1138 005c FF00FFFF .word -65281 + 1139 .cfi_endproc + 1140 .LFE219: + 1142 .text + 1143 .Letext0: + 1144 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1145 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1146 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 1147 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 1148 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 1149 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 1150 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 1151 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 1152 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/cc5G6dGG.s page 111 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_tim.c + /tmp/cc5G6dGG.s:16 .text.LL_TIM_DeInit:0000000000000000 $t + /tmp/cc5G6dGG.s:23 .text.LL_TIM_DeInit:0000000000000000 LL_TIM_DeInit + /tmp/cc5G6dGG.s:218 .text.LL_TIM_DeInit:00000000000000a4 $d + /tmp/cc5G6dGG.s:228 .text.LL_TIM_StructInit:0000000000000000 $t + /tmp/cc5G6dGG.s:235 .text.LL_TIM_StructInit:0000000000000000 LL_TIM_StructInit + /tmp/cc5G6dGG.s:261 .text.LL_TIM_Init:0000000000000000 $t + /tmp/cc5G6dGG.s:268 .text.LL_TIM_Init:0000000000000000 LL_TIM_Init + /tmp/cc5G6dGG.s:372 .text.LL_TIM_Init:000000000000005c $d + /tmp/cc5G6dGG.s:380 .text.LL_TIM_OC_StructInit:0000000000000000 $t + /tmp/cc5G6dGG.s:387 .text.LL_TIM_OC_StructInit:0000000000000000 LL_TIM_OC_StructInit + /tmp/cc5G6dGG.s:411 .text.LL_TIM_OC_Init:0000000000000000 $t + /tmp/cc5G6dGG.s:418 .text.LL_TIM_OC_Init:0000000000000000 LL_TIM_OC_Init + /tmp/cc5G6dGG.s:719 .text.LL_TIM_OC_Init:00000000000000fc $d + /tmp/cc5G6dGG.s:728 .text.LL_TIM_IC_StructInit:0000000000000000 $t + /tmp/cc5G6dGG.s:735 .text.LL_TIM_IC_StructInit:0000000000000000 LL_TIM_IC_StructInit + /tmp/cc5G6dGG.s:761 .text.LL_TIM_IC_Init:0000000000000000 $t + /tmp/cc5G6dGG.s:768 .text.LL_TIM_IC_Init:0000000000000000 LL_TIM_IC_Init + /tmp/cc5G6dGG.s:972 .text.LL_TIM_IC_Init:00000000000000f0 $d + /tmp/cc5G6dGG.s:981 .text.LL_TIM_ENCODER_StructInit:0000000000000000 $t + /tmp/cc5G6dGG.s:988 .text.LL_TIM_ENCODER_StructInit:0000000000000000 LL_TIM_ENCODER_StructInit + /tmp/cc5G6dGG.s:1025 .text.LL_TIM_ENCODER_Init:0000000000000000 $t + /tmp/cc5G6dGG.s:1032 .text.LL_TIM_ENCODER_Init:0000000000000000 LL_TIM_ENCODER_Init + /tmp/cc5G6dGG.s:1138 .text.LL_TIM_ENCODER_Init:000000000000005c $d + .debug_frame:0000000000000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32l0xx_ll_usart.d b/build/stm32l0xx_ll_usart.d new file mode 100644 index 0000000..ab4cff8 --- /dev/null +++ b/build/stm32l0xx_ll_usart.d @@ -0,0 +1,112 @@ +build/stm32l0xx_ll_usart.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/build/stm32l0xx_ll_usart.lst b/build/stm32l0xx_ll_usart.lst new file mode 100644 index 0000000..e8e96c8 --- /dev/null +++ b/build/stm32l0xx_ll_usart.lst @@ -0,0 +1,3748 @@ +ARM GAS /tmp/ccZXt8KR.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_usart.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_USART_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_USART_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_USART_DeInit: + 24 .LFB413: + 25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @file stm32l0xx_ll_usart.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief USART LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ****************************************************************************** + ARM GAS /tmp/ccZXt8KR.s page 2 + + + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USE_FULL_LL_DRIVER) + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Includes ------------------------------------------------------------------*/ + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #include "stm32l0xx_ll_usart.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #include "stm32l0xx_ll_rcc.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #include "stm32l0xx_ll_bus.h" + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #ifdef USE_FULL_ASSERT + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #include "stm32_assert.h" + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #else + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define assert_param(expr) ((void)0U) + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup STM32L0xx_LL_Driver + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5) + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup USART_LL + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Private types -------------------------------------------------------------*/ + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Private variables ---------------------------------------------------------*/ + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Private constants ---------------------------------------------------------*/ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Constants + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @} + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Private macros ------------------------------------------------------------*/ + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Macros + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * divided by the smallest oversampling used on the USART (i.e. 8) */ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U) + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PARITY_ODD)) + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + ARM GAS /tmp/ccZXt8KR.s page 3 + + + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_1) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_2)) + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @} + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Private function prototypes -----------------------------------------------*/ + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Exported functions --------------------------------------------------------*/ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup USART_LL_Exported_Functions + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** @addtogroup USART_LL_EF_Init + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @{ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief De-initialize USART registers (Registers restored to their default values). + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USARTx USART Instance + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - SUCCESS: USART registers are de-initialized + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - ERROR: USART registers are not de-initialized + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 26 .loc 1 139 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus status = SUCCESS; + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + ARM GAS /tmp/ccZXt8KR.s page 4 + + + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Check the parameters */ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART1) + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (USARTx == USART1) + 32 .loc 1 146 0 + 33 0000 1E4B ldr r3, .L11 + 34 0002 9842 cmp r0, r3 + 35 0004 0AD0 beq .L7 + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Force reset of USART clock */ + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Release reset of USART clock */ + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART1 */ + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART1) + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART2) + 36 .loc 1 156 0 + 37 0006 1E4B ldr r3, .L11+4 + 38 0008 9842 cmp r0, r3 + 39 000a 13D0 beq .L8 + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #else + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (USARTx == USART2) + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Force reset of USART clock */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Release reset of USART clock */ + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART4) + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART4) + 40 .loc 1 168 0 + 41 000c 1D4B ldr r3, .L11+8 + 42 000e 9842 cmp r0, r3 + 43 0010 1CD0 beq .L9 + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Force reset of USART clock */ + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4); + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Release reset of USART clock */ + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4); + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART4 */ + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART5) + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART5) + 44 .loc 1 178 0 + 45 0012 1D4B ldr r3, .L11+12 + 46 0014 9842 cmp r0, r3 + 47 0016 25D0 beq .L10 + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Force reset of USART clock */ + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5); + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + ARM GAS /tmp/ccZXt8KR.s page 5 + + + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Release reset of USART clock */ + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5); + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART5 */ + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** status = ERROR; + 48 .loc 1 189 0 + 49 0018 0020 movs r0, #0 + 50 .LVL1: + 51 001a 0AE0 b .L3 + 52 .LVL2: + 53 .L7: + 54 .LBB30: + 55 .LBB31: + 56 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @file stm32l0xx_ll_bus.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** [..] + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @attention + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * Redistribution and use in source and binary forms, with or without modification, + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * are permitted provided that the following conditions are met: + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 1. Redistributions of source code must retain the above copyright notice, + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * this list of conditions and the following disclaimer in the documentation + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * and/or other materials provided with the distribution. + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * may be used to endorse or promote products derived from this software + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * without specific prior written permission. + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + ARM GAS /tmp/ccZXt8KR.s page 6 + + + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** ****************************************************************************** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifndef __STM32L0xx_LL_BUS_H + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define __STM32L0xx_LL_BUS_H + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #ifdef __cplusplus + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** extern "C" { + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #include "stm32l0xx.h" + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @addtogroup STM32L0xx_LL_Driver + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RCC) + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TSC) + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*TSC*/ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(RNG) + ARM GAS /tmp/ccZXt8KR.s page 7 + + + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*RNG*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(AES) + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*AES*/ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM3) + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM6) + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM7) + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(LCD) + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*LCD*/ + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(SPI2) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART4) + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART5) + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C2) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USB) + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*USB*/ + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(CRS) + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*CRS*/ + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(DAC) + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(I2C3) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ + ARM GAS /tmp/ccZXt8KR.s page 8 + + + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(TIM22) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(USART1) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOD) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOD*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #if defined(GPIOH) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** #endif /*GPIOH*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + ARM GAS /tmp/ccZXt8KR.s page 9 + + + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + ARM GAS /tmp/ccZXt8KR.s page 10 + + + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccZXt8KR.s page 11 + + + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->AHBSMENR, Periphs); + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + ARM GAS /tmp/ccZXt8KR.s page 12 + + + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBSMENR, Periphs); + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + ARM GAS /tmp/ccZXt8KR.s page 13 + + + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + ARM GAS /tmp/ccZXt8KR.s page 14 + + + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + ARM GAS /tmp/ccZXt8KR.s page 15 + + + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB1 peripherals reset. + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + ARM GAS /tmp/ccZXt8KR.s page 16 + + + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB1 peripherals reset. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + ARM GAS /tmp/ccZXt8KR.s page 17 + + + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB1SMENR, Periphs); + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + ARM GAS /tmp/ccZXt8KR.s page 18 + + + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1SMENR, Periphs); + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @} + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @{ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + ARM GAS /tmp/ccZXt8KR.s page 19 + + + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __IO uint32_t tmpreg; + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** (void)tmpreg; + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + ARM GAS /tmp/ccZXt8KR.s page 20 + + + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_FW + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Force APB2 peripherals reset. + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 57 .loc 2 891 0 + 58 001c 1B4B ldr r3, .L11+16 + 59 001e 596A ldr r1, [r3, #36] + 60 0020 8022 movs r2, #128 + 61 0022 D201 lsls r2, r2, #7 + ARM GAS /tmp/ccZXt8KR.s page 21 + + + 62 0024 0A43 orrs r2, r1 + 63 0026 5A62 str r2, [r3, #36] + 64 .LVL3: + 65 .LBE31: + 66 .LBE30: + 67 .LBB32: + 68 .LBB33: + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** /** + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @brief Release APB2 peripherals reset. + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * (*) value not defined in all devices. + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** * @retval None + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** */ + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** { + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 69 .loc 2 918 0 + 70 0028 5A6A ldr r2, [r3, #36] + 71 002a 1949 ldr r1, .L11+20 + 72 002c 0A40 ands r2, r1 + 73 002e 5A62 str r2, [r3, #36] + 74 .LBE33: + 75 .LBE32: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 76 .loc 1 140 0 + 77 0030 0120 movs r0, #1 + 78 .LVL4: + 79 .L3: + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** return (status); + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 80 .loc 1 193 0 + 81 @ sp needed + 82 0032 7047 bx lr + 83 .LVL5: + 84 .L8: + 85 .LBB34: + 86 .LBB35: + ARM GAS /tmp/ccZXt8KR.s page 22 + + + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 87 .loc 2 613 0 + 88 0034 154B ldr r3, .L11+16 + 89 0036 996A ldr r1, [r3, #40] + 90 0038 8022 movs r2, #128 + 91 003a 9202 lsls r2, r2, #10 + 92 003c 0A43 orrs r2, r1 + 93 003e 9A62 str r2, [r3, #40] + 94 .LVL6: + 95 .LBE35: + 96 .LBE34: + 97 .LBB36: + 98 .LBB37: + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 99 .loc 2 664 0 + 100 0040 9A6A ldr r2, [r3, #40] + 101 0042 1449 ldr r1, .L11+24 + 102 0044 0A40 ands r2, r1 + 103 0046 9A62 str r2, [r3, #40] + 104 .LBE37: + 105 .LBE36: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 106 .loc 1 140 0 + 107 0048 0120 movs r0, #1 + 108 .LVL7: + 109 004a F2E7 b .L3 + 110 .LVL8: + 111 .L9: + 112 .LBB38: + 113 .LBB39: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 114 .loc 2 613 0 + 115 004c 0F4B ldr r3, .L11+16 + 116 004e 996A ldr r1, [r3, #40] + 117 0050 8022 movs r2, #128 + 118 0052 1203 lsls r2, r2, #12 + 119 0054 0A43 orrs r2, r1 + 120 0056 9A62 str r2, [r3, #40] + 121 .LVL9: + 122 .LBE39: + 123 .LBE38: + 124 .LBB40: + 125 .LBB41: + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 126 .loc 2 664 0 + 127 0058 9A6A ldr r2, [r3, #40] + 128 005a 0F49 ldr r1, .L11+28 + 129 005c 0A40 ands r2, r1 + 130 005e 9A62 str r2, [r3, #40] + 131 .LBE41: + 132 .LBE40: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 133 .loc 1 140 0 + 134 0060 0120 movs r0, #1 + 135 .LVL10: + 136 0062 E6E7 b .L3 + 137 .LVL11: + ARM GAS /tmp/ccZXt8KR.s page 23 + + + 138 .L10: + 139 .LBB42: + 140 .LBB43: + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 141 .loc 2 613 0 + 142 0064 094B ldr r3, .L11+16 + 143 0066 996A ldr r1, [r3, #40] + 144 0068 8022 movs r2, #128 + 145 006a 5203 lsls r2, r2, #13 + 146 006c 0A43 orrs r2, r1 + 147 006e 9A62 str r2, [r3, #40] + 148 .LVL12: + 149 .LBE43: + 150 .LBE42: + 151 .LBB44: + 152 .LBB45: + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h **** } + 153 .loc 2 664 0 + 154 0070 9A6A ldr r2, [r3, #40] + 155 0072 0A49 ldr r1, .L11+32 + 156 0074 0A40 ands r2, r1 + 157 0076 9A62 str r2, [r3, #40] + 158 .LBE45: + 159 .LBE44: + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 160 .loc 1 140 0 + 161 0078 0120 movs r0, #1 + 162 .LVL13: + 163 007a DAE7 b .L3 + 164 .L12: + 165 .align 2 + 166 .L11: + 167 007c 00380140 .word 1073821696 + 168 0080 00440040 .word 1073759232 + 169 0084 004C0040 .word 1073761280 + 170 0088 00500040 .word 1073762304 + 171 008c 00100240 .word 1073876992 + 172 0090 FFBFFFFF .word -16385 + 173 0094 FFFFFDFF .word -131073 + 174 0098 FFFFF7FF .word -524289 + 175 009c FFFFEFFF .word -1048577 + 176 .cfi_endproc + 177 .LFE413: + 179 .global __aeabi_uidiv + 180 .section .text.LL_USART_Init,"ax",%progbits + 181 .align 1 + 182 .global LL_USART_Init + 183 .syntax unified + 184 .code 16 + 185 .thumb_func + 186 .fpu softvfp + 188 LL_USART_Init: + 189 .LFB414: + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief Initialize USART registers according to the specified + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * parameters in USART_InitStruct. + ARM GAS /tmp/ccZXt8KR.s page 24 + + + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @note As some bits in USART configuration registers can only be written when the USART is dis + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * USART IP should be in disabled state prior calling this function. Otherwise, ERROR resu + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different f + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USARTx USART Instance + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * that contains the configuration information for the specified USART peripheral. + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - SUCCESS: USART registers are initialized according to USART_InitStruct content + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - ERROR: Problem occurred during USART Registers initialization + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 190 .loc 1 209 0 + 191 .cfi_startproc + 192 @ args = 0, pretend = 0, frame = 16 + 193 @ frame_needed = 0, uses_anonymous_args = 0 + 194 .LVL14: + 195 0000 30B5 push {r4, r5, lr} + 196 .LCFI0: + 197 .cfi_def_cfa_offset 12 + 198 .cfi_offset 4, -12 + 199 .cfi_offset 5, -8 + 200 .cfi_offset 14, -4 + 201 0002 85B0 sub sp, sp, #20 + 202 .LCFI1: + 203 .cfi_def_cfa_offset 32 + 204 0004 0400 movs r4, r0 + 205 0006 0D00 movs r5, r1 + 206 .LVL15: + 207 .LBB46: + 208 .LBB47: + 209 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @file stm32l0xx_ll_usart.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Header file of USART LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + ARM GAS /tmp/ccZXt8KR.s page 25 + + + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #ifndef __STM32L0xx_LL_USART_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define __STM32L0xx_LL_USART_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL USART + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Defines used for the bit position in the register and perform offsets*/ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_CR1_DEDT (uint32_t)16 + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_CR1_DEAT (uint32_t)21 + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_CR2_ADD (uint32_t)24 + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_CR3_SCARCNT (uint32_t)17 + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_RTOR_BLEN (uint32_t)24 + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define USART_POSITION_GTPR_GT (uint32_t)8 + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + ARM GAS /tmp/ccZXt8KR.s page 26 + + + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief LL USART Init Structure definition + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** typedef struct + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This feature can be modified afterwards using unitary fu + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } LL_USART_InitTypeDef; + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** typedef struct + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. + ARM GAS /tmp/ccZXt8KR.s page 27 + + + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** For more details, refer to description of this function. + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** For more details, refer to description of this function. + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** For more details, refer to description of this function. + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** For more details, refer to description of this function. + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error fla + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error fl + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected f + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error fl + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block fla + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + ARM GAS /tmp/ccZXt8KR.s page 28 + + + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + ARM GAS /tmp/ccZXt8KR.s page 29 + + + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity co + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< USART wake up from Mute + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : S + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U /*!< Oversampling by 16 */ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U /*!< Clock signal not provid + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * + ARM GAS /tmp/ccZXt8KR.s page 30 + + + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U /*!< The clock pulse of the l + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U /*!< The first clock transiti + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_POLARITY_LOW (uint32_t)0x00000000U /*!< Steady low value on SCLK + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 s + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are used as d + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal works usin + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are + ARM GAS /tmp/ccZXt8KR.s page 31 + + + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal works usin + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data from the da + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmitted/rece + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U /*!< Me + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address detection + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and R + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode + ARM GAS /tmp/ccZXt8KR.s page 32 + + + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake u + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U /*!< IrDA normal power mode * + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U /*!< 10-bit break detection m + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is active high + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of data regi + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of data regi + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros + ARM GAS /tmp/ccZXt8KR.s page 33 + + + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Write a value in USART register + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __REG__ Register to be written + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Read a value in USART register + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __REG__ Register to be read + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Register value + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE_ + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @} + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + ARM GAS /tmp/ccZXt8KR.s page 34 + + + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @{ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief USART Enable + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if USART is enabled + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); + 210 .loc 3 582 0 + 211 0008 0368 ldr r3, [r0] + 212 .LVL16: + 213 .LBE47: + 214 .LBE46: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus status = ERROR; + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if (defined(USART4) || defined(USART5)) + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_RCC_ClocksTypeDef RCC_Clocks; + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Check the parameters */ + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + ARM GAS /tmp/ccZXt8KR.s page 35 + + + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* USART needs to be in disabled state, in order to be able to configure some bits in + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** CRx registers */ + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (LL_USART_IsEnabled(USARTx) == 0U) + 215 .loc 1 228 0 + 216 000a DB07 lsls r3, r3, #31 + 217 000c 57D4 bmi .L20 + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART CR1 Configuration ----------------------- + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->Transfe + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** MODIFY_REG(USARTx->CR1, + 218 .loc 1 237 0 + 219 000e 0368 ldr r3, [r0] + 220 0010 2E4A ldr r2, .L29 + 221 0012 1A40 ands r2, r3 + 222 0014 4B68 ldr r3, [r1, #4] + 223 0016 C968 ldr r1, [r1, #12] + 224 .LVL17: + 225 0018 0B43 orrs r3, r1 + 226 001a 2969 ldr r1, [r5, #16] + 227 001c 0B43 orrs r3, r1 + 228 001e A969 ldr r1, [r5, #24] + 229 0020 0B43 orrs r3, r1 + 230 0022 1343 orrs r3, r2 + 231 0024 0360 str r3, [r0] + 232 .LVL18: + 233 .LBB48: + 234 .LBB49: + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief USART enabled in STOP Mode. + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UESM); + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + ARM GAS /tmp/ccZXt8KR.s page 36 + + + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief USART disabled in STOP Mode. + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_RE); + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Receiver Disable + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Transmitter Enable + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + ARM GAS /tmp/ccZXt8KR.s page 37 + + + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_TE); + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Transmitter Disable + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * of Transmitter and Receiver + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: + ARM GAS /tmp/ccZXt8KR.s page 38 + + + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Method This parameter can be one of the following values: + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccZXt8KR.s page 39 + + + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_MME); + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); + ARM GAS /tmp/ccZXt8KR.s page 40 + + + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Oversampling mode + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) + ARM GAS /tmp/ccZXt8KR.s page 41 + + + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccZXt8KR.s page 42 + + + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None + ARM GAS /tmp/ccZXt8KR.s page 43 + + + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set the length of the stop bits +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); + 235 .loc 3 1031 0 + 236 0026 4368 ldr r3, [r0, #4] + 237 0028 294A ldr r2, .L29+4 + 238 002a 1340 ands r3, r2 + 239 002c AA68 ldr r2, [r5, #8] + 240 002e 1343 orrs r3, r2 + 241 0030 4360 str r3, [r0, #4] + 242 .LVL19: + 243 .LBE49: + 244 .LBE48: + 245 .LBB50: + 246 .LBB51: +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve the length of the stop bits +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ + ARM GAS /tmp/ccZXt8KR.s page 44 + + +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t StopBits) +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccZXt8KR.s page 45 + + +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure RX pin active level logic +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure TX pin active level logic +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + ARM GAS /tmp/ccZXt8KR.s page 46 + + +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure Binary data logic. +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Retrieve Binary data configuration +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccZXt8KR.s page 47 + + +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whethe +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whethe +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whethe +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whethe +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + ARM GAS /tmp/ccZXt8KR.s page 48 + + +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whethe +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable Receiver Timeout +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable Receiver Timeout +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); + ARM GAS /tmp/ccZXt8KR.s page 49 + + +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Set Address of the USART node. +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * for wake up with address mark detection. +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * (b7-b4 should be set to 0) +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * for wake up with 7-bit address mark detection. +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * It may also be used for character detection during normal reception, +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * value and CMF flag is set on match) +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD))); +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD); +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); + ARM GAS /tmp/ccZXt8KR.s page 50 + + +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable RTS HW Flow Control +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable RTS HW Flow Control +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable CTS HW Flow Control +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable CTS HW Flow Control +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + ARM GAS /tmp/ccZXt8KR.s page 51 + + +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); + 247 .loc 3 1456 0 + 248 0032 8368 ldr r3, [r0, #8] + 249 0034 274A ldr r2, .L29+8 + 250 0036 1340 ands r3, r2 + 251 0038 6A69 ldr r2, [r5, #20] + 252 003a 1343 orrs r3, r2 + 253 003c 8360 str r3, [r0, #8] + 254 .LVL20: + 255 .LBE51: + 256 .LBE50: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART CR2 Configuration ----------------------- + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Configure USARTx CR2 (Stop bits) with parameters: + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART CR3 Configuration ----------------------- + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Configure USARTx CR3 (Hardware Flow Control) with parameters: + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->Ha + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART BRR Configuration ----------------------- + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Retrieve Clock frequency used for USART Peripheral + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART1) + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (USARTx == USART1) + 257 .loc 1 260 0 + 258 003e 264B ldr r3, .L29+12 + 259 0040 9842 cmp r0, r3 + 260 0042 0AD0 beq .L24 + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART1 */ + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART1) + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART2) + ARM GAS /tmp/ccZXt8KR.s page 52 + + + 261 .loc 1 266 0 + 262 0044 254B ldr r3, .L29+16 + 263 0046 9842 cmp r0, r3 + 264 0048 1DD0 beq .L25 + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #else + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (USARTx == USART2) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART4) + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART4) + 265 .loc 1 274 0 + 266 004a 254B ldr r3, .L29+20 + 267 004c 9842 cmp r0, r3 + 268 004e 1ED0 beq .L26 + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* USART4 clock is PCLK1 */ + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_RCC_GetSystemClocksFreq(&RCC_Clocks); + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = RCC_Clocks.PCLK1_Frequency; + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART4 */ + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #if defined(USART5) + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else if (USARTx == USART5) + 269 .loc 1 282 0 + 270 0050 244B ldr r3, .L29+24 + 271 0052 9842 cmp r0, r3 + 272 0054 20D0 beq .L27 + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 273 .loc 1 210 0 + 274 0056 0020 movs r0, #0 + 275 .LVL21: + 276 0058 32E0 b .L14 + 277 .LVL22: + 278 .L24: + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 279 .loc 1 262 0 + 280 005a 0320 movs r0, #3 + 281 .LVL23: + 282 005c FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 283 .LVL24: + 284 .L16: + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* USART5 clock is PCLK1 */ + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_RCC_GetSystemClocksFreq(&RCC_Clocks); + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = RCC_Clocks.PCLK1_Frequency; + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** #endif /* USART5 */ + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Nothing to do, as error code is already assigned to ERROR value */ + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Configure the USART Baud Rate : + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** - valid baud rate value (different from 0) is required + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** - Peripheral clock as returned by RCC service, should be valid (different from 0). + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + ARM GAS /tmp/ccZXt8KR.s page 53 + + + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + 285 .loc 1 298 0 + 286 0060 0028 cmp r0, #0 + 287 0062 2FD0 beq .L22 + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** && (USART_InitStruct->BaudRate != 0U)) + 288 .loc 1 299 0 + 289 0064 2968 ldr r1, [r5] + 290 0066 0029 cmp r1, #0 + 291 0068 2ED0 beq .L23 + 292 .LVL25: + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** status = SUCCESS; + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_SetBaudRate(USARTx, + 293 .loc 1 302 0 + 294 006a AA69 ldr r2, [r5, #24] + 295 .LVL26: + 296 .LBB52: + 297 .LBB53: +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable One bit sampling method +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable One bit sampling method +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { + ARM GAS /tmp/ccZXt8KR.s page 54 + + +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Enable Overrun detection +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Disable Overrun detection +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval State of bit (1 or 0). +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param Type This parameter can be one of the following values: +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE + ARM GAS /tmp/ccZXt8KR.s page 55 + + +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** /** +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * (Baud rate value != 0) +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param USARTx USART Instance +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @param BaudRate Baud Rate +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** * @retval None +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** */ +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** uint32_t BaudRate) +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** register uint32_t usartdiv = 0x0U; +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** register uint32_t brrtemp = 0x0U; +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) + 298 .loc 3 1597 0 + 299 006c 8023 movs r3, #128 + 300 006e 1B02 lsls r3, r3, #8 + 301 0070 9A42 cmp r2, r3 + 302 0072 16D0 beq .L28 +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USARTx->BRR = brrtemp; +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** else + ARM GAS /tmp/ccZXt8KR.s page 56 + + +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** { +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + 303 .loc 3 1606 0 + 304 0074 4B08 lsrs r3, r1, #1 + 305 0076 C018 adds r0, r0, r3 + 306 .LVL27: + 307 0078 FFF7FEFF bl __aeabi_uidiv + 308 .LVL28: + 309 007c 0004 lsls r0, r0, #16 + 310 007e 000C lsrs r0, r0, #16 + 311 0080 E060 str r0, [r4, #12] + 312 .LBE53: + 313 .LBE52: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_SetBaudRate(USARTx, + 314 .loc 1 301 0 + 315 0082 0120 movs r0, #1 + 316 0084 1CE0 b .L14 + 317 .LVL29: + 318 .L25: + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 319 .loc 1 271 0 + 320 0086 0C20 movs r0, #12 + 321 .LVL30: + 322 0088 FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 323 .LVL31: + 324 008c E8E7 b .L16 + 325 .LVL32: + 326 .L26: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = RCC_Clocks.PCLK1_Frequency; + 327 .loc 1 277 0 + 328 008e 6846 mov r0, sp + 329 .LVL33: + 330 0090 FFF7FEFF bl LL_RCC_GetSystemClocksFreq + 331 .LVL34: + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 332 .loc 1 278 0 + 333 0094 0298 ldr r0, [sp, #8] + 334 .LVL35: + 335 0096 E3E7 b .L16 + 336 .LVL36: + 337 .L27: + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk = RCC_Clocks.PCLK1_Frequency; + 338 .loc 1 285 0 + 339 0098 6846 mov r0, sp + 340 .LVL37: + 341 009a FFF7FEFF bl LL_RCC_GetSystemClocksFreq + 342 .LVL38: + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 343 .loc 1 286 0 + 344 009e 0298 ldr r0, [sp, #8] + 345 .LVL39: + 346 00a0 DEE7 b .L16 + 347 .LVL40: + 348 .L28: + 349 .LBB55: + 350 .LBB54: +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; + ARM GAS /tmp/ccZXt8KR.s page 57 + + + 351 .loc 3 1599 0 + 352 00a2 4000 lsls r0, r0, #1 + 353 .LVL41: + 354 00a4 4B08 lsrs r3, r1, #1 + 355 00a6 C018 adds r0, r0, r3 + 356 00a8 FFF7FEFF bl __aeabi_uidiv + 357 .LVL42: +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 358 .loc 3 1600 0 + 359 00ac 0E4B ldr r3, .L29+28 + 360 00ae 0340 ands r3, r0 + 361 .LVL43: +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** USARTx->BRR = brrtemp; + 362 .loc 3 1601 0 + 363 00b0 4008 lsrs r0, r0, #1 + 364 .LVL44: + 365 00b2 0722 movs r2, #7 + 366 00b4 1040 ands r0, r2 + 367 00b6 1843 orrs r0, r3 + 368 .LVL45: +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 369 .loc 3 1602 0 + 370 00b8 E060 str r0, [r4, #12] + 371 .LBE54: + 372 .LBE55: + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_SetBaudRate(USARTx, + 373 .loc 1 301 0 + 374 00ba 0120 movs r0, #1 + 375 .LVL46: + 376 00bc 00E0 b .L14 + 377 .LVL47: + 378 .L20: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 379 .loc 1 210 0 + 380 00be 0020 movs r0, #0 + 381 .LVL48: + 382 .L14: + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** periphclk, + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->OverSampling, + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->BaudRate); + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Endif (=> USART not in Disabled state => return ERROR) */ + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** return (status); + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 383 .loc 1 311 0 + 384 00c0 05B0 add sp, sp, #20 + 385 @ sp needed + 386 .LVL49: + 387 .LVL50: + 388 00c2 30BD pop {r4, r5, pc} + 389 .LVL51: + 390 .L22: + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 391 .loc 1 210 0 + 392 00c4 0020 movs r0, #0 + ARM GAS /tmp/ccZXt8KR.s page 58 + + + 393 .LVL52: + 394 00c6 FBE7 b .L14 + 395 .LVL53: + 396 .L23: + 397 00c8 0020 movs r0, #0 + 398 .LVL54: + 399 00ca F9E7 b .L14 + 400 .L30: + 401 .align 2 + 402 .L29: + 403 00cc F369FFEF .word -268473869 + 404 00d0 FFCFFFFF .word -12289 + 405 00d4 FFFCFFFF .word -769 + 406 00d8 00380140 .word 1073821696 + 407 00dc 00440040 .word 1073759232 + 408 00e0 004C0040 .word 1073761280 + 409 00e4 00500040 .word 1073762304 + 410 00e8 F0FF0000 .word 65520 + 411 .cfi_endproc + 412 .LFE414: + 414 .section .text.LL_USART_StructInit,"ax",%progbits + 415 .align 1 + 416 .global LL_USART_StructInit + 417 .syntax unified + 418 .code 16 + 419 .thumb_func + 420 .fpu softvfp + 422 LL_USART_StructInit: + 423 .LFB415: + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief Set each @ref LL_USART_InitTypeDef field to default value. + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * whose fields will be set to default values. + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @retval None + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 424 .loc 1 321 0 + 425 .cfi_startproc + 426 @ args = 0, pretend = 0, frame = 0 + 427 @ frame_needed = 0, uses_anonymous_args = 0 + 428 @ link register save eliminated. + 429 .LVL55: + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Set USART_InitStruct fields to default values */ + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->BaudRate = 9600U; + 430 .loc 1 323 0 + 431 0000 9623 movs r3, #150 + 432 0002 9B01 lsls r3, r3, #6 + 433 0004 0360 str r3, [r0] + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + 434 .loc 1 324 0 + 435 0006 0023 movs r3, #0 + 436 0008 4360 str r3, [r0, #4] + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + 437 .loc 1 325 0 + ARM GAS /tmp/ccZXt8KR.s page 59 + + + 438 000a 8360 str r3, [r0, #8] + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + 439 .loc 1 326 0 + 440 000c C360 str r3, [r0, #12] + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + 441 .loc 1 327 0 + 442 000e 0C22 movs r2, #12 + 443 0010 0261 str r2, [r0, #16] + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + 444 .loc 1 328 0 + 445 0012 4361 str r3, [r0, #20] + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; + 446 .loc 1 329 0 + 447 0014 8361 str r3, [r0, #24] + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 448 .loc 1 330 0 + 449 @ sp needed + 450 0016 7047 bx lr + 451 .cfi_endproc + 452 .LFE415: + 454 .section .text.LL_USART_ClockInit,"ax",%progbits + 455 .align 1 + 456 .global LL_USART_ClockInit + 457 .syntax unified + 458 .code 16 + 459 .thumb_func + 460 .fpu softvfp + 462 LL_USART_ClockInit: + 463 .LFB416: + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief Initialize USART Clock related settings according to the + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * specified parameters in the USART_ClockInitStruct. + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @note As some bits in USART configuration registers can only be written when the USART is dis + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * USART IP should be in disabled state prior calling this function. Otherwise, ERROR resu + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USARTx USART Instance + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * that contains the Clock configuration information for the specified USART peripheral. + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - SUCCESS: USART registers related to Clock settings are initialized according to USAR + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - ERROR: Problem occurred during USART Registers initialization + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStr + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 464 .loc 1 345 0 + 465 .cfi_startproc + 466 @ args = 0, pretend = 0, frame = 0 + 467 @ frame_needed = 0, uses_anonymous_args = 0 + 468 .LVL56: + 469 0000 10B5 push {r4, lr} + 470 .LCFI2: + 471 .cfi_def_cfa_offset 8 + 472 .cfi_offset 4, -8 + 473 .cfi_offset 14, -4 + 474 .LVL57: + 475 .LBB56: + 476 .LBB57: + ARM GAS /tmp/ccZXt8KR.s page 60 + + + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 477 .loc 3 582 0 + 478 0002 0368 ldr r3, [r0] + 479 .LVL58: + 480 .LBE57: + 481 .LBE56: + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** ErrorStatus status = SUCCESS; + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Check USART Instance and Clock signal output parameters */ + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* USART needs to be in disabled state, in order to be able to configure some bits in + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** CRx registers */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (LL_USART_IsEnabled(USARTx) == 0U) + 482 .loc 1 354 0 + 483 0004 DB07 lsls r3, r3, #31 + 484 0006 17D4 bmi .L35 + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART CR2 Configuration -----------------------*/ + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* If Clock signal has to be output */ + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) + 485 .loc 1 358 0 + 486 0008 0B68 ldr r3, [r1] + 487 000a 002B cmp r3, #0 + 488 000c 0ED0 beq .L36 + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Deactivate Clock signal delivery : + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Disable Clock Output: USART_CR2_CLKEN cleared + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** LL_USART_DisableSCLKOutput(USARTx); + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Ensure USART instance is USART capable */ + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_USART_INSTANCE(USARTx)); + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Check clock related parameters */ + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /*---------------------------- USART CR2 Configuration ----------------------- + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * Configure USARTx CR2 (Clock signal related bits) with parameters: + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Enable Clock Output: USART_CR2_CLKEN set + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->Cloc + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->Cloc + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->Last + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** MODIFY_REG(USARTx->CR2, + 489 .loc 1 382 0 + 490 000e 4368 ldr r3, [r0, #4] + 491 0010 0A4A ldr r2, .L37 + 492 0012 1340 ands r3, r2 + 493 0014 4A68 ldr r2, [r1, #4] + 494 0016 8C68 ldr r4, [r1, #8] + 495 0018 2243 orrs r2, r4 + ARM GAS /tmp/ccZXt8KR.s page 61 + + + 496 001a C968 ldr r1, [r1, #12] + 497 .LVL59: + 498 001c 0A43 orrs r2, r1 + 499 001e 1343 orrs r3, r2 + 500 0020 8022 movs r2, #128 + 501 0022 1201 lsls r2, r2, #4 + 502 0024 1343 orrs r3, r2 + 503 0026 4360 str r3, [r0, #4] + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 504 .loc 1 346 0 + 505 0028 0120 movs r0, #1 + 506 .LVL60: + 507 002a 06E0 b .L33 + 508 .LVL61: + 509 .L36: + 510 .LBB58: + 511 .LBB59: +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h **** } + 512 .loc 3 1002 0 + 513 002c 4368 ldr r3, [r0, #4] + 514 002e 044A ldr r2, .L37+4 + 515 0030 1340 ands r3, r2 + 516 0032 4360 str r3, [r0, #4] + 517 .LBE59: + 518 .LBE58: + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 519 .loc 1 346 0 + 520 0034 0120 movs r0, #1 + 521 .LVL62: + 522 0036 00E0 b .L33 + 523 .LVL63: + 524 .L35: + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Else (USART not in Disabled state => return ERROR */ + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** else + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** status = ERROR; + 525 .loc 1 391 0 + 526 0038 0020 movs r0, #0 + 527 .LVL64: + 528 .L33: + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** return (status); + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 529 .loc 1 395 0 + 530 @ sp needed + 531 003a 10BD pop {r4, pc} + 532 .L38: + 533 .align 2 + 534 .L37: + 535 003c FFF0FFFF .word -3841 + 536 0040 FFF7FFFF .word -2049 + ARM GAS /tmp/ccZXt8KR.s page 62 + + + 537 .cfi_endproc + 538 .LFE416: + 540 .section .text.LL_USART_ClockStructInit,"ax",%progbits + 541 .align 1 + 542 .global LL_USART_ClockStructInit + 543 .syntax unified + 544 .code 16 + 545 .thumb_func + 546 .fpu softvfp + 548 LL_USART_ClockStructInit: + 549 .LFB417: + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /** + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * whose fields will be set to default values. + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** * @retval None + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** */ + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** { + 550 .loc 1 404 0 + 551 .cfi_startproc + 552 @ args = 0, pretend = 0, frame = 0 + 553 @ frame_needed = 0, uses_anonymous_args = 0 + 554 @ link register save eliminated. + 555 .LVL65: + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** /* Set LL_USART_ClockInitStruct fields with default values */ + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + 556 .loc 1 406 0 + 557 0000 0023 movs r3, #0 + 558 0002 0360 str r3, [r0] + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when + 559 .loc 1 407 0 + 560 0004 4360 str r3, [r0, #4] + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when + 561 .loc 1 408 0 + 562 0006 8360 str r3, [r0, #8] + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when + 563 .loc 1 409 0 + 564 0008 C360 str r3, [r0, #12] + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c **** } + 565 .loc 1 410 0 + 566 @ sp needed + 567 000a 7047 bx lr + 568 .cfi_endproc + 569 .LFE417: + 571 .text + 572 .Letext0: + 573 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 574 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 575 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 576 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 577 .file 8 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 578 .file 9 "/usr/arm-none-eabi/include/sys/lock.h" + 579 .file 10 "/usr/arm-none-eabi/include/sys/_types.h" + 580 .file 11 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 581 .file 12 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccZXt8KR.s page 63 + + + 582 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h" + ARM GAS /tmp/ccZXt8KR.s page 64 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_usart.c + /tmp/ccZXt8KR.s:16 .text.LL_USART_DeInit:0000000000000000 $t + /tmp/ccZXt8KR.s:23 .text.LL_USART_DeInit:0000000000000000 LL_USART_DeInit + /tmp/ccZXt8KR.s:167 .text.LL_USART_DeInit:000000000000007c $d + /tmp/ccZXt8KR.s:181 .text.LL_USART_Init:0000000000000000 $t + /tmp/ccZXt8KR.s:188 .text.LL_USART_Init:0000000000000000 LL_USART_Init + /tmp/ccZXt8KR.s:403 .text.LL_USART_Init:00000000000000cc $d + /tmp/ccZXt8KR.s:415 .text.LL_USART_StructInit:0000000000000000 $t + /tmp/ccZXt8KR.s:422 .text.LL_USART_StructInit:0000000000000000 LL_USART_StructInit + /tmp/ccZXt8KR.s:455 .text.LL_USART_ClockInit:0000000000000000 $t + /tmp/ccZXt8KR.s:462 .text.LL_USART_ClockInit:0000000000000000 LL_USART_ClockInit + /tmp/ccZXt8KR.s:535 .text.LL_USART_ClockInit:000000000000003c $d + /tmp/ccZXt8KR.s:541 .text.LL_USART_ClockStructInit:0000000000000000 $t + /tmp/ccZXt8KR.s:548 .text.LL_USART_ClockStructInit:0000000000000000 LL_USART_ClockStructInit + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +LL_RCC_GetUSARTClockFreq +LL_RCC_GetSystemClocksFreq diff --git a/build/stm32l0xx_ll_utils.d b/build/stm32l0xx_ll_utils.d new file mode 100644 index 0000000..6b23e8f --- /dev/null +++ b/build/stm32l0xx_ll_utils.d @@ -0,0 +1,115 @@ +build/stm32l0xx_ll_utils.d: \ + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: diff --git a/build/stm32l0xx_ll_utils.lst b/build/stm32l0xx_ll_utils.lst new file mode 100644 index 0000000..febbab8 --- /dev/null +++ b/build/stm32l0xx_ll_utils.lst @@ -0,0 +1,5059 @@ +ARM GAS /tmp/ccFUt0tx.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32l0xx_ll_utils.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.UTILS_SetFlashLatency,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 UTILS_SetFlashLatency: + 23 .LFB276: + 24 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c" + 1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ****************************************************************************** + 3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @file stm32l0xx_ll_utils.c + 4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @author MCD Application Team + 5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief UTILS LL module driver. + 6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ****************************************************************************** + 7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @attention + 8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * + 9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * + 11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * Redistribution and use in source and binary forms, with or without modification, + 12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * are permitted provided that the following conditions are met: + 13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * 1. Redistributions of source code must retain the above copyright notice, + 14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * this list of conditions and the following disclaimer. + 15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * this list of conditions and the following disclaimer in the documentation + 17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * and/or other materials provided with the distribution. + 18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * may be used to endorse or promote products derived from this software + 20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * without specific prior written permission. + 21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * + 22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * + 33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ****************************************************************************** + 34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + ARM GAS /tmp/ccFUt0tx.s page 2 + + + 35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Includes ------------------------------------------------------------------*/ + 36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #include "stm32l0xx_ll_rcc.h" + 37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #include "stm32l0xx_ll_utils.h" + 38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #include "stm32l0xx_ll_system.h" + 39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #include "stm32l0xx_ll_pwr.h" + 40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup STM32L0xx_LL_Driver + 42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL + 46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Private types -------------------------------------------------------------*/ + 50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Private variables ---------------------------------------------------------*/ + 51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Private constants ---------------------------------------------------------*/ + 52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Constants + 53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE1 ((uint32_t)32000000U) /*!< Maximum frequency for system + 56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE2 ((uint32_t)16000000U) /*!< Maximum frequency for system + 57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE3 ((uint32_t)4000000U) /*!< Maximum frequency for system + 58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Defines used for PLL range */ + 60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_SCALE1 ((uint32_t)96000000U) /*!< Frequency max for PLLVCO outp + 61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_SCALE2 ((uint32_t)48000000U) /*!< Frequency max for PLLVCO outp + 62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_SCALE3 ((uint32_t)24000000U) /*!< Frequency max for PLLVCO outp + 63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Defines used for HSE range */ + 65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MIN ((uint32_t)1000000U) /*!< Frequency min for HSE frequen + 66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MAX ((uint32_t)24000000U) /*!< Frequency max for HSE frequen + 67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Defines used for FLASH latency according to HCLK Frequency */ + 69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY1_FREQ ((uint32_t)16000000U) /*!< HCLK frequency to set FLASH l + 70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY1_FREQ ((uint32_t)8000000U) /*!< HCLK frequency to set FLASH l + 71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY1_FREQ ((uint32_t)2000000U) /*!< HCLK frequency to set FLASH l + 72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Private macros ------------------------------------------------------------*/ + 76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Macros + 77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + 80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + 81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + 82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + 83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + 84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + 85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + 86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + 87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + 88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + 90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + 91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + ARM GAS /tmp/ccFUt0tx.s page 3 + + + 92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + 93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + 94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + 96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + 97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + 98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + 99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + 100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \ + 102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + 103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + 104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + 105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + 106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_16) \ + 107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_24) \ + 108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_32) \ + 109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_48)) + 110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == L + 112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PLL_DIV_4)) + 113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3))) + 117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))) + 121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + 123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + 124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ( + 126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Private function prototypes -----------------------------------------------*/ + 130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @defgroup UTILS_LL_Private_Functions UTILS Private functions + 131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + 134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); + 135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); + 136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void); + 138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Exported functions --------------------------------------------------------*/ + 143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Exported_Functions + 144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL_EF_DELAY + 148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + ARM GAS /tmp/ccFUt0tx.s page 4 + + + 149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + 153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid changing the Systick + 154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz + 156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_Get + 157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval None + 158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** void LL_Init1msTick(uint32_t HCLKFrequency) + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Use frequency provided in argument */ + 162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_InitTick(HCLKFrequency, 1000U); + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief This function provides accurate delay (in milliseconds) based + 167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * on SysTick counter flag + 168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid using blocking delay + 169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * and use rather osDelay service. + 170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + 171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * will configure Systick to 1ms + 172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param Delay specifies the delay time length, in milliseconds. + 173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval None + 174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** void LL_mDelay(uint32_t Delay) + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ((void)tmp); + 180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Add a period to guaranty minimum wait */ + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (Delay < LL_MAX_DELAY) + 183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** Delay++; + 185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** while (Delay) + 188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + 190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** Delay--; + 192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_EF_SYSTEM + 201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief System Configuration functions + 202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * + 203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** @verbatim + 204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** =============================================================================== + 205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ##### System Configuration functions ##### + ARM GAS /tmp/ccFUt0tx.s page 5 + + + 206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** =============================================================================== + 207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** [..] + 208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** System, AHB and APB buses clocks configuration + 209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz. + 211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** @endverbatim + 212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** @internal + 213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** Depending on the device voltage range, the maximum frequency should be + 214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** adapted accordingly: + 215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) +----------------------------------------------------------------+ + 216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | Wait states | HCLK clock frequency (MHz) | + 217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | |------------------------------------------------| + 218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | (Latency) | voltage range | voltage range | + 219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | + 220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | |----------------|---------------|---------------| + 221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | + 222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) |-------------- |----------------|---------------|---------------| + 223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | + 224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) |---------------|----------------|---------------|---------------| + 225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| + 226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** (++) +----------------------------------------------------------------+ + 227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** @endinternal + 228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief This function sets directly SystemCoreClock CMSIS variable. + 233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note Variable can be calculated also through SystemCoreClockUpdate function. + 234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval None + 236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** void LL_SetSystemCoreClock(uint32_t HCLKFrequency) + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* HCLK clock frequency */ + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** SystemCoreClock = HCLKFrequency; + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief This function configures system clock with HSI as clock source of the PLL + 245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note Function is based on the following formula: + 247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv) + 248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - PLLMul: The application software must set correctly the PLL multiplication factor to + 249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 96 MHz as PLLVCO when the product is in range 1, + 250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 48 MHz as PLLVCO when the product is in range 2, + 251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 24 MHz when the product is in range 3 + 252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note FLASH latency can be modified through this function. + 253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the PLL. + 255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + 262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + ARM GAS /tmp/ccFUt0tx.s page 6 + + + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (UTILS_PLL_IsBusy() == SUCCESS) + 269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + 272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable HSI if not enabled */ + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (LL_RCC_HSI_IsReady() != 1U) + 275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_HSI_Enable(); + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** while (LL_RCC_HSI_IsReady() != 1U) + 278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Wait for HSI ready */ + 280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Configure PLL */ + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStr + 285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else + 290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = ERROR; + 293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return status; + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief This function configures system clock with HSE as clock source of the PLL + 300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note Function is based on the following formula: + 302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv) + 303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - PLLMul: The application software must set correctly the PLL multiplication factor to + 304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 96 MHz as PLLVCO when the product is in range 1, + 305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 48 MHz as PLLVCO when the product is in range 2, + 306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - 24 MHz when the product is in range 3 + 307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @note FLASH latency can be modified through this function. + 308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000 + 309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param HSEBypass This parameter can be one of the following values: + 310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_ON + 311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_OFF + 312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the PLL. + 314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + ARM GAS /tmp/ccFUt0tx.s page 7 + + + 320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + 321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_Clk + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check the parameters */ + 327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + 328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + 329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (UTILS_PLL_IsBusy() == SUCCESS) + 332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + 335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable HSE if not enabled */ + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (LL_RCC_HSE_IsReady() != 1U) + 338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check if need to enable HSE bypass feature or not */ + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + 341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_HSE_EnableBypass(); + 343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else + 345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_HSE_DisableBypass(); + 347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable HSE */ + 350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_HSE_Enable(); + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** while (LL_RCC_HSE_IsReady() != 1U) + 352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Wait for HSE ready */ + 354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Configure PLL */ + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitS + 359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else + 364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = ERROR; + 367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return status; + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + ARM GAS /tmp/ccFUt0tx.s page 8 + + + 377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @} + 378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Functions + 381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @{ + 382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief Update number of Flash wait states in line with new frequency and current + 385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** voltage range. + 386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param Frequency HCLK frequency + 387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - SUCCESS: Latency has been modified + 389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - ERROR: Latency cannot be modified + 390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) + 392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 25 .loc 1 392 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 @ link register save eliminated. + 30 .LVL0: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + 396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Frequency cannot be equal to 0 */ + 398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (Frequency == 0U) + 31 .loc 1 398 0 + 32 0000 0028 cmp r0, #0 + 33 0002 33D0 beq .L6 + 34 .LBB62: + 35 .LBB63: + 36 .file 2 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @file stm32l0xx_ll_pwr.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Header file of PWR LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * are permitted provided that the following conditions are met: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + ARM GAS /tmp/ccFUt0tx.s page 9 + + + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #ifndef __STM32L0xx_LL_PWR_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define __STM32L0xx_LL_PWR_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL PWR + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Private macros ------------------------------------------------------------*/ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Exported types ------------------------------------------------------------*/ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Exported constants --------------------------------------------------------*/ + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Flags defines which can be used with LL_PWR_WriteReg function + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Flags defines which can be used with LL_PWR_ReadReg function + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + ARM GAS /tmp/ccFUt0tx.s page 10 + + + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_PVD_SUPPORT) + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector outpu + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_PVD_SUPPORT */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_CSR_VREFINTRDYF) + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_CSR_VREFINTRDYF */ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_CSR_EWUP3) + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_CSR_EWUP3 */ + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */ + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */ + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_MODE_PWR Mode Power + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode w + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mod + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage regulator in main mode d + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power m + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_CR_LPDS) + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode du + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mo + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_CR_LPDS */ + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + ARM GAS /tmp/ccFUt0tx.s page 11 + + + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_PVD_SUPPORT) + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected b + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected b + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected b + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected b + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected b + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected b + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected b + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltag + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_PVD_SUPPORT */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #if defined(PWR_CSR_EWUP3) + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 acco + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #endif /* PWR_CSR_EWUP3 */ + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Exported macro ------------------------------------------------------------*/ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Write a value in PWR register + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @param __REG__ Register to be written + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @param __VALUE__ Value to be written in the register + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Read a value in PWR register + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @param __REG__ Register to be read + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval Register value + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + ARM GAS /tmp/ccFUt0tx.s page 12 + + + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @} + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /* Exported functions --------------------------------------------------------*/ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** @defgroup PWR_LL_EF_Configuration Configuration + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @{ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Switch the regulator from main mode to low-power mode + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @note Remind to set the regulator to low power before enabling + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER). + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** SET_BIT(PWR->CR, PWR_CR_LPRUN); + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Switch the regulator from low-power mode to main mode + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Check if the regulator is in low-power mode + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval State of bit (1 or 0). + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN)); + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Set voltage regulator to low-power and switch from + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * run main mode to run low-power mode. + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * CR LPRUN LL_PWR_EnterLowPowerRunMode + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @note This "high level" function is introduced to provide functional + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * compatibility with other families. Notice that the two registers + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * have to be written sequentially, so this function is not atomic. + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * To assure atomicity you can call separately the following functions: + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER); + ARM GAS /tmp/ccFUt0tx.s page 13 + + + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * - @ref LL_PWR_EnableLowPowerRunMode(); + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */ + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Set voltage regulator to main and switch from + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * run main mode to low-power mode. + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * CR LPRUN LL_PWR_ExitLowPowerRunMode + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @note This "high level" function is introduced to provide functional + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * compatibility with other families. Notice that the two registers + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * have to be written sequentially, so this function is not atomic. + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * To assure atomicity you can call separately the following functions: + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * - @ref LL_PWR_DisableLowPowerRunMode(); + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN); + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */ + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Set the main internal regulator output voltage + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @param VoltageScaling This parameter can be one of the following values: + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval None + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** } + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** /** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @brief Get the main internal regulator output voltage + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @retval Returned value can be one of the following values: + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** */ + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** { + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h **** return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); + 37 .loc 2 303 0 + 38 0004 1A4B ldr r3, .L14 + 39 0006 1B68 ldr r3, [r3] + 40 0008 C022 movs r2, #192 + 41 000a 5201 lsls r2, r2, #5 + ARM GAS /tmp/ccFUt0tx.s page 14 + + + 42 000c 1340 ands r3, r2 + 43 .LBE63: + 44 .LBE62: + 399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = ERROR; + 401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else + 403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + 45 .loc 1 404 0 + 46 000e 8022 movs r2, #128 + 47 0010 1201 lsls r2, r2, #4 + 48 0012 9342 cmp r3, r2 + 49 0014 18D0 beq .L11 + 50 .LBB64: + 51 .LBB65: + 52 .loc 2 303 0 + 53 0016 164B ldr r3, .L14 + 54 0018 1B68 ldr r3, [r3] + 55 001a C022 movs r2, #192 + 56 001c 5201 lsls r2, r2, #5 + 57 001e 1340 ands r3, r2 + 58 .LBE65: + 59 .LBE64: + 405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (Frequency > UTILS_SCALE1_LATENCY1_FREQ) + 407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */ + 412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + 60 .loc 1 413 0 + 61 0020 8022 movs r2, #128 + 62 0022 5201 lsls r2, r2, #5 + 63 0024 9342 cmp r3, r2 + 64 0026 14D0 beq .L12 + 414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (Frequency > UTILS_SCALE2_LATENCY1_FREQ) + 416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */ + 421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** else + 423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (Frequency > UTILS_SCALE3_LATENCY1_FREQ) + 65 .loc 1 424 0 + 66 0028 124B ldr r3, .L14+4 + 67 002a 9842 cmp r0, r3 + 68 002c 1AD8 bhi .L9 + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 69 .loc 1 395 0 + 70 002e 0020 movs r0, #0 + 71 .LVL1: + ARM GAS /tmp/ccFUt0tx.s page 15 + + + 72 .L4: + 73 .LBB66: + 74 .LBB67: + 75 .file 3 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @file stm32l0xx_ll_system.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Header file of SYSTEM LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** @verbatim + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ============================================================================== + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ##### How to use this driver ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** The LL SYSTEM driver contains a set of generic APIs that can be + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** used by user: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** (+) Some of the FLASH features need to be handled in the SYSTEM file. + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** (+) Access to DBGCMU registers + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** (+) Access to SYSCFG registers + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** @endverbatim + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ****************************************************************************** + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @attention + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * Redistribution and use in source and binary forms, with or without modification, + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * are permitted provided that the following conditions are met: + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * 1. Redistributions of source code must retain the above copyright notice, + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * this list of conditions and the following disclaimer. + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * this list of conditions and the following disclaimer in the documentation + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * and/or other materials provided with the distribution. + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * may be used to endorse or promote products derived from this software + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * without specific prior written permission. + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** ****************************************************************************** + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #ifndef __STM32L0xx_LL_SYSTEM_H + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define __STM32L0xx_LL_SYSTEM_H + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #ifdef __cplusplus + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** extern "C" { + ARM GAS /tmp/ccFUt0tx.s page 16 + + + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/ + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #include "stm32l0xx.h" + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @addtogroup STM32L0xx_LL_Driver + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Private types -------------------------------------------------------------*/ + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Defines used for position in the register */ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define DBGMCU_REVID_POSITION (uint32_t)16U + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Power-down in Run mode Flash key + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** to unlock the RUN_PD bit in FLAS + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Memory Remap + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /* + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_UFB) + ARM GAS /tmp/ccFUt0tx.s page 17 + + + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG Bank Mode + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000U /*!< Flash Bank1 mapped at 0x0 + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Flash Bank2 mapped at 0x0 + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Data EEPROM Bank1 mapped + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Data EEPROM Bank2 mapped + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_CFGR1_UFB /*!< Flash Bank2 mapped at 0x0 + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Flash Bank1 mapped at 0x0 + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Data EEPROM Bank2 mapped + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** Data EEPROM Bank1 mapped + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_UFB */ + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_BOOTMODE SYSCFG Boot Mode + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_BOOTMODE_FLASH (uint32_t)0x00000000U /* + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0 /* + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_BOOTMODE_SRAM (SYSCFG_CFGR1_BOOT_MODE_1 | SYSCFG_CFGR1_BOOT_MODE_0) /* + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_CAPA) + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_CFGR2 SYSCFG VLCD Rail Connection + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_CAPA_VLCD2_PB2 SYSCFG_CFGR2_CAPA_0 /*!< Connect PB2 pin to LCD_V + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_CAPA_VLCD1_PB12 SYSCFG_CFGR2_CAPA_1 /*!< Connect PB12 pin to LCD_V + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_CAPA_VLCD3_PB0 SYSCFG_CFGR2_CAPA_2 /*!< Connect PB0 pin to LCD_V + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined (SYSCFG_CFGR2_CAPA_3) + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_CAPA_VLCD1_PE11 SYSCFG_CFGR2_CAPA_3 /*!< Connect PE11 pin to LCD_V + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR2_CAPA_3 */ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined (SYSCFG_CFGR2_CAPA_4) + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_CAPA_VLCD3_PE12 SYSCFG_CFGR2_CAPA_4 /*!< Connect PE12 pin to LCD_V + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR2_CAPA_4 */ + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR2_CAPA */ + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /*!< Enable Fast Mode Plus on + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_I2C2_FMP) + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on + ARM GAS /tmp/ccFUt0tx.s page 18 + + + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR2_I2C2_FMP */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_I2C3_FMP) + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP /*!< Enable Fast Mode Plus on + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR2_I2C3_FMP */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_VREFINT_CONTROL SYSCFG VREFINT Control + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_VREFINT_CONNECT_NONE (uint32_t)0x00000000U /*!< No pad connect + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_VREFINT_CONNECT_IO1 SYSCFG_CFGR3_VREF_OUT_0 /*!< PB0 connected + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_VREFINT_CONNECT_IO2 SYSCFG_CFGR3_VREF_OUT_1 /*!< PB1 connected + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 (SYSCFG_CFGR3_VREF_OUT_0 | SYSCFG_CFGR3_VREF_OUT_1) + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI Port + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(GPIOD_BASE) + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*GPIOD_BASE*/ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(GPIOE_BASE) + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*GPIOE_BASE*/ + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(GPIOH_BASE) + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTH (uint32_t)5U /*!< EXTI PORT H */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*GPIOH_BASE*/ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI Line + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXT + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXT + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXT + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXT + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXT + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXT + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXT + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXT + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXT + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXT + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXT + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXT + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXT + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXT + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXT + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXT + ARM GAS /tmp/ccFUt0tx.s page 19 + + + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stoppe + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(TIM3) + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stoppe + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*TIM3*/ + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(TIM6) + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stoppe + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*TIM6*/ + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(TIM7) + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stoppe + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*TIM7*/ + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchd + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent W + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(I2C2) + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*I2C2*/ + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(I2C3) + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*I2C3*/ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stop + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(TIM22) + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /*TIM22*/ + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + ARM GAS /tmp/ccFUt0tx.s page 20 + + + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/ + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/ + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Set memory mapping at address 0x00000000 + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Memory This parameter can be one of the following values: + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get memory mapping at address 0x00000000 + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_UFB) + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Select Flash bank mode (Bank flashed at 0x08000000) + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_SetFlashBankMode + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Bank This parameter can be one of the following values: + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB, Bank); + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get Flash bank mode (Bank flashed at 0x08000000) + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_GetFlashBankMode + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccFUt0tx.s page 21 + + + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB)); + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_UFB */ + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get Boot mode selected by the boot pins status bits + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note It indicates the boot mode selected by the boot pins. Bit 9 + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * corresponds to the complement of nBOOT1 bit in the FLASH_OPTR register. + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * Its value is defined in the option bytes. Bit 8 corresponds to the + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * value sampled on the BOOT0 pin. + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 BOOT_MODE LL_SYSCFG_GetBootMode + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BOOTMODE_FLASH + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_BOOTMODE_SRAM + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)); + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Firewall protection enabled + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_EnableFirewall + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN); + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Check if Firewall protection is enabled or not + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_IsEnabledFirewall + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval State of bit (1 or 0). + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN); + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_CAPA) + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Set VLCD rail connection to optional external capacitor + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note One to three external capacitors can be connected to pads to do + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * VLCD biasing. + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD1 rail can be connected to PB12 or PE11(*), + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD2 rail can be connected to PB2, + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD3 rail can be connected to PB0 or PE12(*) + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_SetVLCDRailConnection + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param IoPinConnect This parameter can be a combination of the following values: + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12 + ARM GAS /tmp/ccFUt0tx.s page 22 + + + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*) + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2 + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0 + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*) + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect) + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect); + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get VLCD rail connection configuration + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note One to three external capacitors can be connected to pads to do + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * VLCD biasing. + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD1 rail can be connected to PB12 or PE11(*), + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD2 rail can be connected to PB2, + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * - LCD_VLCD3 rail can be connected to PB0 or PE12(*) + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_GetVLCDRailConnection + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be a combination of the following values: + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12 + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*) + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2 + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0 + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*) + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetVLCDRailConnection(void) + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA)); + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Enable the I2C fast mode plus driving capability. + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus); + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + ARM GAS /tmp/ccFUt0tx.s page 23 + + + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Disable the I2C fast mode plus driving capability. + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus); + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Select which pad is connected to VREFINT_ADC + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_SetConnection + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param IoPinConnect This parameter can be one of the following values: + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1 + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2 + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect) + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT, IoPinConnect); + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get pad connection to VREFINT_ADC + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_GetConnection + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1 + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2 + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_GetConnection(void) + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT)); + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for ADC enable + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note The VrefInit buffer to ADC through internal path is also + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * enabled using function LL_ADC_SetCommonPathInternalCh() + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * with parameter LL_ADC_PATH_INTERNAL_VREFINT + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_EnableADC + ARM GAS /tmp/ccFUt0tx.s page 24 + + + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableADC(void) + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for ADC disable + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_DisableADC + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableADC(void) + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate temperature sensor reference for ADC enable + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Enable + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Enable(void) + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate temperature sensor reference for ADC disable + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Disable + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Disable(void) + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for comparator enable + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_EnableCOMP + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableCOMP(void) + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for comparator disable + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_DisableCOMP + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableCOMP(void) + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + ARM GAS /tmp/ccFUt0tx.s page 25 + + + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #if defined (RCC_HSI48_SUPPORT) + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for HSI48 oscillator enable + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_EnableHSI48 + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableHSI48(void) + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Buffer used to generate VREFINT reference for HSI48 oscillator disable + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_DisableHSI48 + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableHSI48(void) + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** #endif + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Check if VREFINT is ready or not + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note When set, it indicates that VREFINT is available for BOR, PVD and LCD + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 VREFINT_RDYF LL_SYSCFG_VREFINT_IsReady + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval State of bit (1 or 0). + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsReady(void) + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF) == SYSCFG_CFGR3_VREFINT_RDYF); + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Lock the whole content of SYSCFG_CFGR3 register + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note After SYSCFG_CFGR3 register lock, only read access available. + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * Only system hardware reset unlocks SYSCFG_CFGR3 register. + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_Lock + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_VREFINT_Lock(void) + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Check if SYSCFG_CFGR3 register is locked (only read access) or not + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note When set, it indicates that SYSCFG_CFGR3 register is locked, only read access available + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_IsLocked + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval State of bit (1 or 0). + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsLocked(void) + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK) == SYSCFG_CFGR3_REF_LOCK); + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + ARM GAS /tmp/ccFUt0tx.s page 26 + + + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Configure source input for the EXTI external interrupt. + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Port This parameter can be one of the following values: + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], SYSCFG_EXTICR1_EXTI0 << (Line >> 16U), Port << (Line >> + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get the configured defined for specific EXTI Line + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + ARM GAS /tmp/ccFUt0tx.s page 27 + + + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16U))) + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Return the device identifier + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0x7FF (ex: L053 -> 0x417, L073 -> 0x447) + ARM GAS /tmp/ccFUt0tx.s page 28 + + + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Return the device revision identifier + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @note This field indicates the revision of the device. + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Enable the Debug Module during SLEEP mode + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Disable the Debug Module during SLEEP mode + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Enable the Debug Module during STOP mode + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Disable the Debug Module during STOP mode + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + ARM GAS /tmp/ccFUt0tx.s page 29 + + + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Enable the Debug Module during STANDBY mode + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Disable the Debug Module during STANDBY mode + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Freeze APB1 peripherals (group1 peripherals) + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(DBGMCU->APB1FZ, Periphs); + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group1 peripherals) + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + ARM GAS /tmp/ccFUt0tx.s page 30 + + + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB1FZ, Periphs); + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Freeze APB2 peripherals + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*) + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** SET_BIT(DBGMCU->APB2FZ, Periphs); + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Unfreeze APB2 peripherals + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*) + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * (*) value not defined in all devices + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + ARM GAS /tmp/ccFUt0tx.s page 31 + + + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB2FZ, Periphs); + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @} + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @{ + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Set FLASH Latency + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @param Latency This parameter can be one of the following values: + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval None + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); + 76 .loc 3 933 0 + 77 0030 1149 ldr r1, .L14+8 + 78 0032 0B68 ldr r3, [r1] + 79 0034 0122 movs r2, #1 + 80 0036 9343 bics r3, r2 + 81 0038 0343 orrs r3, r0 + 82 003a 0B60 str r3, [r1] + 83 .LVL2: + 84 .LBE67: + 85 .LBE66: + 86 .LBB68: + 87 .LBB69: + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** } + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** /** + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @brief Get FLASH Latency + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** */ + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** { + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h **** return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); + 88 .loc 3 945 0 + 89 003c 0B68 ldr r3, [r1] + 90 003e 1A40 ands r2, r3 + 91 .LBE69: + 92 .LBE68: + 425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */ + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + ARM GAS /tmp/ccFUt0tx.s page 32 + + + 428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* else HCLK < 4MHz default LL_FLASH_LATENCY_0 0WS */ + 430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_FLASH_SetLatency(latency); + 433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check that the new number of wait states is taken into account to access the Flash + 435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** memory by reading the FLASH_ACR register */ + 436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (LL_FLASH_GetLatency() != latency) + 93 .loc 1 436 0 + 94 0040 9042 cmp r0, r2 + 95 0042 11D0 beq .L13 + 437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = ERROR; + 96 .loc 1 438 0 + 97 0044 0020 movs r0, #0 + 98 .LVL3: + 99 0046 12E0 b .L2 + 100 .LVL4: + 101 .L11: + 406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 102 .loc 1 406 0 + 103 0048 0C4B ldr r3, .L14+12 + 104 004a 9842 cmp r0, r3 + 105 004c 06D8 bhi .L7 + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 106 .loc 1 395 0 + 107 004e 0020 movs r0, #0 + 108 .LVL5: + 109 0050 EEE7 b .L4 + 110 .LVL6: + 111 .L12: + 415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 112 .loc 1 415 0 + 113 0052 0B4B ldr r3, .L14+16 + 114 0054 9842 cmp r0, r3 + 115 0056 03D8 bhi .L8 + 395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 116 .loc 1 395 0 + 117 0058 0020 movs r0, #0 + 118 .LVL7: + 119 005a E9E7 b .L4 + 120 .LVL8: + 121 .L7: + 409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 122 .loc 1 409 0 + 123 005c 0120 movs r0, #1 + 124 .LVL9: + 125 005e E7E7 b .L4 + 126 .LVL10: + 127 .L8: + 418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 128 .loc 1 418 0 + 129 0060 0120 movs r0, #1 + 130 .LVL11: + 131 0062 E5E7 b .L4 + 132 .LVL12: + ARM GAS /tmp/ccFUt0tx.s page 33 + + + 133 .L9: + 427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 134 .loc 1 427 0 + 135 0064 0120 movs r0, #1 + 136 .LVL13: + 137 0066 E3E7 b .L4 + 138 .LVL14: + 139 .L13: + 393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 140 .loc 1 393 0 + 141 0068 0120 movs r0, #1 + 142 .LVL15: + 143 006a 00E0 b .L2 + 144 .LVL16: + 145 .L6: + 400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 146 .loc 1 400 0 + 147 006c 0020 movs r0, #0 + 148 .LVL17: + 149 .L2: + 439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return status; + 442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 150 .loc 1 442 0 + 151 @ sp needed + 152 006e 7047 bx lr + 153 .L15: + 154 .align 2 + 155 .L14: + 156 0070 00700040 .word 1073770496 + 157 0074 80841E00 .word 2000000 + 158 0078 00200240 .word 1073881088 + 159 007c 0024F400 .word 16000000 + 160 0080 00127A00 .word 8000000 + 161 .cfi_endproc + 162 .LFE276: + 164 .section .text.UTILS_EnablePLLAndSwitchSystem,"ax",%progbits + 165 .align 1 + 166 .syntax unified + 167 .code 16 + 168 .thumb_func + 169 .fpu softvfp + 171 UTILS_EnablePLLAndSwitchSystem: + 172 .LFB279: + 443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param PLL_InputFrequency PLL input frequency (in Hz) + 447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the PLL. + 449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval PLL output frequency (in Hz) + 450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *U + 452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + ARM GAS /tmp/ccFUt0tx.s page 34 + + + 455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check the parameters */ + 456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + 457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + 458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check different PLL parameters according to RM */ + 460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* The application software must set correctly the PLL multiplication factor to avoid exceeding + 461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** 96 MHz as PLLVCO when the product is in range 1, + 462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** 48 MHz as PLLVCO when the product is in range 2, + 463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** 24 MHz when the product is in range 3. */ + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_POSITION_PLLMUL]); + 465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + 466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* The application software must set correctly the PLL multiplication factor to avoid exceeding + 468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** maximum frequency 32000000 in range 1 */ + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_POSITION_PLLDIV)+1U); + 470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + 471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return pllfreq; + 473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - SUCCESS: PLL modification can be done + 479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - ERROR: PLL is busy + 480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void) + 482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Check if PLL is busy*/ + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (LL_RCC_PLL_IsReady() != 0U) + 487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* PLL configuration cannot be modified */ + 489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = ERROR; + 490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return status; + 494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /** + 497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @brief Function to enable PLL and switch system clock to PLL + 498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param SYSCLK_Frequency SYSCLK frequency + 499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - SUCCESS: No problem to switch system to PLL + 503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** * - ERROR: Problem to switch system to PLL + 504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** */ + 505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 173 .loc 1 506 0 + 174 .cfi_startproc + 175 @ args = 0, pretend = 0, frame = 0 + 176 @ frame_needed = 0, uses_anonymous_args = 0 + 177 .LVL18: + ARM GAS /tmp/ccFUt0tx.s page 35 + + + 178 0000 70B5 push {r4, r5, r6, lr} + 179 .LCFI0: + 180 .cfi_def_cfa_offset 16 + 181 .cfi_offset 4, -16 + 182 .cfi_offset 5, -12 + 183 .cfi_offset 6, -8 + 184 .cfi_offset 14, -4 + 185 0002 0D00 movs r5, r1 + 186 .LVL19: + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** uint32_t hclk_frequency = 0U; + 509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + 511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + 512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + 513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Calculate HCLK frequency */ + 515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + 187 .loc 1 515 0 + 188 0004 0B68 ldr r3, [r1] + 189 0006 1A09 lsrs r2, r3, #4 + 190 0008 0F23 movs r3, #15 + 191 000a 1340 ands r3, r2 + 192 000c 224A ldr r2, .L27 + 193 000e D35C ldrb r3, [r2, r3] + 194 0010 D840 lsrs r0, r0, r3 + 195 .LVL20: + 196 0012 0400 movs r4, r0 + 197 .LVL21: + 516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (SystemCoreClock < hclk_frequency) + 198 .loc 1 518 0 + 199 0014 214B ldr r3, .L27+4 + 200 0016 1B68 ldr r3, [r3] + 201 0018 8342 cmp r3, r0 + 202 001a 30D3 bcc .L24 + 507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 203 .loc 1 507 0 + 204 001c 0120 movs r0, #1 + 205 .LVL22: + 206 .L17: + 207 .LBB70: + 208 .LBB71: + 209 .file 4 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @file stm32l0xx_ll_rcc.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @attention + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * Redistribution and use in source and binary forms, with or without modification, + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * are permitted provided that the following conditions are met: + ARM GAS /tmp/ccFUt0tx.s page 36 + + + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 1. Redistributions of source code must retain the above copyright notice, + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * this list of conditions and the following disclaimer. + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * this list of conditions and the following disclaimer in the documentation + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * and/or other materials provided with the distribution. + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * may be used to endorse or promote products derived from this software + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * without specific prior written permission. + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** ****************************************************************************** + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #ifndef __STM32L0xx_LL_RCC_H + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __STM32L0xx_LL_RCC_H + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #ifdef __cplusplus + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** extern "C" { + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #include "stm32l0xx.h" + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @addtogroup STM32L0xx_LL_Driver + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC) + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Constants RCC Private Constants + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + ARM GAS /tmp/ccFUt0tx.s page 37 + + + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Defines used for the bit position in the register and perform offsets*/ + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PPRE2 (uint32_t)11U /*!< field position in register RCC_CFGR */ + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PLLDIV (uint32_t)22U /*!< field position in register RCC_CFGR */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSICAL (uint32_t)0U /*!< field position in register RCC_ICSCR */ + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSITRIM (uint32_t)8U /*!< field position in register RCC_ICSCR */ + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSIRANGE (uint32_t)13U /*!< field position in register RCC_ICSCR */ + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSICAL (uint32_t)16U /*!< field position in register RCC_ICSCR */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_MSITRIM (uint32_t)24U /*!< field position in register RCC_ICSCR */ + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define RCC_POSITION_HSI48CAL (uint32_t)8U /*!< field position in register RCC_CRRCR */ + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** typedef struct + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccFUt0tx.s page 38 + + + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * HW set-up. + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */ + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LSI_VALUE ((uint32_t)37000U) /*!< Value of the LSI oscillator in Hz */ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Inte + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrup + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 39 + + + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Inter + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset f + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag * + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable * + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable * + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable * + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable * + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable * + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable * + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving cap + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capab + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capa + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /*!< Xtal mode higher driving capabilit + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler + ARM GAS /tmp/ccFUt0tx.s page 40 + + + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC cl + 244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC cl + 245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC cl + 246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC c + 247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + 252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ + 255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ + 256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ + 257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ + 258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ + 259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ + 260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ + 261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ + 269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ + 280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + ARM GAS /tmp/ccFUt0tx.s page 41 + + + 298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ + 307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ + 308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ + 309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ + 310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + 311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + 316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ + 319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ + 320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ + 321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ + 322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ + 323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + 328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up + 331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up + 332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, n + 340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MC + 341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO s + 342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO s + 343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO s + 344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO s + 345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO s + 346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_HSI48) + 347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO + 348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_HSI48 */ + 349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MC + 350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + ARM GAS /tmp/ccFUt0tx.s page 42 + + + 355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ + 358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ + 359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ + 360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ + 361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ + 362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the + 370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be prov + 371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + 377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART1SEL) + 380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) + 381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USAR + 384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART1SEL */ + 385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) + 386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USAR + 389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection + 396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000U /*!< PCLK1 selected as LPUART1 c + 399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK selected as LPUART1 + 400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clo + 401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clo + 402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + 407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4 + 410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SE + 411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SE + ARM GAS /tmp/ccFUt0tx.s page 43 + + + 412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C3SEL) + 413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4 + 414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SE + 415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SE + 416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CCIPR_I2C3SEL*/ + 417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + 422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(0x00000000U) /*!< PCLK1 selected as + 425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)RCC_CCIPR_LPTIM1SEL_0 /*!< LSI selected as LP + 426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)RCC_CCIPR_LPTIM1SEL_1 /*!< HSI selected as LP + 427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)RCC_CCIPR_LPTIM1SEL /*!< LSE selected as LP + 428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) + 433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) + 435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + 436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as RN + 439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as + 440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ + 444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) + 445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as US + 449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as + 450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ + 455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ + 456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + 459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART1SEL) + 462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selectio + 463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART1SEL */ + 464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selectio + 465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 44 + + + 469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + 471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selecti + 474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bit + 482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C3SEL) + 483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bit + 484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CCIPR_I2C3SEL*/ + 485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + 490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection + 493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) + 498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) + 499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + 500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selectio + 503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ + 507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) + 509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection + 513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ + 518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ + 519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC + 524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock + 525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock + ARM GAS /tmp/ccFUt0tx.s page 45 + + + 526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock + 527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** (selection through @re + 528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + 533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ + 536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ + 537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ + 538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ + 539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ + 540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ + 541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ + 542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ + 543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ + 544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor + 549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ + 552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ + 553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ + 554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + 559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI c + 562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE c + 563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Write a value in RCC register + 582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __REG__ Register to be written + ARM GAS /tmp/ccFUt0tx.s page 46 + + + 583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + 587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Read a value in RCC register + 590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __REG__ Register to be read + 591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Register value + 592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, + 605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetMultiplicator (), + 606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetDivider ()); + 607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + 608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_24 + 616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_32 + 617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_48 + 618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __PLLDIV__ This parameter can be one of the following values: + 619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_2 + 620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_3 + 621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_4 + 622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMu + 625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency + 628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + 629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + 630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + 631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __AHBPRESCALER__: This parameter can be one of the following values: + 632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + 633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + 634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 + 635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 + 636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 + 637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 + 638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + 639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + ARM GAS /tmp/ccFUt0tx.s page 47 + + + 640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + 641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) + 642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl + 644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + 647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + 648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + 649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __APB1PRESCALER__: This parameter can be one of the following values: + 651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 + 652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 + 653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 + 654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + 655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 + 656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + 657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + 662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + 663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + 664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __APB2PRESCALER__: This parameter can be one of the following values: + 666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 + 667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 + 668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 + 669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 + 670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 + 671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval PCLK2 clock frequency (in Hz) + 672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Helper macro to calculate the MSI frequency (in Hz) + 677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange + 678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) + 679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param __MSIRANGE__: This parameter can be one of the following values: + 680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 + 681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 + 682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 + 683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 + 684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 + 685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 + 686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 + 687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval MSI clock frequency (in Hz) + 688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MS + 690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + ARM GAS /tmp/ccFUt0tx.s page 48 + + + 697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ + 700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + 701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE + 705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSECSS_SUPPORT) + 709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable the Clock Security System. + 711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + 712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) + 715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSECSS_SUPPORT */ + 719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) + 722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + 723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) + 726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) + 732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + 733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) + 736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) + 742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable + 743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) + 746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); + 748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) + 752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable + 753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/ccFUt0tx.s page 49 + + + 754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) + 756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready + 762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + 763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) + 766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the RTC prescaler (divider) + 772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler + 773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Div This parameter can be one of the following values: + 774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 + 775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 + 776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 + 777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 + 778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) + 781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); + 783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the RTC divider (prescaler) + 787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler + 788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + 789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 + 790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 + 791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 + 792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 + 793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) + 795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); + 797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI + 804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI oscillator + 809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable + 810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/ccFUt0tx.s page 50 + + + 811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI oscillator + 819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable + 820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) + 823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI clock is ready + 829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + 830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI even in stop mode + 839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note HSI oscillator is forced ON even in Stop mode + 840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + 841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) + 844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIKERON); + 846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI in stop mode + 850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + 851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) + 854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); + 856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI Divider (it divides by 4) + 860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider + 861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableDivider(void) + 864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIDIVEN); + 866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 867:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 51 + + + 868:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 869:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI Divider (it divides by 4) + 870:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider + 871:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 872:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 873:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableDivider(void) + 874:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 875:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN); + 876:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 877:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 878:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 879:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 880:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CR_HSIOUTEN) + 881:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 882:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI Output + 883:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput + 884:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 885:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 886:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableOutput(void) + 887:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 888:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 889:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 890:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 891:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 892:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI Output + 893:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput + 894:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 895:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 896:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableOutput(void) + 897:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 898:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 899:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 900:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CR_HSIOUTEN */ + 901:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 902:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 903:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI Calibration value + 904:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of + 905:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * HSITRIM and the factory trim value + 906:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + 907:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 908:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 909:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) + 910:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 911:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL); + 912:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 913:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 914:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 915:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming + 916:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL + 917:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, + 918:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % + 919:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + 920:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + 921:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 922:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 923:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 924:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + ARM GAS /tmp/ccFUt0tx.s page 52 + + + 925:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); + 926:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 927:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 928:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 929:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming + 930:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + 931:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 932:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 933:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) + 934:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 935:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM); + 936:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 937:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 938:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 939:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} + 940:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 941:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 942:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 943:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 + 944:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ + 945:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 946:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 947:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 948:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI48 + 949:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable + 950:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 951:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 952:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) + 953:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 954:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 955:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 956:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 957:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 958:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI48 + 959:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable + 960:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 961:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 962:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) + 963:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 964:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 965:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 966:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 967:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 968:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready + 969:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady + 970:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 971:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 972:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) + 973:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 974:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); + 975:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 976:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 977:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 978:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value + 979:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + 980:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 981:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccFUt0tx.s page 53 + + + 982:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) + 983:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 984:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL); + 985:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 986:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 987:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CRRCR_HSI48DIV6OUTEN) + 988:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 989:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable HSI48 Divider (it divides by 6) + 990:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider + 991:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None + 992:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + 993:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void) + 994:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { + 995:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); + 996:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 997:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + 998:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** + 999:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable HSI48 Divider (it divides by 6) +1000:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider +1001:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1002:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1003:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void) +1004:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1005:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); +1006:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1007:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1008:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1009:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if HSI48 Divider is enabled (it divides by 6) +1010:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided +1011:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1012:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1013:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void) +1014:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1015:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == (RCC_CRRCR_HSI48DIV6OUTEN)); +1016:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1017:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1018:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /*RCC_CRRCR_HSI48DIV6OUTEN*/ +1019:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1020:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1021:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1022:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1023:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1024:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ +1025:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1026:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE +1027:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1028:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1029:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1030:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1031:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. +1032:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEON LL_RCC_LSE_Enable +1033:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1034:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1035:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) +1036:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1037:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSEON); +1038:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + ARM GAS /tmp/ccFUt0tx.s page 54 + + +1039:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1040:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1041:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. +1042:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEON LL_RCC_LSE_Disable +1043:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1044:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1045:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) +1046:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1047:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); +1048:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1049:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1050:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1051:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). +1052:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass +1053:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1054:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1055:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +1056:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1057:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); +1058:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1059:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1060:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1061:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). +1062:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass +1063:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1064:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1065:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +1066:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1067:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); +1068:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1069:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1070:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1071:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1072:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1073:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability +1074:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1075:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1076:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1077:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1078:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1079:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1080:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1081:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1082:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1083:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive); +1084:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1085:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1086:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1087:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1088:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability +1089:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1090:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1091:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1092:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1093:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1094:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1095:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) + ARM GAS /tmp/ccFUt0tx.s page 55 + + +1096:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1097:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV)); +1098:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1099:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable Clock security system on LSE. +1102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS +1103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +1106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); +1108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable Clock security system on LSE. +1112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Clock security system can be disabled only after a LSE +1113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * failure detection. In that case it MUST be disabled by software. +1114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS +1115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +1118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); +1120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady +1125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY)); +1130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if CSS on LSE failure Detection +1134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected +1135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +1138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD)); +1140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +1147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable + ARM GAS /tmp/ccFUt0tx.s page 56 + + +1153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +1178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MSI MSI +1185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable MSI oscillator +1190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSION LL_RCC_MSI_Enable +1191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_Enable(void) +1194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_MSION); +1196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable MSI oscillator +1200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSION LL_RCC_MSI_Disable +1201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_Disable(void) +1204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_MSION); +1206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if MSI oscillator Ready + ARM GAS /tmp/ccFUt0tx.s page 57 + + +1210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady +1211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +1214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); +1216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. +1220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange +1221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Range This parameter can be one of the following values: +1222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 +1223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 +1224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 +1225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 +1226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 +1227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 +1228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 +1229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +1232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); +1234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. +1238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange +1239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_0 +1241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_1 +1242:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_2 +1243:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_3 +1244:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_4 +1245:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_5 +1246:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MSIRANGE_6 +1247:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1248:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +1249:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1250:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); +1251:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1252:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1253:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1254:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get MSI Calibration value +1255:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note When MSITRIM is written, MSICAL is updated with the sum of +1256:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * MSITRIM and the factory trim value +1257:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration +1258:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +1259:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1260:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +1261:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1262:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL); +1263:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1264:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1265:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1266:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set MSI Calibration trimming + ARM GAS /tmp/ccFUt0tx.s page 58 + + +1267:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the MSICAL +1268:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming +1269:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0xFF +1270:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1271:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1272:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +1273:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1274:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); +1275:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1276:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1277:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1278:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get MSI Calibration trimming +1279:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming +1280:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +1281:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1282:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +1283:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1284:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM); +1285:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1286:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1287:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1288:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1289:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1290:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1291:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1292:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1293:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1294:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1295:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1296:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure the system clock source +1297:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1298:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1299:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI +1300:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1301:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1302:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1303:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1304:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1305:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1306:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1308:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1309:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1310:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1311:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get the system clock source +1312:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1313:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1314:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI +1315:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1316:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1317:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1318:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1319:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1320:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +1322:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1323:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 59 + + +1324:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1325:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set AHB prescaler +1326:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1327:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1328:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1329:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1330:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1331:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1332:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1333:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1334:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1335:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1336:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1337:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1338:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1339:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1340:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +1342:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1343:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1344:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1345:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1346:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler +1347:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1348:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1349:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1350:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1351:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1352:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1353:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1354:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1355:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1356:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +1358:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1359:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1360:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1361:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set APB2 prescaler +1362:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler +1363:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1364:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1365:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1366:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1367:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1368:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1369:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1370:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1371:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +1372:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +1374:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1375:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1376:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1377:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get AHB prescaler +1378:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +1379:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1380:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + ARM GAS /tmp/ccFUt0tx.s page 60 + + +1381:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1382:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1383:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1384:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1385:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1386:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1387:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1388:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1389:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1390:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +1391:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1392:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +1393:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1394:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1395:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1396:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get APB1 prescaler +1397:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler +1398:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1399:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1400:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1401:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1402:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1403:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1404:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1405:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +1406:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1407:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +1408:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1409:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1410:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1411:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get APB2 prescaler +1412:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler +1413:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1414:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1415:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1416:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1417:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1418:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1419:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1420:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +1421:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1422:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +1423:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1424:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1425:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1426:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set Clock After Wake-Up From Stop mode +1427:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop +1428:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Clock This parameter can be one of the following values: +1429:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI +1430:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI +1431:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1432:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1433:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +1434:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1435:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); +1436:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1437:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 61 + + +1438:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1439:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get Clock After Wake-Up From Stop mode +1440:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop +1441:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1442:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI +1443:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI +1444:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1445:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +1446:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1447:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +1448:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1449:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1450:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1451:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1452:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1453:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1454:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO +1455:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1456:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1457:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1458:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1459:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure MCOx +1460:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n +1461:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR MCOPRE LL_RCC_ConfigMCO +1462:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +1463:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK +1464:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK +1465:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +1466:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_MSI +1467:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +1468:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK +1469:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSI +1470:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +1471:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) +1472:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1473:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1474:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: +1475:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +1476:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 +1477:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 +1478:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_8 +1479:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_16 +1480:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1481:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1482:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +1483:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1484:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +1485:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1486:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1487:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1488:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1489:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1490:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1491:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +1492:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1493:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1494:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** + ARM GAS /tmp/ccFUt0tx.s page 62 + + +1495:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1496:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure USARTx clock source +1497:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource +1498:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +1499:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) +1500:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) +1501:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) +1502:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) +1503:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +1504:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +1505:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +1506:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +1507:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1508:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1509:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1510:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1511:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +1512:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1513:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +1514:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1515:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1516:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1517:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure LPUART1x clock source +1518:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource +1519:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPUARTxSource This parameter can be one of the following values: +1520:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 +1521:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK +1522:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI +1523:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE +1524:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1525:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1526:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +1527:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1528:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); +1529:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1530:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1531:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1532:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure I2Cx clock source +1533:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource +1534:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +1535:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +1536:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1537:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1538:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) +1539:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) +1540:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) +1541:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1542:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1543:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1544:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1545:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +1546:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1547:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U)); +1548:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1549:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1550:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1551:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure LPTIMx clock source + ARM GAS /tmp/ccFUt0tx.s page 63 + + +1552:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource +1553:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPTIMxSource This parameter can be one of the following values: +1554:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +1555:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +1556:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +1557:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +1558:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1559:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1560:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +1561:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1562:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource); +1563:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1564:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1565:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) +1566:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) +1567:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1568:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure RNG clock source +1569:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource +1570:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param RNGxSource This parameter can be one of the following values: +1571:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1572:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1573:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1574:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1575:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +1576:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1577:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource); +1578:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1579:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ +1580:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1581:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) +1582:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1583:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure USB clock source +1584:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource +1585:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: +1586:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1587:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1588:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1589:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1590:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +1591:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1592:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource); +1593:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1594:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ +1595:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1596:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ +1597:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1598:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1599:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get USARTx clock source +1600:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource +1601:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +1602:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE (*) +1603:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE +1604:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1605:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) +1606:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) +1607:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) +1608:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) + ARM GAS /tmp/ccFUt0tx.s page 64 + + +1609:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +1610:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +1611:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +1612:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +1613:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1614:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1615:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1616:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +1617:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1618:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +1619:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1620:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1621:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1622:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1623:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1624:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LPUARTx clock source +1625:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource +1626:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPUARTx This parameter can be one of the following values: +1627:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE +1628:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1629:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 +1630:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK +1631:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI +1632:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE +1633:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1634:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +1635:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1636:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); +1637:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1638:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1639:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1640:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get I2Cx clock source +1641:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource +1642:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +1643:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +1644:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE +1645:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1646:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +1647:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1648:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1649:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) +1650:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) +1651:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) +1652:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * +1653:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * (*) value not defined in all devices. +1654:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1655:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +1656:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1657:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U)); +1658:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1659:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1660:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1661:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get LPTIMx clock source +1662:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource +1663:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param LPTIMx This parameter can be one of the following values: +1664:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE +1665:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccFUt0tx.s page 65 + + +1666:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +1667:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +1668:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +1669:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +1670:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1671:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +1672:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1673:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx)); +1674:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1675:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1676:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RCC_CCIPR_HSI48SEL) +1677:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(RNG) +1678:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1679:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get RNGx clock source +1680:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource +1681:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param RNGx This parameter can be one of the following values: +1682:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE +1683:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1684:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +1685:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 +1686:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1687:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +1688:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1689:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +1690:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1691:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RNG */ +1692:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1693:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #if defined(USB) +1694:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1695:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get USBx clock source +1696:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource +1697:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +1698:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +1699:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1700:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1701:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 +1702:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1703:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +1704:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1705:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); +1706:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1707:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* USB */ +1708:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1709:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** #endif /* RCC_CCIPR_HSI48SEL */ +1710:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1711:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1712:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1713:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1714:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1715:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +1716:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1717:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1718:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1719:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1720:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Set RTC Clock Source +1721:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed any more unless +1722:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + ARM GAS /tmp/ccFUt0tx.s page 66 + + +1723:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * set). The RTCRST bit can be used to reset them. +1724:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource +1725:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1726:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1728:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1729:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +1730:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1731:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1732:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +1733:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1734:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); +1735:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1736:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1738:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Get RTC Clock Source +1739:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource +1740:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1741:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1742:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1743:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1744:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +1745:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1746:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +1747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1748:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); +1749:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1750:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1751:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1752:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable RTC +1753:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_EnableRTC +1754:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1755:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1756:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +1757:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1758:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_RTCEN); +1759:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1760:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1761:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1762:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable RTC +1763:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_DisableRTC +1764:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1765:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1766:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) +1767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1768:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); +1769:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1770:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1771:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1772:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +1773:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC +1774:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1775:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1776:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +1777:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1778:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN)); +1779:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + ARM GAS /tmp/ccFUt0tx.s page 67 + + +1780:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1781:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1782:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Force the Backup domain reset +1783:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset +1784:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1785:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1786:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +1787:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1788:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_RTCRST); +1789:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1790:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1791:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1792:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Release the Backup domain reset +1793:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset +1794:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1795:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1796:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +1797:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1798:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); +1799:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1800:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1801:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1802:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @} +1803:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1804:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1805:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +1806:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @{ +1807:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1808:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1809:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1810:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Enable PLL +1811:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +1812:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1813:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +1815:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1816:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); + 210 .loc 4 1816 0 + 211 001e 204A ldr r2, .L27+8 + 212 0020 1168 ldr r1, [r2] + 213 0022 8023 movs r3, #128 + 214 0024 5B04 lsls r3, r3, #17 + 215 0026 0B43 orrs r3, r1 + 216 0028 1360 str r3, [r2] + 217 .L19: + 218 .LBE71: + 219 .LBE70: + 220 .LBB72: + 221 .LBB73: +1817:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1818:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1819:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1820:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Disable PLL +1821:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +1822:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +1823:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1824:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccFUt0tx.s page 68 + + +1825:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +1826:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1827:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +1828:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1829:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1830:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1831:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Check if PLL Ready +1832:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +1833:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1835:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +1836:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 222 .loc 4 1837 0 discriminator 1 + 223 002a 1D4B ldr r3, .L27+8 + 224 002c 1B68 ldr r3, [r3] + 225 .LBE73: + 226 .LBE72: + 519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Set FLASH latency to highest latency */ + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = UTILS_SetFlashLatency(hclk_frequency); + 522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Update system clock configuration */ + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (status == SUCCESS) + 526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Enable PLL */ + 528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_PLL_Enable(); + 529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** while (LL_RCC_PLL_IsReady() != 1U) + 227 .loc 1 529 0 discriminator 1 + 228 002e 9B01 lsls r3, r3, #6 + 229 0030 FBD5 bpl .L19 + 230 .LVL23: + 231 .LBB74: + 232 .LBB75: +1341:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 233 .loc 4 1341 0 + 234 0032 1B4A ldr r2, .L27+8 + 235 0034 D368 ldr r3, [r2, #12] + 236 0036 F021 movs r1, #240 + 237 0038 8B43 bics r3, r1 + 238 003a 2968 ldr r1, [r5] + 239 003c 0B43 orrs r3, r1 + 240 003e D360 str r3, [r2, #12] + 241 .LVL24: + 242 .LBE75: + 243 .LBE74: + 244 .LBB76: + 245 .LBB77: +1307:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 246 .loc 4 1307 0 + 247 0040 D368 ldr r3, [r2, #12] + 248 0042 0321 movs r1, #3 + 249 0044 8B43 bics r3, r1 + 250 0046 0B43 orrs r3, r1 + 251 0048 D360 str r3, [r2, #12] + 252 .L20: + ARM GAS /tmp/ccFUt0tx.s page 69 + + + 253 .LBE77: + 254 .LBE76: + 255 .LBB78: + 256 .LBB79: +1321:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 257 .loc 4 1321 0 discriminator 1 + 258 004a 154B ldr r3, .L27+8 + 259 004c DA68 ldr r2, [r3, #12] + 260 004e 0C23 movs r3, #12 + 261 0050 1340 ands r3, r2 + 262 .LBE79: + 263 .LBE78: + 530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Wait for PLL ready */ + 532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Sysclk activation on the main PLL */ + 535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + 536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + 537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + 264 .loc 1 537 0 discriminator 1 + 265 0052 0C2B cmp r3, #12 + 266 0054 F9D1 bne .L20 + 267 .LVL25: + 268 .LBB80: + 269 .LBB81: +1357:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 270 .loc 4 1357 0 + 271 0056 124B ldr r3, .L27+8 + 272 0058 DA68 ldr r2, [r3, #12] + 273 005a 1249 ldr r1, .L27+12 + 274 005c 0A40 ands r2, r1 + 275 005e 6968 ldr r1, [r5, #4] + 276 0060 0A43 orrs r2, r1 + 277 0062 DA60 str r2, [r3, #12] + 278 .LVL26: + 279 .LBE81: + 280 .LBE80: + 538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Wait for system clock switch to PLL */ + 540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Set APB1 & APB2 prescaler*/ + 543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + 544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + 281 .loc 1 544 0 + 282 0064 AA68 ldr r2, [r5, #8] + 283 .LVL27: + 284 .LBB82: + 285 .LBB83: +1373:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 286 .loc 4 1373 0 + 287 0066 D968 ldr r1, [r3, #12] + 288 0068 0F4D ldr r5, .L27+16 + 289 .LVL28: + 290 006a 2940 ands r1, r5 + 291 006c 0A43 orrs r2, r1 + ARM GAS /tmp/ccFUt0tx.s page 70 + + + 292 .LVL29: + 293 006e DA60 str r2, [r3, #12] + 294 .LVL30: + 295 .L18: + 296 .LBE83: + 297 .LBE82: + 545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (SystemCoreClock > hclk_frequency) + 298 .loc 1 548 0 + 299 0070 0A4B ldr r3, .L27+4 + 300 0072 1B68 ldr r3, [r3] + 301 0074 A342 cmp r3, r4 + 302 0076 07D8 bhi .L25 + 303 .L21: + 304 .LVL31: + 549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Set FLASH latency to lowest latency */ + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** status = UTILS_SetFlashLatency(hclk_frequency); + 552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Update SystemCoreClock variable */ + 555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** if (status == SUCCESS) + 305 .loc 1 555 0 + 306 0078 0128 cmp r0, #1 + 307 007a 09D0 beq .L26 + 308 .L22: + 556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** LL_SetSystemCoreClock(hclk_frequency); + 558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** return status; + 561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 309 .loc 1 561 0 + 310 @ sp needed + 311 .LVL32: + 312 007c 70BD pop {r4, r5, r6, pc} + 313 .LVL33: + 314 .L24: + 521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 315 .loc 1 521 0 + 316 007e FFF7FEFF bl UTILS_SetFlashLatency + 317 .LVL34: + 525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 318 .loc 1 525 0 + 319 0082 0128 cmp r0, #1 + 320 0084 F4D1 bne .L18 + 321 0086 CAE7 b .L17 + 322 .LVL35: + 323 .L25: + 551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 324 .loc 1 551 0 + 325 0088 2000 movs r0, r4 + 326 008a FFF7FEFF bl UTILS_SetFlashLatency + 327 .LVL36: + 328 008e F3E7 b .L21 + ARM GAS /tmp/ccFUt0tx.s page 71 + + + 329 .L26: + 330 .LVL37: + 331 .LBB84: + 332 .LBB85: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 333 .loc 1 240 0 + 334 0090 024B ldr r3, .L27+4 + 335 0092 1C60 str r4, [r3] + 336 0094 F2E7 b .L22 + 337 .L28: + 338 0096 C046 .align 2 + 339 .L27: + 340 0098 00000000 .word AHBPrescTable + 341 009c 00000000 .word SystemCoreClock + 342 00a0 00100240 .word 1073876992 + 343 00a4 FFF8FFFF .word -1793 + 344 00a8 FFC7FFFF .word -14337 + 345 .LBE85: + 346 .LBE84: + 347 .cfi_endproc + 348 .LFE279: + 350 .global __aeabi_uidiv + 351 .section .text.LL_Init1msTick,"ax",%progbits + 352 .align 1 + 353 .global LL_Init1msTick + 354 .syntax unified + 355 .code 16 + 356 .thumb_func + 357 .fpu softvfp + 359 LL_Init1msTick: + 360 .LFB271: + 160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Use frequency provided in argument */ + 361 .loc 1 160 0 + 362 .cfi_startproc + 363 @ args = 0, pretend = 0, frame = 0 + 364 @ frame_needed = 0, uses_anonymous_args = 0 + 365 .LVL38: + 366 0000 10B5 push {r4, lr} + 367 .LCFI1: + 368 .cfi_def_cfa_offset 8 + 369 .cfi_offset 4, -8 + 370 .cfi_offset 14, -4 + 371 .LVL39: + 372 .LBB86: + 373 .LBB87: + 374 .file 5 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h" + 1:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 2:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ****************************************************************************** + 3:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @file stm32l0xx_ll_utils.h + 4:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @author MCD Application Team + 5:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Header file of UTILS LL module. + 6:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @verbatim + 7:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ============================================================================== + 8:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ##### How to use this driver ##### + 9:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ============================================================================== + 10:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** [..] + 11:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** The LL UTILS driver contains a set of generic APIs that can be + ARM GAS /tmp/ccFUt0tx.s page 72 + + + 12:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** used by user: + 13:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** (+) Device electronic signature + 14:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** (+) Timing functions + 15:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** (+) PLL configuration functions + 16:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 17:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @endverbatim + 18:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ****************************************************************************** + 19:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @attention + 20:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * + 21:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 22:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * + 23:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * Redistribution and use in source and binary forms, with or without modification, + 24:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * are permitted provided that the following conditions are met: + 25:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * 1. Redistributions of source code must retain the above copyright notice, + 26:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * this list of conditions and the following disclaimer. + 27:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 28:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * this list of conditions and the following disclaimer in the documentation + 29:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * and/or other materials provided with the distribution. + 30:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 31:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * may be used to endorse or promote products derived from this software + 32:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * without specific prior written permission. + 33:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * + 34:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 35:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 36:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 37:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 38:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 39:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 40:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 41:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 42:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 43:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 44:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * + 45:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** ****************************************************************************** + 46:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 47:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 48:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 49:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #ifndef __STM32L0xx_LL_UTILS_H + 50:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define __STM32L0xx_LL_UTILS_H + 51:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 52:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #ifdef __cplusplus + 53:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** extern "C" { + 54:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #endif + 55:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 56:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Includes ------------------------------------------------------------------*/ + 57:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #include "stm32l0xx.h" + 58:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 59:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @addtogroup STM32L0xx_LL_Driver + 60:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 61:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 62:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 63:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL UTILS + 64:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 65:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 66:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 67:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Private types -------------------------------------------------------------*/ + 68:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Private variables ---------------------------------------------------------*/ + ARM GAS /tmp/ccFUt0tx.s page 73 + + + 69:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 70:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Private constants ---------------------------------------------------------*/ + 71:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + 72:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 73:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 74:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 75:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Max delay can be used in LL_mDelay */ + 76:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define LL_MAX_DELAY 0xFFFFFFFFU + 77:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 78:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 79:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Unique device ID register base address + 80:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 81:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define UID_BASE_ADDRESS UID_BASE + 82:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 83:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 84:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Flash size data register base address + 85:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 86:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + 87:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 88:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 89:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 90:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 91:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 92:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 93:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Private macros ------------------------------------------------------------*/ + 94:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + 95:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 96:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 97:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 98:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 99:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 100:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Exported types ------------------------------------------------------------*/ + 101:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + 102:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 103:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 104:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 105:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief UTILS PLL structure definition + 106:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 107:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** typedef struct + 108:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 109:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + 110:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + 111:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 112:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 113:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 114:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 115:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + 116:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PLL_DIV + 117:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 118:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 119:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 120:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } LL_UTILS_PLLInitTypeDef; + 121:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 122:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 123:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief UTILS System, AHB and APB buses clock configuration structure definition + 124:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 125:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** typedef struct + ARM GAS /tmp/ccFUt0tx.s page 74 + + + 126:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 127:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the + 128:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + 129:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 130:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 131:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @ref LL_RCC_SetAHBPrescaler(). */ + 132:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 133:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from t + 134:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + 135:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 136:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 137:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @ref LL_RCC_SetAPB1Prescaler(). */ + 138:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 139:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from t + 140:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + 141:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 142:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 143:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** @ref LL_RCC_SetAPB2Prescaler(). */ + 144:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 145:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } LL_UTILS_ClkInitTypeDef; + 146:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 147:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 148:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 149:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 150:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 151:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Exported constants --------------------------------------------------------*/ + 152:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + 153:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 154:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 155:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 156:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + 157:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 158:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 159:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled + 160:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled + 161:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 162:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 163:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 164:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 165:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 166:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 167:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 168:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 169:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 170:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Exported macro ------------------------------------------------------------*/ + 171:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 172:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Exported functions --------------------------------------------------------*/ + 173:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + 174:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 175:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 176:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 177:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + 178:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 179:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 180:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 181:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 182:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + ARM GAS /tmp/ccFUt0tx.s page 75 + + + 183:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @retval UID[31:0] + 184:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 185:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word0(void) + 186:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 187:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); + 188:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } + 189:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 190:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 191:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + 192:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @retval UID[63:32] + 193:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 194:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word1(void) + 195:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 196:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); + 197:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } + 198:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 199:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 200:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + 201:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @retval UID[95:64] + 202:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 203:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word2(void) + 204:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 205:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); + 206:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } + 207:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 208:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 209:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief Get Flash memory size + 210:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @note This bitfield indicates the size of the device Flash memory expressed in + 211:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + 212:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @retval FLASH_SIZE[15:0]: Flash memory size + 213:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 214:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetFlashSize(void) + 215:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 216:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + 217:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** } + 218:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 219:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 220:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 221:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @} + 222:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 223:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 224:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** @defgroup UTILS_LL_EF_DELAY DELAY + 225:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @{ + 226:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 227:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** + 228:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /** + 229:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @brief This function configures the Cortex-M SysTick source of the time base. + 230:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 231:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @note When a RTOS is used, it is recommended to avoid changing the SysTick + 232:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 233:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @param Ticks Number of ticks + 234:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** * @retval None + 235:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** */ + 236:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) + 237:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** { + 238:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** /* Configure the SysTick to have interrupt in 1ms time base */ + 239:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + ARM GAS /tmp/ccFUt0tx.s page 76 + + + 375 .loc 5 239 0 + 376 0002 FA21 movs r1, #250 + 377 0004 8900 lsls r1, r1, #2 + 378 0006 FFF7FEFF bl __aeabi_uidiv + 379 .LVL40: + 380 000a 0138 subs r0, r0, #1 + 381 000c 034B ldr r3, .L30 + 382 000e 5860 str r0, [r3, #4] + 240:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 383 .loc 5 240 0 + 384 0010 0022 movs r2, #0 + 385 0012 9A60 str r2, [r3, #8] + 241:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 386 .loc 5 241 0 + 387 0014 0532 adds r2, r2, #5 + 388 0016 1A60 str r2, [r3] + 389 .LVL41: + 390 .LBE87: + 391 .LBE86: + 163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 392 .loc 1 163 0 + 393 @ sp needed + 394 0018 10BD pop {r4, pc} + 395 .L31: + 396 001a C046 .align 2 + 397 .L30: + 398 001c 10E000E0 .word -536813552 + 399 .cfi_endproc + 400 .LFE271: + 402 .section .text.LL_mDelay,"ax",%progbits + 403 .align 1 + 404 .global LL_mDelay + 405 .syntax unified + 406 .code 16 + 407 .thumb_func + 408 .fpu softvfp + 410 LL_mDelay: + 411 .LFB272: + 176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 412 .loc 1 176 0 + 413 .cfi_startproc + 414 @ args = 0, pretend = 0, frame = 8 + 415 @ frame_needed = 0, uses_anonymous_args = 0 + 416 @ link register save eliminated. + 417 .LVL42: + 418 0000 82B0 sub sp, sp, #8 + 419 .LCFI2: + 420 .cfi_def_cfa_offset 8 + 177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 421 .loc 1 177 0 + 422 0002 084B ldr r3, .L38 + 423 0004 1B68 ldr r3, [r3] + 424 0006 0193 str r3, [sp, #4] + 179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 425 .loc 1 179 0 + 426 0008 019B ldr r3, [sp, #4] + 182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + ARM GAS /tmp/ccFUt0tx.s page 77 + + + 427 .loc 1 182 0 + 428 000a 431C adds r3, r0, #1 + 429 000c 00D0 beq .L35 + 184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 430 .loc 1 184 0 + 431 000e 0130 adds r0, r0, #1 + 432 .LVL43: + 433 .L35: + 187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 434 .loc 1 187 0 + 435 0010 0028 cmp r0, #0 + 436 0012 05D0 beq .L37 + 189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 437 .loc 1 189 0 + 438 0014 034B ldr r3, .L38 + 439 0016 1B68 ldr r3, [r3] + 440 0018 DB03 lsls r3, r3, #15 + 441 001a F9D5 bpl .L35 + 191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 442 .loc 1 191 0 + 443 001c 0138 subs r0, r0, #1 + 444 .LVL44: + 445 001e F7E7 b .L35 + 446 .L37: + 194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 447 .loc 1 194 0 + 448 0020 02B0 add sp, sp, #8 + 449 @ sp needed + 450 0022 7047 bx lr + 451 .L39: + 452 .align 2 + 453 .L38: + 454 0024 10E000E0 .word -536813552 + 455 .cfi_endproc + 456 .LFE272: + 458 .section .text.LL_SetSystemCoreClock,"ax",%progbits + 459 .align 1 + 460 .global LL_SetSystemCoreClock + 461 .syntax unified + 462 .code 16 + 463 .thumb_func + 464 .fpu softvfp + 466 LL_SetSystemCoreClock: + 467 .LFB273: + 238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** /* HCLK clock frequency */ + 468 .loc 1 238 0 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 0 + 471 @ frame_needed = 0, uses_anonymous_args = 0 + 472 @ link register save eliminated. + 473 .LVL45: + 240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 474 .loc 1 240 0 + 475 0000 014B ldr r3, .L41 + 476 0002 1860 str r0, [r3] + 241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 477 .loc 1 241 0 + ARM GAS /tmp/ccFUt0tx.s page 78 + + + 478 @ sp needed + 479 0004 7047 bx lr + 480 .L42: + 481 0006 C046 .align 2 + 482 .L41: + 483 0008 00000000 .word SystemCoreClock + 484 .cfi_endproc + 485 .LFE273: + 487 .section .text.LL_PLL_ConfigSystemClock_HSI,"ax",%progbits + 488 .align 1 + 489 .global LL_PLL_ConfigSystemClock_HSI + 490 .syntax unified + 491 .code 16 + 492 .thumb_func + 493 .fpu softvfp + 495 LL_PLL_ConfigSystemClock_HSI: + 496 .LFB274: + 263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 497 .loc 1 263 0 + 498 .cfi_startproc + 499 @ args = 0, pretend = 0, frame = 0 + 500 @ frame_needed = 0, uses_anonymous_args = 0 + 501 .LVL46: + 502 0000 70B5 push {r4, r5, r6, lr} + 503 .LCFI3: + 504 .cfi_def_cfa_offset 16 + 505 .cfi_offset 4, -16 + 506 .cfi_offset 5, -12 + 507 .cfi_offset 6, -8 + 508 .cfi_offset 14, -4 + 509 0002 0500 movs r5, r0 + 510 0004 0C00 movs r4, r1 + 511 .LVL47: + 512 .LBB88: + 513 .LBB89: + 514 .LBB90: + 515 .LBB91: + 516 .loc 4 1837 0 + 517 0006 184B ldr r3, .L48 + 518 0008 1B68 ldr r3, [r3] + 519 .LBE91: + 520 .LBE90: + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 521 .loc 1 486 0 + 522 000a 9B01 lsls r3, r3, #6 + 523 000c 29D4 bmi .L47 + 524 .LVL48: + 525 .LBE89: + 526 .LBE88: + 527 .LBB92: + 528 .LBB93: + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + 529 .loc 1 464 0 + 530 000e 0368 ldr r3, [r0] + 531 0010 9B0C lsrs r3, r3, #18 + 532 0012 164A ldr r2, .L48+4 + 533 0014 D15C ldrb r1, [r2, r3] + ARM GAS /tmp/ccFUt0tx.s page 79 + + + 534 .LVL49: + 535 0016 4A01 lsls r2, r1, #5 + 536 0018 521A subs r2, r2, r1 + 537 001a 9301 lsls r3, r2, #6 + 538 001c 9B1A subs r3, r3, r2 + 539 001e DB00 lsls r3, r3, #3 + 540 0020 5B18 adds r3, r3, r1 + 541 0022 9802 lsls r0, r3, #10 + 542 .LVL50: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + 543 .loc 1 469 0 + 544 0024 6B68 ldr r3, [r5, #4] + 545 0026 990D lsrs r1, r3, #22 + 546 0028 0131 adds r1, r1, #1 + 547 002a FFF7FEFF bl __aeabi_uidiv + 548 .LVL51: + 549 .LBE93: + 550 .LBE92: + 551 .LBB94: + 552 .LBB95: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 553 .loc 4 834 0 + 554 002e 0E4B ldr r3, .L48 + 555 0030 1B68 ldr r3, [r3] + 556 .LBE95: + 557 .LBE94: + 274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 558 .loc 1 274 0 + 559 0032 5B07 lsls r3, r3, #29 + 560 0034 08D4 bmi .L45 + 561 .LBB96: + 562 .LBB97: + 814:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 563 .loc 4 814 0 + 564 0036 0C4A ldr r2, .L48 + 565 0038 1368 ldr r3, [r2] + 566 003a 0121 movs r1, #1 + 567 003c 0B43 orrs r3, r1 + 568 003e 1360 str r3, [r2] + 569 .L46: + 570 .LBE97: + 571 .LBE96: + 572 .LBB98: + 573 .LBB99: + 834:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 574 .loc 4 834 0 discriminator 1 + 575 0040 094B ldr r3, .L48 + 576 0042 1B68 ldr r3, [r3] + 577 .LBE99: + 578 .LBE98: + 277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 579 .loc 1 277 0 discriminator 1 + 580 0044 5B07 lsls r3, r3, #29 + 581 0046 FBD5 bpl .L46 + 582 .L45: + 284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 583 .loc 1 284 0 + ARM GAS /tmp/ccFUt0tx.s page 80 + + + 584 0048 2A68 ldr r2, [r5] + 585 004a 6D68 ldr r5, [r5, #4] + 586 .LVL52: + 587 .LBB100: + 588 .LBB101: +1838:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } +1839:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** +1840:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** /** +1841:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +1842:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +1843:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n +1844:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS +1845:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1846:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +1847:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1848:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values: +1849:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1850:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1851:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1852:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1853:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1854:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1855:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_24 +1856:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_32 +1857:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_48 +1858:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @param PLLDiv This parameter can be one of the following values: +1859:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_2 +1860:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_3 +1861:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_DIV_4 +1862:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** * @retval None +1863:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** */ +1864:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +1865:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** { +1866:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLD + 589 .loc 4 1866 0 + 590 004c 0649 ldr r1, .L48 + 591 004e CB68 ldr r3, [r1, #12] + 592 0050 074E ldr r6, .L48+8 + 593 0052 3340 ands r3, r6 + 594 0054 2A43 orrs r2, r5 + 595 .LVL53: + 596 0056 1343 orrs r3, r2 + 597 0058 CB60 str r3, [r1, #12] + 598 .LVL54: + 599 .LBE101: + 600 .LBE100: + 287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 601 .loc 1 287 0 + 602 005a 2100 movs r1, r4 + 603 005c FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 604 .LVL55: + 605 .L44: + 296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 606 .loc 1 296 0 + 607 @ sp needed + 608 .LVL56: + 609 0060 70BD pop {r4, r5, r6, pc} + ARM GAS /tmp/ccFUt0tx.s page 81 + + + 610 .LVL57: + 611 .L47: + 292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 612 .loc 1 292 0 + 613 0062 0020 movs r0, #0 + 614 .LVL58: + 615 0064 FCE7 b .L44 + 616 .L49: + 617 0066 C046 .align 2 + 618 .L48: + 619 0068 00100240 .word 1073876992 + 620 006c 00000000 .word PLLMulTable + 621 0070 FFFF02FF .word -16580609 + 622 .cfi_endproc + 623 .LFE274: + 625 .section .text.LL_PLL_ConfigSystemClock_HSE,"ax",%progbits + 626 .align 1 + 627 .global LL_PLL_ConfigSystemClock_HSE + 628 .syntax unified + 629 .code 16 + 630 .thumb_func + 631 .fpu softvfp + 633 LL_PLL_ConfigSystemClock_HSE: + 634 .LFB275: + 322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 635 .loc 1 322 0 + 636 .cfi_startproc + 637 @ args = 0, pretend = 0, frame = 0 + 638 @ frame_needed = 0, uses_anonymous_args = 0 + 639 .LVL59: + 640 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 641 .LCFI4: + 642 .cfi_def_cfa_offset 24 + 643 .cfi_offset 3, -24 + 644 .cfi_offset 4, -20 + 645 .cfi_offset 5, -16 + 646 .cfi_offset 6, -12 + 647 .cfi_offset 7, -8 + 648 .cfi_offset 14, -4 + 649 0002 0D00 movs r5, r1 + 650 0004 1600 movs r6, r2 + 651 0006 1C00 movs r4, r3 + 652 .LVL60: + 653 .LBB102: + 654 .LBB103: + 655 .LBB104: + 656 .LBB105: +1837:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 657 .loc 4 1837 0 + 658 0008 1D4B ldr r3, .L58 + 659 .LVL61: + 660 000a 1B68 ldr r3, [r3] + 661 .LBE105: + 662 .LBE104: + 486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 663 .loc 1 486 0 + 664 000c 9B01 lsls r3, r3, #6 + ARM GAS /tmp/ccFUt0tx.s page 82 + + + 665 000e 35D4 bmi .L56 + 666 .LVL62: + 667 .LBE103: + 668 .LBE102: + 669 .LBB106: + 670 .LBB107: + 464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + 671 .loc 1 464 0 + 672 0010 1368 ldr r3, [r2] + 673 0012 9B0C lsrs r3, r3, #18 + 674 0014 1B4A ldr r2, .L58+4 + 675 .LVL63: + 676 0016 D35C ldrb r3, [r2, r3] + 677 0018 5843 muls r0, r3 + 678 .LVL64: + 469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + 679 .loc 1 469 0 + 680 001a 7368 ldr r3, [r6, #4] + 681 001c 990D lsrs r1, r3, #22 + 682 .LVL65: + 683 001e 0131 adds r1, r1, #1 + 684 0020 FFF7FEFF bl __aeabi_uidiv + 685 .LVL66: + 686 .LBE107: + 687 .LBE106: + 688 .LBB108: + 689 .LBB109: + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 690 .loc 4 767 0 + 691 0024 164B ldr r3, .L58 + 692 0026 1B68 ldr r3, [r3] + 693 .LBE109: + 694 .LBE108: + 337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 695 .loc 1 337 0 + 696 0028 9B03 lsls r3, r3, #14 + 697 002a 10D4 bmi .L52 + 340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 698 .loc 1 340 0 + 699 002c 012D cmp r5, #1 + 700 002e 1ED0 beq .L57 + 701 .LBB110: + 702 .LBB111: + 737:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 703 .loc 4 737 0 + 704 0030 134A ldr r2, .L58 + 705 0032 1368 ldr r3, [r2] + 706 0034 1449 ldr r1, .L58+8 + 707 0036 0B40 ands r3, r1 + 708 0038 1360 str r3, [r2] + 709 .L54: + 710 .LBE111: + 711 .LBE110: + 712 .LBB112: + 713 .LBB113: + 747:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 714 .loc 4 747 0 + ARM GAS /tmp/ccFUt0tx.s page 83 + + + 715 003a 114A ldr r2, .L58 + 716 003c 1168 ldr r1, [r2] + 717 003e 8023 movs r3, #128 + 718 0040 5B02 lsls r3, r3, #9 + 719 0042 0B43 orrs r3, r1 + 720 0044 1360 str r3, [r2] + 721 .L55: + 722 .LBE113: + 723 .LBE112: + 724 .LBB114: + 725 .LBB115: + 767:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 726 .loc 4 767 0 discriminator 1 + 727 0046 0E4B ldr r3, .L58 + 728 0048 1B68 ldr r3, [r3] + 729 .LBE115: + 730 .LBE114: + 351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** { + 731 .loc 1 351 0 discriminator 1 + 732 004a 9B03 lsls r3, r3, #14 + 733 004c FBD5 bpl .L55 + 734 .L52: + 358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 735 .loc 1 358 0 + 736 004e 3768 ldr r7, [r6] + 737 0050 7268 ldr r2, [r6, #4] + 738 .LVL67: + 739 .LBB116: + 740 .LBB117: + 741 .loc 4 1866 0 + 742 0052 0B4D ldr r5, .L58 + 743 .LVL68: + 744 0054 EB68 ldr r3, [r5, #12] + 745 0056 0D49 ldr r1, .L58+12 + 746 0058 0B40 ands r3, r1 + 747 005a 8021 movs r1, #128 + 748 005c 4902 lsls r1, r1, #9 + 749 005e 3943 orrs r1, r7 + 750 0060 0A43 orrs r2, r1 + 751 .LVL69: + 752 0062 1343 orrs r3, r2 + 753 0064 EB60 str r3, [r5, #12] + 754 .LVL70: + 755 .LBE117: + 756 .LBE116: + 361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 757 .loc 1 361 0 + 758 0066 2100 movs r1, r4 + 759 0068 FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 760 .LVL71: + 761 .L51: + 370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** + 762 .loc 1 370 0 + 763 @ sp needed + 764 .LVL72: + 765 .LVL73: + 766 006c F8BD pop {r3, r4, r5, r6, r7, pc} + ARM GAS /tmp/ccFUt0tx.s page 84 + + + 767 .LVL74: + 768 .L57: + 769 .LBB118: + 770 .LBB119: + 727:Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h **** } + 771 .loc 4 727 0 + 772 006e 044A ldr r2, .L58 + 773 0070 1168 ldr r1, [r2] + 774 0072 8023 movs r3, #128 + 775 0074 DB02 lsls r3, r3, #11 + 776 0076 0B43 orrs r3, r1 + 777 0078 1360 str r3, [r2] + 778 007a DEE7 b .L54 + 779 .LVL75: + 780 .L56: + 781 .LBE119: + 782 .LBE118: + 366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c **** } + 783 .loc 1 366 0 + 784 007c 0020 movs r0, #0 + 785 .LVL76: + 786 007e F5E7 b .L51 + 787 .L59: + 788 .align 2 + 789 .L58: + 790 0080 00100240 .word 1073876992 + 791 0084 00000000 .word PLLMulTable + 792 0088 FFFFFBFF .word -262145 + 793 008c FFFF02FF .word -16580609 + 794 .cfi_endproc + 795 .LFE275: + 797 .text + 798 .Letext0: + 799 .file 6 "/usr/arm-none-eabi/include/machine/_default_types.h" + 800 .file 7 "/usr/arm-none-eabi/include/sys/_stdint.h" + 801 .file 8 "Drivers/CMSIS/Include/core_cm0plus.h" + 802 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 803 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 804 .file 11 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 805 .file 12 "/usr/arm-none-eabi/include/sys/lock.h" + 806 .file 13 "/usr/arm-none-eabi/include/sys/_types.h" + 807 .file 14 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 808 .file 15 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccFUt0tx.s page 85 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32l0xx_ll_utils.c + /tmp/ccFUt0tx.s:16 .text.UTILS_SetFlashLatency:0000000000000000 $t + /tmp/ccFUt0tx.s:22 .text.UTILS_SetFlashLatency:0000000000000000 UTILS_SetFlashLatency + /tmp/ccFUt0tx.s:156 .text.UTILS_SetFlashLatency:0000000000000070 $d + /tmp/ccFUt0tx.s:165 .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 $t + /tmp/ccFUt0tx.s:171 .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 UTILS_EnablePLLAndSwitchSystem + /tmp/ccFUt0tx.s:340 .text.UTILS_EnablePLLAndSwitchSystem:0000000000000098 $d + /tmp/ccFUt0tx.s:352 .text.LL_Init1msTick:0000000000000000 $t + /tmp/ccFUt0tx.s:359 .text.LL_Init1msTick:0000000000000000 LL_Init1msTick + /tmp/ccFUt0tx.s:398 .text.LL_Init1msTick:000000000000001c $d + /tmp/ccFUt0tx.s:403 .text.LL_mDelay:0000000000000000 $t + /tmp/ccFUt0tx.s:410 .text.LL_mDelay:0000000000000000 LL_mDelay + /tmp/ccFUt0tx.s:454 .text.LL_mDelay:0000000000000024 $d + /tmp/ccFUt0tx.s:459 .text.LL_SetSystemCoreClock:0000000000000000 $t + /tmp/ccFUt0tx.s:466 .text.LL_SetSystemCoreClock:0000000000000000 LL_SetSystemCoreClock + /tmp/ccFUt0tx.s:483 .text.LL_SetSystemCoreClock:0000000000000008 $d + /tmp/ccFUt0tx.s:488 .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 $t + /tmp/ccFUt0tx.s:495 .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 LL_PLL_ConfigSystemClock_HSI + /tmp/ccFUt0tx.s:619 .text.LL_PLL_ConfigSystemClock_HSI:0000000000000068 $d + /tmp/ccFUt0tx.s:626 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 $t + /tmp/ccFUt0tx.s:633 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 LL_PLL_ConfigSystemClock_HSE + /tmp/ccFUt0tx.s:790 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000080 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +AHBPrescTable +SystemCoreClock +__aeabi_uidiv +PLLMulTable diff --git a/build/sx1272.d b/build/sx1272.d new file mode 100644 index 0000000..51abbfc --- /dev/null +++ b/build/sx1272.d @@ -0,0 +1,156 @@ +build/sx1272.d: Drivers/BSP/Components/sx1272/sx1272.c \ + Drivers/BSP/Components/sx1272/sx1272.h Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Phy/radio.h \ + Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h \ + Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h \ + Middlewares/Third_Party/Lora/Utilities/delay.h + +Drivers/BSP/Components/sx1272/sx1272.h: + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Phy/radio.h: + +Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h: + +Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Middlewares/Third_Party/Lora/Utilities/delay.h: diff --git a/build/sx1272.lst b/build/sx1272.lst new file mode 100644 index 0000000..377444c --- /dev/null +++ b/build/sx1272.lst @@ -0,0 +1,9945 @@ +ARM GAS /tmp/ccwcPdtV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "sx1272.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SX1272OnDio4Irq,"ax",%progbits + 16 .align 1 + 17 .global SX1272OnDio4Irq + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 SX1272OnDio4Irq: + 24 .LFB131: + 25 .file 1 "./Drivers/BSP/Components/sx1272/sx1272.c" + 1:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 2:./Drivers/BSP/Components/sx1272/sx1272.c **** / _____) _ | | + 3:./Drivers/BSP/Components/sx1272/sx1272.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Drivers/BSP/Components/sx1272/sx1272.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Drivers/BSP/Components/sx1272/sx1272.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Drivers/BSP/Components/sx1272/sx1272.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Drivers/BSP/Components/sx1272/sx1272.c **** (C)2013 Semtech + 8:./Drivers/BSP/Components/sx1272/sx1272.c **** + 9:./Drivers/BSP/Components/sx1272/sx1272.c **** Description: Generic SX1272 driver implementation + 10:./Drivers/BSP/Components/sx1272/sx1272.c **** + 11:./Drivers/BSP/Components/sx1272/sx1272.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Drivers/BSP/Components/sx1272/sx1272.c **** + 13:./Drivers/BSP/Components/sx1272/sx1272.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 15:./Drivers/BSP/Components/sx1272/sx1272.c **** /******************************************************************************* + 16:./Drivers/BSP/Components/sx1272/sx1272.c **** * @file sx1272.c + 17:./Drivers/BSP/Components/sx1272/sx1272.c **** * @author MCD Application Team + 18:./Drivers/BSP/Components/sx1272/sx1272.c **** * @version V1.0.1 + 19:./Drivers/BSP/Components/sx1272/sx1272.c **** * @date 08-September-2017 + 20:./Drivers/BSP/Components/sx1272/sx1272.c **** * @brief driver sx1272 + 21:./Drivers/BSP/Components/sx1272/sx1272.c **** ****************************************************************************** + 22:./Drivers/BSP/Components/sx1272/sx1272.c **** * @attention + 23:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 24:./Drivers/BSP/Components/sx1272/sx1272.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics

+ 25:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 26:./Drivers/BSP/Components/sx1272/sx1272.c **** * Redistribution and use in source and binary forms, with or without modification, + 27:./Drivers/BSP/Components/sx1272/sx1272.c **** * are permitted provided that the following conditions are met: + 28:./Drivers/BSP/Components/sx1272/sx1272.c **** * 1. Redistributions of source code must retain the above copyright notice, + 29:./Drivers/BSP/Components/sx1272/sx1272.c **** * this list of conditions and the following disclaimer. + 30:./Drivers/BSP/Components/sx1272/sx1272.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 31:./Drivers/BSP/Components/sx1272/sx1272.c **** * this list of conditions and the following disclaimer in the documentation + 32:./Drivers/BSP/Components/sx1272/sx1272.c **** * and/or other materials provided with the distribution. + 33:./Drivers/BSP/Components/sx1272/sx1272.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + ARM GAS /tmp/ccwcPdtV.s page 2 + + + 34:./Drivers/BSP/Components/sx1272/sx1272.c **** * may be used to endorse or promote products derived from this software + 35:./Drivers/BSP/Components/sx1272/sx1272.c **** * without specific prior written permission. + 36:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 37:./Drivers/BSP/Components/sx1272/sx1272.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 38:./Drivers/BSP/Components/sx1272/sx1272.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 39:./Drivers/BSP/Components/sx1272/sx1272.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 40:./Drivers/BSP/Components/sx1272/sx1272.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 41:./Drivers/BSP/Components/sx1272/sx1272.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 42:./Drivers/BSP/Components/sx1272/sx1272.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 43:./Drivers/BSP/Components/sx1272/sx1272.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 44:./Drivers/BSP/Components/sx1272/sx1272.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 45:./Drivers/BSP/Components/sx1272/sx1272.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 46:./Drivers/BSP/Components/sx1272/sx1272.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 47:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 48:./Drivers/BSP/Components/sx1272/sx1272.c **** ****************************************************************************** + 49:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 50:./Drivers/BSP/Components/sx1272/sx1272.c **** + 51:./Drivers/BSP/Components/sx1272/sx1272.c **** #include "sx1272.h" + 52:./Drivers/BSP/Components/sx1272/sx1272.c **** #include "hw.h" + 53:./Drivers/BSP/Components/sx1272/sx1272.c **** #include "radio.h" + 54:./Drivers/BSP/Components/sx1272/sx1272.c **** #include "timeServer.h" + 55:./Drivers/BSP/Components/sx1272/sx1272.c **** #include "delay.h" + 56:./Drivers/BSP/Components/sx1272/sx1272.c **** + 57:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 58:./Drivers/BSP/Components/sx1272/sx1272.c **** * Local types definition + 59:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 60:./Drivers/BSP/Components/sx1272/sx1272.c **** + 61:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 62:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio registers definition + 63:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 64:./Drivers/BSP/Components/sx1272/sx1272.c **** typedef struct + 65:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 66:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioModems_t Modem; + 67:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t Addr; + 68:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t Value; + 69:./Drivers/BSP/Components/sx1272/sx1272.c **** }RadioRegisters_t; + 70:./Drivers/BSP/Components/sx1272/sx1272.c **** + 71:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 72:./Drivers/BSP/Components/sx1272/sx1272.c **** * FSK bandwidth definition + 73:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 74:./Drivers/BSP/Components/sx1272/sx1272.c **** typedef struct + 75:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 76:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t bandwidth; + 77:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t RegValue; + 78:./Drivers/BSP/Components/sx1272/sx1272.c **** }FskBandwidth_t; + 79:./Drivers/BSP/Components/sx1272/sx1272.c **** + 80:./Drivers/BSP/Components/sx1272/sx1272.c **** + 81:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 82:./Drivers/BSP/Components/sx1272/sx1272.c **** * Private functions prototypes + 83:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 84:./Drivers/BSP/Components/sx1272/sx1272.c **** + 85:./Drivers/BSP/Components/sx1272/sx1272.c **** + 86:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 87:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Resets the SX1272 + 88:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 89:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272Reset( void ); + 90:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 3 + + + 91:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 92:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Sets the SX1272 in transmission mode for the given time + 93:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] timeout Transmission timeout [ms] [0: continuous, others timeout] + 94:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 95:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetTx( uint32_t timeout ); + 96:./Drivers/BSP/Components/sx1272/sx1272.c **** + 97:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 98:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Writes the buffer contents to the SX1272 FIFO + 99:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 100:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] buffer Buffer containing data to be put on the FIFO. + 101:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] size Number of bytes to be written to the FIFO + 102:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 103:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272WriteFifo( uint8_t *buffer, uint8_t size ); + 104:./Drivers/BSP/Components/sx1272/sx1272.c **** + 105:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 106:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Reads the contents of the SX1272 FIFO + 107:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 108:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [OUT] buffer Buffer where to copy the FIFO read data. + 109:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] size Number of bytes to be read from the FIFO + 110:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 111:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272ReadFifo( uint8_t *buffer, uint8_t size ); + 112:./Drivers/BSP/Components/sx1272/sx1272.c **** + 113:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 114:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Sets the SX1272 operating mode + 115:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 116:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] opMode New operating mode + 117:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 118:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetOpMode( uint8_t opMode ); + 119:./Drivers/BSP/Components/sx1272/sx1272.c **** + 120:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 121:./Drivers/BSP/Components/sx1272/sx1272.c **** * SX1272 DIO IRQ callback functions prototype + 122:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 123:./Drivers/BSP/Components/sx1272/sx1272.c **** + 124:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 125:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 0 IRQ callback + 126:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 127:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio0Irq( void ); + 128:./Drivers/BSP/Components/sx1272/sx1272.c **** + 129:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 130:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 1 IRQ callback + 131:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 132:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio1Irq( void ); + 133:./Drivers/BSP/Components/sx1272/sx1272.c **** + 134:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 135:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 2 IRQ callback + 136:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 137:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio2Irq( void ); + 138:./Drivers/BSP/Components/sx1272/sx1272.c **** + 139:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 140:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 3 IRQ callback + 141:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 142:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio3Irq( void ); + 143:./Drivers/BSP/Components/sx1272/sx1272.c **** + 144:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 145:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 4 IRQ callback + 146:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 147:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio4Irq( void ); + ARM GAS /tmp/ccwcPdtV.s page 4 + + + 148:./Drivers/BSP/Components/sx1272/sx1272.c **** + 149:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 150:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief DIO 5 IRQ callback + 151:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 152:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio5Irq( void ); + 153:./Drivers/BSP/Components/sx1272/sx1272.c **** + 154:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 155:./Drivers/BSP/Components/sx1272/sx1272.c **** * \brief Tx & Rx timeout timer callback + 156:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 157:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnTimeoutIrq( void ); + 158:./Drivers/BSP/Components/sx1272/sx1272.c **** + 159:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 160:./Drivers/BSP/Components/sx1272/sx1272.c **** * Private global constants + 161:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 162:./Drivers/BSP/Components/sx1272/sx1272.c **** + 163:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 164:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio hardware registers initialization + 165:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 166:./Drivers/BSP/Components/sx1272/sx1272.c **** * \remark RADIO_INIT_REGISTERS_VALUE is defined in sx1272-board.h file + 167:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 168:./Drivers/BSP/Components/sx1272/sx1272.c **** const RadioRegisters_t RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE; + 169:./Drivers/BSP/Components/sx1272/sx1272.c **** + 170:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 171:./Drivers/BSP/Components/sx1272/sx1272.c **** * Constant values need to compute the RSSI value + 172:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 173:./Drivers/BSP/Components/sx1272/sx1272.c **** #define RSSI_OFFSET -139 + 174:./Drivers/BSP/Components/sx1272/sx1272.c **** + 175:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 176:./Drivers/BSP/Components/sx1272/sx1272.c **** * Precomputed FSK bandwidth registers values + 177:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 178:./Drivers/BSP/Components/sx1272/sx1272.c **** const FskBandwidth_t FskBandwidths[] = + 179:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 180:./Drivers/BSP/Components/sx1272/sx1272.c **** { 2600 , 0x17 }, + 181:./Drivers/BSP/Components/sx1272/sx1272.c **** { 3100 , 0x0F }, + 182:./Drivers/BSP/Components/sx1272/sx1272.c **** { 3900 , 0x07 }, + 183:./Drivers/BSP/Components/sx1272/sx1272.c **** { 5200 , 0x16 }, + 184:./Drivers/BSP/Components/sx1272/sx1272.c **** { 6300 , 0x0E }, + 185:./Drivers/BSP/Components/sx1272/sx1272.c **** { 7800 , 0x06 }, + 186:./Drivers/BSP/Components/sx1272/sx1272.c **** { 10400 , 0x15 }, + 187:./Drivers/BSP/Components/sx1272/sx1272.c **** { 12500 , 0x0D }, + 188:./Drivers/BSP/Components/sx1272/sx1272.c **** { 15600 , 0x05 }, + 189:./Drivers/BSP/Components/sx1272/sx1272.c **** { 20800 , 0x14 }, + 190:./Drivers/BSP/Components/sx1272/sx1272.c **** { 25000 , 0x0C }, + 191:./Drivers/BSP/Components/sx1272/sx1272.c **** { 31300 , 0x04 }, + 192:./Drivers/BSP/Components/sx1272/sx1272.c **** { 41700 , 0x13 }, + 193:./Drivers/BSP/Components/sx1272/sx1272.c **** { 50000 , 0x0B }, + 194:./Drivers/BSP/Components/sx1272/sx1272.c **** { 62500 , 0x03 }, + 195:./Drivers/BSP/Components/sx1272/sx1272.c **** { 83333 , 0x12 }, + 196:./Drivers/BSP/Components/sx1272/sx1272.c **** { 100000, 0x0A }, + 197:./Drivers/BSP/Components/sx1272/sx1272.c **** { 125000, 0x02 }, + 198:./Drivers/BSP/Components/sx1272/sx1272.c **** { 166700, 0x11 }, + 199:./Drivers/BSP/Components/sx1272/sx1272.c **** { 200000, 0x09 }, + 200:./Drivers/BSP/Components/sx1272/sx1272.c **** { 250000, 0x01 }, + 201:./Drivers/BSP/Components/sx1272/sx1272.c **** { 300000, 0x00 }, // Invalid Bandwidth + 202:./Drivers/BSP/Components/sx1272/sx1272.c **** }; + 203:./Drivers/BSP/Components/sx1272/sx1272.c **** + 204:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + ARM GAS /tmp/ccwcPdtV.s page 5 + + + 205:./Drivers/BSP/Components/sx1272/sx1272.c **** * Private global variables + 206:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 207:./Drivers/BSP/Components/sx1272/sx1272.c **** + 208:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 209:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio callbacks variable + 210:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 211:./Drivers/BSP/Components/sx1272/sx1272.c **** static RadioEvents_t *RadioEvents; + 212:./Drivers/BSP/Components/sx1272/sx1272.c **** + 213:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 214:./Drivers/BSP/Components/sx1272/sx1272.c **** * Reception buffer + 215:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 216:./Drivers/BSP/Components/sx1272/sx1272.c **** static uint8_t RxTxBuffer[RX_BUFFER_SIZE]; + 217:./Drivers/BSP/Components/sx1272/sx1272.c **** + 218:./Drivers/BSP/Components/sx1272/sx1272.c **** static LoRaBoardCallback_t *LoRaBoardCallbacks; + 219:./Drivers/BSP/Components/sx1272/sx1272.c **** + 220:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 221:./Drivers/BSP/Components/sx1272/sx1272.c **** * Public global variables + 222:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 223:./Drivers/BSP/Components/sx1272/sx1272.c **** + 224:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 225:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio hardware and global parameters + 226:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 227:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272_t SX1272; + 228:./Drivers/BSP/Components/sx1272/sx1272.c **** + 229:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 230:./Drivers/BSP/Components/sx1272/sx1272.c **** * Hardware DIO IRQ callback initialization + 231:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 232:./Drivers/BSP/Components/sx1272/sx1272.c **** DioIrqHandler *DioIrq[] = { SX1272OnDio0Irq, SX1272OnDio1Irq, + 233:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272OnDio2Irq, SX1272OnDio3Irq, + 234:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272OnDio4Irq, NULL }; + 235:./Drivers/BSP/Components/sx1272/sx1272.c **** + 236:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 237:./Drivers/BSP/Components/sx1272/sx1272.c **** * Tx and Rx timers + 238:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 239:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerEvent_t TxTimeoutTimer; + 240:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerEvent_t RxTimeoutTimer; + 241:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerEvent_t RxTimeoutSyncWord; + 242:./Drivers/BSP/Components/sx1272/sx1272.c **** + 243:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 244:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio driver functions implementation + 245:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 246:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272BoardInit( LoRaBoardCallback_t *callbacks ) + 247:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 248:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks =callbacks; + 249:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 250:./Drivers/BSP/Components/sx1272/sx1272.c **** + 251:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t SX1272Init( RadioEvents_t *events ) + 252:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 253:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 254:./Drivers/BSP/Components/sx1272/sx1272.c **** + 255:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents = events; + 256:./Drivers/BSP/Components/sx1272/sx1272.c **** + 257:./Drivers/BSP/Components/sx1272/sx1272.c **** // Initialize driver timeout timers + 258:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerInit( &TxTimeoutTimer, SX1272OnTimeoutIrq ); + 259:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerInit( &RxTimeoutTimer, SX1272OnTimeoutIrq ); + 260:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerInit( &RxTimeoutSyncWord, SX1272OnTimeoutIrq ); + 261:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 6 + + + 262:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetXO( SET ); + 263:./Drivers/BSP/Components/sx1272/sx1272.c **** + 264:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Reset( ); + 265:./Drivers/BSP/Components/sx1272/sx1272.c **** + 266:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_SLEEP ); + 267:./Drivers/BSP/Components/sx1272/sx1272.c **** + 268:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardIoIrqInit( DioIrq ); + 269:./Drivers/BSP/Components/sx1272/sx1272.c **** + 270:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ ) + 271:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 272:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( RadioRegsInit[i].Modem ); + 273:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); + 274:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 275:./Drivers/BSP/Components/sx1272/sx1272.c **** + 276:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( MODEM_FSK ); + 277:./Drivers/BSP/Components/sx1272/sx1272.c **** + 278:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 279:./Drivers/BSP/Components/sx1272/sx1272.c **** + 280:./Drivers/BSP/Components/sx1272/sx1272.c **** return ( uint32_t )LoRaBoardCallbacks->SX1272BoardGetWakeTime( ) + RADIO_WAKEUP_TIME;// BOARD_W + 281:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 282:./Drivers/BSP/Components/sx1272/sx1272.c **** + 283:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioState_t SX1272GetStatus( void ) + 284:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 285:./Drivers/BSP/Components/sx1272/sx1272.c **** return SX1272.Settings.State; + 286:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 287:./Drivers/BSP/Components/sx1272/sx1272.c **** + 288:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetChannel( uint32_t freq ) + 289:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 290:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t channel; + 291:./Drivers/BSP/Components/sx1272/sx1272.c **** + 292:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Channel = freq; + 293:./Drivers/BSP/Components/sx1272/sx1272.c **** + 294:./Drivers/BSP/Components/sx1272/sx1272.c **** SX_FREQ_TO_CHANNEL( channel, freq ); + 295:./Drivers/BSP/Components/sx1272/sx1272.c **** + 296:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FRFMSB, ( uint8_t )( ( channel >> 16 ) & 0xFF ) ); + 297:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FRFMID, ( uint8_t )( ( channel >> 8 ) & 0xFF ) ); + 298:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FRFLSB, ( uint8_t )( channel & 0xFF ) ); + 299:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 300:./Drivers/BSP/Components/sx1272/sx1272.c **** + 301:./Drivers/BSP/Components/sx1272/sx1272.c **** bool SX1272IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarri + 302:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 303:./Drivers/BSP/Components/sx1272/sx1272.c **** bool status = true; + 304:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t rssi = 0; + 305:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t carrierSenseTime = 0; + 306:./Drivers/BSP/Components/sx1272/sx1272.c **** + 307:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 308:./Drivers/BSP/Components/sx1272/sx1272.c **** + 309:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetChannel( freq ); + 310:./Drivers/BSP/Components/sx1272/sx1272.c **** + 311:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_RECEIVER ); + 312:./Drivers/BSP/Components/sx1272/sx1272.c **** + 313:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 1 ); + 314:./Drivers/BSP/Components/sx1272/sx1272.c **** + 315:./Drivers/BSP/Components/sx1272/sx1272.c **** carrierSenseTime = TimerGetCurrentTime( ); + 316:./Drivers/BSP/Components/sx1272/sx1272.c **** + 317:./Drivers/BSP/Components/sx1272/sx1272.c **** // Perform carrier sense for maxCarrierSenseTime + 318:./Drivers/BSP/Components/sx1272/sx1272.c **** while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + ARM GAS /tmp/ccwcPdtV.s page 7 + + + 319:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 320:./Drivers/BSP/Components/sx1272/sx1272.c **** rssi = SX1272ReadRssi( modem ); + 321:./Drivers/BSP/Components/sx1272/sx1272.c **** + 322:./Drivers/BSP/Components/sx1272/sx1272.c **** if( rssi > rssiThresh ) + 323:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 324:./Drivers/BSP/Components/sx1272/sx1272.c **** status = false; + 325:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 326:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 327:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 328:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetSleep( ); + 329:./Drivers/BSP/Components/sx1272/sx1272.c **** return status; + 330:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 331:./Drivers/BSP/Components/sx1272/sx1272.c **** + 332:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t SX1272Random( void ) + 333:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 334:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 335:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t rnd = 0; + 336:./Drivers/BSP/Components/sx1272/sx1272.c **** + 337:./Drivers/BSP/Components/sx1272/sx1272.c **** /* + 338:./Drivers/BSP/Components/sx1272/sx1272.c **** * Radio setup for random number generation + 339:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 340:./Drivers/BSP/Components/sx1272/sx1272.c **** // Set LoRa modem ON + 341:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( MODEM_LORA ); + 342:./Drivers/BSP/Components/sx1272/sx1272.c **** + 343:./Drivers/BSP/Components/sx1272/sx1272.c **** // Disable LoRa modem interrupts + 344:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | + 345:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_RXDONE | + 346:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_PAYLOADCRCERROR | + 347:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + 348:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_TXDONE | + 349:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDONE | + 350:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + 351:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDETECTED ); + 352:./Drivers/BSP/Components/sx1272/sx1272.c **** + 353:./Drivers/BSP/Components/sx1272/sx1272.c **** // Set radio in continuous reception + 354:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_RECEIVER ); + 355:./Drivers/BSP/Components/sx1272/sx1272.c **** + 356:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < 32; i++ ) + 357:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 358:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 1 ); + 359:./Drivers/BSP/Components/sx1272/sx1272.c **** // Unfiltered RSSI value reading. Only takes the LSB value + 360:./Drivers/BSP/Components/sx1272/sx1272.c **** rnd |= ( ( uint32_t )SX1272Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i; + 361:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 362:./Drivers/BSP/Components/sx1272/sx1272.c **** + 363:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetSleep( ); + 364:./Drivers/BSP/Components/sx1272/sx1272.c **** + 365:./Drivers/BSP/Components/sx1272/sx1272.c **** return rnd; + 366:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 367:./Drivers/BSP/Components/sx1272/sx1272.c **** + 368:./Drivers/BSP/Components/sx1272/sx1272.c **** /*! + 369:./Drivers/BSP/Components/sx1272/sx1272.c **** * Returns the known FSK bandwidth registers value + 370:./Drivers/BSP/Components/sx1272/sx1272.c **** * + 371:./Drivers/BSP/Components/sx1272/sx1272.c **** * \param [IN] bandwidth Bandwidth value in Hz + 372:./Drivers/BSP/Components/sx1272/sx1272.c **** * \retval regValue Bandwidth register value. + 373:./Drivers/BSP/Components/sx1272/sx1272.c **** */ + 374:./Drivers/BSP/Components/sx1272/sx1272.c **** static uint8_t GetFskBandwidthRegValue( uint32_t bandwidth ) + 375:./Drivers/BSP/Components/sx1272/sx1272.c **** { + ARM GAS /tmp/ccwcPdtV.s page 8 + + + 376:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 377:./Drivers/BSP/Components/sx1272/sx1272.c **** + 378:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) + 379:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 380:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandw + 381:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 382:./Drivers/BSP/Components/sx1272/sx1272.c **** return FskBandwidths[i].RegValue; + 383:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 384:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 385:./Drivers/BSP/Components/sx1272/sx1272.c **** // ERROR: Value not found + 386:./Drivers/BSP/Components/sx1272/sx1272.c **** while( 1 ); + 387:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 388:./Drivers/BSP/Components/sx1272/sx1272.c **** + 389:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetRxConfig( RadioModems_t modem, uint32_t bandwidth, + 390:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t datarate, uint8_t coderate, + 391:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t bandwidthAfc, uint16_t preambleLen, + 392:./Drivers/BSP/Components/sx1272/sx1272.c **** uint16_t symbTimeout, bool fixLen, + 393:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t payloadLen, + 394:./Drivers/BSP/Components/sx1272/sx1272.c **** bool crcOn, bool freqHopOn, uint8_t hopPeriod, + 395:./Drivers/BSP/Components/sx1272/sx1272.c **** bool iqInverted, bool rxContinuous ) + 396:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 397:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 398:./Drivers/BSP/Components/sx1272/sx1272.c **** + 399:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( modem ) + 400:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 401:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 402:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 403:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Bandwidth = bandwidth; + 404:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate = datarate; + 405:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.BandwidthAfc = bandwidthAfc; + 406:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.FixLen = fixLen; + 407:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PayloadLen = payloadLen; + 408:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.CrcOn = crcOn; + 409:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.IqInverted = iqInverted; + 410:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.RxContinuous = rxContinuous; + 411:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PreambleLen = preambleLen; + 412:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.RxSingleTimeout = ( uint32_t )( symbTimeout * ( ( 1.0 / ( double )d + 413:./Drivers/BSP/Components/sx1272/sx1272.c **** + 414:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); + 415:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); + 416:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); + 417:./Drivers/BSP/Components/sx1272/sx1272.c **** + 418:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) ); + 419:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) ); + 420:./Drivers/BSP/Components/sx1272/sx1272.c **** + 421:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); + 422:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); + 423:./Drivers/BSP/Components/sx1272/sx1272.c **** + 424:./Drivers/BSP/Components/sx1272/sx1272.c **** if( fixLen == 1 ) + 425:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 426:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PAYLOADLENGTH, payloadLen ); + 427:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 428:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 429:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 430:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum + 431:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 432:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 9 + + + 433:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG1, + 434:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_PACKETCONFIG1 ) & + 435:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_CRC_MASK & + 436:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | + 437:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 438:./Drivers/BSP/Components/sx1272/sx1272.c **** ( crcOn << 4 ) ); + 439:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG2, ( SX1272Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DA + 440:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 441:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 442:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 443:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 444:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Bandwidth = bandwidth; + 445:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Datarate = datarate; + 446:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Coderate = coderate; + 447:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PreambleLen = preambleLen; + 448:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FixLen = fixLen; + 449:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PayloadLen = payloadLen; + 450:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.CrcOn = crcOn; + 451:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FreqHopOn = freqHopOn; + 452:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.HopPeriod = hopPeriod; + 453:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.IqInverted = iqInverted; + 454:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.RxContinuous = rxContinuous; + 455:./Drivers/BSP/Components/sx1272/sx1272.c **** + 456:./Drivers/BSP/Components/sx1272/sx1272.c **** if( datarate > 12 ) + 457:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 458:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = 12; + 459:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 460:./Drivers/BSP/Components/sx1272/sx1272.c **** else if( datarate < 6 ) + 461:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 462:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = 6; + 463:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 464:./Drivers/BSP/Components/sx1272/sx1272.c **** + 465:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 466:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 467:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 468:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize = 0x01; + 469:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 470:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 471:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 472:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize = 0x00; + 473:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 474:./Drivers/BSP/Components/sx1272/sx1272.c **** + 475:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_MODEMCONFIG1, + 476:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG1 ) & + 477:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_BW_MASK & + 478:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_CODINGRATE_MASK & + 479:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & + 480:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & + 481:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | + 482:./Drivers/BSP/Components/sx1272/sx1272.c **** ( bandwidth << 6 ) | ( coderate << 3 ) | + 483:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 484:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 485:./Drivers/BSP/Components/sx1272/sx1272.c **** + 486:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_MODEMCONFIG2, + 487:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG2 ) & + 488:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG2_SF_MASK & + 489:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | + ARM GAS /tmp/ccwcPdtV.s page 10 + + + 490:./Drivers/BSP/Components/sx1272/sx1272.c **** ( datarate << 4 ) | + 491:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); + 492:./Drivers/BSP/Components/sx1272/sx1272.c **** + 493:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) ); + 494:./Drivers/BSP/Components/sx1272/sx1272.c **** + 495:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); + 496:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); + 497:./Drivers/BSP/Components/sx1272/sx1272.c **** + 498:./Drivers/BSP/Components/sx1272/sx1272.c **** if( fixLen == 1 ) + 499:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 500:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PAYLOADLENGTH, payloadLen ); + 501:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 502:./Drivers/BSP/Components/sx1272/sx1272.c **** + 503:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) + 504:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 505:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PLLHOP, ( SX1272Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MAS + 506:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_HOPPERIOD, SX1272.Settings.LoRa.HopPeriod ); + 507:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 508:./Drivers/BSP/Components/sx1272/sx1272.c **** + 509:./Drivers/BSP/Components/sx1272/sx1272.c **** if( datarate == 6 ) + 510:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 511:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTOPTIMIZE, + 512:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_DETECTOPTIMIZE ) & + 513:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 514:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF6 ); + 515:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTIONTHRESHOLD, + 516:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONTHRESH_SF6 ); + 517:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 518:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 519:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 520:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTOPTIMIZE, + 521:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_DETECTOPTIMIZE ) & + 522:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 523:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); + 524:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTIONTHRESHOLD, + 525:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); + 526:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 527:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 528:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 529:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 530:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 531:./Drivers/BSP/Components/sx1272/sx1272.c **** + 532:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + 533:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t bandwidth, uint32_t datarate, + 534:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t coderate, uint16_t preambleLen, + 535:./Drivers/BSP/Components/sx1272/sx1272.c **** bool fixLen, bool crcOn, bool freqHopOn, + 536:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) + 537:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 538:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 539:./Drivers/BSP/Components/sx1272/sx1272.c **** + 540:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetRfTxPower( power ); + 541:./Drivers/BSP/Components/sx1272/sx1272.c **** + 542:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( modem ) + 543:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 544:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 545:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 546:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Power = power; + ARM GAS /tmp/ccwcPdtV.s page 11 + + + 547:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Fdev = fdev; + 548:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Bandwidth = bandwidth; + 549:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate = datarate; + 550:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PreambleLen = preambleLen; + 551:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.FixLen = fixLen; + 552:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.CrcOn = crcOn; + 553:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.IqInverted = iqInverted; + 554:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.TxTimeout = timeout; + 555:./Drivers/BSP/Components/sx1272/sx1272.c **** + 556:./Drivers/BSP/Components/sx1272/sx1272.c **** fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); + 557:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); + 558:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); + 559:./Drivers/BSP/Components/sx1272/sx1272.c **** + 560:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); + 561:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); + 562:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); + 563:./Drivers/BSP/Components/sx1272/sx1272.c **** + 564:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); + 565:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLELSB, preambleLen & 0xFF ); + 566:./Drivers/BSP/Components/sx1272/sx1272.c **** + 567:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG1, + 568:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_PACKETCONFIG1 ) & + 569:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_CRC_MASK & + 570:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | + 571:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 572:./Drivers/BSP/Components/sx1272/sx1272.c **** ( crcOn << 4 ) ); + 573:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG2, ( SX1272Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DA + 574:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 575:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 576:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 577:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 578:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Power = power; + 579:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Bandwidth = bandwidth; + 580:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Datarate = datarate; + 581:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Coderate = coderate; + 582:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PreambleLen = preambleLen; + 583:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FixLen = fixLen; + 584:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FreqHopOn = freqHopOn; + 585:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.HopPeriod = hopPeriod; + 586:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.CrcOn = crcOn; + 587:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.IqInverted = iqInverted; + 588:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.TxTimeout = timeout; + 589:./Drivers/BSP/Components/sx1272/sx1272.c **** + 590:./Drivers/BSP/Components/sx1272/sx1272.c **** if( datarate > 12 ) + 591:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 592:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = 12; + 593:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 594:./Drivers/BSP/Components/sx1272/sx1272.c **** else if( datarate < 6 ) + 595:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 596:./Drivers/BSP/Components/sx1272/sx1272.c **** datarate = 6; + 597:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 598:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 599:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 600:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 601:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize = 0x01; + 602:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 603:./Drivers/BSP/Components/sx1272/sx1272.c **** else + ARM GAS /tmp/ccwcPdtV.s page 12 + + + 604:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 605:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize = 0x00; + 606:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 607:./Drivers/BSP/Components/sx1272/sx1272.c **** + 608:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) + 609:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 610:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PLLHOP, ( SX1272Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MAS + 611:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_HOPPERIOD, SX1272.Settings.LoRa.HopPeriod ); + 612:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 613:./Drivers/BSP/Components/sx1272/sx1272.c **** + 614:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_MODEMCONFIG1, + 615:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG1 ) & + 616:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_BW_MASK & + 617:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_CODINGRATE_MASK & + 618:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & + 619:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & + 620:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) | + 621:./Drivers/BSP/Components/sx1272/sx1272.c **** ( bandwidth << 6 ) | ( coderate << 3 ) | + 622:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 623:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 624:./Drivers/BSP/Components/sx1272/sx1272.c **** + 625:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_MODEMCONFIG2, + 626:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG2 ) & + 627:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG2_SF_MASK ) | + 628:./Drivers/BSP/Components/sx1272/sx1272.c **** ( datarate << 4 ) ); + 629:./Drivers/BSP/Components/sx1272/sx1272.c **** + 630:./Drivers/BSP/Components/sx1272/sx1272.c **** + 631:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); + 632:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); + 633:./Drivers/BSP/Components/sx1272/sx1272.c **** + 634:./Drivers/BSP/Components/sx1272/sx1272.c **** if( datarate == 6 ) + 635:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 636:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTOPTIMIZE, + 637:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_DETECTOPTIMIZE ) & + 638:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 639:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF6 ); + 640:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTIONTHRESHOLD, + 641:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONTHRESH_SF6 ); + 642:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 643:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 644:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 645:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTOPTIMIZE, + 646:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_DETECTOPTIMIZE ) & + 647:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 648:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); + 649:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_DETECTIONTHRESHOLD, + 650:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); + 651:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 652:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 653:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 654:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 655:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 656:./Drivers/BSP/Components/sx1272/sx1272.c **** + 657:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t SX1272GetTimeOnAir( RadioModems_t modem, uint8_t pktLen ) + 658:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 659:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t airTime = 0; + 660:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 13 + + + 661:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( modem ) + 662:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 663:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 664:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 665:./Drivers/BSP/Components/sx1272/sx1272.c **** airTime = (uint32_t) round( ( 8 * ( SX1272.Settings.Fsk.PreambleLen + + 666:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MAS + 667:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + + 668:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( ( SX1272Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDR + 669:./Drivers/BSP/Components/sx1272/sx1272.c **** pktLen + + 670:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / + 671:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate ) * 1000 ); + 672:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 673:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 674:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 675:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 676:./Drivers/BSP/Components/sx1272/sx1272.c **** double bw = 0.0; + 677:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.LoRa.Bandwidth ) + 678:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 679:./Drivers/BSP/Components/sx1272/sx1272.c **** case 0: // 125 kHz + 680:./Drivers/BSP/Components/sx1272/sx1272.c **** bw = 125000; + 681:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 682:./Drivers/BSP/Components/sx1272/sx1272.c **** case 1: // 250 kHz + 683:./Drivers/BSP/Components/sx1272/sx1272.c **** bw = 250000; + 684:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 685:./Drivers/BSP/Components/sx1272/sx1272.c **** case 2: // 500 kHz + 686:./Drivers/BSP/Components/sx1272/sx1272.c **** bw = 500000; + 687:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 688:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 689:./Drivers/BSP/Components/sx1272/sx1272.c **** + 690:./Drivers/BSP/Components/sx1272/sx1272.c **** // Symbol rate : time for one symbol (secs) + 691:./Drivers/BSP/Components/sx1272/sx1272.c **** double rs = bw / ( 1 << SX1272.Settings.LoRa.Datarate ); + 692:./Drivers/BSP/Components/sx1272/sx1272.c **** double ts = 1 / rs; + 693:./Drivers/BSP/Components/sx1272/sx1272.c **** // time of preamble + 694:./Drivers/BSP/Components/sx1272/sx1272.c **** double tPreamble = ( SX1272.Settings.LoRa.PreambleLen + 4.25 ) * ts; + 695:./Drivers/BSP/Components/sx1272/sx1272.c **** // Symbol length of payload and time + 696:./Drivers/BSP/Components/sx1272/sx1272.c **** double tmp = ceil( ( 8 * pktLen - 4 * SX1272.Settings.LoRa.Datarate + + 697:./Drivers/BSP/Components/sx1272/sx1272.c **** 28 + 16 * SX1272.Settings.LoRa.CrcOn - + 698:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.FixLen ? 20 : 0 ) ) / + 699:./Drivers/BSP/Components/sx1272/sx1272.c **** ( double )( 4 * ( SX1272.Settings.LoRa.Datarate - + 700:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) + 701:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.Coderate + 4 ); + 702:./Drivers/BSP/Components/sx1272/sx1272.c **** double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); + 703:./Drivers/BSP/Components/sx1272/sx1272.c **** double tPayload = nPayload * ts; + 704:./Drivers/BSP/Components/sx1272/sx1272.c **** // Time on air + 705:./Drivers/BSP/Components/sx1272/sx1272.c **** double tOnAir = tPreamble + tPayload; + 706:./Drivers/BSP/Components/sx1272/sx1272.c **** // return ms secs + 707:./Drivers/BSP/Components/sx1272/sx1272.c **** airTime = (uint32_t) floor( tOnAir * 1000 + 0.999 ); + 708:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 709:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 710:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 711:./Drivers/BSP/Components/sx1272/sx1272.c **** return airTime; + 712:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 713:./Drivers/BSP/Components/sx1272/sx1272.c **** + 714:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272Send( uint8_t *buffer, uint8_t size ) + 715:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 716:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t txTimeout = 0; + 717:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 14 + + + 718:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 719:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 720:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 721:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 722:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 723:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = size; + 724:./Drivers/BSP/Components/sx1272/sx1272.c **** + 725:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.FixLen == false ) + 726:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 727:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteFifo( ( uint8_t* )&size, 1 ); + 728:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 729:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 730:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 731:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PAYLOADLENGTH, size ); + 732:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 733:./Drivers/BSP/Components/sx1272/sx1272.c **** + 734:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( size > 0 ) && ( size <= 64 ) ) + 735:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 736:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.ChunkSize = size; + 737:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 738:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 739:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 740:./Drivers/BSP/Components/sx1272/sx1272.c **** memcpy1( RxTxBuffer, buffer, size ); + 741:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.ChunkSize = 32; + 742:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 743:./Drivers/BSP/Components/sx1272/sx1272.c **** + 744:./Drivers/BSP/Components/sx1272/sx1272.c **** // Write payload buffer + 745:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteFifo( buffer, SX1272.Settings.FskPacketHandler.ChunkSize ); + 746:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.ChunkSize; + 747:./Drivers/BSP/Components/sx1272/sx1272.c **** txTimeout = SX1272.Settings.Fsk.TxTimeout; + 748:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 749:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 750:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 751:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 752:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.IqInverted == true ) + 753:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 754:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ, ( ( SX1272Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_ + 755:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); + 756:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 757:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 758:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 759:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ, ( ( SX1272Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_ + 760:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); + 761:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 762:./Drivers/BSP/Components/sx1272/sx1272.c **** + 763:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRaPacketHandler.Size = size; + 764:./Drivers/BSP/Components/sx1272/sx1272.c **** + 765:./Drivers/BSP/Components/sx1272/sx1272.c **** // Initializes the payload size + 766:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PAYLOADLENGTH, size ); + 767:./Drivers/BSP/Components/sx1272/sx1272.c **** + 768:./Drivers/BSP/Components/sx1272/sx1272.c **** // Full buffer used for Tx + 769:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFOTXBASEADDR, 0 ); + 770:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFOADDRPTR, 0 ); + 771:./Drivers/BSP/Components/sx1272/sx1272.c **** + 772:./Drivers/BSP/Components/sx1272/sx1272.c **** // FIFO operations can not take place in Sleep mode + 773:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP ) + 774:./Drivers/BSP/Components/sx1272/sx1272.c **** { + ARM GAS /tmp/ccwcPdtV.s page 15 + + + 775:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetStby( ); + 776:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 1 ); + 777:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 778:./Drivers/BSP/Components/sx1272/sx1272.c **** // Write payload buffer + 779:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteFifo( buffer, size ); + 780:./Drivers/BSP/Components/sx1272/sx1272.c **** txTimeout = SX1272.Settings.LoRa.TxTimeout; + 781:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 782:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 783:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 784:./Drivers/BSP/Components/sx1272/sx1272.c **** + 785:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetTx( txTimeout ); + 786:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 787:./Drivers/BSP/Components/sx1272/sx1272.c **** + 788:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetSleep( void ) + 789:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 790:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); + 791:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &TxTimeoutTimer ); + 792:./Drivers/BSP/Components/sx1272/sx1272.c **** + 793:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_SLEEP ); + 794:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 795:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 796:./Drivers/BSP/Components/sx1272/sx1272.c **** + 797:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetStby( void ) + 798:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 799:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); + 800:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &TxTimeoutTimer ); + 801:./Drivers/BSP/Components/sx1272/sx1272.c **** + 802:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_STANDBY ); + 803:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 804:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 805:./Drivers/BSP/Components/sx1272/sx1272.c **** + 806:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetRx( uint32_t timeout ) + 807:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 808:./Drivers/BSP/Components/sx1272/sx1272.c **** bool rxContinuous = false; + 809:./Drivers/BSP/Components/sx1272/sx1272.c **** + 810:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 811:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 812:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 813:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 814:./Drivers/BSP/Components/sx1272/sx1272.c **** rxContinuous = SX1272.Settings.Fsk.RxContinuous; + 815:./Drivers/BSP/Components/sx1272/sx1272.c **** + 816:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=PayloadReady + 817:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO1=FifoLevel + 818:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO2=SyncAddr + 819:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO3=FifoEmpty + 820:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO4=Preamble + 821:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO5=ModeReady + 822:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MAS + 823:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 824:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO2_MAS + 825:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO0_00 + 826:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_00 + 827:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO2_11 + 828:./Drivers/BSP/Components/sx1272/sx1272.c **** + 829:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING2, ( SX1272Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MAS + 830:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_MAP_MASK + 831:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_DIO4_11 + ARM GAS /tmp/ccwcPdtV.s page 16 + + + 832:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_MAP_PREA + 833:./Drivers/BSP/Components/sx1272/sx1272.c **** + 834:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.FifoThresh = SX1272Read( REG_FIFOTHRESH ) & 0x3F; + 835:./Drivers/BSP/Components/sx1272/sx1272.c **** + 836:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFI + 837:./Drivers/BSP/Components/sx1272/sx1272.c **** + 838:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = false; + 839:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + 840:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 841:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; + 842:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 843:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 844:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 845:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 846:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.IqInverted == true ) + 847:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 848:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ, ( ( SX1272Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_ + 849:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); + 850:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 851:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 852:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 853:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ, ( ( SX1272Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_ + 854:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); + 855:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 856:./Drivers/BSP/Components/sx1272/sx1272.c **** + 857:./Drivers/BSP/Components/sx1272/sx1272.c **** rxContinuous = SX1272.Settings.LoRa.RxContinuous; + 858:./Drivers/BSP/Components/sx1272/sx1272.c **** + 859:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) + 860:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 861:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | + 862:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_RXDONE | + 863:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_PAYLOADCRCERROR | + 864:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + 865:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_TXDONE | + 866:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDONE | + 867:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + 868:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDETECTED ); + 869:./Drivers/BSP/Components/sx1272/sx1272.c **** + 870:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=RxDone, DIO2=FhssChangeChannel + 871:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DI + 872:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 873:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 874:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 875:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | + 876:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_RXDONE | + 877:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_PAYLOADCRCERROR | + 878:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + 879:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_TXDONE | + 880:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDONE | + 881:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + 882:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDETECTED ); + 883:./Drivers/BSP/Components/sx1272/sx1272.c **** + 884:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=RxDone + 885:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DI + 886:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 887:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFORXBASEADDR, 0 ); + 888:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFOADDRPTR, 0 ); + ARM GAS /tmp/ccwcPdtV.s page 17 + + + 889:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 890:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 891:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 892:./Drivers/BSP/Components/sx1272/sx1272.c **** + 893:./Drivers/BSP/Components/sx1272/sx1272.c **** memset( RxTxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); + 894:./Drivers/BSP/Components/sx1272/sx1272.c **** + 895:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_RX_RUNNING; + 896:./Drivers/BSP/Components/sx1272/sx1272.c **** if( timeout != 0 ) + 897:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 898:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerSetValue( &RxTimeoutTimer, timeout ); + 899:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutTimer ); + 900:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 901:./Drivers/BSP/Components/sx1272/sx1272.c **** + 902:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Modem == MODEM_FSK ) + 903:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 904:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_RECEIVER ); + 905:./Drivers/BSP/Components/sx1272/sx1272.c **** + 906:./Drivers/BSP/Components/sx1272/sx1272.c **** if( rxContinuous == false ) + 907:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 908:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerSetValue( &RxTimeoutSyncWord, SX1272.Settings.Fsk.RxSingleTimeout ); + 909:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); + 910:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 911:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 912:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 913:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 914:./Drivers/BSP/Components/sx1272/sx1272.c **** if( rxContinuous == true ) + 915:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 916:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RFLR_OPMODE_RECEIVER ); + 917:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 918:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 919:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 920:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); + 921:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 922:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 923:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 924:./Drivers/BSP/Components/sx1272/sx1272.c **** + 925:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetTx( uint32_t timeout ) + 926:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 927:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerSetValue( &TxTimeoutTimer, timeout ); + 928:./Drivers/BSP/Components/sx1272/sx1272.c **** + 929:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 930:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 931:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 932:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 933:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=PacketSent + 934:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO1=FifoEmpty + 935:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO2=FifoFull + 936:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO3=FifoEmpty + 937:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO4=LowBat + 938:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO5=ModeReady + 939:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MAS + 940:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 941:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO2_MAS + 942:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_01 + 943:./Drivers/BSP/Components/sx1272/sx1272.c **** + 944:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING2, ( SX1272Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MAS + 945:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_MAP_MASK + ARM GAS /tmp/ccwcPdtV.s page 18 + + + 946:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.FifoThresh = SX1272Read( REG_FIFOTHRESH ) & 0x3F; + 947:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 948:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 949:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 950:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 951:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) + 952:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 953:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | + 954:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_RXDONE | + 955:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_PAYLOADCRCERROR | + 956:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + 957:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_TXDONE | + 958:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDONE | + 959:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + 960:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDETECTED ); + 961:./Drivers/BSP/Components/sx1272/sx1272.c **** + 962:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=TxDone, DIO2=FhssChangeChannel + 963:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DI + 964:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 965:./Drivers/BSP/Components/sx1272/sx1272.c **** else + 966:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 967:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | + 968:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_RXDONE | + 969:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_PAYLOADCRCERROR | + 970:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + 971:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_TXDONE | + 972:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDONE | + 973:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + 974:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_CADDETECTED ); + 975:./Drivers/BSP/Components/sx1272/sx1272.c **** + 976:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO0=TxDone + 977:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DI + 978:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 979:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 980:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 981:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 982:./Drivers/BSP/Components/sx1272/sx1272.c **** + 983:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_TX_RUNNING; + 984:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &TxTimeoutTimer ); + 985:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_TRANSMITTER ); + 986:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 987:./Drivers/BSP/Components/sx1272/sx1272.c **** + 988:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272StartCad( void ) + 989:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 990:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 991:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 992:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + 993:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 994:./Drivers/BSP/Components/sx1272/sx1272.c **** + 995:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 996:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 997:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 998:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 999:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | +1000:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_RXDONE | +1001:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_PAYLOADCRCERROR | +1002:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_VALIDHEADER | + ARM GAS /tmp/ccwcPdtV.s page 19 + + +1003:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_TXDONE | +1004:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_CADDONE | +1005:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | +1006:./Drivers/BSP/Components/sx1272/sx1272.c **** //RFLR_IRQFLAGS_CADDETECTED +1007:./Drivers/BSP/Components/sx1272/sx1272.c **** ); +1008:./Drivers/BSP/Components/sx1272/sx1272.c **** +1009:./Drivers/BSP/Components/sx1272/sx1272.c **** // DIO3=CADDone +1010:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, ( SX1272Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_M +1011:./Drivers/BSP/Components/sx1272/sx1272.c **** +1012:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_CAD; +1013:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RFLR_OPMODE_CAD ); +1014:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1015:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1016:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1017:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1018:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1019:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1020:./Drivers/BSP/Components/sx1272/sx1272.c **** +1021:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +1022:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1023:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t timeout = ( uint32_t )( time * 1000 ); +1024:./Drivers/BSP/Components/sx1272/sx1272.c **** +1025:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetChannel( freq ); +1026:./Drivers/BSP/Components/sx1272/sx1272.c **** +1027:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout ); +1028:./Drivers/BSP/Components/sx1272/sx1272.c **** +1029:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG2, ( SX1272Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_M +1030:./Drivers/BSP/Components/sx1272/sx1272.c **** // Disable radio interrupts +1031:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); +1032:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); +1033:./Drivers/BSP/Components/sx1272/sx1272.c **** +1034:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerSetValue( &TxTimeoutTimer, timeout ); +1035:./Drivers/BSP/Components/sx1272/sx1272.c **** +1036:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_TX_RUNNING; +1037:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &TxTimeoutTimer ); +1038:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_TRANSMITTER ); +1039:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1040:./Drivers/BSP/Components/sx1272/sx1272.c **** +1041:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t SX1272ReadRssi( RadioModems_t modem ) +1042:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1043:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t rssi = 0; +1044:./Drivers/BSP/Components/sx1272/sx1272.c **** +1045:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( modem ) +1046:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1047:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1048:./Drivers/BSP/Components/sx1272/sx1272.c **** rssi = -( SX1272Read( REG_RSSIVALUE ) >> 1 ); +1049:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1050:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1051:./Drivers/BSP/Components/sx1272/sx1272.c **** rssi = RSSI_OFFSET + SX1272Read( REG_LR_RSSIVALUE ); +1052:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1053:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1054:./Drivers/BSP/Components/sx1272/sx1272.c **** rssi = -1; +1055:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1056:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1057:./Drivers/BSP/Components/sx1272/sx1272.c **** return rssi; +1058:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1059:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 20 + + +1060:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272Reset( void ) +1061:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1062:./Drivers/BSP/Components/sx1272/sx1272.c **** GPIO_InitTypeDef initStruct = { 0 }; +1063:./Drivers/BSP/Components/sx1272/sx1272.c **** +1064:./Drivers/BSP/Components/sx1272/sx1272.c **** initStruct.Mode =GPIO_MODE_OUTPUT_PP; +1065:./Drivers/BSP/Components/sx1272/sx1272.c **** initStruct.Pull = GPIO_NOPULL; +1066:./Drivers/BSP/Components/sx1272/sx1272.c **** initStruct.Speed = GPIO_SPEED_HIGH; +1067:./Drivers/BSP/Components/sx1272/sx1272.c **** +1068:./Drivers/BSP/Components/sx1272/sx1272.c **** // Set RESET pin to 1 +1069:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Init( RADIO_RESET_PORT, RADIO_RESET_PIN, &initStruct ); +1070:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_RESET_PORT, RADIO_RESET_PIN, 1 ); +1071:./Drivers/BSP/Components/sx1272/sx1272.c **** +1072:./Drivers/BSP/Components/sx1272/sx1272.c **** // Wait 1 ms +1073:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 1 ); +1074:./Drivers/BSP/Components/sx1272/sx1272.c **** +1075:./Drivers/BSP/Components/sx1272/sx1272.c **** // Configure RESET as input +1076:./Drivers/BSP/Components/sx1272/sx1272.c **** initStruct.Mode = GPIO_NOPULL; +1077:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Init( RADIO_RESET_PORT, RADIO_RESET_PIN, &initStruct ); +1078:./Drivers/BSP/Components/sx1272/sx1272.c **** +1079:./Drivers/BSP/Components/sx1272/sx1272.c **** // Wait 6 ms +1080:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 6 ); +1081:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1082:./Drivers/BSP/Components/sx1272/sx1272.c **** +1083:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetOpMode( uint8_t opMode ) +1084:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1085:./Drivers/BSP/Components/sx1272/sx1272.c **** if( opMode == RF_OPMODE_SLEEP ) +1086:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1087:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetAntSwLowPower( true ); +1088:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1089:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1090:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1091:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetAntSwLowPower( false ); +1092:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetAntSw( opMode ); +1093:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1094:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_OPMODE, ( SX1272Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode ); +1095:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1096:./Drivers/BSP/Components/sx1272/sx1272.c **** +1097:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetModem( RadioModems_t modem ) +1098:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1099:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 ) +1100:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1101:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Modem = MODEM_LORA; +1102:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1103:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1104:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1105:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Modem = MODEM_FSK; +1106:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1107:./Drivers/BSP/Components/sx1272/sx1272.c **** +1108:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Modem == modem ) +1109:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1110:./Drivers/BSP/Components/sx1272/sx1272.c **** return; +1111:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1112:./Drivers/BSP/Components/sx1272/sx1272.c **** +1113:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Modem = modem; +1114:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1115:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1116:./Drivers/BSP/Components/sx1272/sx1272.c **** default: + ARM GAS /tmp/ccwcPdtV.s page 21 + + +1117:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1118:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetSleep( ); +1119:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_OPMODE, ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RF +1120:./Drivers/BSP/Components/sx1272/sx1272.c **** +1121:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, 0x00 ); +1122:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady +1123:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1124:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1125:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetSleep( ); +1126:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_OPMODE, ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RF +1127:./Drivers/BSP/Components/sx1272/sx1272.c **** +1128:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING1, 0x00 ); +1129:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_DIOMAPPING2, 0x00 ); +1130:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1131:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1132:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1133:./Drivers/BSP/Components/sx1272/sx1272.c **** +1134:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272Write( uint8_t addr, uint8_t data ) +1135:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteBuffer( addr, &data, 1 ); +1137:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1138:./Drivers/BSP/Components/sx1272/sx1272.c **** +1139:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t SX1272Read( uint8_t addr ) +1140:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1141:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t data; +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadBuffer( addr, &data, 1 ); +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; +1144:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1145:./Drivers/BSP/Components/sx1272/sx1272.c **** +1146:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +1147:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1148:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; +1149:./Drivers/BSP/Components/sx1272/sx1272.c **** +1150:./Drivers/BSP/Components/sx1272/sx1272.c **** //NSS = 0; +1151:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN, 0 ); +1152:./Drivers/BSP/Components/sx1272/sx1272.c **** +1153:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_SPI_InOut( addr | 0x80 ); +1154:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < size; i++ ) +1155:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1156:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_SPI_InOut( buffer[i] ); +1157:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1158:./Drivers/BSP/Components/sx1272/sx1272.c **** +1159:./Drivers/BSP/Components/sx1272/sx1272.c **** //NSS = 1; +1160:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN, 1 ); +1161:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1162:./Drivers/BSP/Components/sx1272/sx1272.c **** +1163:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ) +1164:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1165:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; +1166:./Drivers/BSP/Components/sx1272/sx1272.c **** +1167:./Drivers/BSP/Components/sx1272/sx1272.c **** //NSS = 0; +1168:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN, 0 ); +1169:./Drivers/BSP/Components/sx1272/sx1272.c **** +1170:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_SPI_InOut( addr & 0x7F ); +1171:./Drivers/BSP/Components/sx1272/sx1272.c **** +1172:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < size; i++ ) +1173:./Drivers/BSP/Components/sx1272/sx1272.c **** { + ARM GAS /tmp/ccwcPdtV.s page 22 + + +1174:./Drivers/BSP/Components/sx1272/sx1272.c **** buffer[i] = HW_SPI_InOut( 0 ); +1175:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1176:./Drivers/BSP/Components/sx1272/sx1272.c **** +1177:./Drivers/BSP/Components/sx1272/sx1272.c **** //NSS = 1; +1178:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_NSS_PORT, RADIO_NSS_PIN, 1 ); +1179:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1180:./Drivers/BSP/Components/sx1272/sx1272.c **** +1181:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272WriteFifo( uint8_t *buffer, uint8_t size ) +1182:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteBuffer( 0, buffer, size ); +1184:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1185:./Drivers/BSP/Components/sx1272/sx1272.c **** +1186:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272ReadFifo( uint8_t *buffer, uint8_t size ) +1187:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadBuffer( 0, buffer, size ); +1189:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1190:./Drivers/BSP/Components/sx1272/sx1272.c **** +1191:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +1192:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1193:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); +1194:./Drivers/BSP/Components/sx1272/sx1272.c **** +1195:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( modem ) +1196:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1197:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1198:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.FixLen == false ) +1199:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1200:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PAYLOADLENGTH, max ); +1201:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1202:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1203:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1204:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PAYLOADMAXLENGTH, max ); +1205:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1206:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1207:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1208:./Drivers/BSP/Components/sx1272/sx1272.c **** +1209:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272SetPublicNetwork( bool enable ) +1210:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1211:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( MODEM_LORA ); +1212:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PublicNetwork = enable; +1213:./Drivers/BSP/Components/sx1272/sx1272.c **** if( enable == true ) +1214:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1215:./Drivers/BSP/Components/sx1272/sx1272.c **** // Change LoRa modem SyncWord +1216:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD ); +1217:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1218:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1219:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1220:./Drivers/BSP/Components/sx1272/sx1272.c **** // Change LoRa modem SyncWord +1221:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD ); +1222:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1223:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1224:./Drivers/BSP/Components/sx1272/sx1272.c **** +1225:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t SX1272GetRadioWakeUpTime( void ) +1226:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1227:./Drivers/BSP/Components/sx1272/sx1272.c **** return ( uint32_t )LoRaBoardCallbacks->SX1272BoardGetWakeTime( ) + RADIO_WAKEUP_TIME;// BOARD_W +1228:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1229:./Drivers/BSP/Components/sx1272/sx1272.c **** +1230:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnTimeoutIrq( void ) + ARM GAS /tmp/ccwcPdtV.s page 23 + + +1231:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1232:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) +1233:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1234:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_RX_RUNNING: +1235:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Modem == MODEM_FSK ) +1236:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1237:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = false; +1238:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; +1239:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; +1240:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; +1241:./Drivers/BSP/Components/sx1272/sx1272.c **** +1242:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irqs +1243:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | +1244:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_IRQFLAGS1_PREAMBLEDETECT | +1245:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_IRQFLAGS1_SYNCADDRESSMATCH ); +1246:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); +1247:./Drivers/BSP/Components/sx1272/sx1272.c **** +1248:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.RxContinuous == true ) +1249:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1250:./Drivers/BSP/Components/sx1272/sx1272.c **** // Continuous mode restart Rx chain +1251:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_RXCONFIG, SX1272Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOU +1252:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); +1253:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1254:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1255:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1256:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1257:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); +1258:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1259:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1260:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) +1261:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1262:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxTimeout( ); +1263:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1264:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1265:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_TX_RUNNING: +1266:./Drivers/BSP/Components/sx1272/sx1272.c **** // Tx timeout shouldn't happen. +1267:./Drivers/BSP/Components/sx1272/sx1272.c **** // But it has been observed that when it happens it is a result of a corrupted SPI transfer +1268:./Drivers/BSP/Components/sx1272/sx1272.c **** // it depends on the platform design. +1269:./Drivers/BSP/Components/sx1272/sx1272.c **** // +1270:./Drivers/BSP/Components/sx1272/sx1272.c **** // The workaround is to put the radio in a known state. Thus, we re-initialize it. +1271:./Drivers/BSP/Components/sx1272/sx1272.c **** +1272:./Drivers/BSP/Components/sx1272/sx1272.c **** // BEGIN WORKAROUND +1273:./Drivers/BSP/Components/sx1272/sx1272.c **** +1274:./Drivers/BSP/Components/sx1272/sx1272.c **** // Reset the radio +1275:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Reset( ); +1276:./Drivers/BSP/Components/sx1272/sx1272.c **** +1277:./Drivers/BSP/Components/sx1272/sx1272.c **** // Initialize radio default values +1278:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_SLEEP ); +1279:./Drivers/BSP/Components/sx1272/sx1272.c **** +1280:./Drivers/BSP/Components/sx1272/sx1272.c **** for( uint8_t i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ ) +1281:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1282:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( RadioRegsInit[i].Modem ); +1283:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); +1284:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1285:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( MODEM_FSK ); +1286:./Drivers/BSP/Components/sx1272/sx1272.c **** +1287:./Drivers/BSP/Components/sx1272/sx1272.c **** // Restore previous network type setting. + ARM GAS /tmp/ccwcPdtV.s page 24 + + +1288:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetPublicNetwork( SX1272.Settings.LoRa.PublicNetwork ); +1289:./Drivers/BSP/Components/sx1272/sx1272.c **** // END WORKAROUND +1290:./Drivers/BSP/Components/sx1272/sx1272.c **** +1291:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1292:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) +1293:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1294:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->TxTimeout( ); +1295:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1296:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1297:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1298:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1299:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1300:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1301:./Drivers/BSP/Components/sx1272/sx1272.c **** +1302:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio0Irq( void ) +1303:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1304:./Drivers/BSP/Components/sx1272/sx1272.c **** volatile uint8_t irqFlags = 0; +1305:./Drivers/BSP/Components/sx1272/sx1272.c **** +1306:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) +1307:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1308:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_RX_RUNNING: +1309:./Drivers/BSP/Components/sx1272/sx1272.c **** //TimerStop( &RxTimeoutTimer ); +1310:./Drivers/BSP/Components/sx1272/sx1272.c **** // RxDone interrupt +1311:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1312:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1313:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1314:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.CrcOn == true ) +1315:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1316:./Drivers/BSP/Components/sx1272/sx1272.c **** irqFlags = SX1272Read( REG_IRQFLAGS2 ); +1317:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) +1318:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1319:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irqs +1320:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | +1321:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_IRQFLAGS1_PREAMBLEDETECT | +1322:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_IRQFLAGS1_SYNCADDRESSMATCH ); +1323:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); +1324:./Drivers/BSP/Components/sx1272/sx1272.c **** +1325:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); +1326:./Drivers/BSP/Components/sx1272/sx1272.c **** +1327:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.RxContinuous == false ) +1328:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1329:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); +1330:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1331:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1332:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1333:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1334:./Drivers/BSP/Components/sx1272/sx1272.c **** // Continuous mode restart Rx chain +1335:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_RXCONFIG, SX1272Read( REG_RXCONFIG ) | RF_RXCONFIG_RES +1336:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); +1337:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1338:./Drivers/BSP/Components/sx1272/sx1272.c **** +1339:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxError != NULL ) ) +1340:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1341:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxError( ); +1342:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1343:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = false; +1344:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + ARM GAS /tmp/ccwcPdtV.s page 25 + + +1345:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; +1346:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; +1347:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1348:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1349:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1350:./Drivers/BSP/Components/sx1272/sx1272.c **** +1351:./Drivers/BSP/Components/sx1272/sx1272.c **** // Read received packet size +1352:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272.Settings.FskPacketHandler.Size == 0 ) && ( SX1272.Settings.FskPacketHa +1353:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1354:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.FixLen == false ) +1355:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1356:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( ( uint8_t* )&SX1272.Settings.FskPacketHandler.Size, 1 ); +1357:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1358:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1359:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1360:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = SX1272Read( REG_PAYLOADLENGTH ); +1361:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1362:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes, SX1272.S +1363:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. +1364:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1365:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1366:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1367:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes, SX1272.S +1368:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. +1369:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1370:./Drivers/BSP/Components/sx1272/sx1272.c **** +1371:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); +1372:./Drivers/BSP/Components/sx1272/sx1272.c **** +1373:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.RxContinuous == false ) +1374:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1375:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1376:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); +1377:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1378:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1379:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1380:./Drivers/BSP/Components/sx1272/sx1272.c **** // Continuous mode restart Rx chain +1381:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_RXCONFIG, SX1272Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWI +1382:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); +1383:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1384:./Drivers/BSP/Components/sx1272/sx1272.c **** +1385:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) +1386:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1387:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxDone( RxTxBuffer, SX1272.Settings.FskPacketHandler.Size, SX1272. +1388:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1389:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = false; +1390:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; +1391:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; +1392:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; +1393:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1394:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1395:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1396:./Drivers/BSP/Components/sx1272/sx1272.c **** int8_t snr = 0; +1397:./Drivers/BSP/Components/sx1272/sx1272.c **** +1398:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1399:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); +1400:./Drivers/BSP/Components/sx1272/sx1272.c **** +1401:./Drivers/BSP/Components/sx1272/sx1272.c **** irqFlags = SX1272Read( REG_LR_IRQFLAGS ); + ARM GAS /tmp/ccwcPdtV.s page 26 + + +1402:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADC +1403:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1404:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1405:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); +1406:./Drivers/BSP/Components/sx1272/sx1272.c **** +1407:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.RxContinuous == false ) +1408:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1409:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1410:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1411:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); +1412:./Drivers/BSP/Components/sx1272/sx1272.c **** +1413:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxError != NULL ) ) +1414:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1415:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxError( ); +1416:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1417:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1418:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1419:./Drivers/BSP/Components/sx1272/sx1272.c **** +1420:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRaPacketHandler.SnrValue = SX1272Read( REG_LR_PKTSNRVALUE ); +1421:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is +1422:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1423:./Drivers/BSP/Components/sx1272/sx1272.c **** // Invert and divide by 4 +1424:./Drivers/BSP/Components/sx1272/sx1272.c **** snr = ( ( ~SX1272.Settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2; +1425:./Drivers/BSP/Components/sx1272/sx1272.c **** snr = -snr; +1426:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1427:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1428:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1429:./Drivers/BSP/Components/sx1272/sx1272.c **** // Divide by 4 +1430:./Drivers/BSP/Components/sx1272/sx1272.c **** snr = ( SX1272.Settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2; +1431:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1432:./Drivers/BSP/Components/sx1272/sx1272.c **** +1433:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t rssi = SX1272Read( REG_LR_PKTRSSIVALUE ); +1434:./Drivers/BSP/Components/sx1272/sx1272.c **** if( snr < 0 ) +1435:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1436:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi > +1437:./Drivers/BSP/Components/sx1272/sx1272.c **** snr; +1438:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1439:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1440:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1441:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi > +1442:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1443:./Drivers/BSP/Components/sx1272/sx1272.c **** +1444:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRaPacketHandler.Size = SX1272Read( REG_LR_RXNBBYTES ); +1445:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFOADDRPTR, SX1272Read( REG_LR_FIFORXCURRENTADDR ) ); +1446:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( RxTxBuffer, SX1272.Settings.LoRaPacketHandler.Size ); +1447:./Drivers/BSP/Components/sx1272/sx1272.c **** +1448:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.RxContinuous == false ) +1449:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1450:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1451:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1452:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); +1453:./Drivers/BSP/Components/sx1272/sx1272.c **** +1454:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) +1455:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1456:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxDone( RxTxBuffer, SX1272.Settings.LoRaPacketHandler.Size, SX +1457:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "rxDone\n\r" ); +1458:./Drivers/BSP/Components/sx1272/sx1272.c **** } + ARM GAS /tmp/ccwcPdtV.s page 27 + + +1459:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1460:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1461:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1462:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1463:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1464:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1465:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_TX_RUNNING: +1466:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &TxTimeoutTimer ); +1467:./Drivers/BSP/Components/sx1272/sx1272.c **** // TxDone interrupt +1468:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1469:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1470:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1471:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1472:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); +1473:./Drivers/BSP/Components/sx1272/sx1272.c **** // Intentional fall through +1474:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1475:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1476:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1477:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) +1478:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1479:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->TxDone( ); +1480:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "txDone\n\r" ); +1481:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1482:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1483:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1484:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1485:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1486:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1487:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1488:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1489:./Drivers/BSP/Components/sx1272/sx1272.c **** +1490:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio1Irq( void ) +1491:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1492:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) +1493:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1494:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_RX_RUNNING: +1495:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1496:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1497:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1498:./Drivers/BSP/Components/sx1272/sx1272.c **** // FifoLevel interrupt +1499:./Drivers/BSP/Components/sx1272/sx1272.c **** // Read received packet size +1500:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272.Settings.FskPacketHandler.Size == 0 ) && ( SX1272.Settings.FskPacketHa +1501:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1502:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.Fsk.FixLen == false ) +1503:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1504:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( ( uint8_t* )&SX1272.Settings.FskPacketHandler.Size, 1 ); +1505:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1506:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1507:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1508:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = SX1272Read( REG_PAYLOADLENGTH ); +1509:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1510:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1511:./Drivers/BSP/Components/sx1272/sx1272.c **** +1512:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272.Settings.FskPacketHandler.Size - SX1272.Settings.FskPacketHandler.NbBy +1513:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1514:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( ( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes ), SX12 +1515:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Fi + ARM GAS /tmp/ccwcPdtV.s page 28 + + +1516:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1517:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1518:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1519:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadFifo( ( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes ), SX12 +1520:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. +1521:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1522:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1523:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1524:./Drivers/BSP/Components/sx1272/sx1272.c **** // Sync time out +1525:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); +1526:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1527:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT ); +1528:./Drivers/BSP/Components/sx1272/sx1272.c **** +1529:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; +1530:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) +1531:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1532:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->RxTimeout( ); +1533:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "rxTimeOut\n\r" ); +1534:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1535:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1536:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1537:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1538:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1539:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1540:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_TX_RUNNING: +1541:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1542:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1543:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1544:./Drivers/BSP/Components/sx1272/sx1272.c **** // FifoEmpty interrupt +1545:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272.Settings.FskPacketHandler.Size - SX1272.Settings.FskPacketHandler.NbBy +1546:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1547:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteFifo( ( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes ), SX1 +1548:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Ch +1549:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1550:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1551:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1552:./Drivers/BSP/Components/sx1272/sx1272.c **** // Write the last chunk of data +1553:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteFifo( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes, SX1272. +1554:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Si +1555:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1556:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1557:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1558:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1559:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1560:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1561:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1562:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1563:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1564:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1565:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1566:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1567:./Drivers/BSP/Components/sx1272/sx1272.c **** +1568:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio2Irq( void ) +1569:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1570:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t afcChannel = 0; +1571:./Drivers/BSP/Components/sx1272/sx1272.c **** +1572:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) + ARM GAS /tmp/ccwcPdtV.s page 29 + + +1573:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1574:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_RX_RUNNING: +1575:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1576:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1577:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1578:./Drivers/BSP/Components/sx1272/sx1272.c **** // Checks if DIO4 is connected. If it is not PreambleDtected is set to true. +1579:./Drivers/BSP/Components/sx1272/sx1272.c **** #ifndef RADIO_DIO_4 +1580:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = true; +1581:./Drivers/BSP/Components/sx1272/sx1272.c **** #endif +1582:./Drivers/BSP/Components/sx1272/sx1272.c **** +1583:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272.Settings.FskPacketHandler.PreambleDetected == true ) && ( SX1272.Setti +1584:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1585:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); +1586:./Drivers/BSP/Components/sx1272/sx1272.c **** +1587:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = true; +1588:./Drivers/BSP/Components/sx1272/sx1272.c **** +1589:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.RssiValue = -( SX1272Read( REG_RSSIVALUE ) >> +1590:./Drivers/BSP/Components/sx1272/sx1272.c **** +1591:./Drivers/BSP/Components/sx1272/sx1272.c **** afcChannel = ( ( ( uint16_t )SX1272Read( REG_AFCMSB ) << 8 ) | +1592:./Drivers/BSP/Components/sx1272/sx1272.c **** ( uint16_t )SX1272Read( REG_AFCLSB ) ); +1593:./Drivers/BSP/Components/sx1272/sx1272.c **** +1594:./Drivers/BSP/Components/sx1272/sx1272.c **** SX_CHANNEL_TO_FREQ( afcChannel, SX1272.Settings.FskPacketHandler.AfcValue ); +1595:./Drivers/BSP/Components/sx1272/sx1272.c **** +1596:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.RxGain = ( SX1272Read( REG_LNA ) >> 5 ) & 0x07 +1597:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1598:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1599:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1600:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) +1601:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1602:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1603:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); +1604:./Drivers/BSP/Components/sx1272/sx1272.c **** +1605:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->FhssChangeChannel != NULL ) ) +1606:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1607:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->FhssChangeChannel( ( SX1272Read( REG_LR_HOPCHANNEL ) & RFLR_HO +1608:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1609:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1610:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1611:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1612:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1613:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1614:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1615:./Drivers/BSP/Components/sx1272/sx1272.c **** case RF_TX_RUNNING: +1616:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1617:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1618:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1619:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1620:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1621:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRa.FreqHopOn == true ) +1622:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1623:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1624:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); +1625:./Drivers/BSP/Components/sx1272/sx1272.c **** +1626:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->FhssChangeChannel != NULL ) ) +1627:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1628:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->FhssChangeChannel( ( SX1272Read( REG_LR_HOPCHANNEL ) & RFLR_HO +1629:./Drivers/BSP/Components/sx1272/sx1272.c **** } + ARM GAS /tmp/ccwcPdtV.s page 30 + + +1630:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1631:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1632:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1633:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1634:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1635:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1636:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1637:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1638:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1639:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1640:./Drivers/BSP/Components/sx1272/sx1272.c **** +1641:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio3Irq( void ) +1642:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1643:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1644:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1645:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1646:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1647:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1648:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETEC +1649:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1650:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1651:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); +1652:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) +1653:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1654:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->CadDone( true ); +1655:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1656:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1657:./Drivers/BSP/Components/sx1272/sx1272.c **** else +1658:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1659:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq +1660:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); +1661:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) +1662:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1663:./Drivers/BSP/Components/sx1272/sx1272.c **** RadioEvents->CadDone( false ); +1664:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1665:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1666:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1667:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1668:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1669:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1670:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1671:./Drivers/BSP/Components/sx1272/sx1272.c **** +1672:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio4Irq( void ) +1673:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 26 .loc 1 1673 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. +1674:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 31 .loc 1 1674 0 + 32 0000 064B ldr r3, .L4 + 33 0002 5B79 ldrb r3, [r3, #5] + 34 0004 002B cmp r3, #0 + 35 0006 07D1 bne .L1 +1675:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1676:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: + ARM GAS /tmp/ccwcPdtV.s page 31 + + +1677:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1678:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.FskPacketHandler.PreambleDetected == false ) + 36 .loc 1 1678 0 + 37 0008 044A ldr r2, .L4 + 38 000a 3033 adds r3, r3, #48 + 39 000c D35C ldrb r3, [r2, r3] + 40 000e 002B cmp r3, #0 + 41 0010 02D1 bne .L1 +1679:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1680:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.PreambleDetected = true; + 42 .loc 1 1680 0 + 43 0012 3033 adds r3, r3, #48 + 44 0014 0121 movs r1, #1 + 45 0016 D154 strb r1, [r2, r3] + 46 .L1: +1681:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1682:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1683:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1684:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1685:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1686:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1687:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1688:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1689:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 47 .loc 1 1689 0 + 48 @ sp needed + 49 0018 7047 bx lr + 50 .L5: + 51 001a C046 .align 2 + 52 .L4: + 53 001c 00000000 .word .LANCHOR0 + 54 .cfi_endproc + 55 .LFE131: + 57 .section .text.SX1272BoardInit,"ax",%progbits + 58 .align 1 + 59 .global SX1272BoardInit + 60 .syntax unified + 61 .code 16 + 62 .thumb_func + 63 .fpu softvfp + 65 SX1272BoardInit: + 66 .LFB96: + 247:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks =callbacks; + 67 .loc 1 247 0 + 68 .cfi_startproc + 69 @ args = 0, pretend = 0, frame = 0 + 70 @ frame_needed = 0, uses_anonymous_args = 0 + 71 @ link register save eliminated. + 72 .LVL0: + 248:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 73 .loc 1 248 0 + 74 0000 014B ldr r3, .L7 + 75 0002 1860 str r0, [r3] + 249:./Drivers/BSP/Components/sx1272/sx1272.c **** + 76 .loc 1 249 0 + 77 @ sp needed + 78 0004 7047 bx lr + ARM GAS /tmp/ccwcPdtV.s page 32 + + + 79 .L8: + 80 0006 C046 .align 2 + 81 .L7: + 82 0008 00000000 .word .LANCHOR1 + 83 .cfi_endproc + 84 .LFE96: + 86 .section .text.SX1272GetStatus,"ax",%progbits + 87 .align 1 + 88 .global SX1272GetStatus + 89 .syntax unified + 90 .code 16 + 91 .thumb_func + 92 .fpu softvfp + 94 SX1272GetStatus: + 95 .LFB98: + 284:./Drivers/BSP/Components/sx1272/sx1272.c **** return SX1272.Settings.State; + 96 .loc 1 284 0 + 97 .cfi_startproc + 98 @ args = 0, pretend = 0, frame = 0 + 99 @ frame_needed = 0, uses_anonymous_args = 0 + 100 @ link register save eliminated. + 285:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 101 .loc 1 285 0 + 102 0000 014B ldr r3, .L10 + 103 0002 1879 ldrb r0, [r3, #4] + 286:./Drivers/BSP/Components/sx1272/sx1272.c **** + 104 .loc 1 286 0 + 105 @ sp needed + 106 0004 7047 bx lr + 107 .L11: + 108 0006 C046 .align 2 + 109 .L10: + 110 0008 00000000 .word .LANCHOR0 + 111 .cfi_endproc + 112 .LFE98: + 114 .section .text.SX1272Reset,"ax",%progbits + 115 .align 1 + 116 .global SX1272Reset + 117 .syntax unified + 118 .code 16 + 119 .thumb_func + 120 .fpu softvfp + 122 SX1272Reset: + 123 .LFB114: +1061:./Drivers/BSP/Components/sx1272/sx1272.c **** GPIO_InitTypeDef initStruct = { 0 }; + 124 .loc 1 1061 0 + 125 .cfi_startproc + 126 @ args = 0, pretend = 0, frame = 24 + 127 @ frame_needed = 0, uses_anonymous_args = 0 + 128 0000 10B5 push {r4, lr} + 129 .LCFI0: + 130 .cfi_def_cfa_offset 8 + 131 .cfi_offset 4, -8 + 132 .cfi_offset 14, -4 + 133 0002 86B0 sub sp, sp, #24 + 134 .LCFI1: + 135 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccwcPdtV.s page 33 + + +1062:./Drivers/BSP/Components/sx1272/sx1272.c **** + 136 .loc 1 1062 0 + 137 0004 1422 movs r2, #20 + 138 0006 0021 movs r1, #0 + 139 0008 01A8 add r0, sp, #4 + 140 000a FFF7FEFF bl memset + 141 .LVL1: +1064:./Drivers/BSP/Components/sx1272/sx1272.c **** initStruct.Pull = GPIO_NOPULL; + 142 .loc 1 1064 0 + 143 000e 0123 movs r3, #1 + 144 0010 0293 str r3, [sp, #8] +1066:./Drivers/BSP/Components/sx1272/sx1272.c **** + 145 .loc 1 1066 0 + 146 0012 0233 adds r3, r3, #2 + 147 0014 0493 str r3, [sp, #16] +1069:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Write( RADIO_RESET_PORT, RADIO_RESET_PIN, 1 ); + 148 .loc 1 1069 0 + 149 0016 A024 movs r4, #160 + 150 0018 E405 lsls r4, r4, #23 + 151 001a 01AA add r2, sp, #4 + 152 001c 0121 movs r1, #1 + 153 001e 2000 movs r0, r4 + 154 0020 FFF7FEFF bl HW_GPIO_Init + 155 .LVL2: +1070:./Drivers/BSP/Components/sx1272/sx1272.c **** + 156 .loc 1 1070 0 + 157 0024 0122 movs r2, #1 + 158 0026 0121 movs r1, #1 + 159 0028 2000 movs r0, r4 + 160 002a FFF7FEFF bl HW_GPIO_Write + 161 .LVL3: +1073:./Drivers/BSP/Components/sx1272/sx1272.c **** + 162 .loc 1 1073 0 + 163 002e 0120 movs r0, #1 + 164 0030 FFF7FEFF bl DelayMs + 165 .LVL4: +1076:./Drivers/BSP/Components/sx1272/sx1272.c **** HW_GPIO_Init( RADIO_RESET_PORT, RADIO_RESET_PIN, &initStruct ); + 166 .loc 1 1076 0 + 167 0034 0023 movs r3, #0 + 168 0036 0293 str r3, [sp, #8] +1077:./Drivers/BSP/Components/sx1272/sx1272.c **** + 169 .loc 1 1077 0 + 170 0038 01AA add r2, sp, #4 + 171 003a 0121 movs r1, #1 + 172 003c 2000 movs r0, r4 + 173 003e FFF7FEFF bl HW_GPIO_Init + 174 .LVL5: +1080:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 175 .loc 1 1080 0 + 176 0042 0620 movs r0, #6 + 177 0044 FFF7FEFF bl DelayMs + 178 .LVL6: +1081:./Drivers/BSP/Components/sx1272/sx1272.c **** + 179 .loc 1 1081 0 + 180 0048 06B0 add sp, sp, #24 + 181 @ sp needed + 182 004a 10BD pop {r4, pc} + ARM GAS /tmp/ccwcPdtV.s page 34 + + + 183 .cfi_endproc + 184 .LFE114: + 186 .section .text.SX1272WriteBuffer,"ax",%progbits + 187 .align 1 + 188 .global SX1272WriteBuffer + 189 .syntax unified + 190 .code 16 + 191 .thumb_func + 192 .fpu softvfp + 194 SX1272WriteBuffer: + 195 .LFB119: +1147:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 196 .loc 1 1147 0 + 197 .cfi_startproc + 198 @ args = 0, pretend = 0, frame = 0 + 199 @ frame_needed = 0, uses_anonymous_args = 0 + 200 .LVL7: + 201 0000 70B5 push {r4, r5, r6, lr} + 202 .LCFI2: + 203 .cfi_def_cfa_offset 16 + 204 .cfi_offset 4, -16 + 205 .cfi_offset 5, -12 + 206 .cfi_offset 6, -8 + 207 .cfi_offset 14, -4 + 208 0002 0400 movs r4, r0 + 209 0004 0E00 movs r6, r1 + 210 0006 1500 movs r5, r2 +1151:./Drivers/BSP/Components/sx1272/sx1272.c **** + 211 .loc 1 1151 0 + 212 0008 0022 movs r2, #0 + 213 .LVL8: + 214 000a 4021 movs r1, #64 + 215 .LVL9: + 216 000c 0B48 ldr r0, .L16 + 217 .LVL10: + 218 000e FFF7FEFF bl HW_GPIO_Write + 219 .LVL11: +1153:./Drivers/BSP/Components/sx1272/sx1272.c **** for( i = 0; i < size; i++ ) + 220 .loc 1 1153 0 + 221 0012 8020 movs r0, #128 + 222 0014 4042 rsbs r0, r0, #0 + 223 0016 2043 orrs r0, r4 + 224 0018 C0B2 uxtb r0, r0 + 225 001a FFF7FEFF bl HW_SPI_InOut + 226 .LVL12: +1154:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 227 .loc 1 1154 0 + 228 001e 0024 movs r4, #0 + 229 0020 04E0 b .L14 + 230 .LVL13: + 231 .L15: +1156:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 232 .loc 1 1156 0 discriminator 3 + 233 0022 305D ldrb r0, [r6, r4] + 234 0024 FFF7FEFF bl HW_SPI_InOut + 235 .LVL14: +1154:./Drivers/BSP/Components/sx1272/sx1272.c **** { + ARM GAS /tmp/ccwcPdtV.s page 35 + + + 236 .loc 1 1154 0 discriminator 3 + 237 0028 0134 adds r4, r4, #1 + 238 .LVL15: + 239 002a E4B2 uxtb r4, r4 + 240 .LVL16: + 241 .L14: +1154:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 242 .loc 1 1154 0 is_stmt 0 discriminator 1 + 243 002c AC42 cmp r4, r5 + 244 002e F8D3 bcc .L15 +1160:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 245 .loc 1 1160 0 is_stmt 1 + 246 0030 0122 movs r2, #1 + 247 0032 4021 movs r1, #64 + 248 0034 0148 ldr r0, .L16 + 249 0036 FFF7FEFF bl HW_GPIO_Write + 250 .LVL17: +1161:./Drivers/BSP/Components/sx1272/sx1272.c **** + 251 .loc 1 1161 0 + 252 @ sp needed + 253 .LVL18: + 254 .LVL19: + 255 003a 70BD pop {r4, r5, r6, pc} + 256 .L17: + 257 .align 2 + 258 .L16: + 259 003c 00040050 .word 1342178304 + 260 .cfi_endproc + 261 .LFE119: + 263 .section .text.SX1272Write,"ax",%progbits + 264 .align 1 + 265 .global SX1272Write + 266 .syntax unified + 267 .code 16 + 268 .thumb_func + 269 .fpu softvfp + 271 SX1272Write: + 272 .LFB117: +1135:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteBuffer( addr, &data, 1 ); + 273 .loc 1 1135 0 + 274 .cfi_startproc + 275 @ args = 0, pretend = 0, frame = 8 + 276 @ frame_needed = 0, uses_anonymous_args = 0 + 277 .LVL20: + 278 0000 00B5 push {lr} + 279 .LCFI3: + 280 .cfi_def_cfa_offset 4 + 281 .cfi_offset 14, -4 + 282 0002 83B0 sub sp, sp, #12 + 283 .LCFI4: + 284 .cfi_def_cfa_offset 16 + 285 0004 6B46 mov r3, sp + 286 0006 D971 strb r1, [r3, #7] + 287 0008 0733 adds r3, r3, #7 +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 288 .loc 1 1136 0 + 289 000a 0122 movs r2, #1 + ARM GAS /tmp/ccwcPdtV.s page 36 + + + 290 000c 1900 movs r1, r3 + 291 .LVL21: + 292 000e FFF7FEFF bl SX1272WriteBuffer + 293 .LVL22: +1137:./Drivers/BSP/Components/sx1272/sx1272.c **** + 294 .loc 1 1137 0 + 295 0012 03B0 add sp, sp, #12 + 296 @ sp needed + 297 0014 00BD pop {pc} + 298 .cfi_endproc + 299 .LFE117: + 301 .global __aeabi_uidiv + 302 .global __aeabi_uidivmod + 303 .section .text.SX1272SetChannel,"ax",%progbits + 304 .align 1 + 305 .global SX1272SetChannel + 306 .syntax unified + 307 .code 16 + 308 .thumb_func + 309 .fpu softvfp + 311 SX1272SetChannel: + 312 .LFB99: + 289:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t channel; + 313 .loc 1 289 0 + 314 .cfi_startproc + 315 @ args = 0, pretend = 0, frame = 8 + 316 @ frame_needed = 0, uses_anonymous_args = 0 + 317 .LVL23: + 318 0000 30B5 push {r4, r5, lr} + 319 .LCFI5: + 320 .cfi_def_cfa_offset 12 + 321 .cfi_offset 4, -12 + 322 .cfi_offset 5, -8 + 323 .cfi_offset 14, -4 + 324 0002 83B0 sub sp, sp, #12 + 325 .LCFI6: + 326 .cfi_def_cfa_offset 24 + 327 0004 0500 movs r5, r0 + 292:./Drivers/BSP/Components/sx1272/sx1272.c **** + 328 .loc 1 292 0 + 329 0006 154B ldr r3, .L20 + 330 0008 9860 str r0, [r3, #8] + 331 .LBB361: + 294:./Drivers/BSP/Components/sx1272/sx1272.c **** + 332 .loc 1 294 0 + 333 000a 1549 ldr r1, .L20+4 + 334 000c FFF7FEFF bl __aeabi_uidiv + 335 .LVL24: + 336 0010 0402 lsls r4, r0, #8 + 337 0012 1349 ldr r1, .L20+4 + 338 0014 2800 movs r0, r5 + 339 .LVL25: + 340 0016 FFF7FEFF bl __aeabi_uidivmod + 341 .LVL26: + 342 001a 0802 lsls r0, r1, #8 + 343 001c 114B ldr r3, .L20+8 + 344 001e 9C46 mov ip, r3 + ARM GAS /tmp/ccwcPdtV.s page 37 + + + 345 0020 6044 add r0, r0, ip + 346 0022 0F49 ldr r1, .L20+4 + 347 0024 FFF7FEFF bl __aeabi_uidiv + 348 .LVL27: + 349 0028 2418 adds r4, r4, r0 + 350 .LVL28: + 351 .LBE361: + 296:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FRFMID, ( uint8_t )( ( channel >> 8 ) & 0xFF ) ); + 352 .loc 1 296 0 + 353 002a 230C lsrs r3, r4, #16 + 354 .LVL29: + 355 002c 6A46 mov r2, sp + 356 002e D11D adds r1, r2, #7 + 357 0030 0B70 strb r3, [r1] + 358 .LVL30: + 359 .LBB362: + 360 .LBB363: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 361 .loc 1 1136 0 + 362 0032 0122 movs r2, #1 + 363 0034 0620 movs r0, #6 + 364 0036 FFF7FEFF bl SX1272WriteBuffer + 365 .LVL31: + 366 .LBE363: + 367 .LBE362: + 297:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FRFLSB, ( uint8_t )( channel & 0xFF ) ); + 368 .loc 1 297 0 + 369 003a 230A lsrs r3, r4, #8 + 370 .LVL32: + 371 003c 6A46 mov r2, sp + 372 003e 911D adds r1, r2, #6 + 373 0040 0B70 strb r3, [r1] + 374 .LVL33: + 375 .LBB364: + 376 .LBB365: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 377 .loc 1 1136 0 + 378 0042 0122 movs r2, #1 + 379 0044 0720 movs r0, #7 + 380 0046 FFF7FEFF bl SX1272WriteBuffer + 381 .LVL34: + 382 004a 6B46 mov r3, sp + 383 004c 591D adds r1, r3, #5 + 384 004e 0C70 strb r4, [r1] + 385 .LVL35: + 386 .LBE365: + 387 .LBE364: + 388 .LBB366: + 389 .LBB367: + 390 0050 0122 movs r2, #1 + 391 0052 0820 movs r0, #8 + 392 0054 FFF7FEFF bl SX1272WriteBuffer + 393 .LVL36: + 394 .LBE367: + 395 .LBE366: + 299:./Drivers/BSP/Components/sx1272/sx1272.c **** + 396 .loc 1 299 0 + ARM GAS /tmp/ccwcPdtV.s page 38 + + + 397 0058 03B0 add sp, sp, #12 + 398 @ sp needed + 399 .LVL37: + 400 .LVL38: + 401 005a 30BD pop {r4, r5, pc} + 402 .L21: + 403 .align 2 + 404 .L20: + 405 005c 00000000 .word .LANCHOR0 + 406 0060 093D0000 .word 15625 + 407 0064 841E0000 .word 7812 + 408 .cfi_endproc + 409 .LFE99: + 411 .section .text.SX1272ReadBuffer,"ax",%progbits + 412 .align 1 + 413 .global SX1272ReadBuffer + 414 .syntax unified + 415 .code 16 + 416 .thumb_func + 417 .fpu softvfp + 419 SX1272ReadBuffer: + 420 .LFB120: +1164:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 421 .loc 1 1164 0 + 422 .cfi_startproc + 423 @ args = 0, pretend = 0, frame = 0 + 424 @ frame_needed = 0, uses_anonymous_args = 0 + 425 .LVL39: + 426 0000 70B5 push {r4, r5, r6, lr} + 427 .LCFI7: + 428 .cfi_def_cfa_offset 16 + 429 .cfi_offset 4, -16 + 430 .cfi_offset 5, -12 + 431 .cfi_offset 6, -8 + 432 .cfi_offset 14, -4 + 433 0002 0400 movs r4, r0 + 434 0004 0E00 movs r6, r1 + 435 0006 1500 movs r5, r2 +1168:./Drivers/BSP/Components/sx1272/sx1272.c **** + 436 .loc 1 1168 0 + 437 0008 0022 movs r2, #0 + 438 .LVL40: + 439 000a 4021 movs r1, #64 + 440 .LVL41: + 441 000c 0B48 ldr r0, .L25 + 442 .LVL42: + 443 000e FFF7FEFF bl HW_GPIO_Write + 444 .LVL43: +1170:./Drivers/BSP/Components/sx1272/sx1272.c **** + 445 .loc 1 1170 0 + 446 0012 7F20 movs r0, #127 + 447 0014 2040 ands r0, r4 + 448 0016 FFF7FEFF bl HW_SPI_InOut + 449 .LVL44: +1172:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 450 .loc 1 1172 0 + 451 001a 0024 movs r4, #0 + ARM GAS /tmp/ccwcPdtV.s page 39 + + + 452 001c 05E0 b .L23 + 453 .LVL45: + 454 .L24: +1174:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 455 .loc 1 1174 0 discriminator 3 + 456 001e 0020 movs r0, #0 + 457 0020 FFF7FEFF bl HW_SPI_InOut + 458 .LVL46: + 459 0024 3055 strb r0, [r6, r4] +1172:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 460 .loc 1 1172 0 discriminator 3 + 461 0026 0134 adds r4, r4, #1 + 462 .LVL47: + 463 0028 E4B2 uxtb r4, r4 + 464 .LVL48: + 465 .L23: +1172:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 466 .loc 1 1172 0 is_stmt 0 discriminator 1 + 467 002a AC42 cmp r4, r5 + 468 002c F7D3 bcc .L24 +1178:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 469 .loc 1 1178 0 is_stmt 1 + 470 002e 0122 movs r2, #1 + 471 0030 4021 movs r1, #64 + 472 0032 0248 ldr r0, .L25 + 473 0034 FFF7FEFF bl HW_GPIO_Write + 474 .LVL49: +1179:./Drivers/BSP/Components/sx1272/sx1272.c **** + 475 .loc 1 1179 0 + 476 @ sp needed + 477 .LVL50: + 478 .LVL51: + 479 0038 70BD pop {r4, r5, r6, pc} + 480 .L26: + 481 003a C046 .align 2 + 482 .L25: + 483 003c 00040050 .word 1342178304 + 484 .cfi_endproc + 485 .LFE120: + 487 .section .text.SX1272Read,"ax",%progbits + 488 .align 1 + 489 .global SX1272Read + 490 .syntax unified + 491 .code 16 + 492 .thumb_func + 493 .fpu softvfp + 495 SX1272Read: + 496 .LFB118: +1140:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t data; + 497 .loc 1 1140 0 + 498 .cfi_startproc + 499 @ args = 0, pretend = 0, frame = 8 + 500 @ frame_needed = 0, uses_anonymous_args = 0 + 501 .LVL52: + 502 0000 10B5 push {r4, lr} + 503 .LCFI8: + 504 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccwcPdtV.s page 40 + + + 505 .cfi_offset 4, -8 + 506 .cfi_offset 14, -4 + 507 0002 82B0 sub sp, sp, #8 + 508 .LCFI9: + 509 .cfi_def_cfa_offset 16 +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 510 .loc 1 1142 0 + 511 0004 6B46 mov r3, sp + 512 0006 DC1D adds r4, r3, #7 + 513 0008 0122 movs r2, #1 + 514 000a 2100 movs r1, r4 + 515 000c FFF7FEFF bl SX1272ReadBuffer + 516 .LVL53: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 517 .loc 1 1143 0 + 518 0010 2078 ldrb r0, [r4] +1144:./Drivers/BSP/Components/sx1272/sx1272.c **** + 519 .loc 1 1144 0 + 520 0012 02B0 add sp, sp, #8 + 521 @ sp needed + 522 0014 10BD pop {r4, pc} + 523 .cfi_endproc + 524 .LFE118: + 526 .global __aeabi_i2d + 527 .global __aeabi_dadd + 528 .global __aeabi_dmul + 529 .global __aeabi_ui2d + 530 .global __aeabi_ddiv + 531 .global __aeabi_d2uiz + 532 .global __aeabi_dcmpgt + 533 .section .text.SX1272GetTimeOnAir,"ax",%progbits + 534 .align 1 + 535 .global SX1272GetTimeOnAir + 536 .syntax unified + 537 .code 16 + 538 .thumb_func + 539 .fpu softvfp + 541 SX1272GetTimeOnAir: + 542 .LFB105: + 658:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t airTime = 0; + 543 .loc 1 658 0 + 544 .cfi_startproc + 545 @ args = 0, pretend = 0, frame = 24 + 546 @ frame_needed = 0, uses_anonymous_args = 0 + 547 .LVL54: + 548 0000 F0B5 push {r4, r5, r6, r7, lr} + 549 .LCFI10: + 550 .cfi_def_cfa_offset 20 + 551 .cfi_offset 4, -20 + 552 .cfi_offset 5, -16 + 553 .cfi_offset 6, -12 + 554 .cfi_offset 7, -8 + 555 .cfi_offset 14, -4 + 556 0002 87B0 sub sp, sp, #28 + 557 .LCFI11: + 558 .cfi_def_cfa_offset 48 + 559 0004 0C00 movs r4, r1 + ARM GAS /tmp/ccwcPdtV.s page 41 + + + 560 .LVL55: + 661:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 561 .loc 1 661 0 + 562 0006 0028 cmp r0, #0 + 563 0008 03D0 beq .L30 + 564 000a 0128 cmp r0, #1 + 565 000c 62D0 beq .L31 + 659:./Drivers/BSP/Components/sx1272/sx1272.c **** + 566 .loc 1 659 0 + 567 000e 0020 movs r0, #0 + 568 .LVL56: + 711:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 569 .loc 1 711 0 + 570 0010 54E0 b .L28 + 571 .LVL57: + 572 .L30: + 665:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MAS + 573 .loc 1 665 0 + 574 0012 7F4E ldr r6, .L55 + 575 0014 358C ldrh r5, [r6, #32] + 576 .LVL58: + 577 .LBB368: + 578 .LBB369: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 579 .loc 1 1142 0 + 580 0016 04AB add r3, sp, #16 + 581 0018 DF1D adds r7, r3, #7 + 582 001a 0122 movs r2, #1 + 583 001c 3900 movs r1, r7 + 584 .LVL59: + 585 001e 2720 movs r0, #39 + 586 .LVL60: + 587 0020 FFF7FEFF bl SX1272ReadBuffer + 588 .LVL61: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 589 .loc 1 1143 0 + 590 0024 3878 ldrb r0, [r7] + 591 .LVL62: + 592 .LBE369: + 593 .LBE368: + 666:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + + 594 .loc 1 666 0 + 595 0026 F823 movs r3, #248 + 596 0028 9843 bics r0, r3 + 597 002a 0130 adds r0, r0, #1 + 665:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MAS + 598 .loc 1 665 0 + 599 002c 2818 adds r0, r5, r0 + 666:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + + 600 .loc 1 666 0 + 601 002e FFF7FEFF bl __aeabi_i2d + 602 .LVL63: + 667:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( ( SX1272Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDR + 603 .loc 1 667 0 + 604 0032 2223 movs r3, #34 + 605 0034 F35C ldrb r3, [r6, r3] + 606 0036 002B cmp r3, #0 + ARM GAS /tmp/ccwcPdtV.s page 42 + + + 607 0038 42D0 beq .L44 + 608 003a 0022 movs r2, #0 + 609 003c 0023 movs r3, #0 + 610 .L32: + 666:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + + 611 .loc 1 666 0 + 612 003e FFF7FEFF bl __aeabi_dadd + 613 .LVL64: + 614 0042 0600 movs r6, r0 + 615 0044 0F00 movs r7, r1 + 616 .LVL65: + 617 .LBB370: + 618 .LBB371: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 619 .loc 1 1142 0 + 620 0046 04AB add r3, sp, #16 + 621 0048 DD1D adds r5, r3, #7 + 622 004a 0122 movs r2, #1 + 623 004c 2900 movs r1, r5 + 624 004e 3020 movs r0, #48 + 625 0050 FFF7FEFF bl SX1272ReadBuffer + 626 .LVL66: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 627 .loc 1 1143 0 + 628 0054 2B78 ldrb r3, [r5] + 629 .LVL67: + 630 .LBE371: + 631 .LBE370: + 668:./Drivers/BSP/Components/sx1272/sx1272.c **** pktLen + + 632 .loc 1 668 0 + 633 0056 F922 movs r2, #249 + 634 0058 9343 bics r3, r2 + 635 005a 34D0 beq .L45 + 636 005c 0022 movs r2, #0 + 637 005e 6D4B ldr r3, .L55+4 + 638 .L33: + 667:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( ( SX1272Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDR + 639 .loc 1 667 0 + 640 0060 3000 movs r0, r6 + 641 0062 3900 movs r1, r7 + 642 0064 FFF7FEFF bl __aeabi_dadd + 643 .LVL68: + 644 0068 0600 movs r6, r0 + 645 006a 0F00 movs r7, r1 + 668:./Drivers/BSP/Components/sx1272/sx1272.c **** pktLen + + 646 .loc 1 668 0 + 647 006c 2000 movs r0, r4 + 648 006e FFF7FEFF bl __aeabi_i2d + 649 .LVL69: + 650 0072 3200 movs r2, r6 + 651 0074 3B00 movs r3, r7 + 652 0076 FFF7FEFF bl __aeabi_dadd + 653 .LVL70: + 670:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate ) * 1000 ); + 654 .loc 1 670 0 + 655 007a 654A ldr r2, .L55 + 656 007c 2423 movs r3, #36 + ARM GAS /tmp/ccwcPdtV.s page 43 + + + 657 007e D35C ldrb r3, [r2, r3] + 658 0080 002B cmp r3, #0 + 659 0082 23D1 bne .L54 + 660 0084 0022 movs r2, #0 + 661 0086 0023 movs r3, #0 + 662 .L34: + 669:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / + 663 .loc 1 669 0 + 664 0088 FFF7FEFF bl __aeabi_dadd + 665 .LVL71: + 665:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MAS + 666 .loc 1 665 0 + 667 008c 0022 movs r2, #0 + 668 008e 624B ldr r3, .L55+8 + 669 0090 FFF7FEFF bl __aeabi_dmul + 670 .LVL72: + 671 0094 0400 movs r4, r0 + 672 0096 0D00 movs r5, r1 + 671:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 673 .loc 1 671 0 + 674 0098 5D4B ldr r3, .L55 + 675 009a D869 ldr r0, [r3, #28] + 670:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate ) * 1000 ); + 676 .loc 1 670 0 + 677 009c FFF7FEFF bl __aeabi_ui2d + 678 .LVL73: + 679 00a0 0200 movs r2, r0 + 680 00a2 0B00 movs r3, r1 + 681 00a4 2000 movs r0, r4 + 682 00a6 2900 movs r1, r5 + 683 00a8 FFF7FEFF bl __aeabi_ddiv + 684 .LVL74: + 665:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MAS + 685 .loc 1 665 0 + 686 00ac 0022 movs r2, #0 + 687 00ae 5B4B ldr r3, .L55+12 + 688 00b0 FFF7FEFF bl __aeabi_dmul + 689 .LVL75: + 690 00b4 FFF7FEFF bl round + 691 .LVL76: + 692 00b8 FFF7FEFF bl __aeabi_d2uiz + 693 .LVL77: + 694 .L28: + 712:./Drivers/BSP/Components/sx1272/sx1272.c **** + 695 .loc 1 712 0 + 696 00bc 07B0 add sp, sp, #28 + 697 @ sp needed + 698 00be F0BD pop {r4, r5, r6, r7, pc} + 699 .LVL78: + 700 .L44: + 667:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( ( SX1272Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDR + 701 .loc 1 667 0 + 702 00c0 0022 movs r2, #0 + 703 00c2 544B ldr r3, .L55+4 + 704 00c4 BBE7 b .L32 + 705 .L45: + 668:./Drivers/BSP/Components/sx1272/sx1272.c **** pktLen + + ARM GAS /tmp/ccwcPdtV.s page 44 + + + 706 .loc 1 668 0 + 707 00c6 0022 movs r2, #0 + 708 00c8 0023 movs r3, #0 + 709 00ca C9E7 b .L33 + 710 .L54: + 670:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate ) * 1000 ); + 711 .loc 1 670 0 + 712 00cc 0022 movs r2, #0 + 713 00ce 8023 movs r3, #128 + 714 00d0 DB05 lsls r3, r3, #23 + 715 00d2 D9E7 b .L34 + 716 .LVL79: + 717 .L31: + 718 .LBB372: + 677:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 719 .loc 1 677 0 + 720 00d4 4E4B ldr r3, .L55 + 721 00d6 5B6C ldr r3, [r3, #68] + 722 00d8 012B cmp r3, #1 + 723 00da 00D1 bne .LCB625 + 724 00dc 82E0 b .L36 @long jump + 725 .LCB625: + 726 00de 002B cmp r3, #0 + 727 00e0 00D1 bne .LCB627 + 728 00e2 89E0 b .L47 @long jump + 729 .LCB627: + 730 00e4 022B cmp r3, #2 + 731 00e6 00D1 bne .LCB629 + 732 00e8 81E0 b .L38 @long jump + 733 .LCB629: + 676:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.LoRa.Bandwidth ) + 734 .loc 1 676 0 + 735 00ea 0022 movs r2, #0 + 736 00ec 0023 movs r3, #0 + 737 00ee 0092 str r2, [sp] + 738 00f0 0193 str r3, [sp, #4] + 739 .LVL80: + 740 .L37: + 691:./Drivers/BSP/Components/sx1272/sx1272.c **** double ts = 1 / rs; + 741 .loc 1 691 0 + 742 00f2 474D ldr r5, .L55 + 743 00f4 AE6C ldr r6, [r5, #72] + 744 00f6 0120 movs r0, #1 + 745 .LVL81: + 746 00f8 B040 lsls r0, r0, r6 + 747 00fa FFF7FEFF bl __aeabi_i2d + 748 .LVL82: + 749 00fe 0200 movs r2, r0 + 750 0100 0B00 movs r3, r1 + 751 0102 0098 ldr r0, [sp] + 752 0104 0199 ldr r1, [sp, #4] + 753 0106 FFF7FEFF bl __aeabi_ddiv + 754 .LVL83: + 755 010a 0200 movs r2, r0 + 756 010c 0B00 movs r3, r1 + 757 .LVL84: + 692:./Drivers/BSP/Components/sx1272/sx1272.c **** // time of preamble + ARM GAS /tmp/ccwcPdtV.s page 45 + + + 758 .loc 1 692 0 + 759 010e 0020 movs r0, #0 + 760 0110 4049 ldr r1, .L55+4 + 761 0112 FFF7FEFF bl __aeabi_ddiv + 762 .LVL85: + 763 0116 0090 str r0, [sp] + 764 0118 0191 str r1, [sp, #4] + 765 .LVL86: + 694:./Drivers/BSP/Components/sx1272/sx1272.c **** // Symbol length of payload and time + 766 .loc 1 694 0 + 767 011a 4E23 movs r3, #78 + 768 011c E85A ldrh r0, [r5, r3] + 769 .LVL87: + 770 011e FFF7FEFF bl __aeabi_i2d + 771 .LVL88: + 772 0122 0022 movs r2, #0 + 773 0124 3E4B ldr r3, .L55+16 + 774 0126 FFF7FEFF bl __aeabi_dadd + 775 .LVL89: + 776 012a 009A ldr r2, [sp] + 777 012c 019B ldr r3, [sp, #4] + 778 012e FFF7FEFF bl __aeabi_dmul + 779 .LVL90: + 780 0132 0290 str r0, [sp, #8] + 781 0134 0391 str r1, [sp, #12] + 782 .LVL91: + 696:./Drivers/BSP/Components/sx1272/sx1272.c **** 28 + 16 * SX1272.Settings.LoRa.CrcOn - + 783 .loc 1 696 0 + 784 0136 E400 lsls r4, r4, #3 + 785 0138 B000 lsls r0, r6, #2 + 786 .LVL92: + 787 013a 241A subs r4, r4, r0 + 697:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.FixLen ? 20 : 0 ) ) / + 788 .loc 1 697 0 + 789 013c 5223 movs r3, #82 + 790 013e E85C ldrb r0, [r5, r3] + 791 0140 0001 lsls r0, r0, #4 + 792 0142 0019 adds r0, r0, r4 + 698:./Drivers/BSP/Components/sx1272/sx1272.c **** ( double )( 4 * ( SX1272.Settings.LoRa.Datarate - + 793 .loc 1 698 0 + 794 0144 023B subs r3, r3, #2 + 795 0146 EB5C ldrb r3, [r5, r3] + 796 0148 002B cmp r3, #0 + 797 014a 5AD0 beq .L48 + 798 014c 1424 movs r4, #20 + 799 .L39: + 697:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.FixLen ? 20 : 0 ) ) / + 800 .loc 1 697 0 + 801 014e 001B subs r0, r0, r4 + 802 0150 1C30 adds r0, r0, #28 + 696:./Drivers/BSP/Components/sx1272/sx1272.c **** 28 + 16 * SX1272.Settings.LoRa.CrcOn - + 803 .loc 1 696 0 + 804 0152 FFF7FEFF bl __aeabi_ui2d + 805 .LVL93: + 806 0156 0400 movs r4, r0 + 807 0158 0D00 movs r5, r1 + 700:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.Coderate + 4 ); + ARM GAS /tmp/ccwcPdtV.s page 46 + + + 808 .loc 1 700 0 + 809 015a 2D4A ldr r2, .L55 + 810 015c 4C23 movs r3, #76 + 811 015e D35C ldrb r3, [r2, r3] + 812 0160 002B cmp r3, #0 + 813 0162 50D0 beq .L49 + 814 0164 0220 movs r0, #2 + 815 .L40: + 699:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( SX1272.Settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) + 816 .loc 1 699 0 + 817 0166 301A subs r0, r6, r0 + 818 0168 8000 lsls r0, r0, #2 + 819 016a FFF7FEFF bl __aeabi_ui2d + 820 .LVL94: + 821 016e 0200 movs r2, r0 + 822 0170 0B00 movs r3, r1 + 696:./Drivers/BSP/Components/sx1272/sx1272.c **** 28 + 16 * SX1272.Settings.LoRa.CrcOn - + 823 .loc 1 696 0 + 824 0172 2000 movs r0, r4 + 825 0174 2900 movs r1, r5 + 826 0176 FFF7FEFF bl __aeabi_ddiv + 827 .LVL95: + 828 017a FFF7FEFF bl ceil + 829 .LVL96: + 830 017e 0400 movs r4, r0 + 831 0180 0D00 movs r5, r1 + 701:./Drivers/BSP/Components/sx1272/sx1272.c **** double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); + 832 .loc 1 701 0 + 833 0182 234A ldr r2, .L55 + 834 0184 4D23 movs r3, #77 + 835 0186 D05C ldrb r0, [r2, r3] + 836 0188 0430 adds r0, r0, #4 + 700:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.Coderate + 4 ); + 837 .loc 1 700 0 + 838 018a FFF7FEFF bl __aeabi_i2d + 839 .LVL97: + 840 018e 0200 movs r2, r0 + 841 0190 0B00 movs r3, r1 + 696:./Drivers/BSP/Components/sx1272/sx1272.c **** 28 + 16 * SX1272.Settings.LoRa.CrcOn - + 842 .loc 1 696 0 + 843 0192 2000 movs r0, r4 + 844 0194 2900 movs r1, r5 + 845 0196 FFF7FEFF bl __aeabi_dmul + 846 .LVL98: + 847 019a 0400 movs r4, r0 + 848 019c 0D00 movs r5, r1 + 849 .LVL99: + 702:./Drivers/BSP/Components/sx1272/sx1272.c **** double tPayload = nPayload * ts; + 850 .loc 1 702 0 + 851 019e 0022 movs r2, #0 + 852 01a0 0023 movs r3, #0 + 853 01a2 FFF7FEFF bl __aeabi_dcmpgt + 854 .LVL100: + 855 01a6 0028 cmp r0, #0 + 856 01a8 2FD0 beq .L53 + 702:./Drivers/BSP/Components/sx1272/sx1272.c **** double tPayload = nPayload * ts; + 857 .loc 1 702 0 is_stmt 0 discriminator 1 + ARM GAS /tmp/ccwcPdtV.s page 47 + + + 858 01aa 0022 movs r2, #0 + 859 01ac 1A4B ldr r3, .L55+8 + 860 01ae 2000 movs r0, r4 + 861 01b0 2900 movs r1, r5 + 862 01b2 FFF7FEFF bl __aeabi_dadd + 863 .LVL101: + 864 .L41: + 703:./Drivers/BSP/Components/sx1272/sx1272.c **** // Time on air + 865 .loc 1 703 0 is_stmt 1 discriminator 4 + 866 01b6 009A ldr r2, [sp] + 867 01b8 019B ldr r3, [sp, #4] + 868 01ba FFF7FEFF bl __aeabi_dmul + 869 .LVL102: + 870 01be 0200 movs r2, r0 + 871 01c0 0B00 movs r3, r1 + 872 .LVL103: + 705:./Drivers/BSP/Components/sx1272/sx1272.c **** // return ms secs + 873 .loc 1 705 0 discriminator 4 + 874 01c2 0298 ldr r0, [sp, #8] + 875 01c4 0399 ldr r1, [sp, #12] + 876 01c6 FFF7FEFF bl __aeabi_dadd + 877 .LVL104: + 707:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 878 .loc 1 707 0 discriminator 4 + 879 01ca 0022 movs r2, #0 + 880 01cc 134B ldr r3, .L55+12 + 881 01ce FFF7FEFF bl __aeabi_dmul + 882 .LVL105: + 883 01d2 144A ldr r2, .L55+20 + 884 01d4 144B ldr r3, .L55+24 + 885 01d6 FFF7FEFF bl __aeabi_dadd + 886 .LVL106: + 887 01da FFF7FEFF bl floor + 888 .LVL107: + 889 01de FFF7FEFF bl __aeabi_d2uiz + 890 .LVL108: + 891 .LBE372: + 709:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 892 .loc 1 709 0 discriminator 4 + 893 01e2 6BE7 b .L28 + 894 .LVL109: + 895 .L36: + 896 .LBB373: + 683:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 897 .loc 1 683 0 + 898 01e4 0022 movs r2, #0 + 899 01e6 114B ldr r3, .L55+28 + 900 01e8 0092 str r2, [sp] + 901 01ea 0193 str r3, [sp, #4] + 684:./Drivers/BSP/Components/sx1272/sx1272.c **** case 2: // 500 kHz + 902 .loc 1 684 0 + 903 01ec 81E7 b .L37 + 904 .LVL110: + 905 .L38: + 686:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 906 .loc 1 686 0 + 907 01ee 0022 movs r2, #0 + ARM GAS /tmp/ccwcPdtV.s page 48 + + + 908 01f0 0F4B ldr r3, .L55+32 + 909 01f2 0092 str r2, [sp] + 910 01f4 0193 str r3, [sp, #4] + 687:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 911 .loc 1 687 0 + 912 01f6 7CE7 b .L37 + 913 .LVL111: + 914 .L47: + 680:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 915 .loc 1 680 0 + 916 01f8 0022 movs r2, #0 + 917 01fa 0E4B ldr r3, .L55+36 + 918 01fc 0092 str r2, [sp] + 919 01fe 0193 str r3, [sp, #4] + 920 0200 77E7 b .L37 + 921 .LVL112: + 922 .L48: + 698:./Drivers/BSP/Components/sx1272/sx1272.c **** ( double )( 4 * ( SX1272.Settings.LoRa.Datarate - + 923 .loc 1 698 0 + 924 0202 0024 movs r4, #0 + 925 0204 A3E7 b .L39 + 926 .L49: + 700:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272.Settings.LoRa.Coderate + 4 ); + 927 .loc 1 700 0 + 928 0206 0020 movs r0, #0 + 929 0208 ADE7 b .L40 + 930 .LVL113: + 931 .L53: + 702:./Drivers/BSP/Components/sx1272/sx1272.c **** double tPayload = nPayload * ts; + 932 .loc 1 702 0 + 933 020a 0020 movs r0, #0 + 934 020c 0249 ldr r1, .L55+8 + 935 020e D2E7 b .L41 + 936 .L56: + 937 .align 2 + 938 .L55: + 939 0210 00000000 .word .LANCHOR0 + 940 0214 0000F03F .word 1072693248 + 941 0218 00002040 .word 1075838976 + 942 021c 00408F40 .word 1083129856 + 943 0220 00001140 .word 1074855936 + 944 0224 2B8716D9 .word -652835029 + 945 0228 CEF7EF3F .word 1072691150 + 946 022c 80840E41 .word 1091470464 + 947 0230 80841E41 .word 1092519040 + 948 0234 8084FE40 .word 1090421888 + 949 .LBE373: + 950 .cfi_endproc + 951 .LFE105: + 953 .section .text.SX1272ReadRssi,"ax",%progbits + 954 .align 1 + 955 .global SX1272ReadRssi + 956 .syntax unified + 957 .code 16 + 958 .thumb_func + 959 .fpu softvfp + 961 SX1272ReadRssi: + ARM GAS /tmp/ccwcPdtV.s page 49 + + + 962 .LFB113: +1042:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t rssi = 0; + 963 .loc 1 1042 0 + 964 .cfi_startproc + 965 @ args = 0, pretend = 0, frame = 8 + 966 @ frame_needed = 0, uses_anonymous_args = 0 + 967 .LVL114: + 968 0000 10B5 push {r4, lr} + 969 .LCFI12: + 970 .cfi_def_cfa_offset 8 + 971 .cfi_offset 4, -8 + 972 .cfi_offset 14, -4 + 973 0002 82B0 sub sp, sp, #8 + 974 .LCFI13: + 975 .cfi_def_cfa_offset 16 + 976 .LVL115: +1045:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 977 .loc 1 1045 0 + 978 0004 0028 cmp r0, #0 + 979 0006 04D0 beq .L59 + 980 0008 0128 cmp r0, #1 + 981 000a 0FD0 beq .L60 +1054:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 982 .loc 1 1054 0 + 983 000c 0120 movs r0, #1 + 984 .LVL116: + 985 000e 4042 rsbs r0, r0, #0 + 986 0010 0AE0 b .L58 + 987 .LVL117: + 988 .L59: + 989 .LBB374: + 990 .LBB375: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 991 .loc 1 1142 0 + 992 0012 6B46 mov r3, sp + 993 0014 DC1D adds r4, r3, #7 + 994 0016 0122 movs r2, #1 + 995 0018 2100 movs r1, r4 + 996 001a 1120 movs r0, #17 + 997 .LVL118: + 998 001c FFF7FEFF bl SX1272ReadBuffer + 999 .LVL119: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1000 .loc 1 1143 0 + 1001 0020 2078 ldrb r0, [r4] + 1002 .LVL120: + 1003 .LBE375: + 1004 .LBE374: +1048:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 1005 .loc 1 1048 0 + 1006 0022 4008 lsrs r0, r0, #1 + 1007 0024 4042 rsbs r0, r0, #0 + 1008 0026 00B2 sxth r0, r0 + 1009 .LVL121: + 1010 .L58: +1058:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1011 .loc 1 1058 0 + ARM GAS /tmp/ccwcPdtV.s page 50 + + + 1012 0028 02B0 add sp, sp, #8 + 1013 @ sp needed + 1014 002a 10BD pop {r4, pc} + 1015 .LVL122: + 1016 .L60: + 1017 .LBB376: + 1018 .LBB377: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1019 .loc 1 1142 0 + 1020 002c 6B46 mov r3, sp + 1021 002e DC1D adds r4, r3, #7 + 1022 0030 0122 movs r2, #1 + 1023 0032 2100 movs r1, r4 + 1024 0034 1B20 movs r0, #27 + 1025 .LVL123: + 1026 0036 FFF7FEFF bl SX1272ReadBuffer + 1027 .LVL124: + 1028 .LBE377: + 1029 .LBE376: +1051:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 1030 .loc 1 1051 0 + 1031 003a 2078 ldrb r0, [r4] + 1032 003c 8B38 subs r0, r0, #139 + 1033 .LVL125: +1052:./Drivers/BSP/Components/sx1272/sx1272.c **** default: + 1034 .loc 1 1052 0 + 1035 003e F3E7 b .L58 + 1036 .cfi_endproc + 1037 .LFE113: + 1039 .section .text.SX1272SetOpMode,"ax",%progbits + 1040 .align 1 + 1041 .global SX1272SetOpMode + 1042 .syntax unified + 1043 .code 16 + 1044 .thumb_func + 1045 .fpu softvfp + 1047 SX1272SetOpMode: + 1048 .LFB115: +1084:./Drivers/BSP/Components/sx1272/sx1272.c **** if( opMode == RF_OPMODE_SLEEP ) + 1049 .loc 1 1084 0 + 1050 .cfi_startproc + 1051 @ args = 0, pretend = 0, frame = 8 + 1052 @ frame_needed = 0, uses_anonymous_args = 0 + 1053 .LVL126: + 1054 0000 30B5 push {r4, r5, lr} + 1055 .LCFI14: + 1056 .cfi_def_cfa_offset 12 + 1057 .cfi_offset 4, -12 + 1058 .cfi_offset 5, -8 + 1059 .cfi_offset 14, -4 + 1060 0002 83B0 sub sp, sp, #12 + 1061 .LCFI15: + 1062 .cfi_def_cfa_offset 24 + 1063 0004 051E subs r5, r0, #0 +1085:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1064 .loc 1 1085 0 + 1065 0006 1CD0 beq .L66 + ARM GAS /tmp/ccwcPdtV.s page 51 + + +1091:./Drivers/BSP/Components/sx1272/sx1272.c **** LoRaBoardCallbacks->SX1272BoardSetAntSw( opMode ); + 1066 .loc 1 1091 0 + 1067 0008 114C ldr r4, .L67 + 1068 000a 2368 ldr r3, [r4] + 1069 000c 1B69 ldr r3, [r3, #16] + 1070 000e 0020 movs r0, #0 + 1071 .LVL127: + 1072 0010 9847 blx r3 + 1073 .LVL128: +1092:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1074 .loc 1 1092 0 + 1075 0012 2368 ldr r3, [r4] + 1076 0014 5B69 ldr r3, [r3, #20] + 1077 0016 2800 movs r0, r5 + 1078 0018 9847 blx r3 + 1079 .LVL129: + 1080 .L65: + 1081 .LBB378: + 1082 .LBB379: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1083 .loc 1 1142 0 + 1084 001a 6B46 mov r3, sp + 1085 001c DC1D adds r4, r3, #7 + 1086 001e 0122 movs r2, #1 + 1087 0020 2100 movs r1, r4 + 1088 0022 0120 movs r0, #1 + 1089 0024 FFF7FEFF bl SX1272ReadBuffer + 1090 .LVL130: + 1091 .LBE379: + 1092 .LBE378: +1094:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1093 .loc 1 1094 0 + 1094 0028 0020 movs r0, #0 + 1095 002a 2056 ldrsb r0, [r4, r0] + 1096 002c 0723 movs r3, #7 + 1097 002e 9843 bics r0, r3 + 1098 0030 2843 orrs r0, r5 + 1099 .LVL131: + 1100 0032 2070 strb r0, [r4] + 1101 .LVL132: + 1102 .LBB380: + 1103 .LBB381: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1104 .loc 1 1136 0 + 1105 0034 0122 movs r2, #1 + 1106 0036 2100 movs r1, r4 + 1107 0038 0120 movs r0, #1 + 1108 003a FFF7FEFF bl SX1272WriteBuffer + 1109 .LVL133: + 1110 .LBE381: + 1111 .LBE380: +1095:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1112 .loc 1 1095 0 + 1113 003e 03B0 add sp, sp, #12 + 1114 @ sp needed + 1115 0040 30BD pop {r4, r5, pc} + 1116 .LVL134: + ARM GAS /tmp/ccwcPdtV.s page 52 + + + 1117 .L66: +1087:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1118 .loc 1 1087 0 + 1119 0042 034B ldr r3, .L67 + 1120 0044 1B68 ldr r3, [r3] + 1121 0046 1B69 ldr r3, [r3, #16] + 1122 0048 0120 movs r0, #1 + 1123 .LVL135: + 1124 004a 9847 blx r3 + 1125 .LVL136: + 1126 004c E5E7 b .L65 + 1127 .L68: + 1128 004e C046 .align 2 + 1129 .L67: + 1130 0050 00000000 .word .LANCHOR1 + 1131 .cfi_endproc + 1132 .LFE115: + 1134 .section .text.SX1272SetSleep,"ax",%progbits + 1135 .align 1 + 1136 .global SX1272SetSleep + 1137 .syntax unified + 1138 .code 16 + 1139 .thumb_func + 1140 .fpu softvfp + 1142 SX1272SetSleep: + 1143 .LFB107: + 789:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); + 1144 .loc 1 789 0 + 1145 .cfi_startproc + 1146 @ args = 0, pretend = 0, frame = 0 + 1147 @ frame_needed = 0, uses_anonymous_args = 0 + 1148 0000 10B5 push {r4, lr} + 1149 .LCFI16: + 1150 .cfi_def_cfa_offset 8 + 1151 .cfi_offset 4, -8 + 1152 .cfi_offset 14, -4 + 790:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &TxTimeoutTimer ); + 1153 .loc 1 790 0 + 1154 0002 0648 ldr r0, .L70 + 1155 0004 FFF7FEFF bl TimerStop + 1156 .LVL137: + 791:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1157 .loc 1 791 0 + 1158 0008 0548 ldr r0, .L70+4 + 1159 000a FFF7FEFF bl TimerStop + 1160 .LVL138: + 793:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 1161 .loc 1 793 0 + 1162 000e 0020 movs r0, #0 + 1163 0010 FFF7FEFF bl SX1272SetOpMode + 1164 .LVL139: + 794:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1165 .loc 1 794 0 + 1166 0014 034B ldr r3, .L70+8 + 1167 0016 0022 movs r2, #0 + 1168 0018 1A71 strb r2, [r3, #4] + 795:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 53 + + + 1169 .loc 1 795 0 + 1170 @ sp needed + 1171 001a 10BD pop {r4, pc} + 1172 .L71: + 1173 .align 2 + 1174 .L70: + 1175 001c 00000000 .word .LANCHOR2 + 1176 0020 00000000 .word .LANCHOR3 + 1177 0024 00000000 .word .LANCHOR0 + 1178 .cfi_endproc + 1179 .LFE107: + 1181 .section .text.SX1272SetStby,"ax",%progbits + 1182 .align 1 + 1183 .global SX1272SetStby + 1184 .syntax unified + 1185 .code 16 + 1186 .thumb_func + 1187 .fpu softvfp + 1189 SX1272SetStby: + 1190 .LFB108: + 798:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutTimer ); + 1191 .loc 1 798 0 + 1192 .cfi_startproc + 1193 @ args = 0, pretend = 0, frame = 0 + 1194 @ frame_needed = 0, uses_anonymous_args = 0 + 1195 0000 10B5 push {r4, lr} + 1196 .LCFI17: + 1197 .cfi_def_cfa_offset 8 + 1198 .cfi_offset 4, -8 + 1199 .cfi_offset 14, -4 + 799:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &TxTimeoutTimer ); + 1200 .loc 1 799 0 + 1201 0002 0648 ldr r0, .L73 + 1202 0004 FFF7FEFF bl TimerStop + 1203 .LVL140: + 800:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1204 .loc 1 800 0 + 1205 0008 0548 ldr r0, .L73+4 + 1206 000a FFF7FEFF bl TimerStop + 1207 .LVL141: + 802:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 1208 .loc 1 802 0 + 1209 000e 0120 movs r0, #1 + 1210 0010 FFF7FEFF bl SX1272SetOpMode + 1211 .LVL142: + 803:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1212 .loc 1 803 0 + 1213 0014 034B ldr r3, .L73+8 + 1214 0016 0022 movs r2, #0 + 1215 0018 1A71 strb r2, [r3, #4] + 804:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1216 .loc 1 804 0 + 1217 @ sp needed + 1218 001a 10BD pop {r4, pc} + 1219 .L74: + 1220 .align 2 + 1221 .L73: + ARM GAS /tmp/ccwcPdtV.s page 54 + + + 1222 001c 00000000 .word .LANCHOR2 + 1223 0020 00000000 .word .LANCHOR3 + 1224 0024 00000000 .word .LANCHOR0 + 1225 .cfi_endproc + 1226 .LFE108: + 1228 .section .text.SX1272SetRx,"ax",%progbits + 1229 .align 1 + 1230 .global SX1272SetRx + 1231 .syntax unified + 1232 .code 16 + 1233 .thumb_func + 1234 .fpu softvfp + 1236 SX1272SetRx: + 1237 .LFB109: + 807:./Drivers/BSP/Components/sx1272/sx1272.c **** bool rxContinuous = false; + 1238 .loc 1 807 0 + 1239 .cfi_startproc + 1240 @ args = 0, pretend = 0, frame = 16 + 1241 @ frame_needed = 0, uses_anonymous_args = 0 + 1242 .LVL143: + 1243 0000 F0B5 push {r4, r5, r6, r7, lr} + 1244 .LCFI18: + 1245 .cfi_def_cfa_offset 20 + 1246 .cfi_offset 4, -20 + 1247 .cfi_offset 5, -16 + 1248 .cfi_offset 6, -12 + 1249 .cfi_offset 7, -8 + 1250 .cfi_offset 14, -4 + 1251 0002 85B0 sub sp, sp, #20 + 1252 .LCFI19: + 1253 .cfi_def_cfa_offset 40 + 1254 0004 0600 movs r6, r0 + 1255 .LVL144: + 810:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1256 .loc 1 810 0 + 1257 0006 804B ldr r3, .L92 + 1258 0008 5B79 ldrb r3, [r3, #5] + 1259 000a 002B cmp r3, #0 + 1260 000c 03D0 beq .L77 + 1261 000e 012B cmp r3, #1 + 1262 0010 59D0 beq .L78 + 808:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1263 .loc 1 808 0 + 1264 0012 0027 movs r7, #0 + 1265 0014 3EE0 b .L76 + 1266 .L77: + 814:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1267 .loc 1 814 0 + 1268 0016 7C4C ldr r4, .L92 + 1269 0018 2623 movs r3, #38 + 1270 001a E75C ldrb r7, [r4, r3] + 1271 .LVL145: + 1272 .LBB382: + 1273 .LBB383: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1274 .loc 1 1142 0 + 1275 001c 0F25 movs r5, #15 + ARM GAS /tmp/ccwcPdtV.s page 55 + + + 1276 001e 6D44 add r5, r5, sp + 1277 0020 0122 movs r2, #1 + 1278 0022 2900 movs r1, r5 + 1279 0024 4020 movs r0, #64 + 1280 .LVL146: + 1281 0026 FFF7FEFF bl SX1272ReadBuffer + 1282 .LVL147: + 1283 .LBE383: + 1284 .LBE382: + 822:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 1285 .loc 1 822 0 + 1286 002a 0022 movs r2, #0 + 1287 002c AA56 ldrsb r2, [r5, r2] + 825:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_00 + 1288 .loc 1 825 0 + 1289 002e 0323 movs r3, #3 + 1290 0030 1340 ands r3, r2 + 822:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 1291 .loc 1 822 0 + 1292 0032 0C22 movs r2, #12 + 1293 0034 1343 orrs r3, r2 + 1294 .LVL148: + 1295 0036 6A46 mov r2, sp + 1296 0038 511D adds r1, r2, #5 + 1297 003a 0B70 strb r3, [r1] + 1298 .LVL149: + 1299 .LBB384: + 1300 .LBB385: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1301 .loc 1 1136 0 + 1302 003c 0122 movs r2, #1 + 1303 003e 4020 movs r0, #64 + 1304 0040 FFF7FEFF bl SX1272WriteBuffer + 1305 .LVL150: + 1306 .LBE385: + 1307 .LBE384: + 1308 .LBB386: + 1309 .LBB387: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1310 .loc 1 1142 0 + 1311 0044 0122 movs r2, #1 + 1312 0046 2900 movs r1, r5 + 1313 0048 4120 movs r0, #65 + 1314 004a FFF7FEFF bl SX1272ReadBuffer + 1315 .LVL151: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1316 .loc 1 1143 0 + 1317 004e 2A78 ldrb r2, [r5] + 1318 .LVL152: + 1319 .LBE387: + 1320 .LBE386: + 829:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_MAP_MASK + 1321 .loc 1 829 0 + 1322 0050 3F23 movs r3, #63 + 1323 0052 5B42 rsbs r3, r3, #0 + 1324 0054 1343 orrs r3, r2 + 1325 .LVL153: + ARM GAS /tmp/ccwcPdtV.s page 56 + + + 1326 0056 01A9 add r1, sp, #4 + 1327 0058 0B70 strb r3, [r1] + 1328 .LVL154: + 1329 .LBB388: + 1330 .LBB389: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1331 .loc 1 1136 0 + 1332 005a 0122 movs r2, #1 + 1333 005c 4120 movs r0, #65 + 1334 005e FFF7FEFF bl SX1272WriteBuffer + 1335 .LVL155: + 1336 .LBE389: + 1337 .LBE388: + 1338 .LBB390: + 1339 .LBB391: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1340 .loc 1 1142 0 + 1341 0062 0122 movs r2, #1 + 1342 0064 2900 movs r1, r5 + 1343 0066 3520 movs r0, #53 + 1344 0068 FFF7FEFF bl SX1272ReadBuffer + 1345 .LVL156: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1346 .loc 1 1143 0 + 1347 006c 2A78 ldrb r2, [r5] + 1348 .LVL157: + 1349 .LBE391: + 1350 .LBE390: + 834:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1351 .loc 1 834 0 + 1352 006e 3F23 movs r3, #63 + 1353 0070 1340 ands r3, r2 + 1354 0072 3E22 movs r2, #62 + 1355 0074 A354 strb r3, [r4, r2] + 1356 .LVL158: + 1357 0076 6B46 mov r3, sp + 1358 0078 D91C adds r1, r3, #3 + 1359 007a 1E23 movs r3, #30 + 1360 007c 0B70 strb r3, [r1] + 1361 .LVL159: + 1362 .LBB392: + 1363 .LBB393: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1364 .loc 1 1136 0 + 1365 007e 3D3A subs r2, r2, #61 + 1366 0080 0D20 movs r0, #13 + 1367 0082 FFF7FEFF bl SX1272WriteBuffer + 1368 .LVL160: + 1369 .LBE393: + 1370 .LBE392: + 838:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + 1371 .loc 1 838 0 + 1372 0086 0023 movs r3, #0 + 1373 0088 3022 movs r2, #48 + 1374 008a A354 strb r3, [r4, r2] + 839:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 1375 .loc 1 839 0 + ARM GAS /tmp/ccwcPdtV.s page 57 + + + 1376 008c 0132 adds r2, r2, #1 + 1377 008e A354 strb r3, [r4, r2] + 840:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; + 1378 .loc 1 840 0 + 1379 0090 A387 strh r3, [r4, #60] + 841:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1380 .loc 1 841 0 + 1381 0092 6387 strh r3, [r4, #58] + 1382 .LVL161: + 1383 .L76: + 893:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1384 .loc 1 893 0 + 1385 0094 8022 movs r2, #128 + 1386 0096 5200 lsls r2, r2, #1 + 1387 0098 0021 movs r1, #0 + 1388 009a 5C48 ldr r0, .L92+4 + 1389 009c FFF7FEFF bl memset + 1390 .LVL162: + 895:./Drivers/BSP/Components/sx1272/sx1272.c **** if( timeout != 0 ) + 1391 .loc 1 895 0 + 1392 00a0 594B ldr r3, .L92 + 1393 00a2 0122 movs r2, #1 + 1394 00a4 1A71 strb r2, [r3, #4] + 896:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1395 .loc 1 896 0 + 1396 00a6 002E cmp r6, #0 + 1397 00a8 00D0 beq .LCB1258 + 1398 00aa 8FE0 b .L89 @long jump + 1399 .LCB1258: + 1400 .L83: + 902:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1401 .loc 1 902 0 + 1402 00ac 564B ldr r3, .L92 + 1403 00ae 5B79 ldrb r3, [r3, #5] + 1404 00b0 002B cmp r3, #0 + 1405 00b2 00D1 bne .LCB1263 + 1406 00b4 93E0 b .L90 @long jump + 1407 .LCB1263: + 914:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1408 .loc 1 914 0 + 1409 00b6 002F cmp r7, #0 + 1410 00b8 00D0 beq .LCB1265 + 1411 00ba A0E0 b .L91 @long jump + 1412 .LCB1265: + 920:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1413 .loc 1 920 0 + 1414 00bc 0620 movs r0, #6 + 1415 00be FFF7FEFF bl SX1272SetOpMode + 1416 .LVL163: + 1417 .L75: + 923:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1418 .loc 1 923 0 + 1419 00c2 05B0 add sp, sp, #20 + 1420 @ sp needed + 1421 .LVL164: + 1422 .LVL165: + 1423 00c4 F0BD pop {r4, r5, r6, r7, pc} + ARM GAS /tmp/ccwcPdtV.s page 58 + + + 1424 .LVL166: + 1425 .L78: + 846:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1426 .loc 1 846 0 + 1427 00c6 504A ldr r2, .L92 + 1428 00c8 5523 movs r3, #85 + 1429 00ca D35C ldrb r3, [r2, r3] + 1430 00cc 002B cmp r3, #0 + 1431 00ce 48D0 beq .L79 + 1432 .LVL167: + 1433 .LBB394: + 1434 .LBB395: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1435 .loc 1 1142 0 + 1436 00d0 0F24 movs r4, #15 + 1437 00d2 6C44 add r4, r4, sp + 1438 00d4 0122 movs r2, #1 + 1439 00d6 2100 movs r1, r4 + 1440 00d8 3320 movs r0, #51 + 1441 .LVL168: + 1442 00da FFF7FEFF bl SX1272ReadBuffer + 1443 .LVL169: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1444 .loc 1 1143 0 + 1445 00de 2378 ldrb r3, [r4] + 1446 .LVL170: + 1447 .LBE395: + 1448 .LBE394: + 848:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); + 1449 .loc 1 848 0 + 1450 00e0 4122 movs r2, #65 + 1451 00e2 1343 orrs r3, r2 + 1452 .LVL171: + 1453 00e4 6A46 mov r2, sp + 1454 00e6 D11D adds r1, r2, #7 + 1455 00e8 0B70 strb r3, [r1] + 1456 .LVL172: + 1457 .LBB396: + 1458 .LBB397: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1459 .loc 1 1136 0 + 1460 00ea 0122 movs r2, #1 + 1461 00ec 3320 movs r0, #51 + 1462 00ee FFF7FEFF bl SX1272WriteBuffer + 1463 .LVL173: + 1464 00f2 6B46 mov r3, sp + 1465 00f4 991D adds r1, r3, #6 + 1466 00f6 1923 movs r3, #25 + 1467 00f8 0B70 strb r3, [r1] + 1468 .LVL174: + 1469 .LBE397: + 1470 .LBE396: + 1471 .LBB398: + 1472 .LBB399: + 1473 00fa 0122 movs r2, #1 + 1474 00fc 3B20 movs r0, #59 + 1475 00fe FFF7FEFF bl SX1272WriteBuffer + ARM GAS /tmp/ccwcPdtV.s page 59 + + + 1476 .LVL175: + 1477 .L80: + 1478 .LBE399: + 1479 .LBE398: + 857:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1480 .loc 1 857 0 + 1481 0102 414B ldr r3, .L92 + 1482 0104 5622 movs r2, #86 + 1483 0106 9F5C ldrb r7, [r3, r2] + 1484 .LVL176: + 859:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1485 .loc 1 859 0 + 1486 0108 033A subs r2, r2, #3 + 1487 010a 9B5C ldrb r3, [r3, r2] + 1488 010c 002B cmp r3, #0 + 1489 010e 44D0 beq .L81 + 1490 .LVL177: + 1491 0110 0B21 movs r1, #11 + 1492 0112 6944 add r1, r1, sp + 1493 0114 1D23 movs r3, #29 + 1494 0116 0B70 strb r3, [r1] + 1495 .LVL178: + 1496 .LBB400: + 1497 .LBB401: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1498 .loc 1 1136 0 + 1499 0118 523A subs r2, r2, #82 + 1500 011a 1120 movs r0, #17 + 1501 011c FFF7FEFF bl SX1272WriteBuffer + 1502 .LVL179: + 1503 .LBE401: + 1504 .LBE400: + 1505 .LBB402: + 1506 .LBB403: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1507 .loc 1 1142 0 + 1508 0120 0F24 movs r4, #15 + 1509 0122 6C44 add r4, r4, sp + 1510 0124 0122 movs r2, #1 + 1511 0126 2100 movs r1, r4 + 1512 0128 4020 movs r0, #64 + 1513 012a FFF7FEFF bl SX1272ReadBuffer + 1514 .LVL180: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1515 .loc 1 1143 0 + 1516 012e 2278 ldrb r2, [r4] + 1517 .LVL181: + 1518 .LBE403: + 1519 .LBE402: + 871:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1520 .loc 1 871 0 + 1521 0130 3323 movs r3, #51 + 1522 0132 1340 ands r3, r2 + 1523 .LVL182: + 1524 0134 0A21 movs r1, #10 + 1525 0136 6944 add r1, r1, sp + 1526 0138 0B70 strb r3, [r1] + ARM GAS /tmp/ccwcPdtV.s page 60 + + + 1527 .LVL183: + 1528 .LBB404: + 1529 .LBB405: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1530 .loc 1 1136 0 + 1531 013a 0122 movs r2, #1 + 1532 013c 4020 movs r0, #64 + 1533 013e FFF7FEFF bl SX1272WriteBuffer + 1534 .LVL184: + 1535 .L82: + 1536 0142 0F21 movs r1, #15 + 1537 0144 6944 add r1, r1, sp + 1538 0146 0024 movs r4, #0 + 1539 0148 0C70 strb r4, [r1] + 1540 .LVL185: + 1541 .LBE405: + 1542 .LBE404: + 1543 .LBB406: + 1544 .LBB407: + 1545 014a 0122 movs r2, #1 + 1546 014c 0F20 movs r0, #15 + 1547 014e FFF7FEFF bl SX1272WriteBuffer + 1548 .LVL186: + 1549 0152 0E21 movs r1, #14 + 1550 0154 6944 add r1, r1, sp + 1551 0156 0C70 strb r4, [r1] + 1552 .LVL187: + 1553 .LBE407: + 1554 .LBE406: + 1555 .LBB408: + 1556 .LBB409: + 1557 0158 0122 movs r2, #1 + 1558 015a 0D20 movs r0, #13 + 1559 015c FFF7FEFF bl SX1272WriteBuffer + 1560 .LVL188: + 1561 0160 98E7 b .L76 + 1562 .LVL189: + 1563 .L79: + 1564 .LBE409: + 1565 .LBE408: + 1566 .LBB410: + 1567 .LBB411: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1568 .loc 1 1142 0 + 1569 0162 0F24 movs r4, #15 + 1570 0164 6C44 add r4, r4, sp + 1571 0166 0122 movs r2, #1 + 1572 0168 2100 movs r1, r4 + 1573 016a 3320 movs r0, #51 + 1574 .LVL190: + 1575 016c FFF7FEFF bl SX1272ReadBuffer + 1576 .LVL191: + 1577 .LBE411: + 1578 .LBE410: + 853:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); + 1579 .loc 1 853 0 + 1580 0170 0023 movs r3, #0 + ARM GAS /tmp/ccwcPdtV.s page 61 + + + 1581 0172 E356 ldrsb r3, [r4, r3] + 1582 0174 4122 movs r2, #65 + 1583 0176 9343 bics r3, r2 + 1584 0178 0122 movs r2, #1 + 1585 017a 1343 orrs r3, r2 + 1586 .LVL192: + 1587 017c 0921 movs r1, #9 + 1588 017e 6944 add r1, r1, sp + 1589 0180 0B70 strb r3, [r1] + 1590 .LVL193: + 1591 .LBB412: + 1592 .LBB413: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1593 .loc 1 1136 0 + 1594 0182 0122 movs r2, #1 + 1595 0184 3320 movs r0, #51 + 1596 0186 FFF7FEFF bl SX1272WriteBuffer + 1597 .LVL194: + 1598 018a 02A9 add r1, sp, #8 + 1599 018c 1D23 movs r3, #29 + 1600 018e 0B70 strb r3, [r1] + 1601 .LVL195: + 1602 .LBE413: + 1603 .LBE412: + 1604 .LBB414: + 1605 .LBB415: + 1606 0190 0122 movs r2, #1 + 1607 0192 3B20 movs r0, #59 + 1608 0194 FFF7FEFF bl SX1272WriteBuffer + 1609 .LVL196: + 1610 0198 B3E7 b .L80 + 1611 .LVL197: + 1612 .L81: + 1613 019a 0D21 movs r1, #13 + 1614 019c 6944 add r1, r1, sp + 1615 019e 1F23 movs r3, #31 + 1616 01a0 0B70 strb r3, [r1] + 1617 .LVL198: + 1618 .LBE415: + 1619 .LBE414: + 1620 .LBB416: + 1621 .LBB417: + 1622 01a2 0122 movs r2, #1 + 1623 01a4 1120 movs r0, #17 + 1624 01a6 FFF7FEFF bl SX1272WriteBuffer + 1625 .LVL199: + 1626 .LBE417: + 1627 .LBE416: + 1628 .LBB418: + 1629 .LBB419: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1630 .loc 1 1142 0 + 1631 01aa 0F24 movs r4, #15 + 1632 01ac 6C44 add r4, r4, sp + 1633 01ae 0122 movs r2, #1 + 1634 01b0 2100 movs r1, r4 + 1635 01b2 4020 movs r0, #64 + ARM GAS /tmp/ccwcPdtV.s page 62 + + + 1636 01b4 FFF7FEFF bl SX1272ReadBuffer + 1637 .LVL200: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1638 .loc 1 1143 0 + 1639 01b8 2278 ldrb r2, [r4] + 1640 .LVL201: + 1641 .LBE419: + 1642 .LBE418: + 885:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1643 .loc 1 885 0 + 1644 01ba 3F23 movs r3, #63 + 1645 01bc 1340 ands r3, r2 + 1646 .LVL202: + 1647 01be 03A9 add r1, sp, #12 + 1648 01c0 0B70 strb r3, [r1] + 1649 .LVL203: + 1650 .LBB420: + 1651 .LBB421: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1652 .loc 1 1136 0 + 1653 01c2 0122 movs r2, #1 + 1654 01c4 4020 movs r0, #64 + 1655 01c6 FFF7FEFF bl SX1272WriteBuffer + 1656 .LVL204: + 1657 01ca BAE7 b .L82 + 1658 .LVL205: + 1659 .L89: + 1660 .LBE421: + 1661 .LBE420: + 898:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutTimer ); + 1662 .loc 1 898 0 + 1663 01cc 104C ldr r4, .L92+8 + 1664 01ce 3100 movs r1, r6 + 1665 01d0 2000 movs r0, r4 + 1666 01d2 FFF7FEFF bl TimerSetValue + 1667 .LVL206: + 899:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1668 .loc 1 899 0 + 1669 01d6 2000 movs r0, r4 + 1670 01d8 FFF7FEFF bl TimerStart + 1671 .LVL207: + 1672 01dc 66E7 b .L83 + 1673 .L90: + 904:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1674 .loc 1 904 0 + 1675 01de 0520 movs r0, #5 + 1676 01e0 FFF7FEFF bl SX1272SetOpMode + 1677 .LVL208: + 906:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1678 .loc 1 906 0 + 1679 01e4 002F cmp r7, #0 + 1680 01e6 00D0 beq .LCB1566 + 1681 01e8 6BE7 b .L75 @long jump + 1682 .LCB1566: + 908:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); + 1683 .loc 1 908 0 + 1684 01ea 074B ldr r3, .L92 + ARM GAS /tmp/ccwcPdtV.s page 63 + + + 1685 01ec D96A ldr r1, [r3, #44] + 1686 01ee 094C ldr r4, .L92+12 + 1687 01f0 2000 movs r0, r4 + 1688 01f2 FFF7FEFF bl TimerSetValue + 1689 .LVL209: + 909:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1690 .loc 1 909 0 + 1691 01f6 2000 movs r0, r4 + 1692 01f8 FFF7FEFF bl TimerStart + 1693 .LVL210: + 1694 01fc 61E7 b .L75 + 1695 .L91: + 916:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1696 .loc 1 916 0 + 1697 01fe 0520 movs r0, #5 + 1698 0200 FFF7FEFF bl SX1272SetOpMode + 1699 .LVL211: + 1700 0204 5DE7 b .L75 + 1701 .L93: + 1702 0206 C046 .align 2 + 1703 .L92: + 1704 0208 00000000 .word .LANCHOR0 + 1705 020c 00000000 .word RxTxBuffer + 1706 0210 00000000 .word .LANCHOR2 + 1707 0214 00000000 .word .LANCHOR4 + 1708 .cfi_endproc + 1709 .LFE109: + 1711 .section .text.SX1272SetTx,"ax",%progbits + 1712 .align 1 + 1713 .global SX1272SetTx + 1714 .syntax unified + 1715 .code 16 + 1716 .thumb_func + 1717 .fpu softvfp + 1719 SX1272SetTx: + 1720 .LFB110: + 926:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerSetValue( &TxTimeoutTimer, timeout ); + 1721 .loc 1 926 0 + 1722 .cfi_startproc + 1723 @ args = 0, pretend = 0, frame = 8 + 1724 @ frame_needed = 0, uses_anonymous_args = 0 + 1725 .LVL212: + 1726 0000 10B5 push {r4, lr} + 1727 .LCFI20: + 1728 .cfi_def_cfa_offset 8 + 1729 .cfi_offset 4, -8 + 1730 .cfi_offset 14, -4 + 1731 0002 82B0 sub sp, sp, #8 + 1732 .LCFI21: + 1733 .cfi_def_cfa_offset 16 + 1734 0004 0100 movs r1, r0 + 927:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1735 .loc 1 927 0 + 1736 0006 4048 ldr r0, .L100 + 1737 .LVL213: + 1738 0008 FFF7FEFF bl TimerSetValue + 1739 .LVL214: + ARM GAS /tmp/ccwcPdtV.s page 64 + + + 929:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1740 .loc 1 929 0 + 1741 000c 3F4B ldr r3, .L100+4 + 1742 000e 5B79 ldrb r3, [r3, #5] + 1743 0010 002B cmp r3, #0 + 1744 0012 0CD0 beq .L96 + 1745 0014 012B cmp r3, #1 + 1746 0016 39D0 beq .L97 + 1747 .L95: + 983:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &TxTimeoutTimer ); + 1748 .loc 1 983 0 + 1749 0018 3C4B ldr r3, .L100+4 + 1750 001a 0222 movs r2, #2 + 1751 001c 1A71 strb r2, [r3, #4] + 984:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_TRANSMITTER ); + 1752 .loc 1 984 0 + 1753 001e 3A48 ldr r0, .L100 + 1754 0020 FFF7FEFF bl TimerStart + 1755 .LVL215: + 985:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1756 .loc 1 985 0 + 1757 0024 0320 movs r0, #3 + 1758 0026 FFF7FEFF bl SX1272SetOpMode + 1759 .LVL216: + 986:./Drivers/BSP/Components/sx1272/sx1272.c **** + 1760 .loc 1 986 0 + 1761 002a 02B0 add sp, sp, #8 + 1762 @ sp needed + 1763 002c 10BD pop {r4, pc} + 1764 .L96: + 1765 .LVL217: + 1766 .LBB422: + 1767 .LBB423: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1768 .loc 1 1142 0 + 1769 002e 6B46 mov r3, sp + 1770 0030 DC1D adds r4, r3, #7 + 1771 0032 0122 movs r2, #1 + 1772 0034 2100 movs r1, r4 + 1773 0036 4020 movs r0, #64 + 1774 0038 FFF7FEFF bl SX1272ReadBuffer + 1775 .LVL218: + 1776 .LBE423: + 1777 .LBE422: + 939:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 1778 .loc 1 939 0 + 1779 003c 0022 movs r2, #0 + 1780 003e A256 ldrsb r2, [r4, r2] + 940:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO2_MAS + 1781 .loc 1 940 0 + 1782 0040 0323 movs r3, #3 + 1783 0042 1340 ands r3, r2 + 939:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING1_DIO1_MAS + 1784 .loc 1 939 0 + 1785 0044 1022 movs r2, #16 + 1786 0046 1343 orrs r3, r2 + 1787 .LVL219: + ARM GAS /tmp/ccwcPdtV.s page 65 + + + 1788 0048 6A46 mov r2, sp + 1789 004a D11C adds r1, r2, #3 + 1790 004c 0B70 strb r3, [r1] + 1791 .LVL220: + 1792 .LBB424: + 1793 .LBB425: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1794 .loc 1 1136 0 + 1795 004e 0122 movs r2, #1 + 1796 0050 4020 movs r0, #64 + 1797 0052 FFF7FEFF bl SX1272WriteBuffer + 1798 .LVL221: + 1799 .LBE425: + 1800 .LBE424: + 1801 .LBB426: + 1802 .LBB427: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1803 .loc 1 1142 0 + 1804 0056 0122 movs r2, #1 + 1805 0058 2100 movs r1, r4 + 1806 005a 4120 movs r0, #65 + 1807 005c FFF7FEFF bl SX1272ReadBuffer + 1808 .LVL222: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1809 .loc 1 1143 0 + 1810 0060 2278 ldrb r2, [r4] + 1811 .LVL223: + 1812 .LBE427: + 1813 .LBE426: + 944:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_DIOMAPPING2_MAP_MASK + 1814 .loc 1 944 0 + 1815 0062 3E23 movs r3, #62 + 1816 0064 1340 ands r3, r2 + 1817 .LVL224: + 1818 0066 6A46 mov r2, sp + 1819 0068 911C adds r1, r2, #2 + 1820 006a 0B70 strb r3, [r1] + 1821 .LVL225: + 1822 .LBB428: + 1823 .LBB429: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1824 .loc 1 1136 0 + 1825 006c 0122 movs r2, #1 + 1826 006e 4120 movs r0, #65 + 1827 0070 FFF7FEFF bl SX1272WriteBuffer + 1828 .LVL226: + 1829 .LBE429: + 1830 .LBE428: + 1831 .LBB430: + 1832 .LBB431: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1833 .loc 1 1142 0 + 1834 0074 0122 movs r2, #1 + 1835 0076 2100 movs r1, r4 + 1836 0078 3520 movs r0, #53 + 1837 007a FFF7FEFF bl SX1272ReadBuffer + 1838 .LVL227: + ARM GAS /tmp/ccwcPdtV.s page 66 + + +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1839 .loc 1 1143 0 + 1840 007e 2278 ldrb r2, [r4] + 1841 .LVL228: + 1842 .LBE431: + 1843 .LBE430: + 946:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1844 .loc 1 946 0 + 1845 0080 3F23 movs r3, #63 + 1846 0082 1340 ands r3, r2 + 1847 0084 3E22 movs r2, #62 + 1848 0086 2149 ldr r1, .L100+4 + 1849 0088 8B54 strb r3, [r1, r2] + 948:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 1850 .loc 1 948 0 + 1851 008a C5E7 b .L95 + 1852 .L97: + 951:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1853 .loc 1 951 0 + 1854 008c 1F4A ldr r2, .L100+4 + 1855 008e 5323 movs r3, #83 + 1856 0090 D35C ldrb r3, [r2, r3] + 1857 0092 002B cmp r3, #0 + 1858 0094 1BD1 bne .L99 + 1859 .LVL229: + 1860 0096 6B46 mov r3, sp + 1861 0098 D91D adds r1, r3, #7 + 1862 009a F723 movs r3, #247 + 1863 009c 0B70 strb r3, [r1] + 1864 .LVL230: + 1865 .LBB432: + 1866 .LBB433: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1867 .loc 1 1136 0 + 1868 009e 0122 movs r2, #1 + 1869 00a0 1120 movs r0, #17 + 1870 00a2 FFF7FEFF bl SX1272WriteBuffer + 1871 .LVL231: + 1872 .LBE433: + 1873 .LBE432: + 1874 .LBB434: + 1875 .LBB435: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1876 .loc 1 1142 0 + 1877 00a6 6B46 mov r3, sp + 1878 00a8 9C1D adds r4, r3, #6 + 1879 00aa 0122 movs r2, #1 + 1880 00ac 2100 movs r1, r4 + 1881 00ae 4020 movs r0, #64 + 1882 00b0 FFF7FEFF bl SX1272ReadBuffer + 1883 .LVL232: + 1884 .LBE435: + 1885 .LBE434: + 977:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1886 .loc 1 977 0 + 1887 00b4 0022 movs r2, #0 + 1888 00b6 A256 ldrsb r2, [r4, r2] + ARM GAS /tmp/ccwcPdtV.s page 67 + + + 1889 00b8 3F23 movs r3, #63 + 1890 00ba 1340 ands r3, r2 + 1891 00bc 4022 movs r2, #64 + 1892 00be 1343 orrs r3, r2 + 1893 .LVL233: + 1894 00c0 2370 strb r3, [r4] + 1895 .LVL234: + 1896 .LBB436: + 1897 .LBB437: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1898 .loc 1 1136 0 + 1899 00c2 0122 movs r2, #1 + 1900 00c4 2100 movs r1, r4 + 1901 00c6 4020 movs r0, #64 + 1902 00c8 FFF7FEFF bl SX1272WriteBuffer + 1903 .LVL235: + 1904 00cc A4E7 b .L95 + 1905 .LVL236: + 1906 .L99: + 1907 00ce 6B46 mov r3, sp + 1908 00d0 591D adds r1, r3, #5 + 1909 00d2 F523 movs r3, #245 + 1910 00d4 0B70 strb r3, [r1] + 1911 .LVL237: + 1912 .LBE437: + 1913 .LBE436: + 1914 .LBB438: + 1915 .LBB439: + 1916 00d6 0122 movs r2, #1 + 1917 00d8 1120 movs r0, #17 + 1918 00da FFF7FEFF bl SX1272WriteBuffer + 1919 .LVL238: + 1920 .LBE439: + 1921 .LBE438: + 1922 .LBB440: + 1923 .LBB441: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 1924 .loc 1 1142 0 + 1925 00de 6B46 mov r3, sp + 1926 00e0 DC1D adds r4, r3, #7 + 1927 00e2 0122 movs r2, #1 + 1928 00e4 2100 movs r1, r4 + 1929 00e6 4020 movs r0, #64 + 1930 00e8 FFF7FEFF bl SX1272ReadBuffer + 1931 .LVL239: + 1932 .LBE441: + 1933 .LBE440: + 963:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1934 .loc 1 963 0 + 1935 00ec 0022 movs r2, #0 + 1936 00ee A256 ldrsb r2, [r4, r2] + 1937 00f0 3323 movs r3, #51 + 1938 00f2 1340 ands r3, r2 + 1939 00f4 4022 movs r2, #64 + 1940 00f6 1343 orrs r3, r2 + 1941 .LVL240: + 1942 00f8 01A9 add r1, sp, #4 + ARM GAS /tmp/ccwcPdtV.s page 68 + + + 1943 00fa 0B70 strb r3, [r1] + 1944 .LVL241: + 1945 .LBB442: + 1946 .LBB443: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1947 .loc 1 1136 0 + 1948 00fc 0122 movs r2, #1 + 1949 00fe 4020 movs r0, #64 + 1950 0100 FFF7FEFF bl SX1272WriteBuffer + 1951 .LVL242: + 1952 0104 88E7 b .L95 + 1953 .L101: + 1954 0106 C046 .align 2 + 1955 .L100: + 1956 0108 00000000 .word .LANCHOR3 + 1957 010c 00000000 .word .LANCHOR0 + 1958 .LBE443: + 1959 .LBE442: + 1960 .cfi_endproc + 1961 .LFE110: + 1963 .section .text.SX1272StartCad,"ax",%progbits + 1964 .align 1 + 1965 .global SX1272StartCad + 1966 .syntax unified + 1967 .code 16 + 1968 .thumb_func + 1969 .fpu softvfp + 1971 SX1272StartCad: + 1972 .LFB111: + 989:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 1973 .loc 1 989 0 + 1974 .cfi_startproc + 1975 @ args = 0, pretend = 0, frame = 8 + 1976 @ frame_needed = 0, uses_anonymous_args = 0 + 1977 0000 30B5 push {r4, r5, lr} + 1978 .LCFI22: + 1979 .cfi_def_cfa_offset 12 + 1980 .cfi_offset 4, -12 + 1981 .cfi_offset 5, -8 + 1982 .cfi_offset 14, -4 + 1983 0002 83B0 sub sp, sp, #12 + 1984 .LCFI23: + 1985 .cfi_def_cfa_offset 24 + 990:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 1986 .loc 1 990 0 + 1987 0004 114B ldr r3, .L105 + 1988 0006 5B79 ldrb r3, [r3, #5] + 1989 0008 012B cmp r3, #1 + 1990 000a 1CD1 bne .L102 + 1991 .LVL243: + 1992 000c 6B46 mov r3, sp + 1993 000e D91D adds r1, r3, #7 + 1994 0010 FA23 movs r3, #250 + 1995 0012 0B70 strb r3, [r1] + 1996 .LVL244: + 1997 .LBB444: + 1998 .LBB445: + ARM GAS /tmp/ccwcPdtV.s page 69 + + +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 1999 .loc 1 1136 0 + 2000 0014 0122 movs r2, #1 + 2001 0016 1120 movs r0, #17 + 2002 0018 FFF7FEFF bl SX1272WriteBuffer + 2003 .LVL245: + 2004 .LBE445: + 2005 .LBE444: + 2006 .LBB446: + 2007 .LBB447: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2008 .loc 1 1142 0 + 2009 001c 6B46 mov r3, sp + 2010 001e 9C1D adds r4, r3, #6 + 2011 0020 0122 movs r2, #1 + 2012 0022 2100 movs r1, r4 + 2013 0024 4020 movs r0, #64 + 2014 0026 FFF7FEFF bl SX1272ReadBuffer + 2015 .LVL246: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2016 .loc 1 1143 0 + 2017 002a 2378 ldrb r3, [r4] + 2018 .LVL247: + 2019 .LBE447: + 2020 .LBE446: +1010:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2021 .loc 1 1010 0 + 2022 002c 0325 movs r5, #3 + 2023 002e AB43 bics r3, r5 + 2024 .LVL248: + 2025 0030 2370 strb r3, [r4] + 2026 .LVL249: + 2027 .LBB448: + 2028 .LBB449: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2029 .loc 1 1136 0 + 2030 0032 0122 movs r2, #1 + 2031 0034 2100 movs r1, r4 + 2032 0036 4020 movs r0, #64 + 2033 0038 FFF7FEFF bl SX1272WriteBuffer + 2034 .LVL250: + 2035 .LBE449: + 2036 .LBE448: +1012:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RFLR_OPMODE_CAD ); + 2037 .loc 1 1012 0 + 2038 003c 034B ldr r3, .L105 + 2039 003e 1D71 strb r5, [r3, #4] +1013:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2040 .loc 1 1013 0 + 2041 0040 0720 movs r0, #7 + 2042 0042 FFF7FEFF bl SX1272SetOpMode + 2043 .LVL251: + 2044 .L102: +1019:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2045 .loc 1 1019 0 + 2046 0046 03B0 add sp, sp, #12 + 2047 @ sp needed + ARM GAS /tmp/ccwcPdtV.s page 70 + + + 2048 0048 30BD pop {r4, r5, pc} + 2049 .L106: + 2050 004a C046 .align 2 + 2051 .L105: + 2052 004c 00000000 .word .LANCHOR0 + 2053 .cfi_endproc + 2054 .LFE111: + 2056 .section .text.SX1272SetModem,"ax",%progbits + 2057 .align 1 + 2058 .global SX1272SetModem + 2059 .syntax unified + 2060 .code 16 + 2061 .thumb_func + 2062 .fpu softvfp + 2064 SX1272SetModem: + 2065 .LFB116: +1098:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 ) + 2066 .loc 1 1098 0 + 2067 .cfi_startproc + 2068 @ args = 0, pretend = 0, frame = 8 + 2069 @ frame_needed = 0, uses_anonymous_args = 0 + 2070 .LVL252: + 2071 0000 30B5 push {r4, r5, lr} + 2072 .LCFI24: + 2073 .cfi_def_cfa_offset 12 + 2074 .cfi_offset 4, -12 + 2075 .cfi_offset 5, -8 + 2076 .cfi_offset 14, -4 + 2077 0002 83B0 sub sp, sp, #12 + 2078 .LCFI25: + 2079 .cfi_def_cfa_offset 24 + 2080 0004 0400 movs r4, r0 + 2081 .LVL253: + 2082 .LBB450: + 2083 .LBB451: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2084 .loc 1 1142 0 + 2085 0006 6B46 mov r3, sp + 2086 0008 DD1D adds r5, r3, #7 + 2087 000a 0122 movs r2, #1 + 2088 000c 2900 movs r1, r5 + 2089 000e 0120 movs r0, #1 + 2090 .LVL254: + 2091 0010 FFF7FEFF bl SX1272ReadBuffer + 2092 .LVL255: + 2093 .LBE451: + 2094 .LBE450: +1099:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2095 .loc 1 1099 0 + 2096 0014 0023 movs r3, #0 + 2097 0016 EB56 ldrsb r3, [r5, r3] + 2098 0018 002B cmp r3, #0 + 2099 001a 2EDB blt .L113 +1105:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2100 .loc 1 1105 0 + 2101 001c 2A4B ldr r3, .L115 + 2102 001e 0022 movs r2, #0 + ARM GAS /tmp/ccwcPdtV.s page 71 + + + 2103 0020 5A71 strb r2, [r3, #5] + 2104 .L109: +1108:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2105 .loc 1 1108 0 + 2106 0022 294B ldr r3, .L115 + 2107 0024 5B79 ldrb r3, [r3, #5] + 2108 0026 A342 cmp r3, r4 + 2109 0028 25D0 beq .L107 +1113:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 2110 .loc 1 1113 0 + 2111 002a 274B ldr r3, .L115 + 2112 002c 5C71 strb r4, [r3, #5] +1114:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2113 .loc 1 1114 0 + 2114 002e 012C cmp r4, #1 + 2115 0030 27D1 bne .L114 +1125:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_OPMODE, ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RF + 2116 .loc 1 1125 0 + 2117 0032 FFF7FEFF bl SX1272SetSleep + 2118 .LVL256: + 2119 .LBB452: + 2120 .LBB453: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2121 .loc 1 1142 0 + 2122 0036 6B46 mov r3, sp + 2123 0038 DC1D adds r4, r3, #7 + 2124 003a 0122 movs r2, #1 + 2125 003c 2100 movs r1, r4 + 2126 003e 0120 movs r0, #1 + 2127 0040 FFF7FEFF bl SX1272ReadBuffer + 2128 .LVL257: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2129 .loc 1 1143 0 + 2130 0044 2278 ldrb r2, [r4] + 2131 .LVL258: + 2132 .LBE453: + 2133 .LBE452: +1126:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2134 .loc 1 1126 0 + 2135 0046 8023 movs r3, #128 + 2136 0048 5B42 rsbs r3, r3, #0 + 2137 004a 1343 orrs r3, r2 + 2138 .LVL259: + 2139 004c 2370 strb r3, [r4] + 2140 .LVL260: + 2141 .LBB454: + 2142 .LBB455: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2143 .loc 1 1136 0 + 2144 004e 0122 movs r2, #1 + 2145 0050 2100 movs r1, r4 + 2146 0052 0120 movs r0, #1 + 2147 0054 FFF7FEFF bl SX1272WriteBuffer + 2148 .LVL261: + 2149 0058 6B46 mov r3, sp + 2150 005a 991D adds r1, r3, #6 + 2151 005c 0024 movs r4, #0 + ARM GAS /tmp/ccwcPdtV.s page 72 + + + 2152 005e 0C70 strb r4, [r1] + 2153 .LVL262: + 2154 .LBE455: + 2155 .LBE454: + 2156 .LBB456: + 2157 .LBB457: + 2158 0060 0122 movs r2, #1 + 2159 0062 4020 movs r0, #64 + 2160 0064 FFF7FEFF bl SX1272WriteBuffer + 2161 .LVL263: + 2162 0068 6B46 mov r3, sp + 2163 006a 591D adds r1, r3, #5 + 2164 006c 0C70 strb r4, [r1] + 2165 .LVL264: + 2166 .LBE457: + 2167 .LBE456: + 2168 .LBB458: + 2169 .LBB459: + 2170 006e 0122 movs r2, #1 + 2171 0070 4120 movs r0, #65 + 2172 0072 FFF7FEFF bl SX1272WriteBuffer + 2173 .LVL265: + 2174 .L107: + 2175 .LBE459: + 2176 .LBE458: +1132:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2177 .loc 1 1132 0 + 2178 0076 03B0 add sp, sp, #12 + 2179 @ sp needed + 2180 0078 30BD pop {r4, r5, pc} + 2181 .L113: +1101:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2182 .loc 1 1101 0 + 2183 007a 134B ldr r3, .L115 + 2184 007c 0122 movs r2, #1 + 2185 007e 5A71 strb r2, [r3, #5] + 2186 0080 CFE7 b .L109 + 2187 .L114: +1118:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_OPMODE, ( SX1272Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RF + 2188 .loc 1 1118 0 + 2189 0082 FFF7FEFF bl SX1272SetSleep + 2190 .LVL266: + 2191 .LBB460: + 2192 .LBB461: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2193 .loc 1 1142 0 + 2194 0086 6B46 mov r3, sp + 2195 0088 DC1D adds r4, r3, #7 + 2196 008a 0122 movs r2, #1 + 2197 008c 2100 movs r1, r4 + 2198 008e 0120 movs r0, #1 + 2199 0090 FFF7FEFF bl SX1272ReadBuffer + 2200 .LVL267: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2201 .loc 1 1143 0 + 2202 0094 2278 ldrb r2, [r4] + 2203 .LVL268: + ARM GAS /tmp/ccwcPdtV.s page 73 + + + 2204 .LBE461: + 2205 .LBE460: +1119:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2206 .loc 1 1119 0 + 2207 0096 7F23 movs r3, #127 + 2208 0098 1340 ands r3, r2 + 2209 .LVL269: + 2210 009a 01A9 add r1, sp, #4 + 2211 009c 0B70 strb r3, [r1] + 2212 .LVL270: + 2213 .LBB462: + 2214 .LBB463: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2215 .loc 1 1136 0 + 2216 009e 0122 movs r2, #1 + 2217 00a0 0120 movs r0, #1 + 2218 00a2 FFF7FEFF bl SX1272WriteBuffer + 2219 .LVL271: + 2220 00a6 6B46 mov r3, sp + 2221 00a8 D91C adds r1, r3, #3 + 2222 00aa 0023 movs r3, #0 + 2223 00ac 0B70 strb r3, [r1] + 2224 .LVL272: + 2225 .LBE463: + 2226 .LBE462: + 2227 .LBB464: + 2228 .LBB465: + 2229 00ae 0122 movs r2, #1 + 2230 00b0 4020 movs r0, #64 + 2231 00b2 FFF7FEFF bl SX1272WriteBuffer + 2232 .LVL273: + 2233 00b6 6B46 mov r3, sp + 2234 00b8 991C adds r1, r3, #2 + 2235 00ba 3023 movs r3, #48 + 2236 00bc 0B70 strb r3, [r1] + 2237 .LVL274: + 2238 .LBE465: + 2239 .LBE464: + 2240 .LBB466: + 2241 .LBB467: + 2242 00be 0122 movs r2, #1 + 2243 00c0 4120 movs r0, #65 + 2244 00c2 FFF7FEFF bl SX1272WriteBuffer + 2245 .LVL275: + 2246 00c6 D6E7 b .L107 + 2247 .L116: + 2248 .align 2 + 2249 .L115: + 2250 00c8 00000000 .word .LANCHOR0 + 2251 .LBE467: + 2252 .LBE466: + 2253 .cfi_endproc + 2254 .LFE116: + 2256 .section .text.SX1272Init,"ax",%progbits + 2257 .align 1 + 2258 .global SX1272Init + 2259 .syntax unified + ARM GAS /tmp/ccwcPdtV.s page 74 + + + 2260 .code 16 + 2261 .thumb_func + 2262 .fpu softvfp + 2264 SX1272Init: + 2265 .LFB97: + 252:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 2266 .loc 1 252 0 + 2267 .cfi_startproc + 2268 @ args = 0, pretend = 0, frame = 8 + 2269 @ frame_needed = 0, uses_anonymous_args = 0 + 2270 .LVL276: + 2271 0000 70B5 push {r4, r5, r6, lr} + 2272 .LCFI26: + 2273 .cfi_def_cfa_offset 16 + 2274 .cfi_offset 4, -16 + 2275 .cfi_offset 5, -12 + 2276 .cfi_offset 6, -8 + 2277 .cfi_offset 14, -4 + 2278 0002 82B0 sub sp, sp, #8 + 2279 .LCFI27: + 2280 .cfi_def_cfa_offset 24 + 255:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2281 .loc 1 255 0 + 2282 0004 1F4B ldr r3, .L120 + 2283 0006 1860 str r0, [r3] + 258:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerInit( &RxTimeoutTimer, SX1272OnTimeoutIrq ); + 2284 .loc 1 258 0 + 2285 0008 1F4C ldr r4, .L120+4 + 2286 000a 2100 movs r1, r4 + 2287 000c 1F48 ldr r0, .L120+8 + 2288 .LVL277: + 2289 000e FFF7FEFF bl TimerInit + 2290 .LVL278: + 259:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerInit( &RxTimeoutSyncWord, SX1272OnTimeoutIrq ); + 2291 .loc 1 259 0 + 2292 0012 2100 movs r1, r4 + 2293 0014 1E48 ldr r0, .L120+12 + 2294 0016 FFF7FEFF bl TimerInit + 2295 .LVL279: + 260:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2296 .loc 1 260 0 + 2297 001a 2100 movs r1, r4 + 2298 001c 1D48 ldr r0, .L120+16 + 2299 001e FFF7FEFF bl TimerInit + 2300 .LVL280: + 262:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2301 .loc 1 262 0 + 2302 0022 1D4C ldr r4, .L120+20 + 2303 0024 2368 ldr r3, [r4] + 2304 0026 1B68 ldr r3, [r3] + 2305 0028 0120 movs r0, #1 + 2306 002a 9847 blx r3 + 2307 .LVL281: + 264:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2308 .loc 1 264 0 + 2309 002c FFF7FEFF bl SX1272Reset + 2310 .LVL282: + ARM GAS /tmp/ccwcPdtV.s page 75 + + + 266:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2311 .loc 1 266 0 + 2312 0030 0020 movs r0, #0 + 2313 0032 FFF7FEFF bl SX1272SetOpMode + 2314 .LVL283: + 268:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2315 .loc 1 268 0 + 2316 0036 2368 ldr r3, [r4] + 2317 0038 9B68 ldr r3, [r3, #8] + 2318 003a 1848 ldr r0, .L120+24 + 2319 003c 9847 blx r3 + 2320 .LVL284: + 270:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2321 .loc 1 270 0 + 2322 003e 0024 movs r4, #0 + 2323 0040 10E0 b .L118 + 2324 .LVL285: + 2325 .L119: + 272:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); + 2326 .loc 1 272 0 discriminator 3 + 2327 0042 174D ldr r5, .L120+28 + 2328 0044 6600 lsls r6, r4, #1 + 2329 0046 3619 adds r6, r6, r4 + 2330 0048 705D ldrb r0, [r6, r5] + 2331 004a FFF7FEFF bl SX1272SetModem + 2332 .LVL286: + 273:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2333 .loc 1 273 0 discriminator 3 + 2334 004e AD19 adds r5, r5, r6 + 2335 0050 6878 ldrb r0, [r5, #1] + 2336 0052 AB78 ldrb r3, [r5, #2] + 2337 .LVL287: + 2338 0054 6A46 mov r2, sp + 2339 0056 D11D adds r1, r2, #7 + 2340 0058 0B70 strb r3, [r1] + 2341 .LVL288: + 2342 .LBB468: + 2343 .LBB469: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2344 .loc 1 1136 0 discriminator 3 + 2345 005a 0122 movs r2, #1 + 2346 005c FFF7FEFF bl SX1272WriteBuffer + 2347 .LVL289: + 2348 .LBE469: + 2349 .LBE468: + 270:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2350 .loc 1 270 0 discriminator 3 + 2351 0060 0134 adds r4, r4, #1 + 2352 .LVL290: + 2353 0062 E4B2 uxtb r4, r4 + 2354 .LVL291: + 2355 .L118: + 270:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2356 .loc 1 270 0 is_stmt 0 discriminator 1 + 2357 0064 102C cmp r4, #16 + 2358 0066 ECD9 bls .L119 + 276:./Drivers/BSP/Components/sx1272/sx1272.c **** + ARM GAS /tmp/ccwcPdtV.s page 76 + + + 2359 .loc 1 276 0 is_stmt 1 + 2360 0068 0020 movs r0, #0 + 2361 006a FFF7FEFF bl SX1272SetModem + 2362 .LVL292: + 278:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2363 .loc 1 278 0 + 2364 006e 0D4B ldr r3, .L120+32 + 2365 0070 0022 movs r2, #0 + 2366 0072 1A71 strb r2, [r3, #4] + 280:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2367 .loc 1 280 0 + 2368 0074 084B ldr r3, .L120+20 + 2369 0076 1B68 ldr r3, [r3] + 2370 0078 5B68 ldr r3, [r3, #4] + 2371 007a 9847 blx r3 + 2372 .LVL293: + 2373 007c 0230 adds r0, r0, #2 + 281:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2374 .loc 1 281 0 + 2375 007e 02B0 add sp, sp, #8 + 2376 @ sp needed + 2377 .LVL294: + 2378 0080 70BD pop {r4, r5, r6, pc} + 2379 .L121: + 2380 0082 C046 .align 2 + 2381 .L120: + 2382 0084 00000000 .word .LANCHOR5 + 2383 0088 00000000 .word SX1272OnTimeoutIrq + 2384 008c 00000000 .word .LANCHOR3 + 2385 0090 00000000 .word .LANCHOR2 + 2386 0094 00000000 .word .LANCHOR4 + 2387 0098 00000000 .word .LANCHOR1 + 2388 009c 00000000 .word .LANCHOR6 + 2389 00a0 00000000 .word .LANCHOR7 + 2390 00a4 00000000 .word .LANCHOR0 + 2391 .cfi_endproc + 2392 .LFE97: + 2394 .section .text.SX1272IsChannelFree,"ax",%progbits + 2395 .align 1 + 2396 .global SX1272IsChannelFree + 2397 .syntax unified + 2398 .code 16 + 2399 .thumb_func + 2400 .fpu softvfp + 2402 SX1272IsChannelFree: + 2403 .LFB100: + 302:./Drivers/BSP/Components/sx1272/sx1272.c **** bool status = true; + 2404 .loc 1 302 0 + 2405 .cfi_startproc + 2406 @ args = 0, pretend = 0, frame = 0 + 2407 @ frame_needed = 0, uses_anonymous_args = 0 + 2408 .LVL295: + 2409 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 2410 .LCFI28: + 2411 .cfi_def_cfa_offset 24 + 2412 .cfi_offset 3, -24 + 2413 .cfi_offset 4, -20 + ARM GAS /tmp/ccwcPdtV.s page 77 + + + 2414 .cfi_offset 5, -16 + 2415 .cfi_offset 6, -12 + 2416 .cfi_offset 7, -8 + 2417 .cfi_offset 14, -4 + 2418 0002 0400 movs r4, r0 + 2419 0004 0D00 movs r5, r1 + 2420 0006 1700 movs r7, r2 + 2421 0008 1E00 movs r6, r3 + 2422 .LVL296: + 307:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2423 .loc 1 307 0 + 2424 000a FFF7FEFF bl SX1272SetModem + 2425 .LVL297: + 309:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2426 .loc 1 309 0 + 2427 000e 2800 movs r0, r5 + 2428 0010 FFF7FEFF bl SX1272SetChannel + 2429 .LVL298: + 311:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2430 .loc 1 311 0 + 2431 0014 0520 movs r0, #5 + 2432 0016 FFF7FEFF bl SX1272SetOpMode + 2433 .LVL299: + 313:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2434 .loc 1 313 0 + 2435 001a 0120 movs r0, #1 + 2436 001c FFF7FEFF bl DelayMs + 2437 .LVL300: + 315:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2438 .loc 1 315 0 + 2439 0020 FFF7FEFF bl TimerGetCurrentTime + 2440 .LVL301: + 2441 0024 0500 movs r5, r0 + 2442 .LVL302: + 2443 .L123: + 318:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2444 .loc 1 318 0 + 2445 0026 2800 movs r0, r5 + 2446 0028 FFF7FEFF bl TimerGetElapsedTime + 2447 .LVL303: + 2448 002c B042 cmp r0, r6 + 2449 002e 06D2 bcs .L127 + 320:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2450 .loc 1 320 0 + 2451 0030 2000 movs r0, r4 + 2452 0032 FFF7FEFF bl SX1272ReadRssi + 2453 .LVL304: + 322:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2454 .loc 1 322 0 + 2455 0036 B842 cmp r0, r7 + 2456 0038 F5DD ble .L123 + 324:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 2457 .loc 1 324 0 + 2458 003a 0024 movs r4, #0 + 2459 003c 00E0 b .L124 + 2460 .LVL305: + 2461 .L127: + ARM GAS /tmp/ccwcPdtV.s page 78 + + + 303:./Drivers/BSP/Components/sx1272/sx1272.c **** int16_t rssi = 0; + 2462 .loc 1 303 0 + 2463 003e 0124 movs r4, #1 + 2464 .L124: + 2465 .LVL306: + 328:./Drivers/BSP/Components/sx1272/sx1272.c **** return status; + 2466 .loc 1 328 0 + 2467 0040 FFF7FEFF bl SX1272SetSleep + 2468 .LVL307: + 330:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2469 .loc 1 330 0 + 2470 0044 2000 movs r0, r4 + 2471 @ sp needed + 2472 .LVL308: + 2473 .LVL309: + 2474 .LVL310: + 2475 0046 F8BD pop {r3, r4, r5, r6, r7, pc} + 2476 .cfi_endproc + 2477 .LFE100: + 2479 .section .text.SX1272Random,"ax",%progbits + 2480 .align 1 + 2481 .global SX1272Random + 2482 .syntax unified + 2483 .code 16 + 2484 .thumb_func + 2485 .fpu softvfp + 2487 SX1272Random: + 2488 .LFB101: + 333:./Drivers/BSP/Components/sx1272/sx1272.c **** uint8_t i; + 2489 .loc 1 333 0 + 2490 .cfi_startproc + 2491 @ args = 0, pretend = 0, frame = 8 + 2492 @ frame_needed = 0, uses_anonymous_args = 0 + 2493 0000 70B5 push {r4, r5, r6, lr} + 2494 .LCFI29: + 2495 .cfi_def_cfa_offset 16 + 2496 .cfi_offset 4, -16 + 2497 .cfi_offset 5, -12 + 2498 .cfi_offset 6, -8 + 2499 .cfi_offset 14, -4 + 2500 0002 82B0 sub sp, sp, #8 + 2501 .LCFI30: + 2502 .cfi_def_cfa_offset 24 + 2503 .LVL311: + 341:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2504 .loc 1 341 0 + 2505 0004 0120 movs r0, #1 + 2506 0006 FFF7FEFF bl SX1272SetModem + 2507 .LVL312: + 2508 000a 6B46 mov r3, sp + 2509 000c 991D adds r1, r3, #6 + 2510 000e FF23 movs r3, #255 + 2511 0010 0B70 strb r3, [r1] + 2512 .LVL313: + 2513 .LBB470: + 2514 .LBB471: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + ARM GAS /tmp/ccwcPdtV.s page 79 + + + 2515 .loc 1 1136 0 + 2516 0012 0122 movs r2, #1 + 2517 0014 1120 movs r0, #17 + 2518 0016 FFF7FEFF bl SX1272WriteBuffer + 2519 .LVL314: + 2520 .LBE471: + 2521 .LBE470: + 354:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2522 .loc 1 354 0 + 2523 001a 0520 movs r0, #5 + 2524 001c FFF7FEFF bl SX1272SetOpMode + 2525 .LVL315: + 335:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2526 .loc 1 335 0 + 2527 0020 0026 movs r6, #0 + 356:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2528 .loc 1 356 0 + 2529 0022 0024 movs r4, #0 + 2530 0024 10E0 b .L129 + 2531 .LVL316: + 2532 .L130: + 358:./Drivers/BSP/Components/sx1272/sx1272.c **** // Unfiltered RSSI value reading. Only takes the LSB value + 2533 .loc 1 358 0 discriminator 3 + 2534 0026 0120 movs r0, #1 + 2535 0028 FFF7FEFF bl DelayMs + 2536 .LVL317: + 2537 .LBB472: + 2538 .LBB473: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2539 .loc 1 1142 0 discriminator 3 + 2540 002c 6B46 mov r3, sp + 2541 002e DD1D adds r5, r3, #7 + 2542 0030 0122 movs r2, #1 + 2543 0032 2900 movs r1, r5 + 2544 0034 2C20 movs r0, #44 + 2545 0036 FFF7FEFF bl SX1272ReadBuffer + 2546 .LVL318: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2547 .loc 1 1143 0 discriminator 3 + 2548 003a 2A78 ldrb r2, [r5] + 2549 .LVL319: + 2550 .LBE473: + 2551 .LBE472: + 360:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2552 .loc 1 360 0 discriminator 3 + 2553 003c 0123 movs r3, #1 + 2554 003e 1340 ands r3, r2 + 2555 0040 A340 lsls r3, r3, r4 + 2556 0042 1E43 orrs r6, r3 + 2557 .LVL320: + 356:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2558 .loc 1 356 0 discriminator 3 + 2559 0044 0134 adds r4, r4, #1 + 2560 .LVL321: + 2561 0046 E4B2 uxtb r4, r4 + 2562 .LVL322: + 2563 .L129: + ARM GAS /tmp/ccwcPdtV.s page 80 + + + 356:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2564 .loc 1 356 0 is_stmt 0 discriminator 1 + 2565 0048 1F2C cmp r4, #31 + 2566 004a ECD9 bls .L130 + 363:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2567 .loc 1 363 0 is_stmt 1 + 2568 004c FFF7FEFF bl SX1272SetSleep + 2569 .LVL323: + 366:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2570 .loc 1 366 0 + 2571 0050 3000 movs r0, r6 + 2572 0052 02B0 add sp, sp, #8 + 2573 @ sp needed + 2574 .LVL324: + 2575 .LVL325: + 2576 0054 70BD pop {r4, r5, r6, pc} + 2577 .cfi_endproc + 2578 .LFE101: + 2580 .section .text.SX1272SetRxConfig,"ax",%progbits + 2581 .align 1 + 2582 .global SX1272SetRxConfig + 2583 .syntax unified + 2584 .code 16 + 2585 .thumb_func + 2586 .fpu softvfp + 2588 SX1272SetRxConfig: + 2589 .LFB103: + 396:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 2590 .loc 1 396 0 + 2591 .cfi_startproc + 2592 @ args = 40, pretend = 0, frame = 56 + 2593 @ frame_needed = 0, uses_anonymous_args = 0 + 2594 .LVL326: + 2595 0000 F0B5 push {r4, r5, r6, r7, lr} + 2596 .LCFI31: + 2597 .cfi_def_cfa_offset 20 + 2598 .cfi_offset 4, -20 + 2599 .cfi_offset 5, -16 + 2600 .cfi_offset 6, -12 + 2601 .cfi_offset 7, -8 + 2602 .cfi_offset 14, -4 + 2603 0002 DE46 mov lr, fp + 2604 0004 5746 mov r7, r10 + 2605 0006 4E46 mov r6, r9 + 2606 0008 4546 mov r5, r8 + 2607 000a E0B5 push {r5, r6, r7, lr} + 2608 .LCFI32: + 2609 .cfi_def_cfa_offset 36 + 2610 .cfi_offset 8, -36 + 2611 .cfi_offset 9, -32 + 2612 .cfi_offset 10, -28 + 2613 .cfi_offset 11, -24 + 2614 000c 8FB0 sub sp, sp, #60 + 2615 .LCFI33: + 2616 .cfi_def_cfa_offset 96 + 2617 000e 0700 movs r7, r0 + 2618 0010 0C00 movs r4, r1 + ARM GAS /tmp/ccwcPdtV.s page 81 + + + 2619 0012 1500 movs r5, r2 + 2620 0014 0093 str r3, [sp] + 2621 0016 18AB add r3, sp, #96 + 2622 .LVL327: + 2623 0018 04CB ldmia r3!, {r2} + 2624 .LVL328: + 2625 001a 9346 mov fp, r2 + 2626 001c 1B88 ldrh r3, [r3] + 2627 .LVL329: + 2628 001e 9946 mov r9, r3 + 2629 0020 1AAB add r3, sp, #104 + 2630 .LVL330: + 2631 0022 1B88 ldrh r3, [r3] + 2632 .LVL331: + 2633 0024 0493 str r3, [sp, #16] + 2634 0026 1BAB add r3, sp, #108 + 2635 .LVL332: + 2636 0028 1B78 ldrb r3, [r3] + 2637 .LVL333: + 2638 002a 9846 mov r8, r3 + 2639 002c 1CAB add r3, sp, #112 + 2640 .LVL334: + 2641 002e 1B78 ldrb r3, [r3] + 2642 .LVL335: + 2643 0030 9A46 mov r10, r3 + 2644 0032 1DAB add r3, sp, #116 + 2645 .LVL336: + 2646 0034 1E78 ldrb r6, [r3] + 2647 0036 1EAB add r3, sp, #120 + 2648 .LVL337: + 2649 0038 1B78 ldrb r3, [r3] + 2650 .LVL338: + 2651 003a 0693 str r3, [sp, #24] + 2652 003c 1FAB add r3, sp, #124 + 2653 .LVL339: + 2654 003e 1B78 ldrb r3, [r3] + 2655 .LVL340: + 2656 0040 0793 str r3, [sp, #28] + 2657 0042 20AB add r3, sp, #128 + 2658 .LVL341: + 2659 0044 1B78 ldrb r3, [r3] + 2660 .LVL342: + 2661 0046 0293 str r3, [sp, #8] + 2662 0048 21AB add r3, sp, #132 + 2663 .LVL343: + 2664 004a 1B78 ldrb r3, [r3] + 2665 .LVL344: + 2666 004c 0593 str r3, [sp, #20] + 397:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2667 .loc 1 397 0 + 2668 004e FFF7FEFF bl SX1272SetModem + 2669 .LVL345: + 399:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2670 .loc 1 399 0 + 2671 0052 002F cmp r7, #0 + 2672 0054 09D0 beq .L133 + 2673 0056 012F cmp r7, #1 + ARM GAS /tmp/ccwcPdtV.s page 82 + + + 2674 0058 00D1 bne .LCB2580 + 2675 005a E6E0 b .L134 @long jump + 2676 .LCB2580: + 2677 .LVL346: + 2678 .L131: + 530:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2679 .loc 1 530 0 + 2680 005c 0FB0 add sp, sp, #60 + 2681 @ sp needed + 2682 .LVL347: + 2683 005e 3CBC pop {r2, r3, r4, r5} + 2684 0060 9046 mov r8, r2 + 2685 0062 9946 mov r9, r3 + 2686 0064 A246 mov r10, r4 + 2687 0066 AB46 mov fp, r5 + 2688 0068 F0BD pop {r4, r5, r6, r7, pc} + 2689 .LVL348: + 2690 .L133: + 403:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate = datarate; + 2691 .loc 1 403 0 + 2692 006a E64F ldr r7, .L160 + 2693 006c 7C61 str r4, [r7, #20] + 404:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.BandwidthAfc = bandwidthAfc; + 2694 .loc 1 404 0 + 2695 006e FD61 str r5, [r7, #28] + 405:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.FixLen = fixLen; + 2696 .loc 1 405 0 + 2697 0070 5B46 mov r3, fp + 2698 0072 BB61 str r3, [r7, #24] + 406:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PayloadLen = payloadLen; + 2699 .loc 1 406 0 + 2700 0074 2223 movs r3, #34 + 2701 0076 4246 mov r2, r8 + 2702 0078 FA54 strb r2, [r7, r3] + 407:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.CrcOn = crcOn; + 2703 .loc 1 407 0 + 2704 007a 0133 adds r3, r3, #1 + 2705 007c 5246 mov r2, r10 + 2706 007e FA54 strb r2, [r7, r3] + 408:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.IqInverted = iqInverted; + 2707 .loc 1 408 0 + 2708 0080 0133 adds r3, r3, #1 + 2709 0082 FE54 strb r6, [r7, r3] + 409:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.RxContinuous = rxContinuous; + 2710 .loc 1 409 0 + 2711 0084 0133 adds r3, r3, #1 + 2712 0086 6A46 mov r2, sp + 2713 0088 127A ldrb r2, [r2, #8] + 2714 008a FA54 strb r2, [r7, r3] + 410:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PreambleLen = preambleLen; + 2715 .loc 1 410 0 + 2716 008c 0133 adds r3, r3, #1 + 2717 008e 6A46 mov r2, sp + 2718 0090 127D ldrb r2, [r2, #20] + 2719 0092 FA54 strb r2, [r7, r3] + 411:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.RxSingleTimeout = ( uint32_t )( symbTimeout * ( ( 1.0 / ( double )d + 2720 .loc 1 411 0 + ARM GAS /tmp/ccwcPdtV.s page 83 + + + 2721 0094 4B46 mov r3, r9 + 2722 0096 3B84 strh r3, [r7, #32] + 412:./Drivers/BSP/Components/sx1272/sx1272.c **** + 2723 .loc 1 412 0 + 2724 0098 2800 movs r0, r5 + 2725 009a FFF7FEFF bl __aeabi_ui2d + 2726 .LVL349: + 2727 009e 0090 str r0, [sp] + 2728 00a0 0191 str r1, [sp, #4] + 2729 00a2 0200 movs r2, r0 + 2730 00a4 0B00 movs r3, r1 + 2731 00a6 0020 movs r0, #0 + 2732 00a8 D749 ldr r1, .L160+4 + 2733 00aa FFF7FEFF bl __aeabi_ddiv + 2734 .LVL350: + 2735 00ae 0022 movs r2, #0 + 2736 00b0 D64B ldr r3, .L160+8 + 2737 00b2 FFF7FEFF bl __aeabi_dmul + 2738 .LVL351: + 2739 00b6 0290 str r0, [sp, #8] + 2740 00b8 0391 str r1, [sp, #12] + 2741 00ba 0498 ldr r0, [sp, #16] + 2742 00bc FFF7FEFF bl __aeabi_i2d + 2743 .LVL352: + 2744 00c0 029A ldr r2, [sp, #8] + 2745 00c2 039B ldr r3, [sp, #12] + 2746 00c4 FFF7FEFF bl __aeabi_dmul + 2747 .LVL353: + 2748 00c8 0022 movs r2, #0 + 2749 00ca D14B ldr r3, .L160+12 + 2750 00cc FFF7FEFF bl __aeabi_dmul + 2751 .LVL354: + 2752 00d0 FFF7FEFF bl __aeabi_d2uiz + 2753 .LVL355: + 2754 00d4 F862 str r0, [r7, #44] + 414:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); + 2755 .loc 1 414 0 + 2756 00d6 009A ldr r2, [sp] + 2757 00d8 019B ldr r3, [sp, #4] + 2758 00da 0020 movs r0, #0 + 2759 00dc CD49 ldr r1, .L160+16 + 2760 00de FFF7FEFF bl __aeabi_ddiv + 2761 .LVL356: + 2762 00e2 FFF7FEFF bl __aeabi_d2uiz + 2763 .LVL357: + 2764 00e6 85B2 uxth r5, r0 + 2765 .LVL358: + 415:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); + 2766 .loc 1 415 0 + 2767 00e8 2B0A lsrs r3, r5, #8 + 2768 .LVL359: + 2769 00ea 08AA add r2, sp, #32 + 2770 00ec D11D adds r1, r2, #7 + 2771 00ee 0B70 strb r3, [r1] + 2772 .LVL360: + 2773 .LBB474: + 2774 .LBB475: + ARM GAS /tmp/ccwcPdtV.s page 84 + + +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2775 .loc 1 1136 0 + 2776 00f0 0122 movs r2, #1 + 2777 00f2 0220 movs r0, #2 + 2778 00f4 FFF7FEFF bl SX1272WriteBuffer + 2779 .LVL361: + 2780 00f8 08AB add r3, sp, #32 + 2781 00fa 991D adds r1, r3, #6 + 2782 00fc 0D70 strb r5, [r1] + 2783 .LVL362: + 2784 .LBE475: + 2785 .LBE474: + 2786 .LBB476: + 2787 .LBB477: + 2788 00fe 0122 movs r2, #1 + 2789 0100 0320 movs r0, #3 + 2790 0102 FFF7FEFF bl SX1272WriteBuffer + 2791 .LVL363: + 2792 .LBE477: + 2793 .LBE476: + 2794 .LBB478: + 2795 .LBB479: + 378:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2796 .loc 1 378 0 + 2797 0106 0023 movs r3, #0 + 2798 0108 01E0 b .L135 + 2799 .LVL364: + 2800 .L136: + 2801 010a 0133 adds r3, r3, #1 + 2802 .LVL365: + 2803 010c DBB2 uxtb r3, r3 + 2804 .LVL366: + 2805 .L135: + 2806 010e 142B cmp r3, #20 + 2807 0110 16D8 bhi .L139 + 380:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2808 .loc 1 380 0 + 2809 0112 DA00 lsls r2, r3, #3 + 2810 0114 C048 ldr r0, .L160+20 + 2811 0116 1258 ldr r2, [r2, r0] + 2812 0118 9442 cmp r4, r2 + 2813 011a F6D3 bcc .L136 + 2814 011c 5A1C adds r2, r3, #1 + 2815 011e D200 lsls r2, r2, #3 + 2816 0120 1258 ldr r2, [r2, r0] + 2817 0122 9442 cmp r4, r2 + 2818 0124 F1D2 bcs .L136 + 382:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2819 .loc 1 382 0 + 2820 0126 DB00 lsls r3, r3, #3 + 2821 .LVL367: + 2822 0128 C318 adds r3, r0, r3 + 2823 012a 1B79 ldrb r3, [r3, #4] + 2824 .LVL368: + 2825 012c 08AA add r2, sp, #32 + 2826 012e 511D adds r1, r2, #5 + 2827 0130 0B70 strb r3, [r1] + ARM GAS /tmp/ccwcPdtV.s page 85 + + + 2828 .LVL369: + 2829 .LBE479: + 2830 .LBE478: + 2831 .LBB480: + 2832 .LBB481: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2833 .loc 1 1136 0 + 2834 0132 0122 movs r2, #1 + 2835 0134 1220 movs r0, #18 + 2836 0136 FFF7FEFF bl SX1272WriteBuffer + 2837 .LVL370: + 2838 .LBE481: + 2839 .LBE480: + 2840 .LBB482: + 2841 .LBB483: + 378:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2842 .loc 1 378 0 + 2843 013a 0023 movs r3, #0 + 2844 013c 5846 mov r0, fp + 2845 013e 02E0 b .L137 + 2846 .LVL371: + 2847 .L139: + 2848 0140 FEE7 b .L139 + 2849 .LVL372: + 2850 .L140: + 2851 0142 0133 adds r3, r3, #1 + 2852 .LVL373: + 2853 0144 DBB2 uxtb r3, r3 + 2854 .LVL374: + 2855 .L137: + 2856 0146 142B cmp r3, #20 + 2857 0148 31D8 bhi .L144 + 380:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2858 .loc 1 380 0 + 2859 014a D900 lsls r1, r3, #3 + 2860 014c B24C ldr r4, .L160+20 + 2861 014e 0959 ldr r1, [r1, r4] + 2862 0150 8842 cmp r0, r1 + 2863 0152 F6D3 bcc .L140 + 2864 0154 591C adds r1, r3, #1 + 2865 0156 C900 lsls r1, r1, #3 + 2866 0158 0959 ldr r1, [r1, r4] + 2867 015a 8842 cmp r0, r1 + 2868 015c F1D2 bcs .L140 + 382:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2869 .loc 1 382 0 + 2870 015e DA00 lsls r2, r3, #3 + 2871 0160 A318 adds r3, r4, r2 + 2872 .LVL375: + 2873 0162 1B79 ldrb r3, [r3, #4] + 2874 .LVL376: + 2875 0164 09A9 add r1, sp, #36 + 2876 0166 0B70 strb r3, [r1] + 2877 .LVL377: + 2878 .LBE483: + 2879 .LBE482: + 2880 .LBB484: + ARM GAS /tmp/ccwcPdtV.s page 86 + + + 2881 .LBB485: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2882 .loc 1 1136 0 + 2883 0168 0122 movs r2, #1 + 2884 016a 1320 movs r0, #19 + 2885 016c FFF7FEFF bl SX1272WriteBuffer + 2886 .LVL378: + 2887 .LBE485: + 2888 .LBE484: + 421:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); + 2889 .loc 1 421 0 + 2890 0170 4B46 mov r3, r9 + 2891 0172 1B0A lsrs r3, r3, #8 + 2892 .LVL379: + 2893 0174 08AA add r2, sp, #32 + 2894 0176 D11C adds r1, r2, #3 + 2895 0178 0B70 strb r3, [r1] + 2896 .LVL380: + 2897 .LBB486: + 2898 .LBB487: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 2899 .loc 1 1136 0 + 2900 017a 0122 movs r2, #1 + 2901 017c 2520 movs r0, #37 + 2902 017e FFF7FEFF bl SX1272WriteBuffer + 2903 .LVL381: + 2904 0182 08AB add r3, sp, #32 + 2905 0184 991C adds r1, r3, #2 + 2906 0186 4B46 mov r3, r9 + 2907 0188 0B70 strb r3, [r1] + 2908 .LVL382: + 2909 .LBE487: + 2910 .LBE486: + 2911 .LBB488: + 2912 .LBB489: + 2913 018a 0122 movs r2, #1 + 2914 018c 2620 movs r0, #38 + 2915 018e FFF7FEFF bl SX1272WriteBuffer + 2916 .LVL383: + 2917 .LBE489: + 2918 .LBE488: + 424:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 2919 .loc 1 424 0 + 2920 0192 4346 mov r3, r8 + 2921 0194 002B cmp r3, #0 + 2922 0196 0BD1 bne .L141 + 2923 .LVL384: + 2924 0198 0921 movs r1, #9 + 2925 019a 08AB add r3, sp, #32 + 2926 019c 9C46 mov ip, r3 + 2927 019e 6144 add r1, r1, ip + 2928 01a0 FF23 movs r3, #255 + 2929 01a2 0B70 strb r3, [r1] + 2930 .LVL385: + 2931 .LBB490: + 2932 .LBB491: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + ARM GAS /tmp/ccwcPdtV.s page 87 + + + 2933 .loc 1 1136 0 + 2934 01a4 0122 movs r2, #1 + 2935 01a6 3220 movs r0, #50 + 2936 01a8 FFF7FEFF bl SX1272WriteBuffer + 2937 .LVL386: + 2938 01ac 07E0 b .L145 + 2939 .LVL387: + 2940 .L144: + 2941 01ae FEE7 b .L144 + 2942 .LVL388: + 2943 .L141: + 2944 01b0 0AA9 add r1, sp, #40 + 2945 01b2 5346 mov r3, r10 + 2946 01b4 0B70 strb r3, [r1] + 2947 .LVL389: + 2948 .LBE491: + 2949 .LBE490: + 2950 .LBB492: + 2951 .LBB493: + 2952 01b6 0122 movs r2, #1 + 2953 01b8 3220 movs r0, #50 + 2954 01ba FFF7FEFF bl SX1272WriteBuffer + 2955 .LVL390: + 2956 .L145: + 2957 .LBE493: + 2958 .LBE492: + 2959 .LBB494: + 2960 .LBB495: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 2961 .loc 1 1142 0 + 2962 01be 1724 movs r4, #23 + 2963 01c0 08AB add r3, sp, #32 + 2964 01c2 9C46 mov ip, r3 + 2965 01c4 6444 add r4, r4, ip + 2966 01c6 0122 movs r2, #1 + 2967 01c8 2100 movs r1, r4 + 2968 01ca 3020 movs r0, #48 + 2969 01cc FFF7FEFF bl SX1272ReadBuffer + 2970 .LVL391: + 2971 .LBE495: + 2972 .LBE494: + 434:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_CRC_MASK & + 2973 .loc 1 434 0 + 2974 01d0 0023 movs r3, #0 + 2975 01d2 E356 ldrsb r3, [r4, r3] + 435:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | + 2976 .loc 1 435 0 + 2977 01d4 6F22 movs r2, #111 + 2978 01d6 1340 ands r3, r2 + 436:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 2979 .loc 1 436 0 + 2980 01d8 4246 mov r2, r8 + 2981 01da 002A cmp r2, #0 + 2982 01dc 22D0 beq .L155 + 2983 01de 0022 movs r2, #0 + 2984 .L146: + 436:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + ARM GAS /tmp/ccwcPdtV.s page 88 + + + 2985 .loc 1 436 0 is_stmt 0 discriminator 4 + 2986 01e0 1343 orrs r3, r2 + 438:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG2, ( SX1272Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DA + 2987 .loc 1 438 0 is_stmt 1 discriminator 4 + 2988 01e2 3601 lsls r6, r6, #4 + 437:./Drivers/BSP/Components/sx1272/sx1272.c **** ( crcOn << 4 ) ); + 2989 .loc 1 437 0 discriminator 4 + 2990 01e4 1E43 orrs r6, r3 + 2991 .LVL392: + 2992 01e6 0B21 movs r1, #11 + 2993 01e8 08AB add r3, sp, #32 + 2994 01ea 9C46 mov ip, r3 + 2995 01ec 6144 add r1, r1, ip + 2996 01ee 0E70 strb r6, [r1] + 2997 .LVL393: + 2998 .LBB496: + 2999 .LBB497: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3000 .loc 1 1136 0 discriminator 4 + 3001 01f0 0122 movs r2, #1 + 3002 01f2 3020 movs r0, #48 + 3003 01f4 FFF7FEFF bl SX1272WriteBuffer + 3004 .LVL394: + 3005 .LBE497: + 3006 .LBE496: + 3007 .LBB498: + 3008 .LBB499: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3009 .loc 1 1142 0 discriminator 4 + 3010 01f8 1724 movs r4, #23 + 3011 01fa 08AB add r3, sp, #32 + 3012 01fc 9C46 mov ip, r3 + 3013 01fe 6444 add r4, r4, ip + 3014 0200 0122 movs r2, #1 + 3015 0202 2100 movs r1, r4 + 3016 0204 3120 movs r0, #49 + 3017 0206 FFF7FEFF bl SX1272ReadBuffer + 3018 .LVL395: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3019 .loc 1 1143 0 discriminator 4 + 3020 020a 2278 ldrb r2, [r4] + 3021 .LVL396: + 3022 .LBE499: + 3023 .LBE498: + 439:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3024 .loc 1 439 0 discriminator 4 + 3025 020c 4023 movs r3, #64 + 3026 020e 1343 orrs r3, r2 + 3027 .LVL397: + 3028 0210 0A21 movs r1, #10 + 3029 0212 08AA add r2, sp, #32 + 3030 0214 9446 mov ip, r2 + 3031 0216 6144 add r1, r1, ip + 3032 0218 0B70 strb r3, [r1] + 3033 .LVL398: + 3034 .LBB500: + 3035 .LBB501: + ARM GAS /tmp/ccwcPdtV.s page 89 + + +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3036 .loc 1 1136 0 discriminator 4 + 3037 021a 0122 movs r2, #1 + 3038 021c 3120 movs r0, #49 + 3039 021e FFF7FEFF bl SX1272WriteBuffer + 3040 .LVL399: + 3041 0222 1BE7 b .L131 + 3042 .LVL400: + 3043 .L155: + 3044 .LBE501: + 3045 .LBE500: + 436:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 3046 .loc 1 436 0 + 3047 0224 8022 movs r2, #128 + 3048 0226 5242 rsbs r2, r2, #0 + 3049 0228 DAE7 b .L146 + 3050 .LVL401: + 3051 .L134: + 444:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Datarate = datarate; + 3052 .loc 1 444 0 + 3053 022a 764B ldr r3, .L160 + 3054 022c 5C64 str r4, [r3, #68] + 445:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Coderate = coderate; + 3055 .loc 1 445 0 + 3056 022e 9D64 str r5, [r3, #72] + 446:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PreambleLen = preambleLen; + 3057 .loc 1 446 0 + 3058 0230 4D22 movs r2, #77 + 3059 0232 6946 mov r1, sp + 3060 0234 0978 ldrb r1, [r1] + 3061 0236 9954 strb r1, [r3, r2] + 447:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FixLen = fixLen; + 3062 .loc 1 447 0 + 3063 0238 0132 adds r2, r2, #1 + 3064 023a 4946 mov r1, r9 + 3065 023c 9952 strh r1, [r3, r2] + 448:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PayloadLen = payloadLen; + 3066 .loc 1 448 0 + 3067 023e 0232 adds r2, r2, #2 + 3068 0240 4146 mov r1, r8 + 3069 0242 9954 strb r1, [r3, r2] + 449:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.CrcOn = crcOn; + 3070 .loc 1 449 0 + 3071 0244 0132 adds r2, r2, #1 + 3072 0246 5146 mov r1, r10 + 3073 0248 9954 strb r1, [r3, r2] + 450:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FreqHopOn = freqHopOn; + 3074 .loc 1 450 0 + 3075 024a 0132 adds r2, r2, #1 + 3076 024c 9E54 strb r6, [r3, r2] + 451:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.HopPeriod = hopPeriod; + 3077 .loc 1 451 0 + 3078 024e 0132 adds r2, r2, #1 + 3079 0250 6946 mov r1, sp + 3080 0252 097E ldrb r1, [r1, #24] + 3081 0254 9954 strb r1, [r3, r2] + 452:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.IqInverted = iqInverted; + ARM GAS /tmp/ccwcPdtV.s page 90 + + + 3082 .loc 1 452 0 + 3083 0256 0132 adds r2, r2, #1 + 3084 0258 6946 mov r1, sp + 3085 025a 097F ldrb r1, [r1, #28] + 3086 025c 9954 strb r1, [r3, r2] + 453:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.RxContinuous = rxContinuous; + 3087 .loc 1 453 0 + 3088 025e 0132 adds r2, r2, #1 + 3089 0260 6946 mov r1, sp + 3090 0262 097A ldrb r1, [r1, #8] + 3091 0264 9954 strb r1, [r3, r2] + 454:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3092 .loc 1 454 0 + 3093 0266 0132 adds r2, r2, #1 + 3094 0268 6946 mov r1, sp + 3095 026a 097D ldrb r1, [r1, #20] + 3096 026c 9954 strb r1, [r3, r2] + 456:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3097 .loc 1 456 0 + 3098 026e 0C2D cmp r5, #12 + 3099 0270 00D9 bls .LCB3024 + 3100 0272 BAE0 b .L156 @long jump + 3101 .LCB3024: + 460:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3102 .loc 1 460 0 + 3103 0274 052D cmp r5, #5 + 3104 0276 00D8 bhi .LCB3028 + 3105 0278 B9E0 b .L157 @long jump + 3106 .LCB3028: + 3107 .LVL402: + 3108 .L147: + 465:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3109 .loc 1 465 0 + 3110 027a 002C cmp r4, #0 + 3111 027c 04D1 bne .L148 + 465:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3112 .loc 1 465 0 is_stmt 0 discriminator 1 + 3113 027e 2B00 movs r3, r5 + 3114 0280 0B3B subs r3, r3, #11 + 3115 0282 012B cmp r3, #1 + 3116 0284 00D8 bhi .LCB3037 + 3117 0286 B7E0 b .L149 @long jump + 3118 .LCB3037: + 3119 .L148: + 465:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3120 .loc 1 465 0 discriminator 3 + 3121 0288 012C cmp r4, #1 + 3122 028a 00D1 bne .LCB3040 + 3123 028c B1E0 b .L159 @long jump + 3124 .LCB3040: + 3125 .L150: + 472:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3126 .loc 1 472 0 is_stmt 1 + 3127 028e 5D4A ldr r2, .L160 + 3128 0290 4C23 movs r3, #76 + 3129 0292 0021 movs r1, #0 + 3130 0294 D154 strb r1, [r2, r3] + ARM GAS /tmp/ccwcPdtV.s page 91 + + + 3131 .L151: + 3132 .LVL403: + 3133 .LBB502: + 3134 .LBB503: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3135 .loc 1 1142 0 + 3136 0296 1727 movs r7, #23 + 3137 0298 08AB add r3, sp, #32 + 3138 029a 9C46 mov ip, r3 + 3139 029c 6744 add r7, r7, ip + 3140 029e 0122 movs r2, #1 + 3141 02a0 3900 movs r1, r7 + 3142 02a2 1D20 movs r0, #29 + 3143 02a4 FFF7FEFF bl SX1272ReadBuffer + 3144 .LVL404: + 3145 .LBE503: + 3146 .LBE502: + 482:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 3147 .loc 1 482 0 + 3148 02a8 A301 lsls r3, r4, #6 + 3149 02aa DBB2 uxtb r3, r3 + 3150 02ac 009A ldr r2, [sp] + 3151 02ae D200 lsls r2, r2, #3 + 3152 02b0 D2B2 uxtb r2, r2 + 3153 02b2 1343 orrs r3, r2 + 483:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3154 .loc 1 483 0 + 3155 02b4 4246 mov r2, r8 + 3156 02b6 9200 lsls r2, r2, #2 + 3157 02b8 D2B2 uxtb r2, r2 + 482:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 3158 .loc 1 482 0 + 3159 02ba 1343 orrs r3, r2 + 483:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3160 .loc 1 483 0 + 3161 02bc 7600 lsls r6, r6, #1 + 3162 02be F6B2 uxtb r6, r6 + 3163 02c0 3343 orrs r3, r6 + 484:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3164 .loc 1 484 0 + 3165 02c2 5049 ldr r1, .L160 + 3166 02c4 4C22 movs r2, #76 + 3167 02c6 8A5C ldrb r2, [r1, r2] + 483:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3168 .loc 1 483 0 + 3169 02c8 1343 orrs r3, r2 + 3170 .LVL405: + 3171 02ca 0CA9 add r1, sp, #48 + 3172 02cc 0B70 strb r3, [r1] + 3173 .LVL406: + 3174 .LBB504: + 3175 .LBB505: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3176 .loc 1 1136 0 + 3177 02ce 0122 movs r2, #1 + 3178 02d0 1D20 movs r0, #29 + 3179 02d2 FFF7FEFF bl SX1272WriteBuffer + ARM GAS /tmp/ccwcPdtV.s page 92 + + + 3180 .LVL407: + 3181 .LBE505: + 3182 .LBE504: + 3183 .LBB506: + 3184 .LBB507: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3185 .loc 1 1142 0 + 3186 02d6 0122 movs r2, #1 + 3187 02d8 3900 movs r1, r7 + 3188 02da 1E20 movs r0, #30 + 3189 02dc FFF7FEFF bl SX1272ReadBuffer + 3190 .LVL408: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3191 .loc 1 1143 0 + 3192 02e0 3A78 ldrb r2, [r7] + 3193 .LVL409: + 3194 .LBE507: + 3195 .LBE506: + 488:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | + 3196 .loc 1 488 0 + 3197 02e2 0C23 movs r3, #12 + 3198 02e4 1340 ands r3, r2 + 490:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); + 3199 .loc 1 490 0 + 3200 02e6 2A01 lsls r2, r5, #4 + 3201 02e8 D2B2 uxtb r2, r2 + 489:./Drivers/BSP/Components/sx1272/sx1272.c **** ( datarate << 4 ) | + 3202 .loc 1 489 0 + 3203 02ea 1343 orrs r3, r2 + 491:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3204 .loc 1 491 0 + 3205 02ec 049C ldr r4, [sp, #16] + 3206 .LVL410: + 3207 02ee 210A lsrs r1, r4, #8 + 3208 02f0 0322 movs r2, #3 + 3209 02f2 0A40 ands r2, r1 + 486:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG2 ) & + 3210 .loc 1 486 0 + 3211 02f4 1343 orrs r3, r2 + 3212 .LVL411: + 3213 02f6 0F21 movs r1, #15 + 3214 02f8 08AA add r2, sp, #32 + 3215 02fa 9446 mov ip, r2 + 3216 02fc 6144 add r1, r1, ip + 3217 02fe 0B70 strb r3, [r1] + 3218 .LVL412: + 3219 .LBB508: + 3220 .LBB509: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3221 .loc 1 1136 0 + 3222 0300 0122 movs r2, #1 + 3223 0302 1E20 movs r0, #30 + 3224 0304 FFF7FEFF bl SX1272WriteBuffer + 3225 .LVL413: + 3226 0308 0E21 movs r1, #14 + 3227 030a 08AB add r3, sp, #32 + 3228 030c 9C46 mov ip, r3 + ARM GAS /tmp/ccwcPdtV.s page 93 + + + 3229 030e 6144 add r1, r1, ip + 3230 0310 0C70 strb r4, [r1] + 3231 .LVL414: + 3232 .LBE509: + 3233 .LBE508: + 3234 .LBB510: + 3235 .LBB511: + 3236 0312 0122 movs r2, #1 + 3237 0314 1F20 movs r0, #31 + 3238 0316 FFF7FEFF bl SX1272WriteBuffer + 3239 .LVL415: + 3240 .LBE511: + 3241 .LBE510: + 495:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); + 3242 .loc 1 495 0 + 3243 031a 4B46 mov r3, r9 + 3244 031c 1B0A lsrs r3, r3, #8 + 3245 .LVL416: + 3246 031e 0D21 movs r1, #13 + 3247 0320 08AA add r2, sp, #32 + 3248 0322 9446 mov ip, r2 + 3249 0324 6144 add r1, r1, ip + 3250 0326 0B70 strb r3, [r1] + 3251 .LVL417: + 3252 .LBB512: + 3253 .LBB513: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3254 .loc 1 1136 0 + 3255 0328 0122 movs r2, #1 + 3256 032a 2020 movs r0, #32 + 3257 032c FFF7FEFF bl SX1272WriteBuffer + 3258 .LVL418: + 3259 0330 0BA9 add r1, sp, #44 + 3260 0332 4B46 mov r3, r9 + 3261 0334 0B70 strb r3, [r1] + 3262 .LVL419: + 3263 .LBE513: + 3264 .LBE512: + 3265 .LBB514: + 3266 .LBB515: + 3267 0336 0122 movs r2, #1 + 3268 0338 2120 movs r0, #33 + 3269 033a FFF7FEFF bl SX1272WriteBuffer + 3270 .LVL420: + 3271 .LBE515: + 3272 .LBE514: + 498:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3273 .loc 1 498 0 + 3274 033e 4346 mov r3, r8 + 3275 0340 002B cmp r3, #0 + 3276 0342 09D0 beq .L152 + 3277 .LVL421: + 3278 0344 1121 movs r1, #17 + 3279 0346 08AB add r3, sp, #32 + 3280 0348 9C46 mov ip, r3 + 3281 034a 6144 add r1, r1, ip + 3282 034c 5346 mov r3, r10 + ARM GAS /tmp/ccwcPdtV.s page 94 + + + 3283 034e 0B70 strb r3, [r1] + 3284 .LVL422: + 3285 .LBB516: + 3286 .LBB517: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3287 .loc 1 1136 0 + 3288 0350 0122 movs r2, #1 + 3289 0352 2220 movs r0, #34 + 3290 0354 FFF7FEFF bl SX1272WriteBuffer + 3291 .LVL423: + 3292 .L152: + 3293 .LBE517: + 3294 .LBE516: + 503:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3295 .loc 1 503 0 + 3296 0358 2A4A ldr r2, .L160 + 3297 035a 5323 movs r3, #83 + 3298 035c D35C ldrb r3, [r2, r3] + 3299 035e 002B cmp r3, #0 + 3300 0360 21D0 beq .L153 + 3301 .LVL424: + 3302 .LBB518: + 3303 .LBB519: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3304 .loc 1 1142 0 + 3305 0362 1724 movs r4, #23 + 3306 0364 08AB add r3, sp, #32 + 3307 0366 9C46 mov ip, r3 + 3308 0368 6444 add r4, r4, ip + 3309 036a 0122 movs r2, #1 + 3310 036c 2100 movs r1, r4 + 3311 036e 4B20 movs r0, #75 + 3312 0370 FFF7FEFF bl SX1272ReadBuffer + 3313 .LVL425: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3314 .loc 1 1143 0 + 3315 0374 2278 ldrb r2, [r4] + 3316 .LVL426: + 3317 .LBE519: + 3318 .LBE518: + 505:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_HOPPERIOD, SX1272.Settings.LoRa.HopPeriod ); + 3319 .loc 1 505 0 + 3320 0376 8023 movs r3, #128 + 3321 0378 5B42 rsbs r3, r3, #0 + 3322 037a 1343 orrs r3, r2 + 3323 .LVL427: + 3324 037c 1321 movs r1, #19 + 3325 037e 08AA add r2, sp, #32 + 3326 0380 9446 mov ip, r2 + 3327 0382 6144 add r1, r1, ip + 3328 0384 0B70 strb r3, [r1] + 3329 .LVL428: + 3330 .LBB520: + 3331 .LBB521: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3332 .loc 1 1136 0 + 3333 0386 0122 movs r2, #1 + ARM GAS /tmp/ccwcPdtV.s page 95 + + + 3334 0388 4B20 movs r0, #75 + 3335 038a FFF7FEFF bl SX1272WriteBuffer + 3336 .LVL429: + 3337 .LBE521: + 3338 .LBE520: + 506:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3339 .loc 1 506 0 + 3340 038e 1D4A ldr r2, .L160 + 3341 0390 5423 movs r3, #84 + 3342 0392 D35C ldrb r3, [r2, r3] + 3343 .LVL430: + 3344 0394 1221 movs r1, #18 + 3345 0396 08AA add r2, sp, #32 + 3346 0398 9446 mov ip, r2 + 3347 039a 6144 add r1, r1, ip + 3348 039c 0B70 strb r3, [r1] + 3349 .LVL431: + 3350 .LBB522: + 3351 .LBB523: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3352 .loc 1 1136 0 + 3353 039e 0122 movs r2, #1 + 3354 03a0 2420 movs r0, #36 + 3355 03a2 FFF7FEFF bl SX1272WriteBuffer + 3356 .LVL432: + 3357 .L153: + 3358 .LBE523: + 3359 .LBE522: + 509:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3360 .loc 1 509 0 + 3361 03a6 062D cmp r5, #6 + 3362 03a8 38D1 bne .L154 + 3363 .LVL433: + 3364 .LBB524: + 3365 .LBB525: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3366 .loc 1 1142 0 + 3367 03aa 1724 movs r4, #23 + 3368 03ac 08AB add r3, sp, #32 + 3369 03ae 9C46 mov ip, r3 + 3370 03b0 6444 add r4, r4, ip + 3371 03b2 0122 movs r2, #1 + 3372 03b4 2100 movs r1, r4 + 3373 03b6 3120 movs r0, #49 + 3374 03b8 FFF7FEFF bl SX1272ReadBuffer + 3375 .LVL434: + 3376 .LBE525: + 3377 .LBE524: + 512:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 3378 .loc 1 512 0 + 3379 03bc 0023 movs r3, #0 + 3380 03be E356 ldrsb r3, [r4, r3] + 3381 03c0 0722 movs r2, #7 + 3382 03c2 9343 bics r3, r2 + 513:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF6 ); + 3383 .loc 1 513 0 + 3384 03c4 0522 movs r2, #5 + ARM GAS /tmp/ccwcPdtV.s page 96 + + + 3385 03c6 1343 orrs r3, r2 + 3386 .LVL435: + 3387 03c8 1521 movs r1, #21 + 3388 03ca 08AA add r2, sp, #32 + 3389 03cc 9446 mov ip, r2 + 3390 03ce 6144 add r1, r1, ip + 3391 03d0 0B70 strb r3, [r1] + 3392 .LVL436: + 3393 .LBB526: + 3394 .LBB527: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3395 .loc 1 1136 0 + 3396 03d2 0122 movs r2, #1 + 3397 03d4 3120 movs r0, #49 + 3398 03d6 FFF7FEFF bl SX1272WriteBuffer + 3399 .LVL437: + 3400 03da 0DA9 add r1, sp, #52 + 3401 03dc 0C23 movs r3, #12 + 3402 03de 0B70 strb r3, [r1] + 3403 .LVL438: + 3404 .LBE527: + 3405 .LBE526: + 3406 .LBB528: + 3407 .LBB529: + 3408 03e0 0122 movs r2, #1 + 3409 03e2 3720 movs r0, #55 + 3410 03e4 FFF7FEFF bl SX1272WriteBuffer + 3411 .LVL439: + 3412 03e8 38E6 b .L131 + 3413 .LVL440: + 3414 .L156: + 3415 .LBE529: + 3416 .LBE528: + 458:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3417 .loc 1 458 0 + 3418 03ea 0C25 movs r5, #12 + 3419 .LVL441: + 3420 03ec 45E7 b .L147 + 3421 .LVL442: + 3422 .L157: + 462:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3423 .loc 1 462 0 + 3424 03ee 0625 movs r5, #6 + 3425 .LVL443: + 3426 03f0 43E7 b .L147 + 3427 .LVL444: + 3428 .L159: + 466:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3429 .loc 1 466 0 + 3430 03f2 0C2D cmp r5, #12 + 3431 03f4 00D0 beq .LCB3363 + 3432 03f6 4AE7 b .L150 @long jump + 3433 .LCB3363: + 3434 .L149: + 468:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3435 .loc 1 468 0 + 3436 03f8 024A ldr r2, .L160 + ARM GAS /tmp/ccwcPdtV.s page 97 + + + 3437 03fa 4C23 movs r3, #76 + 3438 03fc 0121 movs r1, #1 + 3439 03fe D154 strb r1, [r2, r3] + 3440 0400 49E7 b .L151 + 3441 .L161: + 3442 0402 C046 .align 2 + 3443 .L160: + 3444 0404 00000000 .word .LANCHOR0 + 3445 0408 0000F03F .word 1072693248 + 3446 040c 00002040 .word 1075838976 + 3447 0410 00408F40 .word 1083129856 + 3448 0414 80847E41 .word 1098810496 + 3449 0418 00000000 .word FskBandwidths + 3450 .LVL445: + 3451 .L154: + 3452 .LBB530: + 3453 .LBB531: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3454 .loc 1 1142 0 + 3455 041c 1724 movs r4, #23 + 3456 041e 08AB add r3, sp, #32 + 3457 0420 9C46 mov ip, r3 + 3458 0422 6444 add r4, r4, ip + 3459 0424 0122 movs r2, #1 + 3460 0426 2100 movs r1, r4 + 3461 0428 3120 movs r0, #49 + 3462 042a FFF7FEFF bl SX1272ReadBuffer + 3463 .LVL446: + 3464 .LBE531: + 3465 .LBE530: + 521:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 3466 .loc 1 521 0 + 3467 042e 0023 movs r3, #0 + 3468 0430 E356 ldrsb r3, [r4, r3] + 3469 0432 0722 movs r2, #7 + 3470 0434 9343 bics r3, r2 + 522:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); + 3471 .loc 1 522 0 + 3472 0436 0322 movs r2, #3 + 3473 0438 1343 orrs r3, r2 + 3474 .LVL447: + 3475 043a 2370 strb r3, [r4] + 3476 .LVL448: + 3477 .LBB532: + 3478 .LBB533: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3479 .loc 1 1136 0 + 3480 043c 0122 movs r2, #1 + 3481 043e 2100 movs r1, r4 + 3482 0440 3120 movs r0, #49 + 3483 0442 FFF7FEFF bl SX1272WriteBuffer + 3484 .LVL449: + 3485 0446 1621 movs r1, #22 + 3486 0448 08AB add r3, sp, #32 + 3487 044a 9C46 mov ip, r3 + 3488 044c 6144 add r1, r1, ip + 3489 044e 0A23 movs r3, #10 + ARM GAS /tmp/ccwcPdtV.s page 98 + + + 3490 0450 0B70 strb r3, [r1] + 3491 .LVL450: + 3492 .LBE533: + 3493 .LBE532: + 3494 .LBB534: + 3495 .LBB535: + 3496 0452 0122 movs r2, #1 + 3497 0454 3720 movs r0, #55 + 3498 0456 FFF7FEFF bl SX1272WriteBuffer + 3499 .LVL451: + 3500 .LBE535: + 3501 .LBE534: + 530:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3502 .loc 1 530 0 + 3503 045a FFE5 b .L131 + 3504 .cfi_endproc + 3505 .LFE103: + 3507 .section .text.SX1272SetTxConfig,"ax",%progbits + 3508 .align 1 + 3509 .global SX1272SetTxConfig + 3510 .syntax unified + 3511 .code 16 + 3512 .thumb_func + 3513 .fpu softvfp + 3515 SX1272SetTxConfig: + 3516 .LFB104: + 537:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 3517 .loc 1 537 0 + 3518 .cfi_startproc + 3519 @ args = 36, pretend = 0, frame = 40 + 3520 @ frame_needed = 0, uses_anonymous_args = 0 + 3521 .LVL452: + 3522 0000 F0B5 push {r4, r5, r6, r7, lr} + 3523 .LCFI34: + 3524 .cfi_def_cfa_offset 20 + 3525 .cfi_offset 4, -20 + 3526 .cfi_offset 5, -16 + 3527 .cfi_offset 6, -12 + 3528 .cfi_offset 7, -8 + 3529 .cfi_offset 14, -4 + 3530 0002 DE46 mov lr, fp + 3531 0004 5746 mov r7, r10 + 3532 0006 4E46 mov r6, r9 + 3533 0008 4546 mov r5, r8 + 3534 000a E0B5 push {r5, r6, r7, lr} + 3535 .LCFI35: + 3536 .cfi_def_cfa_offset 36 + 3537 .cfi_offset 8, -36 + 3538 .cfi_offset 9, -32 + 3539 .cfi_offset 10, -28 + 3540 .cfi_offset 11, -24 + 3541 000c 8BB0 sub sp, sp, #44 + 3542 .LCFI36: + 3543 .cfi_def_cfa_offset 80 + 3544 000e 0700 movs r7, r0 + 3545 0010 0091 str r1, [sp] + 3546 0012 0292 str r2, [sp, #8] + ARM GAS /tmp/ccwcPdtV.s page 99 + + + 3547 0014 1C00 movs r4, r3 + 3548 0016 14AB add r3, sp, #80 + 3549 .LVL453: + 3550 0018 40CB ldmia r3!, {r6} + 3551 .LVL454: + 3552 001a 1B78 ldrb r3, [r3] + 3553 .LVL455: + 3554 001c 0193 str r3, [sp, #4] + 3555 001e 16AB add r3, sp, #88 + 3556 .LVL456: + 3557 0020 1B88 ldrh r3, [r3] + 3558 .LVL457: + 3559 0022 9946 mov r9, r3 + 3560 0024 17AB add r3, sp, #92 + 3561 .LVL458: + 3562 0026 1B78 ldrb r3, [r3] + 3563 .LVL459: + 3564 0028 9846 mov r8, r3 + 3565 002a 18AB add r3, sp, #96 + 3566 .LVL460: + 3567 002c 1D78 ldrb r5, [r3] + 3568 002e 19AB add r3, sp, #100 + 3569 .LVL461: + 3570 0030 1B78 ldrb r3, [r3] + 3571 .LVL462: + 3572 0032 9A46 mov r10, r3 + 3573 0034 1AAB add r3, sp, #104 + 3574 .LVL463: + 3575 0036 1B78 ldrb r3, [r3] + 3576 .LVL464: + 3577 0038 0393 str r3, [sp, #12] + 3578 003a 1BAB add r3, sp, #108 + 3579 .LVL465: + 3580 003c 1B78 ldrb r3, [r3] + 3581 .LVL466: + 3582 003e 9B46 mov fp, r3 + 538:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3583 .loc 1 538 0 + 3584 0040 FFF7FEFF bl SX1272SetModem + 3585 .LVL467: + 540:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3586 .loc 1 540 0 + 3587 0044 C54B ldr r3, .L181 + 3588 0046 1B68 ldr r3, [r3] + 3589 0048 DB68 ldr r3, [r3, #12] + 3590 004a 0098 ldr r0, [sp] + 3591 004c 9847 blx r3 + 3592 .LVL468: + 542:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3593 .loc 1 542 0 + 3594 004e 002F cmp r7, #0 + 3595 0050 09D0 beq .L164 + 3596 0052 012F cmp r7, #1 + 3597 0054 00D1 bne .LCB3565 + 3598 0056 96E0 b .L165 @long jump + 3599 .LCB3565: + 3600 .LVL469: + ARM GAS /tmp/ccwcPdtV.s page 100 + + + 3601 .L162: + 655:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3602 .loc 1 655 0 + 3603 0058 0BB0 add sp, sp, #44 + 3604 @ sp needed + 3605 005a 3CBC pop {r2, r3, r4, r5} + 3606 005c 9046 mov r8, r2 + 3607 005e 9946 mov r9, r3 + 3608 0060 A246 mov r10, r4 + 3609 0062 AB46 mov fp, r5 + 3610 0064 F0BD pop {r4, r5, r6, r7, pc} + 3611 .LVL470: + 3612 .L164: + 546:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Fdev = fdev; + 3613 .loc 1 546 0 + 3614 0066 BE4B ldr r3, .L181+4 + 3615 0068 6A46 mov r2, sp + 3616 006a 1278 ldrb r2, [r2] + 3617 006c 1A73 strb r2, [r3, #12] + 547:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Bandwidth = bandwidth; + 3618 .loc 1 547 0 + 3619 006e 0298 ldr r0, [sp, #8] + 3620 0070 1861 str r0, [r3, #16] + 548:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.Datarate = datarate; + 3621 .loc 1 548 0 + 3622 0072 5C61 str r4, [r3, #20] + 549:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.PreambleLen = preambleLen; + 3623 .loc 1 549 0 + 3624 0074 DE61 str r6, [r3, #28] + 550:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.FixLen = fixLen; + 3625 .loc 1 550 0 + 3626 0076 4A46 mov r2, r9 + 3627 0078 1A84 strh r2, [r3, #32] + 551:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.CrcOn = crcOn; + 3628 .loc 1 551 0 + 3629 007a 2222 movs r2, #34 + 3630 007c 4146 mov r1, r8 + 3631 007e 9954 strb r1, [r3, r2] + 552:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.IqInverted = iqInverted; + 3632 .loc 1 552 0 + 3633 0080 0232 adds r2, r2, #2 + 3634 0082 9D54 strb r5, [r3, r2] + 553:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.Fsk.TxTimeout = timeout; + 3635 .loc 1 553 0 + 3636 0084 0132 adds r2, r2, #1 + 3637 0086 5946 mov r1, fp + 3638 0088 9954 strb r1, [r3, r2] + 554:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3639 .loc 1 554 0 + 3640 008a 1C9A ldr r2, [sp, #112] + 3641 008c 9A62 str r2, [r3, #40] + 556:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); + 3642 .loc 1 556 0 + 3643 008e FFF7FEFF bl __aeabi_ui2d + 3644 .LVL471: + 3645 0092 0022 movs r2, #0 + 3646 0094 B34B ldr r3, .L181+8 + ARM GAS /tmp/ccwcPdtV.s page 101 + + + 3647 0096 FFF7FEFF bl __aeabi_ddiv + 3648 .LVL472: + 3649 009a FFF7FEFF bl __aeabi_d2uiz + 3650 .LVL473: + 3651 009e 84B2 uxth r4, r0 + 3652 .LVL474: + 557:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); + 3653 .loc 1 557 0 + 3654 00a0 230A lsrs r3, r4, #8 + 3655 .LVL475: + 3656 00a2 0B21 movs r1, #11 + 3657 00a4 04AA add r2, sp, #16 + 3658 00a6 9446 mov ip, r2 + 3659 00a8 6144 add r1, r1, ip + 3660 00aa 0B70 strb r3, [r1] + 3661 .LVL476: + 3662 .LBB536: + 3663 .LBB537: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3664 .loc 1 1136 0 + 3665 00ac 0122 movs r2, #1 + 3666 00ae 0420 movs r0, #4 + 3667 00b0 FFF7FEFF bl SX1272WriteBuffer + 3668 .LVL477: + 3669 00b4 0A21 movs r1, #10 + 3670 00b6 04AB add r3, sp, #16 + 3671 00b8 9C46 mov ip, r3 + 3672 00ba 6144 add r1, r1, ip + 3673 00bc 0C70 strb r4, [r1] + 3674 .LVL478: + 3675 .LBE537: + 3676 .LBE536: + 3677 .LBB538: + 3678 .LBB539: + 3679 00be 0122 movs r2, #1 + 3680 00c0 0520 movs r0, #5 + 3681 00c2 FFF7FEFF bl SX1272WriteBuffer + 3682 .LVL479: + 3683 .LBE539: + 3684 .LBE538: + 560:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); + 3685 .loc 1 560 0 + 3686 00c6 3000 movs r0, r6 + 3687 00c8 FFF7FEFF bl __aeabi_ui2d + 3688 .LVL480: + 3689 00cc 0200 movs r2, r0 + 3690 00ce 0B00 movs r3, r1 + 3691 00d0 0020 movs r0, #0 + 3692 00d2 A549 ldr r1, .L181+12 + 3693 00d4 FFF7FEFF bl __aeabi_ddiv + 3694 .LVL481: + 3695 00d8 FFF7FEFF bl __aeabi_d2uiz + 3696 .LVL482: + 3697 00dc 84B2 uxth r4, r0 + 3698 .LVL483: + 561:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); + 3699 .loc 1 561 0 + ARM GAS /tmp/ccwcPdtV.s page 102 + + + 3700 00de 230A lsrs r3, r4, #8 + 3701 .LVL484: + 3702 00e0 0921 movs r1, #9 + 3703 00e2 04AA add r2, sp, #16 + 3704 00e4 9446 mov ip, r2 + 3705 00e6 6144 add r1, r1, ip + 3706 00e8 0B70 strb r3, [r1] + 3707 .LVL485: + 3708 .LBB540: + 3709 .LBB541: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3710 .loc 1 1136 0 + 3711 00ea 0122 movs r2, #1 + 3712 00ec 0220 movs r0, #2 + 3713 00ee FFF7FEFF bl SX1272WriteBuffer + 3714 .LVL486: + 3715 00f2 06A9 add r1, sp, #24 + 3716 00f4 0C70 strb r4, [r1] + 3717 .LVL487: + 3718 .LBE541: + 3719 .LBE540: + 3720 .LBB542: + 3721 .LBB543: + 3722 00f6 0122 movs r2, #1 + 3723 00f8 0320 movs r0, #3 + 3724 00fa FFF7FEFF bl SX1272WriteBuffer + 3725 .LVL488: + 3726 .LBE543: + 3727 .LBE542: + 564:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PREAMBLELSB, preambleLen & 0xFF ); + 3728 .loc 1 564 0 + 3729 00fe 4B46 mov r3, r9 + 3730 0100 1B0A lsrs r3, r3, #8 + 3731 .LVL489: + 3732 0102 04AA add r2, sp, #16 + 3733 0104 D11D adds r1, r2, #7 + 3734 0106 0B70 strb r3, [r1] + 3735 .LVL490: + 3736 .LBB544: + 3737 .LBB545: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3738 .loc 1 1136 0 + 3739 0108 0122 movs r2, #1 + 3740 010a 2520 movs r0, #37 + 3741 010c FFF7FEFF bl SX1272WriteBuffer + 3742 .LVL491: + 3743 0110 04AB add r3, sp, #16 + 3744 0112 991D adds r1, r3, #6 + 3745 0114 4B46 mov r3, r9 + 3746 0116 0B70 strb r3, [r1] + 3747 .LVL492: + 3748 .LBE545: + 3749 .LBE544: + 3750 .LBB546: + 3751 .LBB547: + 3752 0118 0122 movs r2, #1 + 3753 011a 2620 movs r0, #38 + ARM GAS /tmp/ccwcPdtV.s page 103 + + + 3754 011c FFF7FEFF bl SX1272WriteBuffer + 3755 .LVL493: + 3756 .LBE547: + 3757 .LBE546: + 3758 .LBB548: + 3759 .LBB549: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3760 .loc 1 1142 0 + 3761 0120 1724 movs r4, #23 + 3762 .LVL494: + 3763 0122 04AB add r3, sp, #16 + 3764 0124 9C46 mov ip, r3 + 3765 0126 6444 add r4, r4, ip + 3766 0128 0122 movs r2, #1 + 3767 012a 2100 movs r1, r4 + 3768 012c 3020 movs r0, #48 + 3769 012e FFF7FEFF bl SX1272ReadBuffer + 3770 .LVL495: + 3771 .LBE549: + 3772 .LBE548: + 568:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_CRC_MASK & + 3773 .loc 1 568 0 + 3774 0132 0022 movs r2, #0 + 3775 0134 A256 ldrsb r2, [r4, r2] + 569:./Drivers/BSP/Components/sx1272/sx1272.c **** RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | + 3776 .loc 1 569 0 + 3777 0136 6F23 movs r3, #111 + 3778 0138 1340 ands r3, r2 + 570:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 3779 .loc 1 570 0 + 3780 013a 4246 mov r2, r8 + 3781 013c 002A cmp r2, #0 + 3782 013e 20D1 bne .L177 + 3783 0140 8022 movs r2, #128 + 3784 0142 5242 rsbs r2, r2, #0 + 3785 .L166: + 570:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 3786 .loc 1 570 0 is_stmt 0 discriminator 4 + 3787 0144 1343 orrs r3, r2 + 572:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_PACKETCONFIG2, ( SX1272Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DA + 3788 .loc 1 572 0 is_stmt 1 discriminator 4 + 3789 0146 2D01 lsls r5, r5, #4 + 571:./Drivers/BSP/Components/sx1272/sx1272.c **** ( crcOn << 4 ) ); + 3790 .loc 1 571 0 discriminator 4 + 3791 0148 1D43 orrs r5, r3 + 3792 .LVL496: + 3793 014a 0D21 movs r1, #13 + 3794 014c 04AB add r3, sp, #16 + 3795 014e 9C46 mov ip, r3 + 3796 0150 6144 add r1, r1, ip + 3797 0152 0D70 strb r5, [r1] + 3798 .LVL497: + 3799 .LBB550: + 3800 .LBB551: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3801 .loc 1 1136 0 discriminator 4 + 3802 0154 0122 movs r2, #1 + ARM GAS /tmp/ccwcPdtV.s page 104 + + + 3803 0156 3020 movs r0, #48 + 3804 0158 FFF7FEFF bl SX1272WriteBuffer + 3805 .LVL498: + 3806 .LBE551: + 3807 .LBE550: + 3808 .LBB552: + 3809 .LBB553: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3810 .loc 1 1142 0 discriminator 4 + 3811 015c 1724 movs r4, #23 + 3812 015e 04AB add r3, sp, #16 + 3813 0160 9C46 mov ip, r3 + 3814 0162 6444 add r4, r4, ip + 3815 0164 0122 movs r2, #1 + 3816 0166 2100 movs r1, r4 + 3817 0168 3120 movs r0, #49 + 3818 016a FFF7FEFF bl SX1272ReadBuffer + 3819 .LVL499: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3820 .loc 1 1143 0 discriminator 4 + 3821 016e 2378 ldrb r3, [r4] + 3822 .LVL500: + 3823 .LBE553: + 3824 .LBE552: + 573:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3825 .loc 1 573 0 discriminator 4 + 3826 0170 4022 movs r2, #64 + 3827 0172 1343 orrs r3, r2 + 3828 .LVL501: + 3829 0174 07A9 add r1, sp, #28 + 3830 0176 0B70 strb r3, [r1] + 3831 .LVL502: + 3832 .LBB554: + 3833 .LBB555: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3834 .loc 1 1136 0 discriminator 4 + 3835 0178 0122 movs r2, #1 + 3836 017a 3120 movs r0, #49 + 3837 017c FFF7FEFF bl SX1272WriteBuffer + 3838 .LVL503: + 3839 0180 6AE7 b .L162 + 3840 .LVL504: + 3841 .L177: + 3842 .LBE555: + 3843 .LBE554: + 570:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFI + 3844 .loc 1 570 0 + 3845 0182 0022 movs r2, #0 + 3846 0184 DEE7 b .L166 + 3847 .LVL505: + 3848 .L165: + 578:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Bandwidth = bandwidth; + 3849 .loc 1 578 0 + 3850 0186 764B ldr r3, .L181+4 + 3851 0188 4022 movs r2, #64 + 3852 018a 6946 mov r1, sp + 3853 018c 0978 ldrb r1, [r1] + ARM GAS /tmp/ccwcPdtV.s page 105 + + + 3854 018e 9954 strb r1, [r3, r2] + 579:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Datarate = datarate; + 3855 .loc 1 579 0 + 3856 0190 5C64 str r4, [r3, #68] + 580:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.Coderate = coderate; + 3857 .loc 1 580 0 + 3858 0192 9E64 str r6, [r3, #72] + 581:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PreambleLen = preambleLen; + 3859 .loc 1 581 0 + 3860 0194 0D32 adds r2, r2, #13 + 3861 0196 6946 mov r1, sp + 3862 0198 0979 ldrb r1, [r1, #4] + 3863 019a 9954 strb r1, [r3, r2] + 582:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FixLen = fixLen; + 3864 .loc 1 582 0 + 3865 019c 0132 adds r2, r2, #1 + 3866 019e 4946 mov r1, r9 + 3867 01a0 9952 strh r1, [r3, r2] + 583:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.FreqHopOn = freqHopOn; + 3868 .loc 1 583 0 + 3869 01a2 0232 adds r2, r2, #2 + 3870 01a4 4146 mov r1, r8 + 3871 01a6 9954 strb r1, [r3, r2] + 584:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.HopPeriod = hopPeriod; + 3872 .loc 1 584 0 + 3873 01a8 0332 adds r2, r2, #3 + 3874 01aa 5146 mov r1, r10 + 3875 01ac 9954 strb r1, [r3, r2] + 585:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.CrcOn = crcOn; + 3876 .loc 1 585 0 + 3877 01ae 0132 adds r2, r2, #1 + 3878 01b0 6946 mov r1, sp + 3879 01b2 097B ldrb r1, [r1, #12] + 3880 01b4 9954 strb r1, [r3, r2] + 586:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.IqInverted = iqInverted; + 3881 .loc 1 586 0 + 3882 01b6 023A subs r2, r2, #2 + 3883 01b8 9D54 strb r5, [r3, r2] + 587:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.TxTimeout = timeout; + 3884 .loc 1 587 0 + 3885 01ba 0332 adds r2, r2, #3 + 3886 01bc 5946 mov r1, fp + 3887 01be 9954 strb r1, [r3, r2] + 588:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3888 .loc 1 588 0 + 3889 01c0 1C9A ldr r2, [sp, #112] + 3890 01c2 9A65 str r2, [r3, #88] + 590:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3891 .loc 1 590 0 + 3892 01c4 0C2E cmp r6, #12 + 3893 01c6 03D8 bhi .L175 + 594:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3894 .loc 1 594 0 + 3895 01c8 052E cmp r6, #5 + 3896 01ca 02D8 bhi .L167 + 596:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3897 .loc 1 596 0 + ARM GAS /tmp/ccwcPdtV.s page 106 + + + 3898 01cc 0626 movs r6, #6 + 3899 01ce 00E0 b .L167 + 3900 .L175: + 592:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3901 .loc 1 592 0 + 3902 01d0 0C26 movs r6, #12 + 3903 .L167: + 3904 .LVL506: + 598:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3905 .loc 1 598 0 + 3906 01d2 002C cmp r4, #0 + 3907 01d4 03D1 bne .L168 + 598:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3908 .loc 1 598 0 is_stmt 0 discriminator 1 + 3909 01d6 3300 movs r3, r6 + 3910 01d8 0B3B subs r3, r3, #11 + 3911 01da 012B cmp r3, #1 + 3912 01dc 75D9 bls .L169 + 3913 .L168: + 598:./Drivers/BSP/Components/sx1272/sx1272.c **** ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 3914 .loc 1 598 0 discriminator 3 + 3915 01de 012C cmp r4, #1 + 3916 01e0 71D0 beq .L178 + 3917 .L170: + 605:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3918 .loc 1 605 0 is_stmt 1 + 3919 01e2 5F4A ldr r2, .L181+4 + 3920 01e4 4C23 movs r3, #76 + 3921 01e6 0021 movs r1, #0 + 3922 01e8 D154 strb r1, [r2, r3] + 3923 .L171: + 608:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 3924 .loc 1 608 0 + 3925 01ea 5346 mov r3, r10 + 3926 01ec 002B cmp r3, #0 + 3927 01ee 71D1 bne .L179 + 3928 .L172: + 3929 .LVL507: + 3930 .LBB556: + 3931 .LBB557: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3932 .loc 1 1142 0 + 3933 01f0 1727 movs r7, #23 + 3934 01f2 04AB add r3, sp, #16 + 3935 01f4 9C46 mov ip, r3 + 3936 01f6 6744 add r7, r7, ip + 3937 01f8 0122 movs r2, #1 + 3938 01fa 3900 movs r1, r7 + 3939 01fc 1D20 movs r0, #29 + 3940 01fe FFF7FEFF bl SX1272ReadBuffer + 3941 .LVL508: + 3942 .LBE557: + 3943 .LBE556: + 621:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 3944 .loc 1 621 0 + 3945 0202 A401 lsls r4, r4, #6 + 3946 .LVL509: + ARM GAS /tmp/ccwcPdtV.s page 107 + + + 3947 0204 E4B2 uxtb r4, r4 + 3948 0206 019B ldr r3, [sp, #4] + 3949 0208 DB00 lsls r3, r3, #3 + 3950 020a DBB2 uxtb r3, r3 + 3951 020c 1C43 orrs r4, r3 + 622:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3952 .loc 1 622 0 + 3953 020e 4346 mov r3, r8 + 3954 0210 9B00 lsls r3, r3, #2 + 3955 0212 DBB2 uxtb r3, r3 + 621:./Drivers/BSP/Components/sx1272/sx1272.c **** ( fixLen << 2 ) | ( crcOn << 1 ) | + 3956 .loc 1 621 0 + 3957 0214 1C43 orrs r4, r3 + 622:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3958 .loc 1 622 0 + 3959 0216 6D00 lsls r5, r5, #1 + 3960 0218 EDB2 uxtb r5, r5 + 3961 021a 2543 orrs r5, r4 + 623:./Drivers/BSP/Components/sx1272/sx1272.c **** + 3962 .loc 1 623 0 + 3963 021c 504A ldr r2, .L181+4 + 3964 021e 4C23 movs r3, #76 + 3965 0220 D45C ldrb r4, [r2, r3] + 622:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.LowDatarateOptimize ); + 3966 .loc 1 622 0 + 3967 0222 2543 orrs r5, r4 + 3968 .LVL510: + 3969 0224 1321 movs r1, #19 + 3970 0226 04AB add r3, sp, #16 + 3971 0228 9C46 mov ip, r3 + 3972 022a 6144 add r1, r1, ip + 3973 022c 0D70 strb r5, [r1] + 3974 .LVL511: + 3975 .LBB558: + 3976 .LBB559: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3977 .loc 1 1136 0 + 3978 022e 0122 movs r2, #1 + 3979 0230 1D20 movs r0, #29 + 3980 0232 FFF7FEFF bl SX1272WriteBuffer + 3981 .LVL512: + 3982 .LBE559: + 3983 .LBE558: + 3984 .LBB560: + 3985 .LBB561: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 3986 .loc 1 1142 0 + 3987 0236 0122 movs r2, #1 + 3988 0238 3900 movs r1, r7 + 3989 023a 1E20 movs r0, #30 + 3990 023c FFF7FEFF bl SX1272ReadBuffer + 3991 .LVL513: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 3992 .loc 1 1143 0 + 3993 0240 3A78 ldrb r2, [r7] + 3994 .LVL514: + 3995 .LBE561: + ARM GAS /tmp/ccwcPdtV.s page 108 + + + 3996 .LBE560: + 626:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_MODEMCONFIG2_SF_MASK ) | + 3997 .loc 1 626 0 + 3998 0242 0F23 movs r3, #15 + 3999 0244 1340 ands r3, r2 + 628:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4000 .loc 1 628 0 + 4001 0246 3201 lsls r2, r6, #4 + 4002 0248 D2B2 uxtb r2, r2 + 625:./Drivers/BSP/Components/sx1272/sx1272.c **** ( SX1272Read( REG_LR_MODEMCONFIG2 ) & + 4003 .loc 1 625 0 + 4004 024a 1343 orrs r3, r2 + 4005 .LVL515: + 4006 024c 1221 movs r1, #18 + 4007 024e 04AA add r2, sp, #16 + 4008 0250 9446 mov ip, r2 + 4009 0252 6144 add r1, r1, ip + 4010 0254 0B70 strb r3, [r1] + 4011 .LVL516: + 4012 .LBB562: + 4013 .LBB563: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4014 .loc 1 1136 0 + 4015 0256 0122 movs r2, #1 + 4016 0258 1E20 movs r0, #30 + 4017 025a FFF7FEFF bl SX1272WriteBuffer + 4018 .LVL517: + 4019 .LBE563: + 4020 .LBE562: + 631:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); + 4021 .loc 1 631 0 + 4022 025e 4B46 mov r3, r9 + 4023 0260 1B0A lsrs r3, r3, #8 + 4024 .LVL518: + 4025 0262 1121 movs r1, #17 + 4026 0264 04AA add r2, sp, #16 + 4027 0266 9446 mov ip, r2 + 4028 0268 6144 add r1, r1, ip + 4029 026a 0B70 strb r3, [r1] + 4030 .LVL519: + 4031 .LBB564: + 4032 .LBB565: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4033 .loc 1 1136 0 + 4034 026c 0122 movs r2, #1 + 4035 026e 2020 movs r0, #32 + 4036 0270 FFF7FEFF bl SX1272WriteBuffer + 4037 .LVL520: + 4038 0274 08A9 add r1, sp, #32 + 4039 0276 4B46 mov r3, r9 + 4040 0278 0B70 strb r3, [r1] + 4041 .LVL521: + 4042 .LBE565: + 4043 .LBE564: + 4044 .LBB566: + 4045 .LBB567: + 4046 027a 0122 movs r2, #1 + ARM GAS /tmp/ccwcPdtV.s page 109 + + + 4047 027c 2120 movs r0, #33 + 4048 027e FFF7FEFF bl SX1272WriteBuffer + 4049 .LVL522: + 4050 .LBE567: + 4051 .LBE566: + 634:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4052 .loc 1 634 0 + 4053 0282 062E cmp r6, #6 + 4054 0284 49D0 beq .L180 + 4055 .LVL523: + 4056 .LBB568: + 4057 .LBB569: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4058 .loc 1 1142 0 + 4059 0286 1724 movs r4, #23 + 4060 0288 04AB add r3, sp, #16 + 4061 028a 9C46 mov ip, r3 + 4062 028c 6444 add r4, r4, ip + 4063 028e 0122 movs r2, #1 + 4064 0290 2100 movs r1, r4 + 4065 0292 3120 movs r0, #49 + 4066 0294 FFF7FEFF bl SX1272ReadBuffer + 4067 .LVL524: + 4068 .LBE569: + 4069 .LBE568: + 646:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 4070 .loc 1 646 0 + 4071 0298 0023 movs r3, #0 + 4072 029a E356 ldrsb r3, [r4, r3] + 4073 029c 0722 movs r2, #7 + 4074 029e 9343 bics r3, r2 + 647:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); + 4075 .loc 1 647 0 + 4076 02a0 0322 movs r2, #3 + 4077 02a2 1343 orrs r3, r2 + 4078 .LVL525: + 4079 02a4 2370 strb r3, [r4] + 4080 .LVL526: + 4081 .LBB570: + 4082 .LBB571: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4083 .loc 1 1136 0 + 4084 02a6 0122 movs r2, #1 + 4085 02a8 2100 movs r1, r4 + 4086 02aa 3120 movs r0, #49 + 4087 02ac FFF7FEFF bl SX1272WriteBuffer + 4088 .LVL527: + 4089 02b0 1621 movs r1, #22 + 4090 02b2 04AB add r3, sp, #16 + 4091 02b4 9C46 mov ip, r3 + 4092 02b6 6144 add r1, r1, ip + 4093 02b8 0A23 movs r3, #10 + 4094 02ba 0B70 strb r3, [r1] + 4095 .LVL528: + 4096 .LBE571: + 4097 .LBE570: + 4098 .LBB572: + ARM GAS /tmp/ccwcPdtV.s page 110 + + + 4099 .LBB573: + 4100 02bc 0122 movs r2, #1 + 4101 02be 3720 movs r0, #55 + 4102 02c0 FFF7FEFF bl SX1272WriteBuffer + 4103 .LVL529: + 4104 .LBE573: + 4105 .LBE572: + 655:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4106 .loc 1 655 0 + 4107 02c4 C8E6 b .L162 + 4108 .LVL530: + 4109 .L178: + 599:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4110 .loc 1 599 0 + 4111 02c6 0C2E cmp r6, #12 + 4112 02c8 8BD1 bne .L170 + 4113 .L169: + 601:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4114 .loc 1 601 0 + 4115 02ca 254A ldr r2, .L181+4 + 4116 02cc 4C23 movs r3, #76 + 4117 02ce 0121 movs r1, #1 + 4118 02d0 D154 strb r1, [r2, r3] + 4119 02d2 8AE7 b .L171 + 4120 .L179: + 4121 .LVL531: + 4122 .LBB574: + 4123 .LBB575: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4124 .loc 1 1142 0 + 4125 02d4 1727 movs r7, #23 + 4126 02d6 04AB add r3, sp, #16 + 4127 02d8 9C46 mov ip, r3 + 4128 02da 6744 add r7, r7, ip + 4129 02dc 0122 movs r2, #1 + 4130 02de 3900 movs r1, r7 + 4131 02e0 4B20 movs r0, #75 + 4132 02e2 FFF7FEFF bl SX1272ReadBuffer + 4133 .LVL532: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4134 .loc 1 1143 0 + 4135 02e6 3A78 ldrb r2, [r7] + 4136 .LVL533: + 4137 .LBE575: + 4138 .LBE574: + 610:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_HOPPERIOD, SX1272.Settings.LoRa.HopPeriod ); + 4139 .loc 1 610 0 + 4140 02e8 8023 movs r3, #128 + 4141 02ea 5B42 rsbs r3, r3, #0 + 4142 02ec 1343 orrs r3, r2 + 4143 .LVL534: + 4144 02ee 0F21 movs r1, #15 + 4145 02f0 04AA add r2, sp, #16 + 4146 02f2 9446 mov ip, r2 + 4147 02f4 6144 add r1, r1, ip + 4148 02f6 0B70 strb r3, [r1] + 4149 .LVL535: + ARM GAS /tmp/ccwcPdtV.s page 111 + + + 4150 .LBB576: + 4151 .LBB577: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4152 .loc 1 1136 0 + 4153 02f8 0122 movs r2, #1 + 4154 02fa 4B20 movs r0, #75 + 4155 02fc FFF7FEFF bl SX1272WriteBuffer + 4156 .LVL536: + 4157 .LBE577: + 4158 .LBE576: + 611:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4159 .loc 1 611 0 + 4160 0300 174A ldr r2, .L181+4 + 4161 0302 5423 movs r3, #84 + 4162 0304 D35C ldrb r3, [r2, r3] + 4163 .LVL537: + 4164 0306 0E21 movs r1, #14 + 4165 0308 04AA add r2, sp, #16 + 4166 030a 9446 mov ip, r2 + 4167 030c 6144 add r1, r1, ip + 4168 030e 0B70 strb r3, [r1] + 4169 .LVL538: + 4170 .LBB578: + 4171 .LBB579: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4172 .loc 1 1136 0 + 4173 0310 0122 movs r2, #1 + 4174 0312 2420 movs r0, #36 + 4175 0314 FFF7FEFF bl SX1272WriteBuffer + 4176 .LVL539: + 4177 0318 6AE7 b .L172 + 4178 .LVL540: + 4179 .L180: + 4180 .LBE579: + 4181 .LBE578: + 4182 .LBB580: + 4183 .LBB581: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4184 .loc 1 1142 0 + 4185 031a 1724 movs r4, #23 + 4186 031c 04AB add r3, sp, #16 + 4187 031e 9C46 mov ip, r3 + 4188 0320 6444 add r4, r4, ip + 4189 0322 0122 movs r2, #1 + 4190 0324 2100 movs r1, r4 + 4191 0326 3120 movs r0, #49 + 4192 0328 FFF7FEFF bl SX1272ReadBuffer + 4193 .LVL541: + 4194 .LBE581: + 4195 .LBE580: + 637:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_MASK ) | + 4196 .loc 1 637 0 + 4197 032c 0023 movs r3, #0 + 4198 032e E356 ldrsb r3, [r4, r3] + 4199 0330 0722 movs r2, #7 + 4200 0332 9343 bics r3, r2 + 638:./Drivers/BSP/Components/sx1272/sx1272.c **** RFLR_DETECTIONOPTIMIZE_SF6 ); + ARM GAS /tmp/ccwcPdtV.s page 112 + + + 4201 .loc 1 638 0 + 4202 0334 0522 movs r2, #5 + 4203 0336 1343 orrs r3, r2 + 4204 .LVL542: + 4205 0338 1521 movs r1, #21 + 4206 033a 04AA add r2, sp, #16 + 4207 033c 9446 mov ip, r2 + 4208 033e 6144 add r1, r1, ip + 4209 0340 0B70 strb r3, [r1] + 4210 .LVL543: + 4211 .LBB582: + 4212 .LBB583: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4213 .loc 1 1136 0 + 4214 0342 0122 movs r2, #1 + 4215 0344 3120 movs r0, #49 + 4216 0346 FFF7FEFF bl SX1272WriteBuffer + 4217 .LVL544: + 4218 034a 09A9 add r1, sp, #36 + 4219 034c 0C23 movs r3, #12 + 4220 034e 0B70 strb r3, [r1] + 4221 .LVL545: + 4222 .LBE583: + 4223 .LBE582: + 4224 .LBB584: + 4225 .LBB585: + 4226 0350 0122 movs r2, #1 + 4227 0352 3720 movs r0, #55 + 4228 0354 FFF7FEFF bl SX1272WriteBuffer + 4229 .LVL546: + 4230 0358 7EE6 b .L162 + 4231 .L182: + 4232 035a C046 .align 2 + 4233 .L181: + 4234 035c 00000000 .word .LANCHOR1 + 4235 0360 00000000 .word .LANCHOR0 + 4236 0364 80844E40 .word 1078887552 + 4237 0368 80847E41 .word 1098810496 + 4238 .LBE585: + 4239 .LBE584: + 4240 .cfi_endproc + 4241 .LFE104: + 4243 .section .text.SX1272SetTxContinuousWave,"ax",%progbits + 4244 .align 1 + 4245 .global SX1272SetTxContinuousWave + 4246 .syntax unified + 4247 .code 16 + 4248 .thumb_func + 4249 .fpu softvfp + 4251 SX1272SetTxContinuousWave: + 4252 .LFB112: +1022:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t timeout = ( uint32_t )( time * 1000 ); + 4253 .loc 1 1022 0 + 4254 .cfi_startproc + 4255 @ args = 0, pretend = 0, frame = 8 + 4256 @ frame_needed = 0, uses_anonymous_args = 0 + 4257 .LVL547: + ARM GAS /tmp/ccwcPdtV.s page 113 + + + 4258 0000 30B5 push {r4, r5, lr} + 4259 .LCFI37: + 4260 .cfi_def_cfa_offset 12 + 4261 .cfi_offset 4, -12 + 4262 .cfi_offset 5, -8 + 4263 .cfi_offset 14, -4 + 4264 0002 8DB0 sub sp, sp, #52 + 4265 .LCFI38: + 4266 .cfi_def_cfa_offset 64 + 4267 0004 0C00 movs r4, r1 +1023:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4268 .loc 1 1023 0 + 4269 0006 5301 lsls r3, r2, #5 + 4270 0008 9B1A subs r3, r3, r2 + 4271 000a 9B00 lsls r3, r3, #2 + 4272 000c 9A18 adds r2, r3, r2 + 4273 .LVL548: + 4274 000e D500 lsls r5, r2, #3 + 4275 .LVL549: +1025:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4276 .loc 1 1025 0 + 4277 0010 FFF7FEFF bl SX1272SetChannel + 4278 .LVL550: +1027:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4279 .loc 1 1027 0 + 4280 0014 0895 str r5, [sp, #32] + 4281 0016 0023 movs r3, #0 + 4282 0018 0793 str r3, [sp, #28] + 4283 001a 0693 str r3, [sp, #24] + 4284 001c 0593 str r3, [sp, #20] + 4285 001e 0493 str r3, [sp, #16] + 4286 0020 0393 str r3, [sp, #12] + 4287 0022 0522 movs r2, #5 + 4288 0024 0292 str r2, [sp, #8] + 4289 0026 0193 str r3, [sp, #4] + 4290 0028 9623 movs r3, #150 + 4291 002a 5B01 lsls r3, r3, #5 + 4292 002c 0093 str r3, [sp] + 4293 002e 0023 movs r3, #0 + 4294 0030 0022 movs r2, #0 + 4295 0032 2100 movs r1, r4 + 4296 0034 0020 movs r0, #0 + 4297 0036 FFF7FEFF bl SX1272SetTxConfig + 4298 .LVL551: + 4299 .LBB586: + 4300 .LBB587: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4301 .loc 1 1142 0 + 4302 003a 2F24 movs r4, #47 + 4303 003c 6C44 add r4, r4, sp + 4304 003e 0122 movs r2, #1 + 4305 0040 2100 movs r1, r4 + 4306 0042 3120 movs r0, #49 + 4307 0044 FFF7FEFF bl SX1272ReadBuffer + 4308 .LVL552: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4309 .loc 1 1143 0 + ARM GAS /tmp/ccwcPdtV.s page 114 + + + 4310 0048 2378 ldrb r3, [r4] + 4311 .LVL553: + 4312 .LBE587: + 4313 .LBE586: +1029:./Drivers/BSP/Components/sx1272/sx1272.c **** // Disable radio interrupts + 4314 .loc 1 1029 0 + 4315 004a 4022 movs r2, #64 + 4316 004c 9343 bics r3, r2 + 4317 .LVL554: + 4318 004e 2370 strb r3, [r4] + 4319 .LVL555: + 4320 .LBB588: + 4321 .LBB589: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4322 .loc 1 1136 0 + 4323 0050 3F3A subs r2, r2, #63 + 4324 0052 2100 movs r1, r4 + 4325 0054 3120 movs r0, #49 + 4326 0056 FFF7FEFF bl SX1272WriteBuffer + 4327 .LVL556: + 4328 005a 2E21 movs r1, #46 + 4329 005c 6944 add r1, r1, sp + 4330 005e F023 movs r3, #240 + 4331 0060 0B70 strb r3, [r1] + 4332 .LVL557: + 4333 .LBE589: + 4334 .LBE588: + 4335 .LBB590: + 4336 .LBB591: + 4337 0062 0122 movs r2, #1 + 4338 0064 4020 movs r0, #64 + 4339 0066 FFF7FEFF bl SX1272WriteBuffer + 4340 .LVL558: + 4341 006a 2D21 movs r1, #45 + 4342 006c 6944 add r1, r1, sp + 4343 006e A023 movs r3, #160 + 4344 0070 0B70 strb r3, [r1] + 4345 .LVL559: + 4346 .LBE591: + 4347 .LBE590: + 4348 .LBB592: + 4349 .LBB593: + 4350 0072 0122 movs r2, #1 + 4351 0074 4120 movs r0, #65 + 4352 0076 FFF7FEFF bl SX1272WriteBuffer + 4353 .LVL560: + 4354 .LBE593: + 4355 .LBE592: +1034:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4356 .loc 1 1034 0 + 4357 007a 084C ldr r4, .L184 + 4358 007c 2900 movs r1, r5 + 4359 007e 2000 movs r0, r4 + 4360 0080 FFF7FEFF bl TimerSetValue + 4361 .LVL561: +1036:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &TxTimeoutTimer ); + 4362 .loc 1 1036 0 + ARM GAS /tmp/ccwcPdtV.s page 115 + + + 4363 0084 064B ldr r3, .L184+4 + 4364 0086 0222 movs r2, #2 + 4365 0088 1A71 strb r2, [r3, #4] +1037:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetOpMode( RF_OPMODE_TRANSMITTER ); + 4366 .loc 1 1037 0 + 4367 008a 2000 movs r0, r4 + 4368 008c FFF7FEFF bl TimerStart + 4369 .LVL562: +1038:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4370 .loc 1 1038 0 + 4371 0090 0320 movs r0, #3 + 4372 0092 FFF7FEFF bl SX1272SetOpMode + 4373 .LVL563: +1039:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4374 .loc 1 1039 0 + 4375 0096 0DB0 add sp, sp, #52 + 4376 @ sp needed + 4377 .LVL564: + 4378 0098 30BD pop {r4, r5, pc} + 4379 .L185: + 4380 009a C046 .align 2 + 4381 .L184: + 4382 009c 00000000 .word .LANCHOR3 + 4383 00a0 00000000 .word .LANCHOR0 + 4384 .cfi_endproc + 4385 .LFE112: + 4387 .section .text.SX1272OnDio2Irq,"ax",%progbits + 4388 .align 1 + 4389 .global SX1272OnDio2Irq + 4390 .syntax unified + 4391 .code 16 + 4392 .thumb_func + 4393 .fpu softvfp + 4395 SX1272OnDio2Irq: + 4396 .LFB129: +1569:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t afcChannel = 0; + 4397 .loc 1 1569 0 + 4398 .cfi_startproc + 4399 @ args = 0, pretend = 0, frame = 8 + 4400 @ frame_needed = 0, uses_anonymous_args = 0 + 4401 0000 70B5 push {r4, r5, r6, lr} + 4402 .LCFI39: + 4403 .cfi_def_cfa_offset 16 + 4404 .cfi_offset 4, -16 + 4405 .cfi_offset 5, -12 + 4406 .cfi_offset 6, -8 + 4407 .cfi_offset 14, -4 + 4408 0002 82B0 sub sp, sp, #8 + 4409 .LCFI40: + 4410 .cfi_def_cfa_offset 24 + 4411 .LVL565: +1572:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4412 .loc 1 1572 0 + 4413 0004 4D4B ldr r3, .L193 + 4414 0006 1B79 ldrb r3, [r3, #4] + 4415 0008 012B cmp r3, #1 + 4416 000a 04D0 beq .L188 + ARM GAS /tmp/ccwcPdtV.s page 116 + + + 4417 000c 022B cmp r3, #2 + 4418 000e 00D1 bne .LCB4397 + 4419 0010 6BE0 b .L189 @long jump + 4420 .LCB4397: + 4421 .LVL566: + 4422 .L186: +1639:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4423 .loc 1 1639 0 + 4424 0012 02B0 add sp, sp, #8 + 4425 @ sp needed + 4426 0014 70BD pop {r4, r5, r6, pc} + 4427 .LVL567: + 4428 .L188: +1575:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4429 .loc 1 1575 0 + 4430 0016 494B ldr r3, .L193 + 4431 0018 5B79 ldrb r3, [r3, #5] + 4432 001a 002B cmp r3, #0 + 4433 001c 21D0 beq .L190 + 4434 001e 012B cmp r3, #1 + 4435 0020 F7D1 bne .L186 +1600:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4436 .loc 1 1600 0 + 4437 0022 464A ldr r2, .L193 + 4438 0024 5323 movs r3, #83 + 4439 0026 D35C ldrb r3, [r2, r3] + 4440 0028 002B cmp r3, #0 + 4441 002a F2D0 beq .L186 + 4442 .LVL568: + 4443 002c 6B46 mov r3, sp + 4444 002e 591D adds r1, r3, #5 + 4445 0030 0223 movs r3, #2 + 4446 0032 0B70 strb r3, [r1] + 4447 .LVL569: + 4448 .LBB594: + 4449 .LBB595: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4450 .loc 1 1136 0 + 4451 0034 0122 movs r2, #1 + 4452 0036 1220 movs r0, #18 + 4453 0038 FFF7FEFF bl SX1272WriteBuffer + 4454 .LVL570: + 4455 .LBE595: + 4456 .LBE594: +1605:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4457 .loc 1 1605 0 + 4458 003c 404B ldr r3, .L193+4 + 4459 003e 1B68 ldr r3, [r3] + 4460 0040 002B cmp r3, #0 + 4461 0042 E6D0 beq .L186 +1605:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4462 .loc 1 1605 0 is_stmt 0 discriminator 1 + 4463 0044 5C69 ldr r4, [r3, #20] + 4464 0046 002C cmp r4, #0 + 4465 0048 E3D0 beq .L186 + 4466 .LVL571: + 4467 .LBB596: + ARM GAS /tmp/ccwcPdtV.s page 117 + + + 4468 .LBB597: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4469 .loc 1 1142 0 is_stmt 1 + 4470 004a 6B46 mov r3, sp + 4471 004c DD1D adds r5, r3, #7 + 4472 004e 0122 movs r2, #1 + 4473 0050 2900 movs r1, r5 + 4474 0052 1C20 movs r0, #28 + 4475 0054 FFF7FEFF bl SX1272ReadBuffer + 4476 .LVL572: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4477 .loc 1 1143 0 + 4478 0058 2B78 ldrb r3, [r5] + 4479 .LVL573: + 4480 .LBE597: + 4481 .LBE596: +1607:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4482 .loc 1 1607 0 + 4483 005a 3F20 movs r0, #63 + 4484 005c 1840 ands r0, r3 + 4485 005e A047 blx r4 + 4486 .LVL574: + 4487 0060 D7E7 b .L186 + 4488 .L190: +1580:./Drivers/BSP/Components/sx1272/sx1272.c **** #endif + 4489 .loc 1 1580 0 + 4490 0062 364B ldr r3, .L193 + 4491 0064 3022 movs r2, #48 + 4492 0066 0121 movs r1, #1 + 4493 0068 9954 strb r1, [r3, r2] +1583:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4494 .loc 1 1583 0 + 4495 006a 1B8E ldrh r3, [r3, #48] + 4496 006c 012B cmp r3, #1 + 4497 006e D0D1 bne .L186 +1585:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4498 .loc 1 1585 0 + 4499 0070 3448 ldr r0, .L193+8 + 4500 0072 FFF7FEFF bl TimerStop + 4501 .LVL575: +1587:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4502 .loc 1 1587 0 + 4503 0076 314D ldr r5, .L193 + 4504 0078 3123 movs r3, #49 + 4505 007a 0122 movs r2, #1 + 4506 007c EA54 strb r2, [r5, r3] + 4507 .LVL576: + 4508 .LBB598: + 4509 .LBB599: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4510 .loc 1 1142 0 + 4511 007e 6B46 mov r3, sp + 4512 0080 DC1D adds r4, r3, #7 + 4513 0082 2100 movs r1, r4 + 4514 0084 1120 movs r0, #17 + 4515 0086 FFF7FEFF bl SX1272ReadBuffer + 4516 .LVL577: + ARM GAS /tmp/ccwcPdtV.s page 118 + + +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4517 .loc 1 1143 0 + 4518 008a 2378 ldrb r3, [r4] + 4519 .LVL578: + 4520 .LBE599: + 4521 .LBE598: +1589:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4522 .loc 1 1589 0 + 4523 008c 5B08 lsrs r3, r3, #1 + 4524 008e 5B42 rsbs r3, r3, #0 + 4525 0090 3222 movs r2, #50 + 4526 0092 AB54 strb r3, [r5, r2] + 4527 .LVL579: + 4528 .LBB600: + 4529 .LBB601: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4530 .loc 1 1142 0 + 4531 0094 313A subs r2, r2, #49 + 4532 0096 2100 movs r1, r4 + 4533 0098 1B20 movs r0, #27 + 4534 009a FFF7FEFF bl SX1272ReadBuffer + 4535 .LVL580: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4536 .loc 1 1143 0 + 4537 009e 2678 ldrb r6, [r4] + 4538 .LVL581: + 4539 .LBE601: + 4540 .LBE600: +1591:./Drivers/BSP/Components/sx1272/sx1272.c **** ( uint16_t )SX1272Read( REG_AFCLSB ) ); + 4541 .loc 1 1591 0 + 4542 00a0 3602 lsls r6, r6, #8 + 4543 .LVL582: + 4544 .LBB602: + 4545 .LBB603: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4546 .loc 1 1142 0 + 4547 00a2 0122 movs r2, #1 + 4548 00a4 2100 movs r1, r4 + 4549 00a6 1C20 movs r0, #28 + 4550 00a8 FFF7FEFF bl SX1272ReadBuffer + 4551 .LVL583: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4552 .loc 1 1143 0 + 4553 00ac 2278 ldrb r2, [r4] + 4554 .LVL584: + 4555 .LBE603: + 4556 .LBE602: +1591:./Drivers/BSP/Components/sx1272/sx1272.c **** ( uint16_t )SX1272Read( REG_AFCLSB ) ); + 4557 .loc 1 1591 0 + 4558 00ae 3243 orrs r2, r6 + 4559 .LVL585: + 4560 .LBB604: +1594:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4561 .loc 1 1594 0 + 4562 00b0 130A lsrs r3, r2, #8 + 4563 .LVL586: + 4564 00b2 5901 lsls r1, r3, #5 + ARM GAS /tmp/ccwcPdtV.s page 119 + + + 4565 00b4 C91A subs r1, r1, r3 + 4566 00b6 8801 lsls r0, r1, #6 + 4567 00b8 411A subs r1, r0, r1 + 4568 00ba C900 lsls r1, r1, #3 + 4569 00bc C918 adds r1, r1, r3 + 4570 00be FF20 movs r0, #255 + 4571 00c0 1040 ands r0, r2 + 4572 .LVL587: + 4573 00c2 4301 lsls r3, r0, #5 + 4574 .LVL588: + 4575 00c4 1B1A subs r3, r3, r0 + 4576 00c6 9A01 lsls r2, r3, #6 + 4577 .LVL589: + 4578 00c8 D31A subs r3, r2, r3 + 4579 00ca DB00 lsls r3, r3, #3 + 4580 00cc 1B18 adds r3, r3, r0 + 4581 00ce 8033 adds r3, r3, #128 + 4582 00d0 1B0A lsrs r3, r3, #8 + 4583 00d2 CB18 adds r3, r1, r3 + 4584 00d4 6B63 str r3, [r5, #52] + 4585 .LVL590: + 4586 .LBE604: + 4587 .LBB605: + 4588 .LBB606: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4589 .loc 1 1142 0 + 4590 00d6 0122 movs r2, #1 + 4591 00d8 2100 movs r1, r4 + 4592 00da 0C20 movs r0, #12 + 4593 .LVL591: + 4594 00dc FFF7FEFF bl SX1272ReadBuffer + 4595 .LVL592: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4596 .loc 1 1143 0 + 4597 00e0 2378 ldrb r3, [r4] + 4598 .LVL593: + 4599 .LBE606: + 4600 .LBE605: +1596:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4601 .loc 1 1596 0 + 4602 00e2 5B09 lsrs r3, r3, #5 + 4603 00e4 3822 movs r2, #56 + 4604 00e6 AB54 strb r3, [r5, r2] + 4605 00e8 93E7 b .L186 + 4606 .LVL594: + 4607 .L189: +1616:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4608 .loc 1 1616 0 + 4609 00ea 144B ldr r3, .L193 + 4610 00ec 5B79 ldrb r3, [r3, #5] + 4611 00ee 012B cmp r3, #1 + 4612 00f0 00D0 beq .LCB4584 + 4613 00f2 8EE7 b .L186 @long jump + 4614 .LCB4584: +1621:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4615 .loc 1 1621 0 + 4616 00f4 114A ldr r2, .L193 + ARM GAS /tmp/ccwcPdtV.s page 120 + + + 4617 00f6 5233 adds r3, r3, #82 + 4618 00f8 D35C ldrb r3, [r2, r3] + 4619 00fa 002B cmp r3, #0 + 4620 00fc 00D1 bne .LCB4589 + 4621 00fe 88E7 b .L186 @long jump + 4622 .LCB4589: + 4623 .LVL595: + 4624 0100 6B46 mov r3, sp + 4625 0102 991D adds r1, r3, #6 + 4626 0104 0223 movs r3, #2 + 4627 0106 0B70 strb r3, [r1] + 4628 .LVL596: + 4629 .LBB607: + 4630 .LBB608: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4631 .loc 1 1136 0 + 4632 0108 0122 movs r2, #1 + 4633 010a 1220 movs r0, #18 + 4634 010c FFF7FEFF bl SX1272WriteBuffer + 4635 .LVL597: + 4636 .LBE608: + 4637 .LBE607: +1626:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4638 .loc 1 1626 0 + 4639 0110 0B4B ldr r3, .L193+4 + 4640 0112 1B68 ldr r3, [r3] + 4641 0114 002B cmp r3, #0 + 4642 0116 00D1 bne .LCB4609 + 4643 0118 7BE7 b .L186 @long jump + 4644 .LCB4609: +1626:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4645 .loc 1 1626 0 is_stmt 0 discriminator 1 + 4646 011a 5C69 ldr r4, [r3, #20] + 4647 011c 002C cmp r4, #0 + 4648 011e 00D1 bne .LCB4612 + 4649 0120 77E7 b .L186 @long jump + 4650 .LCB4612: + 4651 .LVL598: + 4652 .LBB609: + 4653 .LBB610: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4654 .loc 1 1142 0 is_stmt 1 + 4655 0122 6B46 mov r3, sp + 4656 0124 DD1D adds r5, r3, #7 + 4657 0126 0122 movs r2, #1 + 4658 0128 2900 movs r1, r5 + 4659 012a 1C20 movs r0, #28 + 4660 012c FFF7FEFF bl SX1272ReadBuffer + 4661 .LVL599: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4662 .loc 1 1143 0 + 4663 0130 2B78 ldrb r3, [r5] + 4664 .LVL600: + 4665 .LBE610: + 4666 .LBE609: +1628:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4667 .loc 1 1628 0 + ARM GAS /tmp/ccwcPdtV.s page 121 + + + 4668 0132 3F20 movs r0, #63 + 4669 0134 1840 ands r0, r3 + 4670 0136 A047 blx r4 + 4671 .LVL601: +1639:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4672 .loc 1 1639 0 + 4673 0138 6BE7 b .L186 + 4674 .L194: + 4675 013a C046 .align 2 + 4676 .L193: + 4677 013c 00000000 .word .LANCHOR0 + 4678 0140 00000000 .word .LANCHOR5 + 4679 0144 00000000 .word .LANCHOR4 + 4680 .cfi_endproc + 4681 .LFE129: + 4683 .section .text.SX1272OnDio3Irq,"ax",%progbits + 4684 .align 1 + 4685 .global SX1272OnDio3Irq + 4686 .syntax unified + 4687 .code 16 + 4688 .thumb_func + 4689 .fpu softvfp + 4691 SX1272OnDio3Irq: + 4692 .LFB130: +1642:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) + 4693 .loc 1 1642 0 + 4694 .cfi_startproc + 4695 @ args = 0, pretend = 0, frame = 8 + 4696 @ frame_needed = 0, uses_anonymous_args = 0 + 4697 0000 10B5 push {r4, lr} + 4698 .LCFI41: + 4699 .cfi_def_cfa_offset 8 + 4700 .cfi_offset 4, -8 + 4701 .cfi_offset 14, -4 + 4702 0002 82B0 sub sp, sp, #8 + 4703 .LCFI42: + 4704 .cfi_def_cfa_offset 16 +1643:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4705 .loc 1 1643 0 + 4706 0004 194B ldr r3, .L199 + 4707 0006 5B79 ldrb r3, [r3, #5] + 4708 0008 012B cmp r3, #1 + 4709 000a 2CD1 bne .L195 + 4710 .LVL602: + 4711 .LBB611: + 4712 .LBB612: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4713 .loc 1 1142 0 + 4714 000c 6B46 mov r3, sp + 4715 000e DC1D adds r4, r3, #7 + 4716 0010 0122 movs r2, #1 + 4717 0012 2100 movs r1, r4 + 4718 0014 1220 movs r0, #18 + 4719 0016 FFF7FEFF bl SX1272ReadBuffer + 4720 .LVL603: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4721 .loc 1 1143 0 + ARM GAS /tmp/ccwcPdtV.s page 122 + + + 4722 001a 2378 ldrb r3, [r4] + 4723 .LVL604: + 4724 .LBE612: + 4725 .LBE611: +1648:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4726 .loc 1 1648 0 + 4727 001c DB07 lsls r3, r3, #31 + 4728 001e 11D5 bpl .L198 + 4729 .LVL605: + 4730 0020 6B46 mov r3, sp + 4731 0022 991D adds r1, r3, #6 + 4732 0024 0523 movs r3, #5 + 4733 0026 0B70 strb r3, [r1] + 4734 .LVL606: + 4735 .LBB613: + 4736 .LBB614: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4737 .loc 1 1136 0 + 4738 0028 0122 movs r2, #1 + 4739 002a 1220 movs r0, #18 + 4740 002c FFF7FEFF bl SX1272WriteBuffer + 4741 .LVL607: + 4742 .LBE614: + 4743 .LBE613: +1652:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4744 .loc 1 1652 0 + 4745 0030 0F4B ldr r3, .L199+4 + 4746 0032 1B68 ldr r3, [r3] + 4747 0034 002B cmp r3, #0 + 4748 0036 16D0 beq .L195 +1652:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4749 .loc 1 1652 0 is_stmt 0 discriminator 1 + 4750 0038 9B69 ldr r3, [r3, #24] + 4751 003a 002B cmp r3, #0 + 4752 003c 13D0 beq .L195 +1654:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4753 .loc 1 1654 0 is_stmt 1 + 4754 003e 0120 movs r0, #1 + 4755 0040 9847 blx r3 + 4756 .LVL608: + 4757 0042 10E0 b .L195 + 4758 .L198: + 4759 .LVL609: + 4760 0044 6B46 mov r3, sp + 4761 0046 D91D adds r1, r3, #7 + 4762 0048 0423 movs r3, #4 + 4763 004a 0B70 strb r3, [r1] + 4764 .LVL610: + 4765 .LBB615: + 4766 .LBB616: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4767 .loc 1 1136 0 + 4768 004c 0122 movs r2, #1 + 4769 004e 1220 movs r0, #18 + 4770 0050 FFF7FEFF bl SX1272WriteBuffer + 4771 .LVL611: + 4772 .LBE616: + ARM GAS /tmp/ccwcPdtV.s page 123 + + + 4773 .LBE615: +1661:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4774 .loc 1 1661 0 + 4775 0054 064B ldr r3, .L199+4 + 4776 0056 1B68 ldr r3, [r3] + 4777 0058 002B cmp r3, #0 + 4778 005a 04D0 beq .L195 +1661:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4779 .loc 1 1661 0 is_stmt 0 discriminator 1 + 4780 005c 9B69 ldr r3, [r3, #24] + 4781 005e 002B cmp r3, #0 + 4782 0060 01D0 beq .L195 +1663:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4783 .loc 1 1663 0 is_stmt 1 + 4784 0062 0020 movs r0, #0 + 4785 0064 9847 blx r3 + 4786 .LVL612: + 4787 .L195: +1670:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4788 .loc 1 1670 0 + 4789 0066 02B0 add sp, sp, #8 + 4790 @ sp needed + 4791 0068 10BD pop {r4, pc} + 4792 .L200: + 4793 006a C046 .align 2 + 4794 .L199: + 4795 006c 00000000 .word .LANCHOR0 + 4796 0070 00000000 .word .LANCHOR5 + 4797 .cfi_endproc + 4798 .LFE130: + 4800 .section .text.SX1272Send,"ax",%progbits + 4801 .align 1 + 4802 .global SX1272Send + 4803 .syntax unified + 4804 .code 16 + 4805 .thumb_func + 4806 .fpu softvfp + 4808 SX1272Send: + 4809 .LFB106: + 715:./Drivers/BSP/Components/sx1272/sx1272.c **** uint32_t txTimeout = 0; + 4810 .loc 1 715 0 + 4811 .cfi_startproc + 4812 @ args = 0, pretend = 0, frame = 16 + 4813 @ frame_needed = 0, uses_anonymous_args = 0 + 4814 .LVL613: + 4815 0000 70B5 push {r4, r5, r6, lr} + 4816 .LCFI43: + 4817 .cfi_def_cfa_offset 16 + 4818 .cfi_offset 4, -16 + 4819 .cfi_offset 5, -12 + 4820 .cfi_offset 6, -8 + 4821 .cfi_offset 14, -4 + 4822 0002 84B0 sub sp, sp, #16 + 4823 .LCFI44: + 4824 .cfi_def_cfa_offset 32 + 4825 0004 0400 movs r4, r0 + 4826 0006 6B46 mov r3, sp + ARM GAS /tmp/ccwcPdtV.s page 124 + + + 4827 0008 D971 strb r1, [r3, #7] + 4828 .LVL614: + 718:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4829 .loc 1 718 0 + 4830 000a 594B ldr r3, .L215 + 4831 000c 5B79 ldrb r3, [r3, #5] + 4832 000e 002B cmp r3, #0 + 4833 0010 03D0 beq .L203 + 4834 0012 012B cmp r3, #1 + 4835 0014 3CD0 beq .L204 + 716:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4836 .loc 1 716 0 + 4837 0016 0020 movs r0, #0 + 4838 .LVL615: + 4839 0018 25E0 b .L202 + 4840 .LVL616: + 4841 .L203: + 722:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = size; + 4842 .loc 1 722 0 + 4843 001a 554B ldr r3, .L215 + 4844 001c 0022 movs r2, #0 + 4845 001e 9A87 strh r2, [r3, #60] + 723:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4846 .loc 1 723 0 + 4847 0020 6A46 mov r2, sp + 4848 0022 0732 adds r2, r2, #7 + 4849 0024 1278 ldrb r2, [r2] + 4850 0026 5A87 strh r2, [r3, #58] + 725:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4851 .loc 1 725 0 + 4852 0028 2221 movs r1, #34 + 4853 .LVL617: + 4854 002a 5B5C ldrb r3, [r3, r1] + 4855 002c 002B cmp r3, #0 + 4856 002e 1ED1 bne .L205 + 4857 .LVL618: + 4858 .LBB617: + 4859 .LBB618: +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4860 .loc 1 1183 0 + 4861 0030 0122 movs r2, #1 + 4862 0032 6B46 mov r3, sp + 4863 0034 D91D adds r1, r3, #7 + 4864 .LVL619: + 4865 0036 0020 movs r0, #0 + 4866 .LVL620: + 4867 0038 FFF7FEFF bl SX1272WriteBuffer + 4868 .LVL621: + 4869 .L206: + 4870 .LBE618: + 4871 .LBE617: + 734:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4872 .loc 1 734 0 + 4873 003c 6B46 mov r3, sp + 4874 003e DA79 ldrb r2, [r3, #7] + 4875 0040 531E subs r3, r2, #1 + 4876 0042 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccwcPdtV.s page 125 + + + 4877 0044 3F2B cmp r3, #63 + 4878 0046 19D8 bhi .L207 + 736:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4879 .loc 1 736 0 + 4880 0048 4949 ldr r1, .L215 + 4881 004a 3F23 movs r3, #63 + 4882 004c CA54 strb r2, [r1, r3] + 4883 .L208: + 745:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.ChunkSize; + 4884 .loc 1 745 0 + 4885 004e 484D ldr r5, .L215 + 4886 0050 3F26 movs r6, #63 + 4887 0052 AA5D ldrb r2, [r5, r6] + 4888 .LVL622: + 4889 .LBB619: + 4890 .LBB620: +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4891 .loc 1 1183 0 + 4892 0054 2100 movs r1, r4 + 4893 0056 0020 movs r0, #0 + 4894 0058 FFF7FEFF bl SX1272WriteBuffer + 4895 .LVL623: + 4896 .LBE620: + 4897 .LBE619: + 746:./Drivers/BSP/Components/sx1272/sx1272.c **** txTimeout = SX1272.Settings.Fsk.TxTimeout; + 4898 .loc 1 746 0 + 4899 005c AB5D ldrb r3, [r5, r6] + 4900 005e AA8F ldrh r2, [r5, #60] + 4901 0060 9B18 adds r3, r3, r2 + 4902 0062 AB87 strh r3, [r5, #60] + 747:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4903 .loc 1 747 0 + 4904 0064 A86A ldr r0, [r5, #40] + 4905 .LVL624: + 4906 .L202: + 785:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4907 .loc 1 785 0 + 4908 0066 FFF7FEFF bl SX1272SetTx + 4909 .LVL625: + 786:./Drivers/BSP/Components/sx1272/sx1272.c **** + 4910 .loc 1 786 0 + 4911 006a 04B0 add sp, sp, #16 + 4912 @ sp needed + 4913 .LVL626: + 4914 006c 70BD pop {r4, r5, r6, pc} + 4915 .LVL627: + 4916 .L205: + 4917 006e 03A9 add r1, sp, #12 + 4918 0070 0A70 strb r2, [r1] + 4919 .LVL628: + 4920 .LBB621: + 4921 .LBB622: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4922 .loc 1 1136 0 + 4923 0072 0122 movs r2, #1 + 4924 .LVL629: + 4925 0074 3220 movs r0, #50 + ARM GAS /tmp/ccwcPdtV.s page 126 + + + 4926 .LVL630: + 4927 0076 FFF7FEFF bl SX1272WriteBuffer + 4928 .LVL631: + 4929 007a DFE7 b .L206 + 4930 .LVL632: + 4931 .L207: + 4932 .LBE622: + 4933 .LBE621: + 740:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.ChunkSize = 32; + 4934 .loc 1 740 0 + 4935 007c 92B2 uxth r2, r2 + 4936 007e 2100 movs r1, r4 + 4937 0080 3C48 ldr r0, .L215+4 + 4938 0082 FFF7FEFF bl memcpy1 + 4939 .LVL633: + 741:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4940 .loc 1 741 0 + 4941 0086 3A4A ldr r2, .L215 + 4942 0088 3F23 movs r3, #63 + 4943 008a 2021 movs r1, #32 + 4944 008c D154 strb r1, [r2, r3] + 4945 008e DEE7 b .L208 + 4946 .LVL634: + 4947 .L204: + 752:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 4948 .loc 1 752 0 + 4949 0090 374A ldr r2, .L215 + 4950 0092 5523 movs r3, #85 + 4951 0094 D35C ldrb r3, [r2, r3] + 4952 0096 002B cmp r3, #0 + 4953 0098 46D0 beq .L209 + 4954 .LVL635: + 4955 .LBB623: + 4956 .LBB624: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 4957 .loc 1 1142 0 + 4958 009a 0F25 movs r5, #15 + 4959 009c 6D44 add r5, r5, sp + 4960 009e 0122 movs r2, #1 + 4961 00a0 2900 movs r1, r5 + 4962 .LVL636: + 4963 00a2 3320 movs r0, #51 + 4964 .LVL637: + 4965 00a4 FFF7FEFF bl SX1272ReadBuffer + 4966 .LVL638: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4967 .loc 1 1143 0 + 4968 00a8 2B78 ldrb r3, [r5] + 4969 .LVL639: + 4970 .LBE624: + 4971 .LBE623: + 754:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); + 4972 .loc 1 754 0 + 4973 00aa 4122 movs r2, #65 + 4974 00ac 9343 bics r3, r2 + 4975 .LVL640: + 4976 00ae 0921 movs r1, #9 + ARM GAS /tmp/ccwcPdtV.s page 127 + + + 4977 00b0 6944 add r1, r1, sp + 4978 00b2 0B70 strb r3, [r1] + 4979 .LVL641: + 4980 .LBB625: + 4981 .LBB626: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 4982 .loc 1 1136 0 + 4983 00b4 403A subs r2, r2, #64 + 4984 00b6 3320 movs r0, #51 + 4985 00b8 FFF7FEFF bl SX1272WriteBuffer + 4986 .LVL642: + 4987 00bc 02A9 add r1, sp, #8 + 4988 00be 1923 movs r3, #25 + 4989 00c0 0B70 strb r3, [r1] + 4990 .LVL643: + 4991 .LBE626: + 4992 .LBE625: + 4993 .LBB627: + 4994 .LBB628: + 4995 00c2 0122 movs r2, #1 + 4996 00c4 3B20 movs r0, #59 + 4997 00c6 FFF7FEFF bl SX1272WriteBuffer + 4998 .LVL644: + 4999 .L210: + 5000 .LBE628: + 5001 .LBE627: + 763:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5002 .loc 1 763 0 + 5003 00ca 6B46 mov r3, sp + 5004 00cc 0733 adds r3, r3, #7 + 5005 00ce 1B78 ldrb r3, [r3] + 5006 00d0 2749 ldr r1, .L215 + 5007 00d2 6422 movs r2, #100 + 5008 00d4 8B54 strb r3, [r1, r2] + 5009 .LVL645: + 5010 00d6 0F21 movs r1, #15 + 5011 00d8 6944 add r1, r1, sp + 5012 00da 0B70 strb r3, [r1] + 5013 .LVL646: + 5014 .LBB629: + 5015 .LBB630: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5016 .loc 1 1136 0 + 5017 00dc 633A subs r2, r2, #99 + 5018 00de 2220 movs r0, #34 + 5019 00e0 FFF7FEFF bl SX1272WriteBuffer + 5020 .LVL647: + 5021 00e4 0E21 movs r1, #14 + 5022 00e6 6944 add r1, r1, sp + 5023 00e8 0025 movs r5, #0 + 5024 00ea 0D70 strb r5, [r1] + 5025 .LVL648: + 5026 .LBE630: + 5027 .LBE629: + 5028 .LBB631: + 5029 .LBB632: + 5030 00ec 0122 movs r2, #1 + ARM GAS /tmp/ccwcPdtV.s page 128 + + + 5031 00ee 0E20 movs r0, #14 + 5032 00f0 FFF7FEFF bl SX1272WriteBuffer + 5033 .LVL649: + 5034 00f4 0D21 movs r1, #13 + 5035 00f6 6944 add r1, r1, sp + 5036 00f8 0D70 strb r5, [r1] + 5037 .LVL650: + 5038 .LBE632: + 5039 .LBE631: + 5040 .LBB633: + 5041 .LBB634: + 5042 00fa 0122 movs r2, #1 + 5043 00fc 0D20 movs r0, #13 + 5044 00fe FFF7FEFF bl SX1272WriteBuffer + 5045 .LVL651: + 5046 .LBE634: + 5047 .LBE633: + 5048 .LBB635: + 5049 .LBB636: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5050 .loc 1 1142 0 + 5051 0102 03AD add r5, sp, #12 + 5052 0104 0122 movs r2, #1 + 5053 0106 2900 movs r1, r5 + 5054 0108 0120 movs r0, #1 + 5055 010a FFF7FEFF bl SX1272ReadBuffer + 5056 .LVL652: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5057 .loc 1 1143 0 + 5058 010e 2B78 ldrb r3, [r5] + 5059 .LVL653: + 5060 .LBE636: + 5061 .LBE635: + 773:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5062 .loc 1 773 0 + 5063 0110 F822 movs r2, #248 + 5064 0112 9343 bics r3, r2 + 5065 0114 25D0 beq .L214 + 5066 .L211: + 779:./Drivers/BSP/Components/sx1272/sx1272.c **** txTimeout = SX1272.Settings.LoRa.TxTimeout; + 5067 .loc 1 779 0 + 5068 0116 6B46 mov r3, sp + 5069 0118 DA79 ldrb r2, [r3, #7] + 5070 .LVL654: + 5071 .LBB637: + 5072 .LBB638: +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5073 .loc 1 1183 0 + 5074 011a 2100 movs r1, r4 + 5075 011c 0020 movs r0, #0 + 5076 011e FFF7FEFF bl SX1272WriteBuffer + 5077 .LVL655: + 5078 .LBE638: + 5079 .LBE637: + 780:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5080 .loc 1 780 0 + 5081 0122 134B ldr r3, .L215 + ARM GAS /tmp/ccwcPdtV.s page 129 + + + 5082 0124 986D ldr r0, [r3, #88] + 5083 .LVL656: + 782:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5084 .loc 1 782 0 + 5085 0126 9EE7 b .L202 + 5086 .LVL657: + 5087 .L209: + 5088 .LBB639: + 5089 .LBB640: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5090 .loc 1 1142 0 + 5091 0128 0F25 movs r5, #15 + 5092 012a 6D44 add r5, r5, sp + 5093 012c 0122 movs r2, #1 + 5094 012e 2900 movs r1, r5 + 5095 .LVL658: + 5096 0130 3320 movs r0, #51 + 5097 .LVL659: + 5098 0132 FFF7FEFF bl SX1272ReadBuffer + 5099 .LVL660: + 5100 .LBE640: + 5101 .LBE639: + 759:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); + 5102 .loc 1 759 0 + 5103 0136 0023 movs r3, #0 + 5104 0138 EB56 ldrsb r3, [r5, r3] + 5105 013a 4122 movs r2, #65 + 5106 013c 9343 bics r3, r2 + 5107 013e 0122 movs r2, #1 + 5108 0140 1343 orrs r3, r2 + 5109 .LVL661: + 5110 0142 0B21 movs r1, #11 + 5111 0144 6944 add r1, r1, sp + 5112 0146 0B70 strb r3, [r1] + 5113 .LVL662: + 5114 .LBB641: + 5115 .LBB642: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5116 .loc 1 1136 0 + 5117 0148 0122 movs r2, #1 + 5118 014a 3320 movs r0, #51 + 5119 014c FFF7FEFF bl SX1272WriteBuffer + 5120 .LVL663: + 5121 0150 0A21 movs r1, #10 + 5122 0152 6944 add r1, r1, sp + 5123 0154 1D23 movs r3, #29 + 5124 0156 0B70 strb r3, [r1] + 5125 .LVL664: + 5126 .LBE642: + 5127 .LBE641: + 5128 .LBB643: + 5129 .LBB644: + 5130 0158 0122 movs r2, #1 + 5131 015a 3B20 movs r0, #59 + 5132 015c FFF7FEFF bl SX1272WriteBuffer + 5133 .LVL665: + 5134 0160 B3E7 b .L210 + ARM GAS /tmp/ccwcPdtV.s page 130 + + + 5135 .LVL666: + 5136 .L214: + 5137 .LBE644: + 5138 .LBE643: + 775:./Drivers/BSP/Components/sx1272/sx1272.c **** DelayMs( 1 ); + 5139 .loc 1 775 0 + 5140 0162 FFF7FEFF bl SX1272SetStby + 5141 .LVL667: + 776:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5142 .loc 1 776 0 + 5143 0166 0120 movs r0, #1 + 5144 0168 FFF7FEFF bl DelayMs + 5145 .LVL668: + 5146 016c D3E7 b .L211 + 5147 .L216: + 5148 016e C046 .align 2 + 5149 .L215: + 5150 0170 00000000 .word .LANCHOR0 + 5151 0174 00000000 .word RxTxBuffer + 5152 .cfi_endproc + 5153 .LFE106: + 5155 .section .text.SX1272OnDio0Irq,"ax",%progbits + 5156 .align 1 + 5157 .global SX1272OnDio0Irq + 5158 .syntax unified + 5159 .code 16 + 5160 .thumb_func + 5161 .fpu softvfp + 5163 SX1272OnDio0Irq: + 5164 .LFB127: +1303:./Drivers/BSP/Components/sx1272/sx1272.c **** volatile uint8_t irqFlags = 0; + 5165 .loc 1 1303 0 + 5166 .cfi_startproc + 5167 @ args = 0, pretend = 0, frame = 16 + 5168 @ frame_needed = 0, uses_anonymous_args = 0 + 5169 0000 70B5 push {r4, r5, r6, lr} + 5170 .LCFI45: + 5171 .cfi_def_cfa_offset 16 + 5172 .cfi_offset 4, -16 + 5173 .cfi_offset 5, -12 + 5174 .cfi_offset 6, -8 + 5175 .cfi_offset 14, -4 + 5176 0002 84B0 sub sp, sp, #16 + 5177 .LCFI46: + 5178 .cfi_def_cfa_offset 32 +1304:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5179 .loc 1 1304 0 + 5180 0004 0F23 movs r3, #15 + 5181 0006 6B44 add r3, r3, sp + 5182 0008 0022 movs r2, #0 + 5183 000a 1A70 strb r2, [r3] +1306:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5184 .loc 1 1306 0 + 5185 000c C94B ldr r3, .L247 + 5186 000e 1B79 ldrb r3, [r3, #4] + 5187 0010 012B cmp r3, #1 + 5188 0012 04D0 beq .L219 + ARM GAS /tmp/ccwcPdtV.s page 131 + + + 5189 0014 022B cmp r3, #2 + 5190 0016 00D1 bne .LCB5159 + 5191 0018 6BE1 b .L220 @long jump + 5192 .LCB5159: + 5193 .L217: +1488:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5194 .loc 1 1488 0 + 5195 001a 04B0 add sp, sp, #16 + 5196 @ sp needed + 5197 001c 70BD pop {r4, r5, r6, pc} + 5198 .L219: +1311:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5199 .loc 1 1311 0 + 5200 001e C54B ldr r3, .L247 + 5201 0020 5B79 ldrb r3, [r3, #5] + 5202 0022 002B cmp r3, #0 + 5203 0024 33D0 beq .L221 + 5204 0026 012B cmp r3, #1 + 5205 0028 F7D1 bne .L217 + 5206 .LVL669: + 5207 002a 0B21 movs r1, #11 + 5208 002c 6944 add r1, r1, sp + 5209 002e 4023 movs r3, #64 + 5210 0030 0B70 strb r3, [r1] + 5211 .LVL670: + 5212 .LBB645: + 5213 .LBB646: + 5214 .LBB647: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5215 .loc 1 1136 0 + 5216 0032 0122 movs r2, #1 + 5217 0034 1220 movs r0, #18 + 5218 0036 FFF7FEFF bl SX1272WriteBuffer + 5219 .LVL671: + 5220 .LBE647: + 5221 .LBE646: + 5222 .LBB648: + 5223 .LBB649: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5224 .loc 1 1142 0 + 5225 003a 0E24 movs r4, #14 + 5226 003c 6C44 add r4, r4, sp + 5227 003e 0122 movs r2, #1 + 5228 0040 2100 movs r1, r4 + 5229 0042 1220 movs r0, #18 + 5230 0044 FFF7FEFF bl SX1272ReadBuffer + 5231 .LVL672: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5232 .loc 1 1143 0 + 5233 0048 2278 ldrb r2, [r4] + 5234 .LVL673: + 5235 .LBE649: + 5236 .LBE648: +1401:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADC + 5237 .loc 1 1401 0 + 5238 004a 0F23 movs r3, #15 + 5239 004c 6B44 add r3, r3, sp + ARM GAS /tmp/ccwcPdtV.s page 132 + + + 5240 004e 1A70 strb r2, [r3] +1402:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5241 .loc 1 1402 0 + 5242 0050 1B78 ldrb r3, [r3] + 5243 0052 9B06 lsls r3, r3, #26 + 5244 0054 00D4 bmi .LCB5219 + 5245 0056 DFE0 b .L234 @long jump + 5246 .LCB5219: + 5247 .LVL674: + 5248 0058 03A9 add r1, sp, #12 + 5249 005a 2023 movs r3, #32 + 5250 005c 0B70 strb r3, [r1] + 5251 .LVL675: + 5252 .LBB650: + 5253 .LBB651: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5254 .loc 1 1136 0 + 5255 005e 0122 movs r2, #1 + 5256 0060 1220 movs r0, #18 + 5257 0062 FFF7FEFF bl SX1272WriteBuffer + 5258 .LVL676: + 5259 .LBE651: + 5260 .LBE650: +1407:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5261 .loc 1 1407 0 + 5262 0066 B34A ldr r2, .L247 + 5263 0068 5623 movs r3, #86 + 5264 006a D35C ldrb r3, [r2, r3] + 5265 006c 002B cmp r3, #0 + 5266 006e 02D1 bne .L235 +1409:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5267 .loc 1 1409 0 + 5268 0070 1300 movs r3, r2 + 5269 0072 0022 movs r2, #0 + 5270 0074 1A71 strb r2, [r3, #4] + 5271 .L235: +1411:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5272 .loc 1 1411 0 + 5273 0076 B048 ldr r0, .L247+4 + 5274 0078 FFF7FEFF bl TimerStop + 5275 .LVL677: +1413:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5276 .loc 1 1413 0 + 5277 007c AF4B ldr r3, .L247+8 + 5278 007e 1B68 ldr r3, [r3] + 5279 0080 002B cmp r3, #0 + 5280 0082 CAD0 beq .L217 +1413:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5281 .loc 1 1413 0 is_stmt 0 discriminator 1 + 5282 0084 1B69 ldr r3, [r3, #16] + 5283 0086 002B cmp r3, #0 + 5284 0088 C7D0 beq .L217 +1415:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5285 .loc 1 1415 0 is_stmt 1 + 5286 008a 9847 blx r3 + 5287 .LVL678: + 5288 008c C5E7 b .L217 + ARM GAS /tmp/ccwcPdtV.s page 133 + + + 5289 .LVL679: + 5290 .L221: + 5291 .LBE645: +1314:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5292 .loc 1 1314 0 + 5293 008e A94A ldr r2, .L247 + 5294 0090 2423 movs r3, #36 + 5295 0092 D35C ldrb r3, [r2, r3] + 5296 0094 002B cmp r3, #0 + 5297 0096 1ED1 bne .L243 + 5298 .L223: +1352:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5299 .loc 1 1352 0 + 5300 0098 A64B ldr r3, .L247 + 5301 009a 5A8F ldrh r2, [r3, #58] + 5302 009c 002A cmp r2, #0 + 5303 009e 76D1 bne .L227 +1352:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5304 .loc 1 1352 0 is_stmt 0 discriminator 1 + 5305 00a0 9B8F ldrh r3, [r3, #60] + 5306 00a2 002B cmp r3, #0 + 5307 00a4 73D1 bne .L227 +1354:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5308 .loc 1 1354 0 is_stmt 1 + 5309 00a6 A34A ldr r2, .L247 + 5310 00a8 2233 adds r3, r3, #34 + 5311 00aa D35C ldrb r3, [r2, r3] + 5312 00ac 002B cmp r3, #0 + 5313 00ae 63D1 bne .L228 + 5314 .LVL680: + 5315 .LBB664: + 5316 .LBB665: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5317 .loc 1 1188 0 + 5318 00b0 1100 movs r1, r2 + 5319 00b2 0122 movs r2, #1 + 5320 00b4 3A31 adds r1, r1, #58 + 5321 00b6 0020 movs r0, #0 + 5322 00b8 FFF7FEFF bl SX1272ReadBuffer + 5323 .LVL681: + 5324 .L229: + 5325 .LBE665: + 5326 .LBE664: +1362:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. + 5327 .loc 1 1362 0 + 5328 00bc 9D4C ldr r4, .L247 + 5329 00be A38F ldrh r3, [r4, #60] + 5330 00c0 9F49 ldr r1, .L247+12 + 5331 00c2 5918 adds r1, r3, r1 + 5332 00c4 628F ldrh r2, [r4, #58] + 5333 00c6 D21A subs r2, r2, r3 + 5334 00c8 D2B2 uxtb r2, r2 + 5335 .LVL682: + 5336 .LBB666: + 5337 .LBB667: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5338 .loc 1 1188 0 + ARM GAS /tmp/ccwcPdtV.s page 134 + + + 5339 00ca 0020 movs r0, #0 + 5340 00cc FFF7FEFF bl SX1272ReadBuffer + 5341 .LVL683: + 5342 .LBE667: + 5343 .LBE666: +1363:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5344 .loc 1 1363 0 + 5345 00d0 638F ldrh r3, [r4, #58] + 5346 00d2 A387 strh r3, [r4, #60] + 5347 00d4 66E0 b .L230 + 5348 .L243: + 5349 .LVL684: + 5350 .LBB668: + 5351 .LBB669: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5352 .loc 1 1142 0 + 5353 00d6 0E24 movs r4, #14 + 5354 00d8 6C44 add r4, r4, sp + 5355 00da 0122 movs r2, #1 + 5356 00dc 2100 movs r1, r4 + 5357 00de 3F20 movs r0, #63 + 5358 00e0 FFF7FEFF bl SX1272ReadBuffer + 5359 .LVL685: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5360 .loc 1 1143 0 + 5361 00e4 2278 ldrb r2, [r4] + 5362 .LVL686: + 5363 .LBE669: + 5364 .LBE668: +1316:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) + 5365 .loc 1 1316 0 + 5366 00e6 0F23 movs r3, #15 + 5367 00e8 6B44 add r3, r3, sp + 5368 00ea 1A70 strb r2, [r3] +1317:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5369 .loc 1 1317 0 + 5370 00ec 1B78 ldrb r3, [r3] + 5371 00ee 9B07 lsls r3, r3, #30 + 5372 00f0 D2D4 bmi .L223 + 5373 .LVL687: + 5374 00f2 02A9 add r1, sp, #8 + 5375 00f4 0B23 movs r3, #11 + 5376 00f6 0B70 strb r3, [r1] + 5377 .LVL688: + 5378 .LBB670: + 5379 .LBB671: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5380 .loc 1 1136 0 + 5381 00f8 0122 movs r2, #1 + 5382 00fa 3E20 movs r0, #62 + 5383 00fc FFF7FEFF bl SX1272WriteBuffer + 5384 .LVL689: + 5385 0100 6B46 mov r3, sp + 5386 0102 D91D adds r1, r3, #7 + 5387 0104 1023 movs r3, #16 + 5388 0106 0B70 strb r3, [r1] + 5389 .LVL690: + ARM GAS /tmp/ccwcPdtV.s page 135 + + + 5390 .LBE671: + 5391 .LBE670: + 5392 .LBB672: + 5393 .LBB673: + 5394 0108 0122 movs r2, #1 + 5395 010a 3F20 movs r0, #63 + 5396 010c FFF7FEFF bl SX1272WriteBuffer + 5397 .LVL691: + 5398 .LBE673: + 5399 .LBE672: +1325:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5400 .loc 1 1325 0 + 5401 0110 8948 ldr r0, .L247+4 + 5402 0112 FFF7FEFF bl TimerStop + 5403 .LVL692: +1327:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5404 .loc 1 1327 0 + 5405 0116 874A ldr r2, .L247 + 5406 0118 2623 movs r3, #38 + 5407 011a D35C ldrb r3, [r2, r3] + 5408 011c 002B cmp r3, #0 + 5409 011e 16D1 bne .L224 +1329:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.State = RF_IDLE; + 5410 .loc 1 1329 0 + 5411 0120 8848 ldr r0, .L247+16 + 5412 0122 FFF7FEFF bl TimerStop + 5413 .LVL693: +1330:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5414 .loc 1 1330 0 + 5415 0126 834B ldr r3, .L247 + 5416 0128 0022 movs r2, #0 + 5417 012a 1A71 strb r2, [r3, #4] + 5418 .L225: +1339:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5419 .loc 1 1339 0 + 5420 012c 834B ldr r3, .L247+8 + 5421 012e 1B68 ldr r3, [r3] + 5422 0130 002B cmp r3, #0 + 5423 0132 03D0 beq .L226 +1339:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5424 .loc 1 1339 0 is_stmt 0 discriminator 1 + 5425 0134 1B69 ldr r3, [r3, #16] + 5426 0136 002B cmp r3, #0 + 5427 0138 00D0 beq .L226 +1341:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5428 .loc 1 1341 0 is_stmt 1 + 5429 013a 9847 blx r3 + 5430 .LVL694: + 5431 .L226: +1343:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + 5432 .loc 1 1343 0 + 5433 013c 7D4B ldr r3, .L247 + 5434 013e 0022 movs r2, #0 + 5435 0140 3021 movs r1, #48 + 5436 0142 5A54 strb r2, [r3, r1] +1344:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 5437 .loc 1 1344 0 + ARM GAS /tmp/ccwcPdtV.s page 136 + + + 5438 0144 0131 adds r1, r1, #1 + 5439 0146 5A54 strb r2, [r3, r1] +1345:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; + 5440 .loc 1 1345 0 + 5441 0148 9A87 strh r2, [r3, #60] +1346:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 5442 .loc 1 1346 0 + 5443 014a 5A87 strh r2, [r3, #58] +1347:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5444 .loc 1 1347 0 + 5445 014c 65E7 b .L217 + 5446 .L224: + 5447 .LVL695: + 5448 .LBB674: + 5449 .LBB675: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5450 .loc 1 1142 0 + 5451 014e 0E24 movs r4, #14 + 5452 0150 6C44 add r4, r4, sp + 5453 0152 0122 movs r2, #1 + 5454 0154 2100 movs r1, r4 + 5455 0156 0D20 movs r0, #13 + 5456 0158 FFF7FEFF bl SX1272ReadBuffer + 5457 .LVL696: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5458 .loc 1 1143 0 + 5459 015c 2378 ldrb r3, [r4] + 5460 .LVL697: + 5461 .LBE675: + 5462 .LBE674: +1335:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); + 5463 .loc 1 1335 0 + 5464 015e 4022 movs r2, #64 + 5465 0160 1343 orrs r3, r2 + 5466 .LVL698: + 5467 0162 0921 movs r1, #9 + 5468 0164 6944 add r1, r1, sp + 5469 0166 0B70 strb r3, [r1] + 5470 .LVL699: + 5471 .LBB676: + 5472 .LBB677: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5473 .loc 1 1136 0 + 5474 0168 0122 movs r2, #1 + 5475 016a 0D20 movs r0, #13 + 5476 016c FFF7FEFF bl SX1272WriteBuffer + 5477 .LVL700: + 5478 .LBE677: + 5479 .LBE676: +1336:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5480 .loc 1 1336 0 + 5481 0170 7448 ldr r0, .L247+16 + 5482 0172 FFF7FEFF bl TimerStart + 5483 .LVL701: + 5484 0176 D9E7 b .L225 + 5485 .L228: + 5486 .LVL702: + ARM GAS /tmp/ccwcPdtV.s page 137 + + + 5487 .LBB678: + 5488 .LBB679: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5489 .loc 1 1142 0 + 5490 0178 0E24 movs r4, #14 + 5491 017a 6C44 add r4, r4, sp + 5492 017c 0122 movs r2, #1 + 5493 017e 2100 movs r1, r4 + 5494 0180 3220 movs r0, #50 + 5495 0182 FFF7FEFF bl SX1272ReadBuffer + 5496 .LVL703: + 5497 .LBE679: + 5498 .LBE678: +1360:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5499 .loc 1 1360 0 + 5500 0186 2278 ldrb r2, [r4] + 5501 0188 6A4B ldr r3, .L247 + 5502 018a 5A87 strh r2, [r3, #58] + 5503 018c 96E7 b .L229 + 5504 .L227: +1367:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. + 5505 .loc 1 1367 0 + 5506 018e 694C ldr r4, .L247 + 5507 0190 A38F ldrh r3, [r4, #60] + 5508 0192 6B49 ldr r1, .L247+12 + 5509 0194 5918 adds r1, r3, r1 + 5510 0196 D21A subs r2, r2, r3 + 5511 0198 D2B2 uxtb r2, r2 + 5512 .LVL704: + 5513 .LBB680: + 5514 .LBB681: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5515 .loc 1 1188 0 + 5516 019a 0020 movs r0, #0 + 5517 019c FFF7FEFF bl SX1272ReadBuffer + 5518 .LVL705: + 5519 .LBE681: + 5520 .LBE680: +1368:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5521 .loc 1 1368 0 + 5522 01a0 638F ldrh r3, [r4, #58] + 5523 01a2 A387 strh r3, [r4, #60] + 5524 .L230: +1371:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5525 .loc 1 1371 0 + 5526 01a4 6448 ldr r0, .L247+4 + 5527 01a6 FFF7FEFF bl TimerStop + 5528 .LVL706: +1373:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5529 .loc 1 1373 0 + 5530 01aa 624A ldr r2, .L247 + 5531 01ac 2623 movs r3, #38 + 5532 01ae D35C ldrb r3, [r2, r3] + 5533 01b0 002B cmp r3, #0 + 5534 01b2 1CD1 bne .L231 +1375:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); + 5535 .loc 1 1375 0 + ARM GAS /tmp/ccwcPdtV.s page 138 + + + 5536 01b4 1300 movs r3, r2 + 5537 01b6 0022 movs r2, #0 + 5538 01b8 1A71 strb r2, [r3, #4] +1376:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5539 .loc 1 1376 0 + 5540 01ba 6248 ldr r0, .L247+16 + 5541 01bc FFF7FEFF bl TimerStop + 5542 .LVL707: + 5543 .L232: +1385:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5544 .loc 1 1385 0 + 5545 01c0 5E4B ldr r3, .L247+8 + 5546 01c2 1B68 ldr r3, [r3] + 5547 01c4 002B cmp r3, #0 + 5548 01c6 09D0 beq .L233 +1385:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5549 .loc 1 1385 0 is_stmt 0 discriminator 1 + 5550 01c8 9C68 ldr r4, [r3, #8] + 5551 01ca 002C cmp r4, #0 + 5552 01cc 06D0 beq .L233 +1387:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5553 .loc 1 1387 0 is_stmt 1 + 5554 01ce 594B ldr r3, .L247 + 5555 01d0 3222 movs r2, #50 + 5556 01d2 9A56 ldrsb r2, [r3, r2] + 5557 01d4 598F ldrh r1, [r3, #58] + 5558 01d6 0023 movs r3, #0 + 5559 01d8 5948 ldr r0, .L247+12 + 5560 01da A047 blx r4 + 5561 .LVL708: + 5562 .L233: +1389:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + 5563 .loc 1 1389 0 + 5564 01dc 554B ldr r3, .L247 + 5565 01de 0022 movs r2, #0 + 5566 01e0 3021 movs r1, #48 + 5567 01e2 5A54 strb r2, [r3, r1] +1390:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 5568 .loc 1 1390 0 + 5569 01e4 0131 adds r1, r1, #1 + 5570 01e6 5A54 strb r2, [r3, r1] +1391:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; + 5571 .loc 1 1391 0 + 5572 01e8 9A87 strh r2, [r3, #60] +1392:./Drivers/BSP/Components/sx1272/sx1272.c **** break; + 5573 .loc 1 1392 0 + 5574 01ea 5A87 strh r2, [r3, #58] +1393:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: + 5575 .loc 1 1393 0 + 5576 01ec 15E7 b .L217 + 5577 .L231: + 5578 .LVL709: + 5579 .LBB682: + 5580 .LBB683: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5581 .loc 1 1142 0 + 5582 01ee 0E24 movs r4, #14 + ARM GAS /tmp/ccwcPdtV.s page 139 + + + 5583 01f0 6C44 add r4, r4, sp + 5584 01f2 0122 movs r2, #1 + 5585 01f4 2100 movs r1, r4 + 5586 01f6 0D20 movs r0, #13 + 5587 01f8 FFF7FEFF bl SX1272ReadBuffer + 5588 .LVL710: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5589 .loc 1 1143 0 + 5590 01fc 2378 ldrb r3, [r4] + 5591 .LVL711: + 5592 .LBE683: + 5593 .LBE682: +1381:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); + 5594 .loc 1 1381 0 + 5595 01fe 4022 movs r2, #64 + 5596 0200 1343 orrs r3, r2 + 5597 .LVL712: + 5598 0202 0A21 movs r1, #10 + 5599 0204 6944 add r1, r1, sp + 5600 0206 0B70 strb r3, [r1] + 5601 .LVL713: + 5602 .LBB684: + 5603 .LBB685: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5604 .loc 1 1136 0 + 5605 0208 0122 movs r2, #1 + 5606 020a 0D20 movs r0, #13 + 5607 020c FFF7FEFF bl SX1272WriteBuffer + 5608 .LVL714: + 5609 .LBE685: + 5610 .LBE684: +1382:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5611 .loc 1 1382 0 + 5612 0210 4C48 ldr r0, .L247+16 + 5613 0212 FFF7FEFF bl TimerStart + 5614 .LVL715: + 5615 0216 D3E7 b .L232 + 5616 .LVL716: + 5617 .L234: + 5618 .LBB686: + 5619 .LBB652: + 5620 .LBB653: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5621 .loc 1 1142 0 + 5622 0218 0E24 movs r4, #14 + 5623 021a 6C44 add r4, r4, sp + 5624 021c 0122 movs r2, #1 + 5625 021e 2100 movs r1, r4 + 5626 0220 1920 movs r0, #25 + 5627 0222 FFF7FEFF bl SX1272ReadBuffer + 5628 .LVL717: + 5629 .LBE653: + 5630 .LBE652: +1420:./Drivers/BSP/Components/sx1272/sx1272.c **** if( SX1272.Settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is + 5631 .loc 1 1420 0 + 5632 0226 0023 movs r3, #0 + 5633 0228 E356 ldrsb r3, [r4, r3] + ARM GAS /tmp/ccwcPdtV.s page 140 + + + 5634 022a 4249 ldr r1, .L247 + 5635 022c 6022 movs r2, #96 + 5636 022e 8B54 strb r3, [r1, r2] +1421:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5637 .loc 1 1421 0 + 5638 0230 002B cmp r3, #0 + 5639 0232 50DB blt .L244 +1430:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5640 .loc 1 1430 0 + 5641 0234 9B10 asrs r3, r3, #2 + 5642 0236 3F24 movs r4, #63 + 5643 0238 1C40 ands r4, r3 + 5644 .LVL718: + 5645 .L237: + 5646 .LBB654: + 5647 .LBB655: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5648 .loc 1 1142 0 + 5649 023a 0E25 movs r5, #14 + 5650 023c 6D44 add r5, r5, sp + 5651 023e 0122 movs r2, #1 + 5652 0240 2900 movs r1, r5 + 5653 0242 1A20 movs r0, #26 + 5654 0244 FFF7FEFF bl SX1272ReadBuffer + 5655 .LVL719: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5656 .loc 1 1143 0 + 5657 0248 2A78 ldrb r2, [r5] + 5658 .LVL720: + 5659 .LBE655: + 5660 .LBE654: +1433:./Drivers/BSP/Components/sx1272/sx1272.c **** if( snr < 0 ) + 5661 .loc 1 1433 0 + 5662 024a 13B2 sxth r3, r2 + 5663 .LVL721: +1434:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5664 .loc 1 1434 0 + 5665 024c 002C cmp r4, #0 + 5666 024e 48DB blt .L245 +1441:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5667 .loc 1 1441 0 + 5668 0250 1B11 asrs r3, r3, #4 + 5669 .LVL722: + 5670 0252 9B18 adds r3, r3, r2 + 5671 0254 8B3B subs r3, r3, #139 + 5672 0256 3749 ldr r1, .L247 + 5673 0258 6222 movs r2, #98 + 5674 .LVL723: + 5675 025a 8B52 strh r3, [r1, r2] + 5676 .L239: + 5677 .LVL724: + 5678 .LBB656: + 5679 .LBB657: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5680 .loc 1 1142 0 + 5681 025c 0E24 movs r4, #14 + 5682 .LVL725: + ARM GAS /tmp/ccwcPdtV.s page 141 + + + 5683 025e 6C44 add r4, r4, sp + 5684 0260 0122 movs r2, #1 + 5685 0262 2100 movs r1, r4 + 5686 0264 1320 movs r0, #19 + 5687 0266 FFF7FEFF bl SX1272ReadBuffer + 5688 .LVL726: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5689 .loc 1 1143 0 + 5690 026a 2378 ldrb r3, [r4] + 5691 .LVL727: + 5692 .LBE657: + 5693 .LBE656: +1444:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( REG_LR_FIFOADDRPTR, SX1272Read( REG_LR_FIFORXCURRENTADDR ) ); + 5694 .loc 1 1444 0 + 5695 026c 314D ldr r5, .L247 + 5696 026e 6426 movs r6, #100 + 5697 0270 AB55 strb r3, [r5, r6] + 5698 .LVL728: + 5699 .LBB658: + 5700 .LBB659: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 5701 .loc 1 1142 0 + 5702 0272 0122 movs r2, #1 + 5703 0274 2100 movs r1, r4 + 5704 0276 1020 movs r0, #16 + 5705 0278 FFF7FEFF bl SX1272ReadBuffer + 5706 .LVL729: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5707 .loc 1 1143 0 + 5708 027c 2378 ldrb r3, [r4] + 5709 .LVL730: + 5710 027e 0D21 movs r1, #13 + 5711 0280 6944 add r1, r1, sp + 5712 0282 0B70 strb r3, [r1] + 5713 .LVL731: + 5714 .LBE659: + 5715 .LBE658: + 5716 .LBB660: + 5717 .LBB661: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5718 .loc 1 1136 0 + 5719 0284 0122 movs r2, #1 + 5720 0286 0D20 movs r0, #13 + 5721 0288 FFF7FEFF bl SX1272WriteBuffer + 5722 .LVL732: + 5723 .LBE661: + 5724 .LBE660: +1446:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5725 .loc 1 1446 0 + 5726 028c AA5D ldrb r2, [r5, r6] + 5727 .LVL733: + 5728 .LBB662: + 5729 .LBB663: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5730 .loc 1 1188 0 + 5731 028e 2C49 ldr r1, .L247+12 + 5732 0290 0020 movs r0, #0 + ARM GAS /tmp/ccwcPdtV.s page 142 + + + 5733 0292 FFF7FEFF bl SX1272ReadBuffer + 5734 .LVL734: + 5735 .LBE663: + 5736 .LBE662: +1448:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5737 .loc 1 1448 0 + 5738 0296 5623 movs r3, #86 + 5739 0298 EB5C ldrb r3, [r5, r3] + 5740 029a 002B cmp r3, #0 + 5741 029c 02D1 bne .L240 +1450:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5742 .loc 1 1450 0 + 5743 029e 254B ldr r3, .L247 + 5744 02a0 0022 movs r2, #0 + 5745 02a2 1A71 strb r2, [r3, #4] + 5746 .L240: +1452:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5747 .loc 1 1452 0 + 5748 02a4 2448 ldr r0, .L247+4 + 5749 02a6 FFF7FEFF bl TimerStop + 5750 .LVL735: +1454:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5751 .loc 1 1454 0 + 5752 02aa 244B ldr r3, .L247+8 + 5753 02ac 1B68 ldr r3, [r3] + 5754 02ae 002B cmp r3, #0 + 5755 02b0 00D1 bne .LCB5723 + 5756 02b2 B2E6 b .L217 @long jump + 5757 .LCB5723: +1454:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5758 .loc 1 1454 0 is_stmt 0 discriminator 1 + 5759 02b4 9C68 ldr r4, [r3, #8] + 5760 02b6 002C cmp r4, #0 + 5761 02b8 00D1 bne .LCB5726 + 5762 02ba AEE6 b .L217 @long jump + 5763 .LCB5726: +1456:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "rxDone\n\r" ); + 5764 .loc 1 1456 0 is_stmt 1 + 5765 02bc 1D49 ldr r1, .L247 + 5766 02be 6023 movs r3, #96 + 5767 02c0 CB56 ldrsb r3, [r1, r3] + 5768 02c2 6222 movs r2, #98 + 5769 02c4 8A5E ldrsh r2, [r1, r2] + 5770 02c6 6420 movs r0, #100 + 5771 02c8 095C ldrb r1, [r1, r0] + 5772 02ca 1D48 ldr r0, .L247+12 + 5773 02cc A047 blx r4 + 5774 .LVL736: +1457:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5775 .loc 1 1457 0 + 5776 02ce 1E48 ldr r0, .L247+20 + 5777 02d0 FFF7FEFF bl vcom_Send + 5778 .LVL737: + 5779 02d4 A1E6 b .L217 + 5780 .LVL738: + 5781 .L244: +1424:./Drivers/BSP/Components/sx1272/sx1272.c **** snr = -snr; + ARM GAS /tmp/ccwcPdtV.s page 143 + + + 5782 .loc 1 1424 0 + 5783 02d6 5B42 rsbs r3, r3, #0 + 5784 02d8 9B10 asrs r3, r3, #2 + 5785 02da 3F24 movs r4, #63 + 5786 02dc 1C40 ands r4, r3 + 5787 .LVL739: +1425:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5788 .loc 1 1425 0 + 5789 02de 6442 rsbs r4, r4, #0 + 5790 .LVL740: + 5791 02e0 ABE7 b .L237 + 5792 .LVL741: + 5793 .L245: +1436:./Drivers/BSP/Components/sx1272/sx1272.c **** snr; + 5794 .loc 1 1436 0 + 5795 02e2 1B11 asrs r3, r3, #4 + 5796 .LVL742: + 5797 02e4 9B18 adds r3, r3, r2 + 5798 02e6 1B19 adds r3, r3, r4 + 5799 02e8 8B3B subs r3, r3, #139 + 5800 02ea 1249 ldr r1, .L247 + 5801 02ec 6222 movs r2, #98 + 5802 .LVL743: + 5803 02ee 8B52 strh r3, [r1, r2] + 5804 02f0 B4E7 b .L239 + 5805 .LVL744: + 5806 .L220: + 5807 .LBE686: +1466:./Drivers/BSP/Components/sx1272/sx1272.c **** // TxDone interrupt + 5808 .loc 1 1466 0 + 5809 02f2 1648 ldr r0, .L247+24 + 5810 02f4 FFF7FEFF bl TimerStop + 5811 .LVL745: +1468:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5812 .loc 1 1468 0 + 5813 02f8 0E4B ldr r3, .L247 + 5814 02fa 5B79 ldrb r3, [r3, #5] + 5815 02fc 012B cmp r3, #1 + 5816 02fe 10D0 beq .L246 + 5817 .L241: +1476:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + 5818 .loc 1 1476 0 + 5819 0300 0C4B ldr r3, .L247 + 5820 0302 0022 movs r2, #0 + 5821 0304 1A71 strb r2, [r3, #4] +1477:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5822 .loc 1 1477 0 + 5823 0306 0D4B ldr r3, .L247+8 + 5824 0308 1B68 ldr r3, [r3] + 5825 030a 002B cmp r3, #0 + 5826 030c 00D1 bne .LCB5797 + 5827 030e 84E6 b .L217 @long jump + 5828 .LCB5797: +1477:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5829 .loc 1 1477 0 is_stmt 0 discriminator 1 + 5830 0310 1B68 ldr r3, [r3] + 5831 0312 002B cmp r3, #0 + ARM GAS /tmp/ccwcPdtV.s page 144 + + + 5832 0314 00D1 bne .LCB5800 + 5833 0316 80E6 b .L217 @long jump + 5834 .LCB5800: +1479:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "txDone\n\r" ); + 5835 .loc 1 1479 0 is_stmt 1 + 5836 0318 9847 blx r3 + 5837 .LVL746: +1480:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5838 .loc 1 1480 0 + 5839 031a 0D48 ldr r0, .L247+28 + 5840 031c FFF7FEFF bl vcom_Send + 5841 .LVL747: +1488:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5842 .loc 1 1488 0 + 5843 0320 7BE6 b .L217 + 5844 .L246: + 5845 .LVL748: + 5846 0322 0E21 movs r1, #14 + 5847 0324 6944 add r1, r1, sp + 5848 0326 0733 adds r3, r3, #7 + 5849 0328 0B70 strb r3, [r1] + 5850 .LVL749: + 5851 .LBB687: + 5852 .LBB688: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5853 .loc 1 1136 0 + 5854 032a 0122 movs r2, #1 + 5855 032c 1220 movs r0, #18 + 5856 032e FFF7FEFF bl SX1272WriteBuffer + 5857 .LVL750: + 5858 0332 E5E7 b .L241 + 5859 .L248: + 5860 .align 2 + 5861 .L247: + 5862 0334 00000000 .word .LANCHOR0 + 5863 0338 00000000 .word .LANCHOR2 + 5864 033c 00000000 .word .LANCHOR5 + 5865 0340 00000000 .word RxTxBuffer + 5866 0344 00000000 .word .LANCHOR4 + 5867 0348 00000000 .word .LC47 + 5868 034c 00000000 .word .LANCHOR3 + 5869 0350 0C000000 .word .LC50 + 5870 .LBE688: + 5871 .LBE687: + 5872 .cfi_endproc + 5873 .LFE127: + 5875 .section .text.SX1272OnDio1Irq,"ax",%progbits + 5876 .align 1 + 5877 .global SX1272OnDio1Irq + 5878 .syntax unified + 5879 .code 16 + 5880 .thumb_func + 5881 .fpu softvfp + 5883 SX1272OnDio1Irq: + 5884 .LFB128: +1491:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) + 5885 .loc 1 1491 0 + ARM GAS /tmp/ccwcPdtV.s page 145 + + + 5886 .cfi_startproc + 5887 @ args = 0, pretend = 0, frame = 8 + 5888 @ frame_needed = 0, uses_anonymous_args = 0 + 5889 0000 10B5 push {r4, lr} + 5890 .LCFI47: + 5891 .cfi_def_cfa_offset 8 + 5892 .cfi_offset 4, -8 + 5893 .cfi_offset 14, -4 + 5894 0002 82B0 sub sp, sp, #8 + 5895 .LCFI48: + 5896 .cfi_def_cfa_offset 16 +1492:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5897 .loc 1 1492 0 + 5898 0004 434B ldr r3, .L261 + 5899 0006 1B79 ldrb r3, [r3, #4] + 5900 0008 012B cmp r3, #1 + 5901 000a 03D0 beq .L251 + 5902 000c 022B cmp r3, #2 + 5903 000e 5ED0 beq .L252 + 5904 .L249: +1566:./Drivers/BSP/Components/sx1272/sx1272.c **** + 5905 .loc 1 1566 0 + 5906 0010 02B0 add sp, sp, #8 + 5907 @ sp needed + 5908 0012 10BD pop {r4, pc} + 5909 .L251: +1495:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5910 .loc 1 1495 0 + 5911 0014 3F4B ldr r3, .L261 + 5912 0016 5B79 ldrb r3, [r3, #5] + 5913 0018 002B cmp r3, #0 + 5914 001a 1BD0 beq .L253 + 5915 001c 012B cmp r3, #1 + 5916 001e F7D1 bne .L249 +1525:./Drivers/BSP/Components/sx1272/sx1272.c **** // Clear Irq + 5917 .loc 1 1525 0 + 5918 0020 3D48 ldr r0, .L261+4 + 5919 0022 FFF7FEFF bl TimerStop + 5920 .LVL751: + 5921 0026 6B46 mov r3, sp + 5922 0028 D91D adds r1, r3, #7 + 5923 002a 8023 movs r3, #128 + 5924 002c 0B70 strb r3, [r1] + 5925 .LVL752: + 5926 .LBB689: + 5927 .LBB690: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5928 .loc 1 1136 0 + 5929 002e 0122 movs r2, #1 + 5930 0030 1220 movs r0, #18 + 5931 0032 FFF7FEFF bl SX1272WriteBuffer + 5932 .LVL753: + 5933 .LBE690: + 5934 .LBE689: +1529:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 5935 .loc 1 1529 0 + 5936 0036 374B ldr r3, .L261 + ARM GAS /tmp/ccwcPdtV.s page 146 + + + 5937 0038 0022 movs r2, #0 + 5938 003a 1A71 strb r2, [r3, #4] +1530:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5939 .loc 1 1530 0 + 5940 003c 374B ldr r3, .L261+8 + 5941 003e 1B68 ldr r3, [r3] + 5942 0040 002B cmp r3, #0 + 5943 0042 E5D0 beq .L249 +1530:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5944 .loc 1 1530 0 is_stmt 0 discriminator 1 + 5945 0044 DB68 ldr r3, [r3, #12] + 5946 0046 002B cmp r3, #0 + 5947 0048 E2D0 beq .L249 +1532:./Drivers/BSP/Components/sx1272/sx1272.c **** PRINTF( "rxTimeOut\n\r" ); + 5948 .loc 1 1532 0 is_stmt 1 + 5949 004a 9847 blx r3 + 5950 .LVL754: +1533:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5951 .loc 1 1533 0 + 5952 004c 3448 ldr r0, .L261+12 + 5953 004e FFF7FEFF bl vcom_Send + 5954 .LVL755: + 5955 0052 DDE7 b .L249 + 5956 .L253: +1500:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5957 .loc 1 1500 0 + 5958 0054 2F4B ldr r3, .L261 + 5959 0056 5B8F ldrh r3, [r3, #58] + 5960 0058 002B cmp r3, #0 + 5961 005a 0ED1 bne .L255 +1500:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5962 .loc 1 1500 0 is_stmt 0 discriminator 1 + 5963 005c 2D4B ldr r3, .L261 + 5964 005e 9B8F ldrh r3, [r3, #60] + 5965 0060 002B cmp r3, #0 + 5966 0062 0AD1 bne .L255 +1502:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5967 .loc 1 1502 0 is_stmt 1 + 5968 0064 2B4A ldr r2, .L261 + 5969 0066 2233 adds r3, r3, #34 + 5970 0068 D35C ldrb r3, [r2, r3] + 5971 006a 002B cmp r3, #0 + 5972 006c 19D1 bne .L256 + 5973 .LVL756: + 5974 .LBB691: + 5975 .LBB692: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 5976 .loc 1 1188 0 + 5977 006e 1100 movs r1, r2 + 5978 0070 0122 movs r2, #1 + 5979 0072 3A31 adds r1, r1, #58 + 5980 0074 0020 movs r0, #0 + 5981 0076 FFF7FEFF bl SX1272ReadBuffer + 5982 .LVL757: + 5983 .L255: + 5984 .LBE692: + 5985 .LBE691: + ARM GAS /tmp/ccwcPdtV.s page 147 + + +1512:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 5986 .loc 1 1512 0 + 5987 007a 264A ldr r2, .L261 + 5988 007c 538F ldrh r3, [r2, #58] + 5989 007e 908F ldrh r0, [r2, #60] + 5990 0080 191A subs r1, r3, r0 + 5991 0082 3E24 movs r4, #62 + 5992 0084 125D ldrb r2, [r2, r4] + 5993 0086 9142 cmp r1, r2 + 5994 0088 16DD ble .L257 +1514:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Fi + 5995 .loc 1 1514 0 + 5996 008a 2649 ldr r1, .L261+16 + 5997 008c 4118 adds r1, r0, r1 + 5998 .LVL758: + 5999 .LBB693: + 6000 .LBB694: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6001 .loc 1 1188 0 + 6002 008e 0020 movs r0, #0 + 6003 0090 FFF7FEFF bl SX1272ReadBuffer + 6004 .LVL759: + 6005 .LBE694: + 6006 .LBE693: +1515:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6007 .loc 1 1515 0 + 6008 0094 1F4B ldr r3, .L261 + 6009 0096 3E22 movs r2, #62 + 6010 0098 9A5C ldrb r2, [r3, r2] + 6011 009a 998F ldrh r1, [r3, #60] + 6012 009c 5218 adds r2, r2, r1 + 6013 009e 9A87 strh r2, [r3, #60] + 6014 00a0 B6E7 b .L249 + 6015 .L256: + 6016 .LVL760: + 6017 .LBB695: + 6018 .LBB696: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 6019 .loc 1 1142 0 + 6020 00a2 6B46 mov r3, sp + 6021 00a4 DC1D adds r4, r3, #7 + 6022 00a6 0122 movs r2, #1 + 6023 00a8 2100 movs r1, r4 + 6024 00aa 3220 movs r0, #50 + 6025 00ac FFF7FEFF bl SX1272ReadBuffer + 6026 .LVL761: + 6027 .LBE696: + 6028 .LBE695: +1508:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6029 .loc 1 1508 0 + 6030 00b0 2278 ldrb r2, [r4] + 6031 00b2 184B ldr r3, .L261 + 6032 00b4 5A87 strh r2, [r3, #58] + 6033 00b6 E0E7 b .L255 + 6034 .L257: +1519:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += ( SX1272.Settings.FskPacketHandler. + 6035 .loc 1 1519 0 + ARM GAS /tmp/ccwcPdtV.s page 148 + + + 6036 00b8 1A49 ldr r1, .L261+16 + 6037 00ba 4118 adds r1, r0, r1 + 6038 00bc 1A1A subs r2, r3, r0 + 6039 00be D2B2 uxtb r2, r2 + 6040 .LVL762: + 6041 .LBB697: + 6042 .LBB698: +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6043 .loc 1 1188 0 + 6044 00c0 0020 movs r0, #0 + 6045 00c2 FFF7FEFF bl SX1272ReadBuffer + 6046 .LVL763: + 6047 .LBE698: + 6048 .LBE697: +1520:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6049 .loc 1 1520 0 + 6050 00c6 134B ldr r3, .L261 + 6051 00c8 5A8F ldrh r2, [r3, #58] + 6052 00ca 9A87 strh r2, [r3, #60] + 6053 00cc A0E7 b .L249 + 6054 .L252: +1541:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6055 .loc 1 1541 0 + 6056 00ce 114B ldr r3, .L261 + 6057 00d0 5B79 ldrb r3, [r3, #5] + 6058 00d2 002B cmp r3, #0 + 6059 00d4 9CD1 bne .L249 +1545:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6060 .loc 1 1545 0 + 6061 00d6 0F4A ldr r2, .L261 + 6062 00d8 538F ldrh r3, [r2, #58] + 6063 00da 908F ldrh r0, [r2, #60] + 6064 00dc 191A subs r1, r3, r0 + 6065 00de 3F24 movs r4, #63 + 6066 00e0 125D ldrb r2, [r2, r4] + 6067 00e2 9142 cmp r1, r2 + 6068 00e4 0ADC bgt .L260 +1553:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Si + 6069 .loc 1 1553 0 + 6070 00e6 0F49 ldr r1, .L261+16 + 6071 00e8 4118 adds r1, r0, r1 + 6072 00ea 1A1A subs r2, r3, r0 + 6073 00ec D2B2 uxtb r2, r2 + 6074 .LVL764: + 6075 .LBB699: + 6076 .LBB700: +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6077 .loc 1 1183 0 + 6078 00ee 0020 movs r0, #0 + 6079 00f0 FFF7FEFF bl SX1272WriteBuffer + 6080 .LVL765: + 6081 .LBE700: + 6082 .LBE699: +1554:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6083 .loc 1 1554 0 + 6084 00f4 074B ldr r3, .L261 + 6085 00f6 5A8F ldrh r2, [r3, #58] + ARM GAS /tmp/ccwcPdtV.s page 149 + + + 6086 00f8 9A87 strh r2, [r3, #60] +1566:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6087 .loc 1 1566 0 + 6088 00fa 89E7 b .L249 + 6089 .L260: +1547:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.Ch + 6090 .loc 1 1547 0 + 6091 00fc 0949 ldr r1, .L261+16 + 6092 00fe 4118 adds r1, r0, r1 + 6093 .LVL766: + 6094 .LBB701: + 6095 .LBB702: +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6096 .loc 1 1183 0 + 6097 0100 0020 movs r0, #0 + 6098 0102 FFF7FEFF bl SX1272WriteBuffer + 6099 .LVL767: + 6100 .LBE702: + 6101 .LBE701: +1548:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6102 .loc 1 1548 0 + 6103 0106 034B ldr r3, .L261 + 6104 0108 3F22 movs r2, #63 + 6105 010a 9A5C ldrb r2, [r3, r2] + 6106 010c 998F ldrh r1, [r3, #60] + 6107 010e 5218 adds r2, r2, r1 + 6108 0110 9A87 strh r2, [r3, #60] + 6109 0112 7DE7 b .L249 + 6110 .L262: + 6111 .align 2 + 6112 .L261: + 6113 0114 00000000 .word .LANCHOR0 + 6114 0118 00000000 .word .LANCHOR2 + 6115 011c 00000000 .word .LANCHOR5 + 6116 0120 00000000 .word .LC56 + 6117 0124 00000000 .word RxTxBuffer + 6118 .cfi_endproc + 6119 .LFE128: + 6121 .section .text.SX1272WriteFifo,"ax",%progbits + 6122 .align 1 + 6123 .global SX1272WriteFifo + 6124 .syntax unified + 6125 .code 16 + 6126 .thumb_func + 6127 .fpu softvfp + 6129 SX1272WriteFifo: + 6130 .LFB121: +1182:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272WriteBuffer( 0, buffer, size ); + 6131 .loc 1 1182 0 + 6132 .cfi_startproc + 6133 @ args = 0, pretend = 0, frame = 0 + 6134 @ frame_needed = 0, uses_anonymous_args = 0 + 6135 .LVL768: + 6136 0000 10B5 push {r4, lr} + 6137 .LCFI49: + 6138 .cfi_def_cfa_offset 8 + 6139 .cfi_offset 4, -8 + ARM GAS /tmp/ccwcPdtV.s page 150 + + + 6140 .cfi_offset 14, -4 + 6141 0002 0A00 movs r2, r1 +1183:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6142 .loc 1 1183 0 + 6143 0004 0100 movs r1, r0 + 6144 .LVL769: + 6145 0006 0020 movs r0, #0 + 6146 .LVL770: + 6147 0008 FFF7FEFF bl SX1272WriteBuffer + 6148 .LVL771: +1184:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6149 .loc 1 1184 0 + 6150 @ sp needed + 6151 000c 10BD pop {r4, pc} + 6152 .cfi_endproc + 6153 .LFE121: + 6155 .section .text.SX1272ReadFifo,"ax",%progbits + 6156 .align 1 + 6157 .global SX1272ReadFifo + 6158 .syntax unified + 6159 .code 16 + 6160 .thumb_func + 6161 .fpu softvfp + 6163 SX1272ReadFifo: + 6164 .LFB122: +1187:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272ReadBuffer( 0, buffer, size ); + 6165 .loc 1 1187 0 + 6166 .cfi_startproc + 6167 @ args = 0, pretend = 0, frame = 0 + 6168 @ frame_needed = 0, uses_anonymous_args = 0 + 6169 .LVL772: + 6170 0000 10B5 push {r4, lr} + 6171 .LCFI50: + 6172 .cfi_def_cfa_offset 8 + 6173 .cfi_offset 4, -8 + 6174 .cfi_offset 14, -4 + 6175 0002 0A00 movs r2, r1 +1188:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6176 .loc 1 1188 0 + 6177 0004 0100 movs r1, r0 + 6178 .LVL773: + 6179 0006 0020 movs r0, #0 + 6180 .LVL774: + 6181 0008 FFF7FEFF bl SX1272ReadBuffer + 6182 .LVL775: +1189:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6183 .loc 1 1189 0 + 6184 @ sp needed + 6185 000c 10BD pop {r4, pc} + 6186 .cfi_endproc + 6187 .LFE122: + 6189 .section .text.SX1272SetMaxPayloadLength,"ax",%progbits + 6190 .align 1 + 6191 .global SX1272SetMaxPayloadLength + 6192 .syntax unified + 6193 .code 16 + 6194 .thumb_func + ARM GAS /tmp/ccwcPdtV.s page 151 + + + 6195 .fpu softvfp + 6197 SX1272SetMaxPayloadLength: + 6198 .LFB123: +1192:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( modem ); + 6199 .loc 1 1192 0 + 6200 .cfi_startproc + 6201 @ args = 0, pretend = 0, frame = 8 + 6202 @ frame_needed = 0, uses_anonymous_args = 0 + 6203 .LVL776: + 6204 0000 30B5 push {r4, r5, lr} + 6205 .LCFI51: + 6206 .cfi_def_cfa_offset 12 + 6207 .cfi_offset 4, -12 + 6208 .cfi_offset 5, -8 + 6209 .cfi_offset 14, -4 + 6210 0002 83B0 sub sp, sp, #12 + 6211 .LCFI52: + 6212 .cfi_def_cfa_offset 24 + 6213 0004 0400 movs r4, r0 + 6214 0006 0D00 movs r5, r1 +1193:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6215 .loc 1 1193 0 + 6216 0008 FFF7FEFF bl SX1272SetModem + 6217 .LVL777: +1195:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6218 .loc 1 1195 0 + 6219 000c 002C cmp r4, #0 + 6220 000e 03D0 beq .L267 + 6221 0010 012C cmp r4, #1 + 6222 0012 0ED0 beq .L268 + 6223 .L265: +1207:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6224 .loc 1 1207 0 + 6225 0014 03B0 add sp, sp, #12 + 6226 @ sp needed + 6227 0016 30BD pop {r4, r5, pc} + 6228 .L267: +1198:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6229 .loc 1 1198 0 + 6230 0018 0A4A ldr r2, .L269 + 6231 001a 2223 movs r3, #34 + 6232 001c D35C ldrb r3, [r2, r3] + 6233 001e 002B cmp r3, #0 + 6234 0020 F8D1 bne .L265 + 6235 .LVL778: + 6236 0022 6B46 mov r3, sp + 6237 0024 991D adds r1, r3, #6 + 6238 0026 0D70 strb r5, [r1] + 6239 .LVL779: + 6240 .LBB703: + 6241 .LBB704: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6242 .loc 1 1136 0 + 6243 0028 0122 movs r2, #1 + 6244 002a 3220 movs r0, #50 + 6245 002c FFF7FEFF bl SX1272WriteBuffer + 6246 .LVL780: + ARM GAS /tmp/ccwcPdtV.s page 152 + + + 6247 0030 F0E7 b .L265 + 6248 .LVL781: + 6249 .L268: + 6250 0032 6B46 mov r3, sp + 6251 0034 D91D adds r1, r3, #7 + 6252 0036 0D70 strb r5, [r1] + 6253 .LVL782: + 6254 .LBE704: + 6255 .LBE703: + 6256 .LBB705: + 6257 .LBB706: + 6258 0038 0122 movs r2, #1 + 6259 003a 2320 movs r0, #35 + 6260 003c FFF7FEFF bl SX1272WriteBuffer + 6261 .LVL783: + 6262 .LBE706: + 6263 .LBE705: +1207:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6264 .loc 1 1207 0 + 6265 0040 E8E7 b .L265 + 6266 .L270: + 6267 0042 C046 .align 2 + 6268 .L269: + 6269 0044 00000000 .word .LANCHOR0 + 6270 .cfi_endproc + 6271 .LFE123: + 6273 .section .text.SX1272SetPublicNetwork,"ax",%progbits + 6274 .align 1 + 6275 .global SX1272SetPublicNetwork + 6276 .syntax unified + 6277 .code 16 + 6278 .thumb_func + 6279 .fpu softvfp + 6281 SX1272SetPublicNetwork: + 6282 .LFB124: +1210:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272SetModem( MODEM_LORA ); + 6283 .loc 1 1210 0 + 6284 .cfi_startproc + 6285 @ args = 0, pretend = 0, frame = 8 + 6286 @ frame_needed = 0, uses_anonymous_args = 0 + 6287 .LVL784: + 6288 0000 10B5 push {r4, lr} + 6289 .LCFI53: + 6290 .cfi_def_cfa_offset 8 + 6291 .cfi_offset 4, -8 + 6292 .cfi_offset 14, -4 + 6293 0002 82B0 sub sp, sp, #8 + 6294 .LCFI54: + 6295 .cfi_def_cfa_offset 16 + 6296 0004 0400 movs r4, r0 +1211:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.LoRa.PublicNetwork = enable; + 6297 .loc 1 1211 0 + 6298 0006 0120 movs r0, #1 + 6299 .LVL785: + 6300 0008 FFF7FEFF bl SX1272SetModem + 6301 .LVL786: +1212:./Drivers/BSP/Components/sx1272/sx1272.c **** if( enable == true ) + ARM GAS /tmp/ccwcPdtV.s page 153 + + + 6302 .loc 1 1212 0 + 6303 000c 0B4A ldr r2, .L275 + 6304 000e 5C23 movs r3, #92 + 6305 0010 D454 strb r4, [r2, r3] +1213:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6306 .loc 1 1213 0 + 6307 0012 002C cmp r4, #0 + 6308 0014 09D1 bne .L274 + 6309 .LVL787: + 6310 0016 6B46 mov r3, sp + 6311 0018 D91D adds r1, r3, #7 + 6312 001a 1223 movs r3, #18 + 6313 001c 0B70 strb r3, [r1] + 6314 .LVL788: + 6315 .LBB707: + 6316 .LBB708: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6317 .loc 1 1136 0 + 6318 001e 0122 movs r2, #1 + 6319 0020 3920 movs r0, #57 + 6320 0022 FFF7FEFF bl SX1272WriteBuffer + 6321 .LVL789: + 6322 .L271: + 6323 .LBE708: + 6324 .LBE707: +1223:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6325 .loc 1 1223 0 + 6326 0026 02B0 add sp, sp, #8 + 6327 @ sp needed + 6328 0028 10BD pop {r4, pc} + 6329 .L274: + 6330 .LVL790: + 6331 002a 6B46 mov r3, sp + 6332 002c 991D adds r1, r3, #6 + 6333 002e 3423 movs r3, #52 + 6334 0030 0B70 strb r3, [r1] + 6335 .LVL791: + 6336 .LBB709: + 6337 .LBB710: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6338 .loc 1 1136 0 + 6339 0032 0122 movs r2, #1 + 6340 0034 3920 movs r0, #57 + 6341 0036 FFF7FEFF bl SX1272WriteBuffer + 6342 .LVL792: + 6343 003a F4E7 b .L271 + 6344 .L276: + 6345 .align 2 + 6346 .L275: + 6347 003c 00000000 .word .LANCHOR0 + 6348 .LBE710: + 6349 .LBE709: + 6350 .cfi_endproc + 6351 .LFE124: + 6353 .section .text.SX1272OnTimeoutIrq,"ax",%progbits + 6354 .align 1 + 6355 .global SX1272OnTimeoutIrq + ARM GAS /tmp/ccwcPdtV.s page 154 + + + 6356 .syntax unified + 6357 .code 16 + 6358 .thumb_func + 6359 .fpu softvfp + 6361 SX1272OnTimeoutIrq: + 6362 .LFB126: +1231:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.State ) + 6363 .loc 1 1231 0 + 6364 .cfi_startproc + 6365 @ args = 0, pretend = 0, frame = 8 + 6366 @ frame_needed = 0, uses_anonymous_args = 0 + 6367 0000 70B5 push {r4, r5, r6, lr} + 6368 .LCFI55: + 6369 .cfi_def_cfa_offset 16 + 6370 .cfi_offset 4, -16 + 6371 .cfi_offset 5, -12 + 6372 .cfi_offset 6, -8 + 6373 .cfi_offset 14, -4 + 6374 0002 82B0 sub sp, sp, #8 + 6375 .LCFI56: + 6376 .cfi_def_cfa_offset 24 +1232:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6377 .loc 1 1232 0 + 6378 0004 3C4B ldr r3, .L286 + 6379 0006 1B79 ldrb r3, [r3, #4] + 6380 0008 012B cmp r3, #1 + 6381 000a 03D0 beq .L279 + 6382 000c 022B cmp r3, #2 + 6383 000e 44D0 beq .L280 + 6384 .L277: +1300:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6385 .loc 1 1300 0 + 6386 0010 02B0 add sp, sp, #8 + 6387 @ sp needed + 6388 0012 70BD pop {r4, r5, r6, pc} + 6389 .L279: +1235:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6390 .loc 1 1235 0 + 6391 0014 384B ldr r3, .L286 + 6392 0016 5B79 ldrb r3, [r3, #5] + 6393 0018 002B cmp r3, #0 + 6394 001a 08D0 beq .L285 + 6395 .L281: +1260:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6396 .loc 1 1260 0 + 6397 001c 374B ldr r3, .L286+4 + 6398 001e 1B68 ldr r3, [r3] + 6399 0020 002B cmp r3, #0 + 6400 0022 F5D0 beq .L277 +1260:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6401 .loc 1 1260 0 is_stmt 0 discriminator 1 + 6402 0024 DB68 ldr r3, [r3, #12] + 6403 0026 002B cmp r3, #0 + 6404 0028 F2D0 beq .L277 +1262:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6405 .loc 1 1262 0 is_stmt 1 + 6406 002a 9847 blx r3 + ARM GAS /tmp/ccwcPdtV.s page 155 + + + 6407 .LVL793: + 6408 002c F0E7 b .L277 + 6409 .L285: +1237:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.SyncWordDetected = false; + 6410 .loc 1 1237 0 + 6411 002e 324C ldr r4, .L286 + 6412 0030 3022 movs r2, #48 + 6413 0032 A354 strb r3, [r4, r2] +1238:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.NbBytes = 0; + 6414 .loc 1 1238 0 + 6415 0034 0132 adds r2, r2, #1 + 6416 0036 A354 strb r3, [r4, r2] +1239:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272.Settings.FskPacketHandler.Size = 0; + 6417 .loc 1 1239 0 + 6418 0038 A387 strh r3, [r4, #60] +1240:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6419 .loc 1 1240 0 + 6420 003a 6387 strh r3, [r4, #58] + 6421 .LVL794: + 6422 003c 6B46 mov r3, sp + 6423 003e 591D adds r1, r3, #5 + 6424 0040 0B23 movs r3, #11 + 6425 0042 0B70 strb r3, [r1] + 6426 .LVL795: + 6427 .LBB711: + 6428 .LBB712: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6429 .loc 1 1136 0 + 6430 0044 303A subs r2, r2, #48 + 6431 0046 3E20 movs r0, #62 + 6432 0048 FFF7FEFF bl SX1272WriteBuffer + 6433 .LVL796: + 6434 004c 01A9 add r1, sp, #4 + 6435 004e 1023 movs r3, #16 + 6436 0050 0B70 strb r3, [r1] + 6437 .LVL797: + 6438 .LBE712: + 6439 .LBE711: + 6440 .LBB713: + 6441 .LBB714: + 6442 0052 0122 movs r2, #1 + 6443 0054 3F20 movs r0, #63 + 6444 0056 FFF7FEFF bl SX1272WriteBuffer + 6445 .LVL798: + 6446 .LBE714: + 6447 .LBE713: +1248:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6448 .loc 1 1248 0 + 6449 005a 2623 movs r3, #38 + 6450 005c E35C ldrb r3, [r4, r3] + 6451 005e 002B cmp r3, #0 + 6452 0060 14D0 beq .L282 + 6453 .LVL799: + 6454 .LBB715: + 6455 .LBB716: +1142:./Drivers/BSP/Components/sx1272/sx1272.c **** return data; + 6456 .loc 1 1142 0 + ARM GAS /tmp/ccwcPdtV.s page 156 + + + 6457 0062 6B46 mov r3, sp + 6458 0064 DC1D adds r4, r3, #7 + 6459 0066 0122 movs r2, #1 + 6460 0068 2100 movs r1, r4 + 6461 006a 0D20 movs r0, #13 + 6462 006c FFF7FEFF bl SX1272ReadBuffer + 6463 .LVL800: +1143:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6464 .loc 1 1143 0 + 6465 0070 2378 ldrb r3, [r4] + 6466 .LVL801: + 6467 .LBE716: + 6468 .LBE715: +1251:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStart( &RxTimeoutSyncWord ); + 6469 .loc 1 1251 0 + 6470 0072 4022 movs r2, #64 + 6471 0074 1343 orrs r3, r2 + 6472 .LVL802: + 6473 0076 6A46 mov r2, sp + 6474 0078 911D adds r1, r2, #6 + 6475 007a 0B70 strb r3, [r1] + 6476 .LVL803: + 6477 .LBB717: + 6478 .LBB718: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6479 .loc 1 1136 0 + 6480 007c 0122 movs r2, #1 + 6481 007e 0D20 movs r0, #13 + 6482 0080 FFF7FEFF bl SX1272WriteBuffer + 6483 .LVL804: + 6484 .LBE718: + 6485 .LBE717: +1252:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6486 .loc 1 1252 0 + 6487 0084 1E48 ldr r0, .L286+8 + 6488 0086 FFF7FEFF bl TimerStart + 6489 .LVL805: + 6490 008a C7E7 b .L281 + 6491 .L282: +1256:./Drivers/BSP/Components/sx1272/sx1272.c **** TimerStop( &RxTimeoutSyncWord ); + 6492 .loc 1 1256 0 + 6493 008c 1A4B ldr r3, .L286 + 6494 008e 0022 movs r2, #0 + 6495 0090 1A71 strb r2, [r3, #4] +1257:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6496 .loc 1 1257 0 + 6497 0092 1B48 ldr r0, .L286+8 + 6498 0094 FFF7FEFF bl TimerStop + 6499 .LVL806: + 6500 0098 C0E7 b .L281 + 6501 .L280: +1275:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6502 .loc 1 1275 0 + 6503 009a FFF7FEFF bl SX1272Reset + 6504 .LVL807: +1278:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6505 .loc 1 1278 0 + ARM GAS /tmp/ccwcPdtV.s page 157 + + + 6506 009e 0020 movs r0, #0 + 6507 00a0 FFF7FEFF bl SX1272SetOpMode + 6508 .LVL808: + 6509 .LBB719: +1280:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6510 .loc 1 1280 0 + 6511 00a4 0024 movs r4, #0 + 6512 00a6 10E0 b .L283 + 6513 .LVL809: + 6514 .L284: +1282:./Drivers/BSP/Components/sx1272/sx1272.c **** SX1272Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); + 6515 .loc 1 1282 0 discriminator 3 + 6516 00a8 164D ldr r5, .L286+12 + 6517 00aa 6600 lsls r6, r4, #1 + 6518 00ac 3619 adds r6, r6, r4 + 6519 00ae 705D ldrb r0, [r6, r5] + 6520 00b0 FFF7FEFF bl SX1272SetModem + 6521 .LVL810: +1283:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6522 .loc 1 1283 0 discriminator 3 + 6523 00b4 AD19 adds r5, r5, r6 + 6524 00b6 6878 ldrb r0, [r5, #1] + 6525 00b8 AB78 ldrb r3, [r5, #2] + 6526 .LVL811: + 6527 00ba 6A46 mov r2, sp + 6528 00bc D11D adds r1, r2, #7 + 6529 00be 0B70 strb r3, [r1] + 6530 .LVL812: + 6531 .LBB720: + 6532 .LBB721: +1136:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6533 .loc 1 1136 0 discriminator 3 + 6534 00c0 0122 movs r2, #1 + 6535 00c2 FFF7FEFF bl SX1272WriteBuffer + 6536 .LVL813: + 6537 .LBE721: + 6538 .LBE720: +1280:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6539 .loc 1 1280 0 discriminator 3 + 6540 00c6 0134 adds r4, r4, #1 + 6541 .LVL814: + 6542 00c8 E4B2 uxtb r4, r4 + 6543 .LVL815: + 6544 .L283: +1280:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6545 .loc 1 1280 0 is_stmt 0 discriminator 1 + 6546 00ca 102C cmp r4, #16 + 6547 00cc ECD9 bls .L284 + 6548 .LBE719: +1285:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6549 .loc 1 1285 0 is_stmt 1 + 6550 00ce 0020 movs r0, #0 + 6551 00d0 FFF7FEFF bl SX1272SetModem + 6552 .LVL816: +1288:./Drivers/BSP/Components/sx1272/sx1272.c **** // END WORKAROUND + 6553 .loc 1 1288 0 + 6554 00d4 084C ldr r4, .L286 + ARM GAS /tmp/ccwcPdtV.s page 158 + + + 6555 .LVL817: + 6556 00d6 5C23 movs r3, #92 + 6557 00d8 E05C ldrb r0, [r4, r3] + 6558 00da FFF7FEFF bl SX1272SetPublicNetwork + 6559 .LVL818: +1291:./Drivers/BSP/Components/sx1272/sx1272.c **** if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 6560 .loc 1 1291 0 + 6561 00de 0023 movs r3, #0 + 6562 00e0 2371 strb r3, [r4, #4] +1292:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6563 .loc 1 1292 0 + 6564 00e2 064B ldr r3, .L286+4 + 6565 00e4 1B68 ldr r3, [r3] + 6566 00e6 002B cmp r3, #0 + 6567 00e8 00D1 bne .LCB6500 + 6568 00ea 91E7 b .L277 @long jump + 6569 .LCB6500: +1292:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6570 .loc 1 1292 0 is_stmt 0 discriminator 1 + 6571 00ec 5B68 ldr r3, [r3, #4] + 6572 00ee 002B cmp r3, #0 + 6573 00f0 00D1 bne .LCB6503 + 6574 00f2 8DE7 b .L277 @long jump + 6575 .LCB6503: +1294:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6576 .loc 1 1294 0 is_stmt 1 + 6577 00f4 9847 blx r3 + 6578 .LVL819: +1300:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6579 .loc 1 1300 0 + 6580 00f6 8BE7 b .L277 + 6581 .L287: + 6582 .align 2 + 6583 .L286: + 6584 00f8 00000000 .word .LANCHOR0 + 6585 00fc 00000000 .word .LANCHOR5 + 6586 0100 00000000 .word .LANCHOR4 + 6587 0104 00000000 .word .LANCHOR7 + 6588 .cfi_endproc + 6589 .LFE126: + 6591 .section .text.SX1272GetRadioWakeUpTime,"ax",%progbits + 6592 .align 1 + 6593 .global SX1272GetRadioWakeUpTime + 6594 .syntax unified + 6595 .code 16 + 6596 .thumb_func + 6597 .fpu softvfp + 6599 SX1272GetRadioWakeUpTime: + 6600 .LFB125: +1226:./Drivers/BSP/Components/sx1272/sx1272.c **** return ( uint32_t )LoRaBoardCallbacks->SX1272BoardGetWakeTime( ) + RADIO_WAKEUP_TIME;// BOARD_W + 6601 .loc 1 1226 0 + 6602 .cfi_startproc + 6603 @ args = 0, pretend = 0, frame = 0 + 6604 @ frame_needed = 0, uses_anonymous_args = 0 + 6605 0000 10B5 push {r4, lr} + 6606 .LCFI57: + 6607 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccwcPdtV.s page 159 + + + 6608 .cfi_offset 4, -8 + 6609 .cfi_offset 14, -4 +1227:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6610 .loc 1 1227 0 + 6611 0002 034B ldr r3, .L289 + 6612 0004 1B68 ldr r3, [r3] + 6613 0006 5B68 ldr r3, [r3, #4] + 6614 0008 9847 blx r3 + 6615 .LVL820: + 6616 000a 0230 adds r0, r0, #2 +1228:./Drivers/BSP/Components/sx1272/sx1272.c **** + 6617 .loc 1 1228 0 + 6618 @ sp needed + 6619 000c 10BD pop {r4, pc} + 6620 .L290: + 6621 000e C046 .align 2 + 6622 .L289: + 6623 0010 00000000 .word .LANCHOR1 + 6624 .cfi_endproc + 6625 .LFE125: + 6627 .section .text.SX1272OnDio5Irq,"ax",%progbits + 6628 .align 1 + 6629 .global SX1272OnDio5Irq + 6630 .syntax unified + 6631 .code 16 + 6632 .thumb_func + 6633 .fpu softvfp + 6635 SX1272OnDio5Irq: + 6636 .LFB132: +1690:./Drivers/BSP/Components/sx1272/sx1272.c **** +1691:./Drivers/BSP/Components/sx1272/sx1272.c **** void SX1272OnDio5Irq( void ) +1692:./Drivers/BSP/Components/sx1272/sx1272.c **** { + 6637 .loc 1 1692 0 + 6638 .cfi_startproc + 6639 @ args = 0, pretend = 0, frame = 0 + 6640 @ frame_needed = 0, uses_anonymous_args = 0 + 6641 @ link register save eliminated. +1693:./Drivers/BSP/Components/sx1272/sx1272.c **** switch( SX1272.Settings.Modem ) +1694:./Drivers/BSP/Components/sx1272/sx1272.c **** { +1695:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_FSK: +1696:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1697:./Drivers/BSP/Components/sx1272/sx1272.c **** case MODEM_LORA: +1698:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1699:./Drivers/BSP/Components/sx1272/sx1272.c **** default: +1700:./Drivers/BSP/Components/sx1272/sx1272.c **** break; +1701:./Drivers/BSP/Components/sx1272/sx1272.c **** } +1702:./Drivers/BSP/Components/sx1272/sx1272.c **** } + 6642 .loc 1 1702 0 + 6643 @ sp needed + 6644 0000 7047 bx lr + 6645 .cfi_endproc + 6646 .LFE132: + 6648 .global RxTimeoutSyncWord + 6649 .global RxTimeoutTimer + 6650 .global TxTimeoutTimer + 6651 .global DioIrq + 6652 .global SX1272 + ARM GAS /tmp/ccwcPdtV.s page 160 + + + 6653 .global FskBandwidths + 6654 .global RadioRegsInit + 6655 .section .bss.LoRaBoardCallbacks,"aw",%nobits + 6656 .align 2 + 6657 .set .LANCHOR1,. + 0 + 6660 LoRaBoardCallbacks: + 6661 0000 00000000 .space 4 + 6662 .section .bss.RadioEvents,"aw",%nobits + 6663 .align 2 + 6664 .set .LANCHOR5,. + 0 + 6667 RadioEvents: + 6668 0000 00000000 .space 4 + 6669 .section .bss.RxTimeoutSyncWord,"aw",%nobits + 6670 .align 2 + 6671 .set .LANCHOR4,. + 0 + 6674 RxTimeoutSyncWord: + 6675 0000 00000000 .space 20 + 6675 00000000 + 6675 00000000 + 6675 00000000 + 6675 00000000 + 6676 .section .bss.RxTimeoutTimer,"aw",%nobits + 6677 .align 2 + 6678 .set .LANCHOR2,. + 0 + 6681 RxTimeoutTimer: + 6682 0000 00000000 .space 20 + 6682 00000000 + 6682 00000000 + 6682 00000000 + 6682 00000000 + 6683 .section .bss.RxTxBuffer,"aw",%nobits + 6684 .align 2 + 6687 RxTxBuffer: + 6688 0000 00000000 .space 256 + 6688 00000000 + 6688 00000000 + 6688 00000000 + 6688 00000000 + 6689 .section .bss.SX1272,"aw",%nobits + 6690 .align 2 + 6691 .set .LANCHOR0,. + 0 + 6694 SX1272: + 6695 0000 00000000 .space 104 + 6695 00000000 + 6695 00000000 + 6695 00000000 + 6695 00000000 + 6696 .section .bss.TxTimeoutTimer,"aw",%nobits + 6697 .align 2 + 6698 .set .LANCHOR3,. + 0 + 6701 TxTimeoutTimer: + 6702 0000 00000000 .space 20 + 6702 00000000 + 6702 00000000 + 6702 00000000 + 6702 00000000 + 6703 .section .data.DioIrq,"aw",%progbits + ARM GAS /tmp/ccwcPdtV.s page 161 + + + 6704 .align 2 + 6705 .set .LANCHOR6,. + 0 + 6708 DioIrq: + 6709 0000 00000000 .word SX1272OnDio0Irq + 6710 0004 00000000 .word SX1272OnDio1Irq + 6711 0008 00000000 .word SX1272OnDio2Irq + 6712 000c 00000000 .word SX1272OnDio3Irq + 6713 0010 00000000 .word SX1272OnDio4Irq + 6714 0014 00000000 .word 0 + 6715 .section .rodata.FskBandwidths,"a",%progbits + 6716 .align 2 + 6719 FskBandwidths: + 6720 0000 280A0000 .word 2600 + 6721 0004 17 .byte 23 + 6722 0005 000000 .space 3 + 6723 0008 1C0C0000 .word 3100 + 6724 000c 0F .byte 15 + 6725 000d 000000 .space 3 + 6726 0010 3C0F0000 .word 3900 + 6727 0014 07 .byte 7 + 6728 0015 000000 .space 3 + 6729 0018 50140000 .word 5200 + 6730 001c 16 .byte 22 + 6731 001d 000000 .space 3 + 6732 0020 9C180000 .word 6300 + 6733 0024 0E .byte 14 + 6734 0025 000000 .space 3 + 6735 0028 781E0000 .word 7800 + 6736 002c 06 .byte 6 + 6737 002d 000000 .space 3 + 6738 0030 A0280000 .word 10400 + 6739 0034 15 .byte 21 + 6740 0035 000000 .space 3 + 6741 0038 D4300000 .word 12500 + 6742 003c 0D .byte 13 + 6743 003d 000000 .space 3 + 6744 0040 F03C0000 .word 15600 + 6745 0044 05 .byte 5 + 6746 0045 000000 .space 3 + 6747 0048 40510000 .word 20800 + 6748 004c 14 .byte 20 + 6749 004d 000000 .space 3 + 6750 0050 A8610000 .word 25000 + 6751 0054 0C .byte 12 + 6752 0055 000000 .space 3 + 6753 0058 447A0000 .word 31300 + 6754 005c 04 .byte 4 + 6755 005d 000000 .space 3 + 6756 0060 E4A20000 .word 41700 + 6757 0064 13 .byte 19 + 6758 0065 000000 .space 3 + 6759 0068 50C30000 .word 50000 + 6760 006c 0B .byte 11 + 6761 006d 000000 .space 3 + 6762 0070 24F40000 .word 62500 + 6763 0074 03 .byte 3 + 6764 0075 000000 .space 3 + ARM GAS /tmp/ccwcPdtV.s page 162 + + + 6765 0078 85450100 .word 83333 + 6766 007c 12 .byte 18 + 6767 007d 000000 .space 3 + 6768 0080 A0860100 .word 100000 + 6769 0084 0A .byte 10 + 6770 0085 000000 .space 3 + 6771 0088 48E80100 .word 125000 + 6772 008c 02 .byte 2 + 6773 008d 000000 .space 3 + 6774 0090 2C8B0200 .word 166700 + 6775 0094 11 .byte 17 + 6776 0095 000000 .space 3 + 6777 0098 400D0300 .word 200000 + 6778 009c 09 .byte 9 + 6779 009d 000000 .space 3 + 6780 00a0 90D00300 .word 250000 + 6781 00a4 01 .byte 1 + 6782 00a5 000000 .space 3 + 6783 00a8 E0930400 .word 300000 + 6784 00ac 00 .byte 0 + 6785 00ad 000000 .space 3 + 6786 .section .rodata.RadioRegsInit,"a",%progbits + 6787 .align 2 + 6788 .set .LANCHOR7,. + 0 + 6791 RadioRegsInit: + 6792 0000 00 .byte 0 + 6793 0001 0C .byte 12 + 6794 0002 23 .byte 35 + 6795 0003 00 .byte 0 + 6796 0004 0D .byte 13 + 6797 0005 1E .byte 30 + 6798 0006 00 .byte 0 + 6799 0007 0E .byte 14 + 6800 0008 D2 .byte -46 + 6801 0009 00 .byte 0 + 6802 000a 1A .byte 26 + 6803 000b 01 .byte 1 + 6804 000c 00 .byte 0 + 6805 000d 1F .byte 31 + 6806 000e AA .byte -86 + 6807 000f 00 .byte 0 + 6808 0010 24 .byte 36 + 6809 0011 07 .byte 7 + 6810 0012 00 .byte 0 + 6811 0013 27 .byte 39 + 6812 0014 12 .byte 18 + 6813 0015 00 .byte 0 + 6814 0016 28 .byte 40 + 6815 0017 C1 .byte -63 + 6816 0018 00 .byte 0 + 6817 0019 29 .byte 41 + 6818 001a 94 .byte -108 + 6819 001b 00 .byte 0 + 6820 001c 2A .byte 42 + 6821 001d C1 .byte -63 + 6822 001e 00 .byte 0 + 6823 001f 30 .byte 48 + ARM GAS /tmp/ccwcPdtV.s page 163 + + + 6824 0020 D8 .byte -40 + 6825 0021 00 .byte 0 + 6826 0022 35 .byte 53 + 6827 0023 8F .byte -113 + 6828 0024 00 .byte 0 + 6829 0025 3B .byte 59 + 6830 0026 02 .byte 2 + 6831 0027 00 .byte 0 + 6832 0028 40 .byte 64 + 6833 0029 00 .byte 0 + 6834 002a 00 .byte 0 + 6835 002b 41 .byte 65 + 6836 002c 30 .byte 48 + 6837 002d 01 .byte 1 + 6838 002e 31 .byte 49 + 6839 002f 43 .byte 67 + 6840 0030 01 .byte 1 + 6841 0031 23 .byte 35 + 6842 0032 40 .byte 64 + 6843 .section .rodata.SX1272OnDio0Irq.str1.4,"aMS",%progbits,1 + 6844 .align 2 + 6845 .LC47: + 6846 0000 7278446F .ascii "rxDone\012\015\000" + 6846 6E650A0D + 6846 00 + 6847 0009 000000 .space 3 + 6848 .LC50: + 6849 000c 7478446F .ascii "txDone\012\015\000" + 6849 6E650A0D + 6849 00 + 6850 .section .rodata.SX1272OnDio1Irq.str1.4,"aMS",%progbits,1 + 6851 .align 2 + 6852 .LC56: + 6853 0000 72785469 .ascii "rxTimeOut\012\015\000" + 6853 6D654F75 + 6853 740A0D00 + 6854 .text + 6855 .Letext0: + 6856 .file 2 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 6857 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 6858 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 6859 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 6860 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 6861 .file 7 "/usr/arm-none-eabi/include/math.h" + 6862 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 6863 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 6864 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 6865 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 6866 .file 12 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" + 6867 .file 13 "Middlewares/Third_Party/Lora/Phy/radio.h" + 6868 .file 14 "./Drivers/BSP/Components/sx1272/sx1272.h" + 6869 .file 15 "Middlewares/Third_Party/Lora/Utilities/timeServer.h" + 6870 .file 16 "Inc/vcom.h" + 6871 .file 17 "Inc/hw_gpio.h" + 6872 .file 18 "Inc/hw_spi.h" + 6873 .file 19 "Middlewares/Third_Party/Lora/Utilities/delay.h" + 6874 .file 20 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + ARM GAS /tmp/ccwcPdtV.s page 164 + + + 6875 .file 21 "" + ARM GAS /tmp/ccwcPdtV.s page 165 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 sx1272.c + /tmp/ccwcPdtV.s:16 .text.SX1272OnDio4Irq:0000000000000000 $t + /tmp/ccwcPdtV.s:23 .text.SX1272OnDio4Irq:0000000000000000 SX1272OnDio4Irq + /tmp/ccwcPdtV.s:53 .text.SX1272OnDio4Irq:000000000000001c $d + /tmp/ccwcPdtV.s:58 .text.SX1272BoardInit:0000000000000000 $t + /tmp/ccwcPdtV.s:65 .text.SX1272BoardInit:0000000000000000 SX1272BoardInit + /tmp/ccwcPdtV.s:82 .text.SX1272BoardInit:0000000000000008 $d + /tmp/ccwcPdtV.s:87 .text.SX1272GetStatus:0000000000000000 $t + /tmp/ccwcPdtV.s:94 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.bss.TxTimeoutTimer:0000000000000000 TxTimeoutTimer + /tmp/ccwcPdtV.s:6708 .data.DioIrq:0000000000000000 DioIrq + /tmp/ccwcPdtV.s:6694 .bss.SX1272:0000000000000000 SX1272 + /tmp/ccwcPdtV.s:6791 .rodata.RadioRegsInit:0000000000000000 RadioRegsInit + /tmp/ccwcPdtV.s:6656 .bss.LoRaBoardCallbacks:0000000000000000 $d + /tmp/ccwcPdtV.s:6660 .bss.LoRaBoardCallbacks:0000000000000000 LoRaBoardCallbacks + /tmp/ccwcPdtV.s:6663 .bss.RadioEvents:0000000000000000 $d + /tmp/ccwcPdtV.s:6667 .bss.RadioEvents:0000000000000000 RadioEvents + ARM GAS /tmp/ccwcPdtV.s page 167 + + + /tmp/ccwcPdtV.s:6670 .bss.RxTimeoutSyncWord:0000000000000000 $d + /tmp/ccwcPdtV.s:6677 .bss.RxTimeoutTimer:0000000000000000 $d + /tmp/ccwcPdtV.s:6684 .bss.RxTxBuffer:0000000000000000 $d + /tmp/ccwcPdtV.s:6690 .bss.SX1272:0000000000000000 $d + /tmp/ccwcPdtV.s:6697 .bss.TxTimeoutTimer:0000000000000000 $d + /tmp/ccwcPdtV.s:6704 .data.DioIrq:0000000000000000 $d + /tmp/ccwcPdtV.s:6716 .rodata.FskBandwidths:0000000000000000 $d + /tmp/ccwcPdtV.s:6787 .rodata.RadioRegsInit:0000000000000000 $d + /tmp/ccwcPdtV.s:6844 .rodata.SX1272OnDio0Irq.str1.4:0000000000000000 $d + /tmp/ccwcPdtV.s:6851 .rodata.SX1272OnDio1Irq.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +memset +HW_GPIO_Init +HW_GPIO_Write +DelayMs +HW_SPI_InOut +__aeabi_uidiv +__aeabi_uidivmod +__aeabi_i2d +__aeabi_dadd +__aeabi_dmul +__aeabi_ui2d +__aeabi_ddiv +__aeabi_d2uiz +__aeabi_dcmpgt +round +ceil +floor +TimerStop +TimerSetValue +TimerStart +TimerInit +TimerGetCurrentTime +TimerGetElapsedTime +memcpy1 +vcom_Send diff --git a/build/sx1272mb2das.d b/build/sx1272mb2das.d new file mode 100644 index 0000000..210dd5f --- /dev/null +++ b/build/sx1272mb2das.d @@ -0,0 +1,150 @@ +build/sx1272mb2das.d: Drivers/BSP/sx1272mb2das/sx1272mb2das.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Drivers/BSP/Components/sx1272/sx1272.h \ + Middlewares/Third_Party/Lora/Phy/radio.h \ + Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h \ + Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h \ + Drivers/BSP/sx1272mb2das/sx1272mb2das.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Drivers/BSP/Components/sx1272/sx1272.h: + +Middlewares/Third_Party/Lora/Phy/radio.h: + +Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h: + +Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h: + +Drivers/BSP/sx1272mb2das/sx1272mb2das.h: diff --git a/build/sx1272mb2das.lst b/build/sx1272mb2das.lst new file mode 100644 index 0000000..4a0f501 --- /dev/null +++ b/build/sx1272mb2das.lst @@ -0,0 +1,925 @@ +ARM GAS /tmp/ccy8fBTW.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "sx1272mb2das.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SX1272GetWakeTime,"ax",%progbits + 16 .align 1 + 17 .global SX1272GetWakeTime + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 SX1272GetWakeTime: + 24 .LFB96: + 25 .file 1 "./Drivers/BSP/sx1272mb2das/sx1272mb2das.c" + 1:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /* + 2:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** / _____) _ | | + 3:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** (C)2013 Semtech + 8:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 9:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** Description: SX1272 driver specific target board functions implementation + 10:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 11:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 13:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** */ + 15:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /******************************************************************************* + 16:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @file sx1272mb2das.c + 17:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @author MCD Application Team + 18:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @version V1.0.4 + 19:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @date 08-September-2017 + 20:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @brief driver sx1272mb2das board + 21:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** ****************************************************************************** + 22:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * @attention + 23:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 24:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics

+ 25:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 26:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * Redistribution and use in source and binary forms, with or without modification, + 27:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * are permitted provided that the following conditions are met: + 28:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * 1. Redistributions of source code must retain the above copyright notice, + 29:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * this list of conditions and the following disclaimer. + 30:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 31:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * this list of conditions and the following disclaimer in the documentation + 32:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * and/or other materials provided with the distribution. + 33:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + ARM GAS /tmp/ccy8fBTW.s page 2 + + + 34:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * may be used to endorse or promote products derived from this software + 35:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * without specific prior written permission. + 36:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 37:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 38:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 39:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 40:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 41:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 42:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 43:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 44:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 45:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 46:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 47:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 48:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** ****************************************************************************** + 49:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** */ + 50:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 51:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /* Includes ------------------------------------------------------------------*/ + 52:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** #include "hw.h" + 53:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** #include "sx1272.h" + 54:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** #include "radio.h" + 55:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** #include "sx1272mb2das.h" + 56:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 57:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 58:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** #define IRQ_HIGH_PRIORITY 0 + 59:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 60:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /*! + 61:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * Flag used to set the RF switch control pins in low power mode when the radio is not active. + 62:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** */ + 63:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 64:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 65:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetXO( uint8_t state ); + 66:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 67:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint32_t SX1272GetWakeTime( void ); + 68:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 69:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272IoIrqInit( DioIrqHandler **irqHandlers ); + 70:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 71:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint8_t SX1272GetPaSelect( uint32_t channel ); + 72:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 73:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetAntSwLowPower( bool status ); + 74:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 75:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetRfTxPower( int8_t power ); + 76:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 77:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetAntSw( uint8_t opMode ); + 78:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /*! + 79:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * \brief Controls the antena switch if necessary. + 80:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 81:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * \remark see errata note + 82:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * + 83:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * \param [IN] opMode Current radio operating mode + 84:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** */ + 85:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** static LoRaBoardCallback_t BoardCallbacks = { SX1272SetXO, + 86:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272GetWakeTime, + 87:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272IoIrqInit, + 88:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetRfTxPower, + 89:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetAntSwLowPower, + 90:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetAntSw}; + ARM GAS /tmp/ccy8fBTW.s page 3 + + + 91:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 92:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** /*! + 93:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** * Radio driver structure initialization + 94:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** */ + 95:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** const struct Radio_s Radio = + 96:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 97:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272IoInit, + 98:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272IoDeInit, + 99:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Init, + 100:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272GetStatus, + 101:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetModem, + 102:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetChannel, + 103:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272IsChannelFree, + 104:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Random, + 105:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetRxConfig, + 106:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetTxConfig, + 107:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272CheckRfFrequency, + 108:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272GetTimeOnAir, + 109:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Send, + 110:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetSleep, + 111:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetStby, + 112:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetRx, + 113:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272StartCad, + 114:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetTxContinuousWave, + 115:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272ReadRssi, + 116:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Write, + 117:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Read, + 118:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272WriteBuffer, + 119:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272ReadBuffer, + 120:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetMaxPayloadLength, + 121:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272SetPublicNetwork, + 122:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272GetRadioWakeUpTime + 123:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** }; + 124:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 125:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint32_t SX1272GetWakeTime( void ) + 126:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 26 .loc 1 126 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 127:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** return BOARD_WAKEUP_TIME; + 128:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 31 .loc 1 128 0 + 32 0000 0020 movs r0, #0 + 33 @ sp needed + 34 0002 7047 bx lr + 35 .cfi_endproc + 36 .LFE96: + 38 .section .text.SX1272SetXO,"ax",%progbits + 39 .align 1 + 40 .global SX1272SetXO + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 SX1272SetXO: + ARM GAS /tmp/ccy8fBTW.s page 4 + + + 47 .LFB97: + 129:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 130:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetXO( uint8_t state ) + 131:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 48 .loc 1 131 0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 53 .LVL0: + 132:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 54 .loc 1 132 0 + 55 @ sp needed + 56 0000 7047 bx lr + 57 .cfi_endproc + 58 .LFE97: + 60 .section .text.SX1272SetAntSwLowPower,"ax",%progbits + 61 .align 1 + 62 .global SX1272SetAntSwLowPower + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 SX1272SetAntSwLowPower: + 69 .LFB103: + 133:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272IoInit( void ) + 134:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 135:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** GPIO_InitTypeDef initStruct={0}; + 136:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 137:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272BoardInit( &BoardCallbacks ); + 138:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 139:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Mode = GPIO_MODE_IT_RISING; + 140:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Pull = GPIO_PULLDOWN; + 141:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Speed = GPIO_SPEED_HIGH; + 142:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 143:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_0_PORT, RADIO_DIO_0_PIN, &initStruct ); + 144:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, &initStruct ); + 145:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, &initStruct ); + 146:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, &initStruct ); + 147:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 148:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 149:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272IoIrqInit( DioIrqHandler **irqHandlers ) + 150:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 151:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_0_PORT, RADIO_DIO_0_PIN, IRQ_HIGH_PRIORITY, irqHandlers[0] ); + 152:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, IRQ_HIGH_PRIORITY, irqHandlers[1] ); + 153:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, IRQ_HIGH_PRIORITY, irqHandlers[2] ); + 154:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, IRQ_HIGH_PRIORITY, irqHandlers[3] ); + 155:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 156:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 157:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272IoDeInit( void ) + 158:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 159:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** GPIO_InitTypeDef initStruct={0}; + 160:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 161:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Mode = GPIO_MODE_IT_RISING ;//GPIO_MODE_ANALOG; + 162:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Pull = GPIO_PULLDOWN; + 163:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 164:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_0_PORT, RADIO_DIO_0_PIN, &initStruct ); + ARM GAS /tmp/ccy8fBTW.s page 5 + + + 165:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, &initStruct ); + 166:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, &initStruct ); + 167:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, &initStruct ); + 168:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 169:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 170:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetRfTxPower( int8_t power ) + 171:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 172:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint8_t paConfig = 0; + 173:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint8_t paDac = 0; + 174:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 175:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paConfig = SX1272Read( REG_PACONFIG ); + 176:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paDac = SX1272Read( REG_PADAC ); + 177:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 178:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | SX1272GetPaSelect( SX1272.Settings.Channe + 179:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 180:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) + 181:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 182:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power > 17 ) + 183:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 184:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON; + 185:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 186:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** else + 187:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 188:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF; + 189:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 190:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON ) + 191:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 192:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power < 5 ) + 193:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 194:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = 5; + 195:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 196:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power > 20 ) + 197:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 198:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = 20; + 199:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 200:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( p + 201:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 202:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** else + 203:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 204:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power < 2 ) + 205:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 206:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = 2; + 207:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 208:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power > 17 ) + 209:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 210:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = 17; + 211:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 212:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( p + 213:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 214:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 215:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** else + 216:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 217:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power < -1 ) + 218:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 219:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = -1; + 220:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 221:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** if( power > 14 ) + ARM GAS /tmp/ccy8fBTW.s page 6 + + + 222:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 223:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** power = 14; + 224:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 225:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 226:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 227:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Write( REG_PACONFIG, paConfig ); + 228:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Write( REG_PADAC, paDac ); + 229:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 230:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 231:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint8_t SX1272GetPaSelect( uint32_t channel ) + 232:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 233:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** return RF_PACONFIG_PASELECT_RFO; + 234:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 235:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 236:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetAntSwLowPower( bool status ) + 237:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 70 .loc 1 237 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 @ link register save eliminated. + 75 .LVL1: + 238:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** //Ant Switch Controlled by SX1272 IC + 239:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 76 .loc 1 239 0 + 77 @ sp needed + 78 0000 7047 bx lr + 79 .cfi_endproc + 80 .LFE103: + 82 .section .text.SX1272SetAntSw,"ax",%progbits + 83 .align 1 + 84 .global SX1272SetAntSw + 85 .syntax unified + 86 .code 16 + 87 .thumb_func + 88 .fpu softvfp + 90 SX1272SetAntSw: + 91 .LFB104: + 240:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 241:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** void SX1272SetAntSw( uint8_t opMode ) + 242:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 92 .loc 1 242 0 + 93 .cfi_startproc + 94 @ args = 0, pretend = 0, frame = 0 + 95 @ frame_needed = 0, uses_anonymous_args = 0 + 96 @ link register save eliminated. + 97 .LVL2: + 243:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** switch( opMode ) + 98 .loc 1 243 0 + 99 0000 0328 cmp r0, #3 + 100 0002 03D0 beq .L9 + 244:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 245:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** case RFLR_OPMODE_TRANSMITTER: + 246:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272.RxTx = 1; + 247:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** break; + 248:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** case RFLR_OPMODE_RECEIVER: + 249:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** case RFLR_OPMODE_RECEIVER_SINGLE: + ARM GAS /tmp/ccy8fBTW.s page 7 + + + 250:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** case RFLR_OPMODE_CAD: + 251:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** default: + 252:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272.RxTx = 0; + 101 .loc 1 252 0 + 102 0004 034B ldr r3, .L10 + 103 0006 0022 movs r2, #0 + 104 0008 1A70 strb r2, [r3] + 105 .L4: + 253:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** break; + 254:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 255:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 106 .loc 1 255 0 + 107 @ sp needed + 108 000a 7047 bx lr + 109 .L9: + 246:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** break; + 110 .loc 1 246 0 + 111 000c 014B ldr r3, .L10 + 112 000e 0122 movs r2, #1 + 113 0010 1A70 strb r2, [r3] + 247:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** case RFLR_OPMODE_RECEIVER: + 114 .loc 1 247 0 + 115 0012 FAE7 b .L4 + 116 .L11: + 117 .align 2 + 118 .L10: + 119 0014 00000000 .word SX1272 + 120 .cfi_endproc + 121 .LFE104: + 123 .section .text.SX1272CheckRfFrequency,"ax",%progbits + 124 .align 1 + 125 .global SX1272CheckRfFrequency + 126 .syntax unified + 127 .code 16 + 128 .thumb_func + 129 .fpu softvfp + 131 SX1272CheckRfFrequency: + 132 .LFB105: + 256:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 257:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** bool SX1272CheckRfFrequency( uint32_t frequency ) + 258:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 133 .loc 1 258 0 + 134 .cfi_startproc + 135 @ args = 0, pretend = 0, frame = 0 + 136 @ frame_needed = 0, uses_anonymous_args = 0 + 137 @ link register save eliminated. + 138 .LVL3: + 259:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** // Implement check. Currently all frequencies are supported + 260:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** return true; + 261:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 139 .loc 1 261 0 + 140 0000 0120 movs r0, #1 + 141 .LVL4: + 142 @ sp needed + 143 0002 7047 bx lr + 144 .cfi_endproc + 145 .LFE105: + ARM GAS /tmp/ccy8fBTW.s page 8 + + + 147 .section .text.SX1272SetRfTxPower,"ax",%progbits + 148 .align 1 + 149 .global SX1272SetRfTxPower + 150 .syntax unified + 151 .code 16 + 152 .thumb_func + 153 .fpu softvfp + 155 SX1272SetRfTxPower: + 156 .LFB101: + 171:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** uint8_t paConfig = 0; + 157 .loc 1 171 0 + 158 .cfi_startproc + 159 @ args = 0, pretend = 0, frame = 0 + 160 @ frame_needed = 0, uses_anonymous_args = 0 + 161 .LVL5: + 162 0000 70B5 push {r4, r5, r6, lr} + 163 .LCFI0: + 164 .cfi_def_cfa_offset 16 + 165 .cfi_offset 4, -16 + 166 .cfi_offset 5, -12 + 167 .cfi_offset 6, -8 + 168 .cfi_offset 14, -4 + 169 0002 0400 movs r4, r0 + 170 .LVL6: + 175:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** paDac = SX1272Read( REG_PADAC ); + 171 .loc 1 175 0 + 172 0004 0920 movs r0, #9 + 173 .LVL7: + 174 0006 FFF7FEFF bl SX1272Read + 175 .LVL8: + 176 000a 0600 movs r6, r0 + 177 .LVL9: + 176:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 178 .loc 1 176 0 + 179 000c 5A20 movs r0, #90 + 180 000e FFF7FEFF bl SX1272Read + 181 .LVL10: + 182 0012 0500 movs r5, r0 + 183 .LVL11: + 178:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 184 .loc 1 178 0 + 185 0014 76B2 sxtb r6, r6 + 186 .LVL12: + 217:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 187 .loc 1 217 0 + 188 0016 631C adds r3, r4, #1 + 189 0018 11DB blt .L15 + 190 .LVL13: + 221:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** { + 191 .loc 1 221 0 + 192 001a 0E2C cmp r4, #14 + 193 001c 00DD ble .L14 + 223:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 194 .loc 1 223 0 + 195 001e 0E24 movs r4, #14 + 196 .LVL14: + 197 .L14: + ARM GAS /tmp/ccy8fBTW.s page 9 + + + 225:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 198 .loc 1 225 0 + 199 0020 7021 movs r1, #112 + 200 0022 3140 ands r1, r6 + 201 0024 0134 adds r4, r4, #1 + 202 .LVL15: + 203 0026 64B2 sxtb r4, r4 + 204 0028 0F23 movs r3, #15 + 205 002a 1C40 ands r4, r3 + 206 002c 2143 orrs r1, r4 + 207 .LVL16: + 227:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** SX1272Write( REG_PADAC, paDac ); + 208 .loc 1 227 0 + 209 002e 0920 movs r0, #9 + 210 0030 FFF7FEFF bl SX1272Write + 211 .LVL17: + 228:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 212 .loc 1 228 0 + 213 0034 2900 movs r1, r5 + 214 0036 5A20 movs r0, #90 + 215 0038 FFF7FEFF bl SX1272Write + 216 .LVL18: + 229:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 217 .loc 1 229 0 + 218 @ sp needed + 219 .LVL19: + 220 .LVL20: + 221 003c 70BD pop {r4, r5, r6, pc} + 222 .LVL21: + 223 .L15: + 219:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 224 .loc 1 219 0 + 225 003e 0124 movs r4, #1 + 226 0040 6442 rsbs r4, r4, #0 + 227 0042 EDE7 b .L14 + 228 .cfi_endproc + 229 .LFE101: + 231 .section .text.SX1272IoInit,"ax",%progbits + 232 .align 1 + 233 .global SX1272IoInit + 234 .syntax unified + 235 .code 16 + 236 .thumb_func + 237 .fpu softvfp + 239 SX1272IoInit: + 240 .LFB98: + 134:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** GPIO_InitTypeDef initStruct={0}; + 241 .loc 1 134 0 + 242 .cfi_startproc + 243 @ args = 0, pretend = 0, frame = 24 + 244 @ frame_needed = 0, uses_anonymous_args = 0 + 245 0000 10B5 push {r4, lr} + 246 .LCFI1: + 247 .cfi_def_cfa_offset 8 + 248 .cfi_offset 4, -8 + 249 .cfi_offset 14, -4 + 250 0002 86B0 sub sp, sp, #24 + ARM GAS /tmp/ccy8fBTW.s page 10 + + + 251 .LCFI2: + 252 .cfi_def_cfa_offset 32 + 135:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 253 .loc 1 135 0 + 254 0004 1422 movs r2, #20 + 255 0006 0021 movs r1, #0 + 256 0008 01A8 add r0, sp, #4 + 257 000a FFF7FEFF bl memset + 258 .LVL22: + 137:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 259 .loc 1 137 0 + 260 000e 1148 ldr r0, .L18 + 261 0010 FFF7FEFF bl SX1272BoardInit + 262 .LVL23: + 139:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Pull = GPIO_PULLDOWN; + 263 .loc 1 139 0 + 264 0014 104B ldr r3, .L18+4 + 265 0016 0293 str r3, [sp, #8] + 140:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Speed = GPIO_SPEED_HIGH; + 266 .loc 1 140 0 + 267 0018 0223 movs r3, #2 + 268 001a 0393 str r3, [sp, #12] + 141:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 269 .loc 1 141 0 + 270 001c 0133 adds r3, r3, #1 + 271 001e 0493 str r3, [sp, #16] + 143:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, &initStruct ); + 272 .loc 1 143 0 + 273 0020 8021 movs r1, #128 + 274 0022 A020 movs r0, #160 + 275 0024 01AA add r2, sp, #4 + 276 0026 C900 lsls r1, r1, #3 + 277 0028 C005 lsls r0, r0, #23 + 278 002a FFF7FEFF bl HW_GPIO_Init + 279 .LVL24: + 144:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, &initStruct ); + 280 .loc 1 144 0 + 281 002e 0B4C ldr r4, .L18+8 + 282 0030 01AA add r2, sp, #4 + 283 0032 0821 movs r1, #8 + 284 0034 2000 movs r0, r4 + 285 0036 FFF7FEFF bl HW_GPIO_Init + 286 .LVL25: + 145:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, &initStruct ); + 287 .loc 1 145 0 + 288 003a 01AA add r2, sp, #4 + 289 003c 2021 movs r1, #32 + 290 003e 2000 movs r0, r4 + 291 0040 FFF7FEFF bl HW_GPIO_Init + 292 .LVL26: + 146:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 293 .loc 1 146 0 + 294 0044 01AA add r2, sp, #4 + 295 0046 1021 movs r1, #16 + 296 0048 2000 movs r0, r4 + 297 004a FFF7FEFF bl HW_GPIO_Init + 298 .LVL27: + ARM GAS /tmp/ccy8fBTW.s page 11 + + + 147:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 299 .loc 1 147 0 + 300 004e 06B0 add sp, sp, #24 + 301 @ sp needed + 302 0050 10BD pop {r4, pc} + 303 .L19: + 304 0052 C046 .align 2 + 305 .L18: + 306 0054 00000000 .word .LANCHOR0 + 307 0058 00001110 .word 269549568 + 308 005c 00040050 .word 1342178304 + 309 .cfi_endproc + 310 .LFE98: + 312 .section .text.SX1272IoDeInit,"ax",%progbits + 313 .align 1 + 314 .global SX1272IoDeInit + 315 .syntax unified + 316 .code 16 + 317 .thumb_func + 318 .fpu softvfp + 320 SX1272IoDeInit: + 321 .LFB100: + 158:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** GPIO_InitTypeDef initStruct={0}; + 322 .loc 1 158 0 + 323 .cfi_startproc + 324 @ args = 0, pretend = 0, frame = 24 + 325 @ frame_needed = 0, uses_anonymous_args = 0 + 326 0000 10B5 push {r4, lr} + 327 .LCFI3: + 328 .cfi_def_cfa_offset 8 + 329 .cfi_offset 4, -8 + 330 .cfi_offset 14, -4 + 331 0002 86B0 sub sp, sp, #24 + 332 .LCFI4: + 333 .cfi_def_cfa_offset 32 + 159:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 334 .loc 1 159 0 + 335 0004 1422 movs r2, #20 + 336 0006 0021 movs r1, #0 + 337 0008 01A8 add r0, sp, #4 + 338 000a FFF7FEFF bl memset + 339 .LVL28: + 161:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** initStruct.Pull = GPIO_PULLDOWN; + 340 .loc 1 161 0 + 341 000e 0E4B ldr r3, .L21 + 342 0010 0293 str r3, [sp, #8] + 162:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 343 .loc 1 162 0 + 344 0012 0223 movs r3, #2 + 345 0014 0393 str r3, [sp, #12] + 164:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, &initStruct ); + 346 .loc 1 164 0 + 347 0016 8021 movs r1, #128 + 348 0018 A020 movs r0, #160 + 349 001a 01AA add r2, sp, #4 + 350 001c C900 lsls r1, r1, #3 + 351 001e C005 lsls r0, r0, #23 + ARM GAS /tmp/ccy8fBTW.s page 12 + + + 352 0020 FFF7FEFF bl HW_GPIO_Init + 353 .LVL29: + 165:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, &initStruct ); + 354 .loc 1 165 0 + 355 0024 094C ldr r4, .L21+4 + 356 0026 01AA add r2, sp, #4 + 357 0028 0821 movs r1, #8 + 358 002a 2000 movs r0, r4 + 359 002c FFF7FEFF bl HW_GPIO_Init + 360 .LVL30: + 166:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_Init( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, &initStruct ); + 361 .loc 1 166 0 + 362 0030 01AA add r2, sp, #4 + 363 0032 2021 movs r1, #32 + 364 0034 2000 movs r0, r4 + 365 0036 FFF7FEFF bl HW_GPIO_Init + 366 .LVL31: + 167:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 367 .loc 1 167 0 + 368 003a 01AA add r2, sp, #4 + 369 003c 1021 movs r1, #16 + 370 003e 2000 movs r0, r4 + 371 0040 FFF7FEFF bl HW_GPIO_Init + 372 .LVL32: + 168:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 373 .loc 1 168 0 + 374 0044 06B0 add sp, sp, #24 + 375 @ sp needed + 376 0046 10BD pop {r4, pc} + 377 .L22: + 378 .align 2 + 379 .L21: + 380 0048 00001110 .word 269549568 + 381 004c 00040050 .word 1342178304 + 382 .cfi_endproc + 383 .LFE100: + 385 .section .text.SX1272IoIrqInit,"ax",%progbits + 386 .align 1 + 387 .global SX1272IoIrqInit + 388 .syntax unified + 389 .code 16 + 390 .thumb_func + 391 .fpu softvfp + 393 SX1272IoIrqInit: + 394 .LFB99: + 150:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_0_PORT, RADIO_DIO_0_PIN, IRQ_HIGH_PRIORITY, irqHandlers[0] ); + 395 .loc 1 150 0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 399 .LVL33: + 400 0000 70B5 push {r4, r5, r6, lr} + 401 .LCFI5: + 402 .cfi_def_cfa_offset 16 + 403 .cfi_offset 4, -16 + 404 .cfi_offset 5, -12 + 405 .cfi_offset 6, -8 + ARM GAS /tmp/ccy8fBTW.s page 13 + + + 406 .cfi_offset 14, -4 + 407 0002 0400 movs r4, r0 + 151:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_1_PORT, RADIO_DIO_1_PIN, IRQ_HIGH_PRIORITY, irqHandlers[1] ); + 408 .loc 1 151 0 + 409 0004 8021 movs r1, #128 + 410 0006 A020 movs r0, #160 + 411 .LVL34: + 412 0008 2368 ldr r3, [r4] + 413 000a 0022 movs r2, #0 + 414 000c C900 lsls r1, r1, #3 + 415 000e C005 lsls r0, r0, #23 + 416 0010 FFF7FEFF bl HW_GPIO_SetIrq + 417 .LVL35: + 152:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_2_PORT, RADIO_DIO_2_PIN, IRQ_HIGH_PRIORITY, irqHandlers[2] ); + 418 .loc 1 152 0 + 419 0014 094D ldr r5, .L24 + 420 0016 6368 ldr r3, [r4, #4] + 421 0018 0022 movs r2, #0 + 422 001a 0821 movs r1, #8 + 423 001c 2800 movs r0, r5 + 424 001e FFF7FEFF bl HW_GPIO_SetIrq + 425 .LVL36: + 153:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** HW_GPIO_SetIrq( RADIO_DIO_3_PORT, RADIO_DIO_3_PIN, IRQ_HIGH_PRIORITY, irqHandlers[3] ); + 426 .loc 1 153 0 + 427 0022 A368 ldr r3, [r4, #8] + 428 0024 0022 movs r2, #0 + 429 0026 2021 movs r1, #32 + 430 0028 2800 movs r0, r5 + 431 002a FFF7FEFF bl HW_GPIO_SetIrq + 432 .LVL37: + 154:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** } + 433 .loc 1 154 0 + 434 002e E368 ldr r3, [r4, #12] + 435 0030 0022 movs r2, #0 + 436 0032 1021 movs r1, #16 + 437 0034 2800 movs r0, r5 + 438 0036 FFF7FEFF bl HW_GPIO_SetIrq + 439 .LVL38: + 155:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 440 .loc 1 155 0 + 441 @ sp needed + 442 .LVL39: + 443 003a 70BD pop {r4, r5, r6, pc} + 444 .L25: + 445 .align 2 + 446 .L24: + 447 003c 00040050 .word 1342178304 + 448 .cfi_endproc + 449 .LFE99: + 451 .section .text.SX1272GetPaSelect,"ax",%progbits + 452 .align 1 + 453 .global SX1272GetPaSelect + 454 .syntax unified + 455 .code 16 + 456 .thumb_func + 457 .fpu softvfp + 459 SX1272GetPaSelect: + ARM GAS /tmp/ccy8fBTW.s page 14 + + + 460 .LFB102: + 232:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** return RF_PACONFIG_PASELECT_RFO; + 461 .loc 1 232 0 + 462 .cfi_startproc + 463 @ args = 0, pretend = 0, frame = 0 + 464 @ frame_needed = 0, uses_anonymous_args = 0 + 465 @ link register save eliminated. + 466 .LVL40: + 234:./Drivers/BSP/sx1272mb2das/sx1272mb2das.c **** + 467 .loc 1 234 0 + 468 0000 0020 movs r0, #0 + 469 .LVL41: + 470 @ sp needed + 471 0002 7047 bx lr + 472 .cfi_endproc + 473 .LFE102: + 475 .global Radio + 476 .section .data.BoardCallbacks,"aw",%progbits + 477 .align 2 + 478 .set .LANCHOR0,. + 0 + 481 BoardCallbacks: + 482 0000 00000000 .word SX1272SetXO + 483 0004 00000000 .word SX1272GetWakeTime + 484 0008 00000000 .word SX1272IoIrqInit + 485 000c 00000000 .word SX1272SetRfTxPower + 486 0010 00000000 .word SX1272SetAntSwLowPower + 487 0014 00000000 .word SX1272SetAntSw + 488 .section .rodata.Radio,"a",%progbits + 489 .align 2 + 492 Radio: + 493 0000 00000000 .word SX1272IoInit + 494 0004 00000000 .word SX1272IoDeInit + 495 0008 00000000 .word SX1272Init + 496 000c 00000000 .word SX1272GetStatus + 497 0010 00000000 .word SX1272SetModem + 498 0014 00000000 .word SX1272SetChannel + 499 0018 00000000 .word SX1272IsChannelFree + 500 001c 00000000 .word SX1272Random + 501 0020 00000000 .word SX1272SetRxConfig + 502 0024 00000000 .word SX1272SetTxConfig + 503 0028 00000000 .word SX1272CheckRfFrequency + 504 002c 00000000 .word SX1272GetTimeOnAir + 505 0030 00000000 .word SX1272Send + 506 0034 00000000 .word SX1272SetSleep + 507 0038 00000000 .word SX1272SetStby + 508 003c 00000000 .word SX1272SetRx + 509 0040 00000000 .word SX1272StartCad + 510 0044 00000000 .word SX1272SetTxContinuousWave + 511 0048 00000000 .word SX1272ReadRssi + 512 004c 00000000 .word SX1272Write + 513 0050 00000000 .word SX1272Read + 514 0054 00000000 .word SX1272WriteBuffer + 515 0058 00000000 .word SX1272ReadBuffer + 516 005c 00000000 .word SX1272SetMaxPayloadLength + 517 0060 00000000 .word SX1272SetPublicNetwork + 518 0064 00000000 .word SX1272GetRadioWakeUpTime + 519 .text + ARM GAS /tmp/ccy8fBTW.s page 15 + + + 520 .Letext0: + 521 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 522 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 523 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 524 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 525 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 526 .file 7 "/usr/arm-none-eabi/include/math.h" + 527 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 528 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 529 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 530 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 531 .file 12 "Middlewares/Third_Party/Lora/Phy/radio.h" + 532 .file 13 "Drivers/BSP/Components/sx1272/sx1272.h" + 533 .file 14 "Inc/hw_gpio.h" + 534 .file 15 "" + ARM GAS /tmp/ccy8fBTW.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 sx1272mb2das.c + /tmp/ccy8fBTW.s:16 .text.SX1272GetWakeTime:0000000000000000 $t + /tmp/ccy8fBTW.s:23 .text.SX1272GetWakeTime:0000000000000000 SX1272GetWakeTime + /tmp/ccy8fBTW.s:39 .text.SX1272SetXO:0000000000000000 $t + /tmp/ccy8fBTW.s:46 .text.SX1272SetXO:0000000000000000 SX1272SetXO + /tmp/ccy8fBTW.s:61 .text.SX1272SetAntSwLowPower:0000000000000000 $t + /tmp/ccy8fBTW.s:68 .text.SX1272SetAntSwLowPower:0000000000000000 SX1272SetAntSwLowPower + /tmp/ccy8fBTW.s:83 .text.SX1272SetAntSw:0000000000000000 $t + /tmp/ccy8fBTW.s:90 .text.SX1272SetAntSw:0000000000000000 SX1272SetAntSw + /tmp/ccy8fBTW.s:119 .text.SX1272SetAntSw:0000000000000014 $d + /tmp/ccy8fBTW.s:124 .text.SX1272CheckRfFrequency:0000000000000000 $t + /tmp/ccy8fBTW.s:131 .text.SX1272CheckRfFrequency:0000000000000000 SX1272CheckRfFrequency + /tmp/ccy8fBTW.s:148 .text.SX1272SetRfTxPower:0000000000000000 $t + /tmp/ccy8fBTW.s:155 .text.SX1272SetRfTxPower:0000000000000000 SX1272SetRfTxPower + /tmp/ccy8fBTW.s:232 .text.SX1272IoInit:0000000000000000 $t + /tmp/ccy8fBTW.s:239 .text.SX1272IoInit:0000000000000000 SX1272IoInit + /tmp/ccy8fBTW.s:306 .text.SX1272IoInit:0000000000000054 $d + /tmp/ccy8fBTW.s:313 .text.SX1272IoDeInit:0000000000000000 $t + /tmp/ccy8fBTW.s:320 .text.SX1272IoDeInit:0000000000000000 SX1272IoDeInit + /tmp/ccy8fBTW.s:380 .text.SX1272IoDeInit:0000000000000048 $d + /tmp/ccy8fBTW.s:386 .text.SX1272IoIrqInit:0000000000000000 $t + /tmp/ccy8fBTW.s:393 .text.SX1272IoIrqInit:0000000000000000 SX1272IoIrqInit + /tmp/ccy8fBTW.s:447 .text.SX1272IoIrqInit:000000000000003c $d + /tmp/ccy8fBTW.s:452 .text.SX1272GetPaSelect:0000000000000000 $t + /tmp/ccy8fBTW.s:459 .text.SX1272GetPaSelect:0000000000000000 SX1272GetPaSelect + /tmp/ccy8fBTW.s:492 .rodata.Radio:0000000000000000 Radio + /tmp/ccy8fBTW.s:477 .data.BoardCallbacks:0000000000000000 $d + /tmp/ccy8fBTW.s:481 .data.BoardCallbacks:0000000000000000 BoardCallbacks + /tmp/ccy8fBTW.s:489 .rodata.Radio:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +SX1272 +SX1272Read +SX1272Write +memset +SX1272BoardInit +HW_GPIO_Init +HW_GPIO_SetIrq +SX1272Init +SX1272GetStatus +SX1272SetModem +SX1272SetChannel +SX1272IsChannelFree +SX1272Random +SX1272SetRxConfig +SX1272SetTxConfig +SX1272GetTimeOnAir +SX1272Send +SX1272SetSleep +SX1272SetStby +SX1272SetRx +SX1272StartCad +SX1272SetTxContinuousWave +SX1272ReadRssi +SX1272WriteBuffer + ARM GAS /tmp/ccy8fBTW.s page 17 + + +SX1272ReadBuffer +SX1272SetMaxPayloadLength +SX1272SetPublicNetwork +SX1272GetRadioWakeUpTime diff --git a/build/system_stm32l0xx.d b/build/system_stm32l0xx.d new file mode 100644 index 0000000..116d090 --- /dev/null +++ b/build/system_stm32l0xx.d @@ -0,0 +1,102 @@ +build/system_stm32l0xx.d: Src/system_stm32l0xx.c \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: diff --git a/build/system_stm32l0xx.lst b/build/system_stm32l0xx.lst new file mode 100644 index 0000000..ede9b07 --- /dev/null +++ b/build/system_stm32l0xx.lst @@ -0,0 +1,674 @@ +ARM GAS /tmp/ccISlhEt.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "system_stm32l0xx.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SystemInit,"ax",%progbits + 16 .align 1 + 17 .global SystemInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 SystemInit: + 24 .LFB39: + 25 .file 1 "./Src/system_stm32l0xx.c" + 1:./Src/system_stm32l0xx.c **** /** + 2:./Src/system_stm32l0xx.c **** ****************************************************************************** + 3:./Src/system_stm32l0xx.c **** * @file system_stm32l0xx.c + 4:./Src/system_stm32l0xx.c **** * @author MCD Application Team + 5:./Src/system_stm32l0xx.c **** * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. + 6:./Src/system_stm32l0xx.c **** * + 7:./Src/system_stm32l0xx.c **** * This file provides two functions and one global variable to be called from + 8:./Src/system_stm32l0xx.c **** * user application: + 9:./Src/system_stm32l0xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:./Src/system_stm32l0xx.c **** * before branch to main program. This call is made inside + 11:./Src/system_stm32l0xx.c **** * the "startup_stm32l0xx.s" file. + 12:./Src/system_stm32l0xx.c **** * + 13:./Src/system_stm32l0xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:./Src/system_stm32l0xx.c **** * by the user application to setup the SysTick + 15:./Src/system_stm32l0xx.c **** * timer or configure other parameters. + 16:./Src/system_stm32l0xx.c **** * + 17:./Src/system_stm32l0xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:./Src/system_stm32l0xx.c **** * be called whenever the core clock is changed + 19:./Src/system_stm32l0xx.c **** * during program execution. + 20:./Src/system_stm32l0xx.c **** * + 21:./Src/system_stm32l0xx.c **** * + 22:./Src/system_stm32l0xx.c **** ****************************************************************************** + 23:./Src/system_stm32l0xx.c **** * @attention + 24:./Src/system_stm32l0xx.c **** * + 25:./Src/system_stm32l0xx.c **** *

© COPYRIGHT(c) 2016 STMicroelectronics

+ 26:./Src/system_stm32l0xx.c **** * + 27:./Src/system_stm32l0xx.c **** * Redistribution and use in source and binary forms, with or without modification, + 28:./Src/system_stm32l0xx.c **** * are permitted provided that the following conditions are met: + 29:./Src/system_stm32l0xx.c **** * 1. Redistributions of source code must retain the above copyright notice, + 30:./Src/system_stm32l0xx.c **** * this list of conditions and the following disclaimer. + 31:./Src/system_stm32l0xx.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 32:./Src/system_stm32l0xx.c **** * this list of conditions and the following disclaimer in the documentation + 33:./Src/system_stm32l0xx.c **** * and/or other materials provided with the distribution. + ARM GAS /tmp/ccISlhEt.s page 2 + + + 34:./Src/system_stm32l0xx.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors + 35:./Src/system_stm32l0xx.c **** * may be used to endorse or promote products derived from this software + 36:./Src/system_stm32l0xx.c **** * without specific prior written permission. + 37:./Src/system_stm32l0xx.c **** * + 38:./Src/system_stm32l0xx.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 39:./Src/system_stm32l0xx.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 40:./Src/system_stm32l0xx.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + 41:./Src/system_stm32l0xx.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + 42:./Src/system_stm32l0xx.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + 43:./Src/system_stm32l0xx.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + 44:./Src/system_stm32l0xx.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + 45:./Src/system_stm32l0xx.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + 46:./Src/system_stm32l0xx.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 47:./Src/system_stm32l0xx.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 48:./Src/system_stm32l0xx.c **** * + 49:./Src/system_stm32l0xx.c **** ****************************************************************************** + 50:./Src/system_stm32l0xx.c **** */ + 51:./Src/system_stm32l0xx.c **** + 52:./Src/system_stm32l0xx.c **** /** @addtogroup CMSIS + 53:./Src/system_stm32l0xx.c **** * @{ + 54:./Src/system_stm32l0xx.c **** */ + 55:./Src/system_stm32l0xx.c **** + 56:./Src/system_stm32l0xx.c **** /** @addtogroup stm32l0xx_system + 57:./Src/system_stm32l0xx.c **** * @{ + 58:./Src/system_stm32l0xx.c **** */ + 59:./Src/system_stm32l0xx.c **** + 60:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_Includes + 61:./Src/system_stm32l0xx.c **** * @{ + 62:./Src/system_stm32l0xx.c **** */ + 63:./Src/system_stm32l0xx.c **** + 64:./Src/system_stm32l0xx.c **** #include "stm32l0xx.h" + 65:./Src/system_stm32l0xx.c **** + 66:./Src/system_stm32l0xx.c **** #if !defined (HSE_VALUE) + 67:./Src/system_stm32l0xx.c **** #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + 68:./Src/system_stm32l0xx.c **** #endif /* HSE_VALUE */ + 69:./Src/system_stm32l0xx.c **** + 70:./Src/system_stm32l0xx.c **** #if !defined (MSI_VALUE) + 71:./Src/system_stm32l0xx.c **** #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ + 72:./Src/system_stm32l0xx.c **** #endif /* MSI_VALUE */ + 73:./Src/system_stm32l0xx.c **** + 74:./Src/system_stm32l0xx.c **** #if !defined (HSI_VALUE) + 75:./Src/system_stm32l0xx.c **** #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + 76:./Src/system_stm32l0xx.c **** #endif /* HSI_VALUE */ + 77:./Src/system_stm32l0xx.c **** + 78:./Src/system_stm32l0xx.c **** + 79:./Src/system_stm32l0xx.c **** /** + 80:./Src/system_stm32l0xx.c **** * @} + 81:./Src/system_stm32l0xx.c **** */ + 82:./Src/system_stm32l0xx.c **** + 83:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_TypesDefinitions + 84:./Src/system_stm32l0xx.c **** * @{ + 85:./Src/system_stm32l0xx.c **** */ + 86:./Src/system_stm32l0xx.c **** + 87:./Src/system_stm32l0xx.c **** /** + 88:./Src/system_stm32l0xx.c **** * @} + 89:./Src/system_stm32l0xx.c **** */ + 90:./Src/system_stm32l0xx.c **** + ARM GAS /tmp/ccISlhEt.s page 3 + + + 91:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_Defines + 92:./Src/system_stm32l0xx.c **** * @{ + 93:./Src/system_stm32l0xx.c **** */ + 94:./Src/system_stm32l0xx.c **** /************************* Miscellaneous Configuration ************************/ + 95:./Src/system_stm32l0xx.c **** + 96:./Src/system_stm32l0xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in + 97:./Src/system_stm32l0xx.c **** Internal SRAM. */ + 98:./Src/system_stm32l0xx.c **** /* #define VECT_TAB_SRAM */ + 99:./Src/system_stm32l0xx.c **** #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + 100:./Src/system_stm32l0xx.c **** This value must be a multiple of 0x200. */ + 101:./Src/system_stm32l0xx.c **** /******************************************************************************/ + 102:./Src/system_stm32l0xx.c **** /** + 103:./Src/system_stm32l0xx.c **** * @} + 104:./Src/system_stm32l0xx.c **** */ + 105:./Src/system_stm32l0xx.c **** + 106:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_Macros + 107:./Src/system_stm32l0xx.c **** * @{ + 108:./Src/system_stm32l0xx.c **** */ + 109:./Src/system_stm32l0xx.c **** + 110:./Src/system_stm32l0xx.c **** /** + 111:./Src/system_stm32l0xx.c **** * @} + 112:./Src/system_stm32l0xx.c **** */ + 113:./Src/system_stm32l0xx.c **** + 114:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_Variables + 115:./Src/system_stm32l0xx.c **** * @{ + 116:./Src/system_stm32l0xx.c **** */ + 117:./Src/system_stm32l0xx.c **** /* This variable is updated in three ways: + 118:./Src/system_stm32l0xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 119:./Src/system_stm32l0xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 120:./Src/system_stm32l0xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 121:./Src/system_stm32l0xx.c **** Note: If you use this function to configure the system clock; then there + 122:./Src/system_stm32l0xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock + 123:./Src/system_stm32l0xx.c **** variable is updated automatically. + 124:./Src/system_stm32l0xx.c **** */ + 125:./Src/system_stm32l0xx.c **** uint32_t SystemCoreClock = 2000000U; + 126:./Src/system_stm32l0xx.c **** const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U + 127:./Src/system_stm32l0xx.c **** const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + 128:./Src/system_stm32l0xx.c **** const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; + 129:./Src/system_stm32l0xx.c **** + 130:./Src/system_stm32l0xx.c **** /** + 131:./Src/system_stm32l0xx.c **** * @} + 132:./Src/system_stm32l0xx.c **** */ + 133:./Src/system_stm32l0xx.c **** + 134:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes + 135:./Src/system_stm32l0xx.c **** * @{ + 136:./Src/system_stm32l0xx.c **** */ + 137:./Src/system_stm32l0xx.c **** + 138:./Src/system_stm32l0xx.c **** /** + 139:./Src/system_stm32l0xx.c **** * @} + 140:./Src/system_stm32l0xx.c **** */ + 141:./Src/system_stm32l0xx.c **** + 142:./Src/system_stm32l0xx.c **** /** @addtogroup STM32L0xx_System_Private_Functions + 143:./Src/system_stm32l0xx.c **** * @{ + 144:./Src/system_stm32l0xx.c **** */ + 145:./Src/system_stm32l0xx.c **** + 146:./Src/system_stm32l0xx.c **** /** + 147:./Src/system_stm32l0xx.c **** * @brief Setup the microcontroller system. + ARM GAS /tmp/ccISlhEt.s page 4 + + + 148:./Src/system_stm32l0xx.c **** * @param None + 149:./Src/system_stm32l0xx.c **** * @retval None + 150:./Src/system_stm32l0xx.c **** */ + 151:./Src/system_stm32l0xx.c **** void SystemInit (void) + 152:./Src/system_stm32l0xx.c **** { + 26 .loc 1 152 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 153:./Src/system_stm32l0xx.c **** /*!< Set MSION bit */ + 154:./Src/system_stm32l0xx.c **** RCC->CR |= (uint32_t)0x00000100U; + 31 .loc 1 154 0 + 32 0000 104B ldr r3, .L2 + 33 0002 1968 ldr r1, [r3] + 34 0004 8022 movs r2, #128 + 35 0006 5200 lsls r2, r2, #1 + 36 0008 0A43 orrs r2, r1 + 37 000a 1A60 str r2, [r3] + 155:./Src/system_stm32l0xx.c **** + 156:./Src/system_stm32l0xx.c **** /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + 157:./Src/system_stm32l0xx.c **** RCC->CFGR &= (uint32_t) 0x88FF400CU; + 38 .loc 1 157 0 + 39 000c DA68 ldr r2, [r3, #12] + 40 000e 0E49 ldr r1, .L2+4 + 41 0010 0A40 ands r2, r1 + 42 0012 DA60 str r2, [r3, #12] + 158:./Src/system_stm32l0xx.c **** + 159:./Src/system_stm32l0xx.c **** /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ + 160:./Src/system_stm32l0xx.c **** RCC->CR &= (uint32_t)0xFEF6FFF6U; + 43 .loc 1 160 0 + 44 0014 1A68 ldr r2, [r3] + 45 0016 0D49 ldr r1, .L2+8 + 46 0018 0A40 ands r2, r1 + 47 001a 1A60 str r2, [r3] + 161:./Src/system_stm32l0xx.c **** + 162:./Src/system_stm32l0xx.c **** /*!< Reset HSI48ON bit */ + 163:./Src/system_stm32l0xx.c **** RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; + 48 .loc 1 163 0 + 49 001c 9A68 ldr r2, [r3, #8] + 50 001e 0121 movs r1, #1 + 51 0020 8A43 bics r2, r1 + 52 0022 9A60 str r2, [r3, #8] + 164:./Src/system_stm32l0xx.c **** + 165:./Src/system_stm32l0xx.c **** /*!< Reset HSEBYP bit */ + 166:./Src/system_stm32l0xx.c **** RCC->CR &= (uint32_t)0xFFFBFFFFU; + 53 .loc 1 166 0 + 54 0024 1A68 ldr r2, [r3] + 55 0026 0A49 ldr r1, .L2+12 + 56 0028 0A40 ands r2, r1 + 57 002a 1A60 str r2, [r3] + 167:./Src/system_stm32l0xx.c **** + 168:./Src/system_stm32l0xx.c **** /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + 169:./Src/system_stm32l0xx.c **** RCC->CFGR &= (uint32_t)0xFF02FFFFU; + 58 .loc 1 169 0 + 59 002c DA68 ldr r2, [r3, #12] + 60 002e 0949 ldr r1, .L2+16 + ARM GAS /tmp/ccISlhEt.s page 5 + + + 61 0030 0A40 ands r2, r1 + 62 0032 DA60 str r2, [r3, #12] + 170:./Src/system_stm32l0xx.c **** + 171:./Src/system_stm32l0xx.c **** /*!< Disable all interrupts */ + 172:./Src/system_stm32l0xx.c **** RCC->CIER = 0x00000000U; + 63 .loc 1 172 0 + 64 0034 0022 movs r2, #0 + 65 0036 1A61 str r2, [r3, #16] + 173:./Src/system_stm32l0xx.c **** + 174:./Src/system_stm32l0xx.c **** /* Configure the Vector Table location add offset address ------------------*/ + 175:./Src/system_stm32l0xx.c **** #ifdef VECT_TAB_SRAM + 176:./Src/system_stm32l0xx.c **** SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + 177:./Src/system_stm32l0xx.c **** #else + 178:./Src/system_stm32l0xx.c **** SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 66 .loc 1 178 0 + 67 0038 074B ldr r3, .L2+20 + 68 003a 8022 movs r2, #128 + 69 003c 1205 lsls r2, r2, #20 + 70 003e 9A60 str r2, [r3, #8] + 179:./Src/system_stm32l0xx.c **** #endif + 180:./Src/system_stm32l0xx.c **** } + 71 .loc 1 180 0 + 72 @ sp needed + 73 0040 7047 bx lr + 74 .L3: + 75 0042 C046 .align 2 + 76 .L2: + 77 0044 00100240 .word 1073876992 + 78 0048 0C40FF88 .word -1996537844 + 79 004c F6FFF6FE .word -17367050 + 80 0050 FFFFFBFF .word -262145 + 81 0054 FFFF02FF .word -16580609 + 82 0058 00ED00E0 .word -536810240 + 83 .cfi_endproc + 84 .LFE39: + 86 .global __aeabi_uidiv + 87 .section .text.SystemCoreClockUpdate,"ax",%progbits + 88 .align 1 + 89 .global SystemCoreClockUpdate + 90 .syntax unified + 91 .code 16 + 92 .thumb_func + 93 .fpu softvfp + 95 SystemCoreClockUpdate: + 96 .LFB40: + 181:./Src/system_stm32l0xx.c **** + 182:./Src/system_stm32l0xx.c **** /** + 183:./Src/system_stm32l0xx.c **** * @brief Update SystemCoreClock according to Clock Register Values + 184:./Src/system_stm32l0xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 185:./Src/system_stm32l0xx.c **** * be used by the user application to setup the SysTick timer or configure + 186:./Src/system_stm32l0xx.c **** * other parameters. + 187:./Src/system_stm32l0xx.c **** * + 188:./Src/system_stm32l0xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 189:./Src/system_stm32l0xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 190:./Src/system_stm32l0xx.c **** * based on this variable will be incorrect. + 191:./Src/system_stm32l0xx.c **** * + 192:./Src/system_stm32l0xx.c **** * @note - The system frequency computed by this function is not the real + ARM GAS /tmp/ccISlhEt.s page 6 + + + 193:./Src/system_stm32l0xx.c **** * frequency in the chip. It is calculated based on the predefined + 194:./Src/system_stm32l0xx.c **** * constant and the selected clock source: + 195:./Src/system_stm32l0xx.c **** * + 196:./Src/system_stm32l0xx.c **** * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + 197:./Src/system_stm32l0xx.c **** * value as defined by the MSI range. + 198:./Src/system_stm32l0xx.c **** * + 199:./Src/system_stm32l0xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + 200:./Src/system_stm32l0xx.c **** * + 201:./Src/system_stm32l0xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + 202:./Src/system_stm32l0xx.c **** * + 203:./Src/system_stm32l0xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + 204:./Src/system_stm32l0xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 205:./Src/system_stm32l0xx.c **** * + 206:./Src/system_stm32l0xx.c **** * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value + 207:./Src/system_stm32l0xx.c **** * 16 MHz) but the real value may vary depending on the variations + 208:./Src/system_stm32l0xx.c **** * in voltage and temperature. + 209:./Src/system_stm32l0xx.c **** * + 210:./Src/system_stm32l0xx.c **** * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value + 211:./Src/system_stm32l0xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 212:./Src/system_stm32l0xx.c **** * frequency of the crystal used. Otherwise, this function may + 213:./Src/system_stm32l0xx.c **** * have wrong result. + 214:./Src/system_stm32l0xx.c **** * + 215:./Src/system_stm32l0xx.c **** * - The result of this function could be not correct when using fractional + 216:./Src/system_stm32l0xx.c **** * value for HSE crystal. + 217:./Src/system_stm32l0xx.c **** * @param None + 218:./Src/system_stm32l0xx.c **** * @retval None + 219:./Src/system_stm32l0xx.c **** */ + 220:./Src/system_stm32l0xx.c **** void SystemCoreClockUpdate (void) + 221:./Src/system_stm32l0xx.c **** { + 97 .loc 1 221 0 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 0000 10B5 push {r4, lr} + 102 .LCFI0: + 103 .cfi_def_cfa_offset 8 + 104 .cfi_offset 4, -8 + 105 .cfi_offset 14, -4 + 106 .LVL0: + 222:./Src/system_stm32l0xx.c **** uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; + 223:./Src/system_stm32l0xx.c **** + 224:./Src/system_stm32l0xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 225:./Src/system_stm32l0xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; + 107 .loc 1 225 0 + 108 0002 304B ldr r3, .L14 + 109 0004 DA68 ldr r2, [r3, #12] + 110 0006 0C23 movs r3, #12 + 111 0008 1340 ands r3, r2 + 112 .LVL1: + 226:./Src/system_stm32l0xx.c **** + 227:./Src/system_stm32l0xx.c **** switch (tmp) + 113 .loc 1 227 0 + 114 000a 042B cmp r3, #4 + 115 000c 39D0 beq .L6 + 116 000e 1ED9 bls .L13 + 117 0010 082B cmp r3, #8 + 118 0012 3AD0 beq .L9 + ARM GAS /tmp/ccISlhEt.s page 7 + + + 119 0014 0C2B cmp r3, #12 + 120 0016 48D1 bne .L5 + 228:./Src/system_stm32l0xx.c **** { + 229:./Src/system_stm32l0xx.c **** case 0x00U: /* MSI used as system clock */ + 230:./Src/system_stm32l0xx.c **** msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + 231:./Src/system_stm32l0xx.c **** SystemCoreClock = (32768U * (1U << (msirange + 1U))); + 232:./Src/system_stm32l0xx.c **** break; + 233:./Src/system_stm32l0xx.c **** case 0x04U: /* HSI used as system clock */ + 234:./Src/system_stm32l0xx.c **** SystemCoreClock = HSI_VALUE; + 235:./Src/system_stm32l0xx.c **** break; + 236:./Src/system_stm32l0xx.c **** case 0x08U: /* HSE used as system clock */ + 237:./Src/system_stm32l0xx.c **** SystemCoreClock = HSE_VALUE; + 238:./Src/system_stm32l0xx.c **** break; + 239:./Src/system_stm32l0xx.c **** case 0x0CU: /* PLL used as system clock */ + 240:./Src/system_stm32l0xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/ + 241:./Src/system_stm32l0xx.c **** pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + 121 .loc 1 241 0 + 122 0018 2A4A ldr r2, .L14 + 123 001a D068 ldr r0, [r2, #12] + 124 .LVL2: + 242:./Src/system_stm32l0xx.c **** plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + 125 .loc 1 242 0 + 126 001c D168 ldr r1, [r2, #12] + 127 .LVL3: + 243:./Src/system_stm32l0xx.c **** pllmul = PLLMulTable[(pllmul >> 18U)]; + 128 .loc 1 243 0 + 129 001e 800C lsrs r0, r0, #18 + 130 .LVL4: + 131 0020 0F23 movs r3, #15 + 132 .LVL5: + 133 0022 0340 ands r3, r0 + 134 0024 2848 ldr r0, .L14+4 + 135 0026 C05C ldrb r0, [r0, r3] + 136 .LVL6: + 244:./Src/system_stm32l0xx.c **** plldiv = (plldiv >> 22U) + 1U; + 137 .loc 1 244 0 + 138 0028 8B0D lsrs r3, r1, #22 + 139 002a 0321 movs r1, #3 + 140 .LVL7: + 141 002c 1940 ands r1, r3 + 142 002e 0131 adds r1, r1, #1 + 143 .LVL8: + 245:./Src/system_stm32l0xx.c **** + 246:./Src/system_stm32l0xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 144 .loc 1 246 0 + 145 0030 D368 ldr r3, [r2, #12] + 146 .LVL9: + 247:./Src/system_stm32l0xx.c **** + 248:./Src/system_stm32l0xx.c **** if (pllsource == 0x00U) + 147 .loc 1 248 0 + 148 0032 DB03 lsls r3, r3, #15 + 149 0034 2DD4 bmi .L12 + 150 .LVL10: + 249:./Src/system_stm32l0xx.c **** { + 250:./Src/system_stm32l0xx.c **** /* HSI oscillator clock selected as PLL clock entry */ + 251:./Src/system_stm32l0xx.c **** SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + 151 .loc 1 251 0 + ARM GAS /tmp/ccISlhEt.s page 8 + + + 152 0036 4301 lsls r3, r0, #5 + 153 0038 1B1A subs r3, r3, r0 + 154 003a 9A01 lsls r2, r3, #6 + 155 003c D31A subs r3, r2, r3 + 156 003e DB00 lsls r3, r3, #3 + 157 0040 1B18 adds r3, r3, r0 + 158 0042 9802 lsls r0, r3, #10 + 159 .LVL11: + 160 0044 FFF7FEFF bl __aeabi_uidiv + 161 .LVL12: + 162 0048 204B ldr r3, .L14+8 + 163 004a 1860 str r0, [r3] + 164 004c 0DE0 b .L11 + 165 .LVL13: + 166 .L13: + 227:./Src/system_stm32l0xx.c **** { + 167 .loc 1 227 0 + 168 004e 002B cmp r3, #0 + 169 0050 2BD1 bne .L5 + 230:./Src/system_stm32l0xx.c **** SystemCoreClock = (32768U * (1U << (msirange + 1U))); + 170 .loc 1 230 0 + 171 0052 1C4B ldr r3, .L14 + 172 .LVL14: + 173 0054 5A68 ldr r2, [r3, #4] + 174 .LVL15: + 175 0056 520B lsrs r2, r2, #13 + 176 0058 0723 movs r3, #7 + 177 005a 1340 ands r3, r2 + 178 .LVL16: + 231:./Src/system_stm32l0xx.c **** break; + 179 .loc 1 231 0 + 180 005c 0133 adds r3, r3, #1 + 181 .LVL17: + 182 005e 8022 movs r2, #128 + 183 0060 1202 lsls r2, r2, #8 + 184 0062 9A40 lsls r2, r2, r3 + 185 0064 1300 movs r3, r2 + 186 .LVL18: + 187 0066 194A ldr r2, .L14+8 + 188 0068 1360 str r3, [r2] + 189 .LVL19: + 190 .L11: + 252:./Src/system_stm32l0xx.c **** } + 253:./Src/system_stm32l0xx.c **** else + 254:./Src/system_stm32l0xx.c **** { + 255:./Src/system_stm32l0xx.c **** /* HSE selected as PLL clock entry */ + 256:./Src/system_stm32l0xx.c **** SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + 257:./Src/system_stm32l0xx.c **** } + 258:./Src/system_stm32l0xx.c **** break; + 259:./Src/system_stm32l0xx.c **** default: /* MSI used as system clock */ + 260:./Src/system_stm32l0xx.c **** msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + 261:./Src/system_stm32l0xx.c **** SystemCoreClock = (32768U * (1U << (msirange + 1U))); + 262:./Src/system_stm32l0xx.c **** break; + 263:./Src/system_stm32l0xx.c **** } + 264:./Src/system_stm32l0xx.c **** /* Compute HCLK clock frequency --------------------------------------------*/ + 265:./Src/system_stm32l0xx.c **** /* Get HCLK prescaler */ + 266:./Src/system_stm32l0xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + ARM GAS /tmp/ccISlhEt.s page 9 + + + 191 .loc 1 266 0 + 192 006a 164B ldr r3, .L14 + 193 006c DA68 ldr r2, [r3, #12] + 194 006e 1209 lsrs r2, r2, #4 + 195 0070 0F23 movs r3, #15 + 196 0072 1340 ands r3, r2 + 197 0074 164A ldr r2, .L14+12 + 198 0076 D35C ldrb r3, [r2, r3] + 199 .LVL20: + 267:./Src/system_stm32l0xx.c **** /* HCLK clock frequency */ + 268:./Src/system_stm32l0xx.c **** SystemCoreClock >>= tmp; + 200 .loc 1 268 0 + 201 0078 144A ldr r2, .L14+8 + 202 007a 1168 ldr r1, [r2] + 203 007c D940 lsrs r1, r1, r3 + 204 007e 1160 str r1, [r2] + 269:./Src/system_stm32l0xx.c **** } + 205 .loc 1 269 0 + 206 @ sp needed + 207 0080 10BD pop {r4, pc} + 208 .LVL21: + 209 .L6: + 234:./Src/system_stm32l0xx.c **** break; + 210 .loc 1 234 0 + 211 0082 124B ldr r3, .L14+8 + 212 .LVL22: + 213 0084 134A ldr r2, .L14+16 + 214 .LVL23: + 215 0086 1A60 str r2, [r3] + 235:./Src/system_stm32l0xx.c **** case 0x08U: /* HSE used as system clock */ + 216 .loc 1 235 0 + 217 0088 EFE7 b .L11 + 218 .LVL24: + 219 .L9: + 237:./Src/system_stm32l0xx.c **** break; + 220 .loc 1 237 0 + 221 008a 104B ldr r3, .L14+8 + 222 .LVL25: + 223 008c 124A ldr r2, .L14+20 + 224 .LVL26: + 225 008e 1A60 str r2, [r3] + 238:./Src/system_stm32l0xx.c **** case 0x0CU: /* PLL used as system clock */ + 226 .loc 1 238 0 + 227 0090 EBE7 b .L11 + 228 .LVL27: + 229 .L12: + 256:./Src/system_stm32l0xx.c **** } + 230 .loc 1 256 0 + 231 0092 4201 lsls r2, r0, #5 + 232 0094 121A subs r2, r2, r0 + 233 0096 9301 lsls r3, r2, #6 + 234 0098 9B1A subs r3, r3, r2 + 235 009a DB00 lsls r3, r3, #3 + 236 009c 1B18 adds r3, r3, r0 + 237 009e 5802 lsls r0, r3, #9 + 238 .LVL28: + 239 00a0 FFF7FEFF bl __aeabi_uidiv + ARM GAS /tmp/ccISlhEt.s page 10 + + + 240 .LVL29: + 241 00a4 094B ldr r3, .L14+8 + 242 00a6 1860 str r0, [r3] + 243 00a8 DFE7 b .L11 + 244 .LVL30: + 245 .L5: + 260:./Src/system_stm32l0xx.c **** SystemCoreClock = (32768U * (1U << (msirange + 1U))); + 246 .loc 1 260 0 + 247 00aa 064B ldr r3, .L14 + 248 .LVL31: + 249 00ac 5A68 ldr r2, [r3, #4] + 250 .LVL32: + 251 00ae 520B lsrs r2, r2, #13 + 252 00b0 0723 movs r3, #7 + 253 00b2 1340 ands r3, r2 + 254 .LVL33: + 261:./Src/system_stm32l0xx.c **** break; + 255 .loc 1 261 0 + 256 00b4 0133 adds r3, r3, #1 + 257 .LVL34: + 258 00b6 8022 movs r2, #128 + 259 00b8 1202 lsls r2, r2, #8 + 260 00ba 9A40 lsls r2, r2, r3 + 261 00bc 1300 movs r3, r2 + 262 .LVL35: + 263 00be 034A ldr r2, .L14+8 + 264 00c0 1360 str r3, [r2] + 262:./Src/system_stm32l0xx.c **** } + 265 .loc 1 262 0 + 266 00c2 D2E7 b .L11 + 267 .L15: + 268 .align 2 + 269 .L14: + 270 00c4 00100240 .word 1073876992 + 271 00c8 00000000 .word .LANCHOR1 + 272 00cc 00000000 .word .LANCHOR0 + 273 00d0 00000000 .word .LANCHOR2 + 274 00d4 0024F400 .word 16000000 + 275 00d8 00127A00 .word 8000000 + 276 .cfi_endproc + 277 .LFE40: + 279 .global PLLMulTable + 280 .global APBPrescTable + 281 .global AHBPrescTable + 282 .global SystemCoreClock + 283 .section .data.SystemCoreClock,"aw",%progbits + 284 .align 2 + 285 .set .LANCHOR0,. + 0 + 288 SystemCoreClock: + 289 0000 80841E00 .word 2000000 + 290 .section .rodata.AHBPrescTable,"a",%progbits + 291 .align 2 + 292 .set .LANCHOR2,. + 0 + 295 AHBPrescTable: + 296 0000 00 .byte 0 + 297 0001 00 .byte 0 + 298 0002 00 .byte 0 + ARM GAS /tmp/ccISlhEt.s page 11 + + + 299 0003 00 .byte 0 + 300 0004 00 .byte 0 + 301 0005 00 .byte 0 + 302 0006 00 .byte 0 + 303 0007 00 .byte 0 + 304 0008 01 .byte 1 + 305 0009 02 .byte 2 + 306 000a 03 .byte 3 + 307 000b 04 .byte 4 + 308 000c 06 .byte 6 + 309 000d 07 .byte 7 + 310 000e 08 .byte 8 + 311 000f 09 .byte 9 + 312 .section .rodata.APBPrescTable,"a",%progbits + 313 .align 2 + 316 APBPrescTable: + 317 0000 00 .byte 0 + 318 0001 00 .byte 0 + 319 0002 00 .byte 0 + 320 0003 00 .byte 0 + 321 0004 01 .byte 1 + 322 0005 02 .byte 2 + 323 0006 03 .byte 3 + 324 0007 04 .byte 4 + 325 .section .rodata.PLLMulTable,"a",%progbits + 326 .align 2 + 327 .set .LANCHOR1,. + 0 + 330 PLLMulTable: + 331 0000 03 .byte 3 + 332 0001 04 .byte 4 + 333 0002 06 .byte 6 + 334 0003 08 .byte 8 + 335 0004 0C .byte 12 + 336 0005 10 .byte 16 + 337 0006 18 .byte 24 + 338 0007 20 .byte 32 + 339 0008 30 .byte 48 + 340 .text + 341 .Letext0: + 342 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 343 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 344 .file 4 "Drivers/CMSIS/Include/core_cm0plus.h" + 345 .file 5 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 346 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 347 .file 7 "/usr/arm-none-eabi/include/sys/lock.h" + 348 .file 8 "/usr/arm-none-eabi/include/sys/_types.h" + 349 .file 9 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 350 .file 10 "/usr/arm-none-eabi/include/sys/reent.h" + ARM GAS /tmp/ccISlhEt.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 system_stm32l0xx.c + /tmp/ccISlhEt.s:16 .text.SystemInit:0000000000000000 $t + /tmp/ccISlhEt.s:23 .text.SystemInit:0000000000000000 SystemInit + /tmp/ccISlhEt.s:77 .text.SystemInit:0000000000000044 $d + /tmp/ccISlhEt.s:88 .text.SystemCoreClockUpdate:0000000000000000 $t + /tmp/ccISlhEt.s:95 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate + /tmp/ccISlhEt.s:270 .text.SystemCoreClockUpdate:00000000000000c4 $d + /tmp/ccISlhEt.s:330 .rodata.PLLMulTable:0000000000000000 PLLMulTable + /tmp/ccISlhEt.s:316 .rodata.APBPrescTable:0000000000000000 APBPrescTable + /tmp/ccISlhEt.s:295 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable + /tmp/ccISlhEt.s:288 .data.SystemCoreClock:0000000000000000 SystemCoreClock + /tmp/ccISlhEt.s:284 .data.SystemCoreClock:0000000000000000 $d + /tmp/ccISlhEt.s:291 .rodata.AHBPrescTable:0000000000000000 $d + /tmp/ccISlhEt.s:313 .rodata.APBPrescTable:0000000000000000 $d + /tmp/ccISlhEt.s:326 .rodata.PLLMulTable:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv diff --git a/build/timeServer.d b/build/timeServer.d new file mode 100644 index 0000000..dd59ef4 --- /dev/null +++ b/build/timeServer.d @@ -0,0 +1,141 @@ +build/timeServer.d: Middlewares/Third_Party/Lora/Utilities/timeServer.c \ + Inc/hw.h Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h \ + Middlewares/Third_Party/Lora/Utilities/timeServer.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Middlewares/Third_Party/Lora/Utilities/timeServer.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: diff --git a/build/timeServer.lst b/build/timeServer.lst new file mode 100644 index 0000000..31cacd4 --- /dev/null +++ b/build/timeServer.lst @@ -0,0 +1,1694 @@ +ARM GAS /tmp/cciA02i6.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "timeServer.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.TimerSetTimeout,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 TimerSetTimeout: + 23 .LFB107: + 24 .file 1 "./Middlewares/Third_Party/Lora/Utilities/timeServer.c" + 1:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* + 2:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 9:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** Description: Generic lora driver implementation + 10:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 11:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 13:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene + 14:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 15:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /****************************************************************************** + 16:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @file timeserver.c + 17:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @author MCD Application Team + 18:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @version V1.1.2 + 19:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @date 08-September-2017 + 20:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @brief Time server infrastructure + 21:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** ****************************************************************************** + 22:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * @attention + 23:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 24:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 25:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * All rights reserved.

+ 26:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 27:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * Redistribution and use in source and binary forms, with or without + 28:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * modification, are permitted, provided that the following conditions are met: + 29:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 30:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * 1. Redistribution of source code must retain the above copyright notice, + 31:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * this list of conditions and the following disclaimer. + 32:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 33:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * this list of conditions and the following disclaimer in the documentation + 34:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * and/or other materials provided with the distribution. + ARM GAS /tmp/cciA02i6.s page 2 + + + 35:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 36:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * contributors to this software may be used to endorse or promote products + 37:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * derived from this software without specific written permission. + 38:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * 4. This software, including modifications and/or derivative works of this + 39:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * software, must execute solely and exclusively on microcontroller or + 40:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 41:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * 5. Redistribution and use of this software other than as permitted under + 42:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * this license is void and will automatically terminate your rights under + 43:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * this license. + 44:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 45:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 46:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 47:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + 48:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 49:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 50:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 51:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 52:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 53:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 54:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 55:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 56:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 57:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 58:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** ****************************************************************************** + 59:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 60:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 61:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* Includes ------------------------------------------------------------------*/ + 62:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** #include + 63:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** #include "hw.h" + 64:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** #include "timeServer.h" + 65:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** //#include "low_power.h" + 66:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 67:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 68:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 69:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * safely execute call back + 70:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 71:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** #define exec_cb( _callback_ ) \ + 72:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** do { \ + 73:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( _callback_ == NULL ) \ + 74:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { \ + 75:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** while(1); \ + 76:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } \ + 77:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else \ + 78:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { \ + 79:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** _callback_( ); \ + 80:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } \ + 81:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } while(0); + 82:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 83:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 84:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 85:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 86:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * Timers list head pointer + 87:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 88:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static TimerEvent_t *TimerListHead = NULL; + 89:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 90:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 91:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \brief Adds or replace the head timer of the list. + ARM GAS /tmp/cciA02i6.s page 3 + + + 92:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 93:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \remark The list is automatically sorted. The list head always contains the + 94:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * next timer to expire. + 95:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 96:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] obj Timer object to be become the new head + 97:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] remainingTime Remaining time of the previous head to be replaced + 98:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 99:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerInsertNewHeadTimer( TimerEvent_t *obj ); + 100:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 101:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 102:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \brief Adds a timer to the list. + 103:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 104:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \remark The list is automatically sorted. The list head always contains the + 105:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * next timer to expire. + 106:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 107:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] obj Timer object to be added to the list + 108:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] remainingTime Remaining time of the running head after which the object may be adde + 109:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 110:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerInsertTimer( TimerEvent_t *obj ); + 111:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 112:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 113:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \brief Sets a timeout with the duration "timestamp" + 114:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 115:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] timestamp Delay duration + 116:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 117:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerSetTimeout( TimerEvent_t *obj ); + 118:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 119:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /*! + 120:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \brief Check if the Object to be added is not already in the list + 121:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * + 122:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \param [IN] timestamp Delay duration + 123:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** * \retval true (the object is already in the list) or false + 124:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** */ + 125:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static bool TimerExists( TimerEvent_t *obj ); + 126:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 127:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 128:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 129:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerInit( TimerEvent_t *obj, void ( *callback )( void ) ) + 130:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 131:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp = 0; + 132:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->ReloadValue = 0; + 133:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->IsRunning = false; + 134:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Callback = callback; + 135:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = NULL; + 136:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 137:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 138:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerStart( TimerEvent_t *obj ) + 139:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 140:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t elapsedTime = 0; + 141:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 142:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** BACKUP_PRIMASK(); + 143:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 144:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** DISABLE_IRQ( ); + 145:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 146:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 147:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( ( obj == NULL ) || ( TimerExists( obj ) == true ) ) + 148:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + ARM GAS /tmp/cciA02i6.s page 4 + + + 149:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** RESTORE_PRIMASK( ); + 150:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return; + 151:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 152:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp = obj->ReloadValue; + 153:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->IsRunning = false; + 154:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 155:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( TimerListHead == NULL ) + 156:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 157:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** HW_RTC_SetTimerContext( ); + 158:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerInsertNewHeadTimer( obj ); // insert a timeout at now+obj->Timestamp + 159:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 160:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 161:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 162:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** elapsedTime = HW_RTC_GetTimerElapsedTime( ); + 163:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp += elapsedTime; + 164:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 165:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( obj->Timestamp < TimerListHead->Timestamp ) + 166:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 167:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerInsertNewHeadTimer( obj); + 168:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 169:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 170:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 171:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerInsertTimer( obj); + 172:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 173:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 174:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** RESTORE_PRIMASK( ); + 175:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 176:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 177:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerInsertTimer( TimerEvent_t *obj) + 178:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 179:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur = TimerListHead; + 180:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* next = TimerListHead->Next; + 181:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 182:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** while (cur->Next != NULL ) + 183:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 184:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( obj->Timestamp > next->Timestamp ) + 185:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 186:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = next; + 187:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** next = next->Next; + 188:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 189:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 190:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 191:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur->Next = obj; + 192:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = next; + 193:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return; + 194:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 195:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 196:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 197:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur->Next = obj; + 198:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = NULL; + 199:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 200:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 201:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerInsertNewHeadTimer( TimerEvent_t *obj ) + 202:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 203:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur = TimerListHead; + 204:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 205:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( cur != NULL ) + ARM GAS /tmp/cciA02i6.s page 5 + + + 206:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 207:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur->IsRunning = false; + 208:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 209:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 210:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = cur; + 211:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = obj; + 212:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 213:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 214:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 215:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerIrqHandler( void ) + 216:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 217:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur; + 218:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* next; + 219:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 220:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 221:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 222:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t old = HW_RTC_GetTimerContext( ); + 223:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t now = HW_RTC_SetTimerContext( ); + 224:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t DeltaContext = now - old; //intentionnal wrap around + 225:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 226:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* update timeStamp based upon new Time Reference*/ + 227:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* beacuse delta context should never exceed 2^32*/ + 228:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if ( TimerListHead != NULL ) + 229:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 230:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** for (cur=TimerListHead; cur->Next != NULL; cur= cur->Next) + 231:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 232:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** next =cur->Next; + 233:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if (next->Timestamp > DeltaContext) + 234:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 235:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** next->Timestamp -= DeltaContext; + 236:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 237:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 238:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 239:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** next->Timestamp = 0 ; + 240:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 241:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 242:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 243:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 244:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* execute imediately the alarm callback */ + 245:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if ( TimerListHead != NULL ) + 246:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 247:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = TimerListHead; + 248:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 249:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** exec_cb( cur->Callback ); + 250:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 251:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 252:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 253:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** // remove all the expired object from the list + 254:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** while( ( TimerListHead != NULL ) && ( TimerListHead->Timestamp < HW_RTC_GetTimerElapsedTime( ) + 255:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 256:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = TimerListHead; + 257:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 258:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** exec_cb( cur->Callback ); + 259:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 260:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 261:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* start the next TimerListHead if it exists AND NOT running */ + 262:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if(( TimerListHead != NULL ) && (TimerListHead->IsRunning == false)) + ARM GAS /tmp/cciA02i6.s page 6 + + + 263:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 264:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 265:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 266:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 267:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 268:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerStop( TimerEvent_t *obj ) + 269:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 270:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** BACKUP_PRIMASK(); + 271:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 272:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** DISABLE_IRQ( ); + 273:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 274:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* prev = TimerListHead; + 275:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur = TimerListHead; + 276:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 277:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** // List is empty or the Obj to stop does not exist + 278:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( ( TimerListHead == NULL ) || ( obj == NULL ) ) + 279:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 280:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** RESTORE_PRIMASK( ); + 281:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return; + 282:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 283:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 284:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( TimerListHead == obj ) // Stop the Head + 285:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 286:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( TimerListHead->IsRunning == true ) // The head is already running + 287:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 288:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( TimerListHead->Next != NULL ) + 289:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 290:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead->IsRunning = false; + 291:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 292:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 293:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 294:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 295:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 296:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** HW_RTC_StopAlarm( ); + 297:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = NULL; + 298:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 299:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 300:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else // Stop the head before it is started + 301:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 302:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( TimerListHead->Next != NULL ) + 303:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 304:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 305:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 306:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 307:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 308:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = NULL; + 309:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 310:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 311:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 312:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else // Stop an object within the list + 313:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 314:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** while( cur != NULL ) + 315:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 316:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( cur == obj ) + 317:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 318:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( cur->Next != NULL ) + 319:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + ARM GAS /tmp/cciA02i6.s page 7 + + + 320:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = cur->Next; + 321:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** prev->Next = cur; + 322:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 323:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 324:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 325:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = NULL; + 326:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** prev->Next = cur; + 327:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 328:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** break; + 329:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 330:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** else + 331:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 332:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** prev = cur; + 333:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = cur->Next; + 334:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 335:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 336:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 337:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 338:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** RESTORE_PRIMASK( ); + 339:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 340:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 341:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static bool TimerExists( TimerEvent_t *obj ) + 342:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 343:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur = TimerListHead; + 344:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 345:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** while( cur != NULL ) + 346:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 347:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( cur == obj ) + 348:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 349:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return true; + 350:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 351:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = cur->Next; + 352:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 353:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return false; + 354:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 355:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 356:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerReset( TimerEvent_t *obj ) + 357:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 358:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerStop( obj ); + 359:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerStart( obj ); + 360:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 361:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 362:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** void TimerSetValue( TimerEvent_t *obj, uint32_t value ) + 363:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 364:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t minValue = 0; + 365:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t ticks = HW_RTC_ms2Tick( value ); + 366:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 367:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerStop( obj ); + 368:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 369:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** minValue = HW_RTC_GetMinimumTimeout( ); + 370:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 371:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if( ticks < minValue ) + 372:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 373:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** ticks = minValue; + 374:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 375:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 376:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp = ticks; + ARM GAS /tmp/cciA02i6.s page 8 + + + 377:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->ReloadValue = ticks; + 378:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 379:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 380:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerTime_t TimerGetCurrentTime( void ) + 381:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 382:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t now = HW_RTC_GetTimerValue( ); + 383:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return HW_RTC_Tick2ms(now); + 384:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 385:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 386:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerTime_t TimerGetElapsedTime( TimerTime_t past ) + 387:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 388:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t nowInTicks = HW_RTC_GetTimerValue( ); + 389:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t pastInTicks = HW_RTC_ms2Tick( past ); + 390:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* intentional wrap around. Works Ok if tick duation below 1ms */ + 391:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return HW_RTC_Tick2ms( nowInTicks- pastInTicks ); + 392:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 393:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 394:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** static void TimerSetTimeout( TimerEvent_t *obj ) + 395:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 25 .loc 1 395 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 70B5 push {r4, r5, r6, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 16 + 33 .cfi_offset 4, -16 + 34 .cfi_offset 5, -12 + 35 .cfi_offset 6, -8 + 36 .cfi_offset 14, -4 + 37 0002 0400 movs r4, r0 + 396:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** int32_t minTicks= HW_RTC_GetMinimumTimeout( ); + 38 .loc 1 396 0 + 39 0004 FFF7FEFF bl HW_RTC_GetMinimumTimeout + 40 .LVL1: + 41 0008 0500 movs r5, r0 + 42 .LVL2: + 397:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->IsRunning = true; + 43 .loc 1 397 0 + 44 000a 0123 movs r3, #1 + 45 000c 2372 strb r3, [r4, #8] + 398:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 399:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** //in case deadline too soon + 400:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** if(obj->Timestamp < (HW_RTC_GetTimerElapsedTime( ) + minTicks) ) + 46 .loc 1 400 0 + 47 000e 2668 ldr r6, [r4] + 48 0010 FFF7FEFF bl HW_RTC_GetTimerElapsedTime + 49 .LVL3: + 50 0014 2818 adds r0, r5, r0 + 51 0016 8642 cmp r6, r0 + 52 0018 03D3 bcc .L3 + 53 .LVL4: + 54 .L2: + 401:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 402:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp = HW_RTC_GetTimerElapsedTime( ) + minTicks; + 403:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + ARM GAS /tmp/cciA02i6.s page 9 + + + 404:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** HW_RTC_SetAlarm( obj->Timestamp ); + 55 .loc 1 404 0 + 56 001a 2068 ldr r0, [r4] + 57 001c FFF7FEFF bl HW_RTC_SetAlarm + 58 .LVL5: + 405:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 59 .loc 1 405 0 + 60 @ sp needed + 61 .LVL6: + 62 0020 70BD pop {r4, r5, r6, pc} + 63 .LVL7: + 64 .L3: + 402:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 65 .loc 1 402 0 + 66 0022 FFF7FEFF bl HW_RTC_GetTimerElapsedTime + 67 .LVL8: + 68 0026 2D18 adds r5, r5, r0 + 69 .LVL9: + 70 0028 2560 str r5, [r4] + 71 002a F6E7 b .L2 + 72 .cfi_endproc + 73 .LFE107: + 75 .section .text.TimerInit,"ax",%progbits + 76 .align 1 + 77 .global TimerInit + 78 .syntax unified + 79 .code 16 + 80 .thumb_func + 81 .fpu softvfp + 83 TimerInit: + 84 .LFB96: + 130:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp = 0; + 85 .loc 1 130 0 + 86 .cfi_startproc + 87 @ args = 0, pretend = 0, frame = 0 + 88 @ frame_needed = 0, uses_anonymous_args = 0 + 89 @ link register save eliminated. + 90 .LVL10: + 131:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->ReloadValue = 0; + 91 .loc 1 131 0 + 92 0000 0023 movs r3, #0 + 93 0002 0360 str r3, [r0] + 132:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->IsRunning = false; + 94 .loc 1 132 0 + 95 0004 4360 str r3, [r0, #4] + 133:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Callback = callback; + 96 .loc 1 133 0 + 97 0006 0372 strb r3, [r0, #8] + 134:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = NULL; + 98 .loc 1 134 0 + 99 0008 C160 str r1, [r0, #12] + 135:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 100 .loc 1 135 0 + 101 000a 0361 str r3, [r0, #16] + 136:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 102 .loc 1 136 0 + 103 @ sp needed + ARM GAS /tmp/cciA02i6.s page 10 + + + 104 000c 7047 bx lr + 105 .cfi_endproc + 106 .LFE96: + 108 .section .text.TimerStart,"ax",%progbits + 109 .align 1 + 110 .global TimerStart + 111 .syntax unified + 112 .code 16 + 113 .thumb_func + 114 .fpu softvfp + 116 TimerStart: + 117 .LFB97: + 139:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t elapsedTime = 0; + 118 .loc 1 139 0 + 119 .cfi_startproc + 120 @ args = 0, pretend = 0, frame = 0 + 121 @ frame_needed = 0, uses_anonymous_args = 0 + 122 .LVL11: + 123 0000 70B5 push {r4, r5, r6, lr} + 124 .LCFI1: + 125 .cfi_def_cfa_offset 16 + 126 .cfi_offset 4, -16 + 127 .cfi_offset 5, -12 + 128 .cfi_offset 6, -8 + 129 .cfi_offset 14, -4 + 130 0002 0400 movs r4, r0 + 131 .LVL12: + 132 .LBB34: + 133 .LBB35: + 134 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + ARM GAS /tmp/cciA02i6.s page 11 + + + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + ARM GAS /tmp/cciA02i6.s page 12 + + + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cciA02i6.s page 13 + + + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cciA02i6.s page 14 + + + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 135 .loc 2 203 0 + 136 .syntax divided + 137 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 138 0004 EFF31085 MRS r5, primask + 139 @ 0 "" 2 + 140 .thumb + 141 .syntax unified + 142 .LBE35: + 143 .LBE34: + 144 .LBB36: + 145 .LBB37: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 146 .loc 2 71 0 + 147 .syntax divided + 148 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 149 0008 72B6 cpsid i + 150 @ 0 "" 2 + 151 .thumb + 152 .syntax unified + 153 .LBE37: + 154 .LBE36: + 147:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 155 .loc 1 147 0 + 156 000a 0028 cmp r0, #0 + 157 000c 29D0 beq .L6 + 158 .LVL13: + 159 .LBB38: + 160 .LBB39: + 343:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 161 .loc 1 343 0 + 162 000e 264B ldr r3, .L23 + 163 0010 1A68 ldr r2, [r3] + 164 .LVL14: + 165 0012 1300 movs r3, r2 + 166 .LVL15: + 167 .L7: + 345:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 168 .loc 1 345 0 + 169 0014 002B cmp r3, #0 + 170 0016 04D0 beq .L8 + 347:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 171 .loc 1 347 0 + 172 0018 9C42 cmp r4, r3 + 173 001a 01D0 beq .L20 + 351:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 174 .loc 1 351 0 + 175 001c 1B69 ldr r3, [r3, #16] + 176 .LVL16: + 177 001e F9E7 b .L7 + 178 .L20: + 349:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 179 .loc 1 349 0 + ARM GAS /tmp/cciA02i6.s page 15 + + + 180 0020 0123 movs r3, #1 + 181 .LVL17: + 182 .L8: + 183 .LBE39: + 184 .LBE38: + 147:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 185 .loc 1 147 0 + 186 0022 002B cmp r3, #0 + 187 0024 1DD1 bne .L6 + 152:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->IsRunning = false; + 188 .loc 1 152 0 + 189 0026 6368 ldr r3, [r4, #4] + 190 0028 2360 str r3, [r4] + 153:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 191 .loc 1 153 0 + 192 002a 0023 movs r3, #0 + 193 002c 2372 strb r3, [r4, #8] + 155:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 194 .loc 1 155 0 + 195 002e 002A cmp r2, #0 + 196 0030 1AD0 beq .L21 + 162:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Timestamp += elapsedTime; + 197 .loc 1 162 0 + 198 0032 FFF7FEFF bl HW_RTC_GetTimerElapsedTime + 199 .LVL18: + 163:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 200 .loc 1 163 0 + 201 0036 2368 ldr r3, [r4] + 202 0038 9C46 mov ip, r3 + 203 003a 6044 add r0, r0, ip + 204 .LVL19: + 205 003c 2060 str r0, [r4] + 165:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 206 .loc 1 165 0 + 207 003e 1A4B ldr r3, .L23 + 208 0040 1A68 ldr r2, [r3] + 209 0042 1368 ldr r3, [r2] + 210 0044 9842 cmp r0, r3 + 211 0046 1ED2 bcs .L15 + 212 .LVL20: + 213 .LBB40: + 214 .LBB41: + 205:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 215 .loc 1 205 0 + 216 0048 002A cmp r2, #0 + 217 004a 01D0 beq .L16 + 207:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 218 .loc 1 207 0 + 219 004c 0023 movs r3, #0 + 220 004e 1372 strb r3, [r2, #8] + 221 .L16: + 210:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = obj; + 222 .loc 1 210 0 + 223 0050 2261 str r2, [r4, #16] + 211:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 224 .loc 1 211 0 + 225 0052 154B ldr r3, .L23 + ARM GAS /tmp/cciA02i6.s page 16 + + + 226 0054 1C60 str r4, [r3] + 212:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 227 .loc 1 212 0 + 228 0056 2000 movs r0, r4 + 229 0058 FFF7FEFF bl TimerSetTimeout + 230 .LVL21: + 231 .L14: + 232 .LBE41: + 233 .LBE40: + 234 .LBB42: + 235 .LBB43: + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 236 .loc 2 215 0 + 237 .syntax divided + 238 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 239 005c 85F31088 MSR primask, r5 + 240 @ 0 "" 2 + 241 .thumb + 242 .syntax unified + 243 0060 01E0 b .L5 + 244 .LVL22: + 245 .L6: + 246 .LBE43: + 247 .LBE42: + 248 .LBB44: + 249 .LBB45: + 250 .syntax divided + 251 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 252 0062 85F31088 MSR primask, r5 + 253 @ 0 "" 2 + 254 .LVL23: + 255 .thumb + 256 .syntax unified + 257 .L5: + 258 .LBE45: + 259 .LBE44: + 175:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 260 .loc 1 175 0 + 261 @ sp needed + 262 .LVL24: + 263 0066 70BD pop {r4, r5, r6, pc} + 264 .LVL25: + 265 .L21: + 157:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerInsertNewHeadTimer( obj ); // insert a timeout at now+obj->Timestamp + 266 .loc 1 157 0 + 267 0068 FFF7FEFF bl HW_RTC_SetTimerContext + ARM GAS /tmp/cciA02i6.s page 17 + + + 268 .LVL26: + 269 .LBB46: + 270 .LBB47: + 203:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 271 .loc 1 203 0 + 272 006c 0E4B ldr r3, .L23 + 273 006e 1B68 ldr r3, [r3] + 274 .LVL27: + 205:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 275 .loc 1 205 0 + 276 0070 002B cmp r3, #0 + 277 0072 01D0 beq .L13 + 207:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 278 .loc 1 207 0 + 279 0074 0022 movs r2, #0 + 280 0076 1A72 strb r2, [r3, #8] + 281 .L13: + 210:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = obj; + 282 .loc 1 210 0 + 283 0078 2361 str r3, [r4, #16] + 211:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 284 .loc 1 211 0 + 285 007a 0B4B ldr r3, .L23 + 286 .LVL28: + 287 007c 1C60 str r4, [r3] + 288 .LVL29: + 212:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 289 .loc 1 212 0 + 290 007e 2000 movs r0, r4 + 291 0080 FFF7FEFF bl TimerSetTimeout + 292 .LVL30: + 293 0084 EAE7 b .L14 + 294 .LVL31: + 295 .L15: + 296 .LBE47: + 297 .LBE46: + 298 .LBB48: + 299 .LBB49: + 180:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 300 .loc 1 180 0 + 301 0086 1369 ldr r3, [r2, #16] + 302 .LVL32: + 303 .L17: + 182:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 304 .loc 1 182 0 + 305 0088 1169 ldr r1, [r2, #16] + 306 008a 0029 cmp r1, #0 + 307 008c 08D0 beq .L22 + 184:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 308 .loc 1 184 0 + 309 008e 1968 ldr r1, [r3] + 310 0090 8842 cmp r0, r1 + 311 0092 02D9 bls .L18 + 312 .LVL33: + 186:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** next = next->Next; + 313 .loc 1 186 0 + 314 0094 1A00 movs r2, r3 + ARM GAS /tmp/cciA02i6.s page 18 + + + 187:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 315 .loc 1 187 0 + 316 0096 1B69 ldr r3, [r3, #16] + 317 .LVL34: + 318 0098 F6E7 b .L17 + 319 .L18: + 191:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = next; + 320 .loc 1 191 0 + 321 009a 1461 str r4, [r2, #16] + 192:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return; + 322 .loc 1 192 0 + 323 009c 2361 str r3, [r4, #16] + 324 009e DDE7 b .L14 + 325 .L22: + 197:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->Next = NULL; + 326 .loc 1 197 0 + 327 00a0 1461 str r4, [r2, #16] + 198:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 328 .loc 1 198 0 + 329 00a2 0023 movs r3, #0 + 330 .LVL35: + 331 00a4 2361 str r3, [r4, #16] + 332 00a6 D9E7 b .L14 + 333 .L24: + 334 .align 2 + 335 .L23: + 336 00a8 00000000 .word .LANCHOR0 + 337 .LBE49: + 338 .LBE48: + 339 .cfi_endproc + 340 .LFE97: + 342 .section .text.TimerIrqHandler,"ax",%progbits + 343 .align 1 + 344 .global TimerIrqHandler + 345 .syntax unified + 346 .code 16 + 347 .thumb_func + 348 .fpu softvfp + 350 TimerIrqHandler: + 351 .LFB100: + 216:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur; + 352 .loc 1 216 0 + 353 .cfi_startproc + 354 @ args = 0, pretend = 0, frame = 0 + 355 @ frame_needed = 0, uses_anonymous_args = 0 + 356 0000 10B5 push {r4, lr} + 357 .LCFI2: + 358 .cfi_def_cfa_offset 8 + 359 .cfi_offset 4, -8 + 360 .cfi_offset 14, -4 + 222:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t now = HW_RTC_SetTimerContext( ); + 361 .loc 1 222 0 + 362 0002 FFF7FEFF bl HW_RTC_GetTimerContext + 363 .LVL36: + 364 0006 0400 movs r4, r0 + 365 .LVL37: + 223:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t DeltaContext = now - old; //intentionnal wrap around + ARM GAS /tmp/cciA02i6.s page 19 + + + 366 .loc 1 223 0 + 367 0008 FFF7FEFF bl HW_RTC_SetTimerContext + 368 .LVL38: + 224:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 369 .loc 1 224 0 + 370 000c 001B subs r0, r0, r4 + 371 .LVL39: + 228:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 372 .loc 1 228 0 + 373 000e 1C4B ldr r3, .L41 + 374 0010 1B68 ldr r3, [r3] + 375 0012 002B cmp r3, #0 + 376 0014 0DD0 beq .L27 + 230:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 377 .loc 1 230 0 + 378 0016 1C00 movs r4, r3 + 379 .LVL40: + 380 0018 02E0 b .L26 + 381 .LVL41: + 382 .L28: + 239:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 383 .loc 1 239 0 + 384 001a 0021 movs r1, #0 + 385 001c 1160 str r1, [r2] + 386 .L29: + 230:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 387 .loc 1 230 0 discriminator 2 + 388 001e 2469 ldr r4, [r4, #16] + 389 .LVL42: + 390 .L26: + 230:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 391 .loc 1 230 0 is_stmt 0 discriminator 1 + 392 0020 2269 ldr r2, [r4, #16] + 393 0022 002A cmp r2, #0 + 394 0024 05D0 beq .L27 + 395 .LVL43: + 233:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 396 .loc 1 233 0 is_stmt 1 + 397 0026 1168 ldr r1, [r2] + 398 0028 8142 cmp r1, r0 + 399 002a F6D9 bls .L28 + 235:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 400 .loc 1 235 0 + 401 002c 091A subs r1, r1, r0 + 402 002e 1160 str r1, [r2] + 403 0030 F5E7 b .L29 + 404 .LVL44: + 405 .L27: + 245:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 406 .loc 1 245 0 + 407 0032 002B cmp r3, #0 + 408 0034 06D0 beq .L36 + 409 .LVL45: + 248:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** exec_cb( cur->Callback ); + 410 .loc 1 248 0 + 411 0036 124A ldr r2, .L41 + 412 0038 1969 ldr r1, [r3, #16] + ARM GAS /tmp/cciA02i6.s page 20 + + + 413 003a 1160 str r1, [r2] + 249:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 414 .loc 1 249 0 + 415 003c DB68 ldr r3, [r3, #12] + 416 .LVL46: + 417 003e 002B cmp r3, #0 + 418 0040 12D0 beq .L33 + 249:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 419 .loc 1 249 0 is_stmt 0 discriminator 1 + 420 0042 9847 blx r3 + 421 .LVL47: + 422 .L36: + 254:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 423 .loc 1 254 0 is_stmt 1 + 424 0044 0E4B ldr r3, .L41 + 425 0046 1B68 ldr r3, [r3] + 426 0048 002B cmp r3, #0 + 427 004a 0FD0 beq .L37 + 254:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 428 .loc 1 254 0 is_stmt 0 discriminator 1 + 429 004c 1C68 ldr r4, [r3] + 430 004e FFF7FEFF bl HW_RTC_GetTimerElapsedTime + 431 .LVL48: + 432 0052 8442 cmp r4, r0 + 433 0054 0AD2 bcs .L37 + 256:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 434 .loc 1 256 0 is_stmt 1 + 435 0056 0A4A ldr r2, .L41 + 436 0058 1368 ldr r3, [r2] + 437 .LVL49: + 257:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** exec_cb( cur->Callback ); + 438 .loc 1 257 0 + 439 005a 1969 ldr r1, [r3, #16] + 440 005c 1160 str r1, [r2] + 258:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 441 .loc 1 258 0 + 442 005e DB68 ldr r3, [r3, #12] + 443 .LVL50: + 444 0060 002B cmp r3, #0 + 445 0062 02D0 beq .L35 + 258:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 446 .loc 1 258 0 is_stmt 0 discriminator 1 + 447 0064 9847 blx r3 + 448 .LVL51: + 449 0066 EDE7 b .L36 + 450 .LVL52: + 451 .L33: + 452 0068 FEE7 b .L33 + 453 .LVL53: + 454 .L35: + 455 006a FEE7 b .L35 + 456 .L37: + 262:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 457 .loc 1 262 0 is_stmt 1 + 458 006c 044B ldr r3, .L41 + 459 006e 1868 ldr r0, [r3] + 460 0070 0028 cmp r0, #0 + ARM GAS /tmp/cciA02i6.s page 21 + + + 461 0072 04D0 beq .L25 + 262:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 462 .loc 1 262 0 is_stmt 0 discriminator 1 + 463 0074 037A ldrb r3, [r0, #8] + 464 0076 002B cmp r3, #0 + 465 0078 01D1 bne .L25 + 264:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 466 .loc 1 264 0 is_stmt 1 + 467 007a FFF7FEFF bl TimerSetTimeout + 468 .LVL54: + 469 .L25: + 266:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 470 .loc 1 266 0 + 471 @ sp needed + 472 007e 10BD pop {r4, pc} + 473 .L42: + 474 .align 2 + 475 .L41: + 476 0080 00000000 .word .LANCHOR0 + 477 .cfi_endproc + 478 .LFE100: + 480 .section .text.TimerStop,"ax",%progbits + 481 .align 1 + 482 .global TimerStop + 483 .syntax unified + 484 .code 16 + 485 .thumb_func + 486 .fpu softvfp + 488 TimerStop: + 489 .LFB101: + 269:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** BACKUP_PRIMASK(); + 490 .loc 1 269 0 + 491 .cfi_startproc + 492 @ args = 0, pretend = 0, frame = 0 + 493 @ frame_needed = 0, uses_anonymous_args = 0 + 494 .LVL55: + 495 0000 10B5 push {r4, lr} + 496 .LCFI3: + 497 .cfi_def_cfa_offset 8 + 498 .cfi_offset 4, -8 + 499 .cfi_offset 14, -4 + 500 .LBB50: + 501 .LBB51: + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 502 .loc 2 203 0 + 503 .syntax divided + 504 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 505 0002 EFF31084 MRS r4, primask + 506 @ 0 "" 2 + 507 .thumb + 508 .syntax unified + 509 .LBE51: + 510 .LBE50: + 511 .LBB52: + 512 .LBB53: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 513 .loc 2 71 0 + ARM GAS /tmp/cciA02i6.s page 22 + + + 514 .syntax divided + 515 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 516 0006 72B6 cpsid i + 517 @ 0 "" 2 + 518 .thumb + 519 .syntax unified + 520 .LBE53: + 521 .LBE52: + 274:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerEvent_t* cur = TimerListHead; + 522 .loc 1 274 0 + 523 0008 1C4B ldr r3, .L58 + 524 000a 1A68 ldr r2, [r3] + 525 .LVL56: + 278:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 526 .loc 1 278 0 + 527 000c 002A cmp r2, #0 + 528 000e 0BD0 beq .L44 + 278:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 529 .loc 1 278 0 is_stmt 0 discriminator 1 + 530 0010 0028 cmp r0, #0 + 531 0012 09D0 beq .L44 + 284:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 532 .loc 1 284 0 is_stmt 1 + 533 0014 8242 cmp r2, r0 + 534 0016 0AD0 beq .L56 + 275:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 535 .loc 1 275 0 + 536 0018 1300 movs r3, r2 + 537 .LVL57: + 538 .L47: + 314:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 539 .loc 1 314 0 + 540 001a 002B cmp r3, #0 + 541 001c 28D0 beq .L50 + 316:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 542 .loc 1 316 0 + 543 001e 8342 cmp r3, r0 + 544 0020 22D0 beq .L57 + 545 .LVL58: + 332:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** cur = cur->Next; + 546 .loc 1 332 0 + 547 0022 1A00 movs r2, r3 + 333:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 548 .loc 1 333 0 + 549 0024 1B69 ldr r3, [r3, #16] + 550 .LVL59: + 551 0026 F8E7 b .L47 + 552 .LVL60: + 553 .L44: + 554 .LBB54: + 555 .LBB55: + 556 .loc 2 215 0 + 557 .syntax divided + 558 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 559 0028 84F31088 MSR primask, r4 + 560 @ 0 "" 2 + 561 .thumb + ARM GAS /tmp/cciA02i6.s page 23 + + + 562 .syntax unified + 563 002c 22E0 b .L43 + 564 .LVL61: + 565 .L56: + 566 .LBE55: + 567 .LBE54: + 286:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 568 .loc 1 286 0 + 569 002e 137A ldrb r3, [r2, #8] + 570 0030 002B cmp r3, #0 + 571 0032 0FD0 beq .L48 + 288:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 572 .loc 1 288 0 + 573 0034 1069 ldr r0, [r2, #16] + 574 .LVL62: + 575 0036 0028 cmp r0, #0 + 576 0038 06D0 beq .L49 + 290:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = TimerListHead->Next; + 577 .loc 1 290 0 + 578 003a 0023 movs r3, #0 + 579 003c 1372 strb r3, [r2, #8] + 291:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerSetTimeout( TimerListHead ); + 580 .loc 1 291 0 + 581 003e 0F4B ldr r3, .L58 + 582 0040 1860 str r0, [r3] + 292:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 583 .loc 1 292 0 + 584 0042 FFF7FEFF bl TimerSetTimeout + 585 .LVL63: + 586 0046 13E0 b .L50 + 587 .LVL64: + 588 .L49: + 296:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerListHead = NULL; + 589 .loc 1 296 0 + 590 0048 FFF7FEFF bl HW_RTC_StopAlarm + 591 .LVL65: + 297:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 592 .loc 1 297 0 + 593 004c 0B4B ldr r3, .L58 + 594 004e 0022 movs r2, #0 + 595 0050 1A60 str r2, [r3] + 596 0052 0DE0 b .L50 + 597 .LVL66: + 598 .L48: + 302:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 599 .loc 1 302 0 + 600 0054 1369 ldr r3, [r2, #16] + 601 0056 002B cmp r3, #0 + 602 0058 02D0 beq .L51 + 304:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 603 .loc 1 304 0 + 604 005a 084A ldr r2, .L58 + 605 .LVL67: + 606 005c 1360 str r3, [r2] + 607 .LVL68: + 608 005e 07E0 b .L50 + 609 .LVL69: + ARM GAS /tmp/cciA02i6.s page 24 + + + 610 .L51: + 308:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 611 .loc 1 308 0 + 612 0060 064B ldr r3, .L58 + 613 0062 0022 movs r2, #0 + 614 .LVL70: + 615 0064 1A60 str r2, [r3] + 616 .LVL71: + 617 0066 03E0 b .L50 + 618 .LVL72: + 619 .L57: + 318:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 620 .loc 1 318 0 + 621 0068 1B69 ldr r3, [r3, #16] + 622 .LVL73: + 623 006a 002B cmp r3, #0 + 624 006c 03D0 beq .L53 + 625 .LVL74: + 321:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 626 .loc 1 321 0 + 627 006e 1361 str r3, [r2, #16] + 628 .LVL75: + 629 .L50: + 630 .LBB56: + 631 .LBB57: + 632 .loc 2 215 0 + 633 .syntax divided + 634 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 635 0070 84F31088 MSR primask, r4 + 636 @ 0 "" 2 + 637 .LVL76: + 638 .thumb + 639 .syntax unified + 640 .L43: + 641 .LBE57: + 642 .LBE56: + 339:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 643 .loc 1 339 0 + 644 @ sp needed + 645 0074 10BD pop {r4, pc} + 646 .LVL77: + 647 .L53: + 326:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 648 .loc 1 326 0 + 649 0076 0023 movs r3, #0 + 650 0078 1361 str r3, [r2, #16] + 651 007a F9E7 b .L50 + 652 .L59: + 653 .align 2 + 654 .L58: + 655 007c 00000000 .word .LANCHOR0 + 656 .cfi_endproc + 657 .LFE101: + 659 .section .text.TimerReset,"ax",%progbits + 660 .align 1 + 661 .global TimerReset + 662 .syntax unified + ARM GAS /tmp/cciA02i6.s page 25 + + + 663 .code 16 + 664 .thumb_func + 665 .fpu softvfp + 667 TimerReset: + 668 .LFB103: + 357:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerStop( obj ); + 669 .loc 1 357 0 + 670 .cfi_startproc + 671 @ args = 0, pretend = 0, frame = 0 + 672 @ frame_needed = 0, uses_anonymous_args = 0 + 673 .LVL78: + 674 0000 10B5 push {r4, lr} + 675 .LCFI4: + 676 .cfi_def_cfa_offset 8 + 677 .cfi_offset 4, -8 + 678 .cfi_offset 14, -4 + 679 0002 0400 movs r4, r0 + 358:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** TimerStart( obj ); + 680 .loc 1 358 0 + 681 0004 FFF7FEFF bl TimerStop + 682 .LVL79: + 359:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 683 .loc 1 359 0 + 684 0008 2000 movs r0, r4 + 685 000a FFF7FEFF bl TimerStart + 686 .LVL80: + 360:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 687 .loc 1 360 0 + 688 @ sp needed + 689 .LVL81: + 690 000e 10BD pop {r4, pc} + 691 .cfi_endproc + 692 .LFE103: + 694 .section .text.TimerSetValue,"ax",%progbits + 695 .align 1 + 696 .global TimerSetValue + 697 .syntax unified + 698 .code 16 + 699 .thumb_func + 700 .fpu softvfp + 702 TimerSetValue: + 703 .LFB104: + 363:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t minValue = 0; + 704 .loc 1 363 0 + 705 .cfi_startproc + 706 @ args = 0, pretend = 0, frame = 0 + 707 @ frame_needed = 0, uses_anonymous_args = 0 + 708 .LVL82: + 709 0000 70B5 push {r4, r5, r6, lr} + 710 .LCFI5: + 711 .cfi_def_cfa_offset 16 + 712 .cfi_offset 4, -16 + 713 .cfi_offset 5, -12 + 714 .cfi_offset 6, -8 + 715 .cfi_offset 14, -4 + 716 0002 0400 movs r4, r0 + 717 .LVL83: + ARM GAS /tmp/cciA02i6.s page 26 + + + 365:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 718 .loc 1 365 0 + 719 0004 0800 movs r0, r1 + 720 .LVL84: + 721 0006 FFF7FEFF bl HW_RTC_ms2Tick + 722 .LVL85: + 723 000a 0500 movs r5, r0 + 724 .LVL86: + 367:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 725 .loc 1 367 0 + 726 000c 2000 movs r0, r4 + 727 .LVL87: + 728 000e FFF7FEFF bl TimerStop + 729 .LVL88: + 369:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 730 .loc 1 369 0 + 731 0012 FFF7FEFF bl HW_RTC_GetMinimumTimeout + 732 .LVL89: + 371:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** { + 733 .loc 1 371 0 + 734 0016 8542 cmp r5, r0 + 735 0018 02D2 bcs .L63 + 736 .LVL90: + 737 .L62: + 376:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** obj->ReloadValue = ticks; + 738 .loc 1 376 0 + 739 001a 2060 str r0, [r4] + 377:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 740 .loc 1 377 0 + 741 001c 6060 str r0, [r4, #4] + 378:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 742 .loc 1 378 0 + 743 @ sp needed + 744 .LVL91: + 745 001e 70BD pop {r4, r5, r6, pc} + 746 .LVL92: + 747 .L63: + 365:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 748 .loc 1 365 0 + 749 0020 2800 movs r0, r5 + 750 .LVL93: + 751 0022 FAE7 b .L62 + 752 .cfi_endproc + 753 .LFE104: + 755 .section .text.TimerGetCurrentTime,"ax",%progbits + 756 .align 1 + 757 .global TimerGetCurrentTime + 758 .syntax unified + 759 .code 16 + 760 .thumb_func + 761 .fpu softvfp + 763 TimerGetCurrentTime: + 764 .LFB105: + 381:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t now = HW_RTC_GetTimerValue( ); + 765 .loc 1 381 0 + 766 .cfi_startproc + 767 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cciA02i6.s page 27 + + + 768 @ frame_needed = 0, uses_anonymous_args = 0 + 769 0000 10B5 push {r4, lr} + 770 .LCFI6: + 771 .cfi_def_cfa_offset 8 + 772 .cfi_offset 4, -8 + 773 .cfi_offset 14, -4 + 382:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** return HW_RTC_Tick2ms(now); + 774 .loc 1 382 0 + 775 0002 FFF7FEFF bl HW_RTC_GetTimerValue + 776 .LVL94: + 383:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 777 .loc 1 383 0 + 778 0006 FFF7FEFF bl HW_RTC_Tick2ms + 779 .LVL95: + 384:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 780 .loc 1 384 0 + 781 @ sp needed + 782 000a 10BD pop {r4, pc} + 783 .cfi_endproc + 784 .LFE105: + 786 .section .text.TimerGetElapsedTime,"ax",%progbits + 787 .align 1 + 788 .global TimerGetElapsedTime + 789 .syntax unified + 790 .code 16 + 791 .thumb_func + 792 .fpu softvfp + 794 TimerGetElapsedTime: + 795 .LFB106: + 387:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t nowInTicks = HW_RTC_GetTimerValue( ); + 796 .loc 1 387 0 + 797 .cfi_startproc + 798 @ args = 0, pretend = 0, frame = 0 + 799 @ frame_needed = 0, uses_anonymous_args = 0 + 800 .LVL96: + 801 0000 70B5 push {r4, r5, r6, lr} + 802 .LCFI7: + 803 .cfi_def_cfa_offset 16 + 804 .cfi_offset 4, -16 + 805 .cfi_offset 5, -12 + 806 .cfi_offset 6, -8 + 807 .cfi_offset 14, -4 + 808 0002 0500 movs r5, r0 + 388:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** uint32_t pastInTicks = HW_RTC_ms2Tick( past ); + 809 .loc 1 388 0 + 810 0004 FFF7FEFF bl HW_RTC_GetTimerValue + 811 .LVL97: + 812 0008 0400 movs r4, r0 + 813 .LVL98: + 389:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** /* intentional wrap around. Works Ok if tick duation below 1ms */ + 814 .loc 1 389 0 + 815 000a 2800 movs r0, r5 + 816 .LVL99: + 817 000c FFF7FEFF bl HW_RTC_ms2Tick + 818 .LVL100: + 391:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** } + 819 .loc 1 391 0 + ARM GAS /tmp/cciA02i6.s page 28 + + + 820 0010 201A subs r0, r4, r0 + 821 .LVL101: + 822 0012 FFF7FEFF bl HW_RTC_Tick2ms + 823 .LVL102: + 392:./Middlewares/Third_Party/Lora/Utilities/timeServer.c **** + 824 .loc 1 392 0 + 825 @ sp needed + 826 .LVL103: + 827 .LVL104: + 828 0016 70BD pop {r4, r5, r6, pc} + 829 .cfi_endproc + 830 .LFE106: + 832 .section .bss.TimerListHead,"aw",%nobits + 833 .align 2 + 834 .set .LANCHOR0,. + 0 + 837 TimerListHead: + 838 0000 00000000 .space 4 + 839 .text + 840 .Letext0: + 841 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 842 .file 4 "/usr/arm-none-eabi/include/sys/lock.h" + 843 .file 5 "/usr/arm-none-eabi/include/sys/_types.h" + 844 .file 6 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 845 .file 7 "/usr/arm-none-eabi/include/sys/reent.h" + 846 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 847 .file 9 "/usr/arm-none-eabi/include/time.h" + 848 .file 10 "/usr/arm-none-eabi/include/math.h" + 849 .file 11 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 850 .file 12 "Middlewares/Third_Party/Lora/Utilities/utilities.h" + 851 .file 13 "./Middlewares/Third_Party/Lora/Utilities/timeServer.h" + 852 .file 14 "Inc/hw_rtc.h" + ARM GAS /tmp/cciA02i6.s page 29 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 timeServer.c + /tmp/cciA02i6.s:16 .text.TimerSetTimeout:0000000000000000 $t + /tmp/cciA02i6.s:22 .text.TimerSetTimeout:0000000000000000 TimerSetTimeout + /tmp/cciA02i6.s:76 .text.TimerInit:0000000000000000 $t + /tmp/cciA02i6.s:83 .text.TimerInit:0000000000000000 TimerInit + /tmp/cciA02i6.s:109 .text.TimerStart:0000000000000000 $t + /tmp/cciA02i6.s:116 .text.TimerStart:0000000000000000 TimerStart + /tmp/cciA02i6.s:336 .text.TimerStart:00000000000000a8 $d + /tmp/cciA02i6.s:343 .text.TimerIrqHandler:0000000000000000 $t + /tmp/cciA02i6.s:350 .text.TimerIrqHandler:0000000000000000 TimerIrqHandler + /tmp/cciA02i6.s:476 .text.TimerIrqHandler:0000000000000080 $d + /tmp/cciA02i6.s:481 .text.TimerStop:0000000000000000 $t + /tmp/cciA02i6.s:488 .text.TimerStop:0000000000000000 TimerStop + /tmp/cciA02i6.s:655 .text.TimerStop:000000000000007c $d + /tmp/cciA02i6.s:660 .text.TimerReset:0000000000000000 $t + /tmp/cciA02i6.s:667 .text.TimerReset:0000000000000000 TimerReset + /tmp/cciA02i6.s:695 .text.TimerSetValue:0000000000000000 $t + /tmp/cciA02i6.s:702 .text.TimerSetValue:0000000000000000 TimerSetValue + /tmp/cciA02i6.s:756 .text.TimerGetCurrentTime:0000000000000000 $t + /tmp/cciA02i6.s:763 .text.TimerGetCurrentTime:0000000000000000 TimerGetCurrentTime + /tmp/cciA02i6.s:787 .text.TimerGetElapsedTime:0000000000000000 $t + /tmp/cciA02i6.s:794 .text.TimerGetElapsedTime:0000000000000000 TimerGetElapsedTime + /tmp/cciA02i6.s:833 .bss.TimerListHead:0000000000000000 $d + /tmp/cciA02i6.s:837 .bss.TimerListHead:0000000000000000 TimerListHead + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HW_RTC_GetMinimumTimeout +HW_RTC_GetTimerElapsedTime +HW_RTC_SetAlarm +HW_RTC_SetTimerContext +HW_RTC_GetTimerContext +HW_RTC_StopAlarm +HW_RTC_ms2Tick +HW_RTC_GetTimerValue +HW_RTC_Tick2ms diff --git a/build/utilities.d b/build/utilities.d new file mode 100644 index 0000000..7725940 --- /dev/null +++ b/build/utilities.d @@ -0,0 +1,19 @@ +build/utilities.d: Middlewares/Third_Party/Lora/Utilities/utilities.c \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: diff --git a/build/utilities.lst b/build/utilities.lst new file mode 100644 index 0000000..ba21a54 --- /dev/null +++ b/build/utilities.lst @@ -0,0 +1,479 @@ +ARM GAS /tmp/cco3Pbva.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "utilities.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .global __aeabi_uidivmod + 16 .section .text.rand1,"ax",%progbits + 17 .align 1 + 18 .global rand1 + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 rand1: + 25 .LFB85: + 26 .file 1 "./Middlewares/Third_Party/Lora/Utilities/utilities.c" + 1:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** /* + 2:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** / _____) _ | | + 3:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** ( (____ _____ ____ _| |_ _____ ____| |__ + 4:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** \____ \| ___ | (_ _) ___ |/ ___) _ \ + 5:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** _____) ) ____| | | || |_| ____( (___| | | | + 6:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** (______/|_____)_|_|_| \__)_____)\____)_| |_| + 7:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** (C)2013 Semtech + 8:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 9:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** Description: Helper functions implementation + 10:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 11:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** License: Revised BSD License, see LICENSE.TXT file include in the project + 12:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 13:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** Maintainer: Miguel Luis and Gregory Cristian + 14:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** */ + 15:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** #include + 16:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** #include + 17:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** #include + 18:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** #include "utilities.h" + 19:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 20:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** /*! + 21:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** * Redefinition of rand() and srand() standard C functions. + 22:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** * These functions are redefined in order to get the same behavior across + 23:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** * different compiler toolchains implementations. + 24:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** */ + 25:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** // Standard random functions redefinition start + 26:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** #define RAND_LOCAL_MAX 2147483647L + 27:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 28:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** static uint32_t next = 1; + 29:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 30:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** int32_t rand1( void ) + 31:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 27 .loc 1 31 0 + ARM GAS /tmp/cco3Pbva.s page 2 + + + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 0000 10B5 push {r4, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 4, -8 + 35 .cfi_offset 14, -4 + 32:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** return ( ( next = next * 1103515245L + 12345L ) % RAND_LOCAL_MAX ); + 36 .loc 1 32 0 + 37 0002 064B ldr r3, .L2 + 38 0004 0648 ldr r0, .L2+4 + 39 0006 1A68 ldr r2, [r3] + 40 0008 5043 muls r0, r2 + 41 000a 064A ldr r2, .L2+8 + 42 000c 9446 mov ip, r2 + 43 000e 6044 add r0, r0, ip + 44 0010 1860 str r0, [r3] + 45 0012 0549 ldr r1, .L2+12 + 46 0014 FFF7FEFF bl __aeabi_uidivmod + 47 .LVL0: + 33:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 48 .loc 1 33 0 + 49 0018 0800 movs r0, r1 + 50 @ sp needed + 51 001a 10BD pop {r4, pc} + 52 .L3: + 53 .align 2 + 54 .L2: + 55 001c 00000000 .word .LANCHOR0 + 56 0020 6D4EC641 .word 1103515245 + 57 0024 39300000 .word 12345 + 58 0028 FFFFFF7F .word 2147483647 + 59 .cfi_endproc + 60 .LFE85: + 62 .section .text.srand1,"ax",%progbits + 63 .align 1 + 64 .global srand1 + 65 .syntax unified + 66 .code 16 + 67 .thumb_func + 68 .fpu softvfp + 70 srand1: + 71 .LFB86: + 34:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 35:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** void srand1( uint32_t seed ) + 36:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 72 .loc 1 36 0 + 73 .cfi_startproc + 74 @ args = 0, pretend = 0, frame = 0 + 75 @ frame_needed = 0, uses_anonymous_args = 0 + 76 @ link register save eliminated. + 77 .LVL1: + 37:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** next = seed; + 78 .loc 1 37 0 + 79 0000 014B ldr r3, .L5 + 80 0002 1860 str r0, [r3] + ARM GAS /tmp/cco3Pbva.s page 3 + + + 38:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 81 .loc 1 38 0 + 82 @ sp needed + 83 0004 7047 bx lr + 84 .L6: + 85 0006 C046 .align 2 + 86 .L5: + 87 0008 00000000 .word .LANCHOR0 + 88 .cfi_endproc + 89 .LFE86: + 91 .global __aeabi_idivmod + 92 .section .text.randr,"ax",%progbits + 93 .align 1 + 94 .global randr + 95 .syntax unified + 96 .code 16 + 97 .thumb_func + 98 .fpu softvfp + 100 randr: + 101 .LFB87: + 39:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** // Standard random functions redefinition end + 40:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 41:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** int32_t randr( int32_t min, int32_t max ) + 42:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 102 .loc 1 42 0 + 103 .cfi_startproc + 104 @ args = 0, pretend = 0, frame = 0 + 105 @ frame_needed = 0, uses_anonymous_args = 0 + 106 .LVL2: + 107 0000 70B5 push {r4, r5, r6, lr} + 108 .LCFI1: + 109 .cfi_def_cfa_offset 16 + 110 .cfi_offset 4, -16 + 111 .cfi_offset 5, -12 + 112 .cfi_offset 6, -8 + 113 .cfi_offset 14, -4 + 114 0002 0500 movs r5, r0 + 115 0004 0C00 movs r4, r1 + 116 .LBB4: + 117 .LBB5: + 32:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 118 .loc 1 32 0 + 119 0006 094B ldr r3, .L8 + 120 0008 0948 ldr r0, .L8+4 + 121 .LVL3: + 122 000a 1A68 ldr r2, [r3] + 123 000c 5043 muls r0, r2 + 124 000e 094A ldr r2, .L8+8 + 125 0010 9446 mov ip, r2 + 126 0012 6044 add r0, r0, ip + 127 0014 1860 str r0, [r3] + 128 0016 0849 ldr r1, .L8+12 + 129 .LVL4: + 130 0018 FFF7FEFF bl __aeabi_uidivmod + 131 .LVL5: + 132 001c 0800 movs r0, r1 + 133 .LBE5: + ARM GAS /tmp/cco3Pbva.s page 4 + + + 134 .LBE4: + 43:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** return ( int32_t )rand1( ) % ( max - min + 1 ) + min; + 135 .loc 1 43 0 + 136 001e 611B subs r1, r4, r5 + 137 0020 0131 adds r1, r1, #1 + 138 0022 FFF7FEFF bl __aeabi_idivmod + 139 .LVL6: + 140 0026 4819 adds r0, r1, r5 + 44:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 141 .loc 1 44 0 + 142 @ sp needed + 143 .LVL7: + 144 .LVL8: + 145 0028 70BD pop {r4, r5, r6, pc} + 146 .L9: + 147 002a C046 .align 2 + 148 .L8: + 149 002c 00000000 .word .LANCHOR0 + 150 0030 6D4EC641 .word 1103515245 + 151 0034 39300000 .word 12345 + 152 0038 FFFFFF7F .word 2147483647 + 153 .cfi_endproc + 154 .LFE87: + 156 .section .text.memcpy1,"ax",%progbits + 157 .align 1 + 158 .global memcpy1 + 159 .syntax unified + 160 .code 16 + 161 .thumb_func + 162 .fpu softvfp + 164 memcpy1: + 165 .LFB88: + 45:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 46:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** void memcpy1( uint8_t *dst, const uint8_t *src, uint16_t size ) + 47:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 166 .loc 1 47 0 + 167 .cfi_startproc + 168 @ args = 0, pretend = 0, frame = 0 + 169 @ frame_needed = 0, uses_anonymous_args = 0 + 170 @ link register save eliminated. + 171 .LVL9: + 48:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 172 .loc 1 48 0 + 173 0000 04E0 b .L11 + 174 .LVL10: + 175 .L12: + 49:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 50:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** *dst++ = *src++; + 176 .loc 1 50 0 + 177 0002 0A78 ldrb r2, [r1] + 178 0004 0270 strb r2, [r0] + 48:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 179 .loc 1 48 0 + 180 0006 1A00 movs r2, r3 + 181 .loc 1 50 0 + 182 0008 0131 adds r1, r1, #1 + 183 .LVL11: + ARM GAS /tmp/cco3Pbva.s page 5 + + + 184 000a 0130 adds r0, r0, #1 + 185 .LVL12: + 186 .L11: + 48:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 187 .loc 1 48 0 + 188 000c 531E subs r3, r2, #1 + 189 000e 9BB2 uxth r3, r3 + 190 .LVL13: + 191 0010 002A cmp r2, #0 + 192 0012 F6D1 bne .L12 + 51:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 52:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 193 .loc 1 52 0 + 194 @ sp needed + 195 0014 7047 bx lr + 196 .cfi_endproc + 197 .LFE88: + 199 .section .text.memcpyr,"ax",%progbits + 200 .align 1 + 201 .global memcpyr + 202 .syntax unified + 203 .code 16 + 204 .thumb_func + 205 .fpu softvfp + 207 memcpyr: + 208 .LFB89: + 53:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 54:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** void memcpyr( uint8_t *dst, const uint8_t *src, uint16_t size ) + 55:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 209 .loc 1 55 0 + 210 .cfi_startproc + 211 @ args = 0, pretend = 0, frame = 0 + 212 @ frame_needed = 0, uses_anonymous_args = 0 + 213 @ link register save eliminated. + 214 .LVL14: + 56:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** dst = dst + ( size - 1 ); + 215 .loc 1 56 0 + 216 0000 531E subs r3, r2, #1 + 217 0002 C018 adds r0, r0, r3 + 218 .LVL15: + 57:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 219 .loc 1 57 0 + 220 0004 04E0 b .L14 + 221 .LVL16: + 222 .L15: + 58:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 59:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** *dst-- = *src++; + 223 .loc 1 59 0 + 224 0006 0A78 ldrb r2, [r1] + 225 0008 0270 strb r2, [r0] + 57:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 226 .loc 1 57 0 + 227 000a 1A00 movs r2, r3 + 228 .loc 1 59 0 + 229 000c 0131 adds r1, r1, #1 + 230 .LVL17: + 231 000e 0138 subs r0, r0, #1 + ARM GAS /tmp/cco3Pbva.s page 6 + + + 232 .LVL18: + 233 .L14: + 57:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 234 .loc 1 57 0 + 235 0010 531E subs r3, r2, #1 + 236 0012 9BB2 uxth r3, r3 + 237 .LVL19: + 238 0014 002A cmp r2, #0 + 239 0016 F6D1 bne .L15 + 60:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 61:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 240 .loc 1 61 0 + 241 @ sp needed + 242 0018 7047 bx lr + 243 .cfi_endproc + 244 .LFE89: + 246 .section .text.memset1,"ax",%progbits + 247 .align 1 + 248 .global memset1 + 249 .syntax unified + 250 .code 16 + 251 .thumb_func + 252 .fpu softvfp + 254 memset1: + 255 .LFB90: + 62:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 63:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** void memset1( uint8_t *dst, uint8_t value, uint16_t size ) + 64:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 256 .loc 1 64 0 + 257 .cfi_startproc + 258 @ args = 0, pretend = 0, frame = 0 + 259 @ frame_needed = 0, uses_anonymous_args = 0 + 260 @ link register save eliminated. + 261 .LVL20: + 65:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 262 .loc 1 65 0 + 263 0000 02E0 b .L17 + 264 .LVL21: + 265 .L18: + 66:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 67:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** *dst++ = value; + 266 .loc 1 67 0 + 267 0002 0170 strb r1, [r0] + 65:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 268 .loc 1 65 0 + 269 0004 1A00 movs r2, r3 + 270 .loc 1 67 0 + 271 0006 0130 adds r0, r0, #1 + 272 .LVL22: + 273 .L17: + 65:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** while( size-- ) + 274 .loc 1 65 0 + 275 0008 531E subs r3, r2, #1 + 276 000a 9BB2 uxth r3, r3 + 277 .LVL23: + 278 000c 002A cmp r2, #0 + 279 000e F8D1 bne .L18 + ARM GAS /tmp/cco3Pbva.s page 7 + + + 68:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 69:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 280 .loc 1 69 0 + 281 @ sp needed + 282 0010 7047 bx lr + 283 .cfi_endproc + 284 .LFE90: + 286 .section .text.Nibble2HexChar,"ax",%progbits + 287 .align 1 + 288 .global Nibble2HexChar + 289 .syntax unified + 290 .code 16 + 291 .thumb_func + 292 .fpu softvfp + 294 Nibble2HexChar: + 295 .LFB91: + 70:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** + 71:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** int8_t Nibble2HexChar( uint8_t a ) + 72:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 296 .loc 1 72 0 + 297 .cfi_startproc + 298 @ args = 0, pretend = 0, frame = 0 + 299 @ frame_needed = 0, uses_anonymous_args = 0 + 300 @ link register save eliminated. + 301 .LVL24: + 73:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** if( a < 10 ) + 302 .loc 1 73 0 + 303 0000 0928 cmp r0, #9 + 304 0002 04D9 bls .L23 + 74:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 75:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** return '0' + a; + 76:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 77:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** else if( a < 16 ) + 305 .loc 1 77 0 + 306 0004 0F28 cmp r0, #15 + 307 0006 05D8 bhi .L22 + 78:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 79:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** return 'A' + ( a - 10 ); + 308 .loc 1 79 0 + 309 0008 3730 adds r0, r0, #55 + 310 .LVL25: + 311 000a 40B2 sxtb r0, r0 + 312 000c 01E0 b .L21 + 313 .LVL26: + 314 .L23: + 75:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 315 .loc 1 75 0 + 316 000e 3030 adds r0, r0, #48 + 317 .LVL27: + 318 0010 40B2 sxtb r0, r0 + 319 .L21: + 80:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 81:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** else + 82:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** { + 83:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** return '?'; + 84:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 85:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + ARM GAS /tmp/cco3Pbva.s page 8 + + + 320 .loc 1 85 0 + 321 @ sp needed + 322 0012 7047 bx lr + 323 .LVL28: + 324 .L22: + 83:./Middlewares/Third_Party/Lora/Utilities/utilities.c **** } + 325 .loc 1 83 0 + 326 0014 3F20 movs r0, #63 + 327 .LVL29: + 328 0016 FCE7 b .L21 + 329 .cfi_endproc + 330 .LFE91: + 332 .section .data.next,"aw",%progbits + 333 .align 2 + 334 .set .LANCHOR0,. + 0 + 337 next: + 338 0000 01000000 .word 1 + 339 .text + 340 .Letext0: + 341 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 342 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 343 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 344 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 345 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 346 .file 7 "/usr/arm-none-eabi/include/stdlib.h" + 347 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 348 .file 9 "/usr/arm-none-eabi/include/math.h" + ARM GAS /tmp/cco3Pbva.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 utilities.c + /tmp/cco3Pbva.s:17 .text.rand1:0000000000000000 $t + /tmp/cco3Pbva.s:24 .text.rand1:0000000000000000 rand1 + /tmp/cco3Pbva.s:55 .text.rand1:000000000000001c $d + /tmp/cco3Pbva.s:63 .text.srand1:0000000000000000 $t + /tmp/cco3Pbva.s:70 .text.srand1:0000000000000000 srand1 + /tmp/cco3Pbva.s:87 .text.srand1:0000000000000008 $d + /tmp/cco3Pbva.s:93 .text.randr:0000000000000000 $t + /tmp/cco3Pbva.s:100 .text.randr:0000000000000000 randr + /tmp/cco3Pbva.s:149 .text.randr:000000000000002c $d + /tmp/cco3Pbva.s:157 .text.memcpy1:0000000000000000 $t + /tmp/cco3Pbva.s:164 .text.memcpy1:0000000000000000 memcpy1 + /tmp/cco3Pbva.s:200 .text.memcpyr:0000000000000000 $t + /tmp/cco3Pbva.s:207 .text.memcpyr:0000000000000000 memcpyr + /tmp/cco3Pbva.s:247 .text.memset1:0000000000000000 $t + /tmp/cco3Pbva.s:254 .text.memset1:0000000000000000 memset1 + /tmp/cco3Pbva.s:287 .text.Nibble2HexChar:0000000000000000 $t + /tmp/cco3Pbva.s:294 .text.Nibble2HexChar:0000000000000000 Nibble2HexChar + /tmp/cco3Pbva.s:333 .data.next:0000000000000000 $d + /tmp/cco3Pbva.s:337 .data.next:0000000000000000 next + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +__aeabi_uidivmod +__aeabi_idivmod diff --git a/build/vcom.d b/build/vcom.d new file mode 100644 index 0000000..3abc511 --- /dev/null +++ b/build/vcom.d @@ -0,0 +1,137 @@ +build/vcom.d: Src/vcom.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h Inc/vcom.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Inc/vcom.h: diff --git a/build/vcom.lst b/build/vcom.lst new file mode 100644 index 0000000..7183863 --- /dev/null +++ b/build/vcom.lst @@ -0,0 +1,1441 @@ +ARM GAS /tmp/ccoAAM0e.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "vcom.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.vcom_Init,"ax",%progbits + 16 .align 1 + 17 .global vcom_Init + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 vcom_Init: + 24 .LFB96: + 25 .file 1 "./Src/vcom.c" + 1:./Src/vcom.c **** /****************************************************************************** + 2:./Src/vcom.c **** * @file vcom.c + 3:./Src/vcom.c **** * @author MCD Application Team + 4:./Src/vcom.c **** * @version V1.1.2 + 5:./Src/vcom.c **** * @date 08-September-2017 + 6:./Src/vcom.c **** * @brief manages virtual com port + 7:./Src/vcom.c **** ****************************************************************************** + 8:./Src/vcom.c **** * @attention + 9:./Src/vcom.c **** * + 10:./Src/vcom.c **** *

© Copyright (c) 2017 STMicroelectronics International N.V. + 11:./Src/vcom.c **** * All rights reserved.

+ 12:./Src/vcom.c **** * + 13:./Src/vcom.c **** * Redistribution and use in source and binary forms, with or without + 14:./Src/vcom.c **** * modification, are permitted, provided that the following conditions are met: + 15:./Src/vcom.c **** * + 16:./Src/vcom.c **** * 1. Redistribution of source code must retain the above copyright notice, + 17:./Src/vcom.c **** * this list of conditions and the following disclaimer. + 18:./Src/vcom.c **** * 2. Redistributions in binary form must reproduce the above copyright notice, + 19:./Src/vcom.c **** * this list of conditions and the following disclaimer in the documentation + 20:./Src/vcom.c **** * and/or other materials provided with the distribution. + 21:./Src/vcom.c **** * 3. Neither the name of STMicroelectronics nor the names of other + 22:./Src/vcom.c **** * contributors to this software may be used to endorse or promote products + 23:./Src/vcom.c **** * derived from this software without specific written permission. + 24:./Src/vcom.c **** * 4. This software, including modifications and/or derivative works of this + 25:./Src/vcom.c **** * software, must execute solely and exclusively on microcontroller or + 26:./Src/vcom.c **** * microprocessor devices manufactured by or for STMicroelectronics. + 27:./Src/vcom.c **** * 5. Redistribution and use of this software other than as permitted under + 28:./Src/vcom.c **** * this license is void and will automatically terminate your rights under + 29:./Src/vcom.c **** * this license. + 30:./Src/vcom.c **** * + 31:./Src/vcom.c **** * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + 32:./Src/vcom.c **** * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + 33:./Src/vcom.c **** * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + ARM GAS /tmp/ccoAAM0e.s page 2 + + + 34:./Src/vcom.c **** * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + 35:./Src/vcom.c **** * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + 36:./Src/vcom.c **** * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + 37:./Src/vcom.c **** * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 38:./Src/vcom.c **** * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + 39:./Src/vcom.c **** * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + 40:./Src/vcom.c **** * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + 41:./Src/vcom.c **** * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + 42:./Src/vcom.c **** * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 43:./Src/vcom.c **** * + 44:./Src/vcom.c **** ****************************************************************************** + 45:./Src/vcom.c **** */ + 46:./Src/vcom.c **** + 47:./Src/vcom.c **** #include "hw.h" + 48:./Src/vcom.c **** #include "vcom.h" + 49:./Src/vcom.c **** #include + 50:./Src/vcom.c **** + 51:./Src/vcom.c **** + 52:./Src/vcom.c **** /* Private typedef -----------------------------------------------------------*/ + 53:./Src/vcom.c **** /* Private define ------------------------------------------------------------*/ + 54:./Src/vcom.c **** #define BUFSIZE 256 + 55:./Src/vcom.c **** #define USARTX_IRQn USART2_IRQn + 56:./Src/vcom.c **** /* Private macro -------------------------------------------------------------*/ + 57:./Src/vcom.c **** /* Private variables ---------------------------------------------------------*/ + 58:./Src/vcom.c **** + 59:./Src/vcom.c **** /* buffer */ + 60:./Src/vcom.c **** static char buff[BUFSIZE]; + 61:./Src/vcom.c **** /* buffer write index*/ + 62:./Src/vcom.c **** __IO uint16_t iw=0; + 63:./Src/vcom.c **** /* buffer read index*/ + 64:./Src/vcom.c **** static uint16_t ir=0; + 65:./Src/vcom.c **** /* Uart Handle */ + 66:./Src/vcom.c **** static UART_HandleTypeDef UartHandle; + 67:./Src/vcom.c **** + 68:./Src/vcom.c **** /* Private function prototypes -----------------------------------------------*/ + 69:./Src/vcom.c **** /* Functions Definition ------------------------------------------------------*/ + 70:./Src/vcom.c **** + 71:./Src/vcom.c **** void vcom_Init(void) + 72:./Src/vcom.c **** { + 26 .loc 1 72 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 10B5 push {r4, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 4, -8 + 34 .cfi_offset 14, -4 + 73:./Src/vcom.c **** /*## Configure the UART peripheral ######################################*/ + 74:./Src/vcom.c **** /* Put the USART peripheral in the Asynchronous mode (UART Mode) */ + 75:./Src/vcom.c **** /* UART1 configured as follow: + 76:./Src/vcom.c **** - Word Length = 8 Bits + 77:./Src/vcom.c **** - Stop Bit = One Stop bit + 78:./Src/vcom.c **** - Parity = ODD parity + 79:./Src/vcom.c **** - BaudRate = 921600 baud + 80:./Src/vcom.c **** - Hardware flow control disabled (RTS and CTS signals) */ + 81:./Src/vcom.c **** UartHandle.Instance = USARTX; + ARM GAS /tmp/ccoAAM0e.s page 3 + + + 35 .loc 1 81 0 + 36 0002 0F48 ldr r0, .L4 + 37 0004 0F4B ldr r3, .L4+4 + 38 0006 0360 str r3, [r0] + 82:./Src/vcom.c **** + 83:./Src/vcom.c **** UartHandle.Init.BaudRate = 115200; + 39 .loc 1 83 0 + 40 0008 E123 movs r3, #225 + 41 000a 5B02 lsls r3, r3, #9 + 42 000c 4360 str r3, [r0, #4] + 84:./Src/vcom.c **** UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + 43 .loc 1 84 0 + 44 000e 0023 movs r3, #0 + 45 0010 8360 str r3, [r0, #8] + 85:./Src/vcom.c **** UartHandle.Init.StopBits = UART_STOPBITS_1; + 46 .loc 1 85 0 + 47 0012 C360 str r3, [r0, #12] + 86:./Src/vcom.c **** UartHandle.Init.Parity = UART_PARITY_NONE; + 48 .loc 1 86 0 + 49 0014 0361 str r3, [r0, #16] + 87:./Src/vcom.c **** UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 50 .loc 1 87 0 + 51 0016 8361 str r3, [r0, #24] + 88:./Src/vcom.c **** UartHandle.Init.Mode = UART_MODE_TX_RX; + 52 .loc 1 88 0 + 53 0018 0C33 adds r3, r3, #12 + 54 001a 4361 str r3, [r0, #20] + 89:./Src/vcom.c **** + 90:./Src/vcom.c **** if(HAL_UART_Init(&UartHandle) != HAL_OK) + 55 .loc 1 90 0 + 56 001c FFF7FEFF bl HAL_UART_Init + 57 .LVL0: + 58 0020 0028 cmp r0, #0 + 59 0022 08D1 bne .L3 + 60 .L2: + 91:./Src/vcom.c **** { + 92:./Src/vcom.c **** /* Initialization Error */ + 93:./Src/vcom.c **** Error_Handler(); + 94:./Src/vcom.c **** } + 95:./Src/vcom.c **** + 96:./Src/vcom.c **** HAL_NVIC_SetPriority(USARTX_IRQn, 0x1, 0); + 61 .loc 1 96 0 + 62 0024 0022 movs r2, #0 + 63 0026 0121 movs r1, #1 + 64 0028 1C20 movs r0, #28 + 65 002a FFF7FEFF bl HAL_NVIC_SetPriority + 66 .LVL1: + 97:./Src/vcom.c **** HAL_NVIC_EnableIRQ(USARTX_IRQn); + 67 .loc 1 97 0 + 68 002e 1C20 movs r0, #28 + 69 0030 FFF7FEFF bl HAL_NVIC_EnableIRQ + 70 .LVL2: + 98:./Src/vcom.c **** } + 71 .loc 1 98 0 + 72 @ sp needed + 73 0034 10BD pop {r4, pc} + 74 .L3: + ARM GAS /tmp/ccoAAM0e.s page 4 + + + 93:./Src/vcom.c **** } + 75 .loc 1 93 0 + 76 0036 5D21 movs r1, #93 + 77 0038 0348 ldr r0, .L4+8 + 78 003a FFF7FEFF bl _Error_Handler + 79 .LVL3: + 80 003e F1E7 b .L2 + 81 .L5: + 82 .align 2 + 83 .L4: + 84 0040 00000000 .word .LANCHOR0 + 85 0044 00440040 .word 1073759232 + 86 0048 00000000 .word .LC1 + 87 .cfi_endproc + 88 .LFE96: + 90 .section .text.vcom_DeInit,"ax",%progbits + 91 .align 1 + 92 .global vcom_DeInit + 93 .syntax unified + 94 .code 16 + 95 .thumb_func + 96 .fpu softvfp + 98 vcom_DeInit: + 99 .LFB97: + 99:./Src/vcom.c **** + 100:./Src/vcom.c **** + 101:./Src/vcom.c **** void vcom_DeInit(void) + 102:./Src/vcom.c **** { + 100 .loc 1 102 0 + 101 .cfi_startproc + 102 @ args = 0, pretend = 0, frame = 0 + 103 @ frame_needed = 0, uses_anonymous_args = 0 + 104 0000 10B5 push {r4, lr} + 105 .LCFI1: + 106 .cfi_def_cfa_offset 8 + 107 .cfi_offset 4, -8 + 108 .cfi_offset 14, -4 + 103:./Src/vcom.c **** #if 1 + 104:./Src/vcom.c **** HAL_UART_DeInit(&UartHandle); + 109 .loc 1 104 0 + 110 0002 0248 ldr r0, .L7 + 111 0004 FFF7FEFF bl HAL_UART_DeInit + 112 .LVL4: + 105:./Src/vcom.c **** #endif + 106:./Src/vcom.c **** } + 113 .loc 1 106 0 + 114 @ sp needed + 115 0008 10BD pop {r4, pc} + 116 .L8: + 117 000a C046 .align 2 + 118 .L7: + 119 000c 00000000 .word .LANCHOR0 + 120 .cfi_endproc + 121 .LFE97: + 123 .section .text.vcom_Send,"ax",%progbits + 124 .align 1 + 125 .global vcom_Send + ARM GAS /tmp/ccoAAM0e.s page 5 + + + 126 .syntax unified + 127 .code 16 + 128 .thumb_func + 129 .fpu softvfp + 131 vcom_Send: + 132 .LFB98: + 107:./Src/vcom.c **** + 108:./Src/vcom.c **** void vcom_Send( char *format, ... ) + 109:./Src/vcom.c **** { + 133 .loc 1 109 0 + 134 .cfi_startproc + 135 @ args = 4, pretend = 16, frame = 136 + 136 @ frame_needed = 0, uses_anonymous_args = 1 + 137 .LVL5: + 138 0000 0FB4 push {r0, r1, r2, r3} + 139 .LCFI2: + 140 .cfi_def_cfa_offset 16 + 141 0002 F0B5 push {r4, r5, r6, r7, lr} + 142 .LCFI3: + 143 .cfi_def_cfa_offset 36 + 144 .cfi_offset 4, -36 + 145 .cfi_offset 5, -32 + 146 .cfi_offset 6, -28 + 147 .cfi_offset 7, -24 + 148 .cfi_offset 14, -20 + 149 0004 CE46 mov lr, r9 + 150 0006 4746 mov r7, r8 + 151 0008 80B5 push {r7, lr} + 152 .LCFI4: + 153 .cfi_def_cfa_offset 44 + 154 .cfi_offset 8, -44 + 155 .cfi_offset 9, -40 + 156 000a A3B0 sub sp, sp, #140 + 157 .LCFI5: + 158 .cfi_def_cfa_offset 184 + 159 000c 2AAB add r3, sp, #168 + 160 000e 02CB ldmia r3!, {r1} + 110:./Src/vcom.c **** va_list args; + 111:./Src/vcom.c **** va_start(args, format); + 161 .loc 1 111 0 + 162 0010 2193 str r3, [sp, #132] + 163 .LBB21: + 164 .LBB22: + 165 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved. + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met: + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer. + ARM GAS /tmp/ccoAAM0e.s page 6 + + + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution. + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission. + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE. + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/ + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ ) + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccoAAM0e.s page 7 + + + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccoAAM0e.s page 8 + + + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result; + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + ARM GAS /tmp/ccoAAM0e.s page 9 + + + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); + 166 .loc 2 203 0 + 167 .syntax divided + 168 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 169 0012 EFF31085 MRS r5, primask + 170 @ 0 "" 2 + 171 .thumb + 172 .syntax unified + 173 .LBE22: + 174 .LBE21: + 175 .LBB23: + 176 .LBB24: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 177 .loc 2 71 0 + 178 .syntax divided + 179 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 180 0016 72B6 cpsid i + 181 @ 0 "" 2 + 182 .thumb + 183 .syntax unified + 184 .LBE24: + 185 .LBE23: + 112:./Src/vcom.c **** uint8_t len; + 113:./Src/vcom.c **** uint8_t lenTop; + 114:./Src/vcom.c **** char tempBuff[128]; + 115:./Src/vcom.c **** + 116:./Src/vcom.c **** BACKUP_PRIMASK(); + 117:./Src/vcom.c **** DISABLE_IRQ(); + 118:./Src/vcom.c **** + 119:./Src/vcom.c **** /*convert into string at buff[0] of length iw*/ + 120:./Src/vcom.c **** len = vsprintf(&tempBuff[0], format, args); + 186 .loc 1 120 0 + 187 0018 219A ldr r2, [sp, #132] + 188 001a 01A8 add r0, sp, #4 + 189 001c FFF7FEFF bl vsprintf + 190 .LVL6: + 191 0020 C6B2 uxtb r6, r0 + 192 .LVL7: + 121:./Src/vcom.c **** + ARM GAS /tmp/ccoAAM0e.s page 10 + + + 122:./Src/vcom.c **** if (iw+len0 ) + 304 .loc 1 146 0 + 305 0002 12E0 b .L16 + 306 .L17: + 307 .LBB27: + 308 .LBB28: + 309 .LBB29: + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 310 .loc 2 203 0 + 311 .syntax divided + 312 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 313 0004 EFF31082 MRS r2, primask + 314 @ 0 "" 2 + 315 .thumb + 316 .syntax unified + 317 .LBE29: + 318 .LBE28: + 319 .LBB30: + 320 .LBB31: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 321 .loc 2 71 0 + 322 .syntax divided + 323 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 324 0008 72B6 cpsid i + ARM GAS /tmp/ccoAAM0e.s page 13 + + + 325 @ 0 "" 2 + 326 .thumb + 327 .syntax unified + 328 .LBE31: + 329 .LBE30: + 147:./Src/vcom.c **** { + 148:./Src/vcom.c **** BACKUP_PRIMASK(); + 149:./Src/vcom.c **** DISABLE_IRQ(); + 150:./Src/vcom.c **** + 151:./Src/vcom.c **** CurChar = &buff[ir]; + 330 .loc 1 151 0 + 331 000a 114C ldr r4, .L18 + 332 000c 2388 ldrh r3, [r4] + 333 000e 1149 ldr r1, .L18+4 + 334 0010 5918 adds r1, r3, r1 + 335 .LVL18: + 152:./Src/vcom.c **** ir= (ir+1) %BUFSIZE; + 336 .loc 1 152 0 + 337 0012 0133 adds r3, r3, #1 + 338 0014 FF20 movs r0, #255 + 339 0016 0340 ands r3, r0 + 340 0018 2380 strh r3, [r4] + 341 .LBB32: + 342 .LBB33: + 343 .loc 2 215 0 + 344 .syntax divided + 345 @ 215 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 346 001a 82F31088 MSR primask, r2 + 347 @ 0 "" 2 + 348 .thumb + 349 .syntax unified + 350 .LBE33: + 351 .LBE32: + 153:./Src/vcom.c **** + 154:./Src/vcom.c **** RESTORE_PRIMASK(); + 155:./Src/vcom.c **** + 156:./Src/vcom.c **** HAL_UART_Transmit(&UartHandle,(uint8_t *) CurChar, 1, 300); + 352 .loc 1 156 0 + 353 001e 9623 movs r3, #150 + 354 0020 5B00 lsls r3, r3, #1 + 355 0022 0122 movs r2, #1 + 356 0024 0C48 ldr r0, .L18+8 + 357 0026 FFF7FEFF bl HAL_UART_Transmit + 358 .LVL19: + 359 .L16: + 360 .LBE27: + 146:./Src/vcom.c **** { + 361 .loc 1 146 0 + 362 002a 0C4B ldr r3, .L18+12 + 363 002c 1B88 ldrh r3, [r3] + 364 002e 0133 adds r3, r3, #1 + 365 0030 FF33 adds r3, r3, #255 + 366 0032 074A ldr r2, .L18 + 367 0034 1288 ldrh r2, [r2] + 368 0036 9B1A subs r3, r3, r2 + 369 0038 D917 asrs r1, r3, #31 + 370 003a 090E lsrs r1, r1, #24 + ARM GAS /tmp/ccoAAM0e.s page 14 + + + 371 003c 5B18 adds r3, r3, r1 + 372 003e FF22 movs r2, #255 + 373 0040 1340 ands r3, r2 + 374 0042 5B1A subs r3, r3, r1 + 375 0044 002B cmp r3, #0 + 376 0046 DDDC bgt .L17 + 157:./Src/vcom.c **** } + 158:./Src/vcom.c **** HAL_NVIC_ClearPendingIRQ(USARTX_IRQn); + 377 .loc 1 158 0 + 378 0048 1C20 movs r0, #28 + 379 004a FFF7FEFF bl HAL_NVIC_ClearPendingIRQ + 380 .LVL20: + 159:./Src/vcom.c **** } + 381 .loc 1 159 0 + 382 @ sp needed + 383 004e 10BD pop {r4, pc} + 384 .L19: + 385 .align 2 + 386 .L18: + 387 0050 00000000 .word .LANCHOR2 + 388 0054 00000000 .word buff + 389 0058 00000000 .word .LANCHOR0 + 390 005c 00000000 .word .LANCHOR1 + 391 .cfi_endproc + 392 .LFE99: + 394 .section .text.vcom_Send_Lp,"ax",%progbits + 395 .align 1 + 396 .global vcom_Send_Lp + 397 .syntax unified + 398 .code 16 + 399 .thumb_func + 400 .fpu softvfp + 402 vcom_Send_Lp: + 403 .LFB100: + 160:./Src/vcom.c **** + 161:./Src/vcom.c **** void vcom_Send_Lp( char *format, ... ) + 162:./Src/vcom.c **** { + 404 .loc 1 162 0 + 405 .cfi_startproc + 406 @ args = 4, pretend = 16, frame = 136 + 407 @ frame_needed = 0, uses_anonymous_args = 1 + 408 .LVL21: + 409 0000 0FB4 push {r0, r1, r2, r3} + 410 .LCFI7: + 411 .cfi_def_cfa_offset 16 + 412 0002 F0B5 push {r4, r5, r6, r7, lr} + 413 .LCFI8: + 414 .cfi_def_cfa_offset 36 + 415 .cfi_offset 4, -36 + 416 .cfi_offset 5, -32 + 417 .cfi_offset 6, -28 + 418 .cfi_offset 7, -24 + 419 .cfi_offset 14, -20 + 420 0004 CE46 mov lr, r9 + 421 0006 4746 mov r7, r8 + 422 0008 80B5 push {r7, lr} + 423 .LCFI9: + ARM GAS /tmp/ccoAAM0e.s page 15 + + + 424 .cfi_def_cfa_offset 44 + 425 .cfi_offset 8, -44 + 426 .cfi_offset 9, -40 + 427 000a A3B0 sub sp, sp, #140 + 428 .LCFI10: + 429 .cfi_def_cfa_offset 184 + 430 000c 2AAB add r3, sp, #168 + 431 000e 02CB ldmia r3!, {r1} + 163:./Src/vcom.c **** va_list args; + 164:./Src/vcom.c **** va_start(args, format); + 432 .loc 1 164 0 + 433 0010 2193 str r3, [sp, #132] + 434 .LBB34: + 435 .LBB35: + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 436 .loc 2 203 0 + 437 .syntax divided + 438 @ 203 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 439 0012 EFF31085 MRS r5, primask + 440 @ 0 "" 2 + 441 .thumb + 442 .syntax unified + 443 .LBE35: + 444 .LBE34: + 445 .LBB36: + 446 .LBB37: + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 447 .loc 2 71 0 + 448 .syntax divided + 449 @ 71 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 450 0016 72B6 cpsid i + 451 @ 0 "" 2 + 452 .thumb + 453 .syntax unified + 454 .LBE37: + 455 .LBE36: + 165:./Src/vcom.c **** uint8_t len; + 166:./Src/vcom.c **** uint8_t lenTop; + 167:./Src/vcom.c **** char tempBuff[128]; + 168:./Src/vcom.c **** + 169:./Src/vcom.c **** BACKUP_PRIMASK(); + 170:./Src/vcom.c **** DISABLE_IRQ(); + 171:./Src/vcom.c **** + 172:./Src/vcom.c **** /*convert into string at buff[0] of length iw*/ + 173:./Src/vcom.c **** len = vsprintf(&tempBuff[0], format, args); + 456 .loc 1 173 0 + 457 0018 219A ldr r2, [sp, #132] + 458 001a 01A8 add r0, sp, #4 + 459 001c FFF7FEFF bl vsprintf + 460 .LVL22: + 461 0020 C6B2 uxtb r6, r0 + 462 .LVL23: + 174:./Src/vcom.c **** + 175:./Src/vcom.c **** if (iw+len" + 833 .file 14 "/usr/arm-none-eabi/include/stdio.h" + 834 .file 15 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 835 .file 16 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h" + 836 .file 17 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + ARM GAS /tmp/ccoAAM0e.s page 24 + + + 837 .file 18 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h" + 838 .file 19 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h" + 839 .file 20 "Inc/debug.h" + ARM GAS /tmp/ccoAAM0e.s page 25 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 vcom.c + /tmp/ccoAAM0e.s:16 .text.vcom_Init:0000000000000000 $t + /tmp/ccoAAM0e.s:23 .text.vcom_Init:0000000000000000 vcom_Init + /tmp/ccoAAM0e.s:84 .text.vcom_Init:0000000000000040 $d + /tmp/ccoAAM0e.s:91 .text.vcom_DeInit:0000000000000000 $t + /tmp/ccoAAM0e.s:98 .text.vcom_DeInit:0000000000000000 vcom_DeInit + /tmp/ccoAAM0e.s:119 .text.vcom_DeInit:000000000000000c $d + /tmp/ccoAAM0e.s:124 .text.vcom_Send:0000000000000000 $t + /tmp/ccoAAM0e.s:131 .text.vcom_Send:0000000000000000 vcom_Send + /tmp/ccoAAM0e.s:280 .text.vcom_Send:0000000000000094 $d + /tmp/ccoAAM0e.s:800 .bss.buff:0000000000000000 buff + /tmp/ccoAAM0e.s:286 .text.vcom_Print:0000000000000000 $t + /tmp/ccoAAM0e.s:293 .text.vcom_Print:0000000000000000 vcom_Print + /tmp/ccoAAM0e.s:387 .text.vcom_Print:0000000000000050 $d + /tmp/ccoAAM0e.s:395 .text.vcom_Send_Lp:0000000000000000 $t + /tmp/ccoAAM0e.s:402 .text.vcom_Send_Lp:0000000000000000 vcom_Send_Lp + /tmp/ccoAAM0e.s:546 .text.vcom_Send_Lp:000000000000008c $d + /tmp/ccoAAM0e.s:552 .text.vcom_IoInit:0000000000000000 $t + /tmp/ccoAAM0e.s:559 .text.vcom_IoInit:0000000000000000 vcom_IoInit + /tmp/ccoAAM0e.s:633 .text.vcom_IoInit:0000000000000054 $d + /tmp/ccoAAM0e.s:638 .text.HAL_UART_MspInit:0000000000000000 $t + /tmp/ccoAAM0e.s:645 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit + /tmp/ccoAAM0e.s:673 .text.HAL_UART_MspInit:0000000000000014 $d + /tmp/ccoAAM0e.s:678 .text.vcom_IoDeInit:0000000000000000 $t + /tmp/ccoAAM0e.s:685 .text.vcom_IoDeInit:0000000000000000 vcom_IoDeInit + /tmp/ccoAAM0e.s:755 .text.vcom_IoDeInit:0000000000000054 $d + /tmp/ccoAAM0e.s:760 .text.HAL_UART_MspDeInit:0000000000000000 $t + /tmp/ccoAAM0e.s:767 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit + /tmp/ccoAAM0e.s:814 .bss.iw:0000000000000000 iw + /tmp/ccoAAM0e.s:790 .bss.UartHandle:0000000000000000 $d + /tmp/ccoAAM0e.s:794 .bss.UartHandle:0000000000000000 UartHandle + /tmp/ccoAAM0e.s:797 .bss.buff:0000000000000000 $d + /tmp/ccoAAM0e.s:803 .bss.ir:0000000000000000 $d + /tmp/ccoAAM0e.s:807 .bss.ir:0000000000000000 ir + /tmp/ccoAAM0e.s:810 .bss.iw:0000000000000000 $d + /tmp/ccoAAM0e.s:817 .rodata.vcom_Init.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_UART_Init +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +_Error_Handler +HAL_UART_DeInit +vsprintf +memcpy +HAL_NVIC_SetPendingIRQ +HAL_UART_Transmit +HAL_NVIC_ClearPendingIRQ +HAL_GPIO_Init +memset diff --git a/build/voc_sensor.d b/build/voc_sensor.d new file mode 100644 index 0000000..76139c8 --- /dev/null +++ b/build/voc_sensor.d @@ -0,0 +1,147 @@ +build/voc_sensor.d: Src/voc_sensor.c Inc/hw.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/core_cmInstr.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/core_cmFunc.h \ + Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + Inc/stm32l0xx_hal_conf.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h \ + Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h \ + Inc/stm32l0xx_hw_conf.h Inc/hw.h Inc/hw_conf.h Inc/hw_gpio.h \ + Inc/hw_spi.h Inc/hw_rtc.h \ + Middlewares/Third_Party/Lora/Utilities/utilities.h Inc/hw_conf.h \ + Drivers/CMSIS/Include/arm_math.h Drivers/CMSIS/Include/core_cm0.h \ + Inc/hw_msp.h Inc/debug.h Inc/vcom.h Inc/hw_i2c.h Inc/main.h \ + Src/voc_sensor.h Src/../Drivers/BME680/bme680.h \ + Src/../Drivers/BME680/bme680_defs.h + +Inc/hw.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h: + +Drivers/CMSIS/Include/core_cm0plus.h: + +Drivers/CMSIS/Include/core_cmInstr.h: + +Drivers/CMSIS/Include/cmsis_gcc.h: + +Drivers/CMSIS/Include/core_cmFunc.h: + +Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +Inc/stm32l0xx_hal_conf.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h: + +Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h: + +Inc/stm32l0xx_hw_conf.h: + +Inc/hw.h: + +Inc/hw_conf.h: + +Inc/hw_gpio.h: + +Inc/hw_spi.h: + +Inc/hw_rtc.h: + +Middlewares/Third_Party/Lora/Utilities/utilities.h: + +Inc/hw_conf.h: + +Drivers/CMSIS/Include/arm_math.h: + +Drivers/CMSIS/Include/core_cm0.h: + +Inc/hw_msp.h: + +Inc/debug.h: + +Inc/vcom.h: + +Inc/hw_i2c.h: + +Inc/main.h: + +Src/voc_sensor.h: + +Src/../Drivers/BME680/bme680.h: + +Src/../Drivers/BME680/bme680_defs.h: diff --git a/build/voc_sensor.lst b/build/voc_sensor.lst new file mode 100644 index 0000000..f9c34e7 --- /dev/null +++ b/build/voc_sensor.lst @@ -0,0 +1,741 @@ +ARM GAS /tmp/ccnIeFZt.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "voc_sensor.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.user_delay_ms,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 user_delay_ms: + 23 .LFB96: + 24 .file 1 "./Src/voc_sensor.c" + 1:./Src/voc_sensor.c **** // + 2:./Src/voc_sensor.c **** // Created by MightyPork on 2017/11/17. + 3:./Src/voc_sensor.c **** // + 4:./Src/voc_sensor.c **** + 5:./Src/voc_sensor.c **** #include + 6:./Src/voc_sensor.c **** #include + 7:./Src/voc_sensor.c **** #include "voc_sensor.h" + 8:./Src/voc_sensor.c **** + 9:./Src/voc_sensor.c **** struct bme680_dev gas_sensor; + 10:./Src/voc_sensor.c **** + 11:./Src/voc_sensor.c **** static void user_delay_ms(uint32_t period) + 12:./Src/voc_sensor.c **** { + 25 .loc 1 12 0 + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 0 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 .LVL0: + 30 0000 10B5 push {r4, lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 4, -8 + 34 .cfi_offset 14, -4 + 13:./Src/voc_sensor.c **** /* + 14:./Src/voc_sensor.c **** * Return control or wait, + 15:./Src/voc_sensor.c **** * for a period amount of milliseconds + 16:./Src/voc_sensor.c **** */ + 17:./Src/voc_sensor.c **** HAL_Delay(period); + 35 .loc 1 17 0 + 36 0002 FFF7FEFF bl HAL_Delay + 37 .LVL1: + 18:./Src/voc_sensor.c **** } + 38 .loc 1 18 0 + 39 @ sp needed + 40 0006 10BD pop {r4, pc} + ARM GAS /tmp/ccnIeFZt.s page 2 + + + 41 .cfi_endproc + 42 .LFE96: + 44 .section .text.user_i2c_write,"ax",%progbits + 45 .align 1 + 46 .syntax unified + 47 .code 16 + 48 .thumb_func + 49 .fpu softvfp + 51 user_i2c_write: + 52 .LFB98: + 19:./Src/voc_sensor.c **** + 20:./Src/voc_sensor.c **** #if 0 + 21:./Src/voc_sensor.c **** static int8_t user_spi_read(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) + 22:./Src/voc_sensor.c **** { + 23:./Src/voc_sensor.c **** int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + 24:./Src/voc_sensor.c **** + 25:./Src/voc_sensor.c **** /* + 26:./Src/voc_sensor.c **** * The parameter dev_id can be used as a variable to select which Chip Select pin has + 27:./Src/voc_sensor.c **** * to be set low to activate the relevant device on the SPI bus + 28:./Src/voc_sensor.c **** */ + 29:./Src/voc_sensor.c **** + 30:./Src/voc_sensor.c **** /* + 31:./Src/voc_sensor.c **** * Data on the bus should be like + 32:./Src/voc_sensor.c **** * |----------------+---------------------+-------------| + 33:./Src/voc_sensor.c **** * | MOSI | MISO | Chip Select | + 34:./Src/voc_sensor.c **** * |----------------+---------------------|-------------| + 35:./Src/voc_sensor.c **** * | (don't care) | (don't care) | HIGH | + 36:./Src/voc_sensor.c **** * | (reg_addr) | (don't care) | LOW | + 37:./Src/voc_sensor.c **** * | (don't care) | (reg_data[0]) | LOW | + 38:./Src/voc_sensor.c **** * | (....) | (....) | LOW | + 39:./Src/voc_sensor.c **** * | (don't care) | (reg_data[len - 1]) | LOW | + 40:./Src/voc_sensor.c **** * | (don't care) | (don't care) | HIGH | + 41:./Src/voc_sensor.c **** * |----------------+---------------------|-------------| + 42:./Src/voc_sensor.c **** */ + 43:./Src/voc_sensor.c **** + 44:./Src/voc_sensor.c **** return rslt; + 45:./Src/voc_sensor.c **** } + 46:./Src/voc_sensor.c **** + 47:./Src/voc_sensor.c **** static int8_t user_spi_write(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) + 48:./Src/voc_sensor.c **** { + 49:./Src/voc_sensor.c **** int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + 50:./Src/voc_sensor.c **** + 51:./Src/voc_sensor.c **** /* + 52:./Src/voc_sensor.c **** * The parameter dev_id can be used as a variable to select which Chip Select pin has + 53:./Src/voc_sensor.c **** * to be set low to activate the relevant device on the SPI bus + 54:./Src/voc_sensor.c **** */ + 55:./Src/voc_sensor.c **** + 56:./Src/voc_sensor.c **** /* + 57:./Src/voc_sensor.c **** * Data on the bus should be like + 58:./Src/voc_sensor.c **** * |---------------------+--------------+-------------| + 59:./Src/voc_sensor.c **** * | MOSI | MISO | Chip Select | + 60:./Src/voc_sensor.c **** * |---------------------+--------------|-------------| + 61:./Src/voc_sensor.c **** * | (don't care) | (don't care) | HIGH | + 62:./Src/voc_sensor.c **** * | (reg_addr) | (don't care) | LOW | + 63:./Src/voc_sensor.c **** * | (reg_data[0]) | (don't care) | LOW | + 64:./Src/voc_sensor.c **** * | (....) | (....) | LOW | + 65:./Src/voc_sensor.c **** * | (reg_data[len - 1]) | (don't care) | LOW | + ARM GAS /tmp/ccnIeFZt.s page 3 + + + 66:./Src/voc_sensor.c **** * | (don't care) | (don't care) | HIGH | + 67:./Src/voc_sensor.c **** * |---------------------+--------------|-------------| + 68:./Src/voc_sensor.c **** */ + 69:./Src/voc_sensor.c **** + 70:./Src/voc_sensor.c **** return rslt; + 71:./Src/voc_sensor.c **** } + 72:./Src/voc_sensor.c **** #endif + 73:./Src/voc_sensor.c **** + 74:./Src/voc_sensor.c **** static int8_t user_i2c_read(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) + 75:./Src/voc_sensor.c **** { + 76:./Src/voc_sensor.c **** int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + 77:./Src/voc_sensor.c **** + 78:./Src/voc_sensor.c **** /* + 79:./Src/voc_sensor.c **** * The parameter dev_id can be used as a variable to store the I2C address of the device + 80:./Src/voc_sensor.c **** */ + 81:./Src/voc_sensor.c **** + 82:./Src/voc_sensor.c **** /* + 83:./Src/voc_sensor.c **** * Data on the bus should be like + 84:./Src/voc_sensor.c **** * |------------+---------------------| + 85:./Src/voc_sensor.c **** * | I2C action | Data | + 86:./Src/voc_sensor.c **** * |------------+---------------------| + 87:./Src/voc_sensor.c **** * | Start | - | + 88:./Src/voc_sensor.c **** * | Write | (reg_addr) | + 89:./Src/voc_sensor.c **** * | Stop | - | + 90:./Src/voc_sensor.c **** * | Start | - | + 91:./Src/voc_sensor.c **** * | Read | (reg_data[0]) | + 92:./Src/voc_sensor.c **** * | Read | (....) | + 93:./Src/voc_sensor.c **** * | Read | (reg_data[len - 1]) | + 94:./Src/voc_sensor.c **** * | Stop | - | + 95:./Src/voc_sensor.c **** * |------------+---------------------| + 96:./Src/voc_sensor.c **** */ + 97:./Src/voc_sensor.c **** HAL_I2C_Master_Transmit(&hi2c1, dev_id<<1, ®_addr, 1, 100); + 98:./Src/voc_sensor.c **** HAL_I2C_Master_Receive(&hi2c1, dev_id<<1, reg_data, len, 100); + 99:./Src/voc_sensor.c **** + 100:./Src/voc_sensor.c **** return rslt; + 101:./Src/voc_sensor.c **** } + 102:./Src/voc_sensor.c **** + 103:./Src/voc_sensor.c **** static int8_t user_i2c_write(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len) + 104:./Src/voc_sensor.c **** { + 53 .loc 1 104 0 + 54 .cfi_startproc + 55 @ args = 0, pretend = 0, frame = 64 + 56 @ frame_needed = 0, uses_anonymous_args = 0 + 57 .LVL2: + 58 0000 70B5 push {r4, r5, r6, lr} + 59 .LCFI1: + 60 .cfi_def_cfa_offset 16 + 61 .cfi_offset 4, -16 + 62 .cfi_offset 5, -12 + 63 .cfi_offset 6, -8 + 64 .cfi_offset 14, -4 + 65 0002 92B0 sub sp, sp, #72 + 66 .LCFI2: + 67 .cfi_def_cfa_offset 88 + 105:./Src/voc_sensor.c **** /* + 106:./Src/voc_sensor.c **** * The parameter dev_id can be used as a variable to store the I2C address of the device + 107:./Src/voc_sensor.c **** */ + ARM GAS /tmp/ccnIeFZt.s page 4 + + + 108:./Src/voc_sensor.c **** + 109:./Src/voc_sensor.c **** /* + 110:./Src/voc_sensor.c **** * Data on the bus should be like + 111:./Src/voc_sensor.c **** * |------------+---------------------| + 112:./Src/voc_sensor.c **** * | I2C action | Data | + 113:./Src/voc_sensor.c **** * |------------+---------------------| + 114:./Src/voc_sensor.c **** * | Start | - | + 115:./Src/voc_sensor.c **** * | Write | (reg_addr) | + 116:./Src/voc_sensor.c **** * | Write | (reg_data[0]) | + 117:./Src/voc_sensor.c **** * | Write | (....) | + 118:./Src/voc_sensor.c **** * | Write | (reg_data[len - 1]) | + 119:./Src/voc_sensor.c **** * | Stop | - | + 120:./Src/voc_sensor.c **** * |------------+---------------------| + 121:./Src/voc_sensor.c **** */ + 122:./Src/voc_sensor.c **** uint8_t data[64]; + 123:./Src/voc_sensor.c **** data[0] = reg_addr; + 68 .loc 1 123 0 + 69 0004 02AC add r4, sp, #8 + 70 0006 2170 strb r1, [r4] + 71 .LVL3: + 72 .LBB2: + 124:./Src/voc_sensor.c **** for (int i = 0; i < len; i++) { + 73 .loc 1 124 0 + 74 0008 0024 movs r4, #0 + 75 000a 04E0 b .L3 + 76 .LVL4: + 77 .L4: + 125:./Src/voc_sensor.c **** data[i+1] = reg_data[i]; + 78 .loc 1 125 0 discriminator 3 + 79 000c 1519 adds r5, r2, r4 + 80 000e 0134 adds r4, r4, #1 + 81 .LVL5: + 82 0010 2E78 ldrb r6, [r5] + 83 0012 02AD add r5, sp, #8 + 84 0014 2E55 strb r6, [r5, r4] + 85 .LVL6: + 86 .L3: + 124:./Src/voc_sensor.c **** for (int i = 0; i < len; i++) { + 87 .loc 1 124 0 discriminator 1 + 88 0016 A342 cmp r3, r4 + 89 0018 F8DC bgt .L4 + 90 .LBE2: + 126:./Src/voc_sensor.c **** } + 127:./Src/voc_sensor.c **** HAL_I2C_Master_Transmit(&hi2c1, dev_id<<1, &data[0], (uint16_t) (len + 1), 100); + 91 .loc 1 127 0 + 92 001a 0133 adds r3, r3, #1 + 93 .LVL7: + 94 001c 9BB2 uxth r3, r3 + 95 001e 4100 lsls r1, r0, #1 + 96 .LVL8: + 97 0020 6422 movs r2, #100 + 98 .LVL9: + 99 0022 0092 str r2, [sp] + 100 0024 02AA add r2, sp, #8 + 101 0026 0348 ldr r0, .L5 + 102 .LVL10: + 103 0028 FFF7FEFF bl HAL_I2C_Master_Transmit + ARM GAS /tmp/ccnIeFZt.s page 5 + + + 104 .LVL11: + 128:./Src/voc_sensor.c **** + 129:./Src/voc_sensor.c **** return BME680_OK; + 130:./Src/voc_sensor.c **** } + 105 .loc 1 130 0 + 106 002c 0020 movs r0, #0 + 107 002e 12B0 add sp, sp, #72 + 108 @ sp needed + 109 .LVL12: + 110 0030 70BD pop {r4, r5, r6, pc} + 111 .L6: + 112 0032 C046 .align 2 + 113 .L5: + 114 0034 00000000 .word hi2c1 + 115 .cfi_endproc + 116 .LFE98: + 118 .section .text.user_i2c_read,"ax",%progbits + 119 .align 1 + 120 .syntax unified + 121 .code 16 + 122 .thumb_func + 123 .fpu softvfp + 125 user_i2c_read: + 126 .LFB97: + 75:./Src/voc_sensor.c **** int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */ + 127 .loc 1 75 0 + 128 .cfi_startproc + 129 @ args = 0, pretend = 0, frame = 8 + 130 @ frame_needed = 0, uses_anonymous_args = 0 + 131 .LVL13: + 132 0000 F0B5 push {r4, r5, r6, r7, lr} + 133 .LCFI3: + 134 .cfi_def_cfa_offset 20 + 135 .cfi_offset 4, -20 + 136 .cfi_offset 5, -16 + 137 .cfi_offset 6, -12 + 138 .cfi_offset 7, -8 + 139 .cfi_offset 14, -4 + 140 0002 85B0 sub sp, sp, #20 + 141 .LCFI4: + 142 .cfi_def_cfa_offset 40 + 143 0004 0292 str r2, [sp, #8] + 144 0006 1F00 movs r7, r3 + 145 0008 0F23 movs r3, #15 + 146 .LVL14: + 147 000a 6B44 add r3, r3, sp + 148 000c 1A00 movs r2, r3 + 149 .LVL15: + 150 000e 1970 strb r1, [r3] + 151 .LVL16: + 97:./Src/voc_sensor.c **** HAL_I2C_Master_Receive(&hi2c1, dev_id<<1, reg_data, len, 100); + 152 .loc 1 97 0 + 153 0010 4400 lsls r4, r0, #1 + 154 0012 094D ldr r5, .L8 + 155 0014 6426 movs r6, #100 + 156 0016 0096 str r6, [sp] + 157 0018 0123 movs r3, #1 + ARM GAS /tmp/ccnIeFZt.s page 6 + + + 158 001a 2100 movs r1, r4 + 159 .LVL17: + 160 001c 2800 movs r0, r5 + 161 .LVL18: + 162 001e FFF7FEFF bl HAL_I2C_Master_Transmit + 163 .LVL19: + 98:./Src/voc_sensor.c **** + 164 .loc 1 98 0 + 165 0022 0096 str r6, [sp] + 166 0024 3B00 movs r3, r7 + 167 0026 029A ldr r2, [sp, #8] + 168 0028 2100 movs r1, r4 + 169 002a 2800 movs r0, r5 + 170 002c FFF7FEFF bl HAL_I2C_Master_Receive + 171 .LVL20: + 101:./Src/voc_sensor.c **** + 172 .loc 1 101 0 + 173 0030 0020 movs r0, #0 + 174 0032 05B0 add sp, sp, #20 + 175 @ sp needed + 176 0034 F0BD pop {r4, r5, r6, r7, pc} + 177 .L9: + 178 0036 C046 .align 2 + 179 .L8: + 180 0038 00000000 .word hi2c1 + 181 .cfi_endproc + 182 .LFE97: + 184 .section .text.voc_init,"ax",%progbits + 185 .align 1 + 186 .global voc_init + 187 .syntax unified + 188 .code 16 + 189 .thumb_func + 190 .fpu softvfp + 192 voc_init: + 193 .LFB99: + 131:./Src/voc_sensor.c **** + 132:./Src/voc_sensor.c **** + 133:./Src/voc_sensor.c **** void voc_init(void) + 134:./Src/voc_sensor.c **** { + 194 .loc 1 134 0 + 195 .cfi_startproc + 196 @ args = 0, pretend = 0, frame = 0 + 197 @ frame_needed = 0, uses_anonymous_args = 0 + 198 0000 70B5 push {r4, r5, r6, lr} + 199 .LCFI5: + 200 .cfi_def_cfa_offset 16 + 201 .cfi_offset 4, -16 + 202 .cfi_offset 5, -12 + 203 .cfi_offset 6, -8 + 204 .cfi_offset 14, -4 + 135:./Src/voc_sensor.c **** int8_t rslt; + 136:./Src/voc_sensor.c **** gas_sensor.dev_id = BME680_I2C_ADDR_PRIMARY; + 205 .loc 1 136 0 + 206 0002 174C ldr r4, .L11 + 207 0004 7623 movs r3, #118 + 208 0006 6370 strb r3, [r4, #1] + ARM GAS /tmp/ccnIeFZt.s page 7 + + + 137:./Src/voc_sensor.c **** gas_sensor.intf = BME680_I2C_INTF; + 209 .loc 1 137 0 + 210 0008 0125 movs r5, #1 + 211 000a A570 strb r5, [r4, #2] + 138:./Src/voc_sensor.c **** gas_sensor.read = user_i2c_read; + 212 .loc 1 138 0 + 213 000c 154B ldr r3, .L11+4 + 214 000e A364 str r3, [r4, #72] + 139:./Src/voc_sensor.c **** gas_sensor.write = user_i2c_write; + 215 .loc 1 139 0 + 216 0010 154B ldr r3, .L11+8 + 217 0012 E364 str r3, [r4, #76] + 140:./Src/voc_sensor.c **** gas_sensor.delay_ms = user_delay_ms; + 218 .loc 1 140 0 + 219 0014 154B ldr r3, .L11+12 + 220 0016 2365 str r3, [r4, #80] + 141:./Src/voc_sensor.c **** + 142:./Src/voc_sensor.c **** PRINTF("BME680 initializing...\r\n"); + 221 .loc 1 142 0 + 222 0018 1548 ldr r0, .L11+16 + 223 001a FFF7FEFF bl vcom_Send + 224 .LVL21: + 143:./Src/voc_sensor.c **** rslt = bme680_init(&gas_sensor); + 225 .loc 1 143 0 + 226 001e 2000 movs r0, r4 + 227 0020 FFF7FEFF bl bme680_init + 228 .LVL22: + 144:./Src/voc_sensor.c **** assert_param(rslt == BME680_OK); + 145:./Src/voc_sensor.c **** + 146:./Src/voc_sensor.c **** + 147:./Src/voc_sensor.c **** PRINTF("BME680 configuring...\r\n"); + 229 .loc 1 147 0 + 230 0024 1348 ldr r0, .L11+20 + 231 0026 FFF7FEFF bl vcom_Send + 232 .LVL23: + 148:./Src/voc_sensor.c **** /* Set the temperature, pressure and humidity settings */ + 149:./Src/voc_sensor.c **** gas_sensor.tph_sett.os_hum = BME680_OS_2X; + 233 .loc 1 149 0 + 234 002a 0223 movs r3, #2 + 235 002c 3822 movs r2, #56 + 236 002e A354 strb r3, [r4, r2] + 150:./Src/voc_sensor.c **** gas_sensor.tph_sett.os_pres = BME680_OS_4X; + 237 .loc 1 150 0 + 238 0030 0232 adds r2, r2, #2 + 239 0032 0321 movs r1, #3 + 240 0034 A154 strb r1, [r4, r2] + 151:./Src/voc_sensor.c **** gas_sensor.tph_sett.os_temp = BME680_OS_8X; + 241 .loc 1 151 0 + 242 0036 013A subs r2, r2, #1 + 243 0038 0131 adds r1, r1, #1 + 244 003a A154 strb r1, [r4, r2] + 152:./Src/voc_sensor.c **** gas_sensor.tph_sett.filter = BME680_FILTER_SIZE_3; + 245 .loc 1 152 0 + 246 003c 0232 adds r2, r2, #2 + 247 003e A354 strb r3, [r4, r2] + 153:./Src/voc_sensor.c **** + 154:./Src/voc_sensor.c **** /* Set the remaining gas sensor settings and link the heating profile */ + ARM GAS /tmp/ccnIeFZt.s page 8 + + + 155:./Src/voc_sensor.c **** gas_sensor.gas_sett.run_gas = BME680_ENABLE_GAS_MEAS; + 248 .loc 1 155 0 + 249 0040 3C33 adds r3, r3, #60 + 250 0042 E554 strb r5, [r4, r3] + 156:./Src/voc_sensor.c **** /* Create a ramp heat waveform in 3 steps */ + 157:./Src/voc_sensor.c **** gas_sensor.gas_sett.heatr_temp = 320; /* degree Celsius */ + 251 .loc 1 157 0 + 252 0044 0233 adds r3, r3, #2 + 253 0046 0632 adds r2, r2, #6 + 254 0048 FF32 adds r2, r2, #255 + 255 004a E252 strh r2, [r4, r3] + 158:./Src/voc_sensor.c **** gas_sensor.gas_sett.heatr_dur = 150; /* milliseconds */ + 256 .loc 1 158 0 + 257 004c 0233 adds r3, r3, #2 + 258 004e AA3A subs r2, r2, #170 + 259 0050 E252 strh r2, [r4, r3] + 159:./Src/voc_sensor.c **** + 160:./Src/voc_sensor.c **** /* Select the power mode */ + 161:./Src/voc_sensor.c **** /* Must be set before writing the sensor configuration */ + 162:./Src/voc_sensor.c **** gas_sensor.power_mode = BME680_FORCED_MODE; + 260 .loc 1 162 0 + 261 0052 0233 adds r3, r3, #2 + 262 0054 E554 strb r5, [r4, r3] + 263 .LVL24: + 163:./Src/voc_sensor.c **** + 164:./Src/voc_sensor.c **** /* Set the required sensor settings needed */ + 165:./Src/voc_sensor.c **** uint8_t set_required_settings = BME680_OST_SEL | BME680_OSP_SEL | BME680_OSH_SEL | BME680_FILTER_S + 166:./Src/voc_sensor.c **** + 167:./Src/voc_sensor.c **** /* Set the desired sensor configuration */ + 168:./Src/voc_sensor.c **** rslt = bme680_set_sensor_settings(set_required_settings,&gas_sensor); + 264 .loc 1 168 0 + 265 0056 2100 movs r1, r4 + 266 0058 DF20 movs r0, #223 + 267 005a FFF7FEFF bl bme680_set_sensor_settings + 268 .LVL25: + 169:./Src/voc_sensor.c **** assert_param(rslt == BME680_OK); + 170:./Src/voc_sensor.c **** } + 269 .loc 1 170 0 + 270 @ sp needed + 271 005e 70BD pop {r4, r5, r6, pc} + 272 .L12: + 273 .align 2 + 274 .L11: + 275 0060 00000000 .word .LANCHOR0 + 276 0064 00000000 .word user_i2c_read + 277 0068 00000000 .word user_i2c_write + 278 006c 00000000 .word user_delay_ms + 279 0070 00000000 .word .LC6 + 280 0074 1C000000 .word .LC8 + 281 .cfi_endproc + 282 .LFE99: + 284 .global __aeabi_i2f + 285 .global __aeabi_fdiv + 286 .global __aeabi_ui2f + 287 .global __aeabi_f2d + 288 .section .text.voc_measure,"ax",%progbits + 289 .align 1 + ARM GAS /tmp/ccnIeFZt.s page 9 + + + 290 .global voc_measure + 291 .syntax unified + 292 .code 16 + 293 .thumb_func + 294 .fpu softvfp + 296 voc_measure: + 297 .LFB100: + 171:./Src/voc_sensor.c **** + 172:./Src/voc_sensor.c **** void voc_measure(void) + 173:./Src/voc_sensor.c **** { + 298 .loc 1 173 0 + 299 .cfi_startproc + 300 @ args = 0, pretend = 0, frame = 32 + 301 @ frame_needed = 0, uses_anonymous_args = 0 + 302 0000 F0B5 push {r4, r5, r6, r7, lr} + 303 .LCFI6: + 304 .cfi_def_cfa_offset 20 + 305 .cfi_offset 4, -20 + 306 .cfi_offset 5, -16 + 307 .cfi_offset 6, -12 + 308 .cfi_offset 7, -8 + 309 .cfi_offset 14, -4 + 310 0002 8DB0 sub sp, sp, #52 + 311 .LCFI7: + 312 .cfi_def_cfa_offset 72 + 174:./Src/voc_sensor.c **** /* Set the power mode */ + 175:./Src/voc_sensor.c **** int8_t rslt; + 176:./Src/voc_sensor.c **** + 177:./Src/voc_sensor.c **** rslt = bme680_set_sensor_mode(&gas_sensor); + 313 .loc 1 177 0 + 314 0004 254D ldr r5, .L16 + 315 0006 2800 movs r0, r5 + 316 0008 FFF7FEFF bl bme680_set_sensor_mode + 317 .LVL26: + 178:./Src/voc_sensor.c **** assert_param(rslt == BME680_OK); + 179:./Src/voc_sensor.c **** + 180:./Src/voc_sensor.c **** /* Get the total measurement duration so as to sleep or wait till the + 181:./Src/voc_sensor.c **** * measurement is complete */ + 182:./Src/voc_sensor.c **** uint16_t meas_period; + 183:./Src/voc_sensor.c **** bme680_get_profile_dur(&meas_period, &gas_sensor); + 318 .loc 1 183 0 + 319 000c 2624 movs r4, #38 + 320 000e 02AB add r3, sp, #8 + 321 0010 9C46 mov ip, r3 + 322 0012 6444 add r4, r4, ip + 323 0014 2900 movs r1, r5 + 324 0016 2000 movs r0, r4 + 325 0018 FFF7FEFF bl bme680_get_profile_dur + 326 .LVL27: + 184:./Src/voc_sensor.c **** HAL_Delay(meas_period); /* Delay till the measurement is ready */ + 327 .loc 1 184 0 + 328 001c 2088 ldrh r0, [r4] + 329 001e FFF7FEFF bl HAL_Delay + 330 .LVL28: + 185:./Src/voc_sensor.c **** struct bme680_field_data data; + 186:./Src/voc_sensor.c **** + 187:./Src/voc_sensor.c **** rslt = bme680_get_sensor_data(&data, &gas_sensor); + ARM GAS /tmp/ccnIeFZt.s page 10 + + + 331 .loc 1 187 0 + 332 0022 06AC add r4, sp, #24 + 333 0024 2900 movs r1, r5 + 334 0026 2000 movs r0, r4 + 335 0028 FFF7FEFF bl bme680_get_sensor_data + 336 .LVL29: + 188:./Src/voc_sensor.c **** assert_param(rslt == BME680_OK); + 189:./Src/voc_sensor.c **** + 190:./Src/voc_sensor.c **** PRINTF("T: %.2f degC, P: %.2f hPa, H %.2f %%rH ", data.temperature / 100.0f, + 337 .loc 1 190 0 + 338 002c 0423 movs r3, #4 + 339 002e E05E ldrsh r0, [r4, r3] + 340 0030 FFF7FEFF bl __aeabi_i2f + 341 .LVL30: + 342 0034 1A49 ldr r1, .L16+4 + 343 0036 FFF7FEFF bl __aeabi_fdiv + 344 .LVL31: + 345 003a 071C adds r7, r0, #0 + 346 003c A068 ldr r0, [r4, #8] + 347 003e FFF7FEFF bl __aeabi_ui2f + 348 .LVL32: + 349 0042 1749 ldr r1, .L16+4 + 350 0044 FFF7FEFF bl __aeabi_fdiv + 351 .LVL33: + 352 0048 051C adds r5, r0, #0 + 353 004a E068 ldr r0, [r4, #12] + 354 004c FFF7FEFF bl __aeabi_ui2f + 355 .LVL34: + 356 0050 1449 ldr r1, .L16+8 + 357 0052 FFF7FEFF bl __aeabi_fdiv + 358 .LVL35: + 359 0056 061C adds r6, r0, #0 + 360 0058 381C adds r0, r7, #0 + 361 005a FFF7FEFF bl __aeabi_f2d + 362 .LVL36: + 363 005e 0490 str r0, [sp, #16] + 364 0060 0591 str r1, [sp, #20] + 365 0062 301C adds r0, r6, #0 + 366 0064 FFF7FEFF bl __aeabi_f2d + 367 .LVL37: + 368 0068 0290 str r0, [sp, #8] + 369 006a 0391 str r1, [sp, #12] + 370 006c 281C adds r0, r5, #0 + 371 006e FFF7FEFF bl __aeabi_f2d + 372 .LVL38: + 373 0072 0090 str r0, [sp] + 374 0074 0191 str r1, [sp, #4] + 375 0076 049A ldr r2, [sp, #16] + 376 0078 059B ldr r3, [sp, #20] + 377 007a 0B48 ldr r0, .L16+12 + 378 007c FFF7FEFF bl vcom_Send + 379 .LVL39: + 191:./Src/voc_sensor.c **** data.pressure / 100.0f, data.humidity / 1000.0f ); + 192:./Src/voc_sensor.c **** /* Avoid using measurements from an unstable heating setup */ + 193:./Src/voc_sensor.c **** if(data.status & BME680_GASM_VALID_MSK) + 380 .loc 1 193 0 + 381 0080 2378 ldrb r3, [r4] + ARM GAS /tmp/ccnIeFZt.s page 11 + + + 382 0082 9B06 lsls r3, r3, #26 + 383 0084 04D4 bmi .L15 + 384 .L14: + 194:./Src/voc_sensor.c **** PRINTF(", G: %d ohms", data.gas_resistance); + 195:./Src/voc_sensor.c **** + 196:./Src/voc_sensor.c **** PRINTF("\r\n"); + 385 .loc 1 196 0 + 386 0086 0948 ldr r0, .L16+16 + 387 0088 FFF7FEFF bl vcom_Send + 388 .LVL40: + 197:./Src/voc_sensor.c **** } + 389 .loc 1 197 0 + 390 008c 0DB0 add sp, sp, #52 + 391 @ sp needed + 392 008e F0BD pop {r4, r5, r6, r7, pc} + 393 .L15: + 194:./Src/voc_sensor.c **** PRINTF(", G: %d ohms", data.gas_resistance); + 394 .loc 1 194 0 + 395 0090 0A99 ldr r1, [sp, #40] + 396 0092 0748 ldr r0, .L16+20 + 397 0094 FFF7FEFF bl vcom_Send + 398 .LVL41: + 399 0098 F5E7 b .L14 + 400 .L17: + 401 009a C046 .align 2 + 402 .L16: + 403 009c 00000000 .word .LANCHOR0 + 404 00a0 0000C842 .word 1120403456 + 405 00a4 00007A44 .word 1148846080 + 406 00a8 00000000 .word .LC11 + 407 00ac 38000000 .word .LC15 + 408 00b0 28000000 .word .LC13 + 409 .cfi_endproc + 410 .LFE100: + 412 .global gas_sensor + 413 .section .bss.gas_sensor,"aw",%nobits + 414 .align 2 + 415 .set .LANCHOR0,. + 0 + 418 gas_sensor: + 419 0000 00000000 .space 88 + 419 00000000 + 419 00000000 + 419 00000000 + 419 00000000 + 420 .section .rodata.voc_init.str1.4,"aMS",%progbits,1 + 421 .align 2 + 422 .LC6: + 423 0000 424D4536 .ascii "BME680 initializing...\015\012\000" + 423 38302069 + 423 6E697469 + 423 616C697A + 423 696E672E + 424 0019 000000 .space 3 + 425 .LC8: + 426 001c 424D4536 .ascii "BME680 configuring...\015\012\000" + 426 38302063 + 426 6F6E6669 + ARM GAS /tmp/ccnIeFZt.s page 12 + + + 426 67757269 + 426 6E672E2E + 427 .section .rodata.voc_measure.str1.4,"aMS",%progbits,1 + 428 .align 2 + 429 .LC11: + 430 0000 543A2025 .ascii "T: %.2f degC, P: %.2f hPa, H %.2f %%rH \000" + 430 2E326620 + 430 64656743 + 430 2C20503A + 430 20252E32 + 431 .LC13: + 432 0028 2C20473A .ascii ", G: %d ohms\000" + 432 20256420 + 432 6F686D73 + 432 00 + 433 0035 000000 .space 3 + 434 .LC15: + 435 0038 0D0A00 .ascii "\015\012\000" + 436 .text + 437 .Letext0: + 438 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 439 .file 3 "/usr/arm-none-eabi/include/sys/lock.h" + 440 .file 4 "/usr/arm-none-eabi/include/sys/_types.h" + 441 .file 5 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h" + 442 .file 6 "/usr/arm-none-eabi/include/sys/reent.h" + 443 .file 7 "/usr/arm-none-eabi/include/math.h" + 444 .file 8 "/usr/arm-none-eabi/include/sys/_stdint.h" + 445 .file 9 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + 446 .file 10 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h" + 447 .file 11 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h" + 448 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h" + 449 .file 13 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h" + 450 .file 14 "Inc/hw_i2c.h" + 451 .file 15 "./Src/../Drivers/BME680/bme680_defs.h" + 452 .file 16 "./Src/voc_sensor.h" + 453 .file 17 "./Src/../Drivers/BME680/bme680.h" + 454 .file 18 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h" + 455 .file 19 "Inc/vcom.h" + ARM GAS /tmp/ccnIeFZt.s page 13 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 voc_sensor.c + /tmp/ccnIeFZt.s:16 .text.user_delay_ms:0000000000000000 $t + /tmp/ccnIeFZt.s:22 .text.user_delay_ms:0000000000000000 user_delay_ms + /tmp/ccnIeFZt.s:45 .text.user_i2c_write:0000000000000000 $t + /tmp/ccnIeFZt.s:51 .text.user_i2c_write:0000000000000000 user_i2c_write + /tmp/ccnIeFZt.s:114 .text.user_i2c_write:0000000000000034 $d + /tmp/ccnIeFZt.s:119 .text.user_i2c_read:0000000000000000 $t + /tmp/ccnIeFZt.s:125 .text.user_i2c_read:0000000000000000 user_i2c_read + /tmp/ccnIeFZt.s:180 .text.user_i2c_read:0000000000000038 $d + /tmp/ccnIeFZt.s:185 .text.voc_init:0000000000000000 $t + /tmp/ccnIeFZt.s:192 .text.voc_init:0000000000000000 voc_init + /tmp/ccnIeFZt.s:275 .text.voc_init:0000000000000060 $d + /tmp/ccnIeFZt.s:289 .text.voc_measure:0000000000000000 $t + /tmp/ccnIeFZt.s:296 .text.voc_measure:0000000000000000 voc_measure + /tmp/ccnIeFZt.s:403 .text.voc_measure:000000000000009c $d + /tmp/ccnIeFZt.s:418 .bss.gas_sensor:0000000000000000 gas_sensor + /tmp/ccnIeFZt.s:414 .bss.gas_sensor:0000000000000000 $d + /tmp/ccnIeFZt.s:421 .rodata.voc_init.str1.4:0000000000000000 $d + /tmp/ccnIeFZt.s:428 .rodata.voc_measure.str1.4:0000000000000000 $d + .debug_frame:0000000000000010 $d + +UNDEFINED SYMBOLS +HAL_Delay +HAL_I2C_Master_Transmit +hi2c1 +HAL_I2C_Master_Receive +vcom_Send +bme680_init +bme680_set_sensor_settings +__aeabi_i2f +__aeabi_fdiv +__aeabi_ui2f +__aeabi_f2d +bme680_set_sensor_mode +bme680_get_profile_dur +bme680_get_sensor_data